1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file This file implements the LegalizerHelper class to legalize 10 /// individual instructions and the LegalizeMachineIR wrapper pass for the 11 /// primary legalization. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 16 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 19 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/CodeGen/TargetFrameLowering.h" 22 #include "llvm/CodeGen/TargetInstrInfo.h" 23 #include "llvm/CodeGen/TargetLowering.h" 24 #include "llvm/CodeGen/TargetSubtargetInfo.h" 25 #include "llvm/Support/Debug.h" 26 #include "llvm/Support/MathExtras.h" 27 #include "llvm/Support/raw_ostream.h" 28 29 #define DEBUG_TYPE "legalizer" 30 31 using namespace llvm; 32 using namespace LegalizeActions; 33 using namespace MIPatternMatch; 34 35 /// Try to break down \p OrigTy into \p NarrowTy sized pieces. 36 /// 37 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy, 38 /// with any leftover piece as type \p LeftoverTy 39 /// 40 /// Returns -1 in the first element of the pair if the breakdown is not 41 /// satisfiable. 42 static std::pair<int, int> 43 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) { 44 assert(!LeftoverTy.isValid() && "this is an out argument"); 45 46 unsigned Size = OrigTy.getSizeInBits(); 47 unsigned NarrowSize = NarrowTy.getSizeInBits(); 48 unsigned NumParts = Size / NarrowSize; 49 unsigned LeftoverSize = Size - NumParts * NarrowSize; 50 assert(Size > NarrowSize); 51 52 if (LeftoverSize == 0) 53 return {NumParts, 0}; 54 55 if (NarrowTy.isVector()) { 56 unsigned EltSize = OrigTy.getScalarSizeInBits(); 57 if (LeftoverSize % EltSize != 0) 58 return {-1, -1}; 59 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); 60 } else { 61 LeftoverTy = LLT::scalar(LeftoverSize); 62 } 63 64 int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits(); 65 return std::make_pair(NumParts, NumLeftover); 66 } 67 68 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) { 69 70 if (!Ty.isScalar()) 71 return nullptr; 72 73 switch (Ty.getSizeInBits()) { 74 case 16: 75 return Type::getHalfTy(Ctx); 76 case 32: 77 return Type::getFloatTy(Ctx); 78 case 64: 79 return Type::getDoubleTy(Ctx); 80 case 80: 81 return Type::getX86_FP80Ty(Ctx); 82 case 128: 83 return Type::getFP128Ty(Ctx); 84 default: 85 return nullptr; 86 } 87 } 88 89 LegalizerHelper::LegalizerHelper(MachineFunction &MF, 90 GISelChangeObserver &Observer, 91 MachineIRBuilder &Builder) 92 : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()), 93 LI(*MF.getSubtarget().getLegalizerInfo()), 94 TLI(*MF.getSubtarget().getTargetLowering()) { } 95 96 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI, 97 GISelChangeObserver &Observer, 98 MachineIRBuilder &B) 99 : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI), 100 TLI(*MF.getSubtarget().getTargetLowering()) { } 101 102 LegalizerHelper::LegalizeResult 103 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) { 104 LLVM_DEBUG(dbgs() << "Legalizing: " << MI); 105 106 MIRBuilder.setInstrAndDebugLoc(MI); 107 108 if (MI.getOpcode() == TargetOpcode::G_INTRINSIC || 109 MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS) 110 return LI.legalizeIntrinsic(*this, MI) ? Legalized : UnableToLegalize; 111 auto Step = LI.getAction(MI, MRI); 112 switch (Step.Action) { 113 case Legal: 114 LLVM_DEBUG(dbgs() << ".. Already legal\n"); 115 return AlreadyLegal; 116 case Libcall: 117 LLVM_DEBUG(dbgs() << ".. Convert to libcall\n"); 118 return libcall(MI); 119 case NarrowScalar: 120 LLVM_DEBUG(dbgs() << ".. Narrow scalar\n"); 121 return narrowScalar(MI, Step.TypeIdx, Step.NewType); 122 case WidenScalar: 123 LLVM_DEBUG(dbgs() << ".. Widen scalar\n"); 124 return widenScalar(MI, Step.TypeIdx, Step.NewType); 125 case Bitcast: 126 LLVM_DEBUG(dbgs() << ".. Bitcast type\n"); 127 return bitcast(MI, Step.TypeIdx, Step.NewType); 128 case Lower: 129 LLVM_DEBUG(dbgs() << ".. Lower\n"); 130 return lower(MI, Step.TypeIdx, Step.NewType); 131 case FewerElements: 132 LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n"); 133 return fewerElementsVector(MI, Step.TypeIdx, Step.NewType); 134 case MoreElements: 135 LLVM_DEBUG(dbgs() << ".. Increase number of elements\n"); 136 return moreElementsVector(MI, Step.TypeIdx, Step.NewType); 137 case Custom: 138 LLVM_DEBUG(dbgs() << ".. Custom legalization\n"); 139 return LI.legalizeCustom(*this, MI) ? Legalized : UnableToLegalize; 140 default: 141 LLVM_DEBUG(dbgs() << ".. Unable to legalize\n"); 142 return UnableToLegalize; 143 } 144 } 145 146 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts, 147 SmallVectorImpl<Register> &VRegs) { 148 for (int i = 0; i < NumParts; ++i) 149 VRegs.push_back(MRI.createGenericVirtualRegister(Ty)); 150 MIRBuilder.buildUnmerge(VRegs, Reg); 151 } 152 153 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, 154 LLT MainTy, LLT &LeftoverTy, 155 SmallVectorImpl<Register> &VRegs, 156 SmallVectorImpl<Register> &LeftoverRegs) { 157 assert(!LeftoverTy.isValid() && "this is an out argument"); 158 159 unsigned RegSize = RegTy.getSizeInBits(); 160 unsigned MainSize = MainTy.getSizeInBits(); 161 unsigned NumParts = RegSize / MainSize; 162 unsigned LeftoverSize = RegSize - NumParts * MainSize; 163 164 // Use an unmerge when possible. 165 if (LeftoverSize == 0) { 166 for (unsigned I = 0; I < NumParts; ++I) 167 VRegs.push_back(MRI.createGenericVirtualRegister(MainTy)); 168 MIRBuilder.buildUnmerge(VRegs, Reg); 169 return true; 170 } 171 172 if (MainTy.isVector()) { 173 unsigned EltSize = MainTy.getScalarSizeInBits(); 174 if (LeftoverSize % EltSize != 0) 175 return false; 176 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); 177 } else { 178 LeftoverTy = LLT::scalar(LeftoverSize); 179 } 180 181 // For irregular sizes, extract the individual parts. 182 for (unsigned I = 0; I != NumParts; ++I) { 183 Register NewReg = MRI.createGenericVirtualRegister(MainTy); 184 VRegs.push_back(NewReg); 185 MIRBuilder.buildExtract(NewReg, Reg, MainSize * I); 186 } 187 188 for (unsigned Offset = MainSize * NumParts; Offset < RegSize; 189 Offset += LeftoverSize) { 190 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy); 191 LeftoverRegs.push_back(NewReg); 192 MIRBuilder.buildExtract(NewReg, Reg, Offset); 193 } 194 195 return true; 196 } 197 198 void LegalizerHelper::insertParts(Register DstReg, 199 LLT ResultTy, LLT PartTy, 200 ArrayRef<Register> PartRegs, 201 LLT LeftoverTy, 202 ArrayRef<Register> LeftoverRegs) { 203 if (!LeftoverTy.isValid()) { 204 assert(LeftoverRegs.empty()); 205 206 if (!ResultTy.isVector()) { 207 MIRBuilder.buildMerge(DstReg, PartRegs); 208 return; 209 } 210 211 if (PartTy.isVector()) 212 MIRBuilder.buildConcatVectors(DstReg, PartRegs); 213 else 214 MIRBuilder.buildBuildVector(DstReg, PartRegs); 215 return; 216 } 217 218 unsigned PartSize = PartTy.getSizeInBits(); 219 unsigned LeftoverPartSize = LeftoverTy.getSizeInBits(); 220 221 Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy); 222 MIRBuilder.buildUndef(CurResultReg); 223 224 unsigned Offset = 0; 225 for (Register PartReg : PartRegs) { 226 Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy); 227 MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset); 228 CurResultReg = NewResultReg; 229 Offset += PartSize; 230 } 231 232 for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) { 233 // Use the original output register for the final insert to avoid a copy. 234 Register NewResultReg = (I + 1 == E) ? 235 DstReg : MRI.createGenericVirtualRegister(ResultTy); 236 237 MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset); 238 CurResultReg = NewResultReg; 239 Offset += LeftoverPartSize; 240 } 241 } 242 243 /// Append the result registers of G_UNMERGE_VALUES \p MI to \p Regs. 244 static void getUnmergeResults(SmallVectorImpl<Register> &Regs, 245 const MachineInstr &MI) { 246 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES); 247 248 const int StartIdx = Regs.size(); 249 const int NumResults = MI.getNumOperands() - 1; 250 Regs.resize(Regs.size() + NumResults); 251 for (int I = 0; I != NumResults; ++I) 252 Regs[StartIdx + I] = MI.getOperand(I).getReg(); 253 } 254 255 void LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, 256 LLT GCDTy, Register SrcReg) { 257 LLT SrcTy = MRI.getType(SrcReg); 258 if (SrcTy == GCDTy) { 259 // If the source already evenly divides the result type, we don't need to do 260 // anything. 261 Parts.push_back(SrcReg); 262 } else { 263 // Need to split into common type sized pieces. 264 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 265 getUnmergeResults(Parts, *Unmerge); 266 } 267 } 268 269 LLT LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy, 270 LLT NarrowTy, Register SrcReg) { 271 LLT SrcTy = MRI.getType(SrcReg); 272 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 273 extractGCDType(Parts, GCDTy, SrcReg); 274 return GCDTy; 275 } 276 277 LLT LegalizerHelper::buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy, 278 SmallVectorImpl<Register> &VRegs, 279 unsigned PadStrategy) { 280 LLT LCMTy = getLCMType(DstTy, NarrowTy); 281 282 int NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 283 int NumSubParts = NarrowTy.getSizeInBits() / GCDTy.getSizeInBits(); 284 int NumOrigSrc = VRegs.size(); 285 286 Register PadReg; 287 288 // Get a value we can use to pad the source value if the sources won't evenly 289 // cover the result type. 290 if (NumOrigSrc < NumParts * NumSubParts) { 291 if (PadStrategy == TargetOpcode::G_ZEXT) 292 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); 293 else if (PadStrategy == TargetOpcode::G_ANYEXT) 294 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 295 else { 296 assert(PadStrategy == TargetOpcode::G_SEXT); 297 298 // Shift the sign bit of the low register through the high register. 299 auto ShiftAmt = 300 MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1); 301 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0); 302 } 303 } 304 305 // Registers for the final merge to be produced. 306 SmallVector<Register, 4> Remerge(NumParts); 307 308 // Registers needed for intermediate merges, which will be merged into a 309 // source for Remerge. 310 SmallVector<Register, 4> SubMerge(NumSubParts); 311 312 // Once we've fully read off the end of the original source bits, we can reuse 313 // the same high bits for remaining padding elements. 314 Register AllPadReg; 315 316 // Build merges to the LCM type to cover the original result type. 317 for (int I = 0; I != NumParts; ++I) { 318 bool AllMergePartsArePadding = true; 319 320 // Build the requested merges to the requested type. 321 for (int J = 0; J != NumSubParts; ++J) { 322 int Idx = I * NumSubParts + J; 323 if (Idx >= NumOrigSrc) { 324 SubMerge[J] = PadReg; 325 continue; 326 } 327 328 SubMerge[J] = VRegs[Idx]; 329 330 // There are meaningful bits here we can't reuse later. 331 AllMergePartsArePadding = false; 332 } 333 334 // If we've filled up a complete piece with padding bits, we can directly 335 // emit the natural sized constant if applicable, rather than a merge of 336 // smaller constants. 337 if (AllMergePartsArePadding && !AllPadReg) { 338 if (PadStrategy == TargetOpcode::G_ANYEXT) 339 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); 340 else if (PadStrategy == TargetOpcode::G_ZEXT) 341 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); 342 343 // If this is a sign extension, we can't materialize a trivial constant 344 // with the right type and have to produce a merge. 345 } 346 347 if (AllPadReg) { 348 // Avoid creating additional instructions if we're just adding additional 349 // copies of padding bits. 350 Remerge[I] = AllPadReg; 351 continue; 352 } 353 354 if (NumSubParts == 1) 355 Remerge[I] = SubMerge[0]; 356 else 357 Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0); 358 359 // In the sign extend padding case, re-use the first all-signbit merge. 360 if (AllMergePartsArePadding && !AllPadReg) 361 AllPadReg = Remerge[I]; 362 } 363 364 VRegs = std::move(Remerge); 365 return LCMTy; 366 } 367 368 void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy, 369 ArrayRef<Register> RemergeRegs) { 370 LLT DstTy = MRI.getType(DstReg); 371 372 // Create the merge to the widened source, and extract the relevant bits into 373 // the result. 374 375 if (DstTy == LCMTy) { 376 MIRBuilder.buildMerge(DstReg, RemergeRegs); 377 return; 378 } 379 380 auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs); 381 if (DstTy.isScalar() && LCMTy.isScalar()) { 382 MIRBuilder.buildTrunc(DstReg, Remerge); 383 return; 384 } 385 386 if (LCMTy.isVector()) { 387 unsigned NumDefs = LCMTy.getSizeInBits() / DstTy.getSizeInBits(); 388 SmallVector<Register, 8> UnmergeDefs(NumDefs); 389 UnmergeDefs[0] = DstReg; 390 for (unsigned I = 1; I != NumDefs; ++I) 391 UnmergeDefs[I] = MRI.createGenericVirtualRegister(DstTy); 392 393 MIRBuilder.buildUnmerge(UnmergeDefs, 394 MIRBuilder.buildMerge(LCMTy, RemergeRegs)); 395 return; 396 } 397 398 llvm_unreachable("unhandled case"); 399 } 400 401 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) { 402 #define RTLIBCASE_INT(LibcallPrefix) \ 403 do { \ 404 switch (Size) { \ 405 case 32: \ 406 return RTLIB::LibcallPrefix##32; \ 407 case 64: \ 408 return RTLIB::LibcallPrefix##64; \ 409 case 128: \ 410 return RTLIB::LibcallPrefix##128; \ 411 default: \ 412 llvm_unreachable("unexpected size"); \ 413 } \ 414 } while (0) 415 416 #define RTLIBCASE(LibcallPrefix) \ 417 do { \ 418 switch (Size) { \ 419 case 32: \ 420 return RTLIB::LibcallPrefix##32; \ 421 case 64: \ 422 return RTLIB::LibcallPrefix##64; \ 423 case 80: \ 424 return RTLIB::LibcallPrefix##80; \ 425 case 128: \ 426 return RTLIB::LibcallPrefix##128; \ 427 default: \ 428 llvm_unreachable("unexpected size"); \ 429 } \ 430 } while (0) 431 432 switch (Opcode) { 433 case TargetOpcode::G_SDIV: 434 RTLIBCASE_INT(SDIV_I); 435 case TargetOpcode::G_UDIV: 436 RTLIBCASE_INT(UDIV_I); 437 case TargetOpcode::G_SREM: 438 RTLIBCASE_INT(SREM_I); 439 case TargetOpcode::G_UREM: 440 RTLIBCASE_INT(UREM_I); 441 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 442 RTLIBCASE_INT(CTLZ_I); 443 case TargetOpcode::G_FADD: 444 RTLIBCASE(ADD_F); 445 case TargetOpcode::G_FSUB: 446 RTLIBCASE(SUB_F); 447 case TargetOpcode::G_FMUL: 448 RTLIBCASE(MUL_F); 449 case TargetOpcode::G_FDIV: 450 RTLIBCASE(DIV_F); 451 case TargetOpcode::G_FEXP: 452 RTLIBCASE(EXP_F); 453 case TargetOpcode::G_FEXP2: 454 RTLIBCASE(EXP2_F); 455 case TargetOpcode::G_FREM: 456 RTLIBCASE(REM_F); 457 case TargetOpcode::G_FPOW: 458 RTLIBCASE(POW_F); 459 case TargetOpcode::G_FMA: 460 RTLIBCASE(FMA_F); 461 case TargetOpcode::G_FSIN: 462 RTLIBCASE(SIN_F); 463 case TargetOpcode::G_FCOS: 464 RTLIBCASE(COS_F); 465 case TargetOpcode::G_FLOG10: 466 RTLIBCASE(LOG10_F); 467 case TargetOpcode::G_FLOG: 468 RTLIBCASE(LOG_F); 469 case TargetOpcode::G_FLOG2: 470 RTLIBCASE(LOG2_F); 471 case TargetOpcode::G_FCEIL: 472 RTLIBCASE(CEIL_F); 473 case TargetOpcode::G_FFLOOR: 474 RTLIBCASE(FLOOR_F); 475 case TargetOpcode::G_FMINNUM: 476 RTLIBCASE(FMIN_F); 477 case TargetOpcode::G_FMAXNUM: 478 RTLIBCASE(FMAX_F); 479 case TargetOpcode::G_FSQRT: 480 RTLIBCASE(SQRT_F); 481 case TargetOpcode::G_FRINT: 482 RTLIBCASE(RINT_F); 483 case TargetOpcode::G_FNEARBYINT: 484 RTLIBCASE(NEARBYINT_F); 485 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 486 RTLIBCASE(ROUNDEVEN_F); 487 } 488 llvm_unreachable("Unknown libcall function"); 489 } 490 491 /// True if an instruction is in tail position in its caller. Intended for 492 /// legalizing libcalls as tail calls when possible. 493 static bool isLibCallInTailPosition(const TargetInstrInfo &TII, 494 MachineInstr &MI) { 495 MachineBasicBlock &MBB = *MI.getParent(); 496 const Function &F = MBB.getParent()->getFunction(); 497 498 // Conservatively require the attributes of the call to match those of 499 // the return. Ignore NoAlias and NonNull because they don't affect the 500 // call sequence. 501 AttributeList CallerAttrs = F.getAttributes(); 502 if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex) 503 .removeAttribute(Attribute::NoAlias) 504 .removeAttribute(Attribute::NonNull) 505 .hasAttributes()) 506 return false; 507 508 // It's not safe to eliminate the sign / zero extension of the return value. 509 if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) || 510 CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 511 return false; 512 513 // Only tail call if the following instruction is a standard return. 514 auto Next = next_nodbg(MI.getIterator(), MBB.instr_end()); 515 if (Next == MBB.instr_end() || TII.isTailCall(*Next) || !Next->isReturn()) 516 return false; 517 518 return true; 519 } 520 521 LegalizerHelper::LegalizeResult 522 llvm::createLibcall(MachineIRBuilder &MIRBuilder, const char *Name, 523 const CallLowering::ArgInfo &Result, 524 ArrayRef<CallLowering::ArgInfo> Args, 525 const CallingConv::ID CC) { 526 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 527 528 CallLowering::CallLoweringInfo Info; 529 Info.CallConv = CC; 530 Info.Callee = MachineOperand::CreateES(Name); 531 Info.OrigRet = Result; 532 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 533 if (!CLI.lowerCall(MIRBuilder, Info)) 534 return LegalizerHelper::UnableToLegalize; 535 536 return LegalizerHelper::Legalized; 537 } 538 539 LegalizerHelper::LegalizeResult 540 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall, 541 const CallLowering::ArgInfo &Result, 542 ArrayRef<CallLowering::ArgInfo> Args) { 543 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 544 const char *Name = TLI.getLibcallName(Libcall); 545 const CallingConv::ID CC = TLI.getLibcallCallingConv(Libcall); 546 return createLibcall(MIRBuilder, Name, Result, Args, CC); 547 } 548 549 // Useful for libcalls where all operands have the same type. 550 static LegalizerHelper::LegalizeResult 551 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size, 552 Type *OpType) { 553 auto Libcall = getRTLibDesc(MI.getOpcode(), Size); 554 555 SmallVector<CallLowering::ArgInfo, 3> Args; 556 for (unsigned i = 1; i < MI.getNumOperands(); i++) 557 Args.push_back({MI.getOperand(i).getReg(), OpType}); 558 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType}, 559 Args); 560 } 561 562 LegalizerHelper::LegalizeResult 563 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 564 MachineInstr &MI) { 565 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 566 567 SmallVector<CallLowering::ArgInfo, 3> Args; 568 // Add all the args, except for the last which is an imm denoting 'tail'. 569 for (unsigned i = 0; i < MI.getNumOperands() - 1; ++i) { 570 Register Reg = MI.getOperand(i).getReg(); 571 572 // Need derive an IR type for call lowering. 573 LLT OpLLT = MRI.getType(Reg); 574 Type *OpTy = nullptr; 575 if (OpLLT.isPointer()) 576 OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace()); 577 else 578 OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits()); 579 Args.push_back({Reg, OpTy}); 580 } 581 582 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 583 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 584 RTLIB::Libcall RTLibcall; 585 unsigned Opc = MI.getOpcode(); 586 switch (Opc) { 587 case TargetOpcode::G_BZERO: 588 RTLibcall = RTLIB::BZERO; 589 break; 590 case TargetOpcode::G_MEMCPY: 591 RTLibcall = RTLIB::MEMCPY; 592 break; 593 case TargetOpcode::G_MEMMOVE: 594 RTLibcall = RTLIB::MEMMOVE; 595 break; 596 case TargetOpcode::G_MEMSET: 597 RTLibcall = RTLIB::MEMSET; 598 break; 599 default: 600 return LegalizerHelper::UnableToLegalize; 601 } 602 const char *Name = TLI.getLibcallName(RTLibcall); 603 604 // Unsupported libcall on the target. 605 if (!Name) { 606 LLVM_DEBUG(dbgs() << ".. .. Could not find libcall name for " 607 << MIRBuilder.getTII().getName(Opc) << "\n"); 608 return LegalizerHelper::UnableToLegalize; 609 } 610 611 CallLowering::CallLoweringInfo Info; 612 Info.CallConv = TLI.getLibcallCallingConv(RTLibcall); 613 Info.Callee = MachineOperand::CreateES(Name); 614 Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx)); 615 Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() && 616 isLibCallInTailPosition(MIRBuilder.getTII(), MI); 617 618 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 619 if (!CLI.lowerCall(MIRBuilder, Info)) 620 return LegalizerHelper::UnableToLegalize; 621 622 if (Info.LoweredTailCall) { 623 assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?"); 624 // We must have a return following the call (or debug insts) to get past 625 // isLibCallInTailPosition. 626 do { 627 MachineInstr *Next = MI.getNextNode(); 628 assert(Next && (Next->isReturn() || Next->isDebugInstr()) && 629 "Expected instr following MI to be return or debug inst?"); 630 // We lowered a tail call, so the call is now the return from the block. 631 // Delete the old return. 632 Next->eraseFromParent(); 633 } while (MI.getNextNode()); 634 } 635 636 return LegalizerHelper::Legalized; 637 } 638 639 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType, 640 Type *FromType) { 641 auto ToMVT = MVT::getVT(ToType); 642 auto FromMVT = MVT::getVT(FromType); 643 644 switch (Opcode) { 645 case TargetOpcode::G_FPEXT: 646 return RTLIB::getFPEXT(FromMVT, ToMVT); 647 case TargetOpcode::G_FPTRUNC: 648 return RTLIB::getFPROUND(FromMVT, ToMVT); 649 case TargetOpcode::G_FPTOSI: 650 return RTLIB::getFPTOSINT(FromMVT, ToMVT); 651 case TargetOpcode::G_FPTOUI: 652 return RTLIB::getFPTOUINT(FromMVT, ToMVT); 653 case TargetOpcode::G_SITOFP: 654 return RTLIB::getSINTTOFP(FromMVT, ToMVT); 655 case TargetOpcode::G_UITOFP: 656 return RTLIB::getUINTTOFP(FromMVT, ToMVT); 657 } 658 llvm_unreachable("Unsupported libcall function"); 659 } 660 661 static LegalizerHelper::LegalizeResult 662 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType, 663 Type *FromType) { 664 RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType); 665 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType}, 666 {{MI.getOperand(1).getReg(), FromType}}); 667 } 668 669 LegalizerHelper::LegalizeResult 670 LegalizerHelper::libcall(MachineInstr &MI) { 671 LLT LLTy = MRI.getType(MI.getOperand(0).getReg()); 672 unsigned Size = LLTy.getSizeInBits(); 673 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 674 675 switch (MI.getOpcode()) { 676 default: 677 return UnableToLegalize; 678 case TargetOpcode::G_SDIV: 679 case TargetOpcode::G_UDIV: 680 case TargetOpcode::G_SREM: 681 case TargetOpcode::G_UREM: 682 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 683 Type *HLTy = IntegerType::get(Ctx, Size); 684 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 685 if (Status != Legalized) 686 return Status; 687 break; 688 } 689 case TargetOpcode::G_FADD: 690 case TargetOpcode::G_FSUB: 691 case TargetOpcode::G_FMUL: 692 case TargetOpcode::G_FDIV: 693 case TargetOpcode::G_FMA: 694 case TargetOpcode::G_FPOW: 695 case TargetOpcode::G_FREM: 696 case TargetOpcode::G_FCOS: 697 case TargetOpcode::G_FSIN: 698 case TargetOpcode::G_FLOG10: 699 case TargetOpcode::G_FLOG: 700 case TargetOpcode::G_FLOG2: 701 case TargetOpcode::G_FEXP: 702 case TargetOpcode::G_FEXP2: 703 case TargetOpcode::G_FCEIL: 704 case TargetOpcode::G_FFLOOR: 705 case TargetOpcode::G_FMINNUM: 706 case TargetOpcode::G_FMAXNUM: 707 case TargetOpcode::G_FSQRT: 708 case TargetOpcode::G_FRINT: 709 case TargetOpcode::G_FNEARBYINT: 710 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 711 Type *HLTy = getFloatTypeForLLT(Ctx, LLTy); 712 if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) { 713 LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n"); 714 return UnableToLegalize; 715 } 716 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 717 if (Status != Legalized) 718 return Status; 719 break; 720 } 721 case TargetOpcode::G_FPEXT: 722 case TargetOpcode::G_FPTRUNC: { 723 Type *FromTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(1).getReg())); 724 Type *ToTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(0).getReg())); 725 if (!FromTy || !ToTy) 726 return UnableToLegalize; 727 LegalizeResult Status = conversionLibcall(MI, MIRBuilder, ToTy, FromTy ); 728 if (Status != Legalized) 729 return Status; 730 break; 731 } 732 case TargetOpcode::G_FPTOSI: 733 case TargetOpcode::G_FPTOUI: { 734 // FIXME: Support other types 735 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 736 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 737 if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64)) 738 return UnableToLegalize; 739 LegalizeResult Status = conversionLibcall( 740 MI, MIRBuilder, 741 ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx), 742 FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx)); 743 if (Status != Legalized) 744 return Status; 745 break; 746 } 747 case TargetOpcode::G_SITOFP: 748 case TargetOpcode::G_UITOFP: { 749 // FIXME: Support other types 750 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 751 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 752 if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64)) 753 return UnableToLegalize; 754 LegalizeResult Status = conversionLibcall( 755 MI, MIRBuilder, 756 ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx), 757 FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx)); 758 if (Status != Legalized) 759 return Status; 760 break; 761 } 762 case TargetOpcode::G_BZERO: 763 case TargetOpcode::G_MEMCPY: 764 case TargetOpcode::G_MEMMOVE: 765 case TargetOpcode::G_MEMSET: { 766 LegalizeResult Result = 767 createMemLibcall(MIRBuilder, *MIRBuilder.getMRI(), MI); 768 if (Result != Legalized) 769 return Result; 770 MI.eraseFromParent(); 771 return Result; 772 } 773 } 774 775 MI.eraseFromParent(); 776 return Legalized; 777 } 778 779 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, 780 unsigned TypeIdx, 781 LLT NarrowTy) { 782 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 783 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 784 785 switch (MI.getOpcode()) { 786 default: 787 return UnableToLegalize; 788 case TargetOpcode::G_IMPLICIT_DEF: { 789 Register DstReg = MI.getOperand(0).getReg(); 790 LLT DstTy = MRI.getType(DstReg); 791 792 // If SizeOp0 is not an exact multiple of NarrowSize, emit 793 // G_ANYEXT(G_IMPLICIT_DEF). Cast result to vector if needed. 794 // FIXME: Although this would also be legal for the general case, it causes 795 // a lot of regressions in the emitted code (superfluous COPYs, artifact 796 // combines not being hit). This seems to be a problem related to the 797 // artifact combiner. 798 if (SizeOp0 % NarrowSize != 0) { 799 LLT ImplicitTy = NarrowTy; 800 if (DstTy.isVector()) 801 ImplicitTy = LLT::vector(DstTy.getNumElements(), ImplicitTy); 802 803 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); 804 MIRBuilder.buildAnyExt(DstReg, ImplicitReg); 805 806 MI.eraseFromParent(); 807 return Legalized; 808 } 809 810 int NumParts = SizeOp0 / NarrowSize; 811 812 SmallVector<Register, 2> DstRegs; 813 for (int i = 0; i < NumParts; ++i) 814 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); 815 816 if (DstTy.isVector()) 817 MIRBuilder.buildBuildVector(DstReg, DstRegs); 818 else 819 MIRBuilder.buildMerge(DstReg, DstRegs); 820 MI.eraseFromParent(); 821 return Legalized; 822 } 823 case TargetOpcode::G_CONSTANT: { 824 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 825 const APInt &Val = MI.getOperand(1).getCImm()->getValue(); 826 unsigned TotalSize = Ty.getSizeInBits(); 827 unsigned NarrowSize = NarrowTy.getSizeInBits(); 828 int NumParts = TotalSize / NarrowSize; 829 830 SmallVector<Register, 4> PartRegs; 831 for (int I = 0; I != NumParts; ++I) { 832 unsigned Offset = I * NarrowSize; 833 auto K = MIRBuilder.buildConstant(NarrowTy, 834 Val.lshr(Offset).trunc(NarrowSize)); 835 PartRegs.push_back(K.getReg(0)); 836 } 837 838 LLT LeftoverTy; 839 unsigned LeftoverBits = TotalSize - NumParts * NarrowSize; 840 SmallVector<Register, 1> LeftoverRegs; 841 if (LeftoverBits != 0) { 842 LeftoverTy = LLT::scalar(LeftoverBits); 843 auto K = MIRBuilder.buildConstant( 844 LeftoverTy, 845 Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits)); 846 LeftoverRegs.push_back(K.getReg(0)); 847 } 848 849 insertParts(MI.getOperand(0).getReg(), 850 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs); 851 852 MI.eraseFromParent(); 853 return Legalized; 854 } 855 case TargetOpcode::G_SEXT: 856 case TargetOpcode::G_ZEXT: 857 case TargetOpcode::G_ANYEXT: 858 return narrowScalarExt(MI, TypeIdx, NarrowTy); 859 case TargetOpcode::G_TRUNC: { 860 if (TypeIdx != 1) 861 return UnableToLegalize; 862 863 uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 864 if (NarrowTy.getSizeInBits() * 2 != SizeOp1) { 865 LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n"); 866 return UnableToLegalize; 867 } 868 869 auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 870 MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0)); 871 MI.eraseFromParent(); 872 return Legalized; 873 } 874 875 case TargetOpcode::G_FREEZE: 876 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 877 case TargetOpcode::G_ADD: 878 case TargetOpcode::G_SUB: 879 case TargetOpcode::G_SADDO: 880 case TargetOpcode::G_SSUBO: 881 case TargetOpcode::G_SADDE: 882 case TargetOpcode::G_SSUBE: 883 case TargetOpcode::G_UADDO: 884 case TargetOpcode::G_USUBO: 885 case TargetOpcode::G_UADDE: 886 case TargetOpcode::G_USUBE: 887 return narrowScalarAddSub(MI, TypeIdx, NarrowTy); 888 case TargetOpcode::G_MUL: 889 case TargetOpcode::G_UMULH: 890 return narrowScalarMul(MI, NarrowTy); 891 case TargetOpcode::G_EXTRACT: 892 return narrowScalarExtract(MI, TypeIdx, NarrowTy); 893 case TargetOpcode::G_INSERT: 894 return narrowScalarInsert(MI, TypeIdx, NarrowTy); 895 case TargetOpcode::G_LOAD: { 896 auto &MMO = **MI.memoperands_begin(); 897 Register DstReg = MI.getOperand(0).getReg(); 898 LLT DstTy = MRI.getType(DstReg); 899 if (DstTy.isVector()) 900 return UnableToLegalize; 901 902 if (8 * MMO.getSize() != DstTy.getSizeInBits()) { 903 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 904 MIRBuilder.buildLoad(TmpReg, MI.getOperand(1), MMO); 905 MIRBuilder.buildAnyExt(DstReg, TmpReg); 906 MI.eraseFromParent(); 907 return Legalized; 908 } 909 910 return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy); 911 } 912 case TargetOpcode::G_ZEXTLOAD: 913 case TargetOpcode::G_SEXTLOAD: { 914 bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD; 915 Register DstReg = MI.getOperand(0).getReg(); 916 Register PtrReg = MI.getOperand(1).getReg(); 917 918 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 919 auto &MMO = **MI.memoperands_begin(); 920 unsigned MemSize = MMO.getSizeInBits(); 921 922 if (MemSize == NarrowSize) { 923 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); 924 } else if (MemSize < NarrowSize) { 925 MIRBuilder.buildLoadInstr(MI.getOpcode(), TmpReg, PtrReg, MMO); 926 } else if (MemSize > NarrowSize) { 927 // FIXME: Need to split the load. 928 return UnableToLegalize; 929 } 930 931 if (ZExt) 932 MIRBuilder.buildZExt(DstReg, TmpReg); 933 else 934 MIRBuilder.buildSExt(DstReg, TmpReg); 935 936 MI.eraseFromParent(); 937 return Legalized; 938 } 939 case TargetOpcode::G_STORE: { 940 const auto &MMO = **MI.memoperands_begin(); 941 942 Register SrcReg = MI.getOperand(0).getReg(); 943 LLT SrcTy = MRI.getType(SrcReg); 944 if (SrcTy.isVector()) 945 return UnableToLegalize; 946 947 int NumParts = SizeOp0 / NarrowSize; 948 unsigned HandledSize = NumParts * NarrowTy.getSizeInBits(); 949 unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize; 950 if (SrcTy.isVector() && LeftoverBits != 0) 951 return UnableToLegalize; 952 953 if (8 * MMO.getSize() != SrcTy.getSizeInBits()) { 954 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 955 auto &MMO = **MI.memoperands_begin(); 956 MIRBuilder.buildTrunc(TmpReg, SrcReg); 957 MIRBuilder.buildStore(TmpReg, MI.getOperand(1), MMO); 958 MI.eraseFromParent(); 959 return Legalized; 960 } 961 962 return reduceLoadStoreWidth(MI, 0, NarrowTy); 963 } 964 case TargetOpcode::G_SELECT: 965 return narrowScalarSelect(MI, TypeIdx, NarrowTy); 966 case TargetOpcode::G_AND: 967 case TargetOpcode::G_OR: 968 case TargetOpcode::G_XOR: { 969 // Legalize bitwise operation: 970 // A = BinOp<Ty> B, C 971 // into: 972 // B1, ..., BN = G_UNMERGE_VALUES B 973 // C1, ..., CN = G_UNMERGE_VALUES C 974 // A1 = BinOp<Ty/N> B1, C2 975 // ... 976 // AN = BinOp<Ty/N> BN, CN 977 // A = G_MERGE_VALUES A1, ..., AN 978 return narrowScalarBasic(MI, TypeIdx, NarrowTy); 979 } 980 case TargetOpcode::G_SHL: 981 case TargetOpcode::G_LSHR: 982 case TargetOpcode::G_ASHR: 983 return narrowScalarShift(MI, TypeIdx, NarrowTy); 984 case TargetOpcode::G_CTLZ: 985 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 986 case TargetOpcode::G_CTTZ: 987 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 988 case TargetOpcode::G_CTPOP: 989 if (TypeIdx == 1) 990 switch (MI.getOpcode()) { 991 case TargetOpcode::G_CTLZ: 992 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 993 return narrowScalarCTLZ(MI, TypeIdx, NarrowTy); 994 case TargetOpcode::G_CTTZ: 995 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 996 return narrowScalarCTTZ(MI, TypeIdx, NarrowTy); 997 case TargetOpcode::G_CTPOP: 998 return narrowScalarCTPOP(MI, TypeIdx, NarrowTy); 999 default: 1000 return UnableToLegalize; 1001 } 1002 1003 Observer.changingInstr(MI); 1004 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1005 Observer.changedInstr(MI); 1006 return Legalized; 1007 case TargetOpcode::G_INTTOPTR: 1008 if (TypeIdx != 1) 1009 return UnableToLegalize; 1010 1011 Observer.changingInstr(MI); 1012 narrowScalarSrc(MI, NarrowTy, 1); 1013 Observer.changedInstr(MI); 1014 return Legalized; 1015 case TargetOpcode::G_PTRTOINT: 1016 if (TypeIdx != 0) 1017 return UnableToLegalize; 1018 1019 Observer.changingInstr(MI); 1020 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1021 Observer.changedInstr(MI); 1022 return Legalized; 1023 case TargetOpcode::G_PHI: { 1024 // FIXME: add support for when SizeOp0 isn't an exact multiple of 1025 // NarrowSize. 1026 if (SizeOp0 % NarrowSize != 0) 1027 return UnableToLegalize; 1028 1029 unsigned NumParts = SizeOp0 / NarrowSize; 1030 SmallVector<Register, 2> DstRegs(NumParts); 1031 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2); 1032 Observer.changingInstr(MI); 1033 for (unsigned i = 1; i < MI.getNumOperands(); i += 2) { 1034 MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB(); 1035 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 1036 extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts, 1037 SrcRegs[i / 2]); 1038 } 1039 MachineBasicBlock &MBB = *MI.getParent(); 1040 MIRBuilder.setInsertPt(MBB, MI); 1041 for (unsigned i = 0; i < NumParts; ++i) { 1042 DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy); 1043 MachineInstrBuilder MIB = 1044 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); 1045 for (unsigned j = 1; j < MI.getNumOperands(); j += 2) 1046 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); 1047 } 1048 MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI()); 1049 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1050 Observer.changedInstr(MI); 1051 MI.eraseFromParent(); 1052 return Legalized; 1053 } 1054 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 1055 case TargetOpcode::G_INSERT_VECTOR_ELT: { 1056 if (TypeIdx != 2) 1057 return UnableToLegalize; 1058 1059 int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3; 1060 Observer.changingInstr(MI); 1061 narrowScalarSrc(MI, NarrowTy, OpIdx); 1062 Observer.changedInstr(MI); 1063 return Legalized; 1064 } 1065 case TargetOpcode::G_ICMP: { 1066 uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 1067 if (NarrowSize * 2 != SrcSize) 1068 return UnableToLegalize; 1069 1070 Observer.changingInstr(MI); 1071 Register LHSL = MRI.createGenericVirtualRegister(NarrowTy); 1072 Register LHSH = MRI.createGenericVirtualRegister(NarrowTy); 1073 MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2)); 1074 1075 Register RHSL = MRI.createGenericVirtualRegister(NarrowTy); 1076 Register RHSH = MRI.createGenericVirtualRegister(NarrowTy); 1077 MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3)); 1078 1079 CmpInst::Predicate Pred = 1080 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 1081 LLT ResTy = MRI.getType(MI.getOperand(0).getReg()); 1082 1083 if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) { 1084 MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL); 1085 MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH); 1086 MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH); 1087 MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0); 1088 MIRBuilder.buildICmp(Pred, MI.getOperand(0), Or, Zero); 1089 } else { 1090 MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH); 1091 MachineInstrBuilder CmpHEQ = 1092 MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH); 1093 MachineInstrBuilder CmpLU = MIRBuilder.buildICmp( 1094 ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL); 1095 MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH); 1096 } 1097 Observer.changedInstr(MI); 1098 MI.eraseFromParent(); 1099 return Legalized; 1100 } 1101 case TargetOpcode::G_SEXT_INREG: { 1102 if (TypeIdx != 0) 1103 return UnableToLegalize; 1104 1105 int64_t SizeInBits = MI.getOperand(2).getImm(); 1106 1107 // So long as the new type has more bits than the bits we're extending we 1108 // don't need to break it apart. 1109 if (NarrowTy.getScalarSizeInBits() >= SizeInBits) { 1110 Observer.changingInstr(MI); 1111 // We don't lose any non-extension bits by truncating the src and 1112 // sign-extending the dst. 1113 MachineOperand &MO1 = MI.getOperand(1); 1114 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1); 1115 MO1.setReg(TruncMIB.getReg(0)); 1116 1117 MachineOperand &MO2 = MI.getOperand(0); 1118 Register DstExt = MRI.createGenericVirtualRegister(NarrowTy); 1119 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1120 MIRBuilder.buildSExt(MO2, DstExt); 1121 MO2.setReg(DstExt); 1122 Observer.changedInstr(MI); 1123 return Legalized; 1124 } 1125 1126 // Break it apart. Components below the extension point are unmodified. The 1127 // component containing the extension point becomes a narrower SEXT_INREG. 1128 // Components above it are ashr'd from the component containing the 1129 // extension point. 1130 if (SizeOp0 % NarrowSize != 0) 1131 return UnableToLegalize; 1132 int NumParts = SizeOp0 / NarrowSize; 1133 1134 // List the registers where the destination will be scattered. 1135 SmallVector<Register, 2> DstRegs; 1136 // List the registers where the source will be split. 1137 SmallVector<Register, 2> SrcRegs; 1138 1139 // Create all the temporary registers. 1140 for (int i = 0; i < NumParts; ++i) { 1141 Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy); 1142 1143 SrcRegs.push_back(SrcReg); 1144 } 1145 1146 // Explode the big arguments into smaller chunks. 1147 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1)); 1148 1149 Register AshrCstReg = 1150 MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1) 1151 .getReg(0); 1152 Register FullExtensionReg = 0; 1153 Register PartialExtensionReg = 0; 1154 1155 // Do the operation on each small part. 1156 for (int i = 0; i < NumParts; ++i) { 1157 if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits) 1158 DstRegs.push_back(SrcRegs[i]); 1159 else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) { 1160 assert(PartialExtensionReg && 1161 "Expected to visit partial extension before full"); 1162 if (FullExtensionReg) { 1163 DstRegs.push_back(FullExtensionReg); 1164 continue; 1165 } 1166 DstRegs.push_back( 1167 MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg) 1168 .getReg(0)); 1169 FullExtensionReg = DstRegs.back(); 1170 } else { 1171 DstRegs.push_back( 1172 MIRBuilder 1173 .buildInstr( 1174 TargetOpcode::G_SEXT_INREG, {NarrowTy}, 1175 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) 1176 .getReg(0)); 1177 PartialExtensionReg = DstRegs.back(); 1178 } 1179 } 1180 1181 // Gather the destination registers into the final destination. 1182 Register DstReg = MI.getOperand(0).getReg(); 1183 MIRBuilder.buildMerge(DstReg, DstRegs); 1184 MI.eraseFromParent(); 1185 return Legalized; 1186 } 1187 case TargetOpcode::G_BSWAP: 1188 case TargetOpcode::G_BITREVERSE: { 1189 if (SizeOp0 % NarrowSize != 0) 1190 return UnableToLegalize; 1191 1192 Observer.changingInstr(MI); 1193 SmallVector<Register, 2> SrcRegs, DstRegs; 1194 unsigned NumParts = SizeOp0 / NarrowSize; 1195 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 1196 1197 for (unsigned i = 0; i < NumParts; ++i) { 1198 auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 1199 {SrcRegs[NumParts - 1 - i]}); 1200 DstRegs.push_back(DstPart.getReg(0)); 1201 } 1202 1203 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1204 1205 Observer.changedInstr(MI); 1206 MI.eraseFromParent(); 1207 return Legalized; 1208 } 1209 case TargetOpcode::G_PTR_ADD: 1210 case TargetOpcode::G_PTRMASK: { 1211 if (TypeIdx != 1) 1212 return UnableToLegalize; 1213 Observer.changingInstr(MI); 1214 narrowScalarSrc(MI, NarrowTy, 2); 1215 Observer.changedInstr(MI); 1216 return Legalized; 1217 } 1218 case TargetOpcode::G_FPTOUI: { 1219 if (TypeIdx != 0) 1220 return UnableToLegalize; 1221 Observer.changingInstr(MI); 1222 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1223 Observer.changedInstr(MI); 1224 return Legalized; 1225 } 1226 case TargetOpcode::G_FPTOSI: { 1227 if (TypeIdx != 0) 1228 return UnableToLegalize; 1229 Observer.changingInstr(MI); 1230 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_SEXT); 1231 Observer.changedInstr(MI); 1232 return Legalized; 1233 } 1234 case TargetOpcode::G_FPEXT: 1235 if (TypeIdx != 0) 1236 return UnableToLegalize; 1237 Observer.changingInstr(MI); 1238 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_FPEXT); 1239 Observer.changedInstr(MI); 1240 return Legalized; 1241 } 1242 } 1243 1244 Register LegalizerHelper::coerceToScalar(Register Val) { 1245 LLT Ty = MRI.getType(Val); 1246 if (Ty.isScalar()) 1247 return Val; 1248 1249 const DataLayout &DL = MIRBuilder.getDataLayout(); 1250 LLT NewTy = LLT::scalar(Ty.getSizeInBits()); 1251 if (Ty.isPointer()) { 1252 if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace())) 1253 return Register(); 1254 return MIRBuilder.buildPtrToInt(NewTy, Val).getReg(0); 1255 } 1256 1257 Register NewVal = Val; 1258 1259 assert(Ty.isVector()); 1260 LLT EltTy = Ty.getElementType(); 1261 if (EltTy.isPointer()) 1262 NewVal = MIRBuilder.buildPtrToInt(NewTy, NewVal).getReg(0); 1263 return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0); 1264 } 1265 1266 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy, 1267 unsigned OpIdx, unsigned ExtOpcode) { 1268 MachineOperand &MO = MI.getOperand(OpIdx); 1269 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO}); 1270 MO.setReg(ExtB.getReg(0)); 1271 } 1272 1273 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, 1274 unsigned OpIdx) { 1275 MachineOperand &MO = MI.getOperand(OpIdx); 1276 auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO); 1277 MO.setReg(ExtB.getReg(0)); 1278 } 1279 1280 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy, 1281 unsigned OpIdx, unsigned TruncOpcode) { 1282 MachineOperand &MO = MI.getOperand(OpIdx); 1283 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1284 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1285 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); 1286 MO.setReg(DstExt); 1287 } 1288 1289 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy, 1290 unsigned OpIdx, unsigned ExtOpcode) { 1291 MachineOperand &MO = MI.getOperand(OpIdx); 1292 Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy); 1293 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1294 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); 1295 MO.setReg(DstTrunc); 1296 } 1297 1298 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy, 1299 unsigned OpIdx) { 1300 MachineOperand &MO = MI.getOperand(OpIdx); 1301 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1302 MO.setReg(widenWithUnmerge(WideTy, MO.getReg())); 1303 } 1304 1305 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, 1306 unsigned OpIdx) { 1307 MachineOperand &MO = MI.getOperand(OpIdx); 1308 1309 LLT OldTy = MRI.getType(MO.getReg()); 1310 unsigned OldElts = OldTy.getNumElements(); 1311 unsigned NewElts = MoreTy.getNumElements(); 1312 1313 unsigned NumParts = NewElts / OldElts; 1314 1315 // Use concat_vectors if the result is a multiple of the number of elements. 1316 if (NumParts * OldElts == NewElts) { 1317 SmallVector<Register, 8> Parts; 1318 Parts.push_back(MO.getReg()); 1319 1320 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); 1321 for (unsigned I = 1; I != NumParts; ++I) 1322 Parts.push_back(ImpDef); 1323 1324 auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts); 1325 MO.setReg(Concat.getReg(0)); 1326 return; 1327 } 1328 1329 Register MoreReg = MRI.createGenericVirtualRegister(MoreTy); 1330 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); 1331 MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0); 1332 MO.setReg(MoreReg); 1333 } 1334 1335 void LegalizerHelper::bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1336 MachineOperand &Op = MI.getOperand(OpIdx); 1337 Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0)); 1338 } 1339 1340 void LegalizerHelper::bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1341 MachineOperand &MO = MI.getOperand(OpIdx); 1342 Register CastDst = MRI.createGenericVirtualRegister(CastTy); 1343 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1344 MIRBuilder.buildBitcast(MO, CastDst); 1345 MO.setReg(CastDst); 1346 } 1347 1348 LegalizerHelper::LegalizeResult 1349 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, 1350 LLT WideTy) { 1351 if (TypeIdx != 1) 1352 return UnableToLegalize; 1353 1354 Register DstReg = MI.getOperand(0).getReg(); 1355 LLT DstTy = MRI.getType(DstReg); 1356 if (DstTy.isVector()) 1357 return UnableToLegalize; 1358 1359 Register Src1 = MI.getOperand(1).getReg(); 1360 LLT SrcTy = MRI.getType(Src1); 1361 const int DstSize = DstTy.getSizeInBits(); 1362 const int SrcSize = SrcTy.getSizeInBits(); 1363 const int WideSize = WideTy.getSizeInBits(); 1364 const int NumMerge = (DstSize + WideSize - 1) / WideSize; 1365 1366 unsigned NumOps = MI.getNumOperands(); 1367 unsigned NumSrc = MI.getNumOperands() - 1; 1368 unsigned PartSize = DstTy.getSizeInBits() / NumSrc; 1369 1370 if (WideSize >= DstSize) { 1371 // Directly pack the bits in the target type. 1372 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); 1373 1374 for (unsigned I = 2; I != NumOps; ++I) { 1375 const unsigned Offset = (I - 1) * PartSize; 1376 1377 Register SrcReg = MI.getOperand(I).getReg(); 1378 assert(MRI.getType(SrcReg) == LLT::scalar(PartSize)); 1379 1380 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 1381 1382 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 1383 MRI.createGenericVirtualRegister(WideTy); 1384 1385 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 1386 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 1387 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 1388 ResultReg = NextResult; 1389 } 1390 1391 if (WideSize > DstSize) 1392 MIRBuilder.buildTrunc(DstReg, ResultReg); 1393 else if (DstTy.isPointer()) 1394 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 1395 1396 MI.eraseFromParent(); 1397 return Legalized; 1398 } 1399 1400 // Unmerge the original values to the GCD type, and recombine to the next 1401 // multiple greater than the original type. 1402 // 1403 // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6 1404 // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0 1405 // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1 1406 // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2 1407 // %10:_(s6) = G_MERGE_VALUES %4, %5, %6 1408 // %11:_(s6) = G_MERGE_VALUES %7, %8, %9 1409 // %12:_(s12) = G_MERGE_VALUES %10, %11 1410 // 1411 // Padding with undef if necessary: 1412 // 1413 // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6 1414 // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0 1415 // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1 1416 // %7:_(s2) = G_IMPLICIT_DEF 1417 // %8:_(s6) = G_MERGE_VALUES %3, %4, %5 1418 // %9:_(s6) = G_MERGE_VALUES %6, %7, %7 1419 // %10:_(s12) = G_MERGE_VALUES %8, %9 1420 1421 const int GCD = greatestCommonDivisor(SrcSize, WideSize); 1422 LLT GCDTy = LLT::scalar(GCD); 1423 1424 SmallVector<Register, 8> Parts; 1425 SmallVector<Register, 8> NewMergeRegs; 1426 SmallVector<Register, 8> Unmerges; 1427 LLT WideDstTy = LLT::scalar(NumMerge * WideSize); 1428 1429 // Decompose the original operands if they don't evenly divide. 1430 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) { 1431 Register SrcReg = MI.getOperand(I).getReg(); 1432 if (GCD == SrcSize) { 1433 Unmerges.push_back(SrcReg); 1434 } else { 1435 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 1436 for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J) 1437 Unmerges.push_back(Unmerge.getReg(J)); 1438 } 1439 } 1440 1441 // Pad with undef to the next size that is a multiple of the requested size. 1442 if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) { 1443 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 1444 for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I) 1445 Unmerges.push_back(UndefReg); 1446 } 1447 1448 const int PartsPerGCD = WideSize / GCD; 1449 1450 // Build merges of each piece. 1451 ArrayRef<Register> Slicer(Unmerges); 1452 for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) { 1453 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD)); 1454 NewMergeRegs.push_back(Merge.getReg(0)); 1455 } 1456 1457 // A truncate may be necessary if the requested type doesn't evenly divide the 1458 // original result type. 1459 if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) { 1460 MIRBuilder.buildMerge(DstReg, NewMergeRegs); 1461 } else { 1462 auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs); 1463 MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0)); 1464 } 1465 1466 MI.eraseFromParent(); 1467 return Legalized; 1468 } 1469 1470 Register LegalizerHelper::widenWithUnmerge(LLT WideTy, Register OrigReg) { 1471 Register WideReg = MRI.createGenericVirtualRegister(WideTy); 1472 LLT OrigTy = MRI.getType(OrigReg); 1473 LLT LCMTy = getLCMType(WideTy, OrigTy); 1474 1475 const int NumMergeParts = LCMTy.getSizeInBits() / WideTy.getSizeInBits(); 1476 const int NumUnmergeParts = LCMTy.getSizeInBits() / OrigTy.getSizeInBits(); 1477 1478 Register UnmergeSrc = WideReg; 1479 1480 // Create a merge to the LCM type, padding with undef 1481 // %0:_(<3 x s32>) = G_FOO => <4 x s32> 1482 // => 1483 // %1:_(<4 x s32>) = G_FOO 1484 // %2:_(<4 x s32>) = G_IMPLICIT_DEF 1485 // %3:_(<12 x s32>) = G_CONCAT_VECTORS %1, %2, %2 1486 // %0:_(<3 x s32>), %4:_, %5:_, %6:_ = G_UNMERGE_VALUES %3 1487 if (NumMergeParts > 1) { 1488 Register Undef = MIRBuilder.buildUndef(WideTy).getReg(0); 1489 SmallVector<Register, 8> MergeParts(NumMergeParts, Undef); 1490 MergeParts[0] = WideReg; 1491 UnmergeSrc = MIRBuilder.buildMerge(LCMTy, MergeParts).getReg(0); 1492 } 1493 1494 // Unmerge to the original register and pad with dead defs. 1495 SmallVector<Register, 8> UnmergeResults(NumUnmergeParts); 1496 UnmergeResults[0] = OrigReg; 1497 for (int I = 1; I != NumUnmergeParts; ++I) 1498 UnmergeResults[I] = MRI.createGenericVirtualRegister(OrigTy); 1499 1500 MIRBuilder.buildUnmerge(UnmergeResults, UnmergeSrc); 1501 return WideReg; 1502 } 1503 1504 LegalizerHelper::LegalizeResult 1505 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, 1506 LLT WideTy) { 1507 if (TypeIdx != 0) 1508 return UnableToLegalize; 1509 1510 int NumDst = MI.getNumOperands() - 1; 1511 Register SrcReg = MI.getOperand(NumDst).getReg(); 1512 LLT SrcTy = MRI.getType(SrcReg); 1513 if (SrcTy.isVector()) 1514 return UnableToLegalize; 1515 1516 Register Dst0Reg = MI.getOperand(0).getReg(); 1517 LLT DstTy = MRI.getType(Dst0Reg); 1518 if (!DstTy.isScalar()) 1519 return UnableToLegalize; 1520 1521 if (WideTy.getSizeInBits() >= SrcTy.getSizeInBits()) { 1522 if (SrcTy.isPointer()) { 1523 const DataLayout &DL = MIRBuilder.getDataLayout(); 1524 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) { 1525 LLVM_DEBUG( 1526 dbgs() << "Not casting non-integral address space integer\n"); 1527 return UnableToLegalize; 1528 } 1529 1530 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 1531 SrcReg = MIRBuilder.buildPtrToInt(SrcTy, SrcReg).getReg(0); 1532 } 1533 1534 // Widen SrcTy to WideTy. This does not affect the result, but since the 1535 // user requested this size, it is probably better handled than SrcTy and 1536 // should reduce the total number of legalization artifacts 1537 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1538 SrcTy = WideTy; 1539 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); 1540 } 1541 1542 // Theres no unmerge type to target. Directly extract the bits from the 1543 // source type 1544 unsigned DstSize = DstTy.getSizeInBits(); 1545 1546 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 1547 for (int I = 1; I != NumDst; ++I) { 1548 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I); 1549 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); 1550 MIRBuilder.buildTrunc(MI.getOperand(I), Shr); 1551 } 1552 1553 MI.eraseFromParent(); 1554 return Legalized; 1555 } 1556 1557 // Extend the source to a wider type. 1558 LLT LCMTy = getLCMType(SrcTy, WideTy); 1559 1560 Register WideSrc = SrcReg; 1561 if (LCMTy.getSizeInBits() != SrcTy.getSizeInBits()) { 1562 // TODO: If this is an integral address space, cast to integer and anyext. 1563 if (SrcTy.isPointer()) { 1564 LLVM_DEBUG(dbgs() << "Widening pointer source types not implemented\n"); 1565 return UnableToLegalize; 1566 } 1567 1568 WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0); 1569 } 1570 1571 auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc); 1572 1573 // Create a sequence of unmerges and merges to the original results. Since we 1574 // may have widened the source, we will need to pad the results with dead defs 1575 // to cover the source register. 1576 // e.g. widen s48 to s64: 1577 // %1:_(s48), %2:_(s48) = G_UNMERGE_VALUES %0:_(s96) 1578 // 1579 // => 1580 // %4:_(s192) = G_ANYEXT %0:_(s96) 1581 // %5:_(s64), %6, %7 = G_UNMERGE_VALUES %4 ; Requested unmerge 1582 // ; unpack to GCD type, with extra dead defs 1583 // %8:_(s16), %9, %10, %11 = G_UNMERGE_VALUES %5:_(s64) 1584 // %12:_(s16), %13, dead %14, dead %15 = G_UNMERGE_VALUES %6:_(s64) 1585 // dead %16:_(s16), dead %17, dead %18, dead %18 = G_UNMERGE_VALUES %7:_(s64) 1586 // %1:_(s48) = G_MERGE_VALUES %8:_(s16), %9, %10 ; Remerge to destination 1587 // %2:_(s48) = G_MERGE_VALUES %11:_(s16), %12, %13 ; Remerge to destination 1588 const LLT GCDTy = getGCDType(WideTy, DstTy); 1589 const int NumUnmerge = Unmerge->getNumOperands() - 1; 1590 const int PartsPerRemerge = DstTy.getSizeInBits() / GCDTy.getSizeInBits(); 1591 1592 // Directly unmerge to the destination without going through a GCD type 1593 // if possible 1594 if (PartsPerRemerge == 1) { 1595 const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits(); 1596 1597 for (int I = 0; I != NumUnmerge; ++I) { 1598 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 1599 1600 for (int J = 0; J != PartsPerUnmerge; ++J) { 1601 int Idx = I * PartsPerUnmerge + J; 1602 if (Idx < NumDst) 1603 MIB.addDef(MI.getOperand(Idx).getReg()); 1604 else { 1605 // Create dead def for excess components. 1606 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 1607 } 1608 } 1609 1610 MIB.addUse(Unmerge.getReg(I)); 1611 } 1612 } else { 1613 SmallVector<Register, 16> Parts; 1614 for (int J = 0; J != NumUnmerge; ++J) 1615 extractGCDType(Parts, GCDTy, Unmerge.getReg(J)); 1616 1617 SmallVector<Register, 8> RemergeParts; 1618 for (int I = 0; I != NumDst; ++I) { 1619 for (int J = 0; J < PartsPerRemerge; ++J) { 1620 const int Idx = I * PartsPerRemerge + J; 1621 RemergeParts.emplace_back(Parts[Idx]); 1622 } 1623 1624 MIRBuilder.buildMerge(MI.getOperand(I).getReg(), RemergeParts); 1625 RemergeParts.clear(); 1626 } 1627 } 1628 1629 MI.eraseFromParent(); 1630 return Legalized; 1631 } 1632 1633 LegalizerHelper::LegalizeResult 1634 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, 1635 LLT WideTy) { 1636 Register DstReg = MI.getOperand(0).getReg(); 1637 Register SrcReg = MI.getOperand(1).getReg(); 1638 LLT SrcTy = MRI.getType(SrcReg); 1639 1640 LLT DstTy = MRI.getType(DstReg); 1641 unsigned Offset = MI.getOperand(2).getImm(); 1642 1643 if (TypeIdx == 0) { 1644 if (SrcTy.isVector() || DstTy.isVector()) 1645 return UnableToLegalize; 1646 1647 SrcOp Src(SrcReg); 1648 if (SrcTy.isPointer()) { 1649 // Extracts from pointers can be handled only if they are really just 1650 // simple integers. 1651 const DataLayout &DL = MIRBuilder.getDataLayout(); 1652 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) 1653 return UnableToLegalize; 1654 1655 LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits()); 1656 Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src); 1657 SrcTy = SrcAsIntTy; 1658 } 1659 1660 if (DstTy.isPointer()) 1661 return UnableToLegalize; 1662 1663 if (Offset == 0) { 1664 // Avoid a shift in the degenerate case. 1665 MIRBuilder.buildTrunc(DstReg, 1666 MIRBuilder.buildAnyExtOrTrunc(WideTy, Src)); 1667 MI.eraseFromParent(); 1668 return Legalized; 1669 } 1670 1671 // Do a shift in the source type. 1672 LLT ShiftTy = SrcTy; 1673 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1674 Src = MIRBuilder.buildAnyExt(WideTy, Src); 1675 ShiftTy = WideTy; 1676 } 1677 1678 auto LShr = MIRBuilder.buildLShr( 1679 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); 1680 MIRBuilder.buildTrunc(DstReg, LShr); 1681 MI.eraseFromParent(); 1682 return Legalized; 1683 } 1684 1685 if (SrcTy.isScalar()) { 1686 Observer.changingInstr(MI); 1687 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1688 Observer.changedInstr(MI); 1689 return Legalized; 1690 } 1691 1692 if (!SrcTy.isVector()) 1693 return UnableToLegalize; 1694 1695 if (DstTy != SrcTy.getElementType()) 1696 return UnableToLegalize; 1697 1698 if (Offset % SrcTy.getScalarSizeInBits() != 0) 1699 return UnableToLegalize; 1700 1701 Observer.changingInstr(MI); 1702 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1703 1704 MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) * 1705 Offset); 1706 widenScalarDst(MI, WideTy.getScalarType(), 0); 1707 Observer.changedInstr(MI); 1708 return Legalized; 1709 } 1710 1711 LegalizerHelper::LegalizeResult 1712 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, 1713 LLT WideTy) { 1714 if (TypeIdx != 0 || WideTy.isVector()) 1715 return UnableToLegalize; 1716 Observer.changingInstr(MI); 1717 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1718 widenScalarDst(MI, WideTy); 1719 Observer.changedInstr(MI); 1720 return Legalized; 1721 } 1722 1723 LegalizerHelper::LegalizeResult 1724 LegalizerHelper::widenScalarAddSubOverflow(MachineInstr &MI, unsigned TypeIdx, 1725 LLT WideTy) { 1726 if (TypeIdx == 1) 1727 return UnableToLegalize; // TODO 1728 1729 unsigned Opcode; 1730 unsigned ExtOpcode; 1731 Optional<Register> CarryIn = None; 1732 switch (MI.getOpcode()) { 1733 default: 1734 llvm_unreachable("Unexpected opcode!"); 1735 case TargetOpcode::G_SADDO: 1736 Opcode = TargetOpcode::G_ADD; 1737 ExtOpcode = TargetOpcode::G_SEXT; 1738 break; 1739 case TargetOpcode::G_SSUBO: 1740 Opcode = TargetOpcode::G_SUB; 1741 ExtOpcode = TargetOpcode::G_SEXT; 1742 break; 1743 case TargetOpcode::G_UADDO: 1744 Opcode = TargetOpcode::G_ADD; 1745 ExtOpcode = TargetOpcode::G_ZEXT; 1746 break; 1747 case TargetOpcode::G_USUBO: 1748 Opcode = TargetOpcode::G_SUB; 1749 ExtOpcode = TargetOpcode::G_ZEXT; 1750 break; 1751 case TargetOpcode::G_SADDE: 1752 Opcode = TargetOpcode::G_UADDE; 1753 ExtOpcode = TargetOpcode::G_SEXT; 1754 CarryIn = MI.getOperand(4).getReg(); 1755 break; 1756 case TargetOpcode::G_SSUBE: 1757 Opcode = TargetOpcode::G_USUBE; 1758 ExtOpcode = TargetOpcode::G_SEXT; 1759 CarryIn = MI.getOperand(4).getReg(); 1760 break; 1761 case TargetOpcode::G_UADDE: 1762 Opcode = TargetOpcode::G_UADDE; 1763 ExtOpcode = TargetOpcode::G_ZEXT; 1764 CarryIn = MI.getOperand(4).getReg(); 1765 break; 1766 case TargetOpcode::G_USUBE: 1767 Opcode = TargetOpcode::G_USUBE; 1768 ExtOpcode = TargetOpcode::G_ZEXT; 1769 CarryIn = MI.getOperand(4).getReg(); 1770 break; 1771 } 1772 1773 auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)}); 1774 auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)}); 1775 // Do the arithmetic in the larger type. 1776 Register NewOp; 1777 if (CarryIn) { 1778 LLT CarryOutTy = MRI.getType(MI.getOperand(1).getReg()); 1779 NewOp = MIRBuilder 1780 .buildInstr(Opcode, {WideTy, CarryOutTy}, 1781 {LHSExt, RHSExt, *CarryIn}) 1782 .getReg(0); 1783 } else { 1784 NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt}).getReg(0); 1785 } 1786 LLT OrigTy = MRI.getType(MI.getOperand(0).getReg()); 1787 auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp); 1788 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); 1789 // There is no overflow if the ExtOp is the same as NewOp. 1790 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); 1791 // Now trunc the NewOp to the original result. 1792 MIRBuilder.buildTrunc(MI.getOperand(0), NewOp); 1793 MI.eraseFromParent(); 1794 return Legalized; 1795 } 1796 1797 LegalizerHelper::LegalizeResult 1798 LegalizerHelper::widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx, 1799 LLT WideTy) { 1800 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SADDSAT || 1801 MI.getOpcode() == TargetOpcode::G_SSUBSAT || 1802 MI.getOpcode() == TargetOpcode::G_SSHLSAT; 1803 bool IsShift = MI.getOpcode() == TargetOpcode::G_SSHLSAT || 1804 MI.getOpcode() == TargetOpcode::G_USHLSAT; 1805 // We can convert this to: 1806 // 1. Any extend iN to iM 1807 // 2. SHL by M-N 1808 // 3. [US][ADD|SUB|SHL]SAT 1809 // 4. L/ASHR by M-N 1810 // 1811 // It may be more efficient to lower this to a min and a max operation in 1812 // the higher precision arithmetic if the promoted operation isn't legal, 1813 // but this decision is up to the target's lowering request. 1814 Register DstReg = MI.getOperand(0).getReg(); 1815 1816 unsigned NewBits = WideTy.getScalarSizeInBits(); 1817 unsigned SHLAmount = NewBits - MRI.getType(DstReg).getScalarSizeInBits(); 1818 1819 // Shifts must zero-extend the RHS to preserve the unsigned quantity, and 1820 // must not left shift the RHS to preserve the shift amount. 1821 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1)); 1822 auto RHS = IsShift ? MIRBuilder.buildZExt(WideTy, MI.getOperand(2)) 1823 : MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2)); 1824 auto ShiftK = MIRBuilder.buildConstant(WideTy, SHLAmount); 1825 auto ShiftL = MIRBuilder.buildShl(WideTy, LHS, ShiftK); 1826 auto ShiftR = IsShift ? RHS : MIRBuilder.buildShl(WideTy, RHS, ShiftK); 1827 1828 auto WideInst = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, 1829 {ShiftL, ShiftR}, MI.getFlags()); 1830 1831 // Use a shift that will preserve the number of sign bits when the trunc is 1832 // folded away. 1833 auto Result = IsSigned ? MIRBuilder.buildAShr(WideTy, WideInst, ShiftK) 1834 : MIRBuilder.buildLShr(WideTy, WideInst, ShiftK); 1835 1836 MIRBuilder.buildTrunc(DstReg, Result); 1837 MI.eraseFromParent(); 1838 return Legalized; 1839 } 1840 1841 LegalizerHelper::LegalizeResult 1842 LegalizerHelper::widenScalarMulo(MachineInstr &MI, unsigned TypeIdx, 1843 LLT WideTy) { 1844 if (TypeIdx == 1) 1845 return UnableToLegalize; 1846 1847 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULO; 1848 Register Result = MI.getOperand(0).getReg(); 1849 Register OriginalOverflow = MI.getOperand(1).getReg(); 1850 Register LHS = MI.getOperand(2).getReg(); 1851 Register RHS = MI.getOperand(3).getReg(); 1852 LLT SrcTy = MRI.getType(LHS); 1853 LLT OverflowTy = MRI.getType(OriginalOverflow); 1854 unsigned SrcBitWidth = SrcTy.getScalarSizeInBits(); 1855 1856 // To determine if the result overflowed in the larger type, we extend the 1857 // input to the larger type, do the multiply (checking if it overflows), 1858 // then also check the high bits of the result to see if overflow happened 1859 // there. 1860 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 1861 auto LeftOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {LHS}); 1862 auto RightOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {RHS}); 1863 1864 auto Mulo = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy, OverflowTy}, 1865 {LeftOperand, RightOperand}); 1866 auto Mul = Mulo->getOperand(0); 1867 MIRBuilder.buildTrunc(Result, Mul); 1868 1869 MachineInstrBuilder ExtResult; 1870 // Overflow occurred if it occurred in the larger type, or if the high part 1871 // of the result does not zero/sign-extend the low part. Check this second 1872 // possibility first. 1873 if (IsSigned) { 1874 // For signed, overflow occurred when the high part does not sign-extend 1875 // the low part. 1876 ExtResult = MIRBuilder.buildSExtInReg(WideTy, Mul, SrcBitWidth); 1877 } else { 1878 // Unsigned overflow occurred when the high part does not zero-extend the 1879 // low part. 1880 ExtResult = MIRBuilder.buildZExtInReg(WideTy, Mul, SrcBitWidth); 1881 } 1882 1883 // Multiplication cannot overflow if the WideTy is >= 2 * original width, 1884 // so we don't need to check the overflow result of larger type Mulo. 1885 if (WideTy.getScalarSizeInBits() < 2 * SrcBitWidth) { 1886 auto Overflow = 1887 MIRBuilder.buildICmp(CmpInst::ICMP_NE, OverflowTy, Mul, ExtResult); 1888 // Finally check if the multiplication in the larger type itself overflowed. 1889 MIRBuilder.buildOr(OriginalOverflow, Mulo->getOperand(1), Overflow); 1890 } else { 1891 MIRBuilder.buildICmp(CmpInst::ICMP_NE, OriginalOverflow, Mul, ExtResult); 1892 } 1893 MI.eraseFromParent(); 1894 return Legalized; 1895 } 1896 1897 LegalizerHelper::LegalizeResult 1898 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { 1899 switch (MI.getOpcode()) { 1900 default: 1901 return UnableToLegalize; 1902 case TargetOpcode::G_EXTRACT: 1903 return widenScalarExtract(MI, TypeIdx, WideTy); 1904 case TargetOpcode::G_INSERT: 1905 return widenScalarInsert(MI, TypeIdx, WideTy); 1906 case TargetOpcode::G_MERGE_VALUES: 1907 return widenScalarMergeValues(MI, TypeIdx, WideTy); 1908 case TargetOpcode::G_UNMERGE_VALUES: 1909 return widenScalarUnmergeValues(MI, TypeIdx, WideTy); 1910 case TargetOpcode::G_SADDO: 1911 case TargetOpcode::G_SSUBO: 1912 case TargetOpcode::G_UADDO: 1913 case TargetOpcode::G_USUBO: 1914 case TargetOpcode::G_SADDE: 1915 case TargetOpcode::G_SSUBE: 1916 case TargetOpcode::G_UADDE: 1917 case TargetOpcode::G_USUBE: 1918 return widenScalarAddSubOverflow(MI, TypeIdx, WideTy); 1919 case TargetOpcode::G_UMULO: 1920 case TargetOpcode::G_SMULO: 1921 return widenScalarMulo(MI, TypeIdx, WideTy); 1922 case TargetOpcode::G_SADDSAT: 1923 case TargetOpcode::G_SSUBSAT: 1924 case TargetOpcode::G_SSHLSAT: 1925 case TargetOpcode::G_UADDSAT: 1926 case TargetOpcode::G_USUBSAT: 1927 case TargetOpcode::G_USHLSAT: 1928 return widenScalarAddSubShlSat(MI, TypeIdx, WideTy); 1929 case TargetOpcode::G_CTTZ: 1930 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 1931 case TargetOpcode::G_CTLZ: 1932 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 1933 case TargetOpcode::G_CTPOP: { 1934 if (TypeIdx == 0) { 1935 Observer.changingInstr(MI); 1936 widenScalarDst(MI, WideTy, 0); 1937 Observer.changedInstr(MI); 1938 return Legalized; 1939 } 1940 1941 Register SrcReg = MI.getOperand(1).getReg(); 1942 1943 // First ZEXT the input. 1944 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg); 1945 LLT CurTy = MRI.getType(SrcReg); 1946 if (MI.getOpcode() == TargetOpcode::G_CTTZ) { 1947 // The count is the same in the larger type except if the original 1948 // value was zero. This can be handled by setting the bit just off 1949 // the top of the original type. 1950 auto TopBit = 1951 APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits()); 1952 MIBSrc = MIRBuilder.buildOr( 1953 WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit)); 1954 } 1955 1956 // Perform the operation at the larger size. 1957 auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc}); 1958 // This is already the correct result for CTPOP and CTTZs 1959 if (MI.getOpcode() == TargetOpcode::G_CTLZ || 1960 MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) { 1961 // The correct result is NewOp - (Difference in widety and current ty). 1962 unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits(); 1963 MIBNewOp = MIRBuilder.buildSub( 1964 WideTy, MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)); 1965 } 1966 1967 MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp); 1968 MI.eraseFromParent(); 1969 return Legalized; 1970 } 1971 case TargetOpcode::G_BSWAP: { 1972 Observer.changingInstr(MI); 1973 Register DstReg = MI.getOperand(0).getReg(); 1974 1975 Register ShrReg = MRI.createGenericVirtualRegister(WideTy); 1976 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1977 Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy); 1978 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1979 1980 MI.getOperand(0).setReg(DstExt); 1981 1982 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1983 1984 LLT Ty = MRI.getType(DstReg); 1985 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 1986 MIRBuilder.buildConstant(ShiftAmtReg, DiffBits); 1987 MIRBuilder.buildLShr(ShrReg, DstExt, ShiftAmtReg); 1988 1989 MIRBuilder.buildTrunc(DstReg, ShrReg); 1990 Observer.changedInstr(MI); 1991 return Legalized; 1992 } 1993 case TargetOpcode::G_BITREVERSE: { 1994 Observer.changingInstr(MI); 1995 1996 Register DstReg = MI.getOperand(0).getReg(); 1997 LLT Ty = MRI.getType(DstReg); 1998 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 1999 2000 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 2001 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2002 MI.getOperand(0).setReg(DstExt); 2003 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 2004 2005 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); 2006 auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt); 2007 MIRBuilder.buildTrunc(DstReg, Shift); 2008 Observer.changedInstr(MI); 2009 return Legalized; 2010 } 2011 case TargetOpcode::G_FREEZE: 2012 Observer.changingInstr(MI); 2013 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2014 widenScalarDst(MI, WideTy); 2015 Observer.changedInstr(MI); 2016 return Legalized; 2017 2018 case TargetOpcode::G_ADD: 2019 case TargetOpcode::G_AND: 2020 case TargetOpcode::G_MUL: 2021 case TargetOpcode::G_OR: 2022 case TargetOpcode::G_XOR: 2023 case TargetOpcode::G_SUB: 2024 // Perform operation at larger width (any extension is fines here, high bits 2025 // don't affect the result) and then truncate the result back to the 2026 // original type. 2027 Observer.changingInstr(MI); 2028 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2029 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2030 widenScalarDst(MI, WideTy); 2031 Observer.changedInstr(MI); 2032 return Legalized; 2033 2034 case TargetOpcode::G_SHL: 2035 Observer.changingInstr(MI); 2036 2037 if (TypeIdx == 0) { 2038 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2039 widenScalarDst(MI, WideTy); 2040 } else { 2041 assert(TypeIdx == 1); 2042 // The "number of bits to shift" operand must preserve its value as an 2043 // unsigned integer: 2044 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2045 } 2046 2047 Observer.changedInstr(MI); 2048 return Legalized; 2049 2050 case TargetOpcode::G_SDIV: 2051 case TargetOpcode::G_SREM: 2052 case TargetOpcode::G_SMIN: 2053 case TargetOpcode::G_SMAX: 2054 Observer.changingInstr(MI); 2055 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2056 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2057 widenScalarDst(MI, WideTy); 2058 Observer.changedInstr(MI); 2059 return Legalized; 2060 2061 case TargetOpcode::G_ASHR: 2062 case TargetOpcode::G_LSHR: 2063 Observer.changingInstr(MI); 2064 2065 if (TypeIdx == 0) { 2066 unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ? 2067 TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 2068 2069 widenScalarSrc(MI, WideTy, 1, CvtOp); 2070 widenScalarDst(MI, WideTy); 2071 } else { 2072 assert(TypeIdx == 1); 2073 // The "number of bits to shift" operand must preserve its value as an 2074 // unsigned integer: 2075 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2076 } 2077 2078 Observer.changedInstr(MI); 2079 return Legalized; 2080 case TargetOpcode::G_UDIV: 2081 case TargetOpcode::G_UREM: 2082 case TargetOpcode::G_UMIN: 2083 case TargetOpcode::G_UMAX: 2084 Observer.changingInstr(MI); 2085 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2086 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2087 widenScalarDst(MI, WideTy); 2088 Observer.changedInstr(MI); 2089 return Legalized; 2090 2091 case TargetOpcode::G_SELECT: 2092 Observer.changingInstr(MI); 2093 if (TypeIdx == 0) { 2094 // Perform operation at larger width (any extension is fine here, high 2095 // bits don't affect the result) and then truncate the result back to the 2096 // original type. 2097 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2098 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT); 2099 widenScalarDst(MI, WideTy); 2100 } else { 2101 bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector(); 2102 // Explicit extension is required here since high bits affect the result. 2103 widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false)); 2104 } 2105 Observer.changedInstr(MI); 2106 return Legalized; 2107 2108 case TargetOpcode::G_FPTOSI: 2109 case TargetOpcode::G_FPTOUI: 2110 Observer.changingInstr(MI); 2111 2112 if (TypeIdx == 0) 2113 widenScalarDst(MI, WideTy); 2114 else 2115 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2116 2117 Observer.changedInstr(MI); 2118 return Legalized; 2119 case TargetOpcode::G_SITOFP: 2120 Observer.changingInstr(MI); 2121 2122 if (TypeIdx == 0) 2123 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2124 else 2125 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2126 2127 Observer.changedInstr(MI); 2128 return Legalized; 2129 case TargetOpcode::G_UITOFP: 2130 Observer.changingInstr(MI); 2131 2132 if (TypeIdx == 0) 2133 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2134 else 2135 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2136 2137 Observer.changedInstr(MI); 2138 return Legalized; 2139 case TargetOpcode::G_LOAD: 2140 case TargetOpcode::G_SEXTLOAD: 2141 case TargetOpcode::G_ZEXTLOAD: 2142 Observer.changingInstr(MI); 2143 widenScalarDst(MI, WideTy); 2144 Observer.changedInstr(MI); 2145 return Legalized; 2146 2147 case TargetOpcode::G_STORE: { 2148 if (TypeIdx != 0) 2149 return UnableToLegalize; 2150 2151 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 2152 if (!Ty.isScalar()) 2153 return UnableToLegalize; 2154 2155 Observer.changingInstr(MI); 2156 2157 unsigned ExtType = Ty.getScalarSizeInBits() == 1 ? 2158 TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT; 2159 widenScalarSrc(MI, WideTy, 0, ExtType); 2160 2161 Observer.changedInstr(MI); 2162 return Legalized; 2163 } 2164 case TargetOpcode::G_CONSTANT: { 2165 MachineOperand &SrcMO = MI.getOperand(1); 2166 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2167 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( 2168 MRI.getType(MI.getOperand(0).getReg())); 2169 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || 2170 ExtOpc == TargetOpcode::G_ANYEXT) && 2171 "Illegal Extend"); 2172 const APInt &SrcVal = SrcMO.getCImm()->getValue(); 2173 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) 2174 ? SrcVal.sext(WideTy.getSizeInBits()) 2175 : SrcVal.zext(WideTy.getSizeInBits()); 2176 Observer.changingInstr(MI); 2177 SrcMO.setCImm(ConstantInt::get(Ctx, Val)); 2178 2179 widenScalarDst(MI, WideTy); 2180 Observer.changedInstr(MI); 2181 return Legalized; 2182 } 2183 case TargetOpcode::G_FCONSTANT: { 2184 MachineOperand &SrcMO = MI.getOperand(1); 2185 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2186 APFloat Val = SrcMO.getFPImm()->getValueAPF(); 2187 bool LosesInfo; 2188 switch (WideTy.getSizeInBits()) { 2189 case 32: 2190 Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, 2191 &LosesInfo); 2192 break; 2193 case 64: 2194 Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 2195 &LosesInfo); 2196 break; 2197 default: 2198 return UnableToLegalize; 2199 } 2200 2201 assert(!LosesInfo && "extend should always be lossless"); 2202 2203 Observer.changingInstr(MI); 2204 SrcMO.setFPImm(ConstantFP::get(Ctx, Val)); 2205 2206 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2207 Observer.changedInstr(MI); 2208 return Legalized; 2209 } 2210 case TargetOpcode::G_IMPLICIT_DEF: { 2211 Observer.changingInstr(MI); 2212 widenScalarDst(MI, WideTy); 2213 Observer.changedInstr(MI); 2214 return Legalized; 2215 } 2216 case TargetOpcode::G_BRCOND: 2217 Observer.changingInstr(MI); 2218 widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false)); 2219 Observer.changedInstr(MI); 2220 return Legalized; 2221 2222 case TargetOpcode::G_FCMP: 2223 Observer.changingInstr(MI); 2224 if (TypeIdx == 0) 2225 widenScalarDst(MI, WideTy); 2226 else { 2227 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT); 2228 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT); 2229 } 2230 Observer.changedInstr(MI); 2231 return Legalized; 2232 2233 case TargetOpcode::G_ICMP: 2234 Observer.changingInstr(MI); 2235 if (TypeIdx == 0) 2236 widenScalarDst(MI, WideTy); 2237 else { 2238 unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>( 2239 MI.getOperand(1).getPredicate())) 2240 ? TargetOpcode::G_SEXT 2241 : TargetOpcode::G_ZEXT; 2242 widenScalarSrc(MI, WideTy, 2, ExtOpcode); 2243 widenScalarSrc(MI, WideTy, 3, ExtOpcode); 2244 } 2245 Observer.changedInstr(MI); 2246 return Legalized; 2247 2248 case TargetOpcode::G_PTR_ADD: 2249 assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD"); 2250 Observer.changingInstr(MI); 2251 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2252 Observer.changedInstr(MI); 2253 return Legalized; 2254 2255 case TargetOpcode::G_PHI: { 2256 assert(TypeIdx == 0 && "Expecting only Idx 0"); 2257 2258 Observer.changingInstr(MI); 2259 for (unsigned I = 1; I < MI.getNumOperands(); I += 2) { 2260 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 2261 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 2262 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT); 2263 } 2264 2265 MachineBasicBlock &MBB = *MI.getParent(); 2266 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 2267 widenScalarDst(MI, WideTy); 2268 Observer.changedInstr(MI); 2269 return Legalized; 2270 } 2271 case TargetOpcode::G_EXTRACT_VECTOR_ELT: { 2272 if (TypeIdx == 0) { 2273 Register VecReg = MI.getOperand(1).getReg(); 2274 LLT VecTy = MRI.getType(VecReg); 2275 Observer.changingInstr(MI); 2276 2277 widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(), 2278 WideTy.getSizeInBits()), 2279 1, TargetOpcode::G_SEXT); 2280 2281 widenScalarDst(MI, WideTy, 0); 2282 Observer.changedInstr(MI); 2283 return Legalized; 2284 } 2285 2286 if (TypeIdx != 2) 2287 return UnableToLegalize; 2288 Observer.changingInstr(MI); 2289 // TODO: Probably should be zext 2290 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2291 Observer.changedInstr(MI); 2292 return Legalized; 2293 } 2294 case TargetOpcode::G_INSERT_VECTOR_ELT: { 2295 if (TypeIdx == 1) { 2296 Observer.changingInstr(MI); 2297 2298 Register VecReg = MI.getOperand(1).getReg(); 2299 LLT VecTy = MRI.getType(VecReg); 2300 LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy); 2301 2302 widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT); 2303 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2304 widenScalarDst(MI, WideVecTy, 0); 2305 Observer.changedInstr(MI); 2306 return Legalized; 2307 } 2308 2309 if (TypeIdx == 2) { 2310 Observer.changingInstr(MI); 2311 // TODO: Probably should be zext 2312 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT); 2313 Observer.changedInstr(MI); 2314 return Legalized; 2315 } 2316 2317 return UnableToLegalize; 2318 } 2319 case TargetOpcode::G_FADD: 2320 case TargetOpcode::G_FMUL: 2321 case TargetOpcode::G_FSUB: 2322 case TargetOpcode::G_FMA: 2323 case TargetOpcode::G_FMAD: 2324 case TargetOpcode::G_FNEG: 2325 case TargetOpcode::G_FABS: 2326 case TargetOpcode::G_FCANONICALIZE: 2327 case TargetOpcode::G_FMINNUM: 2328 case TargetOpcode::G_FMAXNUM: 2329 case TargetOpcode::G_FMINNUM_IEEE: 2330 case TargetOpcode::G_FMAXNUM_IEEE: 2331 case TargetOpcode::G_FMINIMUM: 2332 case TargetOpcode::G_FMAXIMUM: 2333 case TargetOpcode::G_FDIV: 2334 case TargetOpcode::G_FREM: 2335 case TargetOpcode::G_FCEIL: 2336 case TargetOpcode::G_FFLOOR: 2337 case TargetOpcode::G_FCOS: 2338 case TargetOpcode::G_FSIN: 2339 case TargetOpcode::G_FLOG10: 2340 case TargetOpcode::G_FLOG: 2341 case TargetOpcode::G_FLOG2: 2342 case TargetOpcode::G_FRINT: 2343 case TargetOpcode::G_FNEARBYINT: 2344 case TargetOpcode::G_FSQRT: 2345 case TargetOpcode::G_FEXP: 2346 case TargetOpcode::G_FEXP2: 2347 case TargetOpcode::G_FPOW: 2348 case TargetOpcode::G_INTRINSIC_TRUNC: 2349 case TargetOpcode::G_INTRINSIC_ROUND: 2350 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 2351 assert(TypeIdx == 0); 2352 Observer.changingInstr(MI); 2353 2354 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 2355 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT); 2356 2357 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2358 Observer.changedInstr(MI); 2359 return Legalized; 2360 case TargetOpcode::G_FPOWI: { 2361 if (TypeIdx != 0) 2362 return UnableToLegalize; 2363 Observer.changingInstr(MI); 2364 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2365 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2366 Observer.changedInstr(MI); 2367 return Legalized; 2368 } 2369 case TargetOpcode::G_INTTOPTR: 2370 if (TypeIdx != 1) 2371 return UnableToLegalize; 2372 2373 Observer.changingInstr(MI); 2374 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2375 Observer.changedInstr(MI); 2376 return Legalized; 2377 case TargetOpcode::G_PTRTOINT: 2378 if (TypeIdx != 0) 2379 return UnableToLegalize; 2380 2381 Observer.changingInstr(MI); 2382 widenScalarDst(MI, WideTy, 0); 2383 Observer.changedInstr(MI); 2384 return Legalized; 2385 case TargetOpcode::G_BUILD_VECTOR: { 2386 Observer.changingInstr(MI); 2387 2388 const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType(); 2389 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) 2390 widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT); 2391 2392 // Avoid changing the result vector type if the source element type was 2393 // requested. 2394 if (TypeIdx == 1) { 2395 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); 2396 } else { 2397 widenScalarDst(MI, WideTy, 0); 2398 } 2399 2400 Observer.changedInstr(MI); 2401 return Legalized; 2402 } 2403 case TargetOpcode::G_SEXT_INREG: 2404 if (TypeIdx != 0) 2405 return UnableToLegalize; 2406 2407 Observer.changingInstr(MI); 2408 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2409 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC); 2410 Observer.changedInstr(MI); 2411 return Legalized; 2412 case TargetOpcode::G_PTRMASK: { 2413 if (TypeIdx != 1) 2414 return UnableToLegalize; 2415 Observer.changingInstr(MI); 2416 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2417 Observer.changedInstr(MI); 2418 return Legalized; 2419 } 2420 } 2421 } 2422 2423 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces, 2424 MachineIRBuilder &B, Register Src, LLT Ty) { 2425 auto Unmerge = B.buildUnmerge(Ty, Src); 2426 for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I) 2427 Pieces.push_back(Unmerge.getReg(I)); 2428 } 2429 2430 LegalizerHelper::LegalizeResult 2431 LegalizerHelper::lowerBitcast(MachineInstr &MI) { 2432 Register Dst = MI.getOperand(0).getReg(); 2433 Register Src = MI.getOperand(1).getReg(); 2434 LLT DstTy = MRI.getType(Dst); 2435 LLT SrcTy = MRI.getType(Src); 2436 2437 if (SrcTy.isVector()) { 2438 LLT SrcEltTy = SrcTy.getElementType(); 2439 SmallVector<Register, 8> SrcRegs; 2440 2441 if (DstTy.isVector()) { 2442 int NumDstElt = DstTy.getNumElements(); 2443 int NumSrcElt = SrcTy.getNumElements(); 2444 2445 LLT DstEltTy = DstTy.getElementType(); 2446 LLT DstCastTy = DstEltTy; // Intermediate bitcast result type 2447 LLT SrcPartTy = SrcEltTy; // Original unmerge result type. 2448 2449 // If there's an element size mismatch, insert intermediate casts to match 2450 // the result element type. 2451 if (NumSrcElt < NumDstElt) { // Source element type is larger. 2452 // %1:_(<4 x s8>) = G_BITCAST %0:_(<2 x s16>) 2453 // 2454 // => 2455 // 2456 // %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0 2457 // %3:_(<2 x s8>) = G_BITCAST %2 2458 // %4:_(<2 x s8>) = G_BITCAST %3 2459 // %1:_(<4 x s16>) = G_CONCAT_VECTORS %3, %4 2460 DstCastTy = LLT::vector(NumDstElt / NumSrcElt, DstEltTy); 2461 SrcPartTy = SrcEltTy; 2462 } else if (NumSrcElt > NumDstElt) { // Source element type is smaller. 2463 // 2464 // %1:_(<2 x s16>) = G_BITCAST %0:_(<4 x s8>) 2465 // 2466 // => 2467 // 2468 // %2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %0 2469 // %3:_(s16) = G_BITCAST %2 2470 // %4:_(s16) = G_BITCAST %3 2471 // %1:_(<2 x s16>) = G_BUILD_VECTOR %3, %4 2472 SrcPartTy = LLT::vector(NumSrcElt / NumDstElt, SrcEltTy); 2473 DstCastTy = DstEltTy; 2474 } 2475 2476 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcPartTy); 2477 for (Register &SrcReg : SrcRegs) 2478 SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); 2479 } else 2480 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcEltTy); 2481 2482 MIRBuilder.buildMerge(Dst, SrcRegs); 2483 MI.eraseFromParent(); 2484 return Legalized; 2485 } 2486 2487 if (DstTy.isVector()) { 2488 SmallVector<Register, 8> SrcRegs; 2489 getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType()); 2490 MIRBuilder.buildMerge(Dst, SrcRegs); 2491 MI.eraseFromParent(); 2492 return Legalized; 2493 } 2494 2495 return UnableToLegalize; 2496 } 2497 2498 /// Figure out the bit offset into a register when coercing a vector index for 2499 /// the wide element type. This is only for the case when promoting vector to 2500 /// one with larger elements. 2501 // 2502 /// 2503 /// %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2504 /// %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2505 static Register getBitcastWiderVectorElementOffset(MachineIRBuilder &B, 2506 Register Idx, 2507 unsigned NewEltSize, 2508 unsigned OldEltSize) { 2509 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2510 LLT IdxTy = B.getMRI()->getType(Idx); 2511 2512 // Now figure out the amount we need to shift to get the target bits. 2513 auto OffsetMask = B.buildConstant( 2514 IdxTy, ~(APInt::getAllOnesValue(IdxTy.getSizeInBits()) << Log2EltRatio)); 2515 auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask); 2516 return B.buildShl(IdxTy, OffsetIdx, 2517 B.buildConstant(IdxTy, Log2_32(OldEltSize))).getReg(0); 2518 } 2519 2520 /// Perform a G_EXTRACT_VECTOR_ELT in a different sized vector element. If this 2521 /// is casting to a vector with a smaller element size, perform multiple element 2522 /// extracts and merge the results. If this is coercing to a vector with larger 2523 /// elements, index the bitcasted vector and extract the target element with bit 2524 /// operations. This is intended to force the indexing in the native register 2525 /// size for architectures that can dynamically index the register file. 2526 LegalizerHelper::LegalizeResult 2527 LegalizerHelper::bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx, 2528 LLT CastTy) { 2529 if (TypeIdx != 1) 2530 return UnableToLegalize; 2531 2532 Register Dst = MI.getOperand(0).getReg(); 2533 Register SrcVec = MI.getOperand(1).getReg(); 2534 Register Idx = MI.getOperand(2).getReg(); 2535 LLT SrcVecTy = MRI.getType(SrcVec); 2536 LLT IdxTy = MRI.getType(Idx); 2537 2538 LLT SrcEltTy = SrcVecTy.getElementType(); 2539 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2540 unsigned OldNumElts = SrcVecTy.getNumElements(); 2541 2542 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2543 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2544 2545 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2546 const unsigned OldEltSize = SrcEltTy.getSizeInBits(); 2547 if (NewNumElts > OldNumElts) { 2548 // Decreasing the vector element size 2549 // 2550 // e.g. i64 = extract_vector_elt x:v2i64, y:i32 2551 // => 2552 // v4i32:castx = bitcast x:v2i64 2553 // 2554 // i64 = bitcast 2555 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))), 2556 // (i32 (extract_vector_elt castx, (2 * y + 1))) 2557 // 2558 if (NewNumElts % OldNumElts != 0) 2559 return UnableToLegalize; 2560 2561 // Type of the intermediate result vector. 2562 const unsigned NewEltsPerOldElt = NewNumElts / OldNumElts; 2563 LLT MidTy = LLT::scalarOrVector(NewEltsPerOldElt, NewEltTy); 2564 2565 auto NewEltsPerOldEltK = MIRBuilder.buildConstant(IdxTy, NewEltsPerOldElt); 2566 2567 SmallVector<Register, 8> NewOps(NewEltsPerOldElt); 2568 auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, Idx, NewEltsPerOldEltK); 2569 2570 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) { 2571 auto IdxOffset = MIRBuilder.buildConstant(IdxTy, I); 2572 auto TmpIdx = MIRBuilder.buildAdd(IdxTy, NewBaseIdx, IdxOffset); 2573 auto Elt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, TmpIdx); 2574 NewOps[I] = Elt.getReg(0); 2575 } 2576 2577 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); 2578 MIRBuilder.buildBitcast(Dst, NewVec); 2579 MI.eraseFromParent(); 2580 return Legalized; 2581 } 2582 2583 if (NewNumElts < OldNumElts) { 2584 if (NewEltSize % OldEltSize != 0) 2585 return UnableToLegalize; 2586 2587 // This only depends on powers of 2 because we use bit tricks to figure out 2588 // the bit offset we need to shift to get the target element. A general 2589 // expansion could emit division/multiply. 2590 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2591 return UnableToLegalize; 2592 2593 // Increasing the vector element size. 2594 // %elt:_(small_elt) = G_EXTRACT_VECTOR_ELT %vec:_(<N x small_elt>), %idx 2595 // 2596 // => 2597 // 2598 // %cast = G_BITCAST %vec 2599 // %scaled_idx = G_LSHR %idx, Log2(DstEltSize / SrcEltSize) 2600 // %wide_elt = G_EXTRACT_VECTOR_ELT %cast, %scaled_idx 2601 // %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2602 // %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2603 // %elt_bits = G_LSHR %wide_elt, %offset_bits 2604 // %elt = G_TRUNC %elt_bits 2605 2606 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2607 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2608 2609 // Divide to get the index in the wider element type. 2610 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2611 2612 Register WideElt = CastVec; 2613 if (CastTy.isVector()) { 2614 WideElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2615 ScaledIdx).getReg(0); 2616 } 2617 2618 // Compute the bit offset into the register of the target element. 2619 Register OffsetBits = getBitcastWiderVectorElementOffset( 2620 MIRBuilder, Idx, NewEltSize, OldEltSize); 2621 2622 // Shift the wide element to get the target element. 2623 auto ExtractedBits = MIRBuilder.buildLShr(NewEltTy, WideElt, OffsetBits); 2624 MIRBuilder.buildTrunc(Dst, ExtractedBits); 2625 MI.eraseFromParent(); 2626 return Legalized; 2627 } 2628 2629 return UnableToLegalize; 2630 } 2631 2632 /// Emit code to insert \p InsertReg into \p TargetRet at \p OffsetBits in \p 2633 /// TargetReg, while preserving other bits in \p TargetReg. 2634 /// 2635 /// (InsertReg << Offset) | (TargetReg & ~(-1 >> InsertReg.size()) << Offset) 2636 static Register buildBitFieldInsert(MachineIRBuilder &B, 2637 Register TargetReg, Register InsertReg, 2638 Register OffsetBits) { 2639 LLT TargetTy = B.getMRI()->getType(TargetReg); 2640 LLT InsertTy = B.getMRI()->getType(InsertReg); 2641 auto ZextVal = B.buildZExt(TargetTy, InsertReg); 2642 auto ShiftedInsertVal = B.buildShl(TargetTy, ZextVal, OffsetBits); 2643 2644 // Produce a bitmask of the value to insert 2645 auto EltMask = B.buildConstant( 2646 TargetTy, APInt::getLowBitsSet(TargetTy.getSizeInBits(), 2647 InsertTy.getSizeInBits())); 2648 // Shift it into position 2649 auto ShiftedMask = B.buildShl(TargetTy, EltMask, OffsetBits); 2650 auto InvShiftedMask = B.buildNot(TargetTy, ShiftedMask); 2651 2652 // Clear out the bits in the wide element 2653 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); 2654 2655 // The value to insert has all zeros already, so stick it into the masked 2656 // wide element. 2657 return B.buildOr(TargetTy, MaskedOldElt, ShiftedInsertVal).getReg(0); 2658 } 2659 2660 /// Perform a G_INSERT_VECTOR_ELT in a different sized vector element. If this 2661 /// is increasing the element size, perform the indexing in the target element 2662 /// type, and use bit operations to insert at the element position. This is 2663 /// intended for architectures that can dynamically index the register file and 2664 /// want to force indexing in the native register size. 2665 LegalizerHelper::LegalizeResult 2666 LegalizerHelper::bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, 2667 LLT CastTy) { 2668 if (TypeIdx != 0) 2669 return UnableToLegalize; 2670 2671 Register Dst = MI.getOperand(0).getReg(); 2672 Register SrcVec = MI.getOperand(1).getReg(); 2673 Register Val = MI.getOperand(2).getReg(); 2674 Register Idx = MI.getOperand(3).getReg(); 2675 2676 LLT VecTy = MRI.getType(Dst); 2677 LLT IdxTy = MRI.getType(Idx); 2678 2679 LLT VecEltTy = VecTy.getElementType(); 2680 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2681 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2682 const unsigned OldEltSize = VecEltTy.getSizeInBits(); 2683 2684 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2685 unsigned OldNumElts = VecTy.getNumElements(); 2686 2687 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2688 if (NewNumElts < OldNumElts) { 2689 if (NewEltSize % OldEltSize != 0) 2690 return UnableToLegalize; 2691 2692 // This only depends on powers of 2 because we use bit tricks to figure out 2693 // the bit offset we need to shift to get the target element. A general 2694 // expansion could emit division/multiply. 2695 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2696 return UnableToLegalize; 2697 2698 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2699 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2700 2701 // Divide to get the index in the wider element type. 2702 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2703 2704 Register ExtractedElt = CastVec; 2705 if (CastTy.isVector()) { 2706 ExtractedElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2707 ScaledIdx).getReg(0); 2708 } 2709 2710 // Compute the bit offset into the register of the target element. 2711 Register OffsetBits = getBitcastWiderVectorElementOffset( 2712 MIRBuilder, Idx, NewEltSize, OldEltSize); 2713 2714 Register InsertedElt = buildBitFieldInsert(MIRBuilder, ExtractedElt, 2715 Val, OffsetBits); 2716 if (CastTy.isVector()) { 2717 InsertedElt = MIRBuilder.buildInsertVectorElement( 2718 CastTy, CastVec, InsertedElt, ScaledIdx).getReg(0); 2719 } 2720 2721 MIRBuilder.buildBitcast(Dst, InsertedElt); 2722 MI.eraseFromParent(); 2723 return Legalized; 2724 } 2725 2726 return UnableToLegalize; 2727 } 2728 2729 LegalizerHelper::LegalizeResult 2730 LegalizerHelper::lowerLoad(MachineInstr &MI) { 2731 // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT 2732 Register DstReg = MI.getOperand(0).getReg(); 2733 Register PtrReg = MI.getOperand(1).getReg(); 2734 LLT DstTy = MRI.getType(DstReg); 2735 auto &MMO = **MI.memoperands_begin(); 2736 2737 if (DstTy.getSizeInBits() == MMO.getSizeInBits()) { 2738 if (MI.getOpcode() == TargetOpcode::G_LOAD) { 2739 // This load needs splitting into power of 2 sized loads. 2740 if (DstTy.isVector()) 2741 return UnableToLegalize; 2742 if (isPowerOf2_32(DstTy.getSizeInBits())) 2743 return UnableToLegalize; // Don't know what we're being asked to do. 2744 2745 // Our strategy here is to generate anyextending loads for the smaller 2746 // types up to next power-2 result type, and then combine the two larger 2747 // result values together, before truncating back down to the non-pow-2 2748 // type. 2749 // E.g. v1 = i24 load => 2750 // v2 = i32 zextload (2 byte) 2751 // v3 = i32 load (1 byte) 2752 // v4 = i32 shl v3, 16 2753 // v5 = i32 or v4, v2 2754 // v1 = i24 trunc v5 2755 // By doing this we generate the correct truncate which should get 2756 // combined away as an artifact with a matching extend. 2757 uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits()); 2758 uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize; 2759 2760 MachineFunction &MF = MIRBuilder.getMF(); 2761 MachineMemOperand *LargeMMO = 2762 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2763 MachineMemOperand *SmallMMO = MF.getMachineMemOperand( 2764 &MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2765 2766 LLT PtrTy = MRI.getType(PtrReg); 2767 unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits()); 2768 LLT AnyExtTy = LLT::scalar(AnyExtSize); 2769 Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy); 2770 Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy); 2771 auto LargeLoad = MIRBuilder.buildLoadInstr( 2772 TargetOpcode::G_ZEXTLOAD, LargeLdReg, PtrReg, *LargeMMO); 2773 2774 auto OffsetCst = MIRBuilder.buildConstant( 2775 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2776 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2777 auto SmallPtr = 2778 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); 2779 auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0), 2780 *SmallMMO); 2781 2782 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize); 2783 auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt); 2784 auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad); 2785 MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)}); 2786 MI.eraseFromParent(); 2787 return Legalized; 2788 } 2789 2790 MIRBuilder.buildLoad(DstReg, PtrReg, MMO); 2791 MI.eraseFromParent(); 2792 return Legalized; 2793 } 2794 2795 if (DstTy.isScalar()) { 2796 Register TmpReg = 2797 MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits())); 2798 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); 2799 switch (MI.getOpcode()) { 2800 default: 2801 llvm_unreachable("Unexpected opcode"); 2802 case TargetOpcode::G_LOAD: 2803 MIRBuilder.buildAnyExtOrTrunc(DstReg, TmpReg); 2804 break; 2805 case TargetOpcode::G_SEXTLOAD: 2806 MIRBuilder.buildSExt(DstReg, TmpReg); 2807 break; 2808 case TargetOpcode::G_ZEXTLOAD: 2809 MIRBuilder.buildZExt(DstReg, TmpReg); 2810 break; 2811 } 2812 2813 MI.eraseFromParent(); 2814 return Legalized; 2815 } 2816 2817 return UnableToLegalize; 2818 } 2819 2820 LegalizerHelper::LegalizeResult 2821 LegalizerHelper::lowerStore(MachineInstr &MI) { 2822 // Lower a non-power of 2 store into multiple pow-2 stores. 2823 // E.g. split an i24 store into an i16 store + i8 store. 2824 // We do this by first extending the stored value to the next largest power 2825 // of 2 type, and then using truncating stores to store the components. 2826 // By doing this, likewise with G_LOAD, generate an extend that can be 2827 // artifact-combined away instead of leaving behind extracts. 2828 Register SrcReg = MI.getOperand(0).getReg(); 2829 Register PtrReg = MI.getOperand(1).getReg(); 2830 LLT SrcTy = MRI.getType(SrcReg); 2831 MachineMemOperand &MMO = **MI.memoperands_begin(); 2832 if (SrcTy.getSizeInBits() != MMO.getSizeInBits()) 2833 return UnableToLegalize; 2834 if (SrcTy.isVector()) 2835 return UnableToLegalize; 2836 if (isPowerOf2_32(SrcTy.getSizeInBits())) 2837 return UnableToLegalize; // Don't know what we're being asked to do. 2838 2839 // Extend to the next pow-2. 2840 const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits())); 2841 auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg); 2842 2843 // Obtain the smaller value by shifting away the larger value. 2844 uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits()); 2845 uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize; 2846 auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize); 2847 auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt); 2848 2849 // Generate the PtrAdd and truncating stores. 2850 LLT PtrTy = MRI.getType(PtrReg); 2851 auto OffsetCst = MIRBuilder.buildConstant( 2852 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2853 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2854 auto SmallPtr = 2855 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0)); 2856 2857 MachineFunction &MF = MIRBuilder.getMF(); 2858 MachineMemOperand *LargeMMO = 2859 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2860 MachineMemOperand *SmallMMO = 2861 MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2862 MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO); 2863 MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO); 2864 MI.eraseFromParent(); 2865 return Legalized; 2866 } 2867 2868 LegalizerHelper::LegalizeResult 2869 LegalizerHelper::bitcast(MachineInstr &MI, unsigned TypeIdx, LLT CastTy) { 2870 switch (MI.getOpcode()) { 2871 case TargetOpcode::G_LOAD: { 2872 if (TypeIdx != 0) 2873 return UnableToLegalize; 2874 2875 Observer.changingInstr(MI); 2876 bitcastDst(MI, CastTy, 0); 2877 Observer.changedInstr(MI); 2878 return Legalized; 2879 } 2880 case TargetOpcode::G_STORE: { 2881 if (TypeIdx != 0) 2882 return UnableToLegalize; 2883 2884 Observer.changingInstr(MI); 2885 bitcastSrc(MI, CastTy, 0); 2886 Observer.changedInstr(MI); 2887 return Legalized; 2888 } 2889 case TargetOpcode::G_SELECT: { 2890 if (TypeIdx != 0) 2891 return UnableToLegalize; 2892 2893 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) { 2894 LLVM_DEBUG( 2895 dbgs() << "bitcast action not implemented for vector select\n"); 2896 return UnableToLegalize; 2897 } 2898 2899 Observer.changingInstr(MI); 2900 bitcastSrc(MI, CastTy, 2); 2901 bitcastSrc(MI, CastTy, 3); 2902 bitcastDst(MI, CastTy, 0); 2903 Observer.changedInstr(MI); 2904 return Legalized; 2905 } 2906 case TargetOpcode::G_AND: 2907 case TargetOpcode::G_OR: 2908 case TargetOpcode::G_XOR: { 2909 Observer.changingInstr(MI); 2910 bitcastSrc(MI, CastTy, 1); 2911 bitcastSrc(MI, CastTy, 2); 2912 bitcastDst(MI, CastTy, 0); 2913 Observer.changedInstr(MI); 2914 return Legalized; 2915 } 2916 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 2917 return bitcastExtractVectorElt(MI, TypeIdx, CastTy); 2918 case TargetOpcode::G_INSERT_VECTOR_ELT: 2919 return bitcastInsertVectorElt(MI, TypeIdx, CastTy); 2920 default: 2921 return UnableToLegalize; 2922 } 2923 } 2924 2925 // Legalize an instruction by changing the opcode in place. 2926 void LegalizerHelper::changeOpcode(MachineInstr &MI, unsigned NewOpcode) { 2927 Observer.changingInstr(MI); 2928 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); 2929 Observer.changedInstr(MI); 2930 } 2931 2932 LegalizerHelper::LegalizeResult 2933 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) { 2934 using namespace TargetOpcode; 2935 2936 switch(MI.getOpcode()) { 2937 default: 2938 return UnableToLegalize; 2939 case TargetOpcode::G_BITCAST: 2940 return lowerBitcast(MI); 2941 case TargetOpcode::G_SREM: 2942 case TargetOpcode::G_UREM: { 2943 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 2944 auto Quot = 2945 MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {Ty}, 2946 {MI.getOperand(1), MI.getOperand(2)}); 2947 2948 auto Prod = MIRBuilder.buildMul(Ty, Quot, MI.getOperand(2)); 2949 MIRBuilder.buildSub(MI.getOperand(0), MI.getOperand(1), Prod); 2950 MI.eraseFromParent(); 2951 return Legalized; 2952 } 2953 case TargetOpcode::G_SADDO: 2954 case TargetOpcode::G_SSUBO: 2955 return lowerSADDO_SSUBO(MI); 2956 case TargetOpcode::G_UMULH: 2957 case TargetOpcode::G_SMULH: 2958 return lowerSMULH_UMULH(MI); 2959 case TargetOpcode::G_SMULO: 2960 case TargetOpcode::G_UMULO: { 2961 // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the 2962 // result. 2963 Register Res = MI.getOperand(0).getReg(); 2964 Register Overflow = MI.getOperand(1).getReg(); 2965 Register LHS = MI.getOperand(2).getReg(); 2966 Register RHS = MI.getOperand(3).getReg(); 2967 LLT Ty = MRI.getType(Res); 2968 2969 unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO 2970 ? TargetOpcode::G_SMULH 2971 : TargetOpcode::G_UMULH; 2972 2973 Observer.changingInstr(MI); 2974 const auto &TII = MIRBuilder.getTII(); 2975 MI.setDesc(TII.get(TargetOpcode::G_MUL)); 2976 MI.RemoveOperand(1); 2977 Observer.changedInstr(MI); 2978 2979 auto HiPart = MIRBuilder.buildInstr(Opcode, {Ty}, {LHS, RHS}); 2980 auto Zero = MIRBuilder.buildConstant(Ty, 0); 2981 2982 // Move insert point forward so we can use the Res register if needed. 2983 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 2984 2985 // For *signed* multiply, overflow is detected by checking: 2986 // (hi != (lo >> bitwidth-1)) 2987 if (Opcode == TargetOpcode::G_SMULH) { 2988 auto ShiftAmt = MIRBuilder.buildConstant(Ty, Ty.getSizeInBits() - 1); 2989 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); 2990 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted); 2991 } else { 2992 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero); 2993 } 2994 return Legalized; 2995 } 2996 case TargetOpcode::G_FNEG: { 2997 Register Res = MI.getOperand(0).getReg(); 2998 LLT Ty = MRI.getType(Res); 2999 3000 // TODO: Handle vector types once we are able to 3001 // represent them. 3002 if (Ty.isVector()) 3003 return UnableToLegalize; 3004 auto SignMask = 3005 MIRBuilder.buildConstant(Ty, APInt::getSignMask(Ty.getSizeInBits())); 3006 Register SubByReg = MI.getOperand(1).getReg(); 3007 MIRBuilder.buildXor(Res, SubByReg, SignMask); 3008 MI.eraseFromParent(); 3009 return Legalized; 3010 } 3011 case TargetOpcode::G_FSUB: { 3012 Register Res = MI.getOperand(0).getReg(); 3013 LLT Ty = MRI.getType(Res); 3014 3015 // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)). 3016 // First, check if G_FNEG is marked as Lower. If so, we may 3017 // end up with an infinite loop as G_FSUB is used to legalize G_FNEG. 3018 if (LI.getAction({G_FNEG, {Ty}}).Action == Lower) 3019 return UnableToLegalize; 3020 Register LHS = MI.getOperand(1).getReg(); 3021 Register RHS = MI.getOperand(2).getReg(); 3022 Register Neg = MRI.createGenericVirtualRegister(Ty); 3023 MIRBuilder.buildFNeg(Neg, RHS); 3024 MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags()); 3025 MI.eraseFromParent(); 3026 return Legalized; 3027 } 3028 case TargetOpcode::G_FMAD: 3029 return lowerFMad(MI); 3030 case TargetOpcode::G_FFLOOR: 3031 return lowerFFloor(MI); 3032 case TargetOpcode::G_INTRINSIC_ROUND: 3033 return lowerIntrinsicRound(MI); 3034 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 3035 // Since round even is the assumed rounding mode for unconstrained FP 3036 // operations, rint and roundeven are the same operation. 3037 changeOpcode(MI, TargetOpcode::G_FRINT); 3038 return Legalized; 3039 } 3040 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: { 3041 Register OldValRes = MI.getOperand(0).getReg(); 3042 Register SuccessRes = MI.getOperand(1).getReg(); 3043 Register Addr = MI.getOperand(2).getReg(); 3044 Register CmpVal = MI.getOperand(3).getReg(); 3045 Register NewVal = MI.getOperand(4).getReg(); 3046 MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal, 3047 **MI.memoperands_begin()); 3048 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal); 3049 MI.eraseFromParent(); 3050 return Legalized; 3051 } 3052 case TargetOpcode::G_LOAD: 3053 case TargetOpcode::G_SEXTLOAD: 3054 case TargetOpcode::G_ZEXTLOAD: 3055 return lowerLoad(MI); 3056 case TargetOpcode::G_STORE: 3057 return lowerStore(MI); 3058 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 3059 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 3060 case TargetOpcode::G_CTLZ: 3061 case TargetOpcode::G_CTTZ: 3062 case TargetOpcode::G_CTPOP: 3063 return lowerBitCount(MI); 3064 case G_UADDO: { 3065 Register Res = MI.getOperand(0).getReg(); 3066 Register CarryOut = MI.getOperand(1).getReg(); 3067 Register LHS = MI.getOperand(2).getReg(); 3068 Register RHS = MI.getOperand(3).getReg(); 3069 3070 MIRBuilder.buildAdd(Res, LHS, RHS); 3071 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS); 3072 3073 MI.eraseFromParent(); 3074 return Legalized; 3075 } 3076 case G_UADDE: { 3077 Register Res = MI.getOperand(0).getReg(); 3078 Register CarryOut = MI.getOperand(1).getReg(); 3079 Register LHS = MI.getOperand(2).getReg(); 3080 Register RHS = MI.getOperand(3).getReg(); 3081 Register CarryIn = MI.getOperand(4).getReg(); 3082 LLT Ty = MRI.getType(Res); 3083 3084 auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS); 3085 auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); 3086 MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn); 3087 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS); 3088 3089 MI.eraseFromParent(); 3090 return Legalized; 3091 } 3092 case G_USUBO: { 3093 Register Res = MI.getOperand(0).getReg(); 3094 Register BorrowOut = MI.getOperand(1).getReg(); 3095 Register LHS = MI.getOperand(2).getReg(); 3096 Register RHS = MI.getOperand(3).getReg(); 3097 3098 MIRBuilder.buildSub(Res, LHS, RHS); 3099 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS); 3100 3101 MI.eraseFromParent(); 3102 return Legalized; 3103 } 3104 case G_USUBE: { 3105 Register Res = MI.getOperand(0).getReg(); 3106 Register BorrowOut = MI.getOperand(1).getReg(); 3107 Register LHS = MI.getOperand(2).getReg(); 3108 Register RHS = MI.getOperand(3).getReg(); 3109 Register BorrowIn = MI.getOperand(4).getReg(); 3110 const LLT CondTy = MRI.getType(BorrowOut); 3111 const LLT Ty = MRI.getType(Res); 3112 3113 auto TmpRes = MIRBuilder.buildSub(Ty, LHS, RHS); 3114 auto ZExtBorrowIn = MIRBuilder.buildZExt(Ty, BorrowIn); 3115 MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn); 3116 3117 auto LHS_EQ_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, LHS, RHS); 3118 auto LHS_ULT_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, LHS, RHS); 3119 MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS); 3120 3121 MI.eraseFromParent(); 3122 return Legalized; 3123 } 3124 case G_UITOFP: 3125 return lowerUITOFP(MI); 3126 case G_SITOFP: 3127 return lowerSITOFP(MI); 3128 case G_FPTOUI: 3129 return lowerFPTOUI(MI); 3130 case G_FPTOSI: 3131 return lowerFPTOSI(MI); 3132 case G_FPTRUNC: 3133 return lowerFPTRUNC(MI); 3134 case G_FPOWI: 3135 return lowerFPOWI(MI); 3136 case G_SMIN: 3137 case G_SMAX: 3138 case G_UMIN: 3139 case G_UMAX: 3140 return lowerMinMax(MI); 3141 case G_FCOPYSIGN: 3142 return lowerFCopySign(MI); 3143 case G_FMINNUM: 3144 case G_FMAXNUM: 3145 return lowerFMinNumMaxNum(MI); 3146 case G_MERGE_VALUES: 3147 return lowerMergeValues(MI); 3148 case G_UNMERGE_VALUES: 3149 return lowerUnmergeValues(MI); 3150 case TargetOpcode::G_SEXT_INREG: { 3151 assert(MI.getOperand(2).isImm() && "Expected immediate"); 3152 int64_t SizeInBits = MI.getOperand(2).getImm(); 3153 3154 Register DstReg = MI.getOperand(0).getReg(); 3155 Register SrcReg = MI.getOperand(1).getReg(); 3156 LLT DstTy = MRI.getType(DstReg); 3157 Register TmpRes = MRI.createGenericVirtualRegister(DstTy); 3158 3159 auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits); 3160 MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0)); 3161 MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0)); 3162 MI.eraseFromParent(); 3163 return Legalized; 3164 } 3165 case G_EXTRACT_VECTOR_ELT: 3166 case G_INSERT_VECTOR_ELT: 3167 return lowerExtractInsertVectorElt(MI); 3168 case G_SHUFFLE_VECTOR: 3169 return lowerShuffleVector(MI); 3170 case G_DYN_STACKALLOC: 3171 return lowerDynStackAlloc(MI); 3172 case G_EXTRACT: 3173 return lowerExtract(MI); 3174 case G_INSERT: 3175 return lowerInsert(MI); 3176 case G_BSWAP: 3177 return lowerBswap(MI); 3178 case G_BITREVERSE: 3179 return lowerBitreverse(MI); 3180 case G_READ_REGISTER: 3181 case G_WRITE_REGISTER: 3182 return lowerReadWriteRegister(MI); 3183 case G_UADDSAT: 3184 case G_USUBSAT: { 3185 // Try to make a reasonable guess about which lowering strategy to use. The 3186 // target can override this with custom lowering and calling the 3187 // implementation functions. 3188 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3189 if (LI.isLegalOrCustom({G_UMIN, Ty})) 3190 return lowerAddSubSatToMinMax(MI); 3191 return lowerAddSubSatToAddoSubo(MI); 3192 } 3193 case G_SADDSAT: 3194 case G_SSUBSAT: { 3195 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3196 3197 // FIXME: It would probably make more sense to see if G_SADDO is preferred, 3198 // since it's a shorter expansion. However, we would need to figure out the 3199 // preferred boolean type for the carry out for the query. 3200 if (LI.isLegalOrCustom({G_SMIN, Ty}) && LI.isLegalOrCustom({G_SMAX, Ty})) 3201 return lowerAddSubSatToMinMax(MI); 3202 return lowerAddSubSatToAddoSubo(MI); 3203 } 3204 case G_SSHLSAT: 3205 case G_USHLSAT: 3206 return lowerShlSat(MI); 3207 case G_ABS: { 3208 // Expand %res = G_ABS %a into: 3209 // %v1 = G_ASHR %a, scalar_size-1 3210 // %v2 = G_ADD %a, %v1 3211 // %res = G_XOR %v2, %v1 3212 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 3213 Register OpReg = MI.getOperand(1).getReg(); 3214 auto ShiftAmt = 3215 MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - 1); 3216 auto Shift = 3217 MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt); 3218 auto Add = MIRBuilder.buildAdd(DstTy, OpReg, Shift); 3219 MIRBuilder.buildXor(MI.getOperand(0).getReg(), Add, Shift); 3220 MI.eraseFromParent(); 3221 return Legalized; 3222 } 3223 case G_SELECT: 3224 return lowerSelect(MI); 3225 case G_SDIVREM: 3226 case G_UDIVREM: 3227 return lowerDIVREM(MI); 3228 case G_FSHL: 3229 case G_FSHR: 3230 return lowerFunnelShift(MI); 3231 } 3232 } 3233 3234 Align LegalizerHelper::getStackTemporaryAlignment(LLT Ty, 3235 Align MinAlign) const { 3236 // FIXME: We're missing a way to go back from LLT to llvm::Type to query the 3237 // datalayout for the preferred alignment. Also there should be a target hook 3238 // for this to allow targets to reduce the alignment and ignore the 3239 // datalayout. e.g. AMDGPU should always use a 4-byte alignment, regardless of 3240 // the type. 3241 return std::max(Align(PowerOf2Ceil(Ty.getSizeInBytes())), MinAlign); 3242 } 3243 3244 MachineInstrBuilder 3245 LegalizerHelper::createStackTemporary(TypeSize Bytes, Align Alignment, 3246 MachinePointerInfo &PtrInfo) { 3247 MachineFunction &MF = MIRBuilder.getMF(); 3248 const DataLayout &DL = MIRBuilder.getDataLayout(); 3249 int FrameIdx = MF.getFrameInfo().CreateStackObject(Bytes, Alignment, false); 3250 3251 unsigned AddrSpace = DL.getAllocaAddrSpace(); 3252 LLT FramePtrTy = LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace)); 3253 3254 PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIdx); 3255 return MIRBuilder.buildFrameIndex(FramePtrTy, FrameIdx); 3256 } 3257 3258 static Register clampDynamicVectorIndex(MachineIRBuilder &B, Register IdxReg, 3259 LLT VecTy) { 3260 int64_t IdxVal; 3261 if (mi_match(IdxReg, *B.getMRI(), m_ICst(IdxVal))) 3262 return IdxReg; 3263 3264 LLT IdxTy = B.getMRI()->getType(IdxReg); 3265 unsigned NElts = VecTy.getNumElements(); 3266 if (isPowerOf2_32(NElts)) { 3267 APInt Imm = APInt::getLowBitsSet(IdxTy.getSizeInBits(), Log2_32(NElts)); 3268 return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0); 3269 } 3270 3271 return B.buildUMin(IdxTy, IdxReg, B.buildConstant(IdxTy, NElts - 1)) 3272 .getReg(0); 3273 } 3274 3275 Register LegalizerHelper::getVectorElementPointer(Register VecPtr, LLT VecTy, 3276 Register Index) { 3277 LLT EltTy = VecTy.getElementType(); 3278 3279 // Calculate the element offset and add it to the pointer. 3280 unsigned EltSize = EltTy.getSizeInBits() / 8; // FIXME: should be ABI size. 3281 assert(EltSize * 8 == EltTy.getSizeInBits() && 3282 "Converting bits to bytes lost precision"); 3283 3284 Index = clampDynamicVectorIndex(MIRBuilder, Index, VecTy); 3285 3286 LLT IdxTy = MRI.getType(Index); 3287 auto Mul = MIRBuilder.buildMul(IdxTy, Index, 3288 MIRBuilder.buildConstant(IdxTy, EltSize)); 3289 3290 LLT PtrTy = MRI.getType(VecPtr); 3291 return MIRBuilder.buildPtrAdd(PtrTy, VecPtr, Mul).getReg(0); 3292 } 3293 3294 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef( 3295 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) { 3296 Register DstReg = MI.getOperand(0).getReg(); 3297 LLT DstTy = MRI.getType(DstReg); 3298 LLT LCMTy = getLCMType(DstTy, NarrowTy); 3299 3300 unsigned NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 3301 3302 auto NewUndef = MIRBuilder.buildUndef(NarrowTy); 3303 SmallVector<Register, 8> Parts(NumParts, NewUndef.getReg(0)); 3304 3305 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3306 MI.eraseFromParent(); 3307 return Legalized; 3308 } 3309 3310 // Handle splitting vector operations which need to have the same number of 3311 // elements in each type index, but each type index may have a different element 3312 // type. 3313 // 3314 // e.g. <4 x s64> = G_SHL <4 x s64>, <4 x s32> -> 3315 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3316 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3317 // 3318 // Also handles some irregular breakdown cases, e.g. 3319 // e.g. <3 x s64> = G_SHL <3 x s64>, <3 x s32> -> 3320 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3321 // s64 = G_SHL s64, s32 3322 LegalizerHelper::LegalizeResult 3323 LegalizerHelper::fewerElementsVectorMultiEltType( 3324 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) { 3325 if (TypeIdx != 0) 3326 return UnableToLegalize; 3327 3328 const LLT NarrowTy0 = NarrowTyArg; 3329 const unsigned NewNumElts = 3330 NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1; 3331 3332 const Register DstReg = MI.getOperand(0).getReg(); 3333 LLT DstTy = MRI.getType(DstReg); 3334 LLT LeftoverTy0; 3335 3336 // All of the operands need to have the same number of elements, so if we can 3337 // determine a type breakdown for the result type, we can for all of the 3338 // source types. 3339 int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first; 3340 if (NumParts < 0) 3341 return UnableToLegalize; 3342 3343 SmallVector<MachineInstrBuilder, 4> NewInsts; 3344 3345 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3346 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3347 3348 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) { 3349 Register SrcReg = MI.getOperand(I).getReg(); 3350 LLT SrcTyI = MRI.getType(SrcReg); 3351 LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType()); 3352 LLT LeftoverTyI; 3353 3354 // Split this operand into the requested typed registers, and any leftover 3355 // required to reproduce the original type. 3356 if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs, 3357 LeftoverRegs)) 3358 return UnableToLegalize; 3359 3360 if (I == 1) { 3361 // For the first operand, create an instruction for each part and setup 3362 // the result. 3363 for (Register PartReg : PartRegs) { 3364 Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3365 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3366 .addDef(PartDstReg) 3367 .addUse(PartReg)); 3368 DstRegs.push_back(PartDstReg); 3369 } 3370 3371 for (Register LeftoverReg : LeftoverRegs) { 3372 Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0); 3373 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3374 .addDef(PartDstReg) 3375 .addUse(LeftoverReg)); 3376 LeftoverDstRegs.push_back(PartDstReg); 3377 } 3378 } else { 3379 assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size()); 3380 3381 // Add the newly created operand splits to the existing instructions. The 3382 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3383 // pieces. 3384 unsigned InstCount = 0; 3385 for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J) 3386 NewInsts[InstCount++].addUse(PartRegs[J]); 3387 for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J) 3388 NewInsts[InstCount++].addUse(LeftoverRegs[J]); 3389 } 3390 3391 PartRegs.clear(); 3392 LeftoverRegs.clear(); 3393 } 3394 3395 // Insert the newly built operations and rebuild the result register. 3396 for (auto &MIB : NewInsts) 3397 MIRBuilder.insertInstr(MIB); 3398 3399 insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs); 3400 3401 MI.eraseFromParent(); 3402 return Legalized; 3403 } 3404 3405 LegalizerHelper::LegalizeResult 3406 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx, 3407 LLT NarrowTy) { 3408 if (TypeIdx != 0) 3409 return UnableToLegalize; 3410 3411 Register DstReg = MI.getOperand(0).getReg(); 3412 Register SrcReg = MI.getOperand(1).getReg(); 3413 LLT DstTy = MRI.getType(DstReg); 3414 LLT SrcTy = MRI.getType(SrcReg); 3415 3416 LLT NarrowTy0 = NarrowTy; 3417 LLT NarrowTy1; 3418 unsigned NumParts; 3419 3420 if (NarrowTy.isVector()) { 3421 // Uneven breakdown not handled. 3422 NumParts = DstTy.getNumElements() / NarrowTy.getNumElements(); 3423 if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements()) 3424 return UnableToLegalize; 3425 3426 NarrowTy1 = LLT::vector(NarrowTy.getNumElements(), SrcTy.getElementType()); 3427 } else { 3428 NumParts = DstTy.getNumElements(); 3429 NarrowTy1 = SrcTy.getElementType(); 3430 } 3431 3432 SmallVector<Register, 4> SrcRegs, DstRegs; 3433 extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs); 3434 3435 for (unsigned I = 0; I < NumParts; ++I) { 3436 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3437 MachineInstr *NewInst = 3438 MIRBuilder.buildInstr(MI.getOpcode(), {DstReg}, {SrcRegs[I]}); 3439 3440 NewInst->setFlags(MI.getFlags()); 3441 DstRegs.push_back(DstReg); 3442 } 3443 3444 if (NarrowTy.isVector()) 3445 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3446 else 3447 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3448 3449 MI.eraseFromParent(); 3450 return Legalized; 3451 } 3452 3453 LegalizerHelper::LegalizeResult 3454 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx, 3455 LLT NarrowTy) { 3456 Register DstReg = MI.getOperand(0).getReg(); 3457 Register Src0Reg = MI.getOperand(2).getReg(); 3458 LLT DstTy = MRI.getType(DstReg); 3459 LLT SrcTy = MRI.getType(Src0Reg); 3460 3461 unsigned NumParts; 3462 LLT NarrowTy0, NarrowTy1; 3463 3464 if (TypeIdx == 0) { 3465 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3466 unsigned OldElts = DstTy.getNumElements(); 3467 3468 NarrowTy0 = NarrowTy; 3469 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements(); 3470 NarrowTy1 = NarrowTy.isVector() ? 3471 LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) : 3472 SrcTy.getElementType(); 3473 3474 } else { 3475 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3476 unsigned OldElts = SrcTy.getNumElements(); 3477 3478 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : 3479 NarrowTy.getNumElements(); 3480 NarrowTy0 = LLT::vector(NarrowTy.getNumElements(), 3481 DstTy.getScalarSizeInBits()); 3482 NarrowTy1 = NarrowTy; 3483 } 3484 3485 // FIXME: Don't know how to handle the situation where the small vectors 3486 // aren't all the same size yet. 3487 if (NarrowTy1.isVector() && 3488 NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements()) 3489 return UnableToLegalize; 3490 3491 CmpInst::Predicate Pred 3492 = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 3493 3494 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 3495 extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs); 3496 extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs); 3497 3498 for (unsigned I = 0; I < NumParts; ++I) { 3499 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3500 DstRegs.push_back(DstReg); 3501 3502 if (MI.getOpcode() == TargetOpcode::G_ICMP) 3503 MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3504 else { 3505 MachineInstr *NewCmp 3506 = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3507 NewCmp->setFlags(MI.getFlags()); 3508 } 3509 } 3510 3511 if (NarrowTy1.isVector()) 3512 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3513 else 3514 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3515 3516 MI.eraseFromParent(); 3517 return Legalized; 3518 } 3519 3520 LegalizerHelper::LegalizeResult 3521 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, 3522 LLT NarrowTy) { 3523 Register DstReg = MI.getOperand(0).getReg(); 3524 Register CondReg = MI.getOperand(1).getReg(); 3525 3526 unsigned NumParts = 0; 3527 LLT NarrowTy0, NarrowTy1; 3528 3529 LLT DstTy = MRI.getType(DstReg); 3530 LLT CondTy = MRI.getType(CondReg); 3531 unsigned Size = DstTy.getSizeInBits(); 3532 3533 assert(TypeIdx == 0 || CondTy.isVector()); 3534 3535 if (TypeIdx == 0) { 3536 NarrowTy0 = NarrowTy; 3537 NarrowTy1 = CondTy; 3538 3539 unsigned NarrowSize = NarrowTy0.getSizeInBits(); 3540 // FIXME: Don't know how to handle the situation where the small vectors 3541 // aren't all the same size yet. 3542 if (Size % NarrowSize != 0) 3543 return UnableToLegalize; 3544 3545 NumParts = Size / NarrowSize; 3546 3547 // Need to break down the condition type 3548 if (CondTy.isVector()) { 3549 if (CondTy.getNumElements() == NumParts) 3550 NarrowTy1 = CondTy.getElementType(); 3551 else 3552 NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts, 3553 CondTy.getScalarSizeInBits()); 3554 } 3555 } else { 3556 NumParts = CondTy.getNumElements(); 3557 if (NarrowTy.isVector()) { 3558 // TODO: Handle uneven breakdown. 3559 if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements()) 3560 return UnableToLegalize; 3561 3562 return UnableToLegalize; 3563 } else { 3564 NarrowTy0 = DstTy.getElementType(); 3565 NarrowTy1 = NarrowTy; 3566 } 3567 } 3568 3569 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs; 3570 if (CondTy.isVector()) 3571 extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs); 3572 3573 extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs); 3574 extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs); 3575 3576 for (unsigned i = 0; i < NumParts; ++i) { 3577 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3578 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg, 3579 Src1Regs[i], Src2Regs[i]); 3580 DstRegs.push_back(DstReg); 3581 } 3582 3583 if (NarrowTy0.isVector()) 3584 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3585 else 3586 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3587 3588 MI.eraseFromParent(); 3589 return Legalized; 3590 } 3591 3592 LegalizerHelper::LegalizeResult 3593 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 3594 LLT NarrowTy) { 3595 const Register DstReg = MI.getOperand(0).getReg(); 3596 LLT PhiTy = MRI.getType(DstReg); 3597 LLT LeftoverTy; 3598 3599 // All of the operands need to have the same number of elements, so if we can 3600 // determine a type breakdown for the result type, we can for all of the 3601 // source types. 3602 int NumParts, NumLeftover; 3603 std::tie(NumParts, NumLeftover) 3604 = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy); 3605 if (NumParts < 0) 3606 return UnableToLegalize; 3607 3608 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3609 SmallVector<MachineInstrBuilder, 4> NewInsts; 3610 3611 const int TotalNumParts = NumParts + NumLeftover; 3612 3613 // Insert the new phis in the result block first. 3614 for (int I = 0; I != TotalNumParts; ++I) { 3615 LLT Ty = I < NumParts ? NarrowTy : LeftoverTy; 3616 Register PartDstReg = MRI.createGenericVirtualRegister(Ty); 3617 NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI) 3618 .addDef(PartDstReg)); 3619 if (I < NumParts) 3620 DstRegs.push_back(PartDstReg); 3621 else 3622 LeftoverDstRegs.push_back(PartDstReg); 3623 } 3624 3625 MachineBasicBlock *MBB = MI.getParent(); 3626 MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI()); 3627 insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs); 3628 3629 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3630 3631 // Insert code to extract the incoming values in each predecessor block. 3632 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 3633 PartRegs.clear(); 3634 LeftoverRegs.clear(); 3635 3636 Register SrcReg = MI.getOperand(I).getReg(); 3637 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 3638 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 3639 3640 LLT Unused; 3641 if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs, 3642 LeftoverRegs)) 3643 return UnableToLegalize; 3644 3645 // Add the newly created operand splits to the existing instructions. The 3646 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3647 // pieces. 3648 for (int J = 0; J != TotalNumParts; ++J) { 3649 MachineInstrBuilder MIB = NewInsts[J]; 3650 MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]); 3651 MIB.addMBB(&OpMBB); 3652 } 3653 } 3654 3655 MI.eraseFromParent(); 3656 return Legalized; 3657 } 3658 3659 LegalizerHelper::LegalizeResult 3660 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI, 3661 unsigned TypeIdx, 3662 LLT NarrowTy) { 3663 if (TypeIdx != 1) 3664 return UnableToLegalize; 3665 3666 const int NumDst = MI.getNumOperands() - 1; 3667 const Register SrcReg = MI.getOperand(NumDst).getReg(); 3668 LLT SrcTy = MRI.getType(SrcReg); 3669 3670 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 3671 3672 // TODO: Create sequence of extracts. 3673 if (DstTy == NarrowTy) 3674 return UnableToLegalize; 3675 3676 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3677 if (DstTy == GCDTy) { 3678 // This would just be a copy of the same unmerge. 3679 // TODO: Create extracts, pad with undef and create intermediate merges. 3680 return UnableToLegalize; 3681 } 3682 3683 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 3684 const int NumUnmerge = Unmerge->getNumOperands() - 1; 3685 const int PartsPerUnmerge = NumDst / NumUnmerge; 3686 3687 for (int I = 0; I != NumUnmerge; ++I) { 3688 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 3689 3690 for (int J = 0; J != PartsPerUnmerge; ++J) 3691 MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg()); 3692 MIB.addUse(Unmerge.getReg(I)); 3693 } 3694 3695 MI.eraseFromParent(); 3696 return Legalized; 3697 } 3698 3699 LegalizerHelper::LegalizeResult 3700 LegalizerHelper::fewerElementsVectorMulo(MachineInstr &MI, unsigned TypeIdx, 3701 LLT NarrowTy) { 3702 Register Result = MI.getOperand(0).getReg(); 3703 Register Overflow = MI.getOperand(1).getReg(); 3704 Register LHS = MI.getOperand(2).getReg(); 3705 Register RHS = MI.getOperand(3).getReg(); 3706 3707 LLT SrcTy = MRI.getType(LHS); 3708 if (!SrcTy.isVector()) 3709 return UnableToLegalize; 3710 3711 LLT ElementType = SrcTy.getElementType(); 3712 LLT OverflowElementTy = MRI.getType(Overflow).getElementType(); 3713 const int NumResult = SrcTy.getNumElements(); 3714 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3715 3716 // Unmerge the operands to smaller parts of GCD type. 3717 auto UnmergeLHS = MIRBuilder.buildUnmerge(GCDTy, LHS); 3718 auto UnmergeRHS = MIRBuilder.buildUnmerge(GCDTy, RHS); 3719 3720 const int NumOps = UnmergeLHS->getNumOperands() - 1; 3721 const int PartsPerUnmerge = NumResult / NumOps; 3722 LLT OverflowTy = LLT::scalarOrVector(PartsPerUnmerge, OverflowElementTy); 3723 LLT ResultTy = LLT::scalarOrVector(PartsPerUnmerge, ElementType); 3724 3725 // Perform the operation over unmerged parts. 3726 SmallVector<Register, 8> ResultParts; 3727 SmallVector<Register, 8> OverflowParts; 3728 for (int I = 0; I != NumOps; ++I) { 3729 Register Operand1 = UnmergeLHS->getOperand(I).getReg(); 3730 Register Operand2 = UnmergeRHS->getOperand(I).getReg(); 3731 auto PartMul = MIRBuilder.buildInstr(MI.getOpcode(), {ResultTy, OverflowTy}, 3732 {Operand1, Operand2}); 3733 ResultParts.push_back(PartMul->getOperand(0).getReg()); 3734 OverflowParts.push_back(PartMul->getOperand(1).getReg()); 3735 } 3736 3737 LLT ResultLCMTy = buildLCMMergePieces(SrcTy, NarrowTy, GCDTy, ResultParts); 3738 LLT OverflowLCMTy = 3739 LLT::scalarOrVector(ResultLCMTy.getNumElements(), OverflowElementTy); 3740 3741 // Recombine the pieces to the original result and overflow registers. 3742 buildWidenedRemergeToDst(Result, ResultLCMTy, ResultParts); 3743 buildWidenedRemergeToDst(Overflow, OverflowLCMTy, OverflowParts); 3744 MI.eraseFromParent(); 3745 return Legalized; 3746 } 3747 3748 // Handle FewerElementsVector a G_BUILD_VECTOR or G_CONCAT_VECTORS that produces 3749 // a vector 3750 // 3751 // Create a G_BUILD_VECTOR or G_CONCAT_VECTORS of NarrowTy pieces, padding with 3752 // undef as necessary. 3753 // 3754 // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2 3755 // -> <2 x s16> 3756 // 3757 // %4:_(s16) = G_IMPLICIT_DEF 3758 // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1 3759 // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4 3760 // %7:_(<2 x s16>) = G_IMPLICIT_DEF 3761 // %8:_(<6 x s16>) = G_CONCAT_VECTORS %5, %6, %7 3762 // %3:_(<3 x s16>), %8:_(<3 x s16>) = G_UNMERGE_VALUES %8 3763 LegalizerHelper::LegalizeResult 3764 LegalizerHelper::fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx, 3765 LLT NarrowTy) { 3766 Register DstReg = MI.getOperand(0).getReg(); 3767 LLT DstTy = MRI.getType(DstReg); 3768 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 3769 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 3770 3771 // Break into a common type 3772 SmallVector<Register, 16> Parts; 3773 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 3774 extractGCDType(Parts, GCDTy, MI.getOperand(I).getReg()); 3775 3776 // Build the requested new merge, padding with undef. 3777 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, 3778 TargetOpcode::G_ANYEXT); 3779 3780 // Pack into the original result register. 3781 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3782 3783 MI.eraseFromParent(); 3784 return Legalized; 3785 } 3786 3787 LegalizerHelper::LegalizeResult 3788 LegalizerHelper::fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI, 3789 unsigned TypeIdx, 3790 LLT NarrowVecTy) { 3791 Register DstReg = MI.getOperand(0).getReg(); 3792 Register SrcVec = MI.getOperand(1).getReg(); 3793 Register InsertVal; 3794 bool IsInsert = MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT; 3795 3796 assert((IsInsert ? TypeIdx == 0 : TypeIdx == 1) && "not a vector type index"); 3797 if (IsInsert) 3798 InsertVal = MI.getOperand(2).getReg(); 3799 3800 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 3801 3802 // TODO: Handle total scalarization case. 3803 if (!NarrowVecTy.isVector()) 3804 return UnableToLegalize; 3805 3806 LLT VecTy = MRI.getType(SrcVec); 3807 3808 // If the index is a constant, we can really break this down as you would 3809 // expect, and index into the target size pieces. 3810 int64_t IdxVal; 3811 if (mi_match(Idx, MRI, m_ICst(IdxVal))) { 3812 // Avoid out of bounds indexing the pieces. 3813 if (IdxVal >= VecTy.getNumElements()) { 3814 MIRBuilder.buildUndef(DstReg); 3815 MI.eraseFromParent(); 3816 return Legalized; 3817 } 3818 3819 SmallVector<Register, 8> VecParts; 3820 LLT GCDTy = extractGCDType(VecParts, VecTy, NarrowVecTy, SrcVec); 3821 3822 // Build a sequence of NarrowTy pieces in VecParts for this operand. 3823 LLT LCMTy = buildLCMMergePieces(VecTy, NarrowVecTy, GCDTy, VecParts, 3824 TargetOpcode::G_ANYEXT); 3825 3826 unsigned NewNumElts = NarrowVecTy.getNumElements(); 3827 3828 LLT IdxTy = MRI.getType(Idx); 3829 int64_t PartIdx = IdxVal / NewNumElts; 3830 auto NewIdx = 3831 MIRBuilder.buildConstant(IdxTy, IdxVal - NewNumElts * PartIdx); 3832 3833 if (IsInsert) { 3834 LLT PartTy = MRI.getType(VecParts[PartIdx]); 3835 3836 // Use the adjusted index to insert into one of the subvectors. 3837 auto InsertPart = MIRBuilder.buildInsertVectorElement( 3838 PartTy, VecParts[PartIdx], InsertVal, NewIdx); 3839 VecParts[PartIdx] = InsertPart.getReg(0); 3840 3841 // Recombine the inserted subvector with the others to reform the result 3842 // vector. 3843 buildWidenedRemergeToDst(DstReg, LCMTy, VecParts); 3844 } else { 3845 MIRBuilder.buildExtractVectorElement(DstReg, VecParts[PartIdx], NewIdx); 3846 } 3847 3848 MI.eraseFromParent(); 3849 return Legalized; 3850 } 3851 3852 // With a variable index, we can't perform the operation in a smaller type, so 3853 // we're forced to expand this. 3854 // 3855 // TODO: We could emit a chain of compare/select to figure out which piece to 3856 // index. 3857 return lowerExtractInsertVectorElt(MI); 3858 } 3859 3860 LegalizerHelper::LegalizeResult 3861 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx, 3862 LLT NarrowTy) { 3863 // FIXME: Don't know how to handle secondary types yet. 3864 if (TypeIdx != 0) 3865 return UnableToLegalize; 3866 3867 MachineMemOperand *MMO = *MI.memoperands_begin(); 3868 3869 // This implementation doesn't work for atomics. Give up instead of doing 3870 // something invalid. 3871 if (MMO->getOrdering() != AtomicOrdering::NotAtomic || 3872 MMO->getFailureOrdering() != AtomicOrdering::NotAtomic) 3873 return UnableToLegalize; 3874 3875 bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD; 3876 Register ValReg = MI.getOperand(0).getReg(); 3877 Register AddrReg = MI.getOperand(1).getReg(); 3878 LLT ValTy = MRI.getType(ValReg); 3879 3880 // FIXME: Do we need a distinct NarrowMemory legalize action? 3881 if (ValTy.getSizeInBits() != 8 * MMO->getSize()) { 3882 LLVM_DEBUG(dbgs() << "Can't narrow extload/truncstore\n"); 3883 return UnableToLegalize; 3884 } 3885 3886 int NumParts = -1; 3887 int NumLeftover = -1; 3888 LLT LeftoverTy; 3889 SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs; 3890 if (IsLoad) { 3891 std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy); 3892 } else { 3893 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, 3894 NarrowLeftoverRegs)) { 3895 NumParts = NarrowRegs.size(); 3896 NumLeftover = NarrowLeftoverRegs.size(); 3897 } 3898 } 3899 3900 if (NumParts == -1) 3901 return UnableToLegalize; 3902 3903 LLT PtrTy = MRI.getType(AddrReg); 3904 const LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits()); 3905 3906 unsigned TotalSize = ValTy.getSizeInBits(); 3907 3908 // Split the load/store into PartTy sized pieces starting at Offset. If this 3909 // is a load, return the new registers in ValRegs. For a store, each elements 3910 // of ValRegs should be PartTy. Returns the next offset that needs to be 3911 // handled. 3912 auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs, 3913 unsigned Offset) -> unsigned { 3914 MachineFunction &MF = MIRBuilder.getMF(); 3915 unsigned PartSize = PartTy.getSizeInBits(); 3916 for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize; 3917 Offset += PartSize, ++Idx) { 3918 unsigned ByteSize = PartSize / 8; 3919 unsigned ByteOffset = Offset / 8; 3920 Register NewAddrReg; 3921 3922 MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset); 3923 3924 MachineMemOperand *NewMMO = 3925 MF.getMachineMemOperand(MMO, ByteOffset, ByteSize); 3926 3927 if (IsLoad) { 3928 Register Dst = MRI.createGenericVirtualRegister(PartTy); 3929 ValRegs.push_back(Dst); 3930 MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO); 3931 } else { 3932 MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO); 3933 } 3934 } 3935 3936 return Offset; 3937 }; 3938 3939 unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0); 3940 3941 // Handle the rest of the register if this isn't an even type breakdown. 3942 if (LeftoverTy.isValid()) 3943 splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset); 3944 3945 if (IsLoad) { 3946 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, 3947 LeftoverTy, NarrowLeftoverRegs); 3948 } 3949 3950 MI.eraseFromParent(); 3951 return Legalized; 3952 } 3953 3954 LegalizerHelper::LegalizeResult 3955 LegalizerHelper::reduceOperationWidth(MachineInstr &MI, unsigned int TypeIdx, 3956 LLT NarrowTy) { 3957 assert(TypeIdx == 0 && "only one type index expected"); 3958 3959 const unsigned Opc = MI.getOpcode(); 3960 const int NumOps = MI.getNumOperands() - 1; 3961 const Register DstReg = MI.getOperand(0).getReg(); 3962 const unsigned Flags = MI.getFlags(); 3963 const unsigned NarrowSize = NarrowTy.getSizeInBits(); 3964 const LLT NarrowScalarTy = LLT::scalar(NarrowSize); 3965 3966 assert(NumOps <= 3 && "expected instruction with 1 result and 1-3 sources"); 3967 3968 // First of all check whether we are narrowing (changing the element type) 3969 // or reducing the vector elements 3970 const LLT DstTy = MRI.getType(DstReg); 3971 const bool IsNarrow = NarrowTy.getScalarType() != DstTy.getScalarType(); 3972 3973 SmallVector<Register, 8> ExtractedRegs[3]; 3974 SmallVector<Register, 8> Parts; 3975 3976 unsigned NarrowElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3977 3978 // Break down all the sources into NarrowTy pieces we can operate on. This may 3979 // involve creating merges to a wider type, padded with undef. 3980 for (int I = 0; I != NumOps; ++I) { 3981 Register SrcReg = MI.getOperand(I + 1).getReg(); 3982 LLT SrcTy = MRI.getType(SrcReg); 3983 3984 // The type to narrow SrcReg to. For narrowing, this is a smaller scalar. 3985 // For fewerElements, this is a smaller vector with the same element type. 3986 LLT OpNarrowTy; 3987 if (IsNarrow) { 3988 OpNarrowTy = NarrowScalarTy; 3989 3990 // In case of narrowing, we need to cast vectors to scalars for this to 3991 // work properly 3992 // FIXME: Can we do without the bitcast here if we're narrowing? 3993 if (SrcTy.isVector()) { 3994 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 3995 SrcReg = MIRBuilder.buildBitcast(SrcTy, SrcReg).getReg(0); 3996 } 3997 } else { 3998 OpNarrowTy = LLT::scalarOrVector(NarrowElts, SrcTy.getScalarType()); 3999 } 4000 4001 LLT GCDTy = extractGCDType(ExtractedRegs[I], SrcTy, OpNarrowTy, SrcReg); 4002 4003 // Build a sequence of NarrowTy pieces in ExtractedRegs for this operand. 4004 buildLCMMergePieces(SrcTy, OpNarrowTy, GCDTy, ExtractedRegs[I], 4005 TargetOpcode::G_ANYEXT); 4006 } 4007 4008 SmallVector<Register, 8> ResultRegs; 4009 4010 // Input operands for each sub-instruction. 4011 SmallVector<SrcOp, 4> InputRegs(NumOps, Register()); 4012 4013 int NumParts = ExtractedRegs[0].size(); 4014 const unsigned DstSize = DstTy.getSizeInBits(); 4015 const LLT DstScalarTy = LLT::scalar(DstSize); 4016 4017 // Narrowing needs to use scalar types 4018 LLT DstLCMTy, NarrowDstTy; 4019 if (IsNarrow) { 4020 DstLCMTy = getLCMType(DstScalarTy, NarrowScalarTy); 4021 NarrowDstTy = NarrowScalarTy; 4022 } else { 4023 DstLCMTy = getLCMType(DstTy, NarrowTy); 4024 NarrowDstTy = NarrowTy; 4025 } 4026 4027 // We widened the source registers to satisfy merge/unmerge size 4028 // constraints. We'll have some extra fully undef parts. 4029 const int NumRealParts = (DstSize + NarrowSize - 1) / NarrowSize; 4030 4031 for (int I = 0; I != NumRealParts; ++I) { 4032 // Emit this instruction on each of the split pieces. 4033 for (int J = 0; J != NumOps; ++J) 4034 InputRegs[J] = ExtractedRegs[J][I]; 4035 4036 auto Inst = MIRBuilder.buildInstr(Opc, {NarrowDstTy}, InputRegs, Flags); 4037 ResultRegs.push_back(Inst.getReg(0)); 4038 } 4039 4040 // Fill out the widened result with undef instead of creating instructions 4041 // with undef inputs. 4042 int NumUndefParts = NumParts - NumRealParts; 4043 if (NumUndefParts != 0) 4044 ResultRegs.append(NumUndefParts, 4045 MIRBuilder.buildUndef(NarrowDstTy).getReg(0)); 4046 4047 // Extract the possibly padded result. Use a scratch register if we need to do 4048 // a final bitcast, otherwise use the original result register. 4049 Register MergeDstReg; 4050 if (IsNarrow && DstTy.isVector()) 4051 MergeDstReg = MRI.createGenericVirtualRegister(DstScalarTy); 4052 else 4053 MergeDstReg = DstReg; 4054 4055 buildWidenedRemergeToDst(MergeDstReg, DstLCMTy, ResultRegs); 4056 4057 // Recast to vector if we narrowed a vector 4058 if (IsNarrow && DstTy.isVector()) 4059 MIRBuilder.buildBitcast(DstReg, MergeDstReg); 4060 4061 MI.eraseFromParent(); 4062 return Legalized; 4063 } 4064 4065 LegalizerHelper::LegalizeResult 4066 LegalizerHelper::fewerElementsVectorSextInReg(MachineInstr &MI, unsigned TypeIdx, 4067 LLT NarrowTy) { 4068 Register DstReg = MI.getOperand(0).getReg(); 4069 Register SrcReg = MI.getOperand(1).getReg(); 4070 int64_t Imm = MI.getOperand(2).getImm(); 4071 4072 LLT DstTy = MRI.getType(DstReg); 4073 4074 SmallVector<Register, 8> Parts; 4075 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 4076 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts); 4077 4078 for (Register &R : Parts) 4079 R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0); 4080 4081 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 4082 4083 MI.eraseFromParent(); 4084 return Legalized; 4085 } 4086 4087 LegalizerHelper::LegalizeResult 4088 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, 4089 LLT NarrowTy) { 4090 using namespace TargetOpcode; 4091 4092 switch (MI.getOpcode()) { 4093 case G_IMPLICIT_DEF: 4094 return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy); 4095 case G_TRUNC: 4096 case G_AND: 4097 case G_OR: 4098 case G_XOR: 4099 case G_ADD: 4100 case G_SUB: 4101 case G_MUL: 4102 case G_PTR_ADD: 4103 case G_SMULH: 4104 case G_UMULH: 4105 case G_FADD: 4106 case G_FMUL: 4107 case G_FSUB: 4108 case G_FNEG: 4109 case G_FABS: 4110 case G_FCANONICALIZE: 4111 case G_FDIV: 4112 case G_FREM: 4113 case G_FMA: 4114 case G_FMAD: 4115 case G_FPOW: 4116 case G_FEXP: 4117 case G_FEXP2: 4118 case G_FLOG: 4119 case G_FLOG2: 4120 case G_FLOG10: 4121 case G_FNEARBYINT: 4122 case G_FCEIL: 4123 case G_FFLOOR: 4124 case G_FRINT: 4125 case G_INTRINSIC_ROUND: 4126 case G_INTRINSIC_ROUNDEVEN: 4127 case G_INTRINSIC_TRUNC: 4128 case G_FCOS: 4129 case G_FSIN: 4130 case G_FSQRT: 4131 case G_BSWAP: 4132 case G_BITREVERSE: 4133 case G_SDIV: 4134 case G_UDIV: 4135 case G_SREM: 4136 case G_UREM: 4137 case G_SMIN: 4138 case G_SMAX: 4139 case G_UMIN: 4140 case G_UMAX: 4141 case G_FMINNUM: 4142 case G_FMAXNUM: 4143 case G_FMINNUM_IEEE: 4144 case G_FMAXNUM_IEEE: 4145 case G_FMINIMUM: 4146 case G_FMAXIMUM: 4147 case G_FSHL: 4148 case G_FSHR: 4149 case G_FREEZE: 4150 case G_SADDSAT: 4151 case G_SSUBSAT: 4152 case G_UADDSAT: 4153 case G_USUBSAT: 4154 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 4155 case G_UMULO: 4156 case G_SMULO: 4157 return fewerElementsVectorMulo(MI, TypeIdx, NarrowTy); 4158 case G_SHL: 4159 case G_LSHR: 4160 case G_ASHR: 4161 case G_SSHLSAT: 4162 case G_USHLSAT: 4163 case G_CTLZ: 4164 case G_CTLZ_ZERO_UNDEF: 4165 case G_CTTZ: 4166 case G_CTTZ_ZERO_UNDEF: 4167 case G_CTPOP: 4168 case G_FCOPYSIGN: 4169 return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy); 4170 case G_ZEXT: 4171 case G_SEXT: 4172 case G_ANYEXT: 4173 case G_FPEXT: 4174 case G_FPTRUNC: 4175 case G_SITOFP: 4176 case G_UITOFP: 4177 case G_FPTOSI: 4178 case G_FPTOUI: 4179 case G_INTTOPTR: 4180 case G_PTRTOINT: 4181 case G_ADDRSPACE_CAST: 4182 return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy); 4183 case G_ICMP: 4184 case G_FCMP: 4185 return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy); 4186 case G_SELECT: 4187 return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy); 4188 case G_PHI: 4189 return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy); 4190 case G_UNMERGE_VALUES: 4191 return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy); 4192 case G_BUILD_VECTOR: 4193 assert(TypeIdx == 0 && "not a vector type index"); 4194 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4195 case G_CONCAT_VECTORS: 4196 if (TypeIdx != 1) // TODO: This probably does work as expected already. 4197 return UnableToLegalize; 4198 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4199 case G_EXTRACT_VECTOR_ELT: 4200 case G_INSERT_VECTOR_ELT: 4201 return fewerElementsVectorExtractInsertVectorElt(MI, TypeIdx, NarrowTy); 4202 case G_LOAD: 4203 case G_STORE: 4204 return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy); 4205 case G_SEXT_INREG: 4206 return fewerElementsVectorSextInReg(MI, TypeIdx, NarrowTy); 4207 default: 4208 return UnableToLegalize; 4209 } 4210 } 4211 4212 LegalizerHelper::LegalizeResult 4213 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt, 4214 const LLT HalfTy, const LLT AmtTy) { 4215 4216 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4217 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4218 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4219 4220 if (Amt.isNullValue()) { 4221 MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH}); 4222 MI.eraseFromParent(); 4223 return Legalized; 4224 } 4225 4226 LLT NVT = HalfTy; 4227 unsigned NVTBits = HalfTy.getSizeInBits(); 4228 unsigned VTBits = 2 * NVTBits; 4229 4230 SrcOp Lo(Register(0)), Hi(Register(0)); 4231 if (MI.getOpcode() == TargetOpcode::G_SHL) { 4232 if (Amt.ugt(VTBits)) { 4233 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4234 } else if (Amt.ugt(NVTBits)) { 4235 Lo = MIRBuilder.buildConstant(NVT, 0); 4236 Hi = MIRBuilder.buildShl(NVT, InL, 4237 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4238 } else if (Amt == NVTBits) { 4239 Lo = MIRBuilder.buildConstant(NVT, 0); 4240 Hi = InL; 4241 } else { 4242 Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt)); 4243 auto OrLHS = 4244 MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt)); 4245 auto OrRHS = MIRBuilder.buildLShr( 4246 NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4247 Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4248 } 4249 } else if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4250 if (Amt.ugt(VTBits)) { 4251 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4252 } else if (Amt.ugt(NVTBits)) { 4253 Lo = MIRBuilder.buildLShr(NVT, InH, 4254 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4255 Hi = MIRBuilder.buildConstant(NVT, 0); 4256 } else if (Amt == NVTBits) { 4257 Lo = InH; 4258 Hi = MIRBuilder.buildConstant(NVT, 0); 4259 } else { 4260 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4261 4262 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4263 auto OrRHS = MIRBuilder.buildShl( 4264 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4265 4266 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4267 Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst); 4268 } 4269 } else { 4270 if (Amt.ugt(VTBits)) { 4271 Hi = Lo = MIRBuilder.buildAShr( 4272 NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4273 } else if (Amt.ugt(NVTBits)) { 4274 Lo = MIRBuilder.buildAShr(NVT, InH, 4275 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4276 Hi = MIRBuilder.buildAShr(NVT, InH, 4277 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4278 } else if (Amt == NVTBits) { 4279 Lo = InH; 4280 Hi = MIRBuilder.buildAShr(NVT, InH, 4281 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4282 } else { 4283 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4284 4285 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4286 auto OrRHS = MIRBuilder.buildShl( 4287 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4288 4289 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4290 Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst); 4291 } 4292 } 4293 4294 MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi}); 4295 MI.eraseFromParent(); 4296 4297 return Legalized; 4298 } 4299 4300 // TODO: Optimize if constant shift amount. 4301 LegalizerHelper::LegalizeResult 4302 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, 4303 LLT RequestedTy) { 4304 if (TypeIdx == 1) { 4305 Observer.changingInstr(MI); 4306 narrowScalarSrc(MI, RequestedTy, 2); 4307 Observer.changedInstr(MI); 4308 return Legalized; 4309 } 4310 4311 Register DstReg = MI.getOperand(0).getReg(); 4312 LLT DstTy = MRI.getType(DstReg); 4313 if (DstTy.isVector()) 4314 return UnableToLegalize; 4315 4316 Register Amt = MI.getOperand(2).getReg(); 4317 LLT ShiftAmtTy = MRI.getType(Amt); 4318 const unsigned DstEltSize = DstTy.getScalarSizeInBits(); 4319 if (DstEltSize % 2 != 0) 4320 return UnableToLegalize; 4321 4322 // Ignore the input type. We can only go to exactly half the size of the 4323 // input. If that isn't small enough, the resulting pieces will be further 4324 // legalized. 4325 const unsigned NewBitSize = DstEltSize / 2; 4326 const LLT HalfTy = LLT::scalar(NewBitSize); 4327 const LLT CondTy = LLT::scalar(1); 4328 4329 if (const MachineInstr *KShiftAmt = 4330 getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) { 4331 return narrowScalarShiftByConstant( 4332 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy); 4333 } 4334 4335 // TODO: Expand with known bits. 4336 4337 // Handle the fully general expansion by an unknown amount. 4338 auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize); 4339 4340 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4341 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4342 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4343 4344 auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits); 4345 auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt); 4346 4347 auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0); 4348 auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits); 4349 auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero); 4350 4351 Register ResultRegs[2]; 4352 switch (MI.getOpcode()) { 4353 case TargetOpcode::G_SHL: { 4354 // Short: ShAmt < NewBitSize 4355 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); 4356 4357 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack); 4358 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt); 4359 auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4360 4361 // Long: ShAmt >= NewBitSize 4362 auto LoL = MIRBuilder.buildConstant(HalfTy, 0); // Lo part is zero. 4363 auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part. 4364 4365 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL); 4366 auto Hi = MIRBuilder.buildSelect( 4367 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL)); 4368 4369 ResultRegs[0] = Lo.getReg(0); 4370 ResultRegs[1] = Hi.getReg(0); 4371 break; 4372 } 4373 case TargetOpcode::G_LSHR: 4374 case TargetOpcode::G_ASHR: { 4375 // Short: ShAmt < NewBitSize 4376 auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt}); 4377 4378 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt); 4379 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack); 4380 auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4381 4382 // Long: ShAmt >= NewBitSize 4383 MachineInstrBuilder HiL; 4384 if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4385 HiL = MIRBuilder.buildConstant(HalfTy, 0); // Hi part is zero. 4386 } else { 4387 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1); 4388 HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt); // Sign of Hi part. 4389 } 4390 auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, 4391 {InH, AmtExcess}); // Lo from Hi part. 4392 4393 auto Lo = MIRBuilder.buildSelect( 4394 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL)); 4395 4396 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL); 4397 4398 ResultRegs[0] = Lo.getReg(0); 4399 ResultRegs[1] = Hi.getReg(0); 4400 break; 4401 } 4402 default: 4403 llvm_unreachable("not a shift"); 4404 } 4405 4406 MIRBuilder.buildMerge(DstReg, ResultRegs); 4407 MI.eraseFromParent(); 4408 return Legalized; 4409 } 4410 4411 LegalizerHelper::LegalizeResult 4412 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 4413 LLT MoreTy) { 4414 assert(TypeIdx == 0 && "Expecting only Idx 0"); 4415 4416 Observer.changingInstr(MI); 4417 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 4418 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 4419 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 4420 moreElementsVectorSrc(MI, MoreTy, I); 4421 } 4422 4423 MachineBasicBlock &MBB = *MI.getParent(); 4424 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 4425 moreElementsVectorDst(MI, MoreTy, 0); 4426 Observer.changedInstr(MI); 4427 return Legalized; 4428 } 4429 4430 LegalizerHelper::LegalizeResult 4431 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx, 4432 LLT MoreTy) { 4433 unsigned Opc = MI.getOpcode(); 4434 switch (Opc) { 4435 case TargetOpcode::G_IMPLICIT_DEF: 4436 case TargetOpcode::G_LOAD: { 4437 if (TypeIdx != 0) 4438 return UnableToLegalize; 4439 Observer.changingInstr(MI); 4440 moreElementsVectorDst(MI, MoreTy, 0); 4441 Observer.changedInstr(MI); 4442 return Legalized; 4443 } 4444 case TargetOpcode::G_STORE: 4445 if (TypeIdx != 0) 4446 return UnableToLegalize; 4447 Observer.changingInstr(MI); 4448 moreElementsVectorSrc(MI, MoreTy, 0); 4449 Observer.changedInstr(MI); 4450 return Legalized; 4451 case TargetOpcode::G_AND: 4452 case TargetOpcode::G_OR: 4453 case TargetOpcode::G_XOR: 4454 case TargetOpcode::G_SMIN: 4455 case TargetOpcode::G_SMAX: 4456 case TargetOpcode::G_UMIN: 4457 case TargetOpcode::G_UMAX: 4458 case TargetOpcode::G_FMINNUM: 4459 case TargetOpcode::G_FMAXNUM: 4460 case TargetOpcode::G_FMINNUM_IEEE: 4461 case TargetOpcode::G_FMAXNUM_IEEE: 4462 case TargetOpcode::G_FMINIMUM: 4463 case TargetOpcode::G_FMAXIMUM: { 4464 Observer.changingInstr(MI); 4465 moreElementsVectorSrc(MI, MoreTy, 1); 4466 moreElementsVectorSrc(MI, MoreTy, 2); 4467 moreElementsVectorDst(MI, MoreTy, 0); 4468 Observer.changedInstr(MI); 4469 return Legalized; 4470 } 4471 case TargetOpcode::G_EXTRACT: 4472 if (TypeIdx != 1) 4473 return UnableToLegalize; 4474 Observer.changingInstr(MI); 4475 moreElementsVectorSrc(MI, MoreTy, 1); 4476 Observer.changedInstr(MI); 4477 return Legalized; 4478 case TargetOpcode::G_INSERT: 4479 case TargetOpcode::G_FREEZE: 4480 if (TypeIdx != 0) 4481 return UnableToLegalize; 4482 Observer.changingInstr(MI); 4483 moreElementsVectorSrc(MI, MoreTy, 1); 4484 moreElementsVectorDst(MI, MoreTy, 0); 4485 Observer.changedInstr(MI); 4486 return Legalized; 4487 case TargetOpcode::G_SELECT: 4488 if (TypeIdx != 0) 4489 return UnableToLegalize; 4490 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) 4491 return UnableToLegalize; 4492 4493 Observer.changingInstr(MI); 4494 moreElementsVectorSrc(MI, MoreTy, 2); 4495 moreElementsVectorSrc(MI, MoreTy, 3); 4496 moreElementsVectorDst(MI, MoreTy, 0); 4497 Observer.changedInstr(MI); 4498 return Legalized; 4499 case TargetOpcode::G_UNMERGE_VALUES: { 4500 if (TypeIdx != 1) 4501 return UnableToLegalize; 4502 4503 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 4504 int NumDst = MI.getNumOperands() - 1; 4505 moreElementsVectorSrc(MI, MoreTy, NumDst); 4506 4507 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 4508 for (int I = 0; I != NumDst; ++I) 4509 MIB.addDef(MI.getOperand(I).getReg()); 4510 4511 int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits(); 4512 for (int I = NumDst; I != NewNumDst; ++I) 4513 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 4514 4515 MIB.addUse(MI.getOperand(NumDst).getReg()); 4516 MI.eraseFromParent(); 4517 return Legalized; 4518 } 4519 case TargetOpcode::G_PHI: 4520 return moreElementsVectorPhi(MI, TypeIdx, MoreTy); 4521 default: 4522 return UnableToLegalize; 4523 } 4524 } 4525 4526 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs, 4527 ArrayRef<Register> Src1Regs, 4528 ArrayRef<Register> Src2Regs, 4529 LLT NarrowTy) { 4530 MachineIRBuilder &B = MIRBuilder; 4531 unsigned SrcParts = Src1Regs.size(); 4532 unsigned DstParts = DstRegs.size(); 4533 4534 unsigned DstIdx = 0; // Low bits of the result. 4535 Register FactorSum = 4536 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); 4537 DstRegs[DstIdx] = FactorSum; 4538 4539 unsigned CarrySumPrevDstIdx; 4540 SmallVector<Register, 4> Factors; 4541 4542 for (DstIdx = 1; DstIdx < DstParts; DstIdx++) { 4543 // Collect low parts of muls for DstIdx. 4544 for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1; 4545 i <= std::min(DstIdx, SrcParts - 1); ++i) { 4546 MachineInstrBuilder Mul = 4547 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); 4548 Factors.push_back(Mul.getReg(0)); 4549 } 4550 // Collect high parts of muls from previous DstIdx. 4551 for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts; 4552 i <= std::min(DstIdx - 1, SrcParts - 1); ++i) { 4553 MachineInstrBuilder Umulh = 4554 B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]); 4555 Factors.push_back(Umulh.getReg(0)); 4556 } 4557 // Add CarrySum from additions calculated for previous DstIdx. 4558 if (DstIdx != 1) { 4559 Factors.push_back(CarrySumPrevDstIdx); 4560 } 4561 4562 Register CarrySum; 4563 // Add all factors and accumulate all carries into CarrySum. 4564 if (DstIdx != DstParts - 1) { 4565 MachineInstrBuilder Uaddo = 4566 B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]); 4567 FactorSum = Uaddo.getReg(0); 4568 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0); 4569 for (unsigned i = 2; i < Factors.size(); ++i) { 4570 MachineInstrBuilder Uaddo = 4571 B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]); 4572 FactorSum = Uaddo.getReg(0); 4573 MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1)); 4574 CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0); 4575 } 4576 } else { 4577 // Since value for the next index is not calculated, neither is CarrySum. 4578 FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0); 4579 for (unsigned i = 2; i < Factors.size(); ++i) 4580 FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0); 4581 } 4582 4583 CarrySumPrevDstIdx = CarrySum; 4584 DstRegs[DstIdx] = FactorSum; 4585 Factors.clear(); 4586 } 4587 } 4588 4589 LegalizerHelper::LegalizeResult 4590 LegalizerHelper::narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx, 4591 LLT NarrowTy) { 4592 if (TypeIdx != 0) 4593 return UnableToLegalize; 4594 4595 Register DstReg = MI.getOperand(0).getReg(); 4596 LLT DstType = MRI.getType(DstReg); 4597 // FIXME: add support for vector types 4598 if (DstType.isVector()) 4599 return UnableToLegalize; 4600 4601 uint64_t SizeOp0 = DstType.getSizeInBits(); 4602 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 4603 4604 // FIXME: add support for when SizeOp0 isn't an exact multiple of 4605 // NarrowSize. 4606 if (SizeOp0 % NarrowSize != 0) 4607 return UnableToLegalize; 4608 4609 // Expand in terms of carry-setting/consuming G_<Op>E instructions. 4610 int NumParts = SizeOp0 / NarrowTy.getSizeInBits(); 4611 4612 unsigned Opcode = MI.getOpcode(); 4613 unsigned OpO, OpE, OpF; 4614 switch (Opcode) { 4615 case TargetOpcode::G_SADDO: 4616 case TargetOpcode::G_SADDE: 4617 case TargetOpcode::G_UADDO: 4618 case TargetOpcode::G_UADDE: 4619 case TargetOpcode::G_ADD: 4620 OpO = TargetOpcode::G_UADDO; 4621 OpE = TargetOpcode::G_UADDE; 4622 OpF = TargetOpcode::G_UADDE; 4623 if (Opcode == TargetOpcode::G_SADDO || Opcode == TargetOpcode::G_SADDE) 4624 OpF = TargetOpcode::G_SADDE; 4625 break; 4626 case TargetOpcode::G_SSUBO: 4627 case TargetOpcode::G_SSUBE: 4628 case TargetOpcode::G_USUBO: 4629 case TargetOpcode::G_USUBE: 4630 case TargetOpcode::G_SUB: 4631 OpO = TargetOpcode::G_USUBO; 4632 OpE = TargetOpcode::G_USUBE; 4633 OpF = TargetOpcode::G_USUBE; 4634 if (Opcode == TargetOpcode::G_SSUBO || Opcode == TargetOpcode::G_SSUBE) 4635 OpF = TargetOpcode::G_SSUBE; 4636 break; 4637 default: 4638 llvm_unreachable("Unexpected add/sub opcode!"); 4639 } 4640 4641 // 1 for a plain add/sub, 2 if this is an operation with a carry-out. 4642 unsigned NumDefs = MI.getNumExplicitDefs(); 4643 Register Src1 = MI.getOperand(NumDefs).getReg(); 4644 Register Src2 = MI.getOperand(NumDefs + 1).getReg(); 4645 Register CarryDst; 4646 if (NumDefs == 2) 4647 CarryDst = MI.getOperand(1).getReg(); 4648 Register CarryIn; 4649 if (MI.getNumOperands() == NumDefs + 3) 4650 CarryIn = MI.getOperand(NumDefs + 2).getReg(); 4651 4652 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 4653 extractParts(Src1, NarrowTy, NumParts, Src1Regs); 4654 extractParts(Src2, NarrowTy, NumParts, Src2Regs); 4655 4656 for (int i = 0; i < NumParts; ++i) { 4657 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 4658 Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); 4659 // Forward the final carry-out to the destination register 4660 if (i == NumParts - 1 && CarryDst) 4661 CarryOut = CarryDst; 4662 4663 if (!CarryIn) { 4664 MIRBuilder.buildInstr(OpO, {DstReg, CarryOut}, 4665 {Src1Regs[i], Src2Regs[i]}); 4666 } else if (i == NumParts - 1) { 4667 MIRBuilder.buildInstr(OpF, {DstReg, CarryOut}, 4668 {Src1Regs[i], Src2Regs[i], CarryIn}); 4669 } else { 4670 MIRBuilder.buildInstr(OpE, {DstReg, CarryOut}, 4671 {Src1Regs[i], Src2Regs[i], CarryIn}); 4672 } 4673 4674 DstRegs.push_back(DstReg); 4675 CarryIn = CarryOut; 4676 } 4677 MIRBuilder.buildMerge(DstReg, DstRegs); 4678 MI.eraseFromParent(); 4679 return Legalized; 4680 } 4681 4682 LegalizerHelper::LegalizeResult 4683 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) { 4684 Register DstReg = MI.getOperand(0).getReg(); 4685 Register Src1 = MI.getOperand(1).getReg(); 4686 Register Src2 = MI.getOperand(2).getReg(); 4687 4688 LLT Ty = MRI.getType(DstReg); 4689 if (Ty.isVector()) 4690 return UnableToLegalize; 4691 4692 unsigned SrcSize = MRI.getType(Src1).getSizeInBits(); 4693 unsigned DstSize = Ty.getSizeInBits(); 4694 unsigned NarrowSize = NarrowTy.getSizeInBits(); 4695 if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0) 4696 return UnableToLegalize; 4697 4698 unsigned NumDstParts = DstSize / NarrowSize; 4699 unsigned NumSrcParts = SrcSize / NarrowSize; 4700 bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH; 4701 unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1); 4702 4703 SmallVector<Register, 2> Src1Parts, Src2Parts; 4704 SmallVector<Register, 2> DstTmpRegs(DstTmpParts); 4705 extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts); 4706 extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts); 4707 multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy); 4708 4709 // Take only high half of registers if this is high mul. 4710 ArrayRef<Register> DstRegs( 4711 IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts); 4712 MIRBuilder.buildMerge(DstReg, DstRegs); 4713 MI.eraseFromParent(); 4714 return Legalized; 4715 } 4716 4717 LegalizerHelper::LegalizeResult 4718 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, 4719 LLT NarrowTy) { 4720 if (TypeIdx != 1) 4721 return UnableToLegalize; 4722 4723 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 4724 4725 int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 4726 // FIXME: add support for when SizeOp1 isn't an exact multiple of 4727 // NarrowSize. 4728 if (SizeOp1 % NarrowSize != 0) 4729 return UnableToLegalize; 4730 int NumParts = SizeOp1 / NarrowSize; 4731 4732 SmallVector<Register, 2> SrcRegs, DstRegs; 4733 SmallVector<uint64_t, 2> Indexes; 4734 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 4735 4736 Register OpReg = MI.getOperand(0).getReg(); 4737 uint64_t OpStart = MI.getOperand(2).getImm(); 4738 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 4739 for (int i = 0; i < NumParts; ++i) { 4740 unsigned SrcStart = i * NarrowSize; 4741 4742 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) { 4743 // No part of the extract uses this subregister, ignore it. 4744 continue; 4745 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 4746 // The entire subregister is extracted, forward the value. 4747 DstRegs.push_back(SrcRegs[i]); 4748 continue; 4749 } 4750 4751 // OpSegStart is where this destination segment would start in OpReg if it 4752 // extended infinitely in both directions. 4753 int64_t ExtractOffset; 4754 uint64_t SegSize; 4755 if (OpStart < SrcStart) { 4756 ExtractOffset = 0; 4757 SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart); 4758 } else { 4759 ExtractOffset = OpStart - SrcStart; 4760 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize); 4761 } 4762 4763 Register SegReg = SrcRegs[i]; 4764 if (ExtractOffset != 0 || SegSize != NarrowSize) { 4765 // A genuine extract is needed. 4766 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 4767 MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset); 4768 } 4769 4770 DstRegs.push_back(SegReg); 4771 } 4772 4773 Register DstReg = MI.getOperand(0).getReg(); 4774 if (MRI.getType(DstReg).isVector()) 4775 MIRBuilder.buildBuildVector(DstReg, DstRegs); 4776 else if (DstRegs.size() > 1) 4777 MIRBuilder.buildMerge(DstReg, DstRegs); 4778 else 4779 MIRBuilder.buildCopy(DstReg, DstRegs[0]); 4780 MI.eraseFromParent(); 4781 return Legalized; 4782 } 4783 4784 LegalizerHelper::LegalizeResult 4785 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, 4786 LLT NarrowTy) { 4787 // FIXME: Don't know how to handle secondary types yet. 4788 if (TypeIdx != 0) 4789 return UnableToLegalize; 4790 4791 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 4792 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 4793 4794 // FIXME: add support for when SizeOp0 isn't an exact multiple of 4795 // NarrowSize. 4796 if (SizeOp0 % NarrowSize != 0) 4797 return UnableToLegalize; 4798 4799 int NumParts = SizeOp0 / NarrowSize; 4800 4801 SmallVector<Register, 2> SrcRegs, DstRegs; 4802 SmallVector<uint64_t, 2> Indexes; 4803 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 4804 4805 Register OpReg = MI.getOperand(2).getReg(); 4806 uint64_t OpStart = MI.getOperand(3).getImm(); 4807 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 4808 for (int i = 0; i < NumParts; ++i) { 4809 unsigned DstStart = i * NarrowSize; 4810 4811 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) { 4812 // No part of the insert affects this subregister, forward the original. 4813 DstRegs.push_back(SrcRegs[i]); 4814 continue; 4815 } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 4816 // The entire subregister is defined by this insert, forward the new 4817 // value. 4818 DstRegs.push_back(OpReg); 4819 continue; 4820 } 4821 4822 // OpSegStart is where this destination segment would start in OpReg if it 4823 // extended infinitely in both directions. 4824 int64_t ExtractOffset, InsertOffset; 4825 uint64_t SegSize; 4826 if (OpStart < DstStart) { 4827 InsertOffset = 0; 4828 ExtractOffset = DstStart - OpStart; 4829 SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart); 4830 } else { 4831 InsertOffset = OpStart - DstStart; 4832 ExtractOffset = 0; 4833 SegSize = 4834 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart); 4835 } 4836 4837 Register SegReg = OpReg; 4838 if (ExtractOffset != 0 || SegSize != OpSize) { 4839 // A genuine extract is needed. 4840 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 4841 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); 4842 } 4843 4844 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 4845 MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset); 4846 DstRegs.push_back(DstReg); 4847 } 4848 4849 assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered"); 4850 Register DstReg = MI.getOperand(0).getReg(); 4851 if(MRI.getType(DstReg).isVector()) 4852 MIRBuilder.buildBuildVector(DstReg, DstRegs); 4853 else 4854 MIRBuilder.buildMerge(DstReg, DstRegs); 4855 MI.eraseFromParent(); 4856 return Legalized; 4857 } 4858 4859 LegalizerHelper::LegalizeResult 4860 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, 4861 LLT NarrowTy) { 4862 Register DstReg = MI.getOperand(0).getReg(); 4863 LLT DstTy = MRI.getType(DstReg); 4864 4865 assert(MI.getNumOperands() == 3 && TypeIdx == 0); 4866 4867 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 4868 SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs; 4869 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 4870 LLT LeftoverTy; 4871 if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy, 4872 Src0Regs, Src0LeftoverRegs)) 4873 return UnableToLegalize; 4874 4875 LLT Unused; 4876 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused, 4877 Src1Regs, Src1LeftoverRegs)) 4878 llvm_unreachable("inconsistent extractParts result"); 4879 4880 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 4881 auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 4882 {Src0Regs[I], Src1Regs[I]}); 4883 DstRegs.push_back(Inst.getReg(0)); 4884 } 4885 4886 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 4887 auto Inst = MIRBuilder.buildInstr( 4888 MI.getOpcode(), 4889 {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]}); 4890 DstLeftoverRegs.push_back(Inst.getReg(0)); 4891 } 4892 4893 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 4894 LeftoverTy, DstLeftoverRegs); 4895 4896 MI.eraseFromParent(); 4897 return Legalized; 4898 } 4899 4900 LegalizerHelper::LegalizeResult 4901 LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, 4902 LLT NarrowTy) { 4903 if (TypeIdx != 0) 4904 return UnableToLegalize; 4905 4906 Register DstReg = MI.getOperand(0).getReg(); 4907 Register SrcReg = MI.getOperand(1).getReg(); 4908 4909 LLT DstTy = MRI.getType(DstReg); 4910 if (DstTy.isVector()) 4911 return UnableToLegalize; 4912 4913 SmallVector<Register, 8> Parts; 4914 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 4915 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, MI.getOpcode()); 4916 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 4917 4918 MI.eraseFromParent(); 4919 return Legalized; 4920 } 4921 4922 LegalizerHelper::LegalizeResult 4923 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, 4924 LLT NarrowTy) { 4925 if (TypeIdx != 0) 4926 return UnableToLegalize; 4927 4928 Register CondReg = MI.getOperand(1).getReg(); 4929 LLT CondTy = MRI.getType(CondReg); 4930 if (CondTy.isVector()) // TODO: Handle vselect 4931 return UnableToLegalize; 4932 4933 Register DstReg = MI.getOperand(0).getReg(); 4934 LLT DstTy = MRI.getType(DstReg); 4935 4936 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 4937 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 4938 SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs; 4939 LLT LeftoverTy; 4940 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy, 4941 Src1Regs, Src1LeftoverRegs)) 4942 return UnableToLegalize; 4943 4944 LLT Unused; 4945 if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused, 4946 Src2Regs, Src2LeftoverRegs)) 4947 llvm_unreachable("inconsistent extractParts result"); 4948 4949 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 4950 auto Select = MIRBuilder.buildSelect(NarrowTy, 4951 CondReg, Src1Regs[I], Src2Regs[I]); 4952 DstRegs.push_back(Select.getReg(0)); 4953 } 4954 4955 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 4956 auto Select = MIRBuilder.buildSelect( 4957 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); 4958 DstLeftoverRegs.push_back(Select.getReg(0)); 4959 } 4960 4961 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 4962 LeftoverTy, DstLeftoverRegs); 4963 4964 MI.eraseFromParent(); 4965 return Legalized; 4966 } 4967 4968 LegalizerHelper::LegalizeResult 4969 LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, 4970 LLT NarrowTy) { 4971 if (TypeIdx != 1) 4972 return UnableToLegalize; 4973 4974 Register DstReg = MI.getOperand(0).getReg(); 4975 Register SrcReg = MI.getOperand(1).getReg(); 4976 LLT DstTy = MRI.getType(DstReg); 4977 LLT SrcTy = MRI.getType(SrcReg); 4978 unsigned NarrowSize = NarrowTy.getSizeInBits(); 4979 4980 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 4981 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF; 4982 4983 MachineIRBuilder &B = MIRBuilder; 4984 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 4985 // ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi) 4986 auto C_0 = B.buildConstant(NarrowTy, 0); 4987 auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 4988 UnmergeSrc.getReg(1), C_0); 4989 auto LoCTLZ = IsUndef ? 4990 B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)) : 4991 B.buildCTLZ(DstTy, UnmergeSrc.getReg(0)); 4992 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 4993 auto HiIsZeroCTLZ = B.buildAdd(DstTy, LoCTLZ, C_NarrowSize); 4994 auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)); 4995 B.buildSelect(DstReg, HiIsZero, HiIsZeroCTLZ, HiCTLZ); 4996 4997 MI.eraseFromParent(); 4998 return Legalized; 4999 } 5000 5001 return UnableToLegalize; 5002 } 5003 5004 LegalizerHelper::LegalizeResult 5005 LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, 5006 LLT NarrowTy) { 5007 if (TypeIdx != 1) 5008 return UnableToLegalize; 5009 5010 Register DstReg = MI.getOperand(0).getReg(); 5011 Register SrcReg = MI.getOperand(1).getReg(); 5012 LLT DstTy = MRI.getType(DstReg); 5013 LLT SrcTy = MRI.getType(SrcReg); 5014 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5015 5016 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5017 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF; 5018 5019 MachineIRBuilder &B = MIRBuilder; 5020 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 5021 // cttz(Hi:Lo) -> Lo == 0 ? (cttz(Hi) + NarrowSize) : cttz(Lo) 5022 auto C_0 = B.buildConstant(NarrowTy, 0); 5023 auto LoIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 5024 UnmergeSrc.getReg(0), C_0); 5025 auto HiCTTZ = IsUndef ? 5026 B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)) : 5027 B.buildCTTZ(DstTy, UnmergeSrc.getReg(1)); 5028 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 5029 auto LoIsZeroCTTZ = B.buildAdd(DstTy, HiCTTZ, C_NarrowSize); 5030 auto LoCTTZ = B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)); 5031 B.buildSelect(DstReg, LoIsZero, LoIsZeroCTTZ, LoCTTZ); 5032 5033 MI.eraseFromParent(); 5034 return Legalized; 5035 } 5036 5037 return UnableToLegalize; 5038 } 5039 5040 LegalizerHelper::LegalizeResult 5041 LegalizerHelper::narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, 5042 LLT NarrowTy) { 5043 if (TypeIdx != 1) 5044 return UnableToLegalize; 5045 5046 Register DstReg = MI.getOperand(0).getReg(); 5047 LLT DstTy = MRI.getType(DstReg); 5048 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 5049 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5050 5051 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5052 auto UnmergeSrc = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 5053 5054 auto LoCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(0)); 5055 auto HiCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(1)); 5056 MIRBuilder.buildAdd(DstReg, HiCTPOP, LoCTPOP); 5057 5058 MI.eraseFromParent(); 5059 return Legalized; 5060 } 5061 5062 return UnableToLegalize; 5063 } 5064 5065 LegalizerHelper::LegalizeResult 5066 LegalizerHelper::lowerBitCount(MachineInstr &MI) { 5067 unsigned Opc = MI.getOpcode(); 5068 const auto &TII = MIRBuilder.getTII(); 5069 auto isSupported = [this](const LegalityQuery &Q) { 5070 auto QAction = LI.getAction(Q).Action; 5071 return QAction == Legal || QAction == Libcall || QAction == Custom; 5072 }; 5073 switch (Opc) { 5074 default: 5075 return UnableToLegalize; 5076 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 5077 // This trivially expands to CTLZ. 5078 Observer.changingInstr(MI); 5079 MI.setDesc(TII.get(TargetOpcode::G_CTLZ)); 5080 Observer.changedInstr(MI); 5081 return Legalized; 5082 } 5083 case TargetOpcode::G_CTLZ: { 5084 Register DstReg = MI.getOperand(0).getReg(); 5085 Register SrcReg = MI.getOperand(1).getReg(); 5086 LLT DstTy = MRI.getType(DstReg); 5087 LLT SrcTy = MRI.getType(SrcReg); 5088 unsigned Len = SrcTy.getSizeInBits(); 5089 5090 if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 5091 // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero. 5092 auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg); 5093 auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0); 5094 auto ICmp = MIRBuilder.buildICmp( 5095 CmpInst::ICMP_EQ, SrcTy.changeElementSize(1), SrcReg, ZeroSrc); 5096 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 5097 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CtlzZU); 5098 MI.eraseFromParent(); 5099 return Legalized; 5100 } 5101 // for now, we do this: 5102 // NewLen = NextPowerOf2(Len); 5103 // x = x | (x >> 1); 5104 // x = x | (x >> 2); 5105 // ... 5106 // x = x | (x >>16); 5107 // x = x | (x >>32); // for 64-bit input 5108 // Upto NewLen/2 5109 // return Len - popcount(x); 5110 // 5111 // Ref: "Hacker's Delight" by Henry Warren 5112 Register Op = SrcReg; 5113 unsigned NewLen = PowerOf2Ceil(Len); 5114 for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) { 5115 auto MIBShiftAmt = MIRBuilder.buildConstant(SrcTy, 1ULL << i); 5116 auto MIBOp = MIRBuilder.buildOr( 5117 SrcTy, Op, MIRBuilder.buildLShr(SrcTy, Op, MIBShiftAmt)); 5118 Op = MIBOp.getReg(0); 5119 } 5120 auto MIBPop = MIRBuilder.buildCTPOP(DstTy, Op); 5121 MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(DstTy, Len), 5122 MIBPop); 5123 MI.eraseFromParent(); 5124 return Legalized; 5125 } 5126 case TargetOpcode::G_CTTZ_ZERO_UNDEF: { 5127 // This trivially expands to CTTZ. 5128 Observer.changingInstr(MI); 5129 MI.setDesc(TII.get(TargetOpcode::G_CTTZ)); 5130 Observer.changedInstr(MI); 5131 return Legalized; 5132 } 5133 case TargetOpcode::G_CTTZ: { 5134 Register DstReg = MI.getOperand(0).getReg(); 5135 Register SrcReg = MI.getOperand(1).getReg(); 5136 LLT DstTy = MRI.getType(DstReg); 5137 LLT SrcTy = MRI.getType(SrcReg); 5138 5139 unsigned Len = SrcTy.getSizeInBits(); 5140 if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 5141 // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with 5142 // zero. 5143 auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg); 5144 auto Zero = MIRBuilder.buildConstant(SrcTy, 0); 5145 auto ICmp = MIRBuilder.buildICmp( 5146 CmpInst::ICMP_EQ, DstTy.changeElementSize(1), SrcReg, Zero); 5147 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 5148 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CttzZU); 5149 MI.eraseFromParent(); 5150 return Legalized; 5151 } 5152 // for now, we use: { return popcount(~x & (x - 1)); } 5153 // unless the target has ctlz but not ctpop, in which case we use: 5154 // { return 32 - nlz(~x & (x-1)); } 5155 // Ref: "Hacker's Delight" by Henry Warren 5156 auto MIBCstNeg1 = MIRBuilder.buildConstant(SrcTy, -1); 5157 auto MIBNot = MIRBuilder.buildXor(SrcTy, SrcReg, MIBCstNeg1); 5158 auto MIBTmp = MIRBuilder.buildAnd( 5159 SrcTy, MIBNot, MIRBuilder.buildAdd(SrcTy, SrcReg, MIBCstNeg1)); 5160 if (!isSupported({TargetOpcode::G_CTPOP, {SrcTy, SrcTy}}) && 5161 isSupported({TargetOpcode::G_CTLZ, {SrcTy, SrcTy}})) { 5162 auto MIBCstLen = MIRBuilder.buildConstant(SrcTy, Len); 5163 MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen, 5164 MIRBuilder.buildCTLZ(SrcTy, MIBTmp)); 5165 MI.eraseFromParent(); 5166 return Legalized; 5167 } 5168 MI.setDesc(TII.get(TargetOpcode::G_CTPOP)); 5169 MI.getOperand(1).setReg(MIBTmp.getReg(0)); 5170 return Legalized; 5171 } 5172 case TargetOpcode::G_CTPOP: { 5173 Register SrcReg = MI.getOperand(1).getReg(); 5174 LLT Ty = MRI.getType(SrcReg); 5175 unsigned Size = Ty.getSizeInBits(); 5176 MachineIRBuilder &B = MIRBuilder; 5177 5178 // Count set bits in blocks of 2 bits. Default approach would be 5179 // B2Count = { val & 0x55555555 } + { (val >> 1) & 0x55555555 } 5180 // We use following formula instead: 5181 // B2Count = val - { (val >> 1) & 0x55555555 } 5182 // since it gives same result in blocks of 2 with one instruction less. 5183 auto C_1 = B.buildConstant(Ty, 1); 5184 auto B2Set1LoTo1Hi = B.buildLShr(Ty, SrcReg, C_1); 5185 APInt B2Mask1HiTo0 = APInt::getSplat(Size, APInt(8, 0x55)); 5186 auto C_B2Mask1HiTo0 = B.buildConstant(Ty, B2Mask1HiTo0); 5187 auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0); 5188 auto B2Count = B.buildSub(Ty, SrcReg, B2Count1Hi); 5189 5190 // In order to get count in blocks of 4 add values from adjacent block of 2. 5191 // B4Count = { B2Count & 0x33333333 } + { (B2Count >> 2) & 0x33333333 } 5192 auto C_2 = B.buildConstant(Ty, 2); 5193 auto B4Set2LoTo2Hi = B.buildLShr(Ty, B2Count, C_2); 5194 APInt B4Mask2HiTo0 = APInt::getSplat(Size, APInt(8, 0x33)); 5195 auto C_B4Mask2HiTo0 = B.buildConstant(Ty, B4Mask2HiTo0); 5196 auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0); 5197 auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0); 5198 auto B4Count = B.buildAdd(Ty, B4HiB2Count, B4LoB2Count); 5199 5200 // For count in blocks of 8 bits we don't have to mask high 4 bits before 5201 // addition since count value sits in range {0,...,8} and 4 bits are enough 5202 // to hold such binary values. After addition high 4 bits still hold count 5203 // of set bits in high 4 bit block, set them to zero and get 8 bit result. 5204 // B8Count = { B4Count + (B4Count >> 4) } & 0x0F0F0F0F 5205 auto C_4 = B.buildConstant(Ty, 4); 5206 auto B8HiB4Count = B.buildLShr(Ty, B4Count, C_4); 5207 auto B8CountDirty4Hi = B.buildAdd(Ty, B8HiB4Count, B4Count); 5208 APInt B8Mask4HiTo0 = APInt::getSplat(Size, APInt(8, 0x0F)); 5209 auto C_B8Mask4HiTo0 = B.buildConstant(Ty, B8Mask4HiTo0); 5210 auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0); 5211 5212 assert(Size<=128 && "Scalar size is too large for CTPOP lower algorithm"); 5213 // 8 bits can hold CTPOP result of 128 bit int or smaller. Mul with this 5214 // bitmask will set 8 msb in ResTmp to sum of all B8Counts in 8 bit blocks. 5215 auto MulMask = B.buildConstant(Ty, APInt::getSplat(Size, APInt(8, 0x01))); 5216 auto ResTmp = B.buildMul(Ty, B8Count, MulMask); 5217 5218 // Shift count result from 8 high bits to low bits. 5219 auto C_SizeM8 = B.buildConstant(Ty, Size - 8); 5220 B.buildLShr(MI.getOperand(0).getReg(), ResTmp, C_SizeM8); 5221 5222 MI.eraseFromParent(); 5223 return Legalized; 5224 } 5225 } 5226 } 5227 5228 // Check that (every element of) Reg is undef or not an exact multiple of BW. 5229 static bool isNonZeroModBitWidthOrUndef(const MachineRegisterInfo &MRI, 5230 Register Reg, unsigned BW) { 5231 return matchUnaryPredicate( 5232 MRI, Reg, 5233 [=](const Constant *C) { 5234 // Null constant here means an undef. 5235 const ConstantInt *CI = dyn_cast_or_null<ConstantInt>(C); 5236 return !CI || CI->getValue().urem(BW) != 0; 5237 }, 5238 /*AllowUndefs*/ true); 5239 } 5240 5241 LegalizerHelper::LegalizeResult 5242 LegalizerHelper::lowerFunnelShiftWithInverse(MachineInstr &MI) { 5243 Register Dst = MI.getOperand(0).getReg(); 5244 Register X = MI.getOperand(1).getReg(); 5245 Register Y = MI.getOperand(2).getReg(); 5246 Register Z = MI.getOperand(3).getReg(); 5247 LLT Ty = MRI.getType(Dst); 5248 LLT ShTy = MRI.getType(Z); 5249 5250 unsigned BW = Ty.getScalarSizeInBits(); 5251 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5252 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; 5253 5254 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { 5255 // fshl X, Y, Z -> fshr X, Y, -Z 5256 // fshr X, Y, Z -> fshl X, Y, -Z 5257 auto Zero = MIRBuilder.buildConstant(ShTy, 0); 5258 Z = MIRBuilder.buildSub(Ty, Zero, Z).getReg(0); 5259 } else { 5260 // fshl X, Y, Z -> fshr (srl X, 1), (fshr X, Y, 1), ~Z 5261 // fshr X, Y, Z -> fshl (fshl X, Y, 1), (shl Y, 1), ~Z 5262 auto One = MIRBuilder.buildConstant(ShTy, 1); 5263 if (IsFSHL) { 5264 Y = MIRBuilder.buildInstr(RevOpcode, {Ty}, {X, Y, One}).getReg(0); 5265 X = MIRBuilder.buildLShr(Ty, X, One).getReg(0); 5266 } else { 5267 X = MIRBuilder.buildInstr(RevOpcode, {Ty}, {X, Y, One}).getReg(0); 5268 Y = MIRBuilder.buildShl(Ty, Y, One).getReg(0); 5269 } 5270 5271 Z = MIRBuilder.buildNot(ShTy, Z).getReg(0); 5272 } 5273 5274 MIRBuilder.buildInstr(RevOpcode, {Dst}, {X, Y, Z}); 5275 MI.eraseFromParent(); 5276 return Legalized; 5277 } 5278 5279 LegalizerHelper::LegalizeResult 5280 LegalizerHelper::lowerFunnelShiftAsShifts(MachineInstr &MI) { 5281 Register Dst = MI.getOperand(0).getReg(); 5282 Register X = MI.getOperand(1).getReg(); 5283 Register Y = MI.getOperand(2).getReg(); 5284 Register Z = MI.getOperand(3).getReg(); 5285 LLT Ty = MRI.getType(Dst); 5286 LLT ShTy = MRI.getType(Z); 5287 5288 const unsigned BW = Ty.getScalarSizeInBits(); 5289 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5290 5291 Register ShX, ShY; 5292 Register ShAmt, InvShAmt; 5293 5294 // FIXME: Emit optimized urem by constant instead of letting it expand later. 5295 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { 5296 // fshl: X << C | Y >> (BW - C) 5297 // fshr: X << (BW - C) | Y >> C 5298 // where C = Z % BW is not zero 5299 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); 5300 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); 5301 InvShAmt = MIRBuilder.buildSub(ShTy, BitWidthC, ShAmt).getReg(0); 5302 ShX = MIRBuilder.buildShl(Ty, X, IsFSHL ? ShAmt : InvShAmt).getReg(0); 5303 ShY = MIRBuilder.buildLShr(Ty, Y, IsFSHL ? InvShAmt : ShAmt).getReg(0); 5304 } else { 5305 // fshl: X << (Z % BW) | Y >> 1 >> (BW - 1 - (Z % BW)) 5306 // fshr: X << 1 << (BW - 1 - (Z % BW)) | Y >> (Z % BW) 5307 auto Mask = MIRBuilder.buildConstant(ShTy, BW - 1); 5308 if (isPowerOf2_32(BW)) { 5309 // Z % BW -> Z & (BW - 1) 5310 ShAmt = MIRBuilder.buildAnd(ShTy, Z, Mask).getReg(0); 5311 // (BW - 1) - (Z % BW) -> ~Z & (BW - 1) 5312 auto NotZ = MIRBuilder.buildNot(ShTy, Z); 5313 InvShAmt = MIRBuilder.buildAnd(ShTy, NotZ, Mask).getReg(0); 5314 } else { 5315 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); 5316 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); 5317 InvShAmt = MIRBuilder.buildSub(ShTy, Mask, ShAmt).getReg(0); 5318 } 5319 5320 auto One = MIRBuilder.buildConstant(ShTy, 1); 5321 if (IsFSHL) { 5322 ShX = MIRBuilder.buildShl(Ty, X, ShAmt).getReg(0); 5323 auto ShY1 = MIRBuilder.buildLShr(Ty, Y, One); 5324 ShY = MIRBuilder.buildLShr(Ty, ShY1, InvShAmt).getReg(0); 5325 } else { 5326 auto ShX1 = MIRBuilder.buildShl(Ty, X, One); 5327 ShX = MIRBuilder.buildShl(Ty, ShX1, InvShAmt).getReg(0); 5328 ShY = MIRBuilder.buildLShr(Ty, Y, ShAmt).getReg(0); 5329 } 5330 } 5331 5332 MIRBuilder.buildOr(Dst, ShX, ShY); 5333 MI.eraseFromParent(); 5334 return Legalized; 5335 } 5336 5337 LegalizerHelper::LegalizeResult 5338 LegalizerHelper::lowerFunnelShift(MachineInstr &MI) { 5339 // These operations approximately do the following (while avoiding undefined 5340 // shifts by BW): 5341 // G_FSHL: (X << (Z % BW)) | (Y >> (BW - (Z % BW))) 5342 // G_FSHR: (X << (BW - (Z % BW))) | (Y >> (Z % BW)) 5343 Register Dst = MI.getOperand(0).getReg(); 5344 LLT Ty = MRI.getType(Dst); 5345 LLT ShTy = MRI.getType(MI.getOperand(3).getReg()); 5346 5347 bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5348 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; 5349 if (LI.getAction({RevOpcode, {Ty, ShTy}}).Action == Lower) 5350 return lowerFunnelShiftAsShifts(MI); 5351 return lowerFunnelShiftWithInverse(MI); 5352 } 5353 5354 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float 5355 // representation. 5356 LegalizerHelper::LegalizeResult 5357 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) { 5358 Register Dst = MI.getOperand(0).getReg(); 5359 Register Src = MI.getOperand(1).getReg(); 5360 const LLT S64 = LLT::scalar(64); 5361 const LLT S32 = LLT::scalar(32); 5362 const LLT S1 = LLT::scalar(1); 5363 5364 assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32); 5365 5366 // unsigned cul2f(ulong u) { 5367 // uint lz = clz(u); 5368 // uint e = (u != 0) ? 127U + 63U - lz : 0; 5369 // u = (u << lz) & 0x7fffffffffffffffUL; 5370 // ulong t = u & 0xffffffffffUL; 5371 // uint v = (e << 23) | (uint)(u >> 40); 5372 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U); 5373 // return as_float(v + r); 5374 // } 5375 5376 auto Zero32 = MIRBuilder.buildConstant(S32, 0); 5377 auto Zero64 = MIRBuilder.buildConstant(S64, 0); 5378 5379 auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src); 5380 5381 auto K = MIRBuilder.buildConstant(S32, 127U + 63U); 5382 auto Sub = MIRBuilder.buildSub(S32, K, LZ); 5383 5384 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64); 5385 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32); 5386 5387 auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1); 5388 auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ); 5389 5390 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0); 5391 5392 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); 5393 auto T = MIRBuilder.buildAnd(S64, U, Mask1); 5394 5395 auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40)); 5396 auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23)); 5397 auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl)); 5398 5399 auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL); 5400 auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C); 5401 auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C); 5402 auto One = MIRBuilder.buildConstant(S32, 1); 5403 5404 auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One); 5405 auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32); 5406 auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0); 5407 MIRBuilder.buildAdd(Dst, V, R); 5408 5409 MI.eraseFromParent(); 5410 return Legalized; 5411 } 5412 5413 LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) { 5414 Register Dst = MI.getOperand(0).getReg(); 5415 Register Src = MI.getOperand(1).getReg(); 5416 LLT DstTy = MRI.getType(Dst); 5417 LLT SrcTy = MRI.getType(Src); 5418 5419 if (SrcTy == LLT::scalar(1)) { 5420 auto True = MIRBuilder.buildFConstant(DstTy, 1.0); 5421 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5422 MIRBuilder.buildSelect(Dst, Src, True, False); 5423 MI.eraseFromParent(); 5424 return Legalized; 5425 } 5426 5427 if (SrcTy != LLT::scalar(64)) 5428 return UnableToLegalize; 5429 5430 if (DstTy == LLT::scalar(32)) { 5431 // TODO: SelectionDAG has several alternative expansions to port which may 5432 // be more reasonble depending on the available instructions. If a target 5433 // has sitofp, does not have CTLZ, or can efficiently use f64 as an 5434 // intermediate type, this is probably worse. 5435 return lowerU64ToF32BitOps(MI); 5436 } 5437 5438 return UnableToLegalize; 5439 } 5440 5441 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) { 5442 Register Dst = MI.getOperand(0).getReg(); 5443 Register Src = MI.getOperand(1).getReg(); 5444 LLT DstTy = MRI.getType(Dst); 5445 LLT SrcTy = MRI.getType(Src); 5446 5447 const LLT S64 = LLT::scalar(64); 5448 const LLT S32 = LLT::scalar(32); 5449 const LLT S1 = LLT::scalar(1); 5450 5451 if (SrcTy == S1) { 5452 auto True = MIRBuilder.buildFConstant(DstTy, -1.0); 5453 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5454 MIRBuilder.buildSelect(Dst, Src, True, False); 5455 MI.eraseFromParent(); 5456 return Legalized; 5457 } 5458 5459 if (SrcTy != S64) 5460 return UnableToLegalize; 5461 5462 if (DstTy == S32) { 5463 // signed cl2f(long l) { 5464 // long s = l >> 63; 5465 // float r = cul2f((l + s) ^ s); 5466 // return s ? -r : r; 5467 // } 5468 Register L = Src; 5469 auto SignBit = MIRBuilder.buildConstant(S64, 63); 5470 auto S = MIRBuilder.buildAShr(S64, L, SignBit); 5471 5472 auto LPlusS = MIRBuilder.buildAdd(S64, L, S); 5473 auto Xor = MIRBuilder.buildXor(S64, LPlusS, S); 5474 auto R = MIRBuilder.buildUITOFP(S32, Xor); 5475 5476 auto RNeg = MIRBuilder.buildFNeg(S32, R); 5477 auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S, 5478 MIRBuilder.buildConstant(S64, 0)); 5479 MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R); 5480 MI.eraseFromParent(); 5481 return Legalized; 5482 } 5483 5484 return UnableToLegalize; 5485 } 5486 5487 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) { 5488 Register Dst = MI.getOperand(0).getReg(); 5489 Register Src = MI.getOperand(1).getReg(); 5490 LLT DstTy = MRI.getType(Dst); 5491 LLT SrcTy = MRI.getType(Src); 5492 const LLT S64 = LLT::scalar(64); 5493 const LLT S32 = LLT::scalar(32); 5494 5495 if (SrcTy != S64 && SrcTy != S32) 5496 return UnableToLegalize; 5497 if (DstTy != S32 && DstTy != S64) 5498 return UnableToLegalize; 5499 5500 // FPTOSI gives same result as FPTOUI for positive signed integers. 5501 // FPTOUI needs to deal with fp values that convert to unsigned integers 5502 // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp. 5503 5504 APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits()); 5505 APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle() 5506 : APFloat::IEEEdouble(), 5507 APInt::getNullValue(SrcTy.getSizeInBits())); 5508 TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven); 5509 5510 MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src); 5511 5512 MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP); 5513 // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on 5514 // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1. 5515 MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold); 5516 MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub); 5517 MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt); 5518 MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit); 5519 5520 const LLT S1 = LLT::scalar(1); 5521 5522 MachineInstrBuilder FCMP = 5523 MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold); 5524 MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res); 5525 5526 MI.eraseFromParent(); 5527 return Legalized; 5528 } 5529 5530 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) { 5531 Register Dst = MI.getOperand(0).getReg(); 5532 Register Src = MI.getOperand(1).getReg(); 5533 LLT DstTy = MRI.getType(Dst); 5534 LLT SrcTy = MRI.getType(Src); 5535 const LLT S64 = LLT::scalar(64); 5536 const LLT S32 = LLT::scalar(32); 5537 5538 // FIXME: Only f32 to i64 conversions are supported. 5539 if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64) 5540 return UnableToLegalize; 5541 5542 // Expand f32 -> i64 conversion 5543 // This algorithm comes from compiler-rt's implementation of fixsfdi: 5544 // https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/fixsfdi.c 5545 5546 unsigned SrcEltBits = SrcTy.getScalarSizeInBits(); 5547 5548 auto ExponentMask = MIRBuilder.buildConstant(SrcTy, 0x7F800000); 5549 auto ExponentLoBit = MIRBuilder.buildConstant(SrcTy, 23); 5550 5551 auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask); 5552 auto ExponentBits = MIRBuilder.buildLShr(SrcTy, AndExpMask, ExponentLoBit); 5553 5554 auto SignMask = MIRBuilder.buildConstant(SrcTy, 5555 APInt::getSignMask(SrcEltBits)); 5556 auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask); 5557 auto SignLowBit = MIRBuilder.buildConstant(SrcTy, SrcEltBits - 1); 5558 auto Sign = MIRBuilder.buildAShr(SrcTy, AndSignMask, SignLowBit); 5559 Sign = MIRBuilder.buildSExt(DstTy, Sign); 5560 5561 auto MantissaMask = MIRBuilder.buildConstant(SrcTy, 0x007FFFFF); 5562 auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask); 5563 auto K = MIRBuilder.buildConstant(SrcTy, 0x00800000); 5564 5565 auto R = MIRBuilder.buildOr(SrcTy, AndMantissaMask, K); 5566 R = MIRBuilder.buildZExt(DstTy, R); 5567 5568 auto Bias = MIRBuilder.buildConstant(SrcTy, 127); 5569 auto Exponent = MIRBuilder.buildSub(SrcTy, ExponentBits, Bias); 5570 auto SubExponent = MIRBuilder.buildSub(SrcTy, Exponent, ExponentLoBit); 5571 auto ExponentSub = MIRBuilder.buildSub(SrcTy, ExponentLoBit, Exponent); 5572 5573 auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent); 5574 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); 5575 5576 const LLT S1 = LLT::scalar(1); 5577 auto CmpGt = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, 5578 S1, Exponent, ExponentLoBit); 5579 5580 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl); 5581 5582 auto XorSign = MIRBuilder.buildXor(DstTy, R, Sign); 5583 auto Ret = MIRBuilder.buildSub(DstTy, XorSign, Sign); 5584 5585 auto ZeroSrcTy = MIRBuilder.buildConstant(SrcTy, 0); 5586 5587 auto ExponentLt0 = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, 5588 S1, Exponent, ZeroSrcTy); 5589 5590 auto ZeroDstTy = MIRBuilder.buildConstant(DstTy, 0); 5591 MIRBuilder.buildSelect(Dst, ExponentLt0, ZeroDstTy, Ret); 5592 5593 MI.eraseFromParent(); 5594 return Legalized; 5595 } 5596 5597 // f64 -> f16 conversion using round-to-nearest-even rounding mode. 5598 LegalizerHelper::LegalizeResult 5599 LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) { 5600 Register Dst = MI.getOperand(0).getReg(); 5601 Register Src = MI.getOperand(1).getReg(); 5602 5603 if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly. 5604 return UnableToLegalize; 5605 5606 const unsigned ExpMask = 0x7ff; 5607 const unsigned ExpBiasf64 = 1023; 5608 const unsigned ExpBiasf16 = 15; 5609 const LLT S32 = LLT::scalar(32); 5610 const LLT S1 = LLT::scalar(1); 5611 5612 auto Unmerge = MIRBuilder.buildUnmerge(S32, Src); 5613 Register U = Unmerge.getReg(0); 5614 Register UH = Unmerge.getReg(1); 5615 5616 auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20)); 5617 E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask)); 5618 5619 // Subtract the fp64 exponent bias (1023) to get the real exponent and 5620 // add the f16 bias (15) to get the biased exponent for the f16 format. 5621 E = MIRBuilder.buildAdd( 5622 S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16)); 5623 5624 auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8)); 5625 M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe)); 5626 5627 auto MaskedSig = MIRBuilder.buildAnd(S32, UH, 5628 MIRBuilder.buildConstant(S32, 0x1ff)); 5629 MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U); 5630 5631 auto Zero = MIRBuilder.buildConstant(S32, 0); 5632 auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero); 5633 auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0); 5634 M = MIRBuilder.buildOr(S32, M, Lo40Set); 5635 5636 // (M != 0 ? 0x0200 : 0) | 0x7c00; 5637 auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200); 5638 auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero); 5639 auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero); 5640 5641 auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00); 5642 auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00); 5643 5644 // N = M | (E << 12); 5645 auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12)); 5646 auto N = MIRBuilder.buildOr(S32, M, EShl12); 5647 5648 // B = clamp(1-E, 0, 13); 5649 auto One = MIRBuilder.buildConstant(S32, 1); 5650 auto OneSubExp = MIRBuilder.buildSub(S32, One, E); 5651 auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero); 5652 B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13)); 5653 5654 auto SigSetHigh = MIRBuilder.buildOr(S32, M, 5655 MIRBuilder.buildConstant(S32, 0x1000)); 5656 5657 auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B); 5658 auto D0 = MIRBuilder.buildShl(S32, D, B); 5659 5660 auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, 5661 D0, SigSetHigh); 5662 auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh); 5663 D = MIRBuilder.buildOr(S32, D, D1); 5664 5665 auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One); 5666 auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N); 5667 5668 auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7)); 5669 V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2)); 5670 5671 auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3, 5672 MIRBuilder.buildConstant(S32, 3)); 5673 auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3); 5674 5675 auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3, 5676 MIRBuilder.buildConstant(S32, 5)); 5677 auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5); 5678 5679 V1 = MIRBuilder.buildOr(S32, V0, V1); 5680 V = MIRBuilder.buildAdd(S32, V, V1); 5681 5682 auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, 5683 E, MIRBuilder.buildConstant(S32, 30)); 5684 V = MIRBuilder.buildSelect(S32, CmpEGt30, 5685 MIRBuilder.buildConstant(S32, 0x7c00), V); 5686 5687 auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, 5688 E, MIRBuilder.buildConstant(S32, 1039)); 5689 V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V); 5690 5691 // Extract the sign bit. 5692 auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16)); 5693 Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000)); 5694 5695 // Insert the sign bit 5696 V = MIRBuilder.buildOr(S32, Sign, V); 5697 5698 MIRBuilder.buildTrunc(Dst, V); 5699 MI.eraseFromParent(); 5700 return Legalized; 5701 } 5702 5703 LegalizerHelper::LegalizeResult 5704 LegalizerHelper::lowerFPTRUNC(MachineInstr &MI) { 5705 Register Dst = MI.getOperand(0).getReg(); 5706 Register Src = MI.getOperand(1).getReg(); 5707 5708 LLT DstTy = MRI.getType(Dst); 5709 LLT SrcTy = MRI.getType(Src); 5710 const LLT S64 = LLT::scalar(64); 5711 const LLT S16 = LLT::scalar(16); 5712 5713 if (DstTy.getScalarType() == S16 && SrcTy.getScalarType() == S64) 5714 return lowerFPTRUNC_F64_TO_F16(MI); 5715 5716 return UnableToLegalize; 5717 } 5718 5719 // TODO: If RHS is a constant SelectionDAGBuilder expands this into a 5720 // multiplication tree. 5721 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPOWI(MachineInstr &MI) { 5722 Register Dst = MI.getOperand(0).getReg(); 5723 Register Src0 = MI.getOperand(1).getReg(); 5724 Register Src1 = MI.getOperand(2).getReg(); 5725 LLT Ty = MRI.getType(Dst); 5726 5727 auto CvtSrc1 = MIRBuilder.buildSITOFP(Ty, Src1); 5728 MIRBuilder.buildFPow(Dst, Src0, CvtSrc1, MI.getFlags()); 5729 MI.eraseFromParent(); 5730 return Legalized; 5731 } 5732 5733 static CmpInst::Predicate minMaxToCompare(unsigned Opc) { 5734 switch (Opc) { 5735 case TargetOpcode::G_SMIN: 5736 return CmpInst::ICMP_SLT; 5737 case TargetOpcode::G_SMAX: 5738 return CmpInst::ICMP_SGT; 5739 case TargetOpcode::G_UMIN: 5740 return CmpInst::ICMP_ULT; 5741 case TargetOpcode::G_UMAX: 5742 return CmpInst::ICMP_UGT; 5743 default: 5744 llvm_unreachable("not in integer min/max"); 5745 } 5746 } 5747 5748 LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) { 5749 Register Dst = MI.getOperand(0).getReg(); 5750 Register Src0 = MI.getOperand(1).getReg(); 5751 Register Src1 = MI.getOperand(2).getReg(); 5752 5753 const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode()); 5754 LLT CmpType = MRI.getType(Dst).changeElementSize(1); 5755 5756 auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1); 5757 MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1); 5758 5759 MI.eraseFromParent(); 5760 return Legalized; 5761 } 5762 5763 LegalizerHelper::LegalizeResult 5764 LegalizerHelper::lowerFCopySign(MachineInstr &MI) { 5765 Register Dst = MI.getOperand(0).getReg(); 5766 Register Src0 = MI.getOperand(1).getReg(); 5767 Register Src1 = MI.getOperand(2).getReg(); 5768 5769 const LLT Src0Ty = MRI.getType(Src0); 5770 const LLT Src1Ty = MRI.getType(Src1); 5771 5772 const int Src0Size = Src0Ty.getScalarSizeInBits(); 5773 const int Src1Size = Src1Ty.getScalarSizeInBits(); 5774 5775 auto SignBitMask = MIRBuilder.buildConstant( 5776 Src0Ty, APInt::getSignMask(Src0Size)); 5777 5778 auto NotSignBitMask = MIRBuilder.buildConstant( 5779 Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1)); 5780 5781 Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask).getReg(0); 5782 Register And1; 5783 if (Src0Ty == Src1Ty) { 5784 And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask).getReg(0); 5785 } else if (Src0Size > Src1Size) { 5786 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size); 5787 auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1); 5788 auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt); 5789 And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0); 5790 } else { 5791 auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size); 5792 auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt); 5793 auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift); 5794 And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask).getReg(0); 5795 } 5796 5797 // Be careful about setting nsz/nnan/ninf on every instruction, since the 5798 // constants are a nan and -0.0, but the final result should preserve 5799 // everything. 5800 unsigned Flags = MI.getFlags(); 5801 MIRBuilder.buildOr(Dst, And0, And1, Flags); 5802 5803 MI.eraseFromParent(); 5804 return Legalized; 5805 } 5806 5807 LegalizerHelper::LegalizeResult 5808 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) { 5809 unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ? 5810 TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE; 5811 5812 Register Dst = MI.getOperand(0).getReg(); 5813 Register Src0 = MI.getOperand(1).getReg(); 5814 Register Src1 = MI.getOperand(2).getReg(); 5815 LLT Ty = MRI.getType(Dst); 5816 5817 if (!MI.getFlag(MachineInstr::FmNoNans)) { 5818 // Insert canonicalizes if it's possible we need to quiet to get correct 5819 // sNaN behavior. 5820 5821 // Note this must be done here, and not as an optimization combine in the 5822 // absence of a dedicate quiet-snan instruction as we're using an 5823 // omni-purpose G_FCANONICALIZE. 5824 if (!isKnownNeverSNaN(Src0, MRI)) 5825 Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0); 5826 5827 if (!isKnownNeverSNaN(Src1, MRI)) 5828 Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0); 5829 } 5830 5831 // If there are no nans, it's safe to simply replace this with the non-IEEE 5832 // version. 5833 MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags()); 5834 MI.eraseFromParent(); 5835 return Legalized; 5836 } 5837 5838 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) { 5839 // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c 5840 Register DstReg = MI.getOperand(0).getReg(); 5841 LLT Ty = MRI.getType(DstReg); 5842 unsigned Flags = MI.getFlags(); 5843 5844 auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2), 5845 Flags); 5846 MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags); 5847 MI.eraseFromParent(); 5848 return Legalized; 5849 } 5850 5851 LegalizerHelper::LegalizeResult 5852 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) { 5853 Register DstReg = MI.getOperand(0).getReg(); 5854 Register X = MI.getOperand(1).getReg(); 5855 const unsigned Flags = MI.getFlags(); 5856 const LLT Ty = MRI.getType(DstReg); 5857 const LLT CondTy = Ty.changeElementSize(1); 5858 5859 // round(x) => 5860 // t = trunc(x); 5861 // d = fabs(x - t); 5862 // o = copysign(1.0f, x); 5863 // return t + (d >= 0.5 ? o : 0.0); 5864 5865 auto T = MIRBuilder.buildIntrinsicTrunc(Ty, X, Flags); 5866 5867 auto Diff = MIRBuilder.buildFSub(Ty, X, T, Flags); 5868 auto AbsDiff = MIRBuilder.buildFAbs(Ty, Diff, Flags); 5869 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 5870 auto One = MIRBuilder.buildFConstant(Ty, 1.0); 5871 auto Half = MIRBuilder.buildFConstant(Ty, 0.5); 5872 auto SignOne = MIRBuilder.buildFCopysign(Ty, One, X); 5873 5874 auto Cmp = MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half, 5875 Flags); 5876 auto Sel = MIRBuilder.buildSelect(Ty, Cmp, SignOne, Zero, Flags); 5877 5878 MIRBuilder.buildFAdd(DstReg, T, Sel, Flags); 5879 5880 MI.eraseFromParent(); 5881 return Legalized; 5882 } 5883 5884 LegalizerHelper::LegalizeResult 5885 LegalizerHelper::lowerFFloor(MachineInstr &MI) { 5886 Register DstReg = MI.getOperand(0).getReg(); 5887 Register SrcReg = MI.getOperand(1).getReg(); 5888 unsigned Flags = MI.getFlags(); 5889 LLT Ty = MRI.getType(DstReg); 5890 const LLT CondTy = Ty.changeElementSize(1); 5891 5892 // result = trunc(src); 5893 // if (src < 0.0 && src != result) 5894 // result += -1.0. 5895 5896 auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags); 5897 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 5898 5899 auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy, 5900 SrcReg, Zero, Flags); 5901 auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy, 5902 SrcReg, Trunc, Flags); 5903 auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc); 5904 auto AddVal = MIRBuilder.buildSITOFP(Ty, And); 5905 5906 MIRBuilder.buildFAdd(DstReg, Trunc, AddVal, Flags); 5907 MI.eraseFromParent(); 5908 return Legalized; 5909 } 5910 5911 LegalizerHelper::LegalizeResult 5912 LegalizerHelper::lowerMergeValues(MachineInstr &MI) { 5913 const unsigned NumOps = MI.getNumOperands(); 5914 Register DstReg = MI.getOperand(0).getReg(); 5915 Register Src0Reg = MI.getOperand(1).getReg(); 5916 LLT DstTy = MRI.getType(DstReg); 5917 LLT SrcTy = MRI.getType(Src0Reg); 5918 unsigned PartSize = SrcTy.getSizeInBits(); 5919 5920 LLT WideTy = LLT::scalar(DstTy.getSizeInBits()); 5921 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); 5922 5923 for (unsigned I = 2; I != NumOps; ++I) { 5924 const unsigned Offset = (I - 1) * PartSize; 5925 5926 Register SrcReg = MI.getOperand(I).getReg(); 5927 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 5928 5929 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 5930 MRI.createGenericVirtualRegister(WideTy); 5931 5932 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 5933 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 5934 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 5935 ResultReg = NextResult; 5936 } 5937 5938 if (DstTy.isPointer()) { 5939 if (MIRBuilder.getDataLayout().isNonIntegralAddressSpace( 5940 DstTy.getAddressSpace())) { 5941 LLVM_DEBUG(dbgs() << "Not casting nonintegral address space\n"); 5942 return UnableToLegalize; 5943 } 5944 5945 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 5946 } 5947 5948 MI.eraseFromParent(); 5949 return Legalized; 5950 } 5951 5952 LegalizerHelper::LegalizeResult 5953 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) { 5954 const unsigned NumDst = MI.getNumOperands() - 1; 5955 Register SrcReg = MI.getOperand(NumDst).getReg(); 5956 Register Dst0Reg = MI.getOperand(0).getReg(); 5957 LLT DstTy = MRI.getType(Dst0Reg); 5958 if (DstTy.isPointer()) 5959 return UnableToLegalize; // TODO 5960 5961 SrcReg = coerceToScalar(SrcReg); 5962 if (!SrcReg) 5963 return UnableToLegalize; 5964 5965 // Expand scalarizing unmerge as bitcast to integer and shift. 5966 LLT IntTy = MRI.getType(SrcReg); 5967 5968 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 5969 5970 const unsigned DstSize = DstTy.getSizeInBits(); 5971 unsigned Offset = DstSize; 5972 for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) { 5973 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset); 5974 auto Shift = MIRBuilder.buildLShr(IntTy, SrcReg, ShiftAmt); 5975 MIRBuilder.buildTrunc(MI.getOperand(I), Shift); 5976 } 5977 5978 MI.eraseFromParent(); 5979 return Legalized; 5980 } 5981 5982 /// Lower a vector extract or insert by writing the vector to a stack temporary 5983 /// and reloading the element or vector. 5984 /// 5985 /// %dst = G_EXTRACT_VECTOR_ELT %vec, %idx 5986 /// => 5987 /// %stack_temp = G_FRAME_INDEX 5988 /// G_STORE %vec, %stack_temp 5989 /// %idx = clamp(%idx, %vec.getNumElements()) 5990 /// %element_ptr = G_PTR_ADD %stack_temp, %idx 5991 /// %dst = G_LOAD %element_ptr 5992 LegalizerHelper::LegalizeResult 5993 LegalizerHelper::lowerExtractInsertVectorElt(MachineInstr &MI) { 5994 Register DstReg = MI.getOperand(0).getReg(); 5995 Register SrcVec = MI.getOperand(1).getReg(); 5996 Register InsertVal; 5997 if (MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT) 5998 InsertVal = MI.getOperand(2).getReg(); 5999 6000 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 6001 6002 LLT VecTy = MRI.getType(SrcVec); 6003 LLT EltTy = VecTy.getElementType(); 6004 if (!EltTy.isByteSized()) { // Not implemented. 6005 LLVM_DEBUG(dbgs() << "Can't handle non-byte element vectors yet\n"); 6006 return UnableToLegalize; 6007 } 6008 6009 unsigned EltBytes = EltTy.getSizeInBytes(); 6010 Align VecAlign = getStackTemporaryAlignment(VecTy); 6011 Align EltAlign; 6012 6013 MachinePointerInfo PtrInfo; 6014 auto StackTemp = createStackTemporary(TypeSize::Fixed(VecTy.getSizeInBytes()), 6015 VecAlign, PtrInfo); 6016 MIRBuilder.buildStore(SrcVec, StackTemp, PtrInfo, VecAlign); 6017 6018 // Get the pointer to the element, and be sure not to hit undefined behavior 6019 // if the index is out of bounds. 6020 Register EltPtr = getVectorElementPointer(StackTemp.getReg(0), VecTy, Idx); 6021 6022 int64_t IdxVal; 6023 if (mi_match(Idx, MRI, m_ICst(IdxVal))) { 6024 int64_t Offset = IdxVal * EltBytes; 6025 PtrInfo = PtrInfo.getWithOffset(Offset); 6026 EltAlign = commonAlignment(VecAlign, Offset); 6027 } else { 6028 // We lose information with a variable offset. 6029 EltAlign = getStackTemporaryAlignment(EltTy); 6030 PtrInfo = MachinePointerInfo(MRI.getType(EltPtr).getAddressSpace()); 6031 } 6032 6033 if (InsertVal) { 6034 // Write the inserted element 6035 MIRBuilder.buildStore(InsertVal, EltPtr, PtrInfo, EltAlign); 6036 6037 // Reload the whole vector. 6038 MIRBuilder.buildLoad(DstReg, StackTemp, PtrInfo, VecAlign); 6039 } else { 6040 MIRBuilder.buildLoad(DstReg, EltPtr, PtrInfo, EltAlign); 6041 } 6042 6043 MI.eraseFromParent(); 6044 return Legalized; 6045 } 6046 6047 LegalizerHelper::LegalizeResult 6048 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) { 6049 Register DstReg = MI.getOperand(0).getReg(); 6050 Register Src0Reg = MI.getOperand(1).getReg(); 6051 Register Src1Reg = MI.getOperand(2).getReg(); 6052 LLT Src0Ty = MRI.getType(Src0Reg); 6053 LLT DstTy = MRI.getType(DstReg); 6054 LLT IdxTy = LLT::scalar(32); 6055 6056 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 6057 6058 if (DstTy.isScalar()) { 6059 if (Src0Ty.isVector()) 6060 return UnableToLegalize; 6061 6062 // This is just a SELECT. 6063 assert(Mask.size() == 1 && "Expected a single mask element"); 6064 Register Val; 6065 if (Mask[0] < 0 || Mask[0] > 1) 6066 Val = MIRBuilder.buildUndef(DstTy).getReg(0); 6067 else 6068 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; 6069 MIRBuilder.buildCopy(DstReg, Val); 6070 MI.eraseFromParent(); 6071 return Legalized; 6072 } 6073 6074 Register Undef; 6075 SmallVector<Register, 32> BuildVec; 6076 LLT EltTy = DstTy.getElementType(); 6077 6078 for (int Idx : Mask) { 6079 if (Idx < 0) { 6080 if (!Undef.isValid()) 6081 Undef = MIRBuilder.buildUndef(EltTy).getReg(0); 6082 BuildVec.push_back(Undef); 6083 continue; 6084 } 6085 6086 if (Src0Ty.isScalar()) { 6087 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); 6088 } else { 6089 int NumElts = Src0Ty.getNumElements(); 6090 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; 6091 int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts; 6092 auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx); 6093 auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK); 6094 BuildVec.push_back(Extract.getReg(0)); 6095 } 6096 } 6097 6098 MIRBuilder.buildBuildVector(DstReg, BuildVec); 6099 MI.eraseFromParent(); 6100 return Legalized; 6101 } 6102 6103 LegalizerHelper::LegalizeResult 6104 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) { 6105 const auto &MF = *MI.getMF(); 6106 const auto &TFI = *MF.getSubtarget().getFrameLowering(); 6107 if (TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp) 6108 return UnableToLegalize; 6109 6110 Register Dst = MI.getOperand(0).getReg(); 6111 Register AllocSize = MI.getOperand(1).getReg(); 6112 Align Alignment = assumeAligned(MI.getOperand(2).getImm()); 6113 6114 LLT PtrTy = MRI.getType(Dst); 6115 LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits()); 6116 6117 Register SPReg = TLI.getStackPointerRegisterToSaveRestore(); 6118 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); 6119 SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp); 6120 6121 // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't 6122 // have to generate an extra instruction to negate the alloc and then use 6123 // G_PTR_ADD to add the negative offset. 6124 auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize); 6125 if (Alignment > Align(1)) { 6126 APInt AlignMask(IntPtrTy.getSizeInBits(), Alignment.value(), true); 6127 AlignMask.negate(); 6128 auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask); 6129 Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst); 6130 } 6131 6132 SPTmp = MIRBuilder.buildCast(PtrTy, Alloc); 6133 MIRBuilder.buildCopy(SPReg, SPTmp); 6134 MIRBuilder.buildCopy(Dst, SPTmp); 6135 6136 MI.eraseFromParent(); 6137 return Legalized; 6138 } 6139 6140 LegalizerHelper::LegalizeResult 6141 LegalizerHelper::lowerExtract(MachineInstr &MI) { 6142 Register Dst = MI.getOperand(0).getReg(); 6143 Register Src = MI.getOperand(1).getReg(); 6144 unsigned Offset = MI.getOperand(2).getImm(); 6145 6146 LLT DstTy = MRI.getType(Dst); 6147 LLT SrcTy = MRI.getType(Src); 6148 6149 if (DstTy.isScalar() && 6150 (SrcTy.isScalar() || 6151 (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) { 6152 LLT SrcIntTy = SrcTy; 6153 if (!SrcTy.isScalar()) { 6154 SrcIntTy = LLT::scalar(SrcTy.getSizeInBits()); 6155 Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0); 6156 } 6157 6158 if (Offset == 0) 6159 MIRBuilder.buildTrunc(Dst, Src); 6160 else { 6161 auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset); 6162 auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt); 6163 MIRBuilder.buildTrunc(Dst, Shr); 6164 } 6165 6166 MI.eraseFromParent(); 6167 return Legalized; 6168 } 6169 6170 return UnableToLegalize; 6171 } 6172 6173 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) { 6174 Register Dst = MI.getOperand(0).getReg(); 6175 Register Src = MI.getOperand(1).getReg(); 6176 Register InsertSrc = MI.getOperand(2).getReg(); 6177 uint64_t Offset = MI.getOperand(3).getImm(); 6178 6179 LLT DstTy = MRI.getType(Src); 6180 LLT InsertTy = MRI.getType(InsertSrc); 6181 6182 if (InsertTy.isVector() || 6183 (DstTy.isVector() && DstTy.getElementType() != InsertTy)) 6184 return UnableToLegalize; 6185 6186 const DataLayout &DL = MIRBuilder.getDataLayout(); 6187 if ((DstTy.isPointer() && 6188 DL.isNonIntegralAddressSpace(DstTy.getAddressSpace())) || 6189 (InsertTy.isPointer() && 6190 DL.isNonIntegralAddressSpace(InsertTy.getAddressSpace()))) { 6191 LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n"); 6192 return UnableToLegalize; 6193 } 6194 6195 LLT IntDstTy = DstTy; 6196 6197 if (!DstTy.isScalar()) { 6198 IntDstTy = LLT::scalar(DstTy.getSizeInBits()); 6199 Src = MIRBuilder.buildCast(IntDstTy, Src).getReg(0); 6200 } 6201 6202 if (!InsertTy.isScalar()) { 6203 const LLT IntInsertTy = LLT::scalar(InsertTy.getSizeInBits()); 6204 InsertSrc = MIRBuilder.buildPtrToInt(IntInsertTy, InsertSrc).getReg(0); 6205 } 6206 6207 Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0); 6208 if (Offset != 0) { 6209 auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset); 6210 ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0); 6211 } 6212 6213 APInt MaskVal = APInt::getBitsSetWithWrap( 6214 DstTy.getSizeInBits(), Offset + InsertTy.getSizeInBits(), Offset); 6215 6216 auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal); 6217 auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask); 6218 auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc); 6219 6220 MIRBuilder.buildCast(Dst, Or); 6221 MI.eraseFromParent(); 6222 return Legalized; 6223 } 6224 6225 LegalizerHelper::LegalizeResult 6226 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) { 6227 Register Dst0 = MI.getOperand(0).getReg(); 6228 Register Dst1 = MI.getOperand(1).getReg(); 6229 Register LHS = MI.getOperand(2).getReg(); 6230 Register RHS = MI.getOperand(3).getReg(); 6231 const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO; 6232 6233 LLT Ty = MRI.getType(Dst0); 6234 LLT BoolTy = MRI.getType(Dst1); 6235 6236 if (IsAdd) 6237 MIRBuilder.buildAdd(Dst0, LHS, RHS); 6238 else 6239 MIRBuilder.buildSub(Dst0, LHS, RHS); 6240 6241 // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow. 6242 6243 auto Zero = MIRBuilder.buildConstant(Ty, 0); 6244 6245 // For an addition, the result should be less than one of the operands (LHS) 6246 // if and only if the other operand (RHS) is negative, otherwise there will 6247 // be overflow. 6248 // For a subtraction, the result should be less than one of the operands 6249 // (LHS) if and only if the other operand (RHS) is (non-zero) positive, 6250 // otherwise there will be overflow. 6251 auto ResultLowerThanLHS = 6252 MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS); 6253 auto ConditionRHS = MIRBuilder.buildICmp( 6254 IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero); 6255 6256 MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS); 6257 MI.eraseFromParent(); 6258 return Legalized; 6259 } 6260 6261 LegalizerHelper::LegalizeResult 6262 LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI) { 6263 Register Res = MI.getOperand(0).getReg(); 6264 Register LHS = MI.getOperand(1).getReg(); 6265 Register RHS = MI.getOperand(2).getReg(); 6266 LLT Ty = MRI.getType(Res); 6267 bool IsSigned; 6268 bool IsAdd; 6269 unsigned BaseOp; 6270 switch (MI.getOpcode()) { 6271 default: 6272 llvm_unreachable("unexpected addsat/subsat opcode"); 6273 case TargetOpcode::G_UADDSAT: 6274 IsSigned = false; 6275 IsAdd = true; 6276 BaseOp = TargetOpcode::G_ADD; 6277 break; 6278 case TargetOpcode::G_SADDSAT: 6279 IsSigned = true; 6280 IsAdd = true; 6281 BaseOp = TargetOpcode::G_ADD; 6282 break; 6283 case TargetOpcode::G_USUBSAT: 6284 IsSigned = false; 6285 IsAdd = false; 6286 BaseOp = TargetOpcode::G_SUB; 6287 break; 6288 case TargetOpcode::G_SSUBSAT: 6289 IsSigned = true; 6290 IsAdd = false; 6291 BaseOp = TargetOpcode::G_SUB; 6292 break; 6293 } 6294 6295 if (IsSigned) { 6296 // sadd.sat(a, b) -> 6297 // hi = 0x7fffffff - smax(a, 0) 6298 // lo = 0x80000000 - smin(a, 0) 6299 // a + smin(smax(lo, b), hi) 6300 // ssub.sat(a, b) -> 6301 // lo = smax(a, -1) - 0x7fffffff 6302 // hi = smin(a, -1) - 0x80000000 6303 // a - smin(smax(lo, b), hi) 6304 // TODO: AMDGPU can use a "median of 3" instruction here: 6305 // a +/- med3(lo, b, hi) 6306 uint64_t NumBits = Ty.getScalarSizeInBits(); 6307 auto MaxVal = 6308 MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(NumBits)); 6309 auto MinVal = 6310 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6311 MachineInstrBuilder Hi, Lo; 6312 if (IsAdd) { 6313 auto Zero = MIRBuilder.buildConstant(Ty, 0); 6314 Hi = MIRBuilder.buildSub(Ty, MaxVal, MIRBuilder.buildSMax(Ty, LHS, Zero)); 6315 Lo = MIRBuilder.buildSub(Ty, MinVal, MIRBuilder.buildSMin(Ty, LHS, Zero)); 6316 } else { 6317 auto NegOne = MIRBuilder.buildConstant(Ty, -1); 6318 Lo = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMax(Ty, LHS, NegOne), 6319 MaxVal); 6320 Hi = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMin(Ty, LHS, NegOne), 6321 MinVal); 6322 } 6323 auto RHSClamped = 6324 MIRBuilder.buildSMin(Ty, MIRBuilder.buildSMax(Ty, Lo, RHS), Hi); 6325 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped}); 6326 } else { 6327 // uadd.sat(a, b) -> a + umin(~a, b) 6328 // usub.sat(a, b) -> a - umin(a, b) 6329 Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS; 6330 auto Min = MIRBuilder.buildUMin(Ty, Not, RHS); 6331 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min}); 6332 } 6333 6334 MI.eraseFromParent(); 6335 return Legalized; 6336 } 6337 6338 LegalizerHelper::LegalizeResult 6339 LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) { 6340 Register Res = MI.getOperand(0).getReg(); 6341 Register LHS = MI.getOperand(1).getReg(); 6342 Register RHS = MI.getOperand(2).getReg(); 6343 LLT Ty = MRI.getType(Res); 6344 LLT BoolTy = Ty.changeElementSize(1); 6345 bool IsSigned; 6346 bool IsAdd; 6347 unsigned OverflowOp; 6348 switch (MI.getOpcode()) { 6349 default: 6350 llvm_unreachable("unexpected addsat/subsat opcode"); 6351 case TargetOpcode::G_UADDSAT: 6352 IsSigned = false; 6353 IsAdd = true; 6354 OverflowOp = TargetOpcode::G_UADDO; 6355 break; 6356 case TargetOpcode::G_SADDSAT: 6357 IsSigned = true; 6358 IsAdd = true; 6359 OverflowOp = TargetOpcode::G_SADDO; 6360 break; 6361 case TargetOpcode::G_USUBSAT: 6362 IsSigned = false; 6363 IsAdd = false; 6364 OverflowOp = TargetOpcode::G_USUBO; 6365 break; 6366 case TargetOpcode::G_SSUBSAT: 6367 IsSigned = true; 6368 IsAdd = false; 6369 OverflowOp = TargetOpcode::G_SSUBO; 6370 break; 6371 } 6372 6373 auto OverflowRes = 6374 MIRBuilder.buildInstr(OverflowOp, {Ty, BoolTy}, {LHS, RHS}); 6375 Register Tmp = OverflowRes.getReg(0); 6376 Register Ov = OverflowRes.getReg(1); 6377 MachineInstrBuilder Clamp; 6378 if (IsSigned) { 6379 // sadd.sat(a, b) -> 6380 // {tmp, ov} = saddo(a, b) 6381 // ov ? (tmp >>s 31) + 0x80000000 : r 6382 // ssub.sat(a, b) -> 6383 // {tmp, ov} = ssubo(a, b) 6384 // ov ? (tmp >>s 31) + 0x80000000 : r 6385 uint64_t NumBits = Ty.getScalarSizeInBits(); 6386 auto ShiftAmount = MIRBuilder.buildConstant(Ty, NumBits - 1); 6387 auto Sign = MIRBuilder.buildAShr(Ty, Tmp, ShiftAmount); 6388 auto MinVal = 6389 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6390 Clamp = MIRBuilder.buildAdd(Ty, Sign, MinVal); 6391 } else { 6392 // uadd.sat(a, b) -> 6393 // {tmp, ov} = uaddo(a, b) 6394 // ov ? 0xffffffff : tmp 6395 // usub.sat(a, b) -> 6396 // {tmp, ov} = usubo(a, b) 6397 // ov ? 0 : tmp 6398 Clamp = MIRBuilder.buildConstant(Ty, IsAdd ? -1 : 0); 6399 } 6400 MIRBuilder.buildSelect(Res, Ov, Clamp, Tmp); 6401 6402 MI.eraseFromParent(); 6403 return Legalized; 6404 } 6405 6406 LegalizerHelper::LegalizeResult 6407 LegalizerHelper::lowerShlSat(MachineInstr &MI) { 6408 assert((MI.getOpcode() == TargetOpcode::G_SSHLSAT || 6409 MI.getOpcode() == TargetOpcode::G_USHLSAT) && 6410 "Expected shlsat opcode!"); 6411 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SSHLSAT; 6412 Register Res = MI.getOperand(0).getReg(); 6413 Register LHS = MI.getOperand(1).getReg(); 6414 Register RHS = MI.getOperand(2).getReg(); 6415 LLT Ty = MRI.getType(Res); 6416 LLT BoolTy = Ty.changeElementSize(1); 6417 6418 unsigned BW = Ty.getScalarSizeInBits(); 6419 auto Result = MIRBuilder.buildShl(Ty, LHS, RHS); 6420 auto Orig = IsSigned ? MIRBuilder.buildAShr(Ty, Result, RHS) 6421 : MIRBuilder.buildLShr(Ty, Result, RHS); 6422 6423 MachineInstrBuilder SatVal; 6424 if (IsSigned) { 6425 auto SatMin = MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(BW)); 6426 auto SatMax = MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(BW)); 6427 auto Cmp = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, LHS, 6428 MIRBuilder.buildConstant(Ty, 0)); 6429 SatVal = MIRBuilder.buildSelect(Ty, Cmp, SatMin, SatMax); 6430 } else { 6431 SatVal = MIRBuilder.buildConstant(Ty, APInt::getMaxValue(BW)); 6432 } 6433 auto Ov = MIRBuilder.buildICmp(CmpInst::ICMP_NE, BoolTy, LHS, Orig); 6434 MIRBuilder.buildSelect(Res, Ov, SatVal, Result); 6435 6436 MI.eraseFromParent(); 6437 return Legalized; 6438 } 6439 6440 LegalizerHelper::LegalizeResult 6441 LegalizerHelper::lowerBswap(MachineInstr &MI) { 6442 Register Dst = MI.getOperand(0).getReg(); 6443 Register Src = MI.getOperand(1).getReg(); 6444 const LLT Ty = MRI.getType(Src); 6445 unsigned SizeInBytes = (Ty.getScalarSizeInBits() + 7) / 8; 6446 unsigned BaseShiftAmt = (SizeInBytes - 1) * 8; 6447 6448 // Swap most and least significant byte, set remaining bytes in Res to zero. 6449 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt); 6450 auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt); 6451 auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 6452 auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft); 6453 6454 // Set i-th high/low byte in Res to i-th low/high byte from Src. 6455 for (unsigned i = 1; i < SizeInBytes / 2; ++i) { 6456 // AND with Mask leaves byte i unchanged and sets remaining bytes to 0. 6457 APInt APMask(SizeInBytes * 8, 0xFF << (i * 8)); 6458 auto Mask = MIRBuilder.buildConstant(Ty, APMask); 6459 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i); 6460 // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt. 6461 auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask); 6462 auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt); 6463 Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft); 6464 // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask. 6465 auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 6466 auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask); 6467 Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight); 6468 } 6469 Res.getInstr()->getOperand(0).setReg(Dst); 6470 6471 MI.eraseFromParent(); 6472 return Legalized; 6473 } 6474 6475 //{ (Src & Mask) >> N } | { (Src << N) & Mask } 6476 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B, 6477 MachineInstrBuilder Src, APInt Mask) { 6478 const LLT Ty = Dst.getLLTTy(*B.getMRI()); 6479 MachineInstrBuilder C_N = B.buildConstant(Ty, N); 6480 MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask); 6481 auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N); 6482 auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0); 6483 return B.buildOr(Dst, LHS, RHS); 6484 } 6485 6486 LegalizerHelper::LegalizeResult 6487 LegalizerHelper::lowerBitreverse(MachineInstr &MI) { 6488 Register Dst = MI.getOperand(0).getReg(); 6489 Register Src = MI.getOperand(1).getReg(); 6490 const LLT Ty = MRI.getType(Src); 6491 unsigned Size = Ty.getSizeInBits(); 6492 6493 MachineInstrBuilder BSWAP = 6494 MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src}); 6495 6496 // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654 6497 // [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4] 6498 // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0] 6499 MachineInstrBuilder Swap4 = 6500 SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0))); 6501 6502 // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76 6503 // [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2] 6504 // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC] 6505 MachineInstrBuilder Swap2 = 6506 SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC))); 6507 6508 // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7 6509 // [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1] 6510 // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA] 6511 SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA))); 6512 6513 MI.eraseFromParent(); 6514 return Legalized; 6515 } 6516 6517 LegalizerHelper::LegalizeResult 6518 LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) { 6519 MachineFunction &MF = MIRBuilder.getMF(); 6520 6521 bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER; 6522 int NameOpIdx = IsRead ? 1 : 0; 6523 int ValRegIndex = IsRead ? 0 : 1; 6524 6525 Register ValReg = MI.getOperand(ValRegIndex).getReg(); 6526 const LLT Ty = MRI.getType(ValReg); 6527 const MDString *RegStr = cast<MDString>( 6528 cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0)); 6529 6530 Register PhysReg = TLI.getRegisterByName(RegStr->getString().data(), Ty, MF); 6531 if (!PhysReg.isValid()) 6532 return UnableToLegalize; 6533 6534 if (IsRead) 6535 MIRBuilder.buildCopy(ValReg, PhysReg); 6536 else 6537 MIRBuilder.buildCopy(PhysReg, ValReg); 6538 6539 MI.eraseFromParent(); 6540 return Legalized; 6541 } 6542 6543 LegalizerHelper::LegalizeResult 6544 LegalizerHelper::lowerSMULH_UMULH(MachineInstr &MI) { 6545 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULH; 6546 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 6547 Register Result = MI.getOperand(0).getReg(); 6548 LLT OrigTy = MRI.getType(Result); 6549 auto SizeInBits = OrigTy.getScalarSizeInBits(); 6550 LLT WideTy = OrigTy.changeElementSize(SizeInBits * 2); 6551 6552 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)}); 6553 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)}); 6554 auto Mul = MIRBuilder.buildMul(WideTy, LHS, RHS); 6555 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; 6556 6557 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, SizeInBits); 6558 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); 6559 MIRBuilder.buildTrunc(Result, Shifted); 6560 6561 MI.eraseFromParent(); 6562 return Legalized; 6563 } 6564 6565 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) { 6566 // Implement vector G_SELECT in terms of XOR, AND, OR. 6567 Register DstReg = MI.getOperand(0).getReg(); 6568 Register MaskReg = MI.getOperand(1).getReg(); 6569 Register Op1Reg = MI.getOperand(2).getReg(); 6570 Register Op2Reg = MI.getOperand(3).getReg(); 6571 LLT DstTy = MRI.getType(DstReg); 6572 LLT MaskTy = MRI.getType(MaskReg); 6573 LLT Op1Ty = MRI.getType(Op1Reg); 6574 if (!DstTy.isVector()) 6575 return UnableToLegalize; 6576 6577 // Vector selects can have a scalar predicate. If so, splat into a vector and 6578 // finish for later legalization attempts to try again. 6579 if (MaskTy.isScalar()) { 6580 Register MaskElt = MaskReg; 6581 if (MaskTy.getSizeInBits() < DstTy.getScalarSizeInBits()) 6582 MaskElt = MIRBuilder.buildSExt(DstTy.getElementType(), MaskElt).getReg(0); 6583 // Generate a vector splat idiom to be pattern matched later. 6584 auto ShufSplat = MIRBuilder.buildShuffleSplat(DstTy, MaskElt); 6585 Observer.changingInstr(MI); 6586 MI.getOperand(1).setReg(ShufSplat.getReg(0)); 6587 Observer.changedInstr(MI); 6588 return Legalized; 6589 } 6590 6591 if (MaskTy.getSizeInBits() != Op1Ty.getSizeInBits()) { 6592 return UnableToLegalize; 6593 } 6594 6595 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); 6596 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); 6597 auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask); 6598 MIRBuilder.buildOr(DstReg, NewOp1, NewOp2); 6599 MI.eraseFromParent(); 6600 return Legalized; 6601 } 6602 6603 LegalizerHelper::LegalizeResult LegalizerHelper::lowerDIVREM(MachineInstr &MI) { 6604 // Split DIVREM into individual instructions. 6605 unsigned Opcode = MI.getOpcode(); 6606 6607 MIRBuilder.buildInstr( 6608 Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SDIV 6609 : TargetOpcode::G_UDIV, 6610 {MI.getOperand(0).getReg()}, {MI.getOperand(2), MI.getOperand(3)}); 6611 MIRBuilder.buildInstr( 6612 Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SREM 6613 : TargetOpcode::G_UREM, 6614 {MI.getOperand(1).getReg()}, {MI.getOperand(2), MI.getOperand(3)}); 6615 MI.eraseFromParent(); 6616 return Legalized; 6617 } 6618