1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file This file implements the LegalizerHelper class to legalize 10 /// individual instructions and the LegalizeMachineIR wrapper pass for the 11 /// primary legalization. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 16 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 19 #include "llvm/CodeGen/GlobalISel/LostDebugLocObserver.h" 20 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" 21 #include "llvm/CodeGen/GlobalISel/Utils.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/TargetFrameLowering.h" 24 #include "llvm/CodeGen/TargetInstrInfo.h" 25 #include "llvm/CodeGen/TargetLowering.h" 26 #include "llvm/CodeGen/TargetOpcodes.h" 27 #include "llvm/CodeGen/TargetSubtargetInfo.h" 28 #include "llvm/IR/Instructions.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/MathExtras.h" 31 #include "llvm/Support/raw_ostream.h" 32 33 #define DEBUG_TYPE "legalizer" 34 35 using namespace llvm; 36 using namespace LegalizeActions; 37 using namespace MIPatternMatch; 38 39 /// Try to break down \p OrigTy into \p NarrowTy sized pieces. 40 /// 41 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy, 42 /// with any leftover piece as type \p LeftoverTy 43 /// 44 /// Returns -1 in the first element of the pair if the breakdown is not 45 /// satisfiable. 46 static std::pair<int, int> 47 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) { 48 assert(!LeftoverTy.isValid() && "this is an out argument"); 49 50 unsigned Size = OrigTy.getSizeInBits(); 51 unsigned NarrowSize = NarrowTy.getSizeInBits(); 52 unsigned NumParts = Size / NarrowSize; 53 unsigned LeftoverSize = Size - NumParts * NarrowSize; 54 assert(Size > NarrowSize); 55 56 if (LeftoverSize == 0) 57 return {NumParts, 0}; 58 59 if (NarrowTy.isVector()) { 60 unsigned EltSize = OrigTy.getScalarSizeInBits(); 61 if (LeftoverSize % EltSize != 0) 62 return {-1, -1}; 63 LeftoverTy = LLT::scalarOrVector( 64 ElementCount::getFixed(LeftoverSize / EltSize), EltSize); 65 } else { 66 LeftoverTy = LLT::scalar(LeftoverSize); 67 } 68 69 int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits(); 70 return std::make_pair(NumParts, NumLeftover); 71 } 72 73 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) { 74 75 if (!Ty.isScalar()) 76 return nullptr; 77 78 switch (Ty.getSizeInBits()) { 79 case 16: 80 return Type::getHalfTy(Ctx); 81 case 32: 82 return Type::getFloatTy(Ctx); 83 case 64: 84 return Type::getDoubleTy(Ctx); 85 case 80: 86 return Type::getX86_FP80Ty(Ctx); 87 case 128: 88 return Type::getFP128Ty(Ctx); 89 default: 90 return nullptr; 91 } 92 } 93 94 LegalizerHelper::LegalizerHelper(MachineFunction &MF, 95 GISelChangeObserver &Observer, 96 MachineIRBuilder &Builder) 97 : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()), 98 LI(*MF.getSubtarget().getLegalizerInfo()), 99 TLI(*MF.getSubtarget().getTargetLowering()) { } 100 101 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI, 102 GISelChangeObserver &Observer, 103 MachineIRBuilder &B) 104 : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI), 105 TLI(*MF.getSubtarget().getTargetLowering()) { } 106 107 LegalizerHelper::LegalizeResult 108 LegalizerHelper::legalizeInstrStep(MachineInstr &MI, 109 LostDebugLocObserver &LocObserver) { 110 LLVM_DEBUG(dbgs() << "Legalizing: " << MI); 111 112 MIRBuilder.setInstrAndDebugLoc(MI); 113 114 if (MI.getOpcode() == TargetOpcode::G_INTRINSIC || 115 MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS) 116 return LI.legalizeIntrinsic(*this, MI) ? Legalized : UnableToLegalize; 117 auto Step = LI.getAction(MI, MRI); 118 switch (Step.Action) { 119 case Legal: 120 LLVM_DEBUG(dbgs() << ".. Already legal\n"); 121 return AlreadyLegal; 122 case Libcall: 123 LLVM_DEBUG(dbgs() << ".. Convert to libcall\n"); 124 return libcall(MI, LocObserver); 125 case NarrowScalar: 126 LLVM_DEBUG(dbgs() << ".. Narrow scalar\n"); 127 return narrowScalar(MI, Step.TypeIdx, Step.NewType); 128 case WidenScalar: 129 LLVM_DEBUG(dbgs() << ".. Widen scalar\n"); 130 return widenScalar(MI, Step.TypeIdx, Step.NewType); 131 case Bitcast: 132 LLVM_DEBUG(dbgs() << ".. Bitcast type\n"); 133 return bitcast(MI, Step.TypeIdx, Step.NewType); 134 case Lower: 135 LLVM_DEBUG(dbgs() << ".. Lower\n"); 136 return lower(MI, Step.TypeIdx, Step.NewType); 137 case FewerElements: 138 LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n"); 139 return fewerElementsVector(MI, Step.TypeIdx, Step.NewType); 140 case MoreElements: 141 LLVM_DEBUG(dbgs() << ".. Increase number of elements\n"); 142 return moreElementsVector(MI, Step.TypeIdx, Step.NewType); 143 case Custom: 144 LLVM_DEBUG(dbgs() << ".. Custom legalization\n"); 145 return LI.legalizeCustom(*this, MI) ? Legalized : UnableToLegalize; 146 default: 147 LLVM_DEBUG(dbgs() << ".. Unable to legalize\n"); 148 return UnableToLegalize; 149 } 150 } 151 152 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts, 153 SmallVectorImpl<Register> &VRegs) { 154 for (int i = 0; i < NumParts; ++i) 155 VRegs.push_back(MRI.createGenericVirtualRegister(Ty)); 156 MIRBuilder.buildUnmerge(VRegs, Reg); 157 } 158 159 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, 160 LLT MainTy, LLT &LeftoverTy, 161 SmallVectorImpl<Register> &VRegs, 162 SmallVectorImpl<Register> &LeftoverRegs) { 163 assert(!LeftoverTy.isValid() && "this is an out argument"); 164 165 unsigned RegSize = RegTy.getSizeInBits(); 166 unsigned MainSize = MainTy.getSizeInBits(); 167 unsigned NumParts = RegSize / MainSize; 168 unsigned LeftoverSize = RegSize - NumParts * MainSize; 169 170 // Use an unmerge when possible. 171 if (LeftoverSize == 0) { 172 for (unsigned I = 0; I < NumParts; ++I) 173 VRegs.push_back(MRI.createGenericVirtualRegister(MainTy)); 174 MIRBuilder.buildUnmerge(VRegs, Reg); 175 return true; 176 } 177 178 if (MainTy.isVector()) { 179 unsigned EltSize = MainTy.getScalarSizeInBits(); 180 if (LeftoverSize % EltSize != 0) 181 return false; 182 LeftoverTy = LLT::scalarOrVector( 183 ElementCount::getFixed(LeftoverSize / EltSize), EltSize); 184 } else { 185 LeftoverTy = LLT::scalar(LeftoverSize); 186 } 187 188 // For irregular sizes, extract the individual parts. 189 for (unsigned I = 0; I != NumParts; ++I) { 190 Register NewReg = MRI.createGenericVirtualRegister(MainTy); 191 VRegs.push_back(NewReg); 192 MIRBuilder.buildExtract(NewReg, Reg, MainSize * I); 193 } 194 195 for (unsigned Offset = MainSize * NumParts; Offset < RegSize; 196 Offset += LeftoverSize) { 197 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy); 198 LeftoverRegs.push_back(NewReg); 199 MIRBuilder.buildExtract(NewReg, Reg, Offset); 200 } 201 202 return true; 203 } 204 205 void LegalizerHelper::insertParts(Register DstReg, 206 LLT ResultTy, LLT PartTy, 207 ArrayRef<Register> PartRegs, 208 LLT LeftoverTy, 209 ArrayRef<Register> LeftoverRegs) { 210 if (!LeftoverTy.isValid()) { 211 assert(LeftoverRegs.empty()); 212 213 if (!ResultTy.isVector()) { 214 MIRBuilder.buildMerge(DstReg, PartRegs); 215 return; 216 } 217 218 if (PartTy.isVector()) 219 MIRBuilder.buildConcatVectors(DstReg, PartRegs); 220 else 221 MIRBuilder.buildBuildVector(DstReg, PartRegs); 222 return; 223 } 224 225 SmallVector<Register> GCDRegs; 226 LLT GCDTy = getGCDType(getGCDType(ResultTy, LeftoverTy), PartTy); 227 for (auto PartReg : concat<const Register>(PartRegs, LeftoverRegs)) 228 extractGCDType(GCDRegs, GCDTy, PartReg); 229 LLT ResultLCMTy = buildLCMMergePieces(ResultTy, LeftoverTy, GCDTy, GCDRegs); 230 buildWidenedRemergeToDst(DstReg, ResultLCMTy, GCDRegs); 231 } 232 233 /// Append the result registers of G_UNMERGE_VALUES \p MI to \p Regs. 234 static void getUnmergeResults(SmallVectorImpl<Register> &Regs, 235 const MachineInstr &MI) { 236 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES); 237 238 const int StartIdx = Regs.size(); 239 const int NumResults = MI.getNumOperands() - 1; 240 Regs.resize(Regs.size() + NumResults); 241 for (int I = 0; I != NumResults; ++I) 242 Regs[StartIdx + I] = MI.getOperand(I).getReg(); 243 } 244 245 void LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, 246 LLT GCDTy, Register SrcReg) { 247 LLT SrcTy = MRI.getType(SrcReg); 248 if (SrcTy == GCDTy) { 249 // If the source already evenly divides the result type, we don't need to do 250 // anything. 251 Parts.push_back(SrcReg); 252 } else { 253 // Need to split into common type sized pieces. 254 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 255 getUnmergeResults(Parts, *Unmerge); 256 } 257 } 258 259 LLT LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy, 260 LLT NarrowTy, Register SrcReg) { 261 LLT SrcTy = MRI.getType(SrcReg); 262 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 263 extractGCDType(Parts, GCDTy, SrcReg); 264 return GCDTy; 265 } 266 267 LLT LegalizerHelper::buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy, 268 SmallVectorImpl<Register> &VRegs, 269 unsigned PadStrategy) { 270 LLT LCMTy = getLCMType(DstTy, NarrowTy); 271 272 int NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 273 int NumSubParts = NarrowTy.getSizeInBits() / GCDTy.getSizeInBits(); 274 int NumOrigSrc = VRegs.size(); 275 276 Register PadReg; 277 278 // Get a value we can use to pad the source value if the sources won't evenly 279 // cover the result type. 280 if (NumOrigSrc < NumParts * NumSubParts) { 281 if (PadStrategy == TargetOpcode::G_ZEXT) 282 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); 283 else if (PadStrategy == TargetOpcode::G_ANYEXT) 284 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 285 else { 286 assert(PadStrategy == TargetOpcode::G_SEXT); 287 288 // Shift the sign bit of the low register through the high register. 289 auto ShiftAmt = 290 MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1); 291 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0); 292 } 293 } 294 295 // Registers for the final merge to be produced. 296 SmallVector<Register, 4> Remerge(NumParts); 297 298 // Registers needed for intermediate merges, which will be merged into a 299 // source for Remerge. 300 SmallVector<Register, 4> SubMerge(NumSubParts); 301 302 // Once we've fully read off the end of the original source bits, we can reuse 303 // the same high bits for remaining padding elements. 304 Register AllPadReg; 305 306 // Build merges to the LCM type to cover the original result type. 307 for (int I = 0; I != NumParts; ++I) { 308 bool AllMergePartsArePadding = true; 309 310 // Build the requested merges to the requested type. 311 for (int J = 0; J != NumSubParts; ++J) { 312 int Idx = I * NumSubParts + J; 313 if (Idx >= NumOrigSrc) { 314 SubMerge[J] = PadReg; 315 continue; 316 } 317 318 SubMerge[J] = VRegs[Idx]; 319 320 // There are meaningful bits here we can't reuse later. 321 AllMergePartsArePadding = false; 322 } 323 324 // If we've filled up a complete piece with padding bits, we can directly 325 // emit the natural sized constant if applicable, rather than a merge of 326 // smaller constants. 327 if (AllMergePartsArePadding && !AllPadReg) { 328 if (PadStrategy == TargetOpcode::G_ANYEXT) 329 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); 330 else if (PadStrategy == TargetOpcode::G_ZEXT) 331 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); 332 333 // If this is a sign extension, we can't materialize a trivial constant 334 // with the right type and have to produce a merge. 335 } 336 337 if (AllPadReg) { 338 // Avoid creating additional instructions if we're just adding additional 339 // copies of padding bits. 340 Remerge[I] = AllPadReg; 341 continue; 342 } 343 344 if (NumSubParts == 1) 345 Remerge[I] = SubMerge[0]; 346 else 347 Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0); 348 349 // In the sign extend padding case, re-use the first all-signbit merge. 350 if (AllMergePartsArePadding && !AllPadReg) 351 AllPadReg = Remerge[I]; 352 } 353 354 VRegs = std::move(Remerge); 355 return LCMTy; 356 } 357 358 void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy, 359 ArrayRef<Register> RemergeRegs) { 360 LLT DstTy = MRI.getType(DstReg); 361 362 // Create the merge to the widened source, and extract the relevant bits into 363 // the result. 364 365 if (DstTy == LCMTy) { 366 MIRBuilder.buildMerge(DstReg, RemergeRegs); 367 return; 368 } 369 370 auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs); 371 if (DstTy.isScalar() && LCMTy.isScalar()) { 372 MIRBuilder.buildTrunc(DstReg, Remerge); 373 return; 374 } 375 376 if (LCMTy.isVector()) { 377 unsigned NumDefs = LCMTy.getSizeInBits() / DstTy.getSizeInBits(); 378 SmallVector<Register, 8> UnmergeDefs(NumDefs); 379 UnmergeDefs[0] = DstReg; 380 for (unsigned I = 1; I != NumDefs; ++I) 381 UnmergeDefs[I] = MRI.createGenericVirtualRegister(DstTy); 382 383 MIRBuilder.buildUnmerge(UnmergeDefs, 384 MIRBuilder.buildMerge(LCMTy, RemergeRegs)); 385 return; 386 } 387 388 llvm_unreachable("unhandled case"); 389 } 390 391 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) { 392 #define RTLIBCASE_INT(LibcallPrefix) \ 393 do { \ 394 switch (Size) { \ 395 case 32: \ 396 return RTLIB::LibcallPrefix##32; \ 397 case 64: \ 398 return RTLIB::LibcallPrefix##64; \ 399 case 128: \ 400 return RTLIB::LibcallPrefix##128; \ 401 default: \ 402 llvm_unreachable("unexpected size"); \ 403 } \ 404 } while (0) 405 406 #define RTLIBCASE(LibcallPrefix) \ 407 do { \ 408 switch (Size) { \ 409 case 32: \ 410 return RTLIB::LibcallPrefix##32; \ 411 case 64: \ 412 return RTLIB::LibcallPrefix##64; \ 413 case 80: \ 414 return RTLIB::LibcallPrefix##80; \ 415 case 128: \ 416 return RTLIB::LibcallPrefix##128; \ 417 default: \ 418 llvm_unreachable("unexpected size"); \ 419 } \ 420 } while (0) 421 422 switch (Opcode) { 423 case TargetOpcode::G_SDIV: 424 RTLIBCASE_INT(SDIV_I); 425 case TargetOpcode::G_UDIV: 426 RTLIBCASE_INT(UDIV_I); 427 case TargetOpcode::G_SREM: 428 RTLIBCASE_INT(SREM_I); 429 case TargetOpcode::G_UREM: 430 RTLIBCASE_INT(UREM_I); 431 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 432 RTLIBCASE_INT(CTLZ_I); 433 case TargetOpcode::G_FADD: 434 RTLIBCASE(ADD_F); 435 case TargetOpcode::G_FSUB: 436 RTLIBCASE(SUB_F); 437 case TargetOpcode::G_FMUL: 438 RTLIBCASE(MUL_F); 439 case TargetOpcode::G_FDIV: 440 RTLIBCASE(DIV_F); 441 case TargetOpcode::G_FEXP: 442 RTLIBCASE(EXP_F); 443 case TargetOpcode::G_FEXP2: 444 RTLIBCASE(EXP2_F); 445 case TargetOpcode::G_FREM: 446 RTLIBCASE(REM_F); 447 case TargetOpcode::G_FPOW: 448 RTLIBCASE(POW_F); 449 case TargetOpcode::G_FMA: 450 RTLIBCASE(FMA_F); 451 case TargetOpcode::G_FSIN: 452 RTLIBCASE(SIN_F); 453 case TargetOpcode::G_FCOS: 454 RTLIBCASE(COS_F); 455 case TargetOpcode::G_FLOG10: 456 RTLIBCASE(LOG10_F); 457 case TargetOpcode::G_FLOG: 458 RTLIBCASE(LOG_F); 459 case TargetOpcode::G_FLOG2: 460 RTLIBCASE(LOG2_F); 461 case TargetOpcode::G_FCEIL: 462 RTLIBCASE(CEIL_F); 463 case TargetOpcode::G_FFLOOR: 464 RTLIBCASE(FLOOR_F); 465 case TargetOpcode::G_FMINNUM: 466 RTLIBCASE(FMIN_F); 467 case TargetOpcode::G_FMAXNUM: 468 RTLIBCASE(FMAX_F); 469 case TargetOpcode::G_FSQRT: 470 RTLIBCASE(SQRT_F); 471 case TargetOpcode::G_FRINT: 472 RTLIBCASE(RINT_F); 473 case TargetOpcode::G_FNEARBYINT: 474 RTLIBCASE(NEARBYINT_F); 475 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 476 RTLIBCASE(ROUNDEVEN_F); 477 } 478 llvm_unreachable("Unknown libcall function"); 479 } 480 481 /// True if an instruction is in tail position in its caller. Intended for 482 /// legalizing libcalls as tail calls when possible. 483 static bool isLibCallInTailPosition(const TargetInstrInfo &TII, 484 MachineInstr &MI) { 485 MachineBasicBlock &MBB = *MI.getParent(); 486 const Function &F = MBB.getParent()->getFunction(); 487 488 // Conservatively require the attributes of the call to match those of 489 // the return. Ignore NoAlias and NonNull because they don't affect the 490 // call sequence. 491 AttributeList CallerAttrs = F.getAttributes(); 492 if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex) 493 .removeAttribute(Attribute::NoAlias) 494 .removeAttribute(Attribute::NonNull) 495 .hasAttributes()) 496 return false; 497 498 // It's not safe to eliminate the sign / zero extension of the return value. 499 if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) || 500 CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 501 return false; 502 503 // Only tail call if the following instruction is a standard return. 504 auto Next = next_nodbg(MI.getIterator(), MBB.instr_end()); 505 if (Next == MBB.instr_end() || TII.isTailCall(*Next) || !Next->isReturn()) 506 return false; 507 508 return true; 509 } 510 511 LegalizerHelper::LegalizeResult 512 llvm::createLibcall(MachineIRBuilder &MIRBuilder, const char *Name, 513 const CallLowering::ArgInfo &Result, 514 ArrayRef<CallLowering::ArgInfo> Args, 515 const CallingConv::ID CC) { 516 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 517 518 CallLowering::CallLoweringInfo Info; 519 Info.CallConv = CC; 520 Info.Callee = MachineOperand::CreateES(Name); 521 Info.OrigRet = Result; 522 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 523 if (!CLI.lowerCall(MIRBuilder, Info)) 524 return LegalizerHelper::UnableToLegalize; 525 526 return LegalizerHelper::Legalized; 527 } 528 529 LegalizerHelper::LegalizeResult 530 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall, 531 const CallLowering::ArgInfo &Result, 532 ArrayRef<CallLowering::ArgInfo> Args) { 533 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 534 const char *Name = TLI.getLibcallName(Libcall); 535 const CallingConv::ID CC = TLI.getLibcallCallingConv(Libcall); 536 return createLibcall(MIRBuilder, Name, Result, Args, CC); 537 } 538 539 // Useful for libcalls where all operands have the same type. 540 static LegalizerHelper::LegalizeResult 541 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size, 542 Type *OpType) { 543 auto Libcall = getRTLibDesc(MI.getOpcode(), Size); 544 545 // FIXME: What does the original arg index mean here? 546 SmallVector<CallLowering::ArgInfo, 3> Args; 547 for (unsigned i = 1; i < MI.getNumOperands(); i++) 548 Args.push_back({MI.getOperand(i).getReg(), OpType, 0}); 549 return createLibcall(MIRBuilder, Libcall, 550 {MI.getOperand(0).getReg(), OpType, 0}, Args); 551 } 552 553 LegalizerHelper::LegalizeResult 554 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 555 MachineInstr &MI, LostDebugLocObserver &LocObserver) { 556 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 557 558 SmallVector<CallLowering::ArgInfo, 3> Args; 559 // Add all the args, except for the last which is an imm denoting 'tail'. 560 for (unsigned i = 0; i < MI.getNumOperands() - 1; ++i) { 561 Register Reg = MI.getOperand(i).getReg(); 562 563 // Need derive an IR type for call lowering. 564 LLT OpLLT = MRI.getType(Reg); 565 Type *OpTy = nullptr; 566 if (OpLLT.isPointer()) 567 OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace()); 568 else 569 OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits()); 570 Args.push_back({Reg, OpTy, 0}); 571 } 572 573 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 574 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 575 RTLIB::Libcall RTLibcall; 576 unsigned Opc = MI.getOpcode(); 577 switch (Opc) { 578 case TargetOpcode::G_BZERO: 579 RTLibcall = RTLIB::BZERO; 580 break; 581 case TargetOpcode::G_MEMCPY: 582 RTLibcall = RTLIB::MEMCPY; 583 break; 584 case TargetOpcode::G_MEMMOVE: 585 RTLibcall = RTLIB::MEMMOVE; 586 break; 587 case TargetOpcode::G_MEMSET: 588 RTLibcall = RTLIB::MEMSET; 589 break; 590 default: 591 return LegalizerHelper::UnableToLegalize; 592 } 593 const char *Name = TLI.getLibcallName(RTLibcall); 594 595 // Unsupported libcall on the target. 596 if (!Name) { 597 LLVM_DEBUG(dbgs() << ".. .. Could not find libcall name for " 598 << MIRBuilder.getTII().getName(Opc) << "\n"); 599 return LegalizerHelper::UnableToLegalize; 600 } 601 602 CallLowering::CallLoweringInfo Info; 603 Info.CallConv = TLI.getLibcallCallingConv(RTLibcall); 604 Info.Callee = MachineOperand::CreateES(Name); 605 Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx), 0); 606 Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() && 607 isLibCallInTailPosition(MIRBuilder.getTII(), MI); 608 609 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 610 if (!CLI.lowerCall(MIRBuilder, Info)) 611 return LegalizerHelper::UnableToLegalize; 612 613 614 if (Info.LoweredTailCall) { 615 assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?"); 616 617 // Check debug locations before removing the return. 618 LocObserver.checkpoint(true); 619 620 // We must have a return following the call (or debug insts) to get past 621 // isLibCallInTailPosition. 622 do { 623 MachineInstr *Next = MI.getNextNode(); 624 assert(Next && (Next->isReturn() || Next->isDebugInstr()) && 625 "Expected instr following MI to be return or debug inst?"); 626 // We lowered a tail call, so the call is now the return from the block. 627 // Delete the old return. 628 Next->eraseFromParent(); 629 } while (MI.getNextNode()); 630 631 // We expect to lose the debug location from the return. 632 LocObserver.checkpoint(false); 633 } 634 635 return LegalizerHelper::Legalized; 636 } 637 638 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType, 639 Type *FromType) { 640 auto ToMVT = MVT::getVT(ToType); 641 auto FromMVT = MVT::getVT(FromType); 642 643 switch (Opcode) { 644 case TargetOpcode::G_FPEXT: 645 return RTLIB::getFPEXT(FromMVT, ToMVT); 646 case TargetOpcode::G_FPTRUNC: 647 return RTLIB::getFPROUND(FromMVT, ToMVT); 648 case TargetOpcode::G_FPTOSI: 649 return RTLIB::getFPTOSINT(FromMVT, ToMVT); 650 case TargetOpcode::G_FPTOUI: 651 return RTLIB::getFPTOUINT(FromMVT, ToMVT); 652 case TargetOpcode::G_SITOFP: 653 return RTLIB::getSINTTOFP(FromMVT, ToMVT); 654 case TargetOpcode::G_UITOFP: 655 return RTLIB::getUINTTOFP(FromMVT, ToMVT); 656 } 657 llvm_unreachable("Unsupported libcall function"); 658 } 659 660 static LegalizerHelper::LegalizeResult 661 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType, 662 Type *FromType) { 663 RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType); 664 return createLibcall(MIRBuilder, Libcall, 665 {MI.getOperand(0).getReg(), ToType, 0}, 666 {{MI.getOperand(1).getReg(), FromType, 0}}); 667 } 668 669 LegalizerHelper::LegalizeResult 670 LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) { 671 LLT LLTy = MRI.getType(MI.getOperand(0).getReg()); 672 unsigned Size = LLTy.getSizeInBits(); 673 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 674 675 switch (MI.getOpcode()) { 676 default: 677 return UnableToLegalize; 678 case TargetOpcode::G_SDIV: 679 case TargetOpcode::G_UDIV: 680 case TargetOpcode::G_SREM: 681 case TargetOpcode::G_UREM: 682 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 683 Type *HLTy = IntegerType::get(Ctx, Size); 684 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 685 if (Status != Legalized) 686 return Status; 687 break; 688 } 689 case TargetOpcode::G_FADD: 690 case TargetOpcode::G_FSUB: 691 case TargetOpcode::G_FMUL: 692 case TargetOpcode::G_FDIV: 693 case TargetOpcode::G_FMA: 694 case TargetOpcode::G_FPOW: 695 case TargetOpcode::G_FREM: 696 case TargetOpcode::G_FCOS: 697 case TargetOpcode::G_FSIN: 698 case TargetOpcode::G_FLOG10: 699 case TargetOpcode::G_FLOG: 700 case TargetOpcode::G_FLOG2: 701 case TargetOpcode::G_FEXP: 702 case TargetOpcode::G_FEXP2: 703 case TargetOpcode::G_FCEIL: 704 case TargetOpcode::G_FFLOOR: 705 case TargetOpcode::G_FMINNUM: 706 case TargetOpcode::G_FMAXNUM: 707 case TargetOpcode::G_FSQRT: 708 case TargetOpcode::G_FRINT: 709 case TargetOpcode::G_FNEARBYINT: 710 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 711 Type *HLTy = getFloatTypeForLLT(Ctx, LLTy); 712 if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) { 713 LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n"); 714 return UnableToLegalize; 715 } 716 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 717 if (Status != Legalized) 718 return Status; 719 break; 720 } 721 case TargetOpcode::G_FPEXT: 722 case TargetOpcode::G_FPTRUNC: { 723 Type *FromTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(1).getReg())); 724 Type *ToTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(0).getReg())); 725 if (!FromTy || !ToTy) 726 return UnableToLegalize; 727 LegalizeResult Status = conversionLibcall(MI, MIRBuilder, ToTy, FromTy ); 728 if (Status != Legalized) 729 return Status; 730 break; 731 } 732 case TargetOpcode::G_FPTOSI: 733 case TargetOpcode::G_FPTOUI: { 734 // FIXME: Support other types 735 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 736 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 737 if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64)) 738 return UnableToLegalize; 739 LegalizeResult Status = conversionLibcall( 740 MI, MIRBuilder, 741 ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx), 742 FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx)); 743 if (Status != Legalized) 744 return Status; 745 break; 746 } 747 case TargetOpcode::G_SITOFP: 748 case TargetOpcode::G_UITOFP: { 749 // FIXME: Support other types 750 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 751 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 752 if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64)) 753 return UnableToLegalize; 754 LegalizeResult Status = conversionLibcall( 755 MI, MIRBuilder, 756 ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx), 757 FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx)); 758 if (Status != Legalized) 759 return Status; 760 break; 761 } 762 case TargetOpcode::G_BZERO: 763 case TargetOpcode::G_MEMCPY: 764 case TargetOpcode::G_MEMMOVE: 765 case TargetOpcode::G_MEMSET: { 766 LegalizeResult Result = 767 createMemLibcall(MIRBuilder, *MIRBuilder.getMRI(), MI, LocObserver); 768 if (Result != Legalized) 769 return Result; 770 MI.eraseFromParent(); 771 return Result; 772 } 773 } 774 775 MI.eraseFromParent(); 776 return Legalized; 777 } 778 779 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, 780 unsigned TypeIdx, 781 LLT NarrowTy) { 782 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 783 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 784 785 switch (MI.getOpcode()) { 786 default: 787 return UnableToLegalize; 788 case TargetOpcode::G_IMPLICIT_DEF: { 789 Register DstReg = MI.getOperand(0).getReg(); 790 LLT DstTy = MRI.getType(DstReg); 791 792 // If SizeOp0 is not an exact multiple of NarrowSize, emit 793 // G_ANYEXT(G_IMPLICIT_DEF). Cast result to vector if needed. 794 // FIXME: Although this would also be legal for the general case, it causes 795 // a lot of regressions in the emitted code (superfluous COPYs, artifact 796 // combines not being hit). This seems to be a problem related to the 797 // artifact combiner. 798 if (SizeOp0 % NarrowSize != 0) { 799 LLT ImplicitTy = NarrowTy; 800 if (DstTy.isVector()) 801 ImplicitTy = LLT::vector(DstTy.getElementCount(), ImplicitTy); 802 803 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); 804 MIRBuilder.buildAnyExt(DstReg, ImplicitReg); 805 806 MI.eraseFromParent(); 807 return Legalized; 808 } 809 810 int NumParts = SizeOp0 / NarrowSize; 811 812 SmallVector<Register, 2> DstRegs; 813 for (int i = 0; i < NumParts; ++i) 814 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); 815 816 if (DstTy.isVector()) 817 MIRBuilder.buildBuildVector(DstReg, DstRegs); 818 else 819 MIRBuilder.buildMerge(DstReg, DstRegs); 820 MI.eraseFromParent(); 821 return Legalized; 822 } 823 case TargetOpcode::G_CONSTANT: { 824 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 825 const APInt &Val = MI.getOperand(1).getCImm()->getValue(); 826 unsigned TotalSize = Ty.getSizeInBits(); 827 unsigned NarrowSize = NarrowTy.getSizeInBits(); 828 int NumParts = TotalSize / NarrowSize; 829 830 SmallVector<Register, 4> PartRegs; 831 for (int I = 0; I != NumParts; ++I) { 832 unsigned Offset = I * NarrowSize; 833 auto K = MIRBuilder.buildConstant(NarrowTy, 834 Val.lshr(Offset).trunc(NarrowSize)); 835 PartRegs.push_back(K.getReg(0)); 836 } 837 838 LLT LeftoverTy; 839 unsigned LeftoverBits = TotalSize - NumParts * NarrowSize; 840 SmallVector<Register, 1> LeftoverRegs; 841 if (LeftoverBits != 0) { 842 LeftoverTy = LLT::scalar(LeftoverBits); 843 auto K = MIRBuilder.buildConstant( 844 LeftoverTy, 845 Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits)); 846 LeftoverRegs.push_back(K.getReg(0)); 847 } 848 849 insertParts(MI.getOperand(0).getReg(), 850 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs); 851 852 MI.eraseFromParent(); 853 return Legalized; 854 } 855 case TargetOpcode::G_SEXT: 856 case TargetOpcode::G_ZEXT: 857 case TargetOpcode::G_ANYEXT: 858 return narrowScalarExt(MI, TypeIdx, NarrowTy); 859 case TargetOpcode::G_TRUNC: { 860 if (TypeIdx != 1) 861 return UnableToLegalize; 862 863 uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 864 if (NarrowTy.getSizeInBits() * 2 != SizeOp1) { 865 LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n"); 866 return UnableToLegalize; 867 } 868 869 auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 870 MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0)); 871 MI.eraseFromParent(); 872 return Legalized; 873 } 874 875 case TargetOpcode::G_FREEZE: 876 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 877 case TargetOpcode::G_ADD: 878 case TargetOpcode::G_SUB: 879 case TargetOpcode::G_SADDO: 880 case TargetOpcode::G_SSUBO: 881 case TargetOpcode::G_SADDE: 882 case TargetOpcode::G_SSUBE: 883 case TargetOpcode::G_UADDO: 884 case TargetOpcode::G_USUBO: 885 case TargetOpcode::G_UADDE: 886 case TargetOpcode::G_USUBE: 887 return narrowScalarAddSub(MI, TypeIdx, NarrowTy); 888 case TargetOpcode::G_MUL: 889 case TargetOpcode::G_UMULH: 890 return narrowScalarMul(MI, NarrowTy); 891 case TargetOpcode::G_EXTRACT: 892 return narrowScalarExtract(MI, TypeIdx, NarrowTy); 893 case TargetOpcode::G_INSERT: 894 return narrowScalarInsert(MI, TypeIdx, NarrowTy); 895 case TargetOpcode::G_LOAD: { 896 auto &LoadMI = cast<GLoad>(MI); 897 Register DstReg = LoadMI.getDstReg(); 898 LLT DstTy = MRI.getType(DstReg); 899 if (DstTy.isVector()) 900 return UnableToLegalize; 901 902 if (8 * LoadMI.getMemSize() != DstTy.getSizeInBits()) { 903 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 904 MIRBuilder.buildLoad(TmpReg, LoadMI.getPointerReg(), LoadMI.getMMO()); 905 MIRBuilder.buildAnyExt(DstReg, TmpReg); 906 LoadMI.eraseFromParent(); 907 return Legalized; 908 } 909 910 return reduceLoadStoreWidth(LoadMI, TypeIdx, NarrowTy); 911 } 912 case TargetOpcode::G_ZEXTLOAD: 913 case TargetOpcode::G_SEXTLOAD: { 914 auto &LoadMI = cast<GExtLoad>(MI); 915 Register DstReg = LoadMI.getDstReg(); 916 Register PtrReg = LoadMI.getPointerReg(); 917 918 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 919 auto &MMO = LoadMI.getMMO(); 920 unsigned MemSize = MMO.getSizeInBits(); 921 922 if (MemSize == NarrowSize) { 923 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); 924 } else if (MemSize < NarrowSize) { 925 MIRBuilder.buildLoadInstr(LoadMI.getOpcode(), TmpReg, PtrReg, MMO); 926 } else if (MemSize > NarrowSize) { 927 // FIXME: Need to split the load. 928 return UnableToLegalize; 929 } 930 931 if (isa<GZExtLoad>(LoadMI)) 932 MIRBuilder.buildZExt(DstReg, TmpReg); 933 else 934 MIRBuilder.buildSExt(DstReg, TmpReg); 935 936 LoadMI.eraseFromParent(); 937 return Legalized; 938 } 939 case TargetOpcode::G_STORE: { 940 auto &StoreMI = cast<GStore>(MI); 941 942 Register SrcReg = StoreMI.getValueReg(); 943 LLT SrcTy = MRI.getType(SrcReg); 944 if (SrcTy.isVector()) 945 return UnableToLegalize; 946 947 int NumParts = SizeOp0 / NarrowSize; 948 unsigned HandledSize = NumParts * NarrowTy.getSizeInBits(); 949 unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize; 950 if (SrcTy.isVector() && LeftoverBits != 0) 951 return UnableToLegalize; 952 953 if (8 * StoreMI.getMemSize() != SrcTy.getSizeInBits()) { 954 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 955 MIRBuilder.buildTrunc(TmpReg, SrcReg); 956 MIRBuilder.buildStore(TmpReg, StoreMI.getPointerReg(), StoreMI.getMMO()); 957 StoreMI.eraseFromParent(); 958 return Legalized; 959 } 960 961 return reduceLoadStoreWidth(StoreMI, 0, NarrowTy); 962 } 963 case TargetOpcode::G_SELECT: 964 return narrowScalarSelect(MI, TypeIdx, NarrowTy); 965 case TargetOpcode::G_AND: 966 case TargetOpcode::G_OR: 967 case TargetOpcode::G_XOR: { 968 // Legalize bitwise operation: 969 // A = BinOp<Ty> B, C 970 // into: 971 // B1, ..., BN = G_UNMERGE_VALUES B 972 // C1, ..., CN = G_UNMERGE_VALUES C 973 // A1 = BinOp<Ty/N> B1, C2 974 // ... 975 // AN = BinOp<Ty/N> BN, CN 976 // A = G_MERGE_VALUES A1, ..., AN 977 return narrowScalarBasic(MI, TypeIdx, NarrowTy); 978 } 979 case TargetOpcode::G_SHL: 980 case TargetOpcode::G_LSHR: 981 case TargetOpcode::G_ASHR: 982 return narrowScalarShift(MI, TypeIdx, NarrowTy); 983 case TargetOpcode::G_CTLZ: 984 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 985 case TargetOpcode::G_CTTZ: 986 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 987 case TargetOpcode::G_CTPOP: 988 if (TypeIdx == 1) 989 switch (MI.getOpcode()) { 990 case TargetOpcode::G_CTLZ: 991 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 992 return narrowScalarCTLZ(MI, TypeIdx, NarrowTy); 993 case TargetOpcode::G_CTTZ: 994 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 995 return narrowScalarCTTZ(MI, TypeIdx, NarrowTy); 996 case TargetOpcode::G_CTPOP: 997 return narrowScalarCTPOP(MI, TypeIdx, NarrowTy); 998 default: 999 return UnableToLegalize; 1000 } 1001 1002 Observer.changingInstr(MI); 1003 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1004 Observer.changedInstr(MI); 1005 return Legalized; 1006 case TargetOpcode::G_INTTOPTR: 1007 if (TypeIdx != 1) 1008 return UnableToLegalize; 1009 1010 Observer.changingInstr(MI); 1011 narrowScalarSrc(MI, NarrowTy, 1); 1012 Observer.changedInstr(MI); 1013 return Legalized; 1014 case TargetOpcode::G_PTRTOINT: 1015 if (TypeIdx != 0) 1016 return UnableToLegalize; 1017 1018 Observer.changingInstr(MI); 1019 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1020 Observer.changedInstr(MI); 1021 return Legalized; 1022 case TargetOpcode::G_PHI: { 1023 // FIXME: add support for when SizeOp0 isn't an exact multiple of 1024 // NarrowSize. 1025 if (SizeOp0 % NarrowSize != 0) 1026 return UnableToLegalize; 1027 1028 unsigned NumParts = SizeOp0 / NarrowSize; 1029 SmallVector<Register, 2> DstRegs(NumParts); 1030 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2); 1031 Observer.changingInstr(MI); 1032 for (unsigned i = 1; i < MI.getNumOperands(); i += 2) { 1033 MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB(); 1034 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 1035 extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts, 1036 SrcRegs[i / 2]); 1037 } 1038 MachineBasicBlock &MBB = *MI.getParent(); 1039 MIRBuilder.setInsertPt(MBB, MI); 1040 for (unsigned i = 0; i < NumParts; ++i) { 1041 DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy); 1042 MachineInstrBuilder MIB = 1043 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); 1044 for (unsigned j = 1; j < MI.getNumOperands(); j += 2) 1045 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); 1046 } 1047 MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI()); 1048 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1049 Observer.changedInstr(MI); 1050 MI.eraseFromParent(); 1051 return Legalized; 1052 } 1053 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 1054 case TargetOpcode::G_INSERT_VECTOR_ELT: { 1055 if (TypeIdx != 2) 1056 return UnableToLegalize; 1057 1058 int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3; 1059 Observer.changingInstr(MI); 1060 narrowScalarSrc(MI, NarrowTy, OpIdx); 1061 Observer.changedInstr(MI); 1062 return Legalized; 1063 } 1064 case TargetOpcode::G_ICMP: { 1065 Register LHS = MI.getOperand(2).getReg(); 1066 LLT SrcTy = MRI.getType(LHS); 1067 uint64_t SrcSize = SrcTy.getSizeInBits(); 1068 CmpInst::Predicate Pred = 1069 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 1070 1071 // TODO: Handle the non-equality case for weird sizes. 1072 if (NarrowSize * 2 != SrcSize && !ICmpInst::isEquality(Pred)) 1073 return UnableToLegalize; 1074 1075 LLT LeftoverTy; // Example: s88 -> s64 (NarrowTy) + s24 (leftover) 1076 SmallVector<Register, 4> LHSPartRegs, LHSLeftoverRegs; 1077 if (!extractParts(LHS, SrcTy, NarrowTy, LeftoverTy, LHSPartRegs, 1078 LHSLeftoverRegs)) 1079 return UnableToLegalize; 1080 1081 LLT Unused; // Matches LeftoverTy; G_ICMP LHS and RHS are the same type. 1082 SmallVector<Register, 4> RHSPartRegs, RHSLeftoverRegs; 1083 if (!extractParts(MI.getOperand(3).getReg(), SrcTy, NarrowTy, Unused, 1084 RHSPartRegs, RHSLeftoverRegs)) 1085 return UnableToLegalize; 1086 1087 // We now have the LHS and RHS of the compare split into narrow-type 1088 // registers, plus potentially some leftover type. 1089 Register Dst = MI.getOperand(0).getReg(); 1090 LLT ResTy = MRI.getType(Dst); 1091 if (ICmpInst::isEquality(Pred)) { 1092 // For each part on the LHS and RHS, keep track of the result of XOR-ing 1093 // them together. For each equal part, the result should be all 0s. For 1094 // each non-equal part, we'll get at least one 1. 1095 auto Zero = MIRBuilder.buildConstant(NarrowTy, 0); 1096 SmallVector<Register, 4> Xors; 1097 for (auto LHSAndRHS : zip(LHSPartRegs, RHSPartRegs)) { 1098 auto LHS = std::get<0>(LHSAndRHS); 1099 auto RHS = std::get<1>(LHSAndRHS); 1100 auto Xor = MIRBuilder.buildXor(NarrowTy, LHS, RHS).getReg(0); 1101 Xors.push_back(Xor); 1102 } 1103 1104 // Build a G_XOR for each leftover register. Each G_XOR must be widened 1105 // to the desired narrow type so that we can OR them together later. 1106 SmallVector<Register, 4> WidenedXors; 1107 for (auto LHSAndRHS : zip(LHSLeftoverRegs, RHSLeftoverRegs)) { 1108 auto LHS = std::get<0>(LHSAndRHS); 1109 auto RHS = std::get<1>(LHSAndRHS); 1110 auto Xor = MIRBuilder.buildXor(LeftoverTy, LHS, RHS).getReg(0); 1111 LLT GCDTy = extractGCDType(WidenedXors, NarrowTy, LeftoverTy, Xor); 1112 buildLCMMergePieces(LeftoverTy, NarrowTy, GCDTy, WidenedXors, 1113 /* PadStrategy = */ TargetOpcode::G_ZEXT); 1114 Xors.insert(Xors.end(), WidenedXors.begin(), WidenedXors.end()); 1115 } 1116 1117 // Now, for each part we broke up, we know if they are equal/not equal 1118 // based off the G_XOR. We can OR these all together and compare against 1119 // 0 to get the result. 1120 assert(Xors.size() >= 2 && "Should have gotten at least two Xors?"); 1121 auto Or = MIRBuilder.buildOr(NarrowTy, Xors[0], Xors[1]); 1122 for (unsigned I = 2, E = Xors.size(); I < E; ++I) 1123 Or = MIRBuilder.buildOr(NarrowTy, Or, Xors[I]); 1124 MIRBuilder.buildICmp(Pred, Dst, Or, Zero); 1125 } else { 1126 // TODO: Handle non-power-of-two types. 1127 assert(LHSPartRegs.size() == 2 && "Expected exactly 2 LHS part regs?"); 1128 assert(RHSPartRegs.size() == 2 && "Expected exactly 2 RHS part regs?"); 1129 Register LHSL = LHSPartRegs[0]; 1130 Register LHSH = LHSPartRegs[1]; 1131 Register RHSL = RHSPartRegs[0]; 1132 Register RHSH = RHSPartRegs[1]; 1133 MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH); 1134 MachineInstrBuilder CmpHEQ = 1135 MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH); 1136 MachineInstrBuilder CmpLU = MIRBuilder.buildICmp( 1137 ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL); 1138 MIRBuilder.buildSelect(Dst, CmpHEQ, CmpLU, CmpH); 1139 } 1140 MI.eraseFromParent(); 1141 return Legalized; 1142 } 1143 case TargetOpcode::G_SEXT_INREG: { 1144 if (TypeIdx != 0) 1145 return UnableToLegalize; 1146 1147 int64_t SizeInBits = MI.getOperand(2).getImm(); 1148 1149 // So long as the new type has more bits than the bits we're extending we 1150 // don't need to break it apart. 1151 if (NarrowTy.getScalarSizeInBits() >= SizeInBits) { 1152 Observer.changingInstr(MI); 1153 // We don't lose any non-extension bits by truncating the src and 1154 // sign-extending the dst. 1155 MachineOperand &MO1 = MI.getOperand(1); 1156 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1); 1157 MO1.setReg(TruncMIB.getReg(0)); 1158 1159 MachineOperand &MO2 = MI.getOperand(0); 1160 Register DstExt = MRI.createGenericVirtualRegister(NarrowTy); 1161 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1162 MIRBuilder.buildSExt(MO2, DstExt); 1163 MO2.setReg(DstExt); 1164 Observer.changedInstr(MI); 1165 return Legalized; 1166 } 1167 1168 // Break it apart. Components below the extension point are unmodified. The 1169 // component containing the extension point becomes a narrower SEXT_INREG. 1170 // Components above it are ashr'd from the component containing the 1171 // extension point. 1172 if (SizeOp0 % NarrowSize != 0) 1173 return UnableToLegalize; 1174 int NumParts = SizeOp0 / NarrowSize; 1175 1176 // List the registers where the destination will be scattered. 1177 SmallVector<Register, 2> DstRegs; 1178 // List the registers where the source will be split. 1179 SmallVector<Register, 2> SrcRegs; 1180 1181 // Create all the temporary registers. 1182 for (int i = 0; i < NumParts; ++i) { 1183 Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy); 1184 1185 SrcRegs.push_back(SrcReg); 1186 } 1187 1188 // Explode the big arguments into smaller chunks. 1189 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1)); 1190 1191 Register AshrCstReg = 1192 MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1) 1193 .getReg(0); 1194 Register FullExtensionReg = 0; 1195 Register PartialExtensionReg = 0; 1196 1197 // Do the operation on each small part. 1198 for (int i = 0; i < NumParts; ++i) { 1199 if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits) 1200 DstRegs.push_back(SrcRegs[i]); 1201 else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) { 1202 assert(PartialExtensionReg && 1203 "Expected to visit partial extension before full"); 1204 if (FullExtensionReg) { 1205 DstRegs.push_back(FullExtensionReg); 1206 continue; 1207 } 1208 DstRegs.push_back( 1209 MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg) 1210 .getReg(0)); 1211 FullExtensionReg = DstRegs.back(); 1212 } else { 1213 DstRegs.push_back( 1214 MIRBuilder 1215 .buildInstr( 1216 TargetOpcode::G_SEXT_INREG, {NarrowTy}, 1217 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) 1218 .getReg(0)); 1219 PartialExtensionReg = DstRegs.back(); 1220 } 1221 } 1222 1223 // Gather the destination registers into the final destination. 1224 Register DstReg = MI.getOperand(0).getReg(); 1225 MIRBuilder.buildMerge(DstReg, DstRegs); 1226 MI.eraseFromParent(); 1227 return Legalized; 1228 } 1229 case TargetOpcode::G_BSWAP: 1230 case TargetOpcode::G_BITREVERSE: { 1231 if (SizeOp0 % NarrowSize != 0) 1232 return UnableToLegalize; 1233 1234 Observer.changingInstr(MI); 1235 SmallVector<Register, 2> SrcRegs, DstRegs; 1236 unsigned NumParts = SizeOp0 / NarrowSize; 1237 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 1238 1239 for (unsigned i = 0; i < NumParts; ++i) { 1240 auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 1241 {SrcRegs[NumParts - 1 - i]}); 1242 DstRegs.push_back(DstPart.getReg(0)); 1243 } 1244 1245 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1246 1247 Observer.changedInstr(MI); 1248 MI.eraseFromParent(); 1249 return Legalized; 1250 } 1251 case TargetOpcode::G_PTR_ADD: 1252 case TargetOpcode::G_PTRMASK: { 1253 if (TypeIdx != 1) 1254 return UnableToLegalize; 1255 Observer.changingInstr(MI); 1256 narrowScalarSrc(MI, NarrowTy, 2); 1257 Observer.changedInstr(MI); 1258 return Legalized; 1259 } 1260 case TargetOpcode::G_FPTOUI: 1261 case TargetOpcode::G_FPTOSI: 1262 return narrowScalarFPTOI(MI, TypeIdx, NarrowTy); 1263 case TargetOpcode::G_FPEXT: 1264 if (TypeIdx != 0) 1265 return UnableToLegalize; 1266 Observer.changingInstr(MI); 1267 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_FPEXT); 1268 Observer.changedInstr(MI); 1269 return Legalized; 1270 } 1271 } 1272 1273 Register LegalizerHelper::coerceToScalar(Register Val) { 1274 LLT Ty = MRI.getType(Val); 1275 if (Ty.isScalar()) 1276 return Val; 1277 1278 const DataLayout &DL = MIRBuilder.getDataLayout(); 1279 LLT NewTy = LLT::scalar(Ty.getSizeInBits()); 1280 if (Ty.isPointer()) { 1281 if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace())) 1282 return Register(); 1283 return MIRBuilder.buildPtrToInt(NewTy, Val).getReg(0); 1284 } 1285 1286 Register NewVal = Val; 1287 1288 assert(Ty.isVector()); 1289 LLT EltTy = Ty.getElementType(); 1290 if (EltTy.isPointer()) 1291 NewVal = MIRBuilder.buildPtrToInt(NewTy, NewVal).getReg(0); 1292 return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0); 1293 } 1294 1295 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy, 1296 unsigned OpIdx, unsigned ExtOpcode) { 1297 MachineOperand &MO = MI.getOperand(OpIdx); 1298 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO}); 1299 MO.setReg(ExtB.getReg(0)); 1300 } 1301 1302 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, 1303 unsigned OpIdx) { 1304 MachineOperand &MO = MI.getOperand(OpIdx); 1305 auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO); 1306 MO.setReg(ExtB.getReg(0)); 1307 } 1308 1309 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy, 1310 unsigned OpIdx, unsigned TruncOpcode) { 1311 MachineOperand &MO = MI.getOperand(OpIdx); 1312 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1313 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1314 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); 1315 MO.setReg(DstExt); 1316 } 1317 1318 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy, 1319 unsigned OpIdx, unsigned ExtOpcode) { 1320 MachineOperand &MO = MI.getOperand(OpIdx); 1321 Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy); 1322 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1323 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); 1324 MO.setReg(DstTrunc); 1325 } 1326 1327 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy, 1328 unsigned OpIdx) { 1329 MachineOperand &MO = MI.getOperand(OpIdx); 1330 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1331 MO.setReg(widenWithUnmerge(WideTy, MO.getReg())); 1332 } 1333 1334 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, 1335 unsigned OpIdx) { 1336 MachineOperand &MO = MI.getOperand(OpIdx); 1337 1338 LLT OldTy = MRI.getType(MO.getReg()); 1339 unsigned OldElts = OldTy.getNumElements(); 1340 unsigned NewElts = MoreTy.getNumElements(); 1341 1342 unsigned NumParts = NewElts / OldElts; 1343 1344 // Use concat_vectors if the result is a multiple of the number of elements. 1345 if (NumParts * OldElts == NewElts) { 1346 SmallVector<Register, 8> Parts; 1347 Parts.push_back(MO.getReg()); 1348 1349 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); 1350 for (unsigned I = 1; I != NumParts; ++I) 1351 Parts.push_back(ImpDef); 1352 1353 auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts); 1354 MO.setReg(Concat.getReg(0)); 1355 return; 1356 } 1357 1358 Register MoreReg = MRI.createGenericVirtualRegister(MoreTy); 1359 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); 1360 MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0); 1361 MO.setReg(MoreReg); 1362 } 1363 1364 void LegalizerHelper::bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1365 MachineOperand &Op = MI.getOperand(OpIdx); 1366 Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0)); 1367 } 1368 1369 void LegalizerHelper::bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1370 MachineOperand &MO = MI.getOperand(OpIdx); 1371 Register CastDst = MRI.createGenericVirtualRegister(CastTy); 1372 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1373 MIRBuilder.buildBitcast(MO, CastDst); 1374 MO.setReg(CastDst); 1375 } 1376 1377 LegalizerHelper::LegalizeResult 1378 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, 1379 LLT WideTy) { 1380 if (TypeIdx != 1) 1381 return UnableToLegalize; 1382 1383 Register DstReg = MI.getOperand(0).getReg(); 1384 LLT DstTy = MRI.getType(DstReg); 1385 if (DstTy.isVector()) 1386 return UnableToLegalize; 1387 1388 Register Src1 = MI.getOperand(1).getReg(); 1389 LLT SrcTy = MRI.getType(Src1); 1390 const int DstSize = DstTy.getSizeInBits(); 1391 const int SrcSize = SrcTy.getSizeInBits(); 1392 const int WideSize = WideTy.getSizeInBits(); 1393 const int NumMerge = (DstSize + WideSize - 1) / WideSize; 1394 1395 unsigned NumOps = MI.getNumOperands(); 1396 unsigned NumSrc = MI.getNumOperands() - 1; 1397 unsigned PartSize = DstTy.getSizeInBits() / NumSrc; 1398 1399 if (WideSize >= DstSize) { 1400 // Directly pack the bits in the target type. 1401 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); 1402 1403 for (unsigned I = 2; I != NumOps; ++I) { 1404 const unsigned Offset = (I - 1) * PartSize; 1405 1406 Register SrcReg = MI.getOperand(I).getReg(); 1407 assert(MRI.getType(SrcReg) == LLT::scalar(PartSize)); 1408 1409 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 1410 1411 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 1412 MRI.createGenericVirtualRegister(WideTy); 1413 1414 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 1415 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 1416 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 1417 ResultReg = NextResult; 1418 } 1419 1420 if (WideSize > DstSize) 1421 MIRBuilder.buildTrunc(DstReg, ResultReg); 1422 else if (DstTy.isPointer()) 1423 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 1424 1425 MI.eraseFromParent(); 1426 return Legalized; 1427 } 1428 1429 // Unmerge the original values to the GCD type, and recombine to the next 1430 // multiple greater than the original type. 1431 // 1432 // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6 1433 // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0 1434 // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1 1435 // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2 1436 // %10:_(s6) = G_MERGE_VALUES %4, %5, %6 1437 // %11:_(s6) = G_MERGE_VALUES %7, %8, %9 1438 // %12:_(s12) = G_MERGE_VALUES %10, %11 1439 // 1440 // Padding with undef if necessary: 1441 // 1442 // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6 1443 // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0 1444 // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1 1445 // %7:_(s2) = G_IMPLICIT_DEF 1446 // %8:_(s6) = G_MERGE_VALUES %3, %4, %5 1447 // %9:_(s6) = G_MERGE_VALUES %6, %7, %7 1448 // %10:_(s12) = G_MERGE_VALUES %8, %9 1449 1450 const int GCD = greatestCommonDivisor(SrcSize, WideSize); 1451 LLT GCDTy = LLT::scalar(GCD); 1452 1453 SmallVector<Register, 8> Parts; 1454 SmallVector<Register, 8> NewMergeRegs; 1455 SmallVector<Register, 8> Unmerges; 1456 LLT WideDstTy = LLT::scalar(NumMerge * WideSize); 1457 1458 // Decompose the original operands if they don't evenly divide. 1459 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) { 1460 Register SrcReg = MI.getOperand(I).getReg(); 1461 if (GCD == SrcSize) { 1462 Unmerges.push_back(SrcReg); 1463 } else { 1464 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 1465 for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J) 1466 Unmerges.push_back(Unmerge.getReg(J)); 1467 } 1468 } 1469 1470 // Pad with undef to the next size that is a multiple of the requested size. 1471 if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) { 1472 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 1473 for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I) 1474 Unmerges.push_back(UndefReg); 1475 } 1476 1477 const int PartsPerGCD = WideSize / GCD; 1478 1479 // Build merges of each piece. 1480 ArrayRef<Register> Slicer(Unmerges); 1481 for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) { 1482 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD)); 1483 NewMergeRegs.push_back(Merge.getReg(0)); 1484 } 1485 1486 // A truncate may be necessary if the requested type doesn't evenly divide the 1487 // original result type. 1488 if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) { 1489 MIRBuilder.buildMerge(DstReg, NewMergeRegs); 1490 } else { 1491 auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs); 1492 MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0)); 1493 } 1494 1495 MI.eraseFromParent(); 1496 return Legalized; 1497 } 1498 1499 Register LegalizerHelper::widenWithUnmerge(LLT WideTy, Register OrigReg) { 1500 Register WideReg = MRI.createGenericVirtualRegister(WideTy); 1501 LLT OrigTy = MRI.getType(OrigReg); 1502 LLT LCMTy = getLCMType(WideTy, OrigTy); 1503 1504 const int NumMergeParts = LCMTy.getSizeInBits() / WideTy.getSizeInBits(); 1505 const int NumUnmergeParts = LCMTy.getSizeInBits() / OrigTy.getSizeInBits(); 1506 1507 Register UnmergeSrc = WideReg; 1508 1509 // Create a merge to the LCM type, padding with undef 1510 // %0:_(<3 x s32>) = G_FOO => <4 x s32> 1511 // => 1512 // %1:_(<4 x s32>) = G_FOO 1513 // %2:_(<4 x s32>) = G_IMPLICIT_DEF 1514 // %3:_(<12 x s32>) = G_CONCAT_VECTORS %1, %2, %2 1515 // %0:_(<3 x s32>), %4:_, %5:_, %6:_ = G_UNMERGE_VALUES %3 1516 if (NumMergeParts > 1) { 1517 Register Undef = MIRBuilder.buildUndef(WideTy).getReg(0); 1518 SmallVector<Register, 8> MergeParts(NumMergeParts, Undef); 1519 MergeParts[0] = WideReg; 1520 UnmergeSrc = MIRBuilder.buildMerge(LCMTy, MergeParts).getReg(0); 1521 } 1522 1523 // Unmerge to the original register and pad with dead defs. 1524 SmallVector<Register, 8> UnmergeResults(NumUnmergeParts); 1525 UnmergeResults[0] = OrigReg; 1526 for (int I = 1; I != NumUnmergeParts; ++I) 1527 UnmergeResults[I] = MRI.createGenericVirtualRegister(OrigTy); 1528 1529 MIRBuilder.buildUnmerge(UnmergeResults, UnmergeSrc); 1530 return WideReg; 1531 } 1532 1533 LegalizerHelper::LegalizeResult 1534 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, 1535 LLT WideTy) { 1536 if (TypeIdx != 0) 1537 return UnableToLegalize; 1538 1539 int NumDst = MI.getNumOperands() - 1; 1540 Register SrcReg = MI.getOperand(NumDst).getReg(); 1541 LLT SrcTy = MRI.getType(SrcReg); 1542 if (SrcTy.isVector()) 1543 return UnableToLegalize; 1544 1545 Register Dst0Reg = MI.getOperand(0).getReg(); 1546 LLT DstTy = MRI.getType(Dst0Reg); 1547 if (!DstTy.isScalar()) 1548 return UnableToLegalize; 1549 1550 if (WideTy.getSizeInBits() >= SrcTy.getSizeInBits()) { 1551 if (SrcTy.isPointer()) { 1552 const DataLayout &DL = MIRBuilder.getDataLayout(); 1553 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) { 1554 LLVM_DEBUG( 1555 dbgs() << "Not casting non-integral address space integer\n"); 1556 return UnableToLegalize; 1557 } 1558 1559 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 1560 SrcReg = MIRBuilder.buildPtrToInt(SrcTy, SrcReg).getReg(0); 1561 } 1562 1563 // Widen SrcTy to WideTy. This does not affect the result, but since the 1564 // user requested this size, it is probably better handled than SrcTy and 1565 // should reduce the total number of legalization artifacts 1566 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1567 SrcTy = WideTy; 1568 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); 1569 } 1570 1571 // Theres no unmerge type to target. Directly extract the bits from the 1572 // source type 1573 unsigned DstSize = DstTy.getSizeInBits(); 1574 1575 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 1576 for (int I = 1; I != NumDst; ++I) { 1577 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I); 1578 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); 1579 MIRBuilder.buildTrunc(MI.getOperand(I), Shr); 1580 } 1581 1582 MI.eraseFromParent(); 1583 return Legalized; 1584 } 1585 1586 // Extend the source to a wider type. 1587 LLT LCMTy = getLCMType(SrcTy, WideTy); 1588 1589 Register WideSrc = SrcReg; 1590 if (LCMTy.getSizeInBits() != SrcTy.getSizeInBits()) { 1591 // TODO: If this is an integral address space, cast to integer and anyext. 1592 if (SrcTy.isPointer()) { 1593 LLVM_DEBUG(dbgs() << "Widening pointer source types not implemented\n"); 1594 return UnableToLegalize; 1595 } 1596 1597 WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0); 1598 } 1599 1600 auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc); 1601 1602 // Create a sequence of unmerges and merges to the original results. Since we 1603 // may have widened the source, we will need to pad the results with dead defs 1604 // to cover the source register. 1605 // e.g. widen s48 to s64: 1606 // %1:_(s48), %2:_(s48) = G_UNMERGE_VALUES %0:_(s96) 1607 // 1608 // => 1609 // %4:_(s192) = G_ANYEXT %0:_(s96) 1610 // %5:_(s64), %6, %7 = G_UNMERGE_VALUES %4 ; Requested unmerge 1611 // ; unpack to GCD type, with extra dead defs 1612 // %8:_(s16), %9, %10, %11 = G_UNMERGE_VALUES %5:_(s64) 1613 // %12:_(s16), %13, dead %14, dead %15 = G_UNMERGE_VALUES %6:_(s64) 1614 // dead %16:_(s16), dead %17, dead %18, dead %18 = G_UNMERGE_VALUES %7:_(s64) 1615 // %1:_(s48) = G_MERGE_VALUES %8:_(s16), %9, %10 ; Remerge to destination 1616 // %2:_(s48) = G_MERGE_VALUES %11:_(s16), %12, %13 ; Remerge to destination 1617 const LLT GCDTy = getGCDType(WideTy, DstTy); 1618 const int NumUnmerge = Unmerge->getNumOperands() - 1; 1619 const int PartsPerRemerge = DstTy.getSizeInBits() / GCDTy.getSizeInBits(); 1620 1621 // Directly unmerge to the destination without going through a GCD type 1622 // if possible 1623 if (PartsPerRemerge == 1) { 1624 const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits(); 1625 1626 for (int I = 0; I != NumUnmerge; ++I) { 1627 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 1628 1629 for (int J = 0; J != PartsPerUnmerge; ++J) { 1630 int Idx = I * PartsPerUnmerge + J; 1631 if (Idx < NumDst) 1632 MIB.addDef(MI.getOperand(Idx).getReg()); 1633 else { 1634 // Create dead def for excess components. 1635 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 1636 } 1637 } 1638 1639 MIB.addUse(Unmerge.getReg(I)); 1640 } 1641 } else { 1642 SmallVector<Register, 16> Parts; 1643 for (int J = 0; J != NumUnmerge; ++J) 1644 extractGCDType(Parts, GCDTy, Unmerge.getReg(J)); 1645 1646 SmallVector<Register, 8> RemergeParts; 1647 for (int I = 0; I != NumDst; ++I) { 1648 for (int J = 0; J < PartsPerRemerge; ++J) { 1649 const int Idx = I * PartsPerRemerge + J; 1650 RemergeParts.emplace_back(Parts[Idx]); 1651 } 1652 1653 MIRBuilder.buildMerge(MI.getOperand(I).getReg(), RemergeParts); 1654 RemergeParts.clear(); 1655 } 1656 } 1657 1658 MI.eraseFromParent(); 1659 return Legalized; 1660 } 1661 1662 LegalizerHelper::LegalizeResult 1663 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, 1664 LLT WideTy) { 1665 Register DstReg = MI.getOperand(0).getReg(); 1666 Register SrcReg = MI.getOperand(1).getReg(); 1667 LLT SrcTy = MRI.getType(SrcReg); 1668 1669 LLT DstTy = MRI.getType(DstReg); 1670 unsigned Offset = MI.getOperand(2).getImm(); 1671 1672 if (TypeIdx == 0) { 1673 if (SrcTy.isVector() || DstTy.isVector()) 1674 return UnableToLegalize; 1675 1676 SrcOp Src(SrcReg); 1677 if (SrcTy.isPointer()) { 1678 // Extracts from pointers can be handled only if they are really just 1679 // simple integers. 1680 const DataLayout &DL = MIRBuilder.getDataLayout(); 1681 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) 1682 return UnableToLegalize; 1683 1684 LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits()); 1685 Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src); 1686 SrcTy = SrcAsIntTy; 1687 } 1688 1689 if (DstTy.isPointer()) 1690 return UnableToLegalize; 1691 1692 if (Offset == 0) { 1693 // Avoid a shift in the degenerate case. 1694 MIRBuilder.buildTrunc(DstReg, 1695 MIRBuilder.buildAnyExtOrTrunc(WideTy, Src)); 1696 MI.eraseFromParent(); 1697 return Legalized; 1698 } 1699 1700 // Do a shift in the source type. 1701 LLT ShiftTy = SrcTy; 1702 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1703 Src = MIRBuilder.buildAnyExt(WideTy, Src); 1704 ShiftTy = WideTy; 1705 } 1706 1707 auto LShr = MIRBuilder.buildLShr( 1708 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); 1709 MIRBuilder.buildTrunc(DstReg, LShr); 1710 MI.eraseFromParent(); 1711 return Legalized; 1712 } 1713 1714 if (SrcTy.isScalar()) { 1715 Observer.changingInstr(MI); 1716 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1717 Observer.changedInstr(MI); 1718 return Legalized; 1719 } 1720 1721 if (!SrcTy.isVector()) 1722 return UnableToLegalize; 1723 1724 if (DstTy != SrcTy.getElementType()) 1725 return UnableToLegalize; 1726 1727 if (Offset % SrcTy.getScalarSizeInBits() != 0) 1728 return UnableToLegalize; 1729 1730 Observer.changingInstr(MI); 1731 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1732 1733 MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) * 1734 Offset); 1735 widenScalarDst(MI, WideTy.getScalarType(), 0); 1736 Observer.changedInstr(MI); 1737 return Legalized; 1738 } 1739 1740 LegalizerHelper::LegalizeResult 1741 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, 1742 LLT WideTy) { 1743 if (TypeIdx != 0 || WideTy.isVector()) 1744 return UnableToLegalize; 1745 Observer.changingInstr(MI); 1746 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1747 widenScalarDst(MI, WideTy); 1748 Observer.changedInstr(MI); 1749 return Legalized; 1750 } 1751 1752 LegalizerHelper::LegalizeResult 1753 LegalizerHelper::widenScalarAddSubOverflow(MachineInstr &MI, unsigned TypeIdx, 1754 LLT WideTy) { 1755 if (TypeIdx == 1) 1756 return UnableToLegalize; // TODO 1757 1758 unsigned Opcode; 1759 unsigned ExtOpcode; 1760 Optional<Register> CarryIn = None; 1761 switch (MI.getOpcode()) { 1762 default: 1763 llvm_unreachable("Unexpected opcode!"); 1764 case TargetOpcode::G_SADDO: 1765 Opcode = TargetOpcode::G_ADD; 1766 ExtOpcode = TargetOpcode::G_SEXT; 1767 break; 1768 case TargetOpcode::G_SSUBO: 1769 Opcode = TargetOpcode::G_SUB; 1770 ExtOpcode = TargetOpcode::G_SEXT; 1771 break; 1772 case TargetOpcode::G_UADDO: 1773 Opcode = TargetOpcode::G_ADD; 1774 ExtOpcode = TargetOpcode::G_ZEXT; 1775 break; 1776 case TargetOpcode::G_USUBO: 1777 Opcode = TargetOpcode::G_SUB; 1778 ExtOpcode = TargetOpcode::G_ZEXT; 1779 break; 1780 case TargetOpcode::G_SADDE: 1781 Opcode = TargetOpcode::G_UADDE; 1782 ExtOpcode = TargetOpcode::G_SEXT; 1783 CarryIn = MI.getOperand(4).getReg(); 1784 break; 1785 case TargetOpcode::G_SSUBE: 1786 Opcode = TargetOpcode::G_USUBE; 1787 ExtOpcode = TargetOpcode::G_SEXT; 1788 CarryIn = MI.getOperand(4).getReg(); 1789 break; 1790 case TargetOpcode::G_UADDE: 1791 Opcode = TargetOpcode::G_UADDE; 1792 ExtOpcode = TargetOpcode::G_ZEXT; 1793 CarryIn = MI.getOperand(4).getReg(); 1794 break; 1795 case TargetOpcode::G_USUBE: 1796 Opcode = TargetOpcode::G_USUBE; 1797 ExtOpcode = TargetOpcode::G_ZEXT; 1798 CarryIn = MI.getOperand(4).getReg(); 1799 break; 1800 } 1801 1802 auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)}); 1803 auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)}); 1804 // Do the arithmetic in the larger type. 1805 Register NewOp; 1806 if (CarryIn) { 1807 LLT CarryOutTy = MRI.getType(MI.getOperand(1).getReg()); 1808 NewOp = MIRBuilder 1809 .buildInstr(Opcode, {WideTy, CarryOutTy}, 1810 {LHSExt, RHSExt, *CarryIn}) 1811 .getReg(0); 1812 } else { 1813 NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt}).getReg(0); 1814 } 1815 LLT OrigTy = MRI.getType(MI.getOperand(0).getReg()); 1816 auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp); 1817 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); 1818 // There is no overflow if the ExtOp is the same as NewOp. 1819 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); 1820 // Now trunc the NewOp to the original result. 1821 MIRBuilder.buildTrunc(MI.getOperand(0), NewOp); 1822 MI.eraseFromParent(); 1823 return Legalized; 1824 } 1825 1826 LegalizerHelper::LegalizeResult 1827 LegalizerHelper::widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx, 1828 LLT WideTy) { 1829 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SADDSAT || 1830 MI.getOpcode() == TargetOpcode::G_SSUBSAT || 1831 MI.getOpcode() == TargetOpcode::G_SSHLSAT; 1832 bool IsShift = MI.getOpcode() == TargetOpcode::G_SSHLSAT || 1833 MI.getOpcode() == TargetOpcode::G_USHLSAT; 1834 // We can convert this to: 1835 // 1. Any extend iN to iM 1836 // 2. SHL by M-N 1837 // 3. [US][ADD|SUB|SHL]SAT 1838 // 4. L/ASHR by M-N 1839 // 1840 // It may be more efficient to lower this to a min and a max operation in 1841 // the higher precision arithmetic if the promoted operation isn't legal, 1842 // but this decision is up to the target's lowering request. 1843 Register DstReg = MI.getOperand(0).getReg(); 1844 1845 unsigned NewBits = WideTy.getScalarSizeInBits(); 1846 unsigned SHLAmount = NewBits - MRI.getType(DstReg).getScalarSizeInBits(); 1847 1848 // Shifts must zero-extend the RHS to preserve the unsigned quantity, and 1849 // must not left shift the RHS to preserve the shift amount. 1850 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1)); 1851 auto RHS = IsShift ? MIRBuilder.buildZExt(WideTy, MI.getOperand(2)) 1852 : MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2)); 1853 auto ShiftK = MIRBuilder.buildConstant(WideTy, SHLAmount); 1854 auto ShiftL = MIRBuilder.buildShl(WideTy, LHS, ShiftK); 1855 auto ShiftR = IsShift ? RHS : MIRBuilder.buildShl(WideTy, RHS, ShiftK); 1856 1857 auto WideInst = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, 1858 {ShiftL, ShiftR}, MI.getFlags()); 1859 1860 // Use a shift that will preserve the number of sign bits when the trunc is 1861 // folded away. 1862 auto Result = IsSigned ? MIRBuilder.buildAShr(WideTy, WideInst, ShiftK) 1863 : MIRBuilder.buildLShr(WideTy, WideInst, ShiftK); 1864 1865 MIRBuilder.buildTrunc(DstReg, Result); 1866 MI.eraseFromParent(); 1867 return Legalized; 1868 } 1869 1870 LegalizerHelper::LegalizeResult 1871 LegalizerHelper::widenScalarMulo(MachineInstr &MI, unsigned TypeIdx, 1872 LLT WideTy) { 1873 if (TypeIdx == 1) 1874 return UnableToLegalize; 1875 1876 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULO; 1877 Register Result = MI.getOperand(0).getReg(); 1878 Register OriginalOverflow = MI.getOperand(1).getReg(); 1879 Register LHS = MI.getOperand(2).getReg(); 1880 Register RHS = MI.getOperand(3).getReg(); 1881 LLT SrcTy = MRI.getType(LHS); 1882 LLT OverflowTy = MRI.getType(OriginalOverflow); 1883 unsigned SrcBitWidth = SrcTy.getScalarSizeInBits(); 1884 1885 // To determine if the result overflowed in the larger type, we extend the 1886 // input to the larger type, do the multiply (checking if it overflows), 1887 // then also check the high bits of the result to see if overflow happened 1888 // there. 1889 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 1890 auto LeftOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {LHS}); 1891 auto RightOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {RHS}); 1892 1893 auto Mulo = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy, OverflowTy}, 1894 {LeftOperand, RightOperand}); 1895 auto Mul = Mulo->getOperand(0); 1896 MIRBuilder.buildTrunc(Result, Mul); 1897 1898 MachineInstrBuilder ExtResult; 1899 // Overflow occurred if it occurred in the larger type, or if the high part 1900 // of the result does not zero/sign-extend the low part. Check this second 1901 // possibility first. 1902 if (IsSigned) { 1903 // For signed, overflow occurred when the high part does not sign-extend 1904 // the low part. 1905 ExtResult = MIRBuilder.buildSExtInReg(WideTy, Mul, SrcBitWidth); 1906 } else { 1907 // Unsigned overflow occurred when the high part does not zero-extend the 1908 // low part. 1909 ExtResult = MIRBuilder.buildZExtInReg(WideTy, Mul, SrcBitWidth); 1910 } 1911 1912 // Multiplication cannot overflow if the WideTy is >= 2 * original width, 1913 // so we don't need to check the overflow result of larger type Mulo. 1914 if (WideTy.getScalarSizeInBits() < 2 * SrcBitWidth) { 1915 auto Overflow = 1916 MIRBuilder.buildICmp(CmpInst::ICMP_NE, OverflowTy, Mul, ExtResult); 1917 // Finally check if the multiplication in the larger type itself overflowed. 1918 MIRBuilder.buildOr(OriginalOverflow, Mulo->getOperand(1), Overflow); 1919 } else { 1920 MIRBuilder.buildICmp(CmpInst::ICMP_NE, OriginalOverflow, Mul, ExtResult); 1921 } 1922 MI.eraseFromParent(); 1923 return Legalized; 1924 } 1925 1926 LegalizerHelper::LegalizeResult 1927 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { 1928 switch (MI.getOpcode()) { 1929 default: 1930 return UnableToLegalize; 1931 case TargetOpcode::G_EXTRACT: 1932 return widenScalarExtract(MI, TypeIdx, WideTy); 1933 case TargetOpcode::G_INSERT: 1934 return widenScalarInsert(MI, TypeIdx, WideTy); 1935 case TargetOpcode::G_MERGE_VALUES: 1936 return widenScalarMergeValues(MI, TypeIdx, WideTy); 1937 case TargetOpcode::G_UNMERGE_VALUES: 1938 return widenScalarUnmergeValues(MI, TypeIdx, WideTy); 1939 case TargetOpcode::G_SADDO: 1940 case TargetOpcode::G_SSUBO: 1941 case TargetOpcode::G_UADDO: 1942 case TargetOpcode::G_USUBO: 1943 case TargetOpcode::G_SADDE: 1944 case TargetOpcode::G_SSUBE: 1945 case TargetOpcode::G_UADDE: 1946 case TargetOpcode::G_USUBE: 1947 return widenScalarAddSubOverflow(MI, TypeIdx, WideTy); 1948 case TargetOpcode::G_UMULO: 1949 case TargetOpcode::G_SMULO: 1950 return widenScalarMulo(MI, TypeIdx, WideTy); 1951 case TargetOpcode::G_SADDSAT: 1952 case TargetOpcode::G_SSUBSAT: 1953 case TargetOpcode::G_SSHLSAT: 1954 case TargetOpcode::G_UADDSAT: 1955 case TargetOpcode::G_USUBSAT: 1956 case TargetOpcode::G_USHLSAT: 1957 return widenScalarAddSubShlSat(MI, TypeIdx, WideTy); 1958 case TargetOpcode::G_CTTZ: 1959 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 1960 case TargetOpcode::G_CTLZ: 1961 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 1962 case TargetOpcode::G_CTPOP: { 1963 if (TypeIdx == 0) { 1964 Observer.changingInstr(MI); 1965 widenScalarDst(MI, WideTy, 0); 1966 Observer.changedInstr(MI); 1967 return Legalized; 1968 } 1969 1970 Register SrcReg = MI.getOperand(1).getReg(); 1971 1972 // First ZEXT the input. 1973 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg); 1974 LLT CurTy = MRI.getType(SrcReg); 1975 if (MI.getOpcode() == TargetOpcode::G_CTTZ) { 1976 // The count is the same in the larger type except if the original 1977 // value was zero. This can be handled by setting the bit just off 1978 // the top of the original type. 1979 auto TopBit = 1980 APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits()); 1981 MIBSrc = MIRBuilder.buildOr( 1982 WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit)); 1983 } 1984 1985 // Perform the operation at the larger size. 1986 auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc}); 1987 // This is already the correct result for CTPOP and CTTZs 1988 if (MI.getOpcode() == TargetOpcode::G_CTLZ || 1989 MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) { 1990 // The correct result is NewOp - (Difference in widety and current ty). 1991 unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits(); 1992 MIBNewOp = MIRBuilder.buildSub( 1993 WideTy, MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)); 1994 } 1995 1996 MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp); 1997 MI.eraseFromParent(); 1998 return Legalized; 1999 } 2000 case TargetOpcode::G_BSWAP: { 2001 Observer.changingInstr(MI); 2002 Register DstReg = MI.getOperand(0).getReg(); 2003 2004 Register ShrReg = MRI.createGenericVirtualRegister(WideTy); 2005 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 2006 Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy); 2007 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2008 2009 MI.getOperand(0).setReg(DstExt); 2010 2011 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 2012 2013 LLT Ty = MRI.getType(DstReg); 2014 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 2015 MIRBuilder.buildConstant(ShiftAmtReg, DiffBits); 2016 MIRBuilder.buildLShr(ShrReg, DstExt, ShiftAmtReg); 2017 2018 MIRBuilder.buildTrunc(DstReg, ShrReg); 2019 Observer.changedInstr(MI); 2020 return Legalized; 2021 } 2022 case TargetOpcode::G_BITREVERSE: { 2023 Observer.changingInstr(MI); 2024 2025 Register DstReg = MI.getOperand(0).getReg(); 2026 LLT Ty = MRI.getType(DstReg); 2027 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 2028 2029 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 2030 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2031 MI.getOperand(0).setReg(DstExt); 2032 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 2033 2034 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); 2035 auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt); 2036 MIRBuilder.buildTrunc(DstReg, Shift); 2037 Observer.changedInstr(MI); 2038 return Legalized; 2039 } 2040 case TargetOpcode::G_FREEZE: 2041 Observer.changingInstr(MI); 2042 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2043 widenScalarDst(MI, WideTy); 2044 Observer.changedInstr(MI); 2045 return Legalized; 2046 2047 case TargetOpcode::G_ABS: 2048 Observer.changingInstr(MI); 2049 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2050 widenScalarDst(MI, WideTy); 2051 Observer.changedInstr(MI); 2052 return Legalized; 2053 2054 case TargetOpcode::G_ADD: 2055 case TargetOpcode::G_AND: 2056 case TargetOpcode::G_MUL: 2057 case TargetOpcode::G_OR: 2058 case TargetOpcode::G_XOR: 2059 case TargetOpcode::G_SUB: 2060 // Perform operation at larger width (any extension is fines here, high bits 2061 // don't affect the result) and then truncate the result back to the 2062 // original type. 2063 Observer.changingInstr(MI); 2064 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2065 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2066 widenScalarDst(MI, WideTy); 2067 Observer.changedInstr(MI); 2068 return Legalized; 2069 2070 case TargetOpcode::G_SBFX: 2071 case TargetOpcode::G_UBFX: 2072 Observer.changingInstr(MI); 2073 2074 if (TypeIdx == 0) { 2075 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2076 widenScalarDst(MI, WideTy); 2077 } else { 2078 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2079 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ZEXT); 2080 } 2081 2082 Observer.changedInstr(MI); 2083 return Legalized; 2084 2085 case TargetOpcode::G_SHL: 2086 Observer.changingInstr(MI); 2087 2088 if (TypeIdx == 0) { 2089 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2090 widenScalarDst(MI, WideTy); 2091 } else { 2092 assert(TypeIdx == 1); 2093 // The "number of bits to shift" operand must preserve its value as an 2094 // unsigned integer: 2095 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2096 } 2097 2098 Observer.changedInstr(MI); 2099 return Legalized; 2100 2101 case TargetOpcode::G_SDIV: 2102 case TargetOpcode::G_SREM: 2103 case TargetOpcode::G_SMIN: 2104 case TargetOpcode::G_SMAX: 2105 Observer.changingInstr(MI); 2106 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2107 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2108 widenScalarDst(MI, WideTy); 2109 Observer.changedInstr(MI); 2110 return Legalized; 2111 2112 case TargetOpcode::G_SDIVREM: 2113 Observer.changingInstr(MI); 2114 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2115 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT); 2116 widenScalarDst(MI, WideTy); 2117 widenScalarDst(MI, WideTy, 1); 2118 Observer.changedInstr(MI); 2119 return Legalized; 2120 2121 case TargetOpcode::G_ASHR: 2122 case TargetOpcode::G_LSHR: 2123 Observer.changingInstr(MI); 2124 2125 if (TypeIdx == 0) { 2126 unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ? 2127 TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 2128 2129 widenScalarSrc(MI, WideTy, 1, CvtOp); 2130 widenScalarDst(MI, WideTy); 2131 } else { 2132 assert(TypeIdx == 1); 2133 // The "number of bits to shift" operand must preserve its value as an 2134 // unsigned integer: 2135 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2136 } 2137 2138 Observer.changedInstr(MI); 2139 return Legalized; 2140 case TargetOpcode::G_UDIV: 2141 case TargetOpcode::G_UREM: 2142 case TargetOpcode::G_UMIN: 2143 case TargetOpcode::G_UMAX: 2144 Observer.changingInstr(MI); 2145 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2146 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2147 widenScalarDst(MI, WideTy); 2148 Observer.changedInstr(MI); 2149 return Legalized; 2150 2151 case TargetOpcode::G_UDIVREM: 2152 Observer.changingInstr(MI); 2153 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2154 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ZEXT); 2155 widenScalarDst(MI, WideTy); 2156 widenScalarDst(MI, WideTy, 1); 2157 Observer.changedInstr(MI); 2158 return Legalized; 2159 2160 case TargetOpcode::G_SELECT: 2161 Observer.changingInstr(MI); 2162 if (TypeIdx == 0) { 2163 // Perform operation at larger width (any extension is fine here, high 2164 // bits don't affect the result) and then truncate the result back to the 2165 // original type. 2166 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2167 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT); 2168 widenScalarDst(MI, WideTy); 2169 } else { 2170 bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector(); 2171 // Explicit extension is required here since high bits affect the result. 2172 widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false)); 2173 } 2174 Observer.changedInstr(MI); 2175 return Legalized; 2176 2177 case TargetOpcode::G_FPTOSI: 2178 case TargetOpcode::G_FPTOUI: 2179 Observer.changingInstr(MI); 2180 2181 if (TypeIdx == 0) 2182 widenScalarDst(MI, WideTy); 2183 else 2184 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2185 2186 Observer.changedInstr(MI); 2187 return Legalized; 2188 case TargetOpcode::G_SITOFP: 2189 Observer.changingInstr(MI); 2190 2191 if (TypeIdx == 0) 2192 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2193 else 2194 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2195 2196 Observer.changedInstr(MI); 2197 return Legalized; 2198 case TargetOpcode::G_UITOFP: 2199 Observer.changingInstr(MI); 2200 2201 if (TypeIdx == 0) 2202 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2203 else 2204 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2205 2206 Observer.changedInstr(MI); 2207 return Legalized; 2208 case TargetOpcode::G_LOAD: 2209 case TargetOpcode::G_SEXTLOAD: 2210 case TargetOpcode::G_ZEXTLOAD: 2211 Observer.changingInstr(MI); 2212 widenScalarDst(MI, WideTy); 2213 Observer.changedInstr(MI); 2214 return Legalized; 2215 2216 case TargetOpcode::G_STORE: { 2217 if (TypeIdx != 0) 2218 return UnableToLegalize; 2219 2220 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 2221 if (!Ty.isScalar()) 2222 return UnableToLegalize; 2223 2224 Observer.changingInstr(MI); 2225 2226 unsigned ExtType = Ty.getScalarSizeInBits() == 1 ? 2227 TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT; 2228 widenScalarSrc(MI, WideTy, 0, ExtType); 2229 2230 Observer.changedInstr(MI); 2231 return Legalized; 2232 } 2233 case TargetOpcode::G_CONSTANT: { 2234 MachineOperand &SrcMO = MI.getOperand(1); 2235 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2236 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( 2237 MRI.getType(MI.getOperand(0).getReg())); 2238 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || 2239 ExtOpc == TargetOpcode::G_ANYEXT) && 2240 "Illegal Extend"); 2241 const APInt &SrcVal = SrcMO.getCImm()->getValue(); 2242 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) 2243 ? SrcVal.sext(WideTy.getSizeInBits()) 2244 : SrcVal.zext(WideTy.getSizeInBits()); 2245 Observer.changingInstr(MI); 2246 SrcMO.setCImm(ConstantInt::get(Ctx, Val)); 2247 2248 widenScalarDst(MI, WideTy); 2249 Observer.changedInstr(MI); 2250 return Legalized; 2251 } 2252 case TargetOpcode::G_FCONSTANT: { 2253 MachineOperand &SrcMO = MI.getOperand(1); 2254 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2255 APFloat Val = SrcMO.getFPImm()->getValueAPF(); 2256 bool LosesInfo; 2257 switch (WideTy.getSizeInBits()) { 2258 case 32: 2259 Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, 2260 &LosesInfo); 2261 break; 2262 case 64: 2263 Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 2264 &LosesInfo); 2265 break; 2266 default: 2267 return UnableToLegalize; 2268 } 2269 2270 assert(!LosesInfo && "extend should always be lossless"); 2271 2272 Observer.changingInstr(MI); 2273 SrcMO.setFPImm(ConstantFP::get(Ctx, Val)); 2274 2275 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2276 Observer.changedInstr(MI); 2277 return Legalized; 2278 } 2279 case TargetOpcode::G_IMPLICIT_DEF: { 2280 Observer.changingInstr(MI); 2281 widenScalarDst(MI, WideTy); 2282 Observer.changedInstr(MI); 2283 return Legalized; 2284 } 2285 case TargetOpcode::G_BRCOND: 2286 Observer.changingInstr(MI); 2287 widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false)); 2288 Observer.changedInstr(MI); 2289 return Legalized; 2290 2291 case TargetOpcode::G_FCMP: 2292 Observer.changingInstr(MI); 2293 if (TypeIdx == 0) 2294 widenScalarDst(MI, WideTy); 2295 else { 2296 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT); 2297 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT); 2298 } 2299 Observer.changedInstr(MI); 2300 return Legalized; 2301 2302 case TargetOpcode::G_ICMP: 2303 Observer.changingInstr(MI); 2304 if (TypeIdx == 0) 2305 widenScalarDst(MI, WideTy); 2306 else { 2307 unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>( 2308 MI.getOperand(1).getPredicate())) 2309 ? TargetOpcode::G_SEXT 2310 : TargetOpcode::G_ZEXT; 2311 widenScalarSrc(MI, WideTy, 2, ExtOpcode); 2312 widenScalarSrc(MI, WideTy, 3, ExtOpcode); 2313 } 2314 Observer.changedInstr(MI); 2315 return Legalized; 2316 2317 case TargetOpcode::G_PTR_ADD: 2318 assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD"); 2319 Observer.changingInstr(MI); 2320 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2321 Observer.changedInstr(MI); 2322 return Legalized; 2323 2324 case TargetOpcode::G_PHI: { 2325 assert(TypeIdx == 0 && "Expecting only Idx 0"); 2326 2327 Observer.changingInstr(MI); 2328 for (unsigned I = 1; I < MI.getNumOperands(); I += 2) { 2329 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 2330 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 2331 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT); 2332 } 2333 2334 MachineBasicBlock &MBB = *MI.getParent(); 2335 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 2336 widenScalarDst(MI, WideTy); 2337 Observer.changedInstr(MI); 2338 return Legalized; 2339 } 2340 case TargetOpcode::G_EXTRACT_VECTOR_ELT: { 2341 if (TypeIdx == 0) { 2342 Register VecReg = MI.getOperand(1).getReg(); 2343 LLT VecTy = MRI.getType(VecReg); 2344 Observer.changingInstr(MI); 2345 2346 widenScalarSrc( 2347 MI, LLT::vector(VecTy.getElementCount(), WideTy.getSizeInBits()), 1, 2348 TargetOpcode::G_SEXT); 2349 2350 widenScalarDst(MI, WideTy, 0); 2351 Observer.changedInstr(MI); 2352 return Legalized; 2353 } 2354 2355 if (TypeIdx != 2) 2356 return UnableToLegalize; 2357 Observer.changingInstr(MI); 2358 // TODO: Probably should be zext 2359 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2360 Observer.changedInstr(MI); 2361 return Legalized; 2362 } 2363 case TargetOpcode::G_INSERT_VECTOR_ELT: { 2364 if (TypeIdx == 1) { 2365 Observer.changingInstr(MI); 2366 2367 Register VecReg = MI.getOperand(1).getReg(); 2368 LLT VecTy = MRI.getType(VecReg); 2369 LLT WideVecTy = LLT::vector(VecTy.getElementCount(), WideTy); 2370 2371 widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT); 2372 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2373 widenScalarDst(MI, WideVecTy, 0); 2374 Observer.changedInstr(MI); 2375 return Legalized; 2376 } 2377 2378 if (TypeIdx == 2) { 2379 Observer.changingInstr(MI); 2380 // TODO: Probably should be zext 2381 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT); 2382 Observer.changedInstr(MI); 2383 return Legalized; 2384 } 2385 2386 return UnableToLegalize; 2387 } 2388 case TargetOpcode::G_FADD: 2389 case TargetOpcode::G_FMUL: 2390 case TargetOpcode::G_FSUB: 2391 case TargetOpcode::G_FMA: 2392 case TargetOpcode::G_FMAD: 2393 case TargetOpcode::G_FNEG: 2394 case TargetOpcode::G_FABS: 2395 case TargetOpcode::G_FCANONICALIZE: 2396 case TargetOpcode::G_FMINNUM: 2397 case TargetOpcode::G_FMAXNUM: 2398 case TargetOpcode::G_FMINNUM_IEEE: 2399 case TargetOpcode::G_FMAXNUM_IEEE: 2400 case TargetOpcode::G_FMINIMUM: 2401 case TargetOpcode::G_FMAXIMUM: 2402 case TargetOpcode::G_FDIV: 2403 case TargetOpcode::G_FREM: 2404 case TargetOpcode::G_FCEIL: 2405 case TargetOpcode::G_FFLOOR: 2406 case TargetOpcode::G_FCOS: 2407 case TargetOpcode::G_FSIN: 2408 case TargetOpcode::G_FLOG10: 2409 case TargetOpcode::G_FLOG: 2410 case TargetOpcode::G_FLOG2: 2411 case TargetOpcode::G_FRINT: 2412 case TargetOpcode::G_FNEARBYINT: 2413 case TargetOpcode::G_FSQRT: 2414 case TargetOpcode::G_FEXP: 2415 case TargetOpcode::G_FEXP2: 2416 case TargetOpcode::G_FPOW: 2417 case TargetOpcode::G_INTRINSIC_TRUNC: 2418 case TargetOpcode::G_INTRINSIC_ROUND: 2419 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 2420 assert(TypeIdx == 0); 2421 Observer.changingInstr(MI); 2422 2423 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 2424 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT); 2425 2426 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2427 Observer.changedInstr(MI); 2428 return Legalized; 2429 case TargetOpcode::G_FPOWI: { 2430 if (TypeIdx != 0) 2431 return UnableToLegalize; 2432 Observer.changingInstr(MI); 2433 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2434 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2435 Observer.changedInstr(MI); 2436 return Legalized; 2437 } 2438 case TargetOpcode::G_INTTOPTR: 2439 if (TypeIdx != 1) 2440 return UnableToLegalize; 2441 2442 Observer.changingInstr(MI); 2443 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2444 Observer.changedInstr(MI); 2445 return Legalized; 2446 case TargetOpcode::G_PTRTOINT: 2447 if (TypeIdx != 0) 2448 return UnableToLegalize; 2449 2450 Observer.changingInstr(MI); 2451 widenScalarDst(MI, WideTy, 0); 2452 Observer.changedInstr(MI); 2453 return Legalized; 2454 case TargetOpcode::G_BUILD_VECTOR: { 2455 Observer.changingInstr(MI); 2456 2457 const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType(); 2458 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) 2459 widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT); 2460 2461 // Avoid changing the result vector type if the source element type was 2462 // requested. 2463 if (TypeIdx == 1) { 2464 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); 2465 } else { 2466 widenScalarDst(MI, WideTy, 0); 2467 } 2468 2469 Observer.changedInstr(MI); 2470 return Legalized; 2471 } 2472 case TargetOpcode::G_SEXT_INREG: 2473 if (TypeIdx != 0) 2474 return UnableToLegalize; 2475 2476 Observer.changingInstr(MI); 2477 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2478 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC); 2479 Observer.changedInstr(MI); 2480 return Legalized; 2481 case TargetOpcode::G_PTRMASK: { 2482 if (TypeIdx != 1) 2483 return UnableToLegalize; 2484 Observer.changingInstr(MI); 2485 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2486 Observer.changedInstr(MI); 2487 return Legalized; 2488 } 2489 } 2490 } 2491 2492 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces, 2493 MachineIRBuilder &B, Register Src, LLT Ty) { 2494 auto Unmerge = B.buildUnmerge(Ty, Src); 2495 for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I) 2496 Pieces.push_back(Unmerge.getReg(I)); 2497 } 2498 2499 LegalizerHelper::LegalizeResult 2500 LegalizerHelper::lowerBitcast(MachineInstr &MI) { 2501 Register Dst = MI.getOperand(0).getReg(); 2502 Register Src = MI.getOperand(1).getReg(); 2503 LLT DstTy = MRI.getType(Dst); 2504 LLT SrcTy = MRI.getType(Src); 2505 2506 if (SrcTy.isVector()) { 2507 LLT SrcEltTy = SrcTy.getElementType(); 2508 SmallVector<Register, 8> SrcRegs; 2509 2510 if (DstTy.isVector()) { 2511 int NumDstElt = DstTy.getNumElements(); 2512 int NumSrcElt = SrcTy.getNumElements(); 2513 2514 LLT DstEltTy = DstTy.getElementType(); 2515 LLT DstCastTy = DstEltTy; // Intermediate bitcast result type 2516 LLT SrcPartTy = SrcEltTy; // Original unmerge result type. 2517 2518 // If there's an element size mismatch, insert intermediate casts to match 2519 // the result element type. 2520 if (NumSrcElt < NumDstElt) { // Source element type is larger. 2521 // %1:_(<4 x s8>) = G_BITCAST %0:_(<2 x s16>) 2522 // 2523 // => 2524 // 2525 // %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0 2526 // %3:_(<2 x s8>) = G_BITCAST %2 2527 // %4:_(<2 x s8>) = G_BITCAST %3 2528 // %1:_(<4 x s16>) = G_CONCAT_VECTORS %3, %4 2529 DstCastTy = LLT::fixed_vector(NumDstElt / NumSrcElt, DstEltTy); 2530 SrcPartTy = SrcEltTy; 2531 } else if (NumSrcElt > NumDstElt) { // Source element type is smaller. 2532 // 2533 // %1:_(<2 x s16>) = G_BITCAST %0:_(<4 x s8>) 2534 // 2535 // => 2536 // 2537 // %2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %0 2538 // %3:_(s16) = G_BITCAST %2 2539 // %4:_(s16) = G_BITCAST %3 2540 // %1:_(<2 x s16>) = G_BUILD_VECTOR %3, %4 2541 SrcPartTy = LLT::fixed_vector(NumSrcElt / NumDstElt, SrcEltTy); 2542 DstCastTy = DstEltTy; 2543 } 2544 2545 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcPartTy); 2546 for (Register &SrcReg : SrcRegs) 2547 SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); 2548 } else 2549 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcEltTy); 2550 2551 MIRBuilder.buildMerge(Dst, SrcRegs); 2552 MI.eraseFromParent(); 2553 return Legalized; 2554 } 2555 2556 if (DstTy.isVector()) { 2557 SmallVector<Register, 8> SrcRegs; 2558 getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType()); 2559 MIRBuilder.buildMerge(Dst, SrcRegs); 2560 MI.eraseFromParent(); 2561 return Legalized; 2562 } 2563 2564 return UnableToLegalize; 2565 } 2566 2567 /// Figure out the bit offset into a register when coercing a vector index for 2568 /// the wide element type. This is only for the case when promoting vector to 2569 /// one with larger elements. 2570 // 2571 /// 2572 /// %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2573 /// %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2574 static Register getBitcastWiderVectorElementOffset(MachineIRBuilder &B, 2575 Register Idx, 2576 unsigned NewEltSize, 2577 unsigned OldEltSize) { 2578 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2579 LLT IdxTy = B.getMRI()->getType(Idx); 2580 2581 // Now figure out the amount we need to shift to get the target bits. 2582 auto OffsetMask = B.buildConstant( 2583 IdxTy, ~(APInt::getAllOnesValue(IdxTy.getSizeInBits()) << Log2EltRatio)); 2584 auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask); 2585 return B.buildShl(IdxTy, OffsetIdx, 2586 B.buildConstant(IdxTy, Log2_32(OldEltSize))).getReg(0); 2587 } 2588 2589 /// Perform a G_EXTRACT_VECTOR_ELT in a different sized vector element. If this 2590 /// is casting to a vector with a smaller element size, perform multiple element 2591 /// extracts and merge the results. If this is coercing to a vector with larger 2592 /// elements, index the bitcasted vector and extract the target element with bit 2593 /// operations. This is intended to force the indexing in the native register 2594 /// size for architectures that can dynamically index the register file. 2595 LegalizerHelper::LegalizeResult 2596 LegalizerHelper::bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx, 2597 LLT CastTy) { 2598 if (TypeIdx != 1) 2599 return UnableToLegalize; 2600 2601 Register Dst = MI.getOperand(0).getReg(); 2602 Register SrcVec = MI.getOperand(1).getReg(); 2603 Register Idx = MI.getOperand(2).getReg(); 2604 LLT SrcVecTy = MRI.getType(SrcVec); 2605 LLT IdxTy = MRI.getType(Idx); 2606 2607 LLT SrcEltTy = SrcVecTy.getElementType(); 2608 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2609 unsigned OldNumElts = SrcVecTy.getNumElements(); 2610 2611 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2612 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2613 2614 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2615 const unsigned OldEltSize = SrcEltTy.getSizeInBits(); 2616 if (NewNumElts > OldNumElts) { 2617 // Decreasing the vector element size 2618 // 2619 // e.g. i64 = extract_vector_elt x:v2i64, y:i32 2620 // => 2621 // v4i32:castx = bitcast x:v2i64 2622 // 2623 // i64 = bitcast 2624 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))), 2625 // (i32 (extract_vector_elt castx, (2 * y + 1))) 2626 // 2627 if (NewNumElts % OldNumElts != 0) 2628 return UnableToLegalize; 2629 2630 // Type of the intermediate result vector. 2631 const unsigned NewEltsPerOldElt = NewNumElts / OldNumElts; 2632 LLT MidTy = 2633 LLT::scalarOrVector(ElementCount::getFixed(NewEltsPerOldElt), NewEltTy); 2634 2635 auto NewEltsPerOldEltK = MIRBuilder.buildConstant(IdxTy, NewEltsPerOldElt); 2636 2637 SmallVector<Register, 8> NewOps(NewEltsPerOldElt); 2638 auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, Idx, NewEltsPerOldEltK); 2639 2640 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) { 2641 auto IdxOffset = MIRBuilder.buildConstant(IdxTy, I); 2642 auto TmpIdx = MIRBuilder.buildAdd(IdxTy, NewBaseIdx, IdxOffset); 2643 auto Elt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, TmpIdx); 2644 NewOps[I] = Elt.getReg(0); 2645 } 2646 2647 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); 2648 MIRBuilder.buildBitcast(Dst, NewVec); 2649 MI.eraseFromParent(); 2650 return Legalized; 2651 } 2652 2653 if (NewNumElts < OldNumElts) { 2654 if (NewEltSize % OldEltSize != 0) 2655 return UnableToLegalize; 2656 2657 // This only depends on powers of 2 because we use bit tricks to figure out 2658 // the bit offset we need to shift to get the target element. A general 2659 // expansion could emit division/multiply. 2660 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2661 return UnableToLegalize; 2662 2663 // Increasing the vector element size. 2664 // %elt:_(small_elt) = G_EXTRACT_VECTOR_ELT %vec:_(<N x small_elt>), %idx 2665 // 2666 // => 2667 // 2668 // %cast = G_BITCAST %vec 2669 // %scaled_idx = G_LSHR %idx, Log2(DstEltSize / SrcEltSize) 2670 // %wide_elt = G_EXTRACT_VECTOR_ELT %cast, %scaled_idx 2671 // %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2672 // %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2673 // %elt_bits = G_LSHR %wide_elt, %offset_bits 2674 // %elt = G_TRUNC %elt_bits 2675 2676 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2677 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2678 2679 // Divide to get the index in the wider element type. 2680 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2681 2682 Register WideElt = CastVec; 2683 if (CastTy.isVector()) { 2684 WideElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2685 ScaledIdx).getReg(0); 2686 } 2687 2688 // Compute the bit offset into the register of the target element. 2689 Register OffsetBits = getBitcastWiderVectorElementOffset( 2690 MIRBuilder, Idx, NewEltSize, OldEltSize); 2691 2692 // Shift the wide element to get the target element. 2693 auto ExtractedBits = MIRBuilder.buildLShr(NewEltTy, WideElt, OffsetBits); 2694 MIRBuilder.buildTrunc(Dst, ExtractedBits); 2695 MI.eraseFromParent(); 2696 return Legalized; 2697 } 2698 2699 return UnableToLegalize; 2700 } 2701 2702 /// Emit code to insert \p InsertReg into \p TargetRet at \p OffsetBits in \p 2703 /// TargetReg, while preserving other bits in \p TargetReg. 2704 /// 2705 /// (InsertReg << Offset) | (TargetReg & ~(-1 >> InsertReg.size()) << Offset) 2706 static Register buildBitFieldInsert(MachineIRBuilder &B, 2707 Register TargetReg, Register InsertReg, 2708 Register OffsetBits) { 2709 LLT TargetTy = B.getMRI()->getType(TargetReg); 2710 LLT InsertTy = B.getMRI()->getType(InsertReg); 2711 auto ZextVal = B.buildZExt(TargetTy, InsertReg); 2712 auto ShiftedInsertVal = B.buildShl(TargetTy, ZextVal, OffsetBits); 2713 2714 // Produce a bitmask of the value to insert 2715 auto EltMask = B.buildConstant( 2716 TargetTy, APInt::getLowBitsSet(TargetTy.getSizeInBits(), 2717 InsertTy.getSizeInBits())); 2718 // Shift it into position 2719 auto ShiftedMask = B.buildShl(TargetTy, EltMask, OffsetBits); 2720 auto InvShiftedMask = B.buildNot(TargetTy, ShiftedMask); 2721 2722 // Clear out the bits in the wide element 2723 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); 2724 2725 // The value to insert has all zeros already, so stick it into the masked 2726 // wide element. 2727 return B.buildOr(TargetTy, MaskedOldElt, ShiftedInsertVal).getReg(0); 2728 } 2729 2730 /// Perform a G_INSERT_VECTOR_ELT in a different sized vector element. If this 2731 /// is increasing the element size, perform the indexing in the target element 2732 /// type, and use bit operations to insert at the element position. This is 2733 /// intended for architectures that can dynamically index the register file and 2734 /// want to force indexing in the native register size. 2735 LegalizerHelper::LegalizeResult 2736 LegalizerHelper::bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, 2737 LLT CastTy) { 2738 if (TypeIdx != 0) 2739 return UnableToLegalize; 2740 2741 Register Dst = MI.getOperand(0).getReg(); 2742 Register SrcVec = MI.getOperand(1).getReg(); 2743 Register Val = MI.getOperand(2).getReg(); 2744 Register Idx = MI.getOperand(3).getReg(); 2745 2746 LLT VecTy = MRI.getType(Dst); 2747 LLT IdxTy = MRI.getType(Idx); 2748 2749 LLT VecEltTy = VecTy.getElementType(); 2750 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2751 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2752 const unsigned OldEltSize = VecEltTy.getSizeInBits(); 2753 2754 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2755 unsigned OldNumElts = VecTy.getNumElements(); 2756 2757 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2758 if (NewNumElts < OldNumElts) { 2759 if (NewEltSize % OldEltSize != 0) 2760 return UnableToLegalize; 2761 2762 // This only depends on powers of 2 because we use bit tricks to figure out 2763 // the bit offset we need to shift to get the target element. A general 2764 // expansion could emit division/multiply. 2765 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2766 return UnableToLegalize; 2767 2768 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2769 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2770 2771 // Divide to get the index in the wider element type. 2772 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2773 2774 Register ExtractedElt = CastVec; 2775 if (CastTy.isVector()) { 2776 ExtractedElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2777 ScaledIdx).getReg(0); 2778 } 2779 2780 // Compute the bit offset into the register of the target element. 2781 Register OffsetBits = getBitcastWiderVectorElementOffset( 2782 MIRBuilder, Idx, NewEltSize, OldEltSize); 2783 2784 Register InsertedElt = buildBitFieldInsert(MIRBuilder, ExtractedElt, 2785 Val, OffsetBits); 2786 if (CastTy.isVector()) { 2787 InsertedElt = MIRBuilder.buildInsertVectorElement( 2788 CastTy, CastVec, InsertedElt, ScaledIdx).getReg(0); 2789 } 2790 2791 MIRBuilder.buildBitcast(Dst, InsertedElt); 2792 MI.eraseFromParent(); 2793 return Legalized; 2794 } 2795 2796 return UnableToLegalize; 2797 } 2798 2799 LegalizerHelper::LegalizeResult LegalizerHelper::lowerLoad(GAnyLoad &LoadMI) { 2800 // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT 2801 Register DstReg = LoadMI.getDstReg(); 2802 Register PtrReg = LoadMI.getPointerReg(); 2803 LLT DstTy = MRI.getType(DstReg); 2804 MachineMemOperand &MMO = LoadMI.getMMO(); 2805 LLT MemTy = MMO.getMemoryType(); 2806 MachineFunction &MF = MIRBuilder.getMF(); 2807 if (MemTy.isVector()) 2808 return UnableToLegalize; 2809 2810 unsigned MemSizeInBits = MemTy.getSizeInBits(); 2811 unsigned MemStoreSizeInBits = 8 * MemTy.getSizeInBytes(); 2812 2813 if (MemSizeInBits != MemStoreSizeInBits) { 2814 // Promote to a byte-sized load if not loading an integral number of 2815 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 2816 LLT WideMemTy = LLT::scalar(MemStoreSizeInBits); 2817 MachineMemOperand *NewMMO = 2818 MF.getMachineMemOperand(&MMO, MMO.getPointerInfo(), WideMemTy); 2819 2820 Register LoadReg = DstReg; 2821 LLT LoadTy = DstTy; 2822 2823 // If this wasn't already an extending load, we need to widen the result 2824 // register to avoid creating a load with a narrower result than the source. 2825 if (MemStoreSizeInBits > DstTy.getSizeInBits()) { 2826 LoadTy = WideMemTy; 2827 LoadReg = MRI.createGenericVirtualRegister(WideMemTy); 2828 } 2829 2830 if (isa<GSExtLoad>(LoadMI)) { 2831 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); 2832 MIRBuilder.buildSExtInReg(LoadReg, NewLoad, MemSizeInBits); 2833 } else if (isa<GZExtLoad>(LoadMI) || WideMemTy == DstTy) { 2834 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); 2835 // The extra bits are guaranteed to be zero, since we stored them that 2836 // way. A zext load from Wide thus automatically gives zext from MemVT. 2837 MIRBuilder.buildAssertZExt(LoadReg, NewLoad, MemSizeInBits); 2838 } else { 2839 MIRBuilder.buildLoad(LoadReg, PtrReg, *NewMMO); 2840 } 2841 2842 if (DstTy != LoadTy) 2843 MIRBuilder.buildTrunc(DstReg, LoadReg); 2844 2845 LoadMI.eraseFromParent(); 2846 return Legalized; 2847 } 2848 2849 // This load needs splitting into power of 2 sized loads. 2850 if (DstTy.isVector()) 2851 return UnableToLegalize; 2852 if (isPowerOf2_32(MemSizeInBits)) 2853 return UnableToLegalize; // Don't know what we're being asked to do. 2854 2855 // Big endian lowering not implemented. 2856 if (MIRBuilder.getDataLayout().isBigEndian()) 2857 return UnableToLegalize; 2858 2859 // Our strategy here is to generate anyextending loads for the smaller 2860 // types up to next power-2 result type, and then combine the two larger 2861 // result values together, before truncating back down to the non-pow-2 2862 // type. 2863 // E.g. v1 = i24 load => 2864 // v2 = i32 zextload (2 byte) 2865 // v3 = i32 load (1 byte) 2866 // v4 = i32 shl v3, 16 2867 // v5 = i32 or v4, v2 2868 // v1 = i24 trunc v5 2869 // By doing this we generate the correct truncate which should get 2870 // combined away as an artifact with a matching extend. 2871 uint64_t LargeSplitSize = PowerOf2Floor(MemSizeInBits); 2872 uint64_t SmallSplitSize = MemSizeInBits - LargeSplitSize; 2873 2874 MachineMemOperand *LargeMMO = 2875 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2876 MachineMemOperand *SmallMMO = 2877 MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2878 2879 LLT PtrTy = MRI.getType(PtrReg); 2880 unsigned AnyExtSize = PowerOf2Ceil(DstTy.getSizeInBits()); 2881 LLT AnyExtTy = LLT::scalar(AnyExtSize); 2882 auto LargeLoad = MIRBuilder.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, AnyExtTy, 2883 PtrReg, *LargeMMO); 2884 2885 auto OffsetCst = MIRBuilder.buildConstant(LLT::scalar(PtrTy.getSizeInBits()), 2886 LargeSplitSize / 8); 2887 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2888 auto SmallPtr = MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); 2889 auto SmallLoad = MIRBuilder.buildLoadInstr(LoadMI.getOpcode(), AnyExtTy, 2890 SmallPtr, *SmallMMO); 2891 2892 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize); 2893 auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt); 2894 2895 if (AnyExtTy == DstTy) 2896 MIRBuilder.buildOr(DstReg, Shift, LargeLoad); 2897 else { 2898 auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad); 2899 MIRBuilder.buildTrunc(DstReg, {Or}); 2900 } 2901 2902 LoadMI.eraseFromParent(); 2903 return Legalized; 2904 } 2905 2906 LegalizerHelper::LegalizeResult LegalizerHelper::lowerStore(GStore &StoreMI) { 2907 // Lower a non-power of 2 store into multiple pow-2 stores. 2908 // E.g. split an i24 store into an i16 store + i8 store. 2909 // We do this by first extending the stored value to the next largest power 2910 // of 2 type, and then using truncating stores to store the components. 2911 // By doing this, likewise with G_LOAD, generate an extend that can be 2912 // artifact-combined away instead of leaving behind extracts. 2913 Register SrcReg = StoreMI.getValueReg(); 2914 Register PtrReg = StoreMI.getPointerReg(); 2915 LLT SrcTy = MRI.getType(SrcReg); 2916 MachineFunction &MF = MIRBuilder.getMF(); 2917 MachineMemOperand &MMO = **StoreMI.memoperands_begin(); 2918 LLT MemTy = MMO.getMemoryType(); 2919 2920 if (SrcTy.isVector()) 2921 return UnableToLegalize; 2922 2923 unsigned StoreWidth = MemTy.getSizeInBits(); 2924 unsigned StoreSizeInBits = 8 * MemTy.getSizeInBytes(); 2925 2926 if (StoreWidth != StoreSizeInBits) { 2927 // Promote to a byte-sized store with upper bits zero if not 2928 // storing an integral number of bytes. For example, promote 2929 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2930 LLT WideTy = LLT::scalar(StoreSizeInBits); 2931 2932 if (StoreSizeInBits > SrcTy.getSizeInBits()) { 2933 // Avoid creating a store with a narrower source than result. 2934 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); 2935 SrcTy = WideTy; 2936 } 2937 2938 auto ZextInReg = MIRBuilder.buildZExtInReg(SrcTy, SrcReg, StoreWidth); 2939 2940 MachineMemOperand *NewMMO = 2941 MF.getMachineMemOperand(&MMO, MMO.getPointerInfo(), WideTy); 2942 MIRBuilder.buildStore(ZextInReg, PtrReg, *NewMMO); 2943 StoreMI.eraseFromParent(); 2944 return Legalized; 2945 } 2946 2947 if (isPowerOf2_32(MemTy.getSizeInBits())) 2948 return UnableToLegalize; // Don't know what we're being asked to do. 2949 2950 // Extend to the next pow-2. If this store was itself the result of lowering, 2951 // e.g. an s56 store being broken into s32 + s24, we might have a stored type 2952 // that's wider the stored size. 2953 const LLT NewSrcTy = LLT::scalar(NextPowerOf2(MemTy.getSizeInBits())); 2954 auto ExtVal = MIRBuilder.buildAnyExtOrTrunc(NewSrcTy, SrcReg); 2955 2956 // Obtain the smaller value by shifting away the larger value. 2957 uint64_t LargeSplitSize = PowerOf2Floor(MemTy.getSizeInBits()); 2958 uint64_t SmallSplitSize = MemTy.getSizeInBits() - LargeSplitSize; 2959 auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, LargeSplitSize); 2960 auto SmallVal = MIRBuilder.buildLShr(NewSrcTy, ExtVal, ShiftAmt); 2961 2962 // Generate the PtrAdd and truncating stores. 2963 LLT PtrTy = MRI.getType(PtrReg); 2964 auto OffsetCst = MIRBuilder.buildConstant( 2965 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2966 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2967 auto SmallPtr = 2968 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); 2969 2970 MachineMemOperand *LargeMMO = 2971 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2972 MachineMemOperand *SmallMMO = 2973 MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2974 MIRBuilder.buildStore(ExtVal, PtrReg, *LargeMMO); 2975 MIRBuilder.buildStore(SmallVal, SmallPtr, *SmallMMO); 2976 StoreMI.eraseFromParent(); 2977 return Legalized; 2978 } 2979 2980 LegalizerHelper::LegalizeResult 2981 LegalizerHelper::bitcast(MachineInstr &MI, unsigned TypeIdx, LLT CastTy) { 2982 switch (MI.getOpcode()) { 2983 case TargetOpcode::G_LOAD: { 2984 if (TypeIdx != 0) 2985 return UnableToLegalize; 2986 2987 Observer.changingInstr(MI); 2988 bitcastDst(MI, CastTy, 0); 2989 Observer.changedInstr(MI); 2990 return Legalized; 2991 } 2992 case TargetOpcode::G_STORE: { 2993 if (TypeIdx != 0) 2994 return UnableToLegalize; 2995 2996 Observer.changingInstr(MI); 2997 bitcastSrc(MI, CastTy, 0); 2998 Observer.changedInstr(MI); 2999 return Legalized; 3000 } 3001 case TargetOpcode::G_SELECT: { 3002 if (TypeIdx != 0) 3003 return UnableToLegalize; 3004 3005 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) { 3006 LLVM_DEBUG( 3007 dbgs() << "bitcast action not implemented for vector select\n"); 3008 return UnableToLegalize; 3009 } 3010 3011 Observer.changingInstr(MI); 3012 bitcastSrc(MI, CastTy, 2); 3013 bitcastSrc(MI, CastTy, 3); 3014 bitcastDst(MI, CastTy, 0); 3015 Observer.changedInstr(MI); 3016 return Legalized; 3017 } 3018 case TargetOpcode::G_AND: 3019 case TargetOpcode::G_OR: 3020 case TargetOpcode::G_XOR: { 3021 Observer.changingInstr(MI); 3022 bitcastSrc(MI, CastTy, 1); 3023 bitcastSrc(MI, CastTy, 2); 3024 bitcastDst(MI, CastTy, 0); 3025 Observer.changedInstr(MI); 3026 return Legalized; 3027 } 3028 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 3029 return bitcastExtractVectorElt(MI, TypeIdx, CastTy); 3030 case TargetOpcode::G_INSERT_VECTOR_ELT: 3031 return bitcastInsertVectorElt(MI, TypeIdx, CastTy); 3032 default: 3033 return UnableToLegalize; 3034 } 3035 } 3036 3037 // Legalize an instruction by changing the opcode in place. 3038 void LegalizerHelper::changeOpcode(MachineInstr &MI, unsigned NewOpcode) { 3039 Observer.changingInstr(MI); 3040 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); 3041 Observer.changedInstr(MI); 3042 } 3043 3044 LegalizerHelper::LegalizeResult 3045 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) { 3046 using namespace TargetOpcode; 3047 3048 switch(MI.getOpcode()) { 3049 default: 3050 return UnableToLegalize; 3051 case TargetOpcode::G_BITCAST: 3052 return lowerBitcast(MI); 3053 case TargetOpcode::G_SREM: 3054 case TargetOpcode::G_UREM: { 3055 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3056 auto Quot = 3057 MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {Ty}, 3058 {MI.getOperand(1), MI.getOperand(2)}); 3059 3060 auto Prod = MIRBuilder.buildMul(Ty, Quot, MI.getOperand(2)); 3061 MIRBuilder.buildSub(MI.getOperand(0), MI.getOperand(1), Prod); 3062 MI.eraseFromParent(); 3063 return Legalized; 3064 } 3065 case TargetOpcode::G_SADDO: 3066 case TargetOpcode::G_SSUBO: 3067 return lowerSADDO_SSUBO(MI); 3068 case TargetOpcode::G_UMULH: 3069 case TargetOpcode::G_SMULH: 3070 return lowerSMULH_UMULH(MI); 3071 case TargetOpcode::G_SMULO: 3072 case TargetOpcode::G_UMULO: { 3073 // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the 3074 // result. 3075 Register Res = MI.getOperand(0).getReg(); 3076 Register Overflow = MI.getOperand(1).getReg(); 3077 Register LHS = MI.getOperand(2).getReg(); 3078 Register RHS = MI.getOperand(3).getReg(); 3079 LLT Ty = MRI.getType(Res); 3080 3081 unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO 3082 ? TargetOpcode::G_SMULH 3083 : TargetOpcode::G_UMULH; 3084 3085 Observer.changingInstr(MI); 3086 const auto &TII = MIRBuilder.getTII(); 3087 MI.setDesc(TII.get(TargetOpcode::G_MUL)); 3088 MI.RemoveOperand(1); 3089 Observer.changedInstr(MI); 3090 3091 auto HiPart = MIRBuilder.buildInstr(Opcode, {Ty}, {LHS, RHS}); 3092 auto Zero = MIRBuilder.buildConstant(Ty, 0); 3093 3094 // Move insert point forward so we can use the Res register if needed. 3095 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 3096 3097 // For *signed* multiply, overflow is detected by checking: 3098 // (hi != (lo >> bitwidth-1)) 3099 if (Opcode == TargetOpcode::G_SMULH) { 3100 auto ShiftAmt = MIRBuilder.buildConstant(Ty, Ty.getSizeInBits() - 1); 3101 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); 3102 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted); 3103 } else { 3104 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero); 3105 } 3106 return Legalized; 3107 } 3108 case TargetOpcode::G_FNEG: { 3109 Register Res = MI.getOperand(0).getReg(); 3110 LLT Ty = MRI.getType(Res); 3111 3112 // TODO: Handle vector types once we are able to 3113 // represent them. 3114 if (Ty.isVector()) 3115 return UnableToLegalize; 3116 auto SignMask = 3117 MIRBuilder.buildConstant(Ty, APInt::getSignMask(Ty.getSizeInBits())); 3118 Register SubByReg = MI.getOperand(1).getReg(); 3119 MIRBuilder.buildXor(Res, SubByReg, SignMask); 3120 MI.eraseFromParent(); 3121 return Legalized; 3122 } 3123 case TargetOpcode::G_FSUB: { 3124 Register Res = MI.getOperand(0).getReg(); 3125 LLT Ty = MRI.getType(Res); 3126 3127 // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)). 3128 // First, check if G_FNEG is marked as Lower. If so, we may 3129 // end up with an infinite loop as G_FSUB is used to legalize G_FNEG. 3130 if (LI.getAction({G_FNEG, {Ty}}).Action == Lower) 3131 return UnableToLegalize; 3132 Register LHS = MI.getOperand(1).getReg(); 3133 Register RHS = MI.getOperand(2).getReg(); 3134 Register Neg = MRI.createGenericVirtualRegister(Ty); 3135 MIRBuilder.buildFNeg(Neg, RHS); 3136 MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags()); 3137 MI.eraseFromParent(); 3138 return Legalized; 3139 } 3140 case TargetOpcode::G_FMAD: 3141 return lowerFMad(MI); 3142 case TargetOpcode::G_FFLOOR: 3143 return lowerFFloor(MI); 3144 case TargetOpcode::G_INTRINSIC_ROUND: 3145 return lowerIntrinsicRound(MI); 3146 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 3147 // Since round even is the assumed rounding mode for unconstrained FP 3148 // operations, rint and roundeven are the same operation. 3149 changeOpcode(MI, TargetOpcode::G_FRINT); 3150 return Legalized; 3151 } 3152 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: { 3153 Register OldValRes = MI.getOperand(0).getReg(); 3154 Register SuccessRes = MI.getOperand(1).getReg(); 3155 Register Addr = MI.getOperand(2).getReg(); 3156 Register CmpVal = MI.getOperand(3).getReg(); 3157 Register NewVal = MI.getOperand(4).getReg(); 3158 MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal, 3159 **MI.memoperands_begin()); 3160 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal); 3161 MI.eraseFromParent(); 3162 return Legalized; 3163 } 3164 case TargetOpcode::G_LOAD: 3165 case TargetOpcode::G_SEXTLOAD: 3166 case TargetOpcode::G_ZEXTLOAD: 3167 return lowerLoad(cast<GAnyLoad>(MI)); 3168 case TargetOpcode::G_STORE: 3169 return lowerStore(cast<GStore>(MI)); 3170 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 3171 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 3172 case TargetOpcode::G_CTLZ: 3173 case TargetOpcode::G_CTTZ: 3174 case TargetOpcode::G_CTPOP: 3175 return lowerBitCount(MI); 3176 case G_UADDO: { 3177 Register Res = MI.getOperand(0).getReg(); 3178 Register CarryOut = MI.getOperand(1).getReg(); 3179 Register LHS = MI.getOperand(2).getReg(); 3180 Register RHS = MI.getOperand(3).getReg(); 3181 3182 MIRBuilder.buildAdd(Res, LHS, RHS); 3183 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS); 3184 3185 MI.eraseFromParent(); 3186 return Legalized; 3187 } 3188 case G_UADDE: { 3189 Register Res = MI.getOperand(0).getReg(); 3190 Register CarryOut = MI.getOperand(1).getReg(); 3191 Register LHS = MI.getOperand(2).getReg(); 3192 Register RHS = MI.getOperand(3).getReg(); 3193 Register CarryIn = MI.getOperand(4).getReg(); 3194 LLT Ty = MRI.getType(Res); 3195 3196 auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS); 3197 auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); 3198 MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn); 3199 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS); 3200 3201 MI.eraseFromParent(); 3202 return Legalized; 3203 } 3204 case G_USUBO: { 3205 Register Res = MI.getOperand(0).getReg(); 3206 Register BorrowOut = MI.getOperand(1).getReg(); 3207 Register LHS = MI.getOperand(2).getReg(); 3208 Register RHS = MI.getOperand(3).getReg(); 3209 3210 MIRBuilder.buildSub(Res, LHS, RHS); 3211 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS); 3212 3213 MI.eraseFromParent(); 3214 return Legalized; 3215 } 3216 case G_USUBE: { 3217 Register Res = MI.getOperand(0).getReg(); 3218 Register BorrowOut = MI.getOperand(1).getReg(); 3219 Register LHS = MI.getOperand(2).getReg(); 3220 Register RHS = MI.getOperand(3).getReg(); 3221 Register BorrowIn = MI.getOperand(4).getReg(); 3222 const LLT CondTy = MRI.getType(BorrowOut); 3223 const LLT Ty = MRI.getType(Res); 3224 3225 auto TmpRes = MIRBuilder.buildSub(Ty, LHS, RHS); 3226 auto ZExtBorrowIn = MIRBuilder.buildZExt(Ty, BorrowIn); 3227 MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn); 3228 3229 auto LHS_EQ_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, LHS, RHS); 3230 auto LHS_ULT_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, LHS, RHS); 3231 MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS); 3232 3233 MI.eraseFromParent(); 3234 return Legalized; 3235 } 3236 case G_UITOFP: 3237 return lowerUITOFP(MI); 3238 case G_SITOFP: 3239 return lowerSITOFP(MI); 3240 case G_FPTOUI: 3241 return lowerFPTOUI(MI); 3242 case G_FPTOSI: 3243 return lowerFPTOSI(MI); 3244 case G_FPTRUNC: 3245 return lowerFPTRUNC(MI); 3246 case G_FPOWI: 3247 return lowerFPOWI(MI); 3248 case G_SMIN: 3249 case G_SMAX: 3250 case G_UMIN: 3251 case G_UMAX: 3252 return lowerMinMax(MI); 3253 case G_FCOPYSIGN: 3254 return lowerFCopySign(MI); 3255 case G_FMINNUM: 3256 case G_FMAXNUM: 3257 return lowerFMinNumMaxNum(MI); 3258 case G_MERGE_VALUES: 3259 return lowerMergeValues(MI); 3260 case G_UNMERGE_VALUES: 3261 return lowerUnmergeValues(MI); 3262 case TargetOpcode::G_SEXT_INREG: { 3263 assert(MI.getOperand(2).isImm() && "Expected immediate"); 3264 int64_t SizeInBits = MI.getOperand(2).getImm(); 3265 3266 Register DstReg = MI.getOperand(0).getReg(); 3267 Register SrcReg = MI.getOperand(1).getReg(); 3268 LLT DstTy = MRI.getType(DstReg); 3269 Register TmpRes = MRI.createGenericVirtualRegister(DstTy); 3270 3271 auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits); 3272 MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0)); 3273 MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0)); 3274 MI.eraseFromParent(); 3275 return Legalized; 3276 } 3277 case G_EXTRACT_VECTOR_ELT: 3278 case G_INSERT_VECTOR_ELT: 3279 return lowerExtractInsertVectorElt(MI); 3280 case G_SHUFFLE_VECTOR: 3281 return lowerShuffleVector(MI); 3282 case G_DYN_STACKALLOC: 3283 return lowerDynStackAlloc(MI); 3284 case G_EXTRACT: 3285 return lowerExtract(MI); 3286 case G_INSERT: 3287 return lowerInsert(MI); 3288 case G_BSWAP: 3289 return lowerBswap(MI); 3290 case G_BITREVERSE: 3291 return lowerBitreverse(MI); 3292 case G_READ_REGISTER: 3293 case G_WRITE_REGISTER: 3294 return lowerReadWriteRegister(MI); 3295 case G_UADDSAT: 3296 case G_USUBSAT: { 3297 // Try to make a reasonable guess about which lowering strategy to use. The 3298 // target can override this with custom lowering and calling the 3299 // implementation functions. 3300 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3301 if (LI.isLegalOrCustom({G_UMIN, Ty})) 3302 return lowerAddSubSatToMinMax(MI); 3303 return lowerAddSubSatToAddoSubo(MI); 3304 } 3305 case G_SADDSAT: 3306 case G_SSUBSAT: { 3307 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3308 3309 // FIXME: It would probably make more sense to see if G_SADDO is preferred, 3310 // since it's a shorter expansion. However, we would need to figure out the 3311 // preferred boolean type for the carry out for the query. 3312 if (LI.isLegalOrCustom({G_SMIN, Ty}) && LI.isLegalOrCustom({G_SMAX, Ty})) 3313 return lowerAddSubSatToMinMax(MI); 3314 return lowerAddSubSatToAddoSubo(MI); 3315 } 3316 case G_SSHLSAT: 3317 case G_USHLSAT: 3318 return lowerShlSat(MI); 3319 case G_ABS: 3320 return lowerAbsToAddXor(MI); 3321 case G_SELECT: 3322 return lowerSelect(MI); 3323 case G_SDIVREM: 3324 case G_UDIVREM: 3325 return lowerDIVREM(MI); 3326 case G_FSHL: 3327 case G_FSHR: 3328 return lowerFunnelShift(MI); 3329 case G_ROTL: 3330 case G_ROTR: 3331 return lowerRotate(MI); 3332 } 3333 } 3334 3335 Align LegalizerHelper::getStackTemporaryAlignment(LLT Ty, 3336 Align MinAlign) const { 3337 // FIXME: We're missing a way to go back from LLT to llvm::Type to query the 3338 // datalayout for the preferred alignment. Also there should be a target hook 3339 // for this to allow targets to reduce the alignment and ignore the 3340 // datalayout. e.g. AMDGPU should always use a 4-byte alignment, regardless of 3341 // the type. 3342 return std::max(Align(PowerOf2Ceil(Ty.getSizeInBytes())), MinAlign); 3343 } 3344 3345 MachineInstrBuilder 3346 LegalizerHelper::createStackTemporary(TypeSize Bytes, Align Alignment, 3347 MachinePointerInfo &PtrInfo) { 3348 MachineFunction &MF = MIRBuilder.getMF(); 3349 const DataLayout &DL = MIRBuilder.getDataLayout(); 3350 int FrameIdx = MF.getFrameInfo().CreateStackObject(Bytes, Alignment, false); 3351 3352 unsigned AddrSpace = DL.getAllocaAddrSpace(); 3353 LLT FramePtrTy = LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace)); 3354 3355 PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIdx); 3356 return MIRBuilder.buildFrameIndex(FramePtrTy, FrameIdx); 3357 } 3358 3359 static Register clampDynamicVectorIndex(MachineIRBuilder &B, Register IdxReg, 3360 LLT VecTy) { 3361 int64_t IdxVal; 3362 if (mi_match(IdxReg, *B.getMRI(), m_ICst(IdxVal))) 3363 return IdxReg; 3364 3365 LLT IdxTy = B.getMRI()->getType(IdxReg); 3366 unsigned NElts = VecTy.getNumElements(); 3367 if (isPowerOf2_32(NElts)) { 3368 APInt Imm = APInt::getLowBitsSet(IdxTy.getSizeInBits(), Log2_32(NElts)); 3369 return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0); 3370 } 3371 3372 return B.buildUMin(IdxTy, IdxReg, B.buildConstant(IdxTy, NElts - 1)) 3373 .getReg(0); 3374 } 3375 3376 Register LegalizerHelper::getVectorElementPointer(Register VecPtr, LLT VecTy, 3377 Register Index) { 3378 LLT EltTy = VecTy.getElementType(); 3379 3380 // Calculate the element offset and add it to the pointer. 3381 unsigned EltSize = EltTy.getSizeInBits() / 8; // FIXME: should be ABI size. 3382 assert(EltSize * 8 == EltTy.getSizeInBits() && 3383 "Converting bits to bytes lost precision"); 3384 3385 Index = clampDynamicVectorIndex(MIRBuilder, Index, VecTy); 3386 3387 LLT IdxTy = MRI.getType(Index); 3388 auto Mul = MIRBuilder.buildMul(IdxTy, Index, 3389 MIRBuilder.buildConstant(IdxTy, EltSize)); 3390 3391 LLT PtrTy = MRI.getType(VecPtr); 3392 return MIRBuilder.buildPtrAdd(PtrTy, VecPtr, Mul).getReg(0); 3393 } 3394 3395 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef( 3396 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) { 3397 Register DstReg = MI.getOperand(0).getReg(); 3398 LLT DstTy = MRI.getType(DstReg); 3399 LLT LCMTy = getLCMType(DstTy, NarrowTy); 3400 3401 unsigned NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 3402 3403 auto NewUndef = MIRBuilder.buildUndef(NarrowTy); 3404 SmallVector<Register, 8> Parts(NumParts, NewUndef.getReg(0)); 3405 3406 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3407 MI.eraseFromParent(); 3408 return Legalized; 3409 } 3410 3411 // Handle splitting vector operations which need to have the same number of 3412 // elements in each type index, but each type index may have a different element 3413 // type. 3414 // 3415 // e.g. <4 x s64> = G_SHL <4 x s64>, <4 x s32> -> 3416 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3417 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3418 // 3419 // Also handles some irregular breakdown cases, e.g. 3420 // e.g. <3 x s64> = G_SHL <3 x s64>, <3 x s32> -> 3421 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3422 // s64 = G_SHL s64, s32 3423 LegalizerHelper::LegalizeResult 3424 LegalizerHelper::fewerElementsVectorMultiEltType( 3425 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) { 3426 if (TypeIdx != 0) 3427 return UnableToLegalize; 3428 3429 const LLT NarrowTy0 = NarrowTyArg; 3430 const Register DstReg = MI.getOperand(0).getReg(); 3431 LLT DstTy = MRI.getType(DstReg); 3432 LLT LeftoverTy0; 3433 3434 // All of the operands need to have the same number of elements, so if we can 3435 // determine a type breakdown for the result type, we can for all of the 3436 // source types. 3437 int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first; 3438 if (NumParts < 0) 3439 return UnableToLegalize; 3440 3441 SmallVector<MachineInstrBuilder, 4> NewInsts; 3442 3443 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3444 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3445 3446 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) { 3447 Register SrcReg = MI.getOperand(I).getReg(); 3448 LLT SrcTyI = MRI.getType(SrcReg); 3449 const auto NewEC = NarrowTy0.isVector() ? NarrowTy0.getElementCount() 3450 : ElementCount::getFixed(1); 3451 LLT NarrowTyI = LLT::scalarOrVector(NewEC, SrcTyI.getScalarType()); 3452 LLT LeftoverTyI; 3453 3454 // Split this operand into the requested typed registers, and any leftover 3455 // required to reproduce the original type. 3456 if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs, 3457 LeftoverRegs)) 3458 return UnableToLegalize; 3459 3460 if (I == 1) { 3461 // For the first operand, create an instruction for each part and setup 3462 // the result. 3463 for (Register PartReg : PartRegs) { 3464 Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3465 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3466 .addDef(PartDstReg) 3467 .addUse(PartReg)); 3468 DstRegs.push_back(PartDstReg); 3469 } 3470 3471 for (Register LeftoverReg : LeftoverRegs) { 3472 Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0); 3473 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3474 .addDef(PartDstReg) 3475 .addUse(LeftoverReg)); 3476 LeftoverDstRegs.push_back(PartDstReg); 3477 } 3478 } else { 3479 assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size()); 3480 3481 // Add the newly created operand splits to the existing instructions. The 3482 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3483 // pieces. 3484 unsigned InstCount = 0; 3485 for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J) 3486 NewInsts[InstCount++].addUse(PartRegs[J]); 3487 for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J) 3488 NewInsts[InstCount++].addUse(LeftoverRegs[J]); 3489 } 3490 3491 PartRegs.clear(); 3492 LeftoverRegs.clear(); 3493 } 3494 3495 // Insert the newly built operations and rebuild the result register. 3496 for (auto &MIB : NewInsts) 3497 MIRBuilder.insertInstr(MIB); 3498 3499 insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs); 3500 3501 MI.eraseFromParent(); 3502 return Legalized; 3503 } 3504 3505 LegalizerHelper::LegalizeResult 3506 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx, 3507 LLT NarrowTy) { 3508 if (TypeIdx != 0) 3509 return UnableToLegalize; 3510 3511 Register DstReg = MI.getOperand(0).getReg(); 3512 Register SrcReg = MI.getOperand(1).getReg(); 3513 LLT DstTy = MRI.getType(DstReg); 3514 LLT SrcTy = MRI.getType(SrcReg); 3515 3516 LLT NarrowTy0 = NarrowTy; 3517 LLT NarrowTy1; 3518 unsigned NumParts; 3519 3520 if (NarrowTy.isVector()) { 3521 // Uneven breakdown not handled. 3522 NumParts = DstTy.getNumElements() / NarrowTy.getNumElements(); 3523 if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements()) 3524 return UnableToLegalize; 3525 3526 NarrowTy1 = LLT::vector(NarrowTy.getElementCount(), SrcTy.getElementType()); 3527 } else { 3528 NumParts = DstTy.getNumElements(); 3529 NarrowTy1 = SrcTy.getElementType(); 3530 } 3531 3532 SmallVector<Register, 4> SrcRegs, DstRegs; 3533 extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs); 3534 3535 for (unsigned I = 0; I < NumParts; ++I) { 3536 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3537 MachineInstr *NewInst = 3538 MIRBuilder.buildInstr(MI.getOpcode(), {DstReg}, {SrcRegs[I]}); 3539 3540 NewInst->setFlags(MI.getFlags()); 3541 DstRegs.push_back(DstReg); 3542 } 3543 3544 if (NarrowTy.isVector()) 3545 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3546 else 3547 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3548 3549 MI.eraseFromParent(); 3550 return Legalized; 3551 } 3552 3553 LegalizerHelper::LegalizeResult 3554 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx, 3555 LLT NarrowTy) { 3556 Register DstReg = MI.getOperand(0).getReg(); 3557 Register Src0Reg = MI.getOperand(2).getReg(); 3558 LLT DstTy = MRI.getType(DstReg); 3559 LLT SrcTy = MRI.getType(Src0Reg); 3560 3561 unsigned NumParts; 3562 LLT NarrowTy0, NarrowTy1; 3563 3564 if (TypeIdx == 0) { 3565 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3566 unsigned OldElts = DstTy.getNumElements(); 3567 3568 NarrowTy0 = NarrowTy; 3569 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements(); 3570 NarrowTy1 = NarrowTy.isVector() ? LLT::vector(NarrowTy.getElementCount(), 3571 SrcTy.getScalarSizeInBits()) 3572 : SrcTy.getElementType(); 3573 3574 } else { 3575 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3576 unsigned OldElts = SrcTy.getNumElements(); 3577 3578 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : 3579 NarrowTy.getNumElements(); 3580 NarrowTy0 = 3581 LLT::vector(NarrowTy.getElementCount(), DstTy.getScalarSizeInBits()); 3582 NarrowTy1 = NarrowTy; 3583 } 3584 3585 // FIXME: Don't know how to handle the situation where the small vectors 3586 // aren't all the same size yet. 3587 if (NarrowTy1.isVector() && 3588 NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements()) 3589 return UnableToLegalize; 3590 3591 CmpInst::Predicate Pred 3592 = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 3593 3594 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 3595 extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs); 3596 extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs); 3597 3598 for (unsigned I = 0; I < NumParts; ++I) { 3599 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3600 DstRegs.push_back(DstReg); 3601 3602 if (MI.getOpcode() == TargetOpcode::G_ICMP) 3603 MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3604 else { 3605 MachineInstr *NewCmp 3606 = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3607 NewCmp->setFlags(MI.getFlags()); 3608 } 3609 } 3610 3611 if (NarrowTy1.isVector()) 3612 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3613 else 3614 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3615 3616 MI.eraseFromParent(); 3617 return Legalized; 3618 } 3619 3620 LegalizerHelper::LegalizeResult 3621 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, 3622 LLT NarrowTy) { 3623 Register DstReg = MI.getOperand(0).getReg(); 3624 Register CondReg = MI.getOperand(1).getReg(); 3625 3626 unsigned NumParts = 0; 3627 LLT NarrowTy0, NarrowTy1; 3628 3629 LLT DstTy = MRI.getType(DstReg); 3630 LLT CondTy = MRI.getType(CondReg); 3631 unsigned Size = DstTy.getSizeInBits(); 3632 3633 assert(TypeIdx == 0 || CondTy.isVector()); 3634 3635 if (TypeIdx == 0) { 3636 NarrowTy0 = NarrowTy; 3637 NarrowTy1 = CondTy; 3638 3639 unsigned NarrowSize = NarrowTy0.getSizeInBits(); 3640 // FIXME: Don't know how to handle the situation where the small vectors 3641 // aren't all the same size yet. 3642 if (Size % NarrowSize != 0) 3643 return UnableToLegalize; 3644 3645 NumParts = Size / NarrowSize; 3646 3647 // Need to break down the condition type 3648 if (CondTy.isVector()) { 3649 if (CondTy.getNumElements() == NumParts) 3650 NarrowTy1 = CondTy.getElementType(); 3651 else 3652 NarrowTy1 = 3653 LLT::vector(CondTy.getElementCount().divideCoefficientBy(NumParts), 3654 CondTy.getScalarSizeInBits()); 3655 } 3656 } else { 3657 NumParts = CondTy.getNumElements(); 3658 if (NarrowTy.isVector()) { 3659 // TODO: Handle uneven breakdown. 3660 if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements()) 3661 return UnableToLegalize; 3662 3663 return UnableToLegalize; 3664 } else { 3665 NarrowTy0 = DstTy.getElementType(); 3666 NarrowTy1 = NarrowTy; 3667 } 3668 } 3669 3670 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs; 3671 if (CondTy.isVector()) 3672 extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs); 3673 3674 extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs); 3675 extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs); 3676 3677 for (unsigned i = 0; i < NumParts; ++i) { 3678 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3679 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg, 3680 Src1Regs[i], Src2Regs[i]); 3681 DstRegs.push_back(DstReg); 3682 } 3683 3684 if (NarrowTy0.isVector()) 3685 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3686 else 3687 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3688 3689 MI.eraseFromParent(); 3690 return Legalized; 3691 } 3692 3693 LegalizerHelper::LegalizeResult 3694 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 3695 LLT NarrowTy) { 3696 const Register DstReg = MI.getOperand(0).getReg(); 3697 LLT PhiTy = MRI.getType(DstReg); 3698 LLT LeftoverTy; 3699 3700 // All of the operands need to have the same number of elements, so if we can 3701 // determine a type breakdown for the result type, we can for all of the 3702 // source types. 3703 int NumParts, NumLeftover; 3704 std::tie(NumParts, NumLeftover) 3705 = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy); 3706 if (NumParts < 0) 3707 return UnableToLegalize; 3708 3709 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3710 SmallVector<MachineInstrBuilder, 4> NewInsts; 3711 3712 const int TotalNumParts = NumParts + NumLeftover; 3713 3714 // Insert the new phis in the result block first. 3715 for (int I = 0; I != TotalNumParts; ++I) { 3716 LLT Ty = I < NumParts ? NarrowTy : LeftoverTy; 3717 Register PartDstReg = MRI.createGenericVirtualRegister(Ty); 3718 NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI) 3719 .addDef(PartDstReg)); 3720 if (I < NumParts) 3721 DstRegs.push_back(PartDstReg); 3722 else 3723 LeftoverDstRegs.push_back(PartDstReg); 3724 } 3725 3726 MachineBasicBlock *MBB = MI.getParent(); 3727 MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI()); 3728 insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs); 3729 3730 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3731 3732 // Insert code to extract the incoming values in each predecessor block. 3733 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 3734 PartRegs.clear(); 3735 LeftoverRegs.clear(); 3736 3737 Register SrcReg = MI.getOperand(I).getReg(); 3738 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 3739 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 3740 3741 LLT Unused; 3742 if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs, 3743 LeftoverRegs)) 3744 return UnableToLegalize; 3745 3746 // Add the newly created operand splits to the existing instructions. The 3747 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3748 // pieces. 3749 for (int J = 0; J != TotalNumParts; ++J) { 3750 MachineInstrBuilder MIB = NewInsts[J]; 3751 MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]); 3752 MIB.addMBB(&OpMBB); 3753 } 3754 } 3755 3756 MI.eraseFromParent(); 3757 return Legalized; 3758 } 3759 3760 LegalizerHelper::LegalizeResult 3761 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI, 3762 unsigned TypeIdx, 3763 LLT NarrowTy) { 3764 if (TypeIdx != 1) 3765 return UnableToLegalize; 3766 3767 const int NumDst = MI.getNumOperands() - 1; 3768 const Register SrcReg = MI.getOperand(NumDst).getReg(); 3769 LLT SrcTy = MRI.getType(SrcReg); 3770 3771 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 3772 3773 // TODO: Create sequence of extracts. 3774 if (DstTy == NarrowTy) 3775 return UnableToLegalize; 3776 3777 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3778 if (DstTy == GCDTy) { 3779 // This would just be a copy of the same unmerge. 3780 // TODO: Create extracts, pad with undef and create intermediate merges. 3781 return UnableToLegalize; 3782 } 3783 3784 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 3785 const int NumUnmerge = Unmerge->getNumOperands() - 1; 3786 const int PartsPerUnmerge = NumDst / NumUnmerge; 3787 3788 for (int I = 0; I != NumUnmerge; ++I) { 3789 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 3790 3791 for (int J = 0; J != PartsPerUnmerge; ++J) 3792 MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg()); 3793 MIB.addUse(Unmerge.getReg(I)); 3794 } 3795 3796 MI.eraseFromParent(); 3797 return Legalized; 3798 } 3799 3800 LegalizerHelper::LegalizeResult 3801 LegalizerHelper::fewerElementsVectorMulo(MachineInstr &MI, unsigned TypeIdx, 3802 LLT NarrowTy) { 3803 Register Result = MI.getOperand(0).getReg(); 3804 Register Overflow = MI.getOperand(1).getReg(); 3805 Register LHS = MI.getOperand(2).getReg(); 3806 Register RHS = MI.getOperand(3).getReg(); 3807 3808 LLT SrcTy = MRI.getType(LHS); 3809 if (!SrcTy.isVector()) 3810 return UnableToLegalize; 3811 3812 LLT ElementType = SrcTy.getElementType(); 3813 LLT OverflowElementTy = MRI.getType(Overflow).getElementType(); 3814 const ElementCount NumResult = SrcTy.getElementCount(); 3815 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3816 3817 // Unmerge the operands to smaller parts of GCD type. 3818 auto UnmergeLHS = MIRBuilder.buildUnmerge(GCDTy, LHS); 3819 auto UnmergeRHS = MIRBuilder.buildUnmerge(GCDTy, RHS); 3820 3821 const int NumOps = UnmergeLHS->getNumOperands() - 1; 3822 const ElementCount PartsPerUnmerge = NumResult.divideCoefficientBy(NumOps); 3823 LLT OverflowTy = LLT::scalarOrVector(PartsPerUnmerge, OverflowElementTy); 3824 LLT ResultTy = LLT::scalarOrVector(PartsPerUnmerge, ElementType); 3825 3826 // Perform the operation over unmerged parts. 3827 SmallVector<Register, 8> ResultParts; 3828 SmallVector<Register, 8> OverflowParts; 3829 for (int I = 0; I != NumOps; ++I) { 3830 Register Operand1 = UnmergeLHS->getOperand(I).getReg(); 3831 Register Operand2 = UnmergeRHS->getOperand(I).getReg(); 3832 auto PartMul = MIRBuilder.buildInstr(MI.getOpcode(), {ResultTy, OverflowTy}, 3833 {Operand1, Operand2}); 3834 ResultParts.push_back(PartMul->getOperand(0).getReg()); 3835 OverflowParts.push_back(PartMul->getOperand(1).getReg()); 3836 } 3837 3838 LLT ResultLCMTy = buildLCMMergePieces(SrcTy, NarrowTy, GCDTy, ResultParts); 3839 LLT OverflowLCMTy = 3840 LLT::scalarOrVector(ResultLCMTy.getElementCount(), OverflowElementTy); 3841 3842 // Recombine the pieces to the original result and overflow registers. 3843 buildWidenedRemergeToDst(Result, ResultLCMTy, ResultParts); 3844 buildWidenedRemergeToDst(Overflow, OverflowLCMTy, OverflowParts); 3845 MI.eraseFromParent(); 3846 return Legalized; 3847 } 3848 3849 // Handle FewerElementsVector a G_BUILD_VECTOR or G_CONCAT_VECTORS that produces 3850 // a vector 3851 // 3852 // Create a G_BUILD_VECTOR or G_CONCAT_VECTORS of NarrowTy pieces, padding with 3853 // undef as necessary. 3854 // 3855 // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2 3856 // -> <2 x s16> 3857 // 3858 // %4:_(s16) = G_IMPLICIT_DEF 3859 // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1 3860 // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4 3861 // %7:_(<2 x s16>) = G_IMPLICIT_DEF 3862 // %8:_(<6 x s16>) = G_CONCAT_VECTORS %5, %6, %7 3863 // %3:_(<3 x s16>), %8:_(<3 x s16>) = G_UNMERGE_VALUES %8 3864 LegalizerHelper::LegalizeResult 3865 LegalizerHelper::fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx, 3866 LLT NarrowTy) { 3867 Register DstReg = MI.getOperand(0).getReg(); 3868 LLT DstTy = MRI.getType(DstReg); 3869 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 3870 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 3871 3872 // Break into a common type 3873 SmallVector<Register, 16> Parts; 3874 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 3875 extractGCDType(Parts, GCDTy, MI.getOperand(I).getReg()); 3876 3877 // Build the requested new merge, padding with undef. 3878 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, 3879 TargetOpcode::G_ANYEXT); 3880 3881 // Pack into the original result register. 3882 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3883 3884 MI.eraseFromParent(); 3885 return Legalized; 3886 } 3887 3888 LegalizerHelper::LegalizeResult 3889 LegalizerHelper::fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI, 3890 unsigned TypeIdx, 3891 LLT NarrowVecTy) { 3892 Register DstReg = MI.getOperand(0).getReg(); 3893 Register SrcVec = MI.getOperand(1).getReg(); 3894 Register InsertVal; 3895 bool IsInsert = MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT; 3896 3897 assert((IsInsert ? TypeIdx == 0 : TypeIdx == 1) && "not a vector type index"); 3898 if (IsInsert) 3899 InsertVal = MI.getOperand(2).getReg(); 3900 3901 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 3902 3903 // TODO: Handle total scalarization case. 3904 if (!NarrowVecTy.isVector()) 3905 return UnableToLegalize; 3906 3907 LLT VecTy = MRI.getType(SrcVec); 3908 3909 // If the index is a constant, we can really break this down as you would 3910 // expect, and index into the target size pieces. 3911 int64_t IdxVal; 3912 auto MaybeCst = 3913 getConstantVRegValWithLookThrough(Idx, MRI, /*LookThroughInstrs*/ true, 3914 /*HandleFConstants*/ false); 3915 if (MaybeCst) { 3916 IdxVal = MaybeCst->Value.getSExtValue(); 3917 // Avoid out of bounds indexing the pieces. 3918 if (IdxVal >= VecTy.getNumElements()) { 3919 MIRBuilder.buildUndef(DstReg); 3920 MI.eraseFromParent(); 3921 return Legalized; 3922 } 3923 3924 SmallVector<Register, 8> VecParts; 3925 LLT GCDTy = extractGCDType(VecParts, VecTy, NarrowVecTy, SrcVec); 3926 3927 // Build a sequence of NarrowTy pieces in VecParts for this operand. 3928 LLT LCMTy = buildLCMMergePieces(VecTy, NarrowVecTy, GCDTy, VecParts, 3929 TargetOpcode::G_ANYEXT); 3930 3931 unsigned NewNumElts = NarrowVecTy.getNumElements(); 3932 3933 LLT IdxTy = MRI.getType(Idx); 3934 int64_t PartIdx = IdxVal / NewNumElts; 3935 auto NewIdx = 3936 MIRBuilder.buildConstant(IdxTy, IdxVal - NewNumElts * PartIdx); 3937 3938 if (IsInsert) { 3939 LLT PartTy = MRI.getType(VecParts[PartIdx]); 3940 3941 // Use the adjusted index to insert into one of the subvectors. 3942 auto InsertPart = MIRBuilder.buildInsertVectorElement( 3943 PartTy, VecParts[PartIdx], InsertVal, NewIdx); 3944 VecParts[PartIdx] = InsertPart.getReg(0); 3945 3946 // Recombine the inserted subvector with the others to reform the result 3947 // vector. 3948 buildWidenedRemergeToDst(DstReg, LCMTy, VecParts); 3949 } else { 3950 MIRBuilder.buildExtractVectorElement(DstReg, VecParts[PartIdx], NewIdx); 3951 } 3952 3953 MI.eraseFromParent(); 3954 return Legalized; 3955 } 3956 3957 // With a variable index, we can't perform the operation in a smaller type, so 3958 // we're forced to expand this. 3959 // 3960 // TODO: We could emit a chain of compare/select to figure out which piece to 3961 // index. 3962 return lowerExtractInsertVectorElt(MI); 3963 } 3964 3965 LegalizerHelper::LegalizeResult 3966 LegalizerHelper::reduceLoadStoreWidth(GLoadStore &LdStMI, unsigned TypeIdx, 3967 LLT NarrowTy) { 3968 // FIXME: Don't know how to handle secondary types yet. 3969 if (TypeIdx != 0) 3970 return UnableToLegalize; 3971 3972 // This implementation doesn't work for atomics. Give up instead of doing 3973 // something invalid. 3974 if (LdStMI.isAtomic()) 3975 return UnableToLegalize; 3976 3977 bool IsLoad = isa<GLoad>(LdStMI); 3978 Register ValReg = LdStMI.getReg(0); 3979 Register AddrReg = LdStMI.getPointerReg(); 3980 LLT ValTy = MRI.getType(ValReg); 3981 3982 // FIXME: Do we need a distinct NarrowMemory legalize action? 3983 if (ValTy.getSizeInBits() != 8 * LdStMI.getMemSize()) { 3984 LLVM_DEBUG(dbgs() << "Can't narrow extload/truncstore\n"); 3985 return UnableToLegalize; 3986 } 3987 3988 int NumParts = -1; 3989 int NumLeftover = -1; 3990 LLT LeftoverTy; 3991 SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs; 3992 if (IsLoad) { 3993 std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy); 3994 } else { 3995 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, 3996 NarrowLeftoverRegs)) { 3997 NumParts = NarrowRegs.size(); 3998 NumLeftover = NarrowLeftoverRegs.size(); 3999 } 4000 } 4001 4002 if (NumParts == -1) 4003 return UnableToLegalize; 4004 4005 LLT PtrTy = MRI.getType(AddrReg); 4006 const LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits()); 4007 4008 unsigned TotalSize = ValTy.getSizeInBits(); 4009 4010 // Split the load/store into PartTy sized pieces starting at Offset. If this 4011 // is a load, return the new registers in ValRegs. For a store, each elements 4012 // of ValRegs should be PartTy. Returns the next offset that needs to be 4013 // handled. 4014 auto MMO = LdStMI.getMMO(); 4015 auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs, 4016 unsigned Offset) -> unsigned { 4017 MachineFunction &MF = MIRBuilder.getMF(); 4018 unsigned PartSize = PartTy.getSizeInBits(); 4019 for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize; 4020 Offset += PartSize, ++Idx) { 4021 unsigned ByteOffset = Offset / 8; 4022 Register NewAddrReg; 4023 4024 MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset); 4025 4026 MachineMemOperand *NewMMO = 4027 MF.getMachineMemOperand(&MMO, ByteOffset, PartTy); 4028 4029 if (IsLoad) { 4030 Register Dst = MRI.createGenericVirtualRegister(PartTy); 4031 ValRegs.push_back(Dst); 4032 MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO); 4033 } else { 4034 MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO); 4035 } 4036 } 4037 4038 return Offset; 4039 }; 4040 4041 unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0); 4042 4043 // Handle the rest of the register if this isn't an even type breakdown. 4044 if (LeftoverTy.isValid()) 4045 splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset); 4046 4047 if (IsLoad) { 4048 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, 4049 LeftoverTy, NarrowLeftoverRegs); 4050 } 4051 4052 LdStMI.eraseFromParent(); 4053 return Legalized; 4054 } 4055 4056 LegalizerHelper::LegalizeResult 4057 LegalizerHelper::reduceOperationWidth(MachineInstr &MI, unsigned int TypeIdx, 4058 LLT NarrowTy) { 4059 assert(TypeIdx == 0 && "only one type index expected"); 4060 4061 const unsigned Opc = MI.getOpcode(); 4062 const int NumDefOps = MI.getNumExplicitDefs(); 4063 const int NumSrcOps = MI.getNumOperands() - NumDefOps; 4064 const unsigned Flags = MI.getFlags(); 4065 const unsigned NarrowSize = NarrowTy.getSizeInBits(); 4066 const LLT NarrowScalarTy = LLT::scalar(NarrowSize); 4067 4068 assert(MI.getNumOperands() <= 4 && "expected instruction with either 1 " 4069 "result and 1-3 sources or 2 results and " 4070 "1-2 sources"); 4071 4072 SmallVector<Register, 2> DstRegs; 4073 for (int I = 0; I < NumDefOps; ++I) 4074 DstRegs.push_back(MI.getOperand(I).getReg()); 4075 4076 // First of all check whether we are narrowing (changing the element type) 4077 // or reducing the vector elements 4078 const LLT DstTy = MRI.getType(DstRegs[0]); 4079 const bool IsNarrow = NarrowTy.getScalarType() != DstTy.getScalarType(); 4080 4081 SmallVector<Register, 8> ExtractedRegs[3]; 4082 SmallVector<Register, 8> Parts; 4083 4084 // Break down all the sources into NarrowTy pieces we can operate on. This may 4085 // involve creating merges to a wider type, padded with undef. 4086 for (int I = 0; I != NumSrcOps; ++I) { 4087 Register SrcReg = MI.getOperand(I + NumDefOps).getReg(); 4088 LLT SrcTy = MRI.getType(SrcReg); 4089 4090 // The type to narrow SrcReg to. For narrowing, this is a smaller scalar. 4091 // For fewerElements, this is a smaller vector with the same element type. 4092 LLT OpNarrowTy; 4093 if (IsNarrow) { 4094 OpNarrowTy = NarrowScalarTy; 4095 4096 // In case of narrowing, we need to cast vectors to scalars for this to 4097 // work properly 4098 // FIXME: Can we do without the bitcast here if we're narrowing? 4099 if (SrcTy.isVector()) { 4100 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 4101 SrcReg = MIRBuilder.buildBitcast(SrcTy, SrcReg).getReg(0); 4102 } 4103 } else { 4104 auto NarrowEC = NarrowTy.isVector() ? NarrowTy.getElementCount() 4105 : ElementCount::getFixed(1); 4106 OpNarrowTy = LLT::scalarOrVector(NarrowEC, SrcTy.getScalarType()); 4107 } 4108 4109 LLT GCDTy = extractGCDType(ExtractedRegs[I], SrcTy, OpNarrowTy, SrcReg); 4110 4111 // Build a sequence of NarrowTy pieces in ExtractedRegs for this operand. 4112 buildLCMMergePieces(SrcTy, OpNarrowTy, GCDTy, ExtractedRegs[I], 4113 TargetOpcode::G_ANYEXT); 4114 } 4115 4116 SmallVector<Register, 8> ResultRegs[2]; 4117 4118 // Input operands for each sub-instruction. 4119 SmallVector<SrcOp, 4> InputRegs(NumSrcOps, Register()); 4120 4121 int NumParts = ExtractedRegs[0].size(); 4122 const unsigned DstSize = DstTy.getSizeInBits(); 4123 const LLT DstScalarTy = LLT::scalar(DstSize); 4124 4125 // Narrowing needs to use scalar types 4126 LLT DstLCMTy, NarrowDstTy; 4127 if (IsNarrow) { 4128 DstLCMTy = getLCMType(DstScalarTy, NarrowScalarTy); 4129 NarrowDstTy = NarrowScalarTy; 4130 } else { 4131 DstLCMTy = getLCMType(DstTy, NarrowTy); 4132 NarrowDstTy = NarrowTy; 4133 } 4134 4135 // We widened the source registers to satisfy merge/unmerge size 4136 // constraints. We'll have some extra fully undef parts. 4137 const int NumRealParts = (DstSize + NarrowSize - 1) / NarrowSize; 4138 4139 for (int I = 0; I != NumRealParts; ++I) { 4140 // Emit this instruction on each of the split pieces. 4141 for (int J = 0; J != NumSrcOps; ++J) 4142 InputRegs[J] = ExtractedRegs[J][I]; 4143 4144 MachineInstrBuilder Inst; 4145 if (NumDefOps == 1) 4146 Inst = MIRBuilder.buildInstr(Opc, {NarrowDstTy}, InputRegs, Flags); 4147 else 4148 Inst = MIRBuilder.buildInstr(Opc, {NarrowDstTy, NarrowDstTy}, InputRegs, 4149 Flags); 4150 4151 for (int J = 0; J != NumDefOps; ++J) 4152 ResultRegs[J].push_back(Inst.getReg(J)); 4153 } 4154 4155 // Fill out the widened result with undef instead of creating instructions 4156 // with undef inputs. 4157 int NumUndefParts = NumParts - NumRealParts; 4158 if (NumUndefParts != 0) { 4159 Register Undef = MIRBuilder.buildUndef(NarrowDstTy).getReg(0); 4160 for (int I = 0; I != NumDefOps; ++I) 4161 ResultRegs[I].append(NumUndefParts, Undef); 4162 } 4163 4164 // Extract the possibly padded result. Use a scratch register if we need to do 4165 // a final bitcast, otherwise use the original result register. 4166 Register MergeDstReg; 4167 for (int I = 0; I != NumDefOps; ++I) { 4168 if (IsNarrow && DstTy.isVector()) 4169 MergeDstReg = MRI.createGenericVirtualRegister(DstScalarTy); 4170 else 4171 MergeDstReg = DstRegs[I]; 4172 4173 buildWidenedRemergeToDst(MergeDstReg, DstLCMTy, ResultRegs[I]); 4174 4175 // Recast to vector if we narrowed a vector 4176 if (IsNarrow && DstTy.isVector()) 4177 MIRBuilder.buildBitcast(DstRegs[I], MergeDstReg); 4178 } 4179 4180 MI.eraseFromParent(); 4181 return Legalized; 4182 } 4183 4184 LegalizerHelper::LegalizeResult 4185 LegalizerHelper::fewerElementsVectorSextInReg(MachineInstr &MI, unsigned TypeIdx, 4186 LLT NarrowTy) { 4187 Register DstReg = MI.getOperand(0).getReg(); 4188 Register SrcReg = MI.getOperand(1).getReg(); 4189 int64_t Imm = MI.getOperand(2).getImm(); 4190 4191 LLT DstTy = MRI.getType(DstReg); 4192 4193 SmallVector<Register, 8> Parts; 4194 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 4195 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts); 4196 4197 for (Register &R : Parts) 4198 R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0); 4199 4200 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 4201 4202 MI.eraseFromParent(); 4203 return Legalized; 4204 } 4205 4206 LegalizerHelper::LegalizeResult 4207 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, 4208 LLT NarrowTy) { 4209 using namespace TargetOpcode; 4210 4211 switch (MI.getOpcode()) { 4212 case G_IMPLICIT_DEF: 4213 return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy); 4214 case G_TRUNC: 4215 case G_AND: 4216 case G_OR: 4217 case G_XOR: 4218 case G_ADD: 4219 case G_SUB: 4220 case G_MUL: 4221 case G_PTR_ADD: 4222 case G_SMULH: 4223 case G_UMULH: 4224 case G_FADD: 4225 case G_FMUL: 4226 case G_FSUB: 4227 case G_FNEG: 4228 case G_FABS: 4229 case G_FCANONICALIZE: 4230 case G_FDIV: 4231 case G_FREM: 4232 case G_FMA: 4233 case G_FMAD: 4234 case G_FPOW: 4235 case G_FEXP: 4236 case G_FEXP2: 4237 case G_FLOG: 4238 case G_FLOG2: 4239 case G_FLOG10: 4240 case G_FNEARBYINT: 4241 case G_FCEIL: 4242 case G_FFLOOR: 4243 case G_FRINT: 4244 case G_INTRINSIC_ROUND: 4245 case G_INTRINSIC_ROUNDEVEN: 4246 case G_INTRINSIC_TRUNC: 4247 case G_FCOS: 4248 case G_FSIN: 4249 case G_FSQRT: 4250 case G_BSWAP: 4251 case G_BITREVERSE: 4252 case G_SDIV: 4253 case G_UDIV: 4254 case G_SREM: 4255 case G_UREM: 4256 case G_SDIVREM: 4257 case G_UDIVREM: 4258 case G_SMIN: 4259 case G_SMAX: 4260 case G_UMIN: 4261 case G_UMAX: 4262 case G_ABS: 4263 case G_FMINNUM: 4264 case G_FMAXNUM: 4265 case G_FMINNUM_IEEE: 4266 case G_FMAXNUM_IEEE: 4267 case G_FMINIMUM: 4268 case G_FMAXIMUM: 4269 case G_FSHL: 4270 case G_FSHR: 4271 case G_FREEZE: 4272 case G_SADDSAT: 4273 case G_SSUBSAT: 4274 case G_UADDSAT: 4275 case G_USUBSAT: 4276 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 4277 case G_UMULO: 4278 case G_SMULO: 4279 return fewerElementsVectorMulo(MI, TypeIdx, NarrowTy); 4280 case G_SHL: 4281 case G_LSHR: 4282 case G_ASHR: 4283 case G_SSHLSAT: 4284 case G_USHLSAT: 4285 case G_CTLZ: 4286 case G_CTLZ_ZERO_UNDEF: 4287 case G_CTTZ: 4288 case G_CTTZ_ZERO_UNDEF: 4289 case G_CTPOP: 4290 case G_FCOPYSIGN: 4291 return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy); 4292 case G_ZEXT: 4293 case G_SEXT: 4294 case G_ANYEXT: 4295 case G_FPEXT: 4296 case G_FPTRUNC: 4297 case G_SITOFP: 4298 case G_UITOFP: 4299 case G_FPTOSI: 4300 case G_FPTOUI: 4301 case G_INTTOPTR: 4302 case G_PTRTOINT: 4303 case G_ADDRSPACE_CAST: 4304 return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy); 4305 case G_ICMP: 4306 case G_FCMP: 4307 return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy); 4308 case G_SELECT: 4309 return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy); 4310 case G_PHI: 4311 return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy); 4312 case G_UNMERGE_VALUES: 4313 return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy); 4314 case G_BUILD_VECTOR: 4315 assert(TypeIdx == 0 && "not a vector type index"); 4316 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4317 case G_CONCAT_VECTORS: 4318 if (TypeIdx != 1) // TODO: This probably does work as expected already. 4319 return UnableToLegalize; 4320 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4321 case G_EXTRACT_VECTOR_ELT: 4322 case G_INSERT_VECTOR_ELT: 4323 return fewerElementsVectorExtractInsertVectorElt(MI, TypeIdx, NarrowTy); 4324 case G_LOAD: 4325 case G_STORE: 4326 return reduceLoadStoreWidth(cast<GLoadStore>(MI), TypeIdx, NarrowTy); 4327 case G_SEXT_INREG: 4328 return fewerElementsVectorSextInReg(MI, TypeIdx, NarrowTy); 4329 GISEL_VECREDUCE_CASES_NONSEQ 4330 return fewerElementsVectorReductions(MI, TypeIdx, NarrowTy); 4331 case G_SHUFFLE_VECTOR: 4332 return fewerElementsVectorShuffle(MI, TypeIdx, NarrowTy); 4333 default: 4334 return UnableToLegalize; 4335 } 4336 } 4337 4338 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle( 4339 MachineInstr &MI, unsigned int TypeIdx, LLT NarrowTy) { 4340 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR); 4341 if (TypeIdx != 0) 4342 return UnableToLegalize; 4343 4344 Register DstReg = MI.getOperand(0).getReg(); 4345 Register Src1Reg = MI.getOperand(1).getReg(); 4346 Register Src2Reg = MI.getOperand(2).getReg(); 4347 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 4348 LLT DstTy = MRI.getType(DstReg); 4349 LLT Src1Ty = MRI.getType(Src1Reg); 4350 LLT Src2Ty = MRI.getType(Src2Reg); 4351 // The shuffle should be canonicalized by now. 4352 if (DstTy != Src1Ty) 4353 return UnableToLegalize; 4354 if (DstTy != Src2Ty) 4355 return UnableToLegalize; 4356 4357 if (!isPowerOf2_32(DstTy.getNumElements())) 4358 return UnableToLegalize; 4359 4360 // We only support splitting a shuffle into 2, so adjust NarrowTy accordingly. 4361 // Further legalization attempts will be needed to do split further. 4362 NarrowTy = 4363 DstTy.changeElementCount(DstTy.getElementCount().divideCoefficientBy(2)); 4364 unsigned NewElts = NarrowTy.getNumElements(); 4365 4366 SmallVector<Register> SplitSrc1Regs, SplitSrc2Regs; 4367 extractParts(Src1Reg, NarrowTy, 2, SplitSrc1Regs); 4368 extractParts(Src2Reg, NarrowTy, 2, SplitSrc2Regs); 4369 Register Inputs[4] = {SplitSrc1Regs[0], SplitSrc1Regs[1], SplitSrc2Regs[0], 4370 SplitSrc2Regs[1]}; 4371 4372 Register Hi, Lo; 4373 4374 // If Lo or Hi uses elements from at most two of the four input vectors, then 4375 // express it as a vector shuffle of those two inputs. Otherwise extract the 4376 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 4377 SmallVector<int, 16> Ops; 4378 for (unsigned High = 0; High < 2; ++High) { 4379 Register &Output = High ? Hi : Lo; 4380 4381 // Build a shuffle mask for the output, discovering on the fly which 4382 // input vectors to use as shuffle operands (recorded in InputUsed). 4383 // If building a suitable shuffle vector proves too hard, then bail 4384 // out with useBuildVector set. 4385 unsigned InputUsed[2] = {-1U, -1U}; // Not yet discovered. 4386 unsigned FirstMaskIdx = High * NewElts; 4387 bool UseBuildVector = false; 4388 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 4389 // The mask element. This indexes into the input. 4390 int Idx = Mask[FirstMaskIdx + MaskOffset]; 4391 4392 // The input vector this mask element indexes into. 4393 unsigned Input = (unsigned)Idx / NewElts; 4394 4395 if (Input >= array_lengthof(Inputs)) { 4396 // The mask element does not index into any input vector. 4397 Ops.push_back(-1); 4398 continue; 4399 } 4400 4401 // Turn the index into an offset from the start of the input vector. 4402 Idx -= Input * NewElts; 4403 4404 // Find or create a shuffle vector operand to hold this input. 4405 unsigned OpNo; 4406 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 4407 if (InputUsed[OpNo] == Input) { 4408 // This input vector is already an operand. 4409 break; 4410 } else if (InputUsed[OpNo] == -1U) { 4411 // Create a new operand for this input vector. 4412 InputUsed[OpNo] = Input; 4413 break; 4414 } 4415 } 4416 4417 if (OpNo >= array_lengthof(InputUsed)) { 4418 // More than two input vectors used! Give up on trying to create a 4419 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 4420 UseBuildVector = true; 4421 break; 4422 } 4423 4424 // Add the mask index for the new shuffle vector. 4425 Ops.push_back(Idx + OpNo * NewElts); 4426 } 4427 4428 if (UseBuildVector) { 4429 LLT EltTy = NarrowTy.getElementType(); 4430 SmallVector<Register, 16> SVOps; 4431 4432 // Extract the input elements by hand. 4433 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 4434 // The mask element. This indexes into the input. 4435 int Idx = Mask[FirstMaskIdx + MaskOffset]; 4436 4437 // The input vector this mask element indexes into. 4438 unsigned Input = (unsigned)Idx / NewElts; 4439 4440 if (Input >= array_lengthof(Inputs)) { 4441 // The mask element is "undef" or indexes off the end of the input. 4442 SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0)); 4443 continue; 4444 } 4445 4446 // Turn the index into an offset from the start of the input vector. 4447 Idx -= Input * NewElts; 4448 4449 // Extract the vector element by hand. 4450 SVOps.push_back(MIRBuilder 4451 .buildExtractVectorElement( 4452 EltTy, Inputs[Input], 4453 MIRBuilder.buildConstant(LLT::scalar(32), Idx)) 4454 .getReg(0)); 4455 } 4456 4457 // Construct the Lo/Hi output using a G_BUILD_VECTOR. 4458 Output = MIRBuilder.buildBuildVector(NarrowTy, SVOps).getReg(0); 4459 } else if (InputUsed[0] == -1U) { 4460 // No input vectors were used! The result is undefined. 4461 Output = MIRBuilder.buildUndef(NarrowTy).getReg(0); 4462 } else { 4463 Register Op0 = Inputs[InputUsed[0]]; 4464 // If only one input was used, use an undefined vector for the other. 4465 Register Op1 = InputUsed[1] == -1U 4466 ? MIRBuilder.buildUndef(NarrowTy).getReg(0) 4467 : Inputs[InputUsed[1]]; 4468 // At least one input vector was used. Create a new shuffle vector. 4469 Output = MIRBuilder.buildShuffleVector(NarrowTy, Op0, Op1, Ops).getReg(0); 4470 } 4471 4472 Ops.clear(); 4473 } 4474 4475 MIRBuilder.buildConcatVectors(DstReg, {Lo, Hi}); 4476 MI.eraseFromParent(); 4477 return Legalized; 4478 } 4479 4480 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorReductions( 4481 MachineInstr &MI, unsigned int TypeIdx, LLT NarrowTy) { 4482 unsigned Opc = MI.getOpcode(); 4483 assert(Opc != TargetOpcode::G_VECREDUCE_SEQ_FADD && 4484 Opc != TargetOpcode::G_VECREDUCE_SEQ_FMUL && 4485 "Sequential reductions not expected"); 4486 4487 if (TypeIdx != 1) 4488 return UnableToLegalize; 4489 4490 // The semantics of the normal non-sequential reductions allow us to freely 4491 // re-associate the operation. 4492 Register SrcReg = MI.getOperand(1).getReg(); 4493 LLT SrcTy = MRI.getType(SrcReg); 4494 Register DstReg = MI.getOperand(0).getReg(); 4495 LLT DstTy = MRI.getType(DstReg); 4496 4497 if (SrcTy.getNumElements() % NarrowTy.getNumElements() != 0) 4498 return UnableToLegalize; 4499 4500 SmallVector<Register> SplitSrcs; 4501 const unsigned NumParts = SrcTy.getNumElements() / NarrowTy.getNumElements(); 4502 extractParts(SrcReg, NarrowTy, NumParts, SplitSrcs); 4503 SmallVector<Register> PartialReductions; 4504 for (unsigned Part = 0; Part < NumParts; ++Part) { 4505 PartialReductions.push_back( 4506 MIRBuilder.buildInstr(Opc, {DstTy}, {SplitSrcs[Part]}).getReg(0)); 4507 } 4508 4509 unsigned ScalarOpc; 4510 switch (Opc) { 4511 case TargetOpcode::G_VECREDUCE_FADD: 4512 ScalarOpc = TargetOpcode::G_FADD; 4513 break; 4514 case TargetOpcode::G_VECREDUCE_FMUL: 4515 ScalarOpc = TargetOpcode::G_FMUL; 4516 break; 4517 case TargetOpcode::G_VECREDUCE_FMAX: 4518 ScalarOpc = TargetOpcode::G_FMAXNUM; 4519 break; 4520 case TargetOpcode::G_VECREDUCE_FMIN: 4521 ScalarOpc = TargetOpcode::G_FMINNUM; 4522 break; 4523 case TargetOpcode::G_VECREDUCE_ADD: 4524 ScalarOpc = TargetOpcode::G_ADD; 4525 break; 4526 case TargetOpcode::G_VECREDUCE_MUL: 4527 ScalarOpc = TargetOpcode::G_MUL; 4528 break; 4529 case TargetOpcode::G_VECREDUCE_AND: 4530 ScalarOpc = TargetOpcode::G_AND; 4531 break; 4532 case TargetOpcode::G_VECREDUCE_OR: 4533 ScalarOpc = TargetOpcode::G_OR; 4534 break; 4535 case TargetOpcode::G_VECREDUCE_XOR: 4536 ScalarOpc = TargetOpcode::G_XOR; 4537 break; 4538 case TargetOpcode::G_VECREDUCE_SMAX: 4539 ScalarOpc = TargetOpcode::G_SMAX; 4540 break; 4541 case TargetOpcode::G_VECREDUCE_SMIN: 4542 ScalarOpc = TargetOpcode::G_SMIN; 4543 break; 4544 case TargetOpcode::G_VECREDUCE_UMAX: 4545 ScalarOpc = TargetOpcode::G_UMAX; 4546 break; 4547 case TargetOpcode::G_VECREDUCE_UMIN: 4548 ScalarOpc = TargetOpcode::G_UMIN; 4549 break; 4550 default: 4551 LLVM_DEBUG(dbgs() << "Can't legalize: unknown reduction kind.\n"); 4552 return UnableToLegalize; 4553 } 4554 4555 // If the types involved are powers of 2, we can generate intermediate vector 4556 // ops, before generating a final reduction operation. 4557 if (isPowerOf2_32(SrcTy.getNumElements()) && 4558 isPowerOf2_32(NarrowTy.getNumElements())) { 4559 return tryNarrowPow2Reduction(MI, SrcReg, SrcTy, NarrowTy, ScalarOpc); 4560 } 4561 4562 Register Acc = PartialReductions[0]; 4563 for (unsigned Part = 1; Part < NumParts; ++Part) { 4564 if (Part == NumParts - 1) { 4565 MIRBuilder.buildInstr(ScalarOpc, {DstReg}, 4566 {Acc, PartialReductions[Part]}); 4567 } else { 4568 Acc = MIRBuilder 4569 .buildInstr(ScalarOpc, {DstTy}, {Acc, PartialReductions[Part]}) 4570 .getReg(0); 4571 } 4572 } 4573 MI.eraseFromParent(); 4574 return Legalized; 4575 } 4576 4577 LegalizerHelper::LegalizeResult 4578 LegalizerHelper::tryNarrowPow2Reduction(MachineInstr &MI, Register SrcReg, 4579 LLT SrcTy, LLT NarrowTy, 4580 unsigned ScalarOpc) { 4581 SmallVector<Register> SplitSrcs; 4582 // Split the sources into NarrowTy size pieces. 4583 extractParts(SrcReg, NarrowTy, 4584 SrcTy.getNumElements() / NarrowTy.getNumElements(), SplitSrcs); 4585 // We're going to do a tree reduction using vector operations until we have 4586 // one NarrowTy size value left. 4587 while (SplitSrcs.size() > 1) { 4588 SmallVector<Register> PartialRdxs; 4589 for (unsigned Idx = 0; Idx < SplitSrcs.size()-1; Idx += 2) { 4590 Register LHS = SplitSrcs[Idx]; 4591 Register RHS = SplitSrcs[Idx + 1]; 4592 // Create the intermediate vector op. 4593 Register Res = 4594 MIRBuilder.buildInstr(ScalarOpc, {NarrowTy}, {LHS, RHS}).getReg(0); 4595 PartialRdxs.push_back(Res); 4596 } 4597 SplitSrcs = std::move(PartialRdxs); 4598 } 4599 // Finally generate the requested NarrowTy based reduction. 4600 Observer.changingInstr(MI); 4601 MI.getOperand(1).setReg(SplitSrcs[0]); 4602 Observer.changedInstr(MI); 4603 return Legalized; 4604 } 4605 4606 LegalizerHelper::LegalizeResult 4607 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt, 4608 const LLT HalfTy, const LLT AmtTy) { 4609 4610 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4611 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4612 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4613 4614 if (Amt.isNullValue()) { 4615 MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH}); 4616 MI.eraseFromParent(); 4617 return Legalized; 4618 } 4619 4620 LLT NVT = HalfTy; 4621 unsigned NVTBits = HalfTy.getSizeInBits(); 4622 unsigned VTBits = 2 * NVTBits; 4623 4624 SrcOp Lo(Register(0)), Hi(Register(0)); 4625 if (MI.getOpcode() == TargetOpcode::G_SHL) { 4626 if (Amt.ugt(VTBits)) { 4627 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4628 } else if (Amt.ugt(NVTBits)) { 4629 Lo = MIRBuilder.buildConstant(NVT, 0); 4630 Hi = MIRBuilder.buildShl(NVT, InL, 4631 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4632 } else if (Amt == NVTBits) { 4633 Lo = MIRBuilder.buildConstant(NVT, 0); 4634 Hi = InL; 4635 } else { 4636 Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt)); 4637 auto OrLHS = 4638 MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt)); 4639 auto OrRHS = MIRBuilder.buildLShr( 4640 NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4641 Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4642 } 4643 } else if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4644 if (Amt.ugt(VTBits)) { 4645 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4646 } else if (Amt.ugt(NVTBits)) { 4647 Lo = MIRBuilder.buildLShr(NVT, InH, 4648 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4649 Hi = MIRBuilder.buildConstant(NVT, 0); 4650 } else if (Amt == NVTBits) { 4651 Lo = InH; 4652 Hi = MIRBuilder.buildConstant(NVT, 0); 4653 } else { 4654 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4655 4656 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4657 auto OrRHS = MIRBuilder.buildShl( 4658 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4659 4660 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4661 Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst); 4662 } 4663 } else { 4664 if (Amt.ugt(VTBits)) { 4665 Hi = Lo = MIRBuilder.buildAShr( 4666 NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4667 } else if (Amt.ugt(NVTBits)) { 4668 Lo = MIRBuilder.buildAShr(NVT, InH, 4669 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4670 Hi = MIRBuilder.buildAShr(NVT, InH, 4671 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4672 } else if (Amt == NVTBits) { 4673 Lo = InH; 4674 Hi = MIRBuilder.buildAShr(NVT, InH, 4675 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4676 } else { 4677 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4678 4679 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4680 auto OrRHS = MIRBuilder.buildShl( 4681 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4682 4683 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4684 Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst); 4685 } 4686 } 4687 4688 MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi}); 4689 MI.eraseFromParent(); 4690 4691 return Legalized; 4692 } 4693 4694 // TODO: Optimize if constant shift amount. 4695 LegalizerHelper::LegalizeResult 4696 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, 4697 LLT RequestedTy) { 4698 if (TypeIdx == 1) { 4699 Observer.changingInstr(MI); 4700 narrowScalarSrc(MI, RequestedTy, 2); 4701 Observer.changedInstr(MI); 4702 return Legalized; 4703 } 4704 4705 Register DstReg = MI.getOperand(0).getReg(); 4706 LLT DstTy = MRI.getType(DstReg); 4707 if (DstTy.isVector()) 4708 return UnableToLegalize; 4709 4710 Register Amt = MI.getOperand(2).getReg(); 4711 LLT ShiftAmtTy = MRI.getType(Amt); 4712 const unsigned DstEltSize = DstTy.getScalarSizeInBits(); 4713 if (DstEltSize % 2 != 0) 4714 return UnableToLegalize; 4715 4716 // Ignore the input type. We can only go to exactly half the size of the 4717 // input. If that isn't small enough, the resulting pieces will be further 4718 // legalized. 4719 const unsigned NewBitSize = DstEltSize / 2; 4720 const LLT HalfTy = LLT::scalar(NewBitSize); 4721 const LLT CondTy = LLT::scalar(1); 4722 4723 if (const MachineInstr *KShiftAmt = 4724 getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) { 4725 return narrowScalarShiftByConstant( 4726 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy); 4727 } 4728 4729 // TODO: Expand with known bits. 4730 4731 // Handle the fully general expansion by an unknown amount. 4732 auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize); 4733 4734 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4735 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4736 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4737 4738 auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits); 4739 auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt); 4740 4741 auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0); 4742 auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits); 4743 auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero); 4744 4745 Register ResultRegs[2]; 4746 switch (MI.getOpcode()) { 4747 case TargetOpcode::G_SHL: { 4748 // Short: ShAmt < NewBitSize 4749 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); 4750 4751 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack); 4752 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt); 4753 auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4754 4755 // Long: ShAmt >= NewBitSize 4756 auto LoL = MIRBuilder.buildConstant(HalfTy, 0); // Lo part is zero. 4757 auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part. 4758 4759 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL); 4760 auto Hi = MIRBuilder.buildSelect( 4761 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL)); 4762 4763 ResultRegs[0] = Lo.getReg(0); 4764 ResultRegs[1] = Hi.getReg(0); 4765 break; 4766 } 4767 case TargetOpcode::G_LSHR: 4768 case TargetOpcode::G_ASHR: { 4769 // Short: ShAmt < NewBitSize 4770 auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt}); 4771 4772 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt); 4773 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack); 4774 auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4775 4776 // Long: ShAmt >= NewBitSize 4777 MachineInstrBuilder HiL; 4778 if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4779 HiL = MIRBuilder.buildConstant(HalfTy, 0); // Hi part is zero. 4780 } else { 4781 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1); 4782 HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt); // Sign of Hi part. 4783 } 4784 auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, 4785 {InH, AmtExcess}); // Lo from Hi part. 4786 4787 auto Lo = MIRBuilder.buildSelect( 4788 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL)); 4789 4790 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL); 4791 4792 ResultRegs[0] = Lo.getReg(0); 4793 ResultRegs[1] = Hi.getReg(0); 4794 break; 4795 } 4796 default: 4797 llvm_unreachable("not a shift"); 4798 } 4799 4800 MIRBuilder.buildMerge(DstReg, ResultRegs); 4801 MI.eraseFromParent(); 4802 return Legalized; 4803 } 4804 4805 LegalizerHelper::LegalizeResult 4806 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 4807 LLT MoreTy) { 4808 assert(TypeIdx == 0 && "Expecting only Idx 0"); 4809 4810 Observer.changingInstr(MI); 4811 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 4812 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 4813 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 4814 moreElementsVectorSrc(MI, MoreTy, I); 4815 } 4816 4817 MachineBasicBlock &MBB = *MI.getParent(); 4818 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 4819 moreElementsVectorDst(MI, MoreTy, 0); 4820 Observer.changedInstr(MI); 4821 return Legalized; 4822 } 4823 4824 LegalizerHelper::LegalizeResult 4825 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx, 4826 LLT MoreTy) { 4827 unsigned Opc = MI.getOpcode(); 4828 switch (Opc) { 4829 case TargetOpcode::G_IMPLICIT_DEF: 4830 case TargetOpcode::G_LOAD: { 4831 if (TypeIdx != 0) 4832 return UnableToLegalize; 4833 Observer.changingInstr(MI); 4834 moreElementsVectorDst(MI, MoreTy, 0); 4835 Observer.changedInstr(MI); 4836 return Legalized; 4837 } 4838 case TargetOpcode::G_STORE: 4839 if (TypeIdx != 0) 4840 return UnableToLegalize; 4841 Observer.changingInstr(MI); 4842 moreElementsVectorSrc(MI, MoreTy, 0); 4843 Observer.changedInstr(MI); 4844 return Legalized; 4845 case TargetOpcode::G_AND: 4846 case TargetOpcode::G_OR: 4847 case TargetOpcode::G_XOR: 4848 case TargetOpcode::G_SMIN: 4849 case TargetOpcode::G_SMAX: 4850 case TargetOpcode::G_UMIN: 4851 case TargetOpcode::G_UMAX: 4852 case TargetOpcode::G_FMINNUM: 4853 case TargetOpcode::G_FMAXNUM: 4854 case TargetOpcode::G_FMINNUM_IEEE: 4855 case TargetOpcode::G_FMAXNUM_IEEE: 4856 case TargetOpcode::G_FMINIMUM: 4857 case TargetOpcode::G_FMAXIMUM: { 4858 Observer.changingInstr(MI); 4859 moreElementsVectorSrc(MI, MoreTy, 1); 4860 moreElementsVectorSrc(MI, MoreTy, 2); 4861 moreElementsVectorDst(MI, MoreTy, 0); 4862 Observer.changedInstr(MI); 4863 return Legalized; 4864 } 4865 case TargetOpcode::G_EXTRACT: 4866 if (TypeIdx != 1) 4867 return UnableToLegalize; 4868 Observer.changingInstr(MI); 4869 moreElementsVectorSrc(MI, MoreTy, 1); 4870 Observer.changedInstr(MI); 4871 return Legalized; 4872 case TargetOpcode::G_INSERT: 4873 case TargetOpcode::G_FREEZE: 4874 if (TypeIdx != 0) 4875 return UnableToLegalize; 4876 Observer.changingInstr(MI); 4877 moreElementsVectorSrc(MI, MoreTy, 1); 4878 moreElementsVectorDst(MI, MoreTy, 0); 4879 Observer.changedInstr(MI); 4880 return Legalized; 4881 case TargetOpcode::G_SELECT: 4882 if (TypeIdx != 0) 4883 return UnableToLegalize; 4884 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) 4885 return UnableToLegalize; 4886 4887 Observer.changingInstr(MI); 4888 moreElementsVectorSrc(MI, MoreTy, 2); 4889 moreElementsVectorSrc(MI, MoreTy, 3); 4890 moreElementsVectorDst(MI, MoreTy, 0); 4891 Observer.changedInstr(MI); 4892 return Legalized; 4893 case TargetOpcode::G_UNMERGE_VALUES: { 4894 if (TypeIdx != 1) 4895 return UnableToLegalize; 4896 4897 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 4898 int NumDst = MI.getNumOperands() - 1; 4899 moreElementsVectorSrc(MI, MoreTy, NumDst); 4900 4901 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 4902 for (int I = 0; I != NumDst; ++I) 4903 MIB.addDef(MI.getOperand(I).getReg()); 4904 4905 int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits(); 4906 for (int I = NumDst; I != NewNumDst; ++I) 4907 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 4908 4909 MIB.addUse(MI.getOperand(NumDst).getReg()); 4910 MI.eraseFromParent(); 4911 return Legalized; 4912 } 4913 case TargetOpcode::G_PHI: 4914 return moreElementsVectorPhi(MI, TypeIdx, MoreTy); 4915 case TargetOpcode::G_SHUFFLE_VECTOR: 4916 return moreElementsVectorShuffle(MI, TypeIdx, MoreTy); 4917 default: 4918 return UnableToLegalize; 4919 } 4920 } 4921 4922 LegalizerHelper::LegalizeResult 4923 LegalizerHelper::moreElementsVectorShuffle(MachineInstr &MI, 4924 unsigned int TypeIdx, LLT MoreTy) { 4925 if (TypeIdx != 0) 4926 return UnableToLegalize; 4927 4928 Register DstReg = MI.getOperand(0).getReg(); 4929 Register Src1Reg = MI.getOperand(1).getReg(); 4930 Register Src2Reg = MI.getOperand(2).getReg(); 4931 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 4932 LLT DstTy = MRI.getType(DstReg); 4933 LLT Src1Ty = MRI.getType(Src1Reg); 4934 LLT Src2Ty = MRI.getType(Src2Reg); 4935 unsigned NumElts = DstTy.getNumElements(); 4936 unsigned WidenNumElts = MoreTy.getNumElements(); 4937 4938 // Expect a canonicalized shuffle. 4939 if (DstTy != Src1Ty || DstTy != Src2Ty) 4940 return UnableToLegalize; 4941 4942 moreElementsVectorSrc(MI, MoreTy, 1); 4943 moreElementsVectorSrc(MI, MoreTy, 2); 4944 4945 // Adjust mask based on new input vector length. 4946 SmallVector<int, 16> NewMask; 4947 for (unsigned I = 0; I != NumElts; ++I) { 4948 int Idx = Mask[I]; 4949 if (Idx < static_cast<int>(NumElts)) 4950 NewMask.push_back(Idx); 4951 else 4952 NewMask.push_back(Idx - NumElts + WidenNumElts); 4953 } 4954 for (unsigned I = NumElts; I != WidenNumElts; ++I) 4955 NewMask.push_back(-1); 4956 moreElementsVectorDst(MI, MoreTy, 0); 4957 MIRBuilder.setInstrAndDebugLoc(MI); 4958 MIRBuilder.buildShuffleVector(MI.getOperand(0).getReg(), 4959 MI.getOperand(1).getReg(), 4960 MI.getOperand(2).getReg(), NewMask); 4961 MI.eraseFromParent(); 4962 return Legalized; 4963 } 4964 4965 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs, 4966 ArrayRef<Register> Src1Regs, 4967 ArrayRef<Register> Src2Regs, 4968 LLT NarrowTy) { 4969 MachineIRBuilder &B = MIRBuilder; 4970 unsigned SrcParts = Src1Regs.size(); 4971 unsigned DstParts = DstRegs.size(); 4972 4973 unsigned DstIdx = 0; // Low bits of the result. 4974 Register FactorSum = 4975 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); 4976 DstRegs[DstIdx] = FactorSum; 4977 4978 unsigned CarrySumPrevDstIdx; 4979 SmallVector<Register, 4> Factors; 4980 4981 for (DstIdx = 1; DstIdx < DstParts; DstIdx++) { 4982 // Collect low parts of muls for DstIdx. 4983 for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1; 4984 i <= std::min(DstIdx, SrcParts - 1); ++i) { 4985 MachineInstrBuilder Mul = 4986 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); 4987 Factors.push_back(Mul.getReg(0)); 4988 } 4989 // Collect high parts of muls from previous DstIdx. 4990 for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts; 4991 i <= std::min(DstIdx - 1, SrcParts - 1); ++i) { 4992 MachineInstrBuilder Umulh = 4993 B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]); 4994 Factors.push_back(Umulh.getReg(0)); 4995 } 4996 // Add CarrySum from additions calculated for previous DstIdx. 4997 if (DstIdx != 1) { 4998 Factors.push_back(CarrySumPrevDstIdx); 4999 } 5000 5001 Register CarrySum; 5002 // Add all factors and accumulate all carries into CarrySum. 5003 if (DstIdx != DstParts - 1) { 5004 MachineInstrBuilder Uaddo = 5005 B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]); 5006 FactorSum = Uaddo.getReg(0); 5007 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0); 5008 for (unsigned i = 2; i < Factors.size(); ++i) { 5009 MachineInstrBuilder Uaddo = 5010 B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]); 5011 FactorSum = Uaddo.getReg(0); 5012 MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1)); 5013 CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0); 5014 } 5015 } else { 5016 // Since value for the next index is not calculated, neither is CarrySum. 5017 FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0); 5018 for (unsigned i = 2; i < Factors.size(); ++i) 5019 FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0); 5020 } 5021 5022 CarrySumPrevDstIdx = CarrySum; 5023 DstRegs[DstIdx] = FactorSum; 5024 Factors.clear(); 5025 } 5026 } 5027 5028 LegalizerHelper::LegalizeResult 5029 LegalizerHelper::narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx, 5030 LLT NarrowTy) { 5031 if (TypeIdx != 0) 5032 return UnableToLegalize; 5033 5034 Register DstReg = MI.getOperand(0).getReg(); 5035 LLT DstType = MRI.getType(DstReg); 5036 // FIXME: add support for vector types 5037 if (DstType.isVector()) 5038 return UnableToLegalize; 5039 5040 unsigned Opcode = MI.getOpcode(); 5041 unsigned OpO, OpE, OpF; 5042 switch (Opcode) { 5043 case TargetOpcode::G_SADDO: 5044 case TargetOpcode::G_SADDE: 5045 case TargetOpcode::G_UADDO: 5046 case TargetOpcode::G_UADDE: 5047 case TargetOpcode::G_ADD: 5048 OpO = TargetOpcode::G_UADDO; 5049 OpE = TargetOpcode::G_UADDE; 5050 OpF = TargetOpcode::G_UADDE; 5051 if (Opcode == TargetOpcode::G_SADDO || Opcode == TargetOpcode::G_SADDE) 5052 OpF = TargetOpcode::G_SADDE; 5053 break; 5054 case TargetOpcode::G_SSUBO: 5055 case TargetOpcode::G_SSUBE: 5056 case TargetOpcode::G_USUBO: 5057 case TargetOpcode::G_USUBE: 5058 case TargetOpcode::G_SUB: 5059 OpO = TargetOpcode::G_USUBO; 5060 OpE = TargetOpcode::G_USUBE; 5061 OpF = TargetOpcode::G_USUBE; 5062 if (Opcode == TargetOpcode::G_SSUBO || Opcode == TargetOpcode::G_SSUBE) 5063 OpF = TargetOpcode::G_SSUBE; 5064 break; 5065 default: 5066 llvm_unreachable("Unexpected add/sub opcode!"); 5067 } 5068 5069 // 1 for a plain add/sub, 2 if this is an operation with a carry-out. 5070 unsigned NumDefs = MI.getNumExplicitDefs(); 5071 Register Src1 = MI.getOperand(NumDefs).getReg(); 5072 Register Src2 = MI.getOperand(NumDefs + 1).getReg(); 5073 Register CarryDst, CarryIn; 5074 if (NumDefs == 2) 5075 CarryDst = MI.getOperand(1).getReg(); 5076 if (MI.getNumOperands() == NumDefs + 3) 5077 CarryIn = MI.getOperand(NumDefs + 2).getReg(); 5078 5079 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); 5080 LLT LeftoverTy, DummyTy; 5081 SmallVector<Register, 2> Src1Regs, Src2Regs, Src1Left, Src2Left, DstRegs; 5082 extractParts(Src1, RegTy, NarrowTy, LeftoverTy, Src1Regs, Src1Left); 5083 extractParts(Src2, RegTy, NarrowTy, DummyTy, Src2Regs, Src2Left); 5084 5085 int NarrowParts = Src1Regs.size(); 5086 for (int I = 0, E = Src1Left.size(); I != E; ++I) { 5087 Src1Regs.push_back(Src1Left[I]); 5088 Src2Regs.push_back(Src2Left[I]); 5089 } 5090 DstRegs.reserve(Src1Regs.size()); 5091 5092 for (int i = 0, e = Src1Regs.size(); i != e; ++i) { 5093 Register DstReg = 5094 MRI.createGenericVirtualRegister(MRI.getType(Src1Regs[i])); 5095 Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); 5096 // Forward the final carry-out to the destination register 5097 if (i == e - 1 && CarryDst) 5098 CarryOut = CarryDst; 5099 5100 if (!CarryIn) { 5101 MIRBuilder.buildInstr(OpO, {DstReg, CarryOut}, 5102 {Src1Regs[i], Src2Regs[i]}); 5103 } else if (i == e - 1) { 5104 MIRBuilder.buildInstr(OpF, {DstReg, CarryOut}, 5105 {Src1Regs[i], Src2Regs[i], CarryIn}); 5106 } else { 5107 MIRBuilder.buildInstr(OpE, {DstReg, CarryOut}, 5108 {Src1Regs[i], Src2Regs[i], CarryIn}); 5109 } 5110 5111 DstRegs.push_back(DstReg); 5112 CarryIn = CarryOut; 5113 } 5114 insertParts(MI.getOperand(0).getReg(), RegTy, NarrowTy, 5115 makeArrayRef(DstRegs).take_front(NarrowParts), LeftoverTy, 5116 makeArrayRef(DstRegs).drop_front(NarrowParts)); 5117 5118 MI.eraseFromParent(); 5119 return Legalized; 5120 } 5121 5122 LegalizerHelper::LegalizeResult 5123 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) { 5124 Register DstReg = MI.getOperand(0).getReg(); 5125 Register Src1 = MI.getOperand(1).getReg(); 5126 Register Src2 = MI.getOperand(2).getReg(); 5127 5128 LLT Ty = MRI.getType(DstReg); 5129 if (Ty.isVector()) 5130 return UnableToLegalize; 5131 5132 unsigned SrcSize = MRI.getType(Src1).getSizeInBits(); 5133 unsigned DstSize = Ty.getSizeInBits(); 5134 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5135 if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0) 5136 return UnableToLegalize; 5137 5138 unsigned NumDstParts = DstSize / NarrowSize; 5139 unsigned NumSrcParts = SrcSize / NarrowSize; 5140 bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH; 5141 unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1); 5142 5143 SmallVector<Register, 2> Src1Parts, Src2Parts; 5144 SmallVector<Register, 2> DstTmpRegs(DstTmpParts); 5145 extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts); 5146 extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts); 5147 multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy); 5148 5149 // Take only high half of registers if this is high mul. 5150 ArrayRef<Register> DstRegs( 5151 IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts); 5152 MIRBuilder.buildMerge(DstReg, DstRegs); 5153 MI.eraseFromParent(); 5154 return Legalized; 5155 } 5156 5157 LegalizerHelper::LegalizeResult 5158 LegalizerHelper::narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx, 5159 LLT NarrowTy) { 5160 if (TypeIdx != 0) 5161 return UnableToLegalize; 5162 5163 bool IsSigned = MI.getOpcode() == TargetOpcode::G_FPTOSI; 5164 5165 Register Src = MI.getOperand(1).getReg(); 5166 LLT SrcTy = MRI.getType(Src); 5167 5168 // If all finite floats fit into the narrowed integer type, we can just swap 5169 // out the result type. This is practically only useful for conversions from 5170 // half to at least 16-bits, so just handle the one case. 5171 if (SrcTy.getScalarType() != LLT::scalar(16) || 5172 NarrowTy.getScalarSizeInBits() < (IsSigned ? 17u : 16u)) 5173 return UnableToLegalize; 5174 5175 Observer.changingInstr(MI); 5176 narrowScalarDst(MI, NarrowTy, 0, 5177 IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT); 5178 Observer.changedInstr(MI); 5179 return Legalized; 5180 } 5181 5182 LegalizerHelper::LegalizeResult 5183 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, 5184 LLT NarrowTy) { 5185 if (TypeIdx != 1) 5186 return UnableToLegalize; 5187 5188 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 5189 5190 int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 5191 // FIXME: add support for when SizeOp1 isn't an exact multiple of 5192 // NarrowSize. 5193 if (SizeOp1 % NarrowSize != 0) 5194 return UnableToLegalize; 5195 int NumParts = SizeOp1 / NarrowSize; 5196 5197 SmallVector<Register, 2> SrcRegs, DstRegs; 5198 SmallVector<uint64_t, 2> Indexes; 5199 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 5200 5201 Register OpReg = MI.getOperand(0).getReg(); 5202 uint64_t OpStart = MI.getOperand(2).getImm(); 5203 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 5204 for (int i = 0; i < NumParts; ++i) { 5205 unsigned SrcStart = i * NarrowSize; 5206 5207 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) { 5208 // No part of the extract uses this subregister, ignore it. 5209 continue; 5210 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 5211 // The entire subregister is extracted, forward the value. 5212 DstRegs.push_back(SrcRegs[i]); 5213 continue; 5214 } 5215 5216 // OpSegStart is where this destination segment would start in OpReg if it 5217 // extended infinitely in both directions. 5218 int64_t ExtractOffset; 5219 uint64_t SegSize; 5220 if (OpStart < SrcStart) { 5221 ExtractOffset = 0; 5222 SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart); 5223 } else { 5224 ExtractOffset = OpStart - SrcStart; 5225 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize); 5226 } 5227 5228 Register SegReg = SrcRegs[i]; 5229 if (ExtractOffset != 0 || SegSize != NarrowSize) { 5230 // A genuine extract is needed. 5231 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 5232 MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset); 5233 } 5234 5235 DstRegs.push_back(SegReg); 5236 } 5237 5238 Register DstReg = MI.getOperand(0).getReg(); 5239 if (MRI.getType(DstReg).isVector()) 5240 MIRBuilder.buildBuildVector(DstReg, DstRegs); 5241 else if (DstRegs.size() > 1) 5242 MIRBuilder.buildMerge(DstReg, DstRegs); 5243 else 5244 MIRBuilder.buildCopy(DstReg, DstRegs[0]); 5245 MI.eraseFromParent(); 5246 return Legalized; 5247 } 5248 5249 LegalizerHelper::LegalizeResult 5250 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, 5251 LLT NarrowTy) { 5252 // FIXME: Don't know how to handle secondary types yet. 5253 if (TypeIdx != 0) 5254 return UnableToLegalize; 5255 5256 SmallVector<Register, 2> SrcRegs, LeftoverRegs, DstRegs; 5257 SmallVector<uint64_t, 2> Indexes; 5258 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); 5259 LLT LeftoverTy; 5260 extractParts(MI.getOperand(1).getReg(), RegTy, NarrowTy, LeftoverTy, SrcRegs, 5261 LeftoverRegs); 5262 5263 for (Register Reg : LeftoverRegs) 5264 SrcRegs.push_back(Reg); 5265 5266 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 5267 Register OpReg = MI.getOperand(2).getReg(); 5268 uint64_t OpStart = MI.getOperand(3).getImm(); 5269 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 5270 for (int I = 0, E = SrcRegs.size(); I != E; ++I) { 5271 unsigned DstStart = I * NarrowSize; 5272 5273 if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 5274 // The entire subregister is defined by this insert, forward the new 5275 // value. 5276 DstRegs.push_back(OpReg); 5277 continue; 5278 } 5279 5280 Register SrcReg = SrcRegs[I]; 5281 if (MRI.getType(SrcRegs[I]) == LeftoverTy) { 5282 // The leftover reg is smaller than NarrowTy, so we need to extend it. 5283 SrcReg = MRI.createGenericVirtualRegister(NarrowTy); 5284 MIRBuilder.buildAnyExt(SrcReg, SrcRegs[I]); 5285 } 5286 5287 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) { 5288 // No part of the insert affects this subregister, forward the original. 5289 DstRegs.push_back(SrcReg); 5290 continue; 5291 } 5292 5293 // OpSegStart is where this destination segment would start in OpReg if it 5294 // extended infinitely in both directions. 5295 int64_t ExtractOffset, InsertOffset; 5296 uint64_t SegSize; 5297 if (OpStart < DstStart) { 5298 InsertOffset = 0; 5299 ExtractOffset = DstStart - OpStart; 5300 SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart); 5301 } else { 5302 InsertOffset = OpStart - DstStart; 5303 ExtractOffset = 0; 5304 SegSize = 5305 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart); 5306 } 5307 5308 Register SegReg = OpReg; 5309 if (ExtractOffset != 0 || SegSize != OpSize) { 5310 // A genuine extract is needed. 5311 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 5312 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); 5313 } 5314 5315 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 5316 MIRBuilder.buildInsert(DstReg, SrcReg, SegReg, InsertOffset); 5317 DstRegs.push_back(DstReg); 5318 } 5319 5320 uint64_t WideSize = DstRegs.size() * NarrowSize; 5321 Register DstReg = MI.getOperand(0).getReg(); 5322 if (WideSize > RegTy.getSizeInBits()) { 5323 Register MergeReg = MRI.createGenericVirtualRegister(LLT::scalar(WideSize)); 5324 MIRBuilder.buildMerge(MergeReg, DstRegs); 5325 MIRBuilder.buildTrunc(DstReg, MergeReg); 5326 } else 5327 MIRBuilder.buildMerge(DstReg, DstRegs); 5328 5329 MI.eraseFromParent(); 5330 return Legalized; 5331 } 5332 5333 LegalizerHelper::LegalizeResult 5334 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, 5335 LLT NarrowTy) { 5336 Register DstReg = MI.getOperand(0).getReg(); 5337 LLT DstTy = MRI.getType(DstReg); 5338 5339 assert(MI.getNumOperands() == 3 && TypeIdx == 0); 5340 5341 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 5342 SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs; 5343 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 5344 LLT LeftoverTy; 5345 if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy, 5346 Src0Regs, Src0LeftoverRegs)) 5347 return UnableToLegalize; 5348 5349 LLT Unused; 5350 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused, 5351 Src1Regs, Src1LeftoverRegs)) 5352 llvm_unreachable("inconsistent extractParts result"); 5353 5354 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 5355 auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 5356 {Src0Regs[I], Src1Regs[I]}); 5357 DstRegs.push_back(Inst.getReg(0)); 5358 } 5359 5360 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 5361 auto Inst = MIRBuilder.buildInstr( 5362 MI.getOpcode(), 5363 {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]}); 5364 DstLeftoverRegs.push_back(Inst.getReg(0)); 5365 } 5366 5367 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 5368 LeftoverTy, DstLeftoverRegs); 5369 5370 MI.eraseFromParent(); 5371 return Legalized; 5372 } 5373 5374 LegalizerHelper::LegalizeResult 5375 LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, 5376 LLT NarrowTy) { 5377 if (TypeIdx != 0) 5378 return UnableToLegalize; 5379 5380 Register DstReg = MI.getOperand(0).getReg(); 5381 Register SrcReg = MI.getOperand(1).getReg(); 5382 5383 LLT DstTy = MRI.getType(DstReg); 5384 if (DstTy.isVector()) 5385 return UnableToLegalize; 5386 5387 SmallVector<Register, 8> Parts; 5388 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 5389 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, MI.getOpcode()); 5390 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 5391 5392 MI.eraseFromParent(); 5393 return Legalized; 5394 } 5395 5396 LegalizerHelper::LegalizeResult 5397 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, 5398 LLT NarrowTy) { 5399 if (TypeIdx != 0) 5400 return UnableToLegalize; 5401 5402 Register CondReg = MI.getOperand(1).getReg(); 5403 LLT CondTy = MRI.getType(CondReg); 5404 if (CondTy.isVector()) // TODO: Handle vselect 5405 return UnableToLegalize; 5406 5407 Register DstReg = MI.getOperand(0).getReg(); 5408 LLT DstTy = MRI.getType(DstReg); 5409 5410 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 5411 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 5412 SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs; 5413 LLT LeftoverTy; 5414 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy, 5415 Src1Regs, Src1LeftoverRegs)) 5416 return UnableToLegalize; 5417 5418 LLT Unused; 5419 if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused, 5420 Src2Regs, Src2LeftoverRegs)) 5421 llvm_unreachable("inconsistent extractParts result"); 5422 5423 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 5424 auto Select = MIRBuilder.buildSelect(NarrowTy, 5425 CondReg, Src1Regs[I], Src2Regs[I]); 5426 DstRegs.push_back(Select.getReg(0)); 5427 } 5428 5429 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 5430 auto Select = MIRBuilder.buildSelect( 5431 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); 5432 DstLeftoverRegs.push_back(Select.getReg(0)); 5433 } 5434 5435 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 5436 LeftoverTy, DstLeftoverRegs); 5437 5438 MI.eraseFromParent(); 5439 return Legalized; 5440 } 5441 5442 LegalizerHelper::LegalizeResult 5443 LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, 5444 LLT NarrowTy) { 5445 if (TypeIdx != 1) 5446 return UnableToLegalize; 5447 5448 Register DstReg = MI.getOperand(0).getReg(); 5449 Register SrcReg = MI.getOperand(1).getReg(); 5450 LLT DstTy = MRI.getType(DstReg); 5451 LLT SrcTy = MRI.getType(SrcReg); 5452 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5453 5454 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5455 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF; 5456 5457 MachineIRBuilder &B = MIRBuilder; 5458 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 5459 // ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi) 5460 auto C_0 = B.buildConstant(NarrowTy, 0); 5461 auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 5462 UnmergeSrc.getReg(1), C_0); 5463 auto LoCTLZ = IsUndef ? 5464 B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)) : 5465 B.buildCTLZ(DstTy, UnmergeSrc.getReg(0)); 5466 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 5467 auto HiIsZeroCTLZ = B.buildAdd(DstTy, LoCTLZ, C_NarrowSize); 5468 auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)); 5469 B.buildSelect(DstReg, HiIsZero, HiIsZeroCTLZ, HiCTLZ); 5470 5471 MI.eraseFromParent(); 5472 return Legalized; 5473 } 5474 5475 return UnableToLegalize; 5476 } 5477 5478 LegalizerHelper::LegalizeResult 5479 LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, 5480 LLT NarrowTy) { 5481 if (TypeIdx != 1) 5482 return UnableToLegalize; 5483 5484 Register DstReg = MI.getOperand(0).getReg(); 5485 Register SrcReg = MI.getOperand(1).getReg(); 5486 LLT DstTy = MRI.getType(DstReg); 5487 LLT SrcTy = MRI.getType(SrcReg); 5488 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5489 5490 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5491 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF; 5492 5493 MachineIRBuilder &B = MIRBuilder; 5494 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 5495 // cttz(Hi:Lo) -> Lo == 0 ? (cttz(Hi) + NarrowSize) : cttz(Lo) 5496 auto C_0 = B.buildConstant(NarrowTy, 0); 5497 auto LoIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 5498 UnmergeSrc.getReg(0), C_0); 5499 auto HiCTTZ = IsUndef ? 5500 B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)) : 5501 B.buildCTTZ(DstTy, UnmergeSrc.getReg(1)); 5502 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 5503 auto LoIsZeroCTTZ = B.buildAdd(DstTy, HiCTTZ, C_NarrowSize); 5504 auto LoCTTZ = B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)); 5505 B.buildSelect(DstReg, LoIsZero, LoIsZeroCTTZ, LoCTTZ); 5506 5507 MI.eraseFromParent(); 5508 return Legalized; 5509 } 5510 5511 return UnableToLegalize; 5512 } 5513 5514 LegalizerHelper::LegalizeResult 5515 LegalizerHelper::narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, 5516 LLT NarrowTy) { 5517 if (TypeIdx != 1) 5518 return UnableToLegalize; 5519 5520 Register DstReg = MI.getOperand(0).getReg(); 5521 LLT DstTy = MRI.getType(DstReg); 5522 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 5523 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5524 5525 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5526 auto UnmergeSrc = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 5527 5528 auto LoCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(0)); 5529 auto HiCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(1)); 5530 MIRBuilder.buildAdd(DstReg, HiCTPOP, LoCTPOP); 5531 5532 MI.eraseFromParent(); 5533 return Legalized; 5534 } 5535 5536 return UnableToLegalize; 5537 } 5538 5539 LegalizerHelper::LegalizeResult 5540 LegalizerHelper::lowerBitCount(MachineInstr &MI) { 5541 unsigned Opc = MI.getOpcode(); 5542 const auto &TII = MIRBuilder.getTII(); 5543 auto isSupported = [this](const LegalityQuery &Q) { 5544 auto QAction = LI.getAction(Q).Action; 5545 return QAction == Legal || QAction == Libcall || QAction == Custom; 5546 }; 5547 switch (Opc) { 5548 default: 5549 return UnableToLegalize; 5550 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 5551 // This trivially expands to CTLZ. 5552 Observer.changingInstr(MI); 5553 MI.setDesc(TII.get(TargetOpcode::G_CTLZ)); 5554 Observer.changedInstr(MI); 5555 return Legalized; 5556 } 5557 case TargetOpcode::G_CTLZ: { 5558 Register DstReg = MI.getOperand(0).getReg(); 5559 Register SrcReg = MI.getOperand(1).getReg(); 5560 LLT DstTy = MRI.getType(DstReg); 5561 LLT SrcTy = MRI.getType(SrcReg); 5562 unsigned Len = SrcTy.getSizeInBits(); 5563 5564 if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 5565 // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero. 5566 auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg); 5567 auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0); 5568 auto ICmp = MIRBuilder.buildICmp( 5569 CmpInst::ICMP_EQ, SrcTy.changeElementSize(1), SrcReg, ZeroSrc); 5570 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 5571 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CtlzZU); 5572 MI.eraseFromParent(); 5573 return Legalized; 5574 } 5575 // for now, we do this: 5576 // NewLen = NextPowerOf2(Len); 5577 // x = x | (x >> 1); 5578 // x = x | (x >> 2); 5579 // ... 5580 // x = x | (x >>16); 5581 // x = x | (x >>32); // for 64-bit input 5582 // Upto NewLen/2 5583 // return Len - popcount(x); 5584 // 5585 // Ref: "Hacker's Delight" by Henry Warren 5586 Register Op = SrcReg; 5587 unsigned NewLen = PowerOf2Ceil(Len); 5588 for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) { 5589 auto MIBShiftAmt = MIRBuilder.buildConstant(SrcTy, 1ULL << i); 5590 auto MIBOp = MIRBuilder.buildOr( 5591 SrcTy, Op, MIRBuilder.buildLShr(SrcTy, Op, MIBShiftAmt)); 5592 Op = MIBOp.getReg(0); 5593 } 5594 auto MIBPop = MIRBuilder.buildCTPOP(DstTy, Op); 5595 MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(DstTy, Len), 5596 MIBPop); 5597 MI.eraseFromParent(); 5598 return Legalized; 5599 } 5600 case TargetOpcode::G_CTTZ_ZERO_UNDEF: { 5601 // This trivially expands to CTTZ. 5602 Observer.changingInstr(MI); 5603 MI.setDesc(TII.get(TargetOpcode::G_CTTZ)); 5604 Observer.changedInstr(MI); 5605 return Legalized; 5606 } 5607 case TargetOpcode::G_CTTZ: { 5608 Register DstReg = MI.getOperand(0).getReg(); 5609 Register SrcReg = MI.getOperand(1).getReg(); 5610 LLT DstTy = MRI.getType(DstReg); 5611 LLT SrcTy = MRI.getType(SrcReg); 5612 5613 unsigned Len = SrcTy.getSizeInBits(); 5614 if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 5615 // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with 5616 // zero. 5617 auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg); 5618 auto Zero = MIRBuilder.buildConstant(SrcTy, 0); 5619 auto ICmp = MIRBuilder.buildICmp( 5620 CmpInst::ICMP_EQ, DstTy.changeElementSize(1), SrcReg, Zero); 5621 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 5622 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CttzZU); 5623 MI.eraseFromParent(); 5624 return Legalized; 5625 } 5626 // for now, we use: { return popcount(~x & (x - 1)); } 5627 // unless the target has ctlz but not ctpop, in which case we use: 5628 // { return 32 - nlz(~x & (x-1)); } 5629 // Ref: "Hacker's Delight" by Henry Warren 5630 auto MIBCstNeg1 = MIRBuilder.buildConstant(SrcTy, -1); 5631 auto MIBNot = MIRBuilder.buildXor(SrcTy, SrcReg, MIBCstNeg1); 5632 auto MIBTmp = MIRBuilder.buildAnd( 5633 SrcTy, MIBNot, MIRBuilder.buildAdd(SrcTy, SrcReg, MIBCstNeg1)); 5634 if (!isSupported({TargetOpcode::G_CTPOP, {SrcTy, SrcTy}}) && 5635 isSupported({TargetOpcode::G_CTLZ, {SrcTy, SrcTy}})) { 5636 auto MIBCstLen = MIRBuilder.buildConstant(SrcTy, Len); 5637 MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen, 5638 MIRBuilder.buildCTLZ(SrcTy, MIBTmp)); 5639 MI.eraseFromParent(); 5640 return Legalized; 5641 } 5642 MI.setDesc(TII.get(TargetOpcode::G_CTPOP)); 5643 MI.getOperand(1).setReg(MIBTmp.getReg(0)); 5644 return Legalized; 5645 } 5646 case TargetOpcode::G_CTPOP: { 5647 Register SrcReg = MI.getOperand(1).getReg(); 5648 LLT Ty = MRI.getType(SrcReg); 5649 unsigned Size = Ty.getSizeInBits(); 5650 MachineIRBuilder &B = MIRBuilder; 5651 5652 // Count set bits in blocks of 2 bits. Default approach would be 5653 // B2Count = { val & 0x55555555 } + { (val >> 1) & 0x55555555 } 5654 // We use following formula instead: 5655 // B2Count = val - { (val >> 1) & 0x55555555 } 5656 // since it gives same result in blocks of 2 with one instruction less. 5657 auto C_1 = B.buildConstant(Ty, 1); 5658 auto B2Set1LoTo1Hi = B.buildLShr(Ty, SrcReg, C_1); 5659 APInt B2Mask1HiTo0 = APInt::getSplat(Size, APInt(8, 0x55)); 5660 auto C_B2Mask1HiTo0 = B.buildConstant(Ty, B2Mask1HiTo0); 5661 auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0); 5662 auto B2Count = B.buildSub(Ty, SrcReg, B2Count1Hi); 5663 5664 // In order to get count in blocks of 4 add values from adjacent block of 2. 5665 // B4Count = { B2Count & 0x33333333 } + { (B2Count >> 2) & 0x33333333 } 5666 auto C_2 = B.buildConstant(Ty, 2); 5667 auto B4Set2LoTo2Hi = B.buildLShr(Ty, B2Count, C_2); 5668 APInt B4Mask2HiTo0 = APInt::getSplat(Size, APInt(8, 0x33)); 5669 auto C_B4Mask2HiTo0 = B.buildConstant(Ty, B4Mask2HiTo0); 5670 auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0); 5671 auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0); 5672 auto B4Count = B.buildAdd(Ty, B4HiB2Count, B4LoB2Count); 5673 5674 // For count in blocks of 8 bits we don't have to mask high 4 bits before 5675 // addition since count value sits in range {0,...,8} and 4 bits are enough 5676 // to hold such binary values. After addition high 4 bits still hold count 5677 // of set bits in high 4 bit block, set them to zero and get 8 bit result. 5678 // B8Count = { B4Count + (B4Count >> 4) } & 0x0F0F0F0F 5679 auto C_4 = B.buildConstant(Ty, 4); 5680 auto B8HiB4Count = B.buildLShr(Ty, B4Count, C_4); 5681 auto B8CountDirty4Hi = B.buildAdd(Ty, B8HiB4Count, B4Count); 5682 APInt B8Mask4HiTo0 = APInt::getSplat(Size, APInt(8, 0x0F)); 5683 auto C_B8Mask4HiTo0 = B.buildConstant(Ty, B8Mask4HiTo0); 5684 auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0); 5685 5686 assert(Size<=128 && "Scalar size is too large for CTPOP lower algorithm"); 5687 // 8 bits can hold CTPOP result of 128 bit int or smaller. Mul with this 5688 // bitmask will set 8 msb in ResTmp to sum of all B8Counts in 8 bit blocks. 5689 auto MulMask = B.buildConstant(Ty, APInt::getSplat(Size, APInt(8, 0x01))); 5690 auto ResTmp = B.buildMul(Ty, B8Count, MulMask); 5691 5692 // Shift count result from 8 high bits to low bits. 5693 auto C_SizeM8 = B.buildConstant(Ty, Size - 8); 5694 B.buildLShr(MI.getOperand(0).getReg(), ResTmp, C_SizeM8); 5695 5696 MI.eraseFromParent(); 5697 return Legalized; 5698 } 5699 } 5700 } 5701 5702 // Check that (every element of) Reg is undef or not an exact multiple of BW. 5703 static bool isNonZeroModBitWidthOrUndef(const MachineRegisterInfo &MRI, 5704 Register Reg, unsigned BW) { 5705 return matchUnaryPredicate( 5706 MRI, Reg, 5707 [=](const Constant *C) { 5708 // Null constant here means an undef. 5709 const ConstantInt *CI = dyn_cast_or_null<ConstantInt>(C); 5710 return !CI || CI->getValue().urem(BW) != 0; 5711 }, 5712 /*AllowUndefs*/ true); 5713 } 5714 5715 LegalizerHelper::LegalizeResult 5716 LegalizerHelper::lowerFunnelShiftWithInverse(MachineInstr &MI) { 5717 Register Dst = MI.getOperand(0).getReg(); 5718 Register X = MI.getOperand(1).getReg(); 5719 Register Y = MI.getOperand(2).getReg(); 5720 Register Z = MI.getOperand(3).getReg(); 5721 LLT Ty = MRI.getType(Dst); 5722 LLT ShTy = MRI.getType(Z); 5723 5724 unsigned BW = Ty.getScalarSizeInBits(); 5725 5726 if (!isPowerOf2_32(BW)) 5727 return UnableToLegalize; 5728 5729 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5730 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; 5731 5732 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { 5733 // fshl X, Y, Z -> fshr X, Y, -Z 5734 // fshr X, Y, Z -> fshl X, Y, -Z 5735 auto Zero = MIRBuilder.buildConstant(ShTy, 0); 5736 Z = MIRBuilder.buildSub(Ty, Zero, Z).getReg(0); 5737 } else { 5738 // fshl X, Y, Z -> fshr (srl X, 1), (fshr X, Y, 1), ~Z 5739 // fshr X, Y, Z -> fshl (fshl X, Y, 1), (shl Y, 1), ~Z 5740 auto One = MIRBuilder.buildConstant(ShTy, 1); 5741 if (IsFSHL) { 5742 Y = MIRBuilder.buildInstr(RevOpcode, {Ty}, {X, Y, One}).getReg(0); 5743 X = MIRBuilder.buildLShr(Ty, X, One).getReg(0); 5744 } else { 5745 X = MIRBuilder.buildInstr(RevOpcode, {Ty}, {X, Y, One}).getReg(0); 5746 Y = MIRBuilder.buildShl(Ty, Y, One).getReg(0); 5747 } 5748 5749 Z = MIRBuilder.buildNot(ShTy, Z).getReg(0); 5750 } 5751 5752 MIRBuilder.buildInstr(RevOpcode, {Dst}, {X, Y, Z}); 5753 MI.eraseFromParent(); 5754 return Legalized; 5755 } 5756 5757 LegalizerHelper::LegalizeResult 5758 LegalizerHelper::lowerFunnelShiftAsShifts(MachineInstr &MI) { 5759 Register Dst = MI.getOperand(0).getReg(); 5760 Register X = MI.getOperand(1).getReg(); 5761 Register Y = MI.getOperand(2).getReg(); 5762 Register Z = MI.getOperand(3).getReg(); 5763 LLT Ty = MRI.getType(Dst); 5764 LLT ShTy = MRI.getType(Z); 5765 5766 const unsigned BW = Ty.getScalarSizeInBits(); 5767 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5768 5769 Register ShX, ShY; 5770 Register ShAmt, InvShAmt; 5771 5772 // FIXME: Emit optimized urem by constant instead of letting it expand later. 5773 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { 5774 // fshl: X << C | Y >> (BW - C) 5775 // fshr: X << (BW - C) | Y >> C 5776 // where C = Z % BW is not zero 5777 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); 5778 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); 5779 InvShAmt = MIRBuilder.buildSub(ShTy, BitWidthC, ShAmt).getReg(0); 5780 ShX = MIRBuilder.buildShl(Ty, X, IsFSHL ? ShAmt : InvShAmt).getReg(0); 5781 ShY = MIRBuilder.buildLShr(Ty, Y, IsFSHL ? InvShAmt : ShAmt).getReg(0); 5782 } else { 5783 // fshl: X << (Z % BW) | Y >> 1 >> (BW - 1 - (Z % BW)) 5784 // fshr: X << 1 << (BW - 1 - (Z % BW)) | Y >> (Z % BW) 5785 auto Mask = MIRBuilder.buildConstant(ShTy, BW - 1); 5786 if (isPowerOf2_32(BW)) { 5787 // Z % BW -> Z & (BW - 1) 5788 ShAmt = MIRBuilder.buildAnd(ShTy, Z, Mask).getReg(0); 5789 // (BW - 1) - (Z % BW) -> ~Z & (BW - 1) 5790 auto NotZ = MIRBuilder.buildNot(ShTy, Z); 5791 InvShAmt = MIRBuilder.buildAnd(ShTy, NotZ, Mask).getReg(0); 5792 } else { 5793 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); 5794 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); 5795 InvShAmt = MIRBuilder.buildSub(ShTy, Mask, ShAmt).getReg(0); 5796 } 5797 5798 auto One = MIRBuilder.buildConstant(ShTy, 1); 5799 if (IsFSHL) { 5800 ShX = MIRBuilder.buildShl(Ty, X, ShAmt).getReg(0); 5801 auto ShY1 = MIRBuilder.buildLShr(Ty, Y, One); 5802 ShY = MIRBuilder.buildLShr(Ty, ShY1, InvShAmt).getReg(0); 5803 } else { 5804 auto ShX1 = MIRBuilder.buildShl(Ty, X, One); 5805 ShX = MIRBuilder.buildShl(Ty, ShX1, InvShAmt).getReg(0); 5806 ShY = MIRBuilder.buildLShr(Ty, Y, ShAmt).getReg(0); 5807 } 5808 } 5809 5810 MIRBuilder.buildOr(Dst, ShX, ShY); 5811 MI.eraseFromParent(); 5812 return Legalized; 5813 } 5814 5815 LegalizerHelper::LegalizeResult 5816 LegalizerHelper::lowerFunnelShift(MachineInstr &MI) { 5817 // These operations approximately do the following (while avoiding undefined 5818 // shifts by BW): 5819 // G_FSHL: (X << (Z % BW)) | (Y >> (BW - (Z % BW))) 5820 // G_FSHR: (X << (BW - (Z % BW))) | (Y >> (Z % BW)) 5821 Register Dst = MI.getOperand(0).getReg(); 5822 LLT Ty = MRI.getType(Dst); 5823 LLT ShTy = MRI.getType(MI.getOperand(3).getReg()); 5824 5825 bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5826 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; 5827 5828 // TODO: Use smarter heuristic that accounts for vector legalization. 5829 if (LI.getAction({RevOpcode, {Ty, ShTy}}).Action == Lower) 5830 return lowerFunnelShiftAsShifts(MI); 5831 5832 // This only works for powers of 2, fallback to shifts if it fails. 5833 LegalizerHelper::LegalizeResult Result = lowerFunnelShiftWithInverse(MI); 5834 if (Result == UnableToLegalize) 5835 return lowerFunnelShiftAsShifts(MI); 5836 return Result; 5837 } 5838 5839 LegalizerHelper::LegalizeResult 5840 LegalizerHelper::lowerRotateWithReverseRotate(MachineInstr &MI) { 5841 Register Dst = MI.getOperand(0).getReg(); 5842 Register Src = MI.getOperand(1).getReg(); 5843 Register Amt = MI.getOperand(2).getReg(); 5844 LLT AmtTy = MRI.getType(Amt); 5845 auto Zero = MIRBuilder.buildConstant(AmtTy, 0); 5846 bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL; 5847 unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL; 5848 auto Neg = MIRBuilder.buildSub(AmtTy, Zero, Amt); 5849 MIRBuilder.buildInstr(RevRot, {Dst}, {Src, Neg}); 5850 MI.eraseFromParent(); 5851 return Legalized; 5852 } 5853 5854 LegalizerHelper::LegalizeResult LegalizerHelper::lowerRotate(MachineInstr &MI) { 5855 Register Dst = MI.getOperand(0).getReg(); 5856 Register Src = MI.getOperand(1).getReg(); 5857 Register Amt = MI.getOperand(2).getReg(); 5858 LLT DstTy = MRI.getType(Dst); 5859 LLT SrcTy = MRI.getType(Dst); 5860 LLT AmtTy = MRI.getType(Amt); 5861 5862 unsigned EltSizeInBits = DstTy.getScalarSizeInBits(); 5863 bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL; 5864 5865 MIRBuilder.setInstrAndDebugLoc(MI); 5866 5867 // If a rotate in the other direction is supported, use it. 5868 unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL; 5869 if (LI.isLegalOrCustom({RevRot, {DstTy, SrcTy}}) && 5870 isPowerOf2_32(EltSizeInBits)) 5871 return lowerRotateWithReverseRotate(MI); 5872 5873 auto Zero = MIRBuilder.buildConstant(AmtTy, 0); 5874 unsigned ShOpc = IsLeft ? TargetOpcode::G_SHL : TargetOpcode::G_LSHR; 5875 unsigned RevShiftOpc = IsLeft ? TargetOpcode::G_LSHR : TargetOpcode::G_SHL; 5876 auto BitWidthMinusOneC = MIRBuilder.buildConstant(AmtTy, EltSizeInBits - 1); 5877 Register ShVal; 5878 Register RevShiftVal; 5879 if (isPowerOf2_32(EltSizeInBits)) { 5880 // (rotl x, c) -> x << (c & (w - 1)) | x >> (-c & (w - 1)) 5881 // (rotr x, c) -> x >> (c & (w - 1)) | x << (-c & (w - 1)) 5882 auto NegAmt = MIRBuilder.buildSub(AmtTy, Zero, Amt); 5883 auto ShAmt = MIRBuilder.buildAnd(AmtTy, Amt, BitWidthMinusOneC); 5884 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); 5885 auto RevAmt = MIRBuilder.buildAnd(AmtTy, NegAmt, BitWidthMinusOneC); 5886 RevShiftVal = 5887 MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Src, RevAmt}).getReg(0); 5888 } else { 5889 // (rotl x, c) -> x << (c % w) | x >> 1 >> (w - 1 - (c % w)) 5890 // (rotr x, c) -> x >> (c % w) | x << 1 << (w - 1 - (c % w)) 5891 auto BitWidthC = MIRBuilder.buildConstant(AmtTy, EltSizeInBits); 5892 auto ShAmt = MIRBuilder.buildURem(AmtTy, Amt, BitWidthC); 5893 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); 5894 auto RevAmt = MIRBuilder.buildSub(AmtTy, BitWidthMinusOneC, ShAmt); 5895 auto One = MIRBuilder.buildConstant(AmtTy, 1); 5896 auto Inner = MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Src, One}); 5897 RevShiftVal = 5898 MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Inner, RevAmt}).getReg(0); 5899 } 5900 MIRBuilder.buildOr(Dst, ShVal, RevShiftVal); 5901 MI.eraseFromParent(); 5902 return Legalized; 5903 } 5904 5905 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float 5906 // representation. 5907 LegalizerHelper::LegalizeResult 5908 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) { 5909 Register Dst = MI.getOperand(0).getReg(); 5910 Register Src = MI.getOperand(1).getReg(); 5911 const LLT S64 = LLT::scalar(64); 5912 const LLT S32 = LLT::scalar(32); 5913 const LLT S1 = LLT::scalar(1); 5914 5915 assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32); 5916 5917 // unsigned cul2f(ulong u) { 5918 // uint lz = clz(u); 5919 // uint e = (u != 0) ? 127U + 63U - lz : 0; 5920 // u = (u << lz) & 0x7fffffffffffffffUL; 5921 // ulong t = u & 0xffffffffffUL; 5922 // uint v = (e << 23) | (uint)(u >> 40); 5923 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U); 5924 // return as_float(v + r); 5925 // } 5926 5927 auto Zero32 = MIRBuilder.buildConstant(S32, 0); 5928 auto Zero64 = MIRBuilder.buildConstant(S64, 0); 5929 5930 auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src); 5931 5932 auto K = MIRBuilder.buildConstant(S32, 127U + 63U); 5933 auto Sub = MIRBuilder.buildSub(S32, K, LZ); 5934 5935 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64); 5936 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32); 5937 5938 auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1); 5939 auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ); 5940 5941 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0); 5942 5943 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); 5944 auto T = MIRBuilder.buildAnd(S64, U, Mask1); 5945 5946 auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40)); 5947 auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23)); 5948 auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl)); 5949 5950 auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL); 5951 auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C); 5952 auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C); 5953 auto One = MIRBuilder.buildConstant(S32, 1); 5954 5955 auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One); 5956 auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32); 5957 auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0); 5958 MIRBuilder.buildAdd(Dst, V, R); 5959 5960 MI.eraseFromParent(); 5961 return Legalized; 5962 } 5963 5964 LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) { 5965 Register Dst = MI.getOperand(0).getReg(); 5966 Register Src = MI.getOperand(1).getReg(); 5967 LLT DstTy = MRI.getType(Dst); 5968 LLT SrcTy = MRI.getType(Src); 5969 5970 if (SrcTy == LLT::scalar(1)) { 5971 auto True = MIRBuilder.buildFConstant(DstTy, 1.0); 5972 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5973 MIRBuilder.buildSelect(Dst, Src, True, False); 5974 MI.eraseFromParent(); 5975 return Legalized; 5976 } 5977 5978 if (SrcTy != LLT::scalar(64)) 5979 return UnableToLegalize; 5980 5981 if (DstTy == LLT::scalar(32)) { 5982 // TODO: SelectionDAG has several alternative expansions to port which may 5983 // be more reasonble depending on the available instructions. If a target 5984 // has sitofp, does not have CTLZ, or can efficiently use f64 as an 5985 // intermediate type, this is probably worse. 5986 return lowerU64ToF32BitOps(MI); 5987 } 5988 5989 return UnableToLegalize; 5990 } 5991 5992 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) { 5993 Register Dst = MI.getOperand(0).getReg(); 5994 Register Src = MI.getOperand(1).getReg(); 5995 LLT DstTy = MRI.getType(Dst); 5996 LLT SrcTy = MRI.getType(Src); 5997 5998 const LLT S64 = LLT::scalar(64); 5999 const LLT S32 = LLT::scalar(32); 6000 const LLT S1 = LLT::scalar(1); 6001 6002 if (SrcTy == S1) { 6003 auto True = MIRBuilder.buildFConstant(DstTy, -1.0); 6004 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 6005 MIRBuilder.buildSelect(Dst, Src, True, False); 6006 MI.eraseFromParent(); 6007 return Legalized; 6008 } 6009 6010 if (SrcTy != S64) 6011 return UnableToLegalize; 6012 6013 if (DstTy == S32) { 6014 // signed cl2f(long l) { 6015 // long s = l >> 63; 6016 // float r = cul2f((l + s) ^ s); 6017 // return s ? -r : r; 6018 // } 6019 Register L = Src; 6020 auto SignBit = MIRBuilder.buildConstant(S64, 63); 6021 auto S = MIRBuilder.buildAShr(S64, L, SignBit); 6022 6023 auto LPlusS = MIRBuilder.buildAdd(S64, L, S); 6024 auto Xor = MIRBuilder.buildXor(S64, LPlusS, S); 6025 auto R = MIRBuilder.buildUITOFP(S32, Xor); 6026 6027 auto RNeg = MIRBuilder.buildFNeg(S32, R); 6028 auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S, 6029 MIRBuilder.buildConstant(S64, 0)); 6030 MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R); 6031 MI.eraseFromParent(); 6032 return Legalized; 6033 } 6034 6035 return UnableToLegalize; 6036 } 6037 6038 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) { 6039 Register Dst = MI.getOperand(0).getReg(); 6040 Register Src = MI.getOperand(1).getReg(); 6041 LLT DstTy = MRI.getType(Dst); 6042 LLT SrcTy = MRI.getType(Src); 6043 const LLT S64 = LLT::scalar(64); 6044 const LLT S32 = LLT::scalar(32); 6045 6046 if (SrcTy != S64 && SrcTy != S32) 6047 return UnableToLegalize; 6048 if (DstTy != S32 && DstTy != S64) 6049 return UnableToLegalize; 6050 6051 // FPTOSI gives same result as FPTOUI for positive signed integers. 6052 // FPTOUI needs to deal with fp values that convert to unsigned integers 6053 // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp. 6054 6055 APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits()); 6056 APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle() 6057 : APFloat::IEEEdouble(), 6058 APInt::getNullValue(SrcTy.getSizeInBits())); 6059 TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven); 6060 6061 MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src); 6062 6063 MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP); 6064 // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on 6065 // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1. 6066 MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold); 6067 MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub); 6068 MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt); 6069 MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit); 6070 6071 const LLT S1 = LLT::scalar(1); 6072 6073 MachineInstrBuilder FCMP = 6074 MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold); 6075 MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res); 6076 6077 MI.eraseFromParent(); 6078 return Legalized; 6079 } 6080 6081 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) { 6082 Register Dst = MI.getOperand(0).getReg(); 6083 Register Src = MI.getOperand(1).getReg(); 6084 LLT DstTy = MRI.getType(Dst); 6085 LLT SrcTy = MRI.getType(Src); 6086 const LLT S64 = LLT::scalar(64); 6087 const LLT S32 = LLT::scalar(32); 6088 6089 // FIXME: Only f32 to i64 conversions are supported. 6090 if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64) 6091 return UnableToLegalize; 6092 6093 // Expand f32 -> i64 conversion 6094 // This algorithm comes from compiler-rt's implementation of fixsfdi: 6095 // https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/fixsfdi.c 6096 6097 unsigned SrcEltBits = SrcTy.getScalarSizeInBits(); 6098 6099 auto ExponentMask = MIRBuilder.buildConstant(SrcTy, 0x7F800000); 6100 auto ExponentLoBit = MIRBuilder.buildConstant(SrcTy, 23); 6101 6102 auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask); 6103 auto ExponentBits = MIRBuilder.buildLShr(SrcTy, AndExpMask, ExponentLoBit); 6104 6105 auto SignMask = MIRBuilder.buildConstant(SrcTy, 6106 APInt::getSignMask(SrcEltBits)); 6107 auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask); 6108 auto SignLowBit = MIRBuilder.buildConstant(SrcTy, SrcEltBits - 1); 6109 auto Sign = MIRBuilder.buildAShr(SrcTy, AndSignMask, SignLowBit); 6110 Sign = MIRBuilder.buildSExt(DstTy, Sign); 6111 6112 auto MantissaMask = MIRBuilder.buildConstant(SrcTy, 0x007FFFFF); 6113 auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask); 6114 auto K = MIRBuilder.buildConstant(SrcTy, 0x00800000); 6115 6116 auto R = MIRBuilder.buildOr(SrcTy, AndMantissaMask, K); 6117 R = MIRBuilder.buildZExt(DstTy, R); 6118 6119 auto Bias = MIRBuilder.buildConstant(SrcTy, 127); 6120 auto Exponent = MIRBuilder.buildSub(SrcTy, ExponentBits, Bias); 6121 auto SubExponent = MIRBuilder.buildSub(SrcTy, Exponent, ExponentLoBit); 6122 auto ExponentSub = MIRBuilder.buildSub(SrcTy, ExponentLoBit, Exponent); 6123 6124 auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent); 6125 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); 6126 6127 const LLT S1 = LLT::scalar(1); 6128 auto CmpGt = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, 6129 S1, Exponent, ExponentLoBit); 6130 6131 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl); 6132 6133 auto XorSign = MIRBuilder.buildXor(DstTy, R, Sign); 6134 auto Ret = MIRBuilder.buildSub(DstTy, XorSign, Sign); 6135 6136 auto ZeroSrcTy = MIRBuilder.buildConstant(SrcTy, 0); 6137 6138 auto ExponentLt0 = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, 6139 S1, Exponent, ZeroSrcTy); 6140 6141 auto ZeroDstTy = MIRBuilder.buildConstant(DstTy, 0); 6142 MIRBuilder.buildSelect(Dst, ExponentLt0, ZeroDstTy, Ret); 6143 6144 MI.eraseFromParent(); 6145 return Legalized; 6146 } 6147 6148 // f64 -> f16 conversion using round-to-nearest-even rounding mode. 6149 LegalizerHelper::LegalizeResult 6150 LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) { 6151 Register Dst = MI.getOperand(0).getReg(); 6152 Register Src = MI.getOperand(1).getReg(); 6153 6154 if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly. 6155 return UnableToLegalize; 6156 6157 const unsigned ExpMask = 0x7ff; 6158 const unsigned ExpBiasf64 = 1023; 6159 const unsigned ExpBiasf16 = 15; 6160 const LLT S32 = LLT::scalar(32); 6161 const LLT S1 = LLT::scalar(1); 6162 6163 auto Unmerge = MIRBuilder.buildUnmerge(S32, Src); 6164 Register U = Unmerge.getReg(0); 6165 Register UH = Unmerge.getReg(1); 6166 6167 auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20)); 6168 E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask)); 6169 6170 // Subtract the fp64 exponent bias (1023) to get the real exponent and 6171 // add the f16 bias (15) to get the biased exponent for the f16 format. 6172 E = MIRBuilder.buildAdd( 6173 S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16)); 6174 6175 auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8)); 6176 M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe)); 6177 6178 auto MaskedSig = MIRBuilder.buildAnd(S32, UH, 6179 MIRBuilder.buildConstant(S32, 0x1ff)); 6180 MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U); 6181 6182 auto Zero = MIRBuilder.buildConstant(S32, 0); 6183 auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero); 6184 auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0); 6185 M = MIRBuilder.buildOr(S32, M, Lo40Set); 6186 6187 // (M != 0 ? 0x0200 : 0) | 0x7c00; 6188 auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200); 6189 auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero); 6190 auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero); 6191 6192 auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00); 6193 auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00); 6194 6195 // N = M | (E << 12); 6196 auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12)); 6197 auto N = MIRBuilder.buildOr(S32, M, EShl12); 6198 6199 // B = clamp(1-E, 0, 13); 6200 auto One = MIRBuilder.buildConstant(S32, 1); 6201 auto OneSubExp = MIRBuilder.buildSub(S32, One, E); 6202 auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero); 6203 B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13)); 6204 6205 auto SigSetHigh = MIRBuilder.buildOr(S32, M, 6206 MIRBuilder.buildConstant(S32, 0x1000)); 6207 6208 auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B); 6209 auto D0 = MIRBuilder.buildShl(S32, D, B); 6210 6211 auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, 6212 D0, SigSetHigh); 6213 auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh); 6214 D = MIRBuilder.buildOr(S32, D, D1); 6215 6216 auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One); 6217 auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N); 6218 6219 auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7)); 6220 V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2)); 6221 6222 auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3, 6223 MIRBuilder.buildConstant(S32, 3)); 6224 auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3); 6225 6226 auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3, 6227 MIRBuilder.buildConstant(S32, 5)); 6228 auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5); 6229 6230 V1 = MIRBuilder.buildOr(S32, V0, V1); 6231 V = MIRBuilder.buildAdd(S32, V, V1); 6232 6233 auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, 6234 E, MIRBuilder.buildConstant(S32, 30)); 6235 V = MIRBuilder.buildSelect(S32, CmpEGt30, 6236 MIRBuilder.buildConstant(S32, 0x7c00), V); 6237 6238 auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, 6239 E, MIRBuilder.buildConstant(S32, 1039)); 6240 V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V); 6241 6242 // Extract the sign bit. 6243 auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16)); 6244 Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000)); 6245 6246 // Insert the sign bit 6247 V = MIRBuilder.buildOr(S32, Sign, V); 6248 6249 MIRBuilder.buildTrunc(Dst, V); 6250 MI.eraseFromParent(); 6251 return Legalized; 6252 } 6253 6254 LegalizerHelper::LegalizeResult 6255 LegalizerHelper::lowerFPTRUNC(MachineInstr &MI) { 6256 Register Dst = MI.getOperand(0).getReg(); 6257 Register Src = MI.getOperand(1).getReg(); 6258 6259 LLT DstTy = MRI.getType(Dst); 6260 LLT SrcTy = MRI.getType(Src); 6261 const LLT S64 = LLT::scalar(64); 6262 const LLT S16 = LLT::scalar(16); 6263 6264 if (DstTy.getScalarType() == S16 && SrcTy.getScalarType() == S64) 6265 return lowerFPTRUNC_F64_TO_F16(MI); 6266 6267 return UnableToLegalize; 6268 } 6269 6270 // TODO: If RHS is a constant SelectionDAGBuilder expands this into a 6271 // multiplication tree. 6272 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPOWI(MachineInstr &MI) { 6273 Register Dst = MI.getOperand(0).getReg(); 6274 Register Src0 = MI.getOperand(1).getReg(); 6275 Register Src1 = MI.getOperand(2).getReg(); 6276 LLT Ty = MRI.getType(Dst); 6277 6278 auto CvtSrc1 = MIRBuilder.buildSITOFP(Ty, Src1); 6279 MIRBuilder.buildFPow(Dst, Src0, CvtSrc1, MI.getFlags()); 6280 MI.eraseFromParent(); 6281 return Legalized; 6282 } 6283 6284 static CmpInst::Predicate minMaxToCompare(unsigned Opc) { 6285 switch (Opc) { 6286 case TargetOpcode::G_SMIN: 6287 return CmpInst::ICMP_SLT; 6288 case TargetOpcode::G_SMAX: 6289 return CmpInst::ICMP_SGT; 6290 case TargetOpcode::G_UMIN: 6291 return CmpInst::ICMP_ULT; 6292 case TargetOpcode::G_UMAX: 6293 return CmpInst::ICMP_UGT; 6294 default: 6295 llvm_unreachable("not in integer min/max"); 6296 } 6297 } 6298 6299 LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) { 6300 Register Dst = MI.getOperand(0).getReg(); 6301 Register Src0 = MI.getOperand(1).getReg(); 6302 Register Src1 = MI.getOperand(2).getReg(); 6303 6304 const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode()); 6305 LLT CmpType = MRI.getType(Dst).changeElementSize(1); 6306 6307 auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1); 6308 MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1); 6309 6310 MI.eraseFromParent(); 6311 return Legalized; 6312 } 6313 6314 LegalizerHelper::LegalizeResult 6315 LegalizerHelper::lowerFCopySign(MachineInstr &MI) { 6316 Register Dst = MI.getOperand(0).getReg(); 6317 Register Src0 = MI.getOperand(1).getReg(); 6318 Register Src1 = MI.getOperand(2).getReg(); 6319 6320 const LLT Src0Ty = MRI.getType(Src0); 6321 const LLT Src1Ty = MRI.getType(Src1); 6322 6323 const int Src0Size = Src0Ty.getScalarSizeInBits(); 6324 const int Src1Size = Src1Ty.getScalarSizeInBits(); 6325 6326 auto SignBitMask = MIRBuilder.buildConstant( 6327 Src0Ty, APInt::getSignMask(Src0Size)); 6328 6329 auto NotSignBitMask = MIRBuilder.buildConstant( 6330 Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1)); 6331 6332 Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask).getReg(0); 6333 Register And1; 6334 if (Src0Ty == Src1Ty) { 6335 And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask).getReg(0); 6336 } else if (Src0Size > Src1Size) { 6337 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size); 6338 auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1); 6339 auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt); 6340 And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0); 6341 } else { 6342 auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size); 6343 auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt); 6344 auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift); 6345 And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask).getReg(0); 6346 } 6347 6348 // Be careful about setting nsz/nnan/ninf on every instruction, since the 6349 // constants are a nan and -0.0, but the final result should preserve 6350 // everything. 6351 unsigned Flags = MI.getFlags(); 6352 MIRBuilder.buildOr(Dst, And0, And1, Flags); 6353 6354 MI.eraseFromParent(); 6355 return Legalized; 6356 } 6357 6358 LegalizerHelper::LegalizeResult 6359 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) { 6360 unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ? 6361 TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE; 6362 6363 Register Dst = MI.getOperand(0).getReg(); 6364 Register Src0 = MI.getOperand(1).getReg(); 6365 Register Src1 = MI.getOperand(2).getReg(); 6366 LLT Ty = MRI.getType(Dst); 6367 6368 if (!MI.getFlag(MachineInstr::FmNoNans)) { 6369 // Insert canonicalizes if it's possible we need to quiet to get correct 6370 // sNaN behavior. 6371 6372 // Note this must be done here, and not as an optimization combine in the 6373 // absence of a dedicate quiet-snan instruction as we're using an 6374 // omni-purpose G_FCANONICALIZE. 6375 if (!isKnownNeverSNaN(Src0, MRI)) 6376 Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0); 6377 6378 if (!isKnownNeverSNaN(Src1, MRI)) 6379 Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0); 6380 } 6381 6382 // If there are no nans, it's safe to simply replace this with the non-IEEE 6383 // version. 6384 MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags()); 6385 MI.eraseFromParent(); 6386 return Legalized; 6387 } 6388 6389 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) { 6390 // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c 6391 Register DstReg = MI.getOperand(0).getReg(); 6392 LLT Ty = MRI.getType(DstReg); 6393 unsigned Flags = MI.getFlags(); 6394 6395 auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2), 6396 Flags); 6397 MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags); 6398 MI.eraseFromParent(); 6399 return Legalized; 6400 } 6401 6402 LegalizerHelper::LegalizeResult 6403 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) { 6404 Register DstReg = MI.getOperand(0).getReg(); 6405 Register X = MI.getOperand(1).getReg(); 6406 const unsigned Flags = MI.getFlags(); 6407 const LLT Ty = MRI.getType(DstReg); 6408 const LLT CondTy = Ty.changeElementSize(1); 6409 6410 // round(x) => 6411 // t = trunc(x); 6412 // d = fabs(x - t); 6413 // o = copysign(1.0f, x); 6414 // return t + (d >= 0.5 ? o : 0.0); 6415 6416 auto T = MIRBuilder.buildIntrinsicTrunc(Ty, X, Flags); 6417 6418 auto Diff = MIRBuilder.buildFSub(Ty, X, T, Flags); 6419 auto AbsDiff = MIRBuilder.buildFAbs(Ty, Diff, Flags); 6420 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 6421 auto One = MIRBuilder.buildFConstant(Ty, 1.0); 6422 auto Half = MIRBuilder.buildFConstant(Ty, 0.5); 6423 auto SignOne = MIRBuilder.buildFCopysign(Ty, One, X); 6424 6425 auto Cmp = MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half, 6426 Flags); 6427 auto Sel = MIRBuilder.buildSelect(Ty, Cmp, SignOne, Zero, Flags); 6428 6429 MIRBuilder.buildFAdd(DstReg, T, Sel, Flags); 6430 6431 MI.eraseFromParent(); 6432 return Legalized; 6433 } 6434 6435 LegalizerHelper::LegalizeResult 6436 LegalizerHelper::lowerFFloor(MachineInstr &MI) { 6437 Register DstReg = MI.getOperand(0).getReg(); 6438 Register SrcReg = MI.getOperand(1).getReg(); 6439 unsigned Flags = MI.getFlags(); 6440 LLT Ty = MRI.getType(DstReg); 6441 const LLT CondTy = Ty.changeElementSize(1); 6442 6443 // result = trunc(src); 6444 // if (src < 0.0 && src != result) 6445 // result += -1.0. 6446 6447 auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags); 6448 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 6449 6450 auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy, 6451 SrcReg, Zero, Flags); 6452 auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy, 6453 SrcReg, Trunc, Flags); 6454 auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc); 6455 auto AddVal = MIRBuilder.buildSITOFP(Ty, And); 6456 6457 MIRBuilder.buildFAdd(DstReg, Trunc, AddVal, Flags); 6458 MI.eraseFromParent(); 6459 return Legalized; 6460 } 6461 6462 LegalizerHelper::LegalizeResult 6463 LegalizerHelper::lowerMergeValues(MachineInstr &MI) { 6464 const unsigned NumOps = MI.getNumOperands(); 6465 Register DstReg = MI.getOperand(0).getReg(); 6466 Register Src0Reg = MI.getOperand(1).getReg(); 6467 LLT DstTy = MRI.getType(DstReg); 6468 LLT SrcTy = MRI.getType(Src0Reg); 6469 unsigned PartSize = SrcTy.getSizeInBits(); 6470 6471 LLT WideTy = LLT::scalar(DstTy.getSizeInBits()); 6472 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); 6473 6474 for (unsigned I = 2; I != NumOps; ++I) { 6475 const unsigned Offset = (I - 1) * PartSize; 6476 6477 Register SrcReg = MI.getOperand(I).getReg(); 6478 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 6479 6480 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 6481 MRI.createGenericVirtualRegister(WideTy); 6482 6483 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 6484 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 6485 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 6486 ResultReg = NextResult; 6487 } 6488 6489 if (DstTy.isPointer()) { 6490 if (MIRBuilder.getDataLayout().isNonIntegralAddressSpace( 6491 DstTy.getAddressSpace())) { 6492 LLVM_DEBUG(dbgs() << "Not casting nonintegral address space\n"); 6493 return UnableToLegalize; 6494 } 6495 6496 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 6497 } 6498 6499 MI.eraseFromParent(); 6500 return Legalized; 6501 } 6502 6503 LegalizerHelper::LegalizeResult 6504 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) { 6505 const unsigned NumDst = MI.getNumOperands() - 1; 6506 Register SrcReg = MI.getOperand(NumDst).getReg(); 6507 Register Dst0Reg = MI.getOperand(0).getReg(); 6508 LLT DstTy = MRI.getType(Dst0Reg); 6509 if (DstTy.isPointer()) 6510 return UnableToLegalize; // TODO 6511 6512 SrcReg = coerceToScalar(SrcReg); 6513 if (!SrcReg) 6514 return UnableToLegalize; 6515 6516 // Expand scalarizing unmerge as bitcast to integer and shift. 6517 LLT IntTy = MRI.getType(SrcReg); 6518 6519 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 6520 6521 const unsigned DstSize = DstTy.getSizeInBits(); 6522 unsigned Offset = DstSize; 6523 for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) { 6524 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset); 6525 auto Shift = MIRBuilder.buildLShr(IntTy, SrcReg, ShiftAmt); 6526 MIRBuilder.buildTrunc(MI.getOperand(I), Shift); 6527 } 6528 6529 MI.eraseFromParent(); 6530 return Legalized; 6531 } 6532 6533 /// Lower a vector extract or insert by writing the vector to a stack temporary 6534 /// and reloading the element or vector. 6535 /// 6536 /// %dst = G_EXTRACT_VECTOR_ELT %vec, %idx 6537 /// => 6538 /// %stack_temp = G_FRAME_INDEX 6539 /// G_STORE %vec, %stack_temp 6540 /// %idx = clamp(%idx, %vec.getNumElements()) 6541 /// %element_ptr = G_PTR_ADD %stack_temp, %idx 6542 /// %dst = G_LOAD %element_ptr 6543 LegalizerHelper::LegalizeResult 6544 LegalizerHelper::lowerExtractInsertVectorElt(MachineInstr &MI) { 6545 Register DstReg = MI.getOperand(0).getReg(); 6546 Register SrcVec = MI.getOperand(1).getReg(); 6547 Register InsertVal; 6548 if (MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT) 6549 InsertVal = MI.getOperand(2).getReg(); 6550 6551 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 6552 6553 LLT VecTy = MRI.getType(SrcVec); 6554 LLT EltTy = VecTy.getElementType(); 6555 if (!EltTy.isByteSized()) { // Not implemented. 6556 LLVM_DEBUG(dbgs() << "Can't handle non-byte element vectors yet\n"); 6557 return UnableToLegalize; 6558 } 6559 6560 unsigned EltBytes = EltTy.getSizeInBytes(); 6561 Align VecAlign = getStackTemporaryAlignment(VecTy); 6562 Align EltAlign; 6563 6564 MachinePointerInfo PtrInfo; 6565 auto StackTemp = createStackTemporary(TypeSize::Fixed(VecTy.getSizeInBytes()), 6566 VecAlign, PtrInfo); 6567 MIRBuilder.buildStore(SrcVec, StackTemp, PtrInfo, VecAlign); 6568 6569 // Get the pointer to the element, and be sure not to hit undefined behavior 6570 // if the index is out of bounds. 6571 Register EltPtr = getVectorElementPointer(StackTemp.getReg(0), VecTy, Idx); 6572 6573 int64_t IdxVal; 6574 if (mi_match(Idx, MRI, m_ICst(IdxVal))) { 6575 int64_t Offset = IdxVal * EltBytes; 6576 PtrInfo = PtrInfo.getWithOffset(Offset); 6577 EltAlign = commonAlignment(VecAlign, Offset); 6578 } else { 6579 // We lose information with a variable offset. 6580 EltAlign = getStackTemporaryAlignment(EltTy); 6581 PtrInfo = MachinePointerInfo(MRI.getType(EltPtr).getAddressSpace()); 6582 } 6583 6584 if (InsertVal) { 6585 // Write the inserted element 6586 MIRBuilder.buildStore(InsertVal, EltPtr, PtrInfo, EltAlign); 6587 6588 // Reload the whole vector. 6589 MIRBuilder.buildLoad(DstReg, StackTemp, PtrInfo, VecAlign); 6590 } else { 6591 MIRBuilder.buildLoad(DstReg, EltPtr, PtrInfo, EltAlign); 6592 } 6593 6594 MI.eraseFromParent(); 6595 return Legalized; 6596 } 6597 6598 LegalizerHelper::LegalizeResult 6599 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) { 6600 Register DstReg = MI.getOperand(0).getReg(); 6601 Register Src0Reg = MI.getOperand(1).getReg(); 6602 Register Src1Reg = MI.getOperand(2).getReg(); 6603 LLT Src0Ty = MRI.getType(Src0Reg); 6604 LLT DstTy = MRI.getType(DstReg); 6605 LLT IdxTy = LLT::scalar(32); 6606 6607 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 6608 6609 if (DstTy.isScalar()) { 6610 if (Src0Ty.isVector()) 6611 return UnableToLegalize; 6612 6613 // This is just a SELECT. 6614 assert(Mask.size() == 1 && "Expected a single mask element"); 6615 Register Val; 6616 if (Mask[0] < 0 || Mask[0] > 1) 6617 Val = MIRBuilder.buildUndef(DstTy).getReg(0); 6618 else 6619 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; 6620 MIRBuilder.buildCopy(DstReg, Val); 6621 MI.eraseFromParent(); 6622 return Legalized; 6623 } 6624 6625 Register Undef; 6626 SmallVector<Register, 32> BuildVec; 6627 LLT EltTy = DstTy.getElementType(); 6628 6629 for (int Idx : Mask) { 6630 if (Idx < 0) { 6631 if (!Undef.isValid()) 6632 Undef = MIRBuilder.buildUndef(EltTy).getReg(0); 6633 BuildVec.push_back(Undef); 6634 continue; 6635 } 6636 6637 if (Src0Ty.isScalar()) { 6638 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); 6639 } else { 6640 int NumElts = Src0Ty.getNumElements(); 6641 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; 6642 int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts; 6643 auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx); 6644 auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK); 6645 BuildVec.push_back(Extract.getReg(0)); 6646 } 6647 } 6648 6649 MIRBuilder.buildBuildVector(DstReg, BuildVec); 6650 MI.eraseFromParent(); 6651 return Legalized; 6652 } 6653 6654 LegalizerHelper::LegalizeResult 6655 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) { 6656 const auto &MF = *MI.getMF(); 6657 const auto &TFI = *MF.getSubtarget().getFrameLowering(); 6658 if (TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp) 6659 return UnableToLegalize; 6660 6661 Register Dst = MI.getOperand(0).getReg(); 6662 Register AllocSize = MI.getOperand(1).getReg(); 6663 Align Alignment = assumeAligned(MI.getOperand(2).getImm()); 6664 6665 LLT PtrTy = MRI.getType(Dst); 6666 LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits()); 6667 6668 Register SPReg = TLI.getStackPointerRegisterToSaveRestore(); 6669 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); 6670 SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp); 6671 6672 // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't 6673 // have to generate an extra instruction to negate the alloc and then use 6674 // G_PTR_ADD to add the negative offset. 6675 auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize); 6676 if (Alignment > Align(1)) { 6677 APInt AlignMask(IntPtrTy.getSizeInBits(), Alignment.value(), true); 6678 AlignMask.negate(); 6679 auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask); 6680 Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst); 6681 } 6682 6683 SPTmp = MIRBuilder.buildCast(PtrTy, Alloc); 6684 MIRBuilder.buildCopy(SPReg, SPTmp); 6685 MIRBuilder.buildCopy(Dst, SPTmp); 6686 6687 MI.eraseFromParent(); 6688 return Legalized; 6689 } 6690 6691 LegalizerHelper::LegalizeResult 6692 LegalizerHelper::lowerExtract(MachineInstr &MI) { 6693 Register Dst = MI.getOperand(0).getReg(); 6694 Register Src = MI.getOperand(1).getReg(); 6695 unsigned Offset = MI.getOperand(2).getImm(); 6696 6697 LLT DstTy = MRI.getType(Dst); 6698 LLT SrcTy = MRI.getType(Src); 6699 6700 if (DstTy.isScalar() && 6701 (SrcTy.isScalar() || 6702 (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) { 6703 LLT SrcIntTy = SrcTy; 6704 if (!SrcTy.isScalar()) { 6705 SrcIntTy = LLT::scalar(SrcTy.getSizeInBits()); 6706 Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0); 6707 } 6708 6709 if (Offset == 0) 6710 MIRBuilder.buildTrunc(Dst, Src); 6711 else { 6712 auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset); 6713 auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt); 6714 MIRBuilder.buildTrunc(Dst, Shr); 6715 } 6716 6717 MI.eraseFromParent(); 6718 return Legalized; 6719 } 6720 6721 return UnableToLegalize; 6722 } 6723 6724 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) { 6725 Register Dst = MI.getOperand(0).getReg(); 6726 Register Src = MI.getOperand(1).getReg(); 6727 Register InsertSrc = MI.getOperand(2).getReg(); 6728 uint64_t Offset = MI.getOperand(3).getImm(); 6729 6730 LLT DstTy = MRI.getType(Src); 6731 LLT InsertTy = MRI.getType(InsertSrc); 6732 6733 if (InsertTy.isVector() || 6734 (DstTy.isVector() && DstTy.getElementType() != InsertTy)) 6735 return UnableToLegalize; 6736 6737 const DataLayout &DL = MIRBuilder.getDataLayout(); 6738 if ((DstTy.isPointer() && 6739 DL.isNonIntegralAddressSpace(DstTy.getAddressSpace())) || 6740 (InsertTy.isPointer() && 6741 DL.isNonIntegralAddressSpace(InsertTy.getAddressSpace()))) { 6742 LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n"); 6743 return UnableToLegalize; 6744 } 6745 6746 LLT IntDstTy = DstTy; 6747 6748 if (!DstTy.isScalar()) { 6749 IntDstTy = LLT::scalar(DstTy.getSizeInBits()); 6750 Src = MIRBuilder.buildCast(IntDstTy, Src).getReg(0); 6751 } 6752 6753 if (!InsertTy.isScalar()) { 6754 const LLT IntInsertTy = LLT::scalar(InsertTy.getSizeInBits()); 6755 InsertSrc = MIRBuilder.buildPtrToInt(IntInsertTy, InsertSrc).getReg(0); 6756 } 6757 6758 Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0); 6759 if (Offset != 0) { 6760 auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset); 6761 ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0); 6762 } 6763 6764 APInt MaskVal = APInt::getBitsSetWithWrap( 6765 DstTy.getSizeInBits(), Offset + InsertTy.getSizeInBits(), Offset); 6766 6767 auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal); 6768 auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask); 6769 auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc); 6770 6771 MIRBuilder.buildCast(Dst, Or); 6772 MI.eraseFromParent(); 6773 return Legalized; 6774 } 6775 6776 LegalizerHelper::LegalizeResult 6777 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) { 6778 Register Dst0 = MI.getOperand(0).getReg(); 6779 Register Dst1 = MI.getOperand(1).getReg(); 6780 Register LHS = MI.getOperand(2).getReg(); 6781 Register RHS = MI.getOperand(3).getReg(); 6782 const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO; 6783 6784 LLT Ty = MRI.getType(Dst0); 6785 LLT BoolTy = MRI.getType(Dst1); 6786 6787 if (IsAdd) 6788 MIRBuilder.buildAdd(Dst0, LHS, RHS); 6789 else 6790 MIRBuilder.buildSub(Dst0, LHS, RHS); 6791 6792 // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow. 6793 6794 auto Zero = MIRBuilder.buildConstant(Ty, 0); 6795 6796 // For an addition, the result should be less than one of the operands (LHS) 6797 // if and only if the other operand (RHS) is negative, otherwise there will 6798 // be overflow. 6799 // For a subtraction, the result should be less than one of the operands 6800 // (LHS) if and only if the other operand (RHS) is (non-zero) positive, 6801 // otherwise there will be overflow. 6802 auto ResultLowerThanLHS = 6803 MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS); 6804 auto ConditionRHS = MIRBuilder.buildICmp( 6805 IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero); 6806 6807 MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS); 6808 MI.eraseFromParent(); 6809 return Legalized; 6810 } 6811 6812 LegalizerHelper::LegalizeResult 6813 LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI) { 6814 Register Res = MI.getOperand(0).getReg(); 6815 Register LHS = MI.getOperand(1).getReg(); 6816 Register RHS = MI.getOperand(2).getReg(); 6817 LLT Ty = MRI.getType(Res); 6818 bool IsSigned; 6819 bool IsAdd; 6820 unsigned BaseOp; 6821 switch (MI.getOpcode()) { 6822 default: 6823 llvm_unreachable("unexpected addsat/subsat opcode"); 6824 case TargetOpcode::G_UADDSAT: 6825 IsSigned = false; 6826 IsAdd = true; 6827 BaseOp = TargetOpcode::G_ADD; 6828 break; 6829 case TargetOpcode::G_SADDSAT: 6830 IsSigned = true; 6831 IsAdd = true; 6832 BaseOp = TargetOpcode::G_ADD; 6833 break; 6834 case TargetOpcode::G_USUBSAT: 6835 IsSigned = false; 6836 IsAdd = false; 6837 BaseOp = TargetOpcode::G_SUB; 6838 break; 6839 case TargetOpcode::G_SSUBSAT: 6840 IsSigned = true; 6841 IsAdd = false; 6842 BaseOp = TargetOpcode::G_SUB; 6843 break; 6844 } 6845 6846 if (IsSigned) { 6847 // sadd.sat(a, b) -> 6848 // hi = 0x7fffffff - smax(a, 0) 6849 // lo = 0x80000000 - smin(a, 0) 6850 // a + smin(smax(lo, b), hi) 6851 // ssub.sat(a, b) -> 6852 // lo = smax(a, -1) - 0x7fffffff 6853 // hi = smin(a, -1) - 0x80000000 6854 // a - smin(smax(lo, b), hi) 6855 // TODO: AMDGPU can use a "median of 3" instruction here: 6856 // a +/- med3(lo, b, hi) 6857 uint64_t NumBits = Ty.getScalarSizeInBits(); 6858 auto MaxVal = 6859 MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(NumBits)); 6860 auto MinVal = 6861 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6862 MachineInstrBuilder Hi, Lo; 6863 if (IsAdd) { 6864 auto Zero = MIRBuilder.buildConstant(Ty, 0); 6865 Hi = MIRBuilder.buildSub(Ty, MaxVal, MIRBuilder.buildSMax(Ty, LHS, Zero)); 6866 Lo = MIRBuilder.buildSub(Ty, MinVal, MIRBuilder.buildSMin(Ty, LHS, Zero)); 6867 } else { 6868 auto NegOne = MIRBuilder.buildConstant(Ty, -1); 6869 Lo = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMax(Ty, LHS, NegOne), 6870 MaxVal); 6871 Hi = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMin(Ty, LHS, NegOne), 6872 MinVal); 6873 } 6874 auto RHSClamped = 6875 MIRBuilder.buildSMin(Ty, MIRBuilder.buildSMax(Ty, Lo, RHS), Hi); 6876 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped}); 6877 } else { 6878 // uadd.sat(a, b) -> a + umin(~a, b) 6879 // usub.sat(a, b) -> a - umin(a, b) 6880 Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS; 6881 auto Min = MIRBuilder.buildUMin(Ty, Not, RHS); 6882 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min}); 6883 } 6884 6885 MI.eraseFromParent(); 6886 return Legalized; 6887 } 6888 6889 LegalizerHelper::LegalizeResult 6890 LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) { 6891 Register Res = MI.getOperand(0).getReg(); 6892 Register LHS = MI.getOperand(1).getReg(); 6893 Register RHS = MI.getOperand(2).getReg(); 6894 LLT Ty = MRI.getType(Res); 6895 LLT BoolTy = Ty.changeElementSize(1); 6896 bool IsSigned; 6897 bool IsAdd; 6898 unsigned OverflowOp; 6899 switch (MI.getOpcode()) { 6900 default: 6901 llvm_unreachable("unexpected addsat/subsat opcode"); 6902 case TargetOpcode::G_UADDSAT: 6903 IsSigned = false; 6904 IsAdd = true; 6905 OverflowOp = TargetOpcode::G_UADDO; 6906 break; 6907 case TargetOpcode::G_SADDSAT: 6908 IsSigned = true; 6909 IsAdd = true; 6910 OverflowOp = TargetOpcode::G_SADDO; 6911 break; 6912 case TargetOpcode::G_USUBSAT: 6913 IsSigned = false; 6914 IsAdd = false; 6915 OverflowOp = TargetOpcode::G_USUBO; 6916 break; 6917 case TargetOpcode::G_SSUBSAT: 6918 IsSigned = true; 6919 IsAdd = false; 6920 OverflowOp = TargetOpcode::G_SSUBO; 6921 break; 6922 } 6923 6924 auto OverflowRes = 6925 MIRBuilder.buildInstr(OverflowOp, {Ty, BoolTy}, {LHS, RHS}); 6926 Register Tmp = OverflowRes.getReg(0); 6927 Register Ov = OverflowRes.getReg(1); 6928 MachineInstrBuilder Clamp; 6929 if (IsSigned) { 6930 // sadd.sat(a, b) -> 6931 // {tmp, ov} = saddo(a, b) 6932 // ov ? (tmp >>s 31) + 0x80000000 : r 6933 // ssub.sat(a, b) -> 6934 // {tmp, ov} = ssubo(a, b) 6935 // ov ? (tmp >>s 31) + 0x80000000 : r 6936 uint64_t NumBits = Ty.getScalarSizeInBits(); 6937 auto ShiftAmount = MIRBuilder.buildConstant(Ty, NumBits - 1); 6938 auto Sign = MIRBuilder.buildAShr(Ty, Tmp, ShiftAmount); 6939 auto MinVal = 6940 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6941 Clamp = MIRBuilder.buildAdd(Ty, Sign, MinVal); 6942 } else { 6943 // uadd.sat(a, b) -> 6944 // {tmp, ov} = uaddo(a, b) 6945 // ov ? 0xffffffff : tmp 6946 // usub.sat(a, b) -> 6947 // {tmp, ov} = usubo(a, b) 6948 // ov ? 0 : tmp 6949 Clamp = MIRBuilder.buildConstant(Ty, IsAdd ? -1 : 0); 6950 } 6951 MIRBuilder.buildSelect(Res, Ov, Clamp, Tmp); 6952 6953 MI.eraseFromParent(); 6954 return Legalized; 6955 } 6956 6957 LegalizerHelper::LegalizeResult 6958 LegalizerHelper::lowerShlSat(MachineInstr &MI) { 6959 assert((MI.getOpcode() == TargetOpcode::G_SSHLSAT || 6960 MI.getOpcode() == TargetOpcode::G_USHLSAT) && 6961 "Expected shlsat opcode!"); 6962 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SSHLSAT; 6963 Register Res = MI.getOperand(0).getReg(); 6964 Register LHS = MI.getOperand(1).getReg(); 6965 Register RHS = MI.getOperand(2).getReg(); 6966 LLT Ty = MRI.getType(Res); 6967 LLT BoolTy = Ty.changeElementSize(1); 6968 6969 unsigned BW = Ty.getScalarSizeInBits(); 6970 auto Result = MIRBuilder.buildShl(Ty, LHS, RHS); 6971 auto Orig = IsSigned ? MIRBuilder.buildAShr(Ty, Result, RHS) 6972 : MIRBuilder.buildLShr(Ty, Result, RHS); 6973 6974 MachineInstrBuilder SatVal; 6975 if (IsSigned) { 6976 auto SatMin = MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(BW)); 6977 auto SatMax = MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(BW)); 6978 auto Cmp = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, LHS, 6979 MIRBuilder.buildConstant(Ty, 0)); 6980 SatVal = MIRBuilder.buildSelect(Ty, Cmp, SatMin, SatMax); 6981 } else { 6982 SatVal = MIRBuilder.buildConstant(Ty, APInt::getMaxValue(BW)); 6983 } 6984 auto Ov = MIRBuilder.buildICmp(CmpInst::ICMP_NE, BoolTy, LHS, Orig); 6985 MIRBuilder.buildSelect(Res, Ov, SatVal, Result); 6986 6987 MI.eraseFromParent(); 6988 return Legalized; 6989 } 6990 6991 LegalizerHelper::LegalizeResult 6992 LegalizerHelper::lowerBswap(MachineInstr &MI) { 6993 Register Dst = MI.getOperand(0).getReg(); 6994 Register Src = MI.getOperand(1).getReg(); 6995 const LLT Ty = MRI.getType(Src); 6996 unsigned SizeInBytes = (Ty.getScalarSizeInBits() + 7) / 8; 6997 unsigned BaseShiftAmt = (SizeInBytes - 1) * 8; 6998 6999 // Swap most and least significant byte, set remaining bytes in Res to zero. 7000 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt); 7001 auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt); 7002 auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 7003 auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft); 7004 7005 // Set i-th high/low byte in Res to i-th low/high byte from Src. 7006 for (unsigned i = 1; i < SizeInBytes / 2; ++i) { 7007 // AND with Mask leaves byte i unchanged and sets remaining bytes to 0. 7008 APInt APMask(SizeInBytes * 8, 0xFF << (i * 8)); 7009 auto Mask = MIRBuilder.buildConstant(Ty, APMask); 7010 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i); 7011 // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt. 7012 auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask); 7013 auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt); 7014 Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft); 7015 // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask. 7016 auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 7017 auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask); 7018 Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight); 7019 } 7020 Res.getInstr()->getOperand(0).setReg(Dst); 7021 7022 MI.eraseFromParent(); 7023 return Legalized; 7024 } 7025 7026 //{ (Src & Mask) >> N } | { (Src << N) & Mask } 7027 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B, 7028 MachineInstrBuilder Src, APInt Mask) { 7029 const LLT Ty = Dst.getLLTTy(*B.getMRI()); 7030 MachineInstrBuilder C_N = B.buildConstant(Ty, N); 7031 MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask); 7032 auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N); 7033 auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0); 7034 return B.buildOr(Dst, LHS, RHS); 7035 } 7036 7037 LegalizerHelper::LegalizeResult 7038 LegalizerHelper::lowerBitreverse(MachineInstr &MI) { 7039 Register Dst = MI.getOperand(0).getReg(); 7040 Register Src = MI.getOperand(1).getReg(); 7041 const LLT Ty = MRI.getType(Src); 7042 unsigned Size = Ty.getSizeInBits(); 7043 7044 MachineInstrBuilder BSWAP = 7045 MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src}); 7046 7047 // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654 7048 // [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4] 7049 // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0] 7050 MachineInstrBuilder Swap4 = 7051 SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0))); 7052 7053 // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76 7054 // [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2] 7055 // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC] 7056 MachineInstrBuilder Swap2 = 7057 SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC))); 7058 7059 // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7 7060 // [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1] 7061 // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA] 7062 SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA))); 7063 7064 MI.eraseFromParent(); 7065 return Legalized; 7066 } 7067 7068 LegalizerHelper::LegalizeResult 7069 LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) { 7070 MachineFunction &MF = MIRBuilder.getMF(); 7071 7072 bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER; 7073 int NameOpIdx = IsRead ? 1 : 0; 7074 int ValRegIndex = IsRead ? 0 : 1; 7075 7076 Register ValReg = MI.getOperand(ValRegIndex).getReg(); 7077 const LLT Ty = MRI.getType(ValReg); 7078 const MDString *RegStr = cast<MDString>( 7079 cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0)); 7080 7081 Register PhysReg = TLI.getRegisterByName(RegStr->getString().data(), Ty, MF); 7082 if (!PhysReg.isValid()) 7083 return UnableToLegalize; 7084 7085 if (IsRead) 7086 MIRBuilder.buildCopy(ValReg, PhysReg); 7087 else 7088 MIRBuilder.buildCopy(PhysReg, ValReg); 7089 7090 MI.eraseFromParent(); 7091 return Legalized; 7092 } 7093 7094 LegalizerHelper::LegalizeResult 7095 LegalizerHelper::lowerSMULH_UMULH(MachineInstr &MI) { 7096 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULH; 7097 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 7098 Register Result = MI.getOperand(0).getReg(); 7099 LLT OrigTy = MRI.getType(Result); 7100 auto SizeInBits = OrigTy.getScalarSizeInBits(); 7101 LLT WideTy = OrigTy.changeElementSize(SizeInBits * 2); 7102 7103 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)}); 7104 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)}); 7105 auto Mul = MIRBuilder.buildMul(WideTy, LHS, RHS); 7106 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; 7107 7108 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, SizeInBits); 7109 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); 7110 MIRBuilder.buildTrunc(Result, Shifted); 7111 7112 MI.eraseFromParent(); 7113 return Legalized; 7114 } 7115 7116 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) { 7117 // Implement vector G_SELECT in terms of XOR, AND, OR. 7118 Register DstReg = MI.getOperand(0).getReg(); 7119 Register MaskReg = MI.getOperand(1).getReg(); 7120 Register Op1Reg = MI.getOperand(2).getReg(); 7121 Register Op2Reg = MI.getOperand(3).getReg(); 7122 LLT DstTy = MRI.getType(DstReg); 7123 LLT MaskTy = MRI.getType(MaskReg); 7124 LLT Op1Ty = MRI.getType(Op1Reg); 7125 if (!DstTy.isVector()) 7126 return UnableToLegalize; 7127 7128 // Vector selects can have a scalar predicate. If so, splat into a vector and 7129 // finish for later legalization attempts to try again. 7130 if (MaskTy.isScalar()) { 7131 Register MaskElt = MaskReg; 7132 if (MaskTy.getSizeInBits() < DstTy.getScalarSizeInBits()) 7133 MaskElt = MIRBuilder.buildSExt(DstTy.getElementType(), MaskElt).getReg(0); 7134 // Generate a vector splat idiom to be pattern matched later. 7135 auto ShufSplat = MIRBuilder.buildShuffleSplat(DstTy, MaskElt); 7136 Observer.changingInstr(MI); 7137 MI.getOperand(1).setReg(ShufSplat.getReg(0)); 7138 Observer.changedInstr(MI); 7139 return Legalized; 7140 } 7141 7142 if (MaskTy.getSizeInBits() != Op1Ty.getSizeInBits()) { 7143 return UnableToLegalize; 7144 } 7145 7146 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); 7147 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); 7148 auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask); 7149 MIRBuilder.buildOr(DstReg, NewOp1, NewOp2); 7150 MI.eraseFromParent(); 7151 return Legalized; 7152 } 7153 7154 LegalizerHelper::LegalizeResult LegalizerHelper::lowerDIVREM(MachineInstr &MI) { 7155 // Split DIVREM into individual instructions. 7156 unsigned Opcode = MI.getOpcode(); 7157 7158 MIRBuilder.buildInstr( 7159 Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SDIV 7160 : TargetOpcode::G_UDIV, 7161 {MI.getOperand(0).getReg()}, {MI.getOperand(2), MI.getOperand(3)}); 7162 MIRBuilder.buildInstr( 7163 Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SREM 7164 : TargetOpcode::G_UREM, 7165 {MI.getOperand(1).getReg()}, {MI.getOperand(2), MI.getOperand(3)}); 7166 MI.eraseFromParent(); 7167 return Legalized; 7168 } 7169 7170 LegalizerHelper::LegalizeResult 7171 LegalizerHelper::lowerAbsToAddXor(MachineInstr &MI) { 7172 // Expand %res = G_ABS %a into: 7173 // %v1 = G_ASHR %a, scalar_size-1 7174 // %v2 = G_ADD %a, %v1 7175 // %res = G_XOR %v2, %v1 7176 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 7177 Register OpReg = MI.getOperand(1).getReg(); 7178 auto ShiftAmt = 7179 MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - 1); 7180 auto Shift = MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt); 7181 auto Add = MIRBuilder.buildAdd(DstTy, OpReg, Shift); 7182 MIRBuilder.buildXor(MI.getOperand(0).getReg(), Add, Shift); 7183 MI.eraseFromParent(); 7184 return Legalized; 7185 } 7186 7187 LegalizerHelper::LegalizeResult 7188 LegalizerHelper::lowerAbsToMaxNeg(MachineInstr &MI) { 7189 // Expand %res = G_ABS %a into: 7190 // %v1 = G_CONSTANT 0 7191 // %v2 = G_SUB %v1, %a 7192 // %res = G_SMAX %a, %v2 7193 Register SrcReg = MI.getOperand(1).getReg(); 7194 LLT Ty = MRI.getType(SrcReg); 7195 auto Zero = MIRBuilder.buildConstant(Ty, 0).getReg(0); 7196 auto Sub = MIRBuilder.buildSub(Ty, Zero, SrcReg).getReg(0); 7197 MIRBuilder.buildSMax(MI.getOperand(0), SrcReg, Sub); 7198 MI.eraseFromParent(); 7199 return Legalized; 7200 } 7201