1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetFrameLowering.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/CodeGen/TargetLowering.h"
24 #include "llvm/CodeGen/TargetSubtargetInfo.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Support/raw_ostream.h"
28 
29 #define DEBUG_TYPE "legalizer"
30 
31 using namespace llvm;
32 using namespace LegalizeActions;
33 using namespace MIPatternMatch;
34 
35 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
36 ///
37 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
38 /// with any leftover piece as type \p LeftoverTy
39 ///
40 /// Returns -1 in the first element of the pair if the breakdown is not
41 /// satisfiable.
42 static std::pair<int, int>
43 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
44   assert(!LeftoverTy.isValid() && "this is an out argument");
45 
46   unsigned Size = OrigTy.getSizeInBits();
47   unsigned NarrowSize = NarrowTy.getSizeInBits();
48   unsigned NumParts = Size / NarrowSize;
49   unsigned LeftoverSize = Size - NumParts * NarrowSize;
50   assert(Size > NarrowSize);
51 
52   if (LeftoverSize == 0)
53     return {NumParts, 0};
54 
55   if (NarrowTy.isVector()) {
56     unsigned EltSize = OrigTy.getScalarSizeInBits();
57     if (LeftoverSize % EltSize != 0)
58       return {-1, -1};
59     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
60   } else {
61     LeftoverTy = LLT::scalar(LeftoverSize);
62   }
63 
64   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
65   return std::make_pair(NumParts, NumLeftover);
66 }
67 
68 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) {
69 
70   if (!Ty.isScalar())
71     return nullptr;
72 
73   switch (Ty.getSizeInBits()) {
74   case 16:
75     return Type::getHalfTy(Ctx);
76   case 32:
77     return Type::getFloatTy(Ctx);
78   case 64:
79     return Type::getDoubleTy(Ctx);
80   case 80:
81     return Type::getX86_FP80Ty(Ctx);
82   case 128:
83     return Type::getFP128Ty(Ctx);
84   default:
85     return nullptr;
86   }
87 }
88 
89 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
90                                  GISelChangeObserver &Observer,
91                                  MachineIRBuilder &Builder)
92     : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()),
93       LI(*MF.getSubtarget().getLegalizerInfo()) {
94   MIRBuilder.setChangeObserver(Observer);
95 }
96 
97 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
98                                  GISelChangeObserver &Observer,
99                                  MachineIRBuilder &B)
100     : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI) {
101   MIRBuilder.setChangeObserver(Observer);
102 }
103 LegalizerHelper::LegalizeResult
104 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
105   LLVM_DEBUG(dbgs() << "Legalizing: " << MI);
106 
107   MIRBuilder.setInstrAndDebugLoc(MI);
108 
109   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
110       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
111     return LI.legalizeIntrinsic(*this, MI) ? Legalized : UnableToLegalize;
112   auto Step = LI.getAction(MI, MRI);
113   switch (Step.Action) {
114   case Legal:
115     LLVM_DEBUG(dbgs() << ".. Already legal\n");
116     return AlreadyLegal;
117   case Libcall:
118     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
119     return libcall(MI);
120   case NarrowScalar:
121     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
122     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
123   case WidenScalar:
124     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
125     return widenScalar(MI, Step.TypeIdx, Step.NewType);
126   case Bitcast:
127     LLVM_DEBUG(dbgs() << ".. Bitcast type\n");
128     return bitcast(MI, Step.TypeIdx, Step.NewType);
129   case Lower:
130     LLVM_DEBUG(dbgs() << ".. Lower\n");
131     return lower(MI, Step.TypeIdx, Step.NewType);
132   case FewerElements:
133     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
134     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
135   case MoreElements:
136     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
137     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
138   case Custom:
139     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
140     return LI.legalizeCustom(*this, MI) ? Legalized : UnableToLegalize;
141   default:
142     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
143     return UnableToLegalize;
144   }
145 }
146 
147 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
148                                    SmallVectorImpl<Register> &VRegs) {
149   for (int i = 0; i < NumParts; ++i)
150     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
151   MIRBuilder.buildUnmerge(VRegs, Reg);
152 }
153 
154 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
155                                    LLT MainTy, LLT &LeftoverTy,
156                                    SmallVectorImpl<Register> &VRegs,
157                                    SmallVectorImpl<Register> &LeftoverRegs) {
158   assert(!LeftoverTy.isValid() && "this is an out argument");
159 
160   unsigned RegSize = RegTy.getSizeInBits();
161   unsigned MainSize = MainTy.getSizeInBits();
162   unsigned NumParts = RegSize / MainSize;
163   unsigned LeftoverSize = RegSize - NumParts * MainSize;
164 
165   // Use an unmerge when possible.
166   if (LeftoverSize == 0) {
167     for (unsigned I = 0; I < NumParts; ++I)
168       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
169     MIRBuilder.buildUnmerge(VRegs, Reg);
170     return true;
171   }
172 
173   if (MainTy.isVector()) {
174     unsigned EltSize = MainTy.getScalarSizeInBits();
175     if (LeftoverSize % EltSize != 0)
176       return false;
177     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
178   } else {
179     LeftoverTy = LLT::scalar(LeftoverSize);
180   }
181 
182   // For irregular sizes, extract the individual parts.
183   for (unsigned I = 0; I != NumParts; ++I) {
184     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
185     VRegs.push_back(NewReg);
186     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
187   }
188 
189   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
190        Offset += LeftoverSize) {
191     Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
192     LeftoverRegs.push_back(NewReg);
193     MIRBuilder.buildExtract(NewReg, Reg, Offset);
194   }
195 
196   return true;
197 }
198 
199 void LegalizerHelper::insertParts(Register DstReg,
200                                   LLT ResultTy, LLT PartTy,
201                                   ArrayRef<Register> PartRegs,
202                                   LLT LeftoverTy,
203                                   ArrayRef<Register> LeftoverRegs) {
204   if (!LeftoverTy.isValid()) {
205     assert(LeftoverRegs.empty());
206 
207     if (!ResultTy.isVector()) {
208       MIRBuilder.buildMerge(DstReg, PartRegs);
209       return;
210     }
211 
212     if (PartTy.isVector())
213       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
214     else
215       MIRBuilder.buildBuildVector(DstReg, PartRegs);
216     return;
217   }
218 
219   unsigned PartSize = PartTy.getSizeInBits();
220   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
221 
222   Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
223   MIRBuilder.buildUndef(CurResultReg);
224 
225   unsigned Offset = 0;
226   for (Register PartReg : PartRegs) {
227     Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
228     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
229     CurResultReg = NewResultReg;
230     Offset += PartSize;
231   }
232 
233   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
234     // Use the original output register for the final insert to avoid a copy.
235     Register NewResultReg = (I + 1 == E) ?
236       DstReg : MRI.createGenericVirtualRegister(ResultTy);
237 
238     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
239     CurResultReg = NewResultReg;
240     Offset += LeftoverPartSize;
241   }
242 }
243 
244 /// Return the result registers of G_UNMERGE_VALUES \p MI in \p Regs
245 static void getUnmergeResults(SmallVectorImpl<Register> &Regs,
246                               const MachineInstr &MI) {
247   assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES);
248 
249   const int NumResults = MI.getNumOperands() - 1;
250   Regs.resize(NumResults);
251   for (int I = 0; I != NumResults; ++I)
252     Regs[I] = MI.getOperand(I).getReg();
253 }
254 
255 LLT LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy,
256                                     LLT NarrowTy, Register SrcReg) {
257   LLT SrcTy = MRI.getType(SrcReg);
258 
259   LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy);
260   if (SrcTy == GCDTy) {
261     // If the source already evenly divides the result type, we don't need to do
262     // anything.
263     Parts.push_back(SrcReg);
264   } else {
265     // Need to split into common type sized pieces.
266     auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
267     getUnmergeResults(Parts, *Unmerge);
268   }
269 
270   return GCDTy;
271 }
272 
273 LLT LegalizerHelper::buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy,
274                                          SmallVectorImpl<Register> &VRegs,
275                                          unsigned PadStrategy) {
276   LLT LCMTy = getLCMType(DstTy, NarrowTy);
277 
278   int NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits();
279   int NumSubParts = NarrowTy.getSizeInBits() / GCDTy.getSizeInBits();
280   int NumOrigSrc = VRegs.size();
281 
282   Register PadReg;
283 
284   // Get a value we can use to pad the source value if the sources won't evenly
285   // cover the result type.
286   if (NumOrigSrc < NumParts * NumSubParts) {
287     if (PadStrategy == TargetOpcode::G_ZEXT)
288       PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0);
289     else if (PadStrategy == TargetOpcode::G_ANYEXT)
290       PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
291     else {
292       assert(PadStrategy == TargetOpcode::G_SEXT);
293 
294       // Shift the sign bit of the low register through the high register.
295       auto ShiftAmt =
296         MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1);
297       PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0);
298     }
299   }
300 
301   // Registers for the final merge to be produced.
302   SmallVector<Register, 4> Remerge(NumParts);
303 
304   // Registers needed for intermediate merges, which will be merged into a
305   // source for Remerge.
306   SmallVector<Register, 4> SubMerge(NumSubParts);
307 
308   // Once we've fully read off the end of the original source bits, we can reuse
309   // the same high bits for remaining padding elements.
310   Register AllPadReg;
311 
312   // Build merges to the LCM type to cover the original result type.
313   for (int I = 0; I != NumParts; ++I) {
314     bool AllMergePartsArePadding = true;
315 
316     // Build the requested merges to the requested type.
317     for (int J = 0; J != NumSubParts; ++J) {
318       int Idx = I * NumSubParts + J;
319       if (Idx >= NumOrigSrc) {
320         SubMerge[J] = PadReg;
321         continue;
322       }
323 
324       SubMerge[J] = VRegs[Idx];
325 
326       // There are meaningful bits here we can't reuse later.
327       AllMergePartsArePadding = false;
328     }
329 
330     // If we've filled up a complete piece with padding bits, we can directly
331     // emit the natural sized constant if applicable, rather than a merge of
332     // smaller constants.
333     if (AllMergePartsArePadding && !AllPadReg) {
334       if (PadStrategy == TargetOpcode::G_ANYEXT)
335         AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0);
336       else if (PadStrategy == TargetOpcode::G_ZEXT)
337         AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0);
338 
339       // If this is a sign extension, we can't materialize a trivial constant
340       // with the right type and have to produce a merge.
341     }
342 
343     if (AllPadReg) {
344       // Avoid creating additional instructions if we're just adding additional
345       // copies of padding bits.
346       Remerge[I] = AllPadReg;
347       continue;
348     }
349 
350     if (NumSubParts == 1)
351       Remerge[I] = SubMerge[0];
352     else
353       Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0);
354 
355     // In the sign extend padding case, re-use the first all-signbit merge.
356     if (AllMergePartsArePadding && !AllPadReg)
357       AllPadReg = Remerge[I];
358   }
359 
360   VRegs = std::move(Remerge);
361   return LCMTy;
362 }
363 
364 void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy,
365                                                ArrayRef<Register> RemergeRegs) {
366   LLT DstTy = MRI.getType(DstReg);
367 
368   // Create the merge to the widened source, and extract the relevant bits into
369   // the result.
370 
371   if (DstTy == LCMTy) {
372     MIRBuilder.buildMerge(DstReg, RemergeRegs);
373     return;
374   }
375 
376   auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs);
377   if (DstTy.isScalar() && LCMTy.isScalar()) {
378     MIRBuilder.buildTrunc(DstReg, Remerge);
379     return;
380   }
381 
382   if (LCMTy.isVector()) {
383     MIRBuilder.buildExtract(DstReg, Remerge, 0);
384     return;
385   }
386 
387   llvm_unreachable("unhandled case");
388 }
389 
390 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
391 #define RTLIBCASE_INT(LibcallPrefix)                                           \
392   do {                                                                         \
393     switch (Size) {                                                            \
394     case 32:                                                                   \
395       return RTLIB::LibcallPrefix##32;                                         \
396     case 64:                                                                   \
397       return RTLIB::LibcallPrefix##64;                                         \
398     case 128:                                                                  \
399       return RTLIB::LibcallPrefix##128;                                        \
400     default:                                                                   \
401       llvm_unreachable("unexpected size");                                     \
402     }                                                                          \
403   } while (0)
404 
405 #define RTLIBCASE(LibcallPrefix)                                               \
406   do {                                                                         \
407     switch (Size) {                                                            \
408     case 32:                                                                   \
409       return RTLIB::LibcallPrefix##32;                                         \
410     case 64:                                                                   \
411       return RTLIB::LibcallPrefix##64;                                         \
412     case 80:                                                                   \
413       return RTLIB::LibcallPrefix##80;                                         \
414     case 128:                                                                  \
415       return RTLIB::LibcallPrefix##128;                                        \
416     default:                                                                   \
417       llvm_unreachable("unexpected size");                                     \
418     }                                                                          \
419   } while (0)
420 
421   switch (Opcode) {
422   case TargetOpcode::G_SDIV:
423     RTLIBCASE_INT(SDIV_I);
424   case TargetOpcode::G_UDIV:
425     RTLIBCASE_INT(UDIV_I);
426   case TargetOpcode::G_SREM:
427     RTLIBCASE_INT(SREM_I);
428   case TargetOpcode::G_UREM:
429     RTLIBCASE_INT(UREM_I);
430   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
431     RTLIBCASE_INT(CTLZ_I);
432   case TargetOpcode::G_FADD:
433     RTLIBCASE(ADD_F);
434   case TargetOpcode::G_FSUB:
435     RTLIBCASE(SUB_F);
436   case TargetOpcode::G_FMUL:
437     RTLIBCASE(MUL_F);
438   case TargetOpcode::G_FDIV:
439     RTLIBCASE(DIV_F);
440   case TargetOpcode::G_FEXP:
441     RTLIBCASE(EXP_F);
442   case TargetOpcode::G_FEXP2:
443     RTLIBCASE(EXP2_F);
444   case TargetOpcode::G_FREM:
445     RTLIBCASE(REM_F);
446   case TargetOpcode::G_FPOW:
447     RTLIBCASE(POW_F);
448   case TargetOpcode::G_FMA:
449     RTLIBCASE(FMA_F);
450   case TargetOpcode::G_FSIN:
451     RTLIBCASE(SIN_F);
452   case TargetOpcode::G_FCOS:
453     RTLIBCASE(COS_F);
454   case TargetOpcode::G_FLOG10:
455     RTLIBCASE(LOG10_F);
456   case TargetOpcode::G_FLOG:
457     RTLIBCASE(LOG_F);
458   case TargetOpcode::G_FLOG2:
459     RTLIBCASE(LOG2_F);
460   case TargetOpcode::G_FCEIL:
461     RTLIBCASE(CEIL_F);
462   case TargetOpcode::G_FFLOOR:
463     RTLIBCASE(FLOOR_F);
464   case TargetOpcode::G_FMINNUM:
465     RTLIBCASE(FMIN_F);
466   case TargetOpcode::G_FMAXNUM:
467     RTLIBCASE(FMAX_F);
468   case TargetOpcode::G_FSQRT:
469     RTLIBCASE(SQRT_F);
470   case TargetOpcode::G_FRINT:
471     RTLIBCASE(RINT_F);
472   case TargetOpcode::G_FNEARBYINT:
473     RTLIBCASE(NEARBYINT_F);
474   case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
475     RTLIBCASE(ROUNDEVEN_F);
476   }
477   llvm_unreachable("Unknown libcall function");
478 }
479 
480 /// True if an instruction is in tail position in its caller. Intended for
481 /// legalizing libcalls as tail calls when possible.
482 static bool isLibCallInTailPosition(const TargetInstrInfo &TII,
483                                     MachineInstr &MI) {
484   MachineBasicBlock &MBB = *MI.getParent();
485   const Function &F = MBB.getParent()->getFunction();
486 
487   // Conservatively require the attributes of the call to match those of
488   // the return. Ignore NoAlias and NonNull because they don't affect the
489   // call sequence.
490   AttributeList CallerAttrs = F.getAttributes();
491   if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
492           .removeAttribute(Attribute::NoAlias)
493           .removeAttribute(Attribute::NonNull)
494           .hasAttributes())
495     return false;
496 
497   // It's not safe to eliminate the sign / zero extension of the return value.
498   if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
499       CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
500     return false;
501 
502   // Only tail call if the following instruction is a standard return.
503   auto Next = next_nodbg(MI.getIterator(), MBB.instr_end());
504   if (Next == MBB.instr_end() || TII.isTailCall(*Next) || !Next->isReturn())
505     return false;
506 
507   return true;
508 }
509 
510 LegalizerHelper::LegalizeResult
511 llvm::createLibcall(MachineIRBuilder &MIRBuilder, const char *Name,
512                     const CallLowering::ArgInfo &Result,
513                     ArrayRef<CallLowering::ArgInfo> Args,
514                     const CallingConv::ID CC) {
515   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
516 
517   CallLowering::CallLoweringInfo Info;
518   Info.CallConv = CC;
519   Info.Callee = MachineOperand::CreateES(Name);
520   Info.OrigRet = Result;
521   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
522   if (!CLI.lowerCall(MIRBuilder, Info))
523     return LegalizerHelper::UnableToLegalize;
524 
525   return LegalizerHelper::Legalized;
526 }
527 
528 LegalizerHelper::LegalizeResult
529 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
530                     const CallLowering::ArgInfo &Result,
531                     ArrayRef<CallLowering::ArgInfo> Args) {
532   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
533   const char *Name = TLI.getLibcallName(Libcall);
534   const CallingConv::ID CC = TLI.getLibcallCallingConv(Libcall);
535   return createLibcall(MIRBuilder, Name, Result, Args, CC);
536 }
537 
538 // Useful for libcalls where all operands have the same type.
539 static LegalizerHelper::LegalizeResult
540 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
541               Type *OpType) {
542   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
543 
544   SmallVector<CallLowering::ArgInfo, 3> Args;
545   for (unsigned i = 1; i < MI.getNumOperands(); i++)
546     Args.push_back({MI.getOperand(i).getReg(), OpType});
547   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
548                        Args);
549 }
550 
551 LegalizerHelper::LegalizeResult
552 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
553                        MachineInstr &MI) {
554   assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
555   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
556 
557   SmallVector<CallLowering::ArgInfo, 3> Args;
558   // Add all the args, except for the last which is an imm denoting 'tail'.
559   for (unsigned i = 1; i < MI.getNumOperands() - 1; i++) {
560     Register Reg = MI.getOperand(i).getReg();
561 
562     // Need derive an IR type for call lowering.
563     LLT OpLLT = MRI.getType(Reg);
564     Type *OpTy = nullptr;
565     if (OpLLT.isPointer())
566       OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace());
567     else
568       OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits());
569     Args.push_back({Reg, OpTy});
570   }
571 
572   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
573   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
574   Intrinsic::ID ID = MI.getOperand(0).getIntrinsicID();
575   RTLIB::Libcall RTLibcall;
576   switch (ID) {
577   case Intrinsic::memcpy:
578     RTLibcall = RTLIB::MEMCPY;
579     break;
580   case Intrinsic::memset:
581     RTLibcall = RTLIB::MEMSET;
582     break;
583   case Intrinsic::memmove:
584     RTLibcall = RTLIB::MEMMOVE;
585     break;
586   default:
587     return LegalizerHelper::UnableToLegalize;
588   }
589   const char *Name = TLI.getLibcallName(RTLibcall);
590 
591   MIRBuilder.setInstrAndDebugLoc(MI);
592 
593   CallLowering::CallLoweringInfo Info;
594   Info.CallConv = TLI.getLibcallCallingConv(RTLibcall);
595   Info.Callee = MachineOperand::CreateES(Name);
596   Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx));
597   Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() == 1 &&
598                     isLibCallInTailPosition(MIRBuilder.getTII(), MI);
599 
600   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
601   if (!CLI.lowerCall(MIRBuilder, Info))
602     return LegalizerHelper::UnableToLegalize;
603 
604   if (Info.LoweredTailCall) {
605     assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?");
606     // We must have a return following the call (or debug insts) to get past
607     // isLibCallInTailPosition.
608     do {
609       MachineInstr *Next = MI.getNextNode();
610       assert(Next && (Next->isReturn() || Next->isDebugInstr()) &&
611              "Expected instr following MI to be return or debug inst?");
612       // We lowered a tail call, so the call is now the return from the block.
613       // Delete the old return.
614       Next->eraseFromParent();
615     } while (MI.getNextNode());
616   }
617 
618   return LegalizerHelper::Legalized;
619 }
620 
621 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
622                                        Type *FromType) {
623   auto ToMVT = MVT::getVT(ToType);
624   auto FromMVT = MVT::getVT(FromType);
625 
626   switch (Opcode) {
627   case TargetOpcode::G_FPEXT:
628     return RTLIB::getFPEXT(FromMVT, ToMVT);
629   case TargetOpcode::G_FPTRUNC:
630     return RTLIB::getFPROUND(FromMVT, ToMVT);
631   case TargetOpcode::G_FPTOSI:
632     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
633   case TargetOpcode::G_FPTOUI:
634     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
635   case TargetOpcode::G_SITOFP:
636     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
637   case TargetOpcode::G_UITOFP:
638     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
639   }
640   llvm_unreachable("Unsupported libcall function");
641 }
642 
643 static LegalizerHelper::LegalizeResult
644 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
645                   Type *FromType) {
646   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
647   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
648                        {{MI.getOperand(1).getReg(), FromType}});
649 }
650 
651 LegalizerHelper::LegalizeResult
652 LegalizerHelper::libcall(MachineInstr &MI) {
653   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
654   unsigned Size = LLTy.getSizeInBits();
655   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
656 
657   switch (MI.getOpcode()) {
658   default:
659     return UnableToLegalize;
660   case TargetOpcode::G_SDIV:
661   case TargetOpcode::G_UDIV:
662   case TargetOpcode::G_SREM:
663   case TargetOpcode::G_UREM:
664   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
665     Type *HLTy = IntegerType::get(Ctx, Size);
666     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
667     if (Status != Legalized)
668       return Status;
669     break;
670   }
671   case TargetOpcode::G_FADD:
672   case TargetOpcode::G_FSUB:
673   case TargetOpcode::G_FMUL:
674   case TargetOpcode::G_FDIV:
675   case TargetOpcode::G_FMA:
676   case TargetOpcode::G_FPOW:
677   case TargetOpcode::G_FREM:
678   case TargetOpcode::G_FCOS:
679   case TargetOpcode::G_FSIN:
680   case TargetOpcode::G_FLOG10:
681   case TargetOpcode::G_FLOG:
682   case TargetOpcode::G_FLOG2:
683   case TargetOpcode::G_FEXP:
684   case TargetOpcode::G_FEXP2:
685   case TargetOpcode::G_FCEIL:
686   case TargetOpcode::G_FFLOOR:
687   case TargetOpcode::G_FMINNUM:
688   case TargetOpcode::G_FMAXNUM:
689   case TargetOpcode::G_FSQRT:
690   case TargetOpcode::G_FRINT:
691   case TargetOpcode::G_FNEARBYINT:
692   case TargetOpcode::G_INTRINSIC_ROUNDEVEN: {
693     Type *HLTy = getFloatTypeForLLT(Ctx, LLTy);
694     if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) {
695       LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n");
696       return UnableToLegalize;
697     }
698     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
699     if (Status != Legalized)
700       return Status;
701     break;
702   }
703   case TargetOpcode::G_FPEXT:
704   case TargetOpcode::G_FPTRUNC: {
705     Type *FromTy = getFloatTypeForLLT(Ctx,  MRI.getType(MI.getOperand(1).getReg()));
706     Type *ToTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(0).getReg()));
707     if (!FromTy || !ToTy)
708       return UnableToLegalize;
709     LegalizeResult Status = conversionLibcall(MI, MIRBuilder, ToTy, FromTy );
710     if (Status != Legalized)
711       return Status;
712     break;
713   }
714   case TargetOpcode::G_FPTOSI:
715   case TargetOpcode::G_FPTOUI: {
716     // FIXME: Support other types
717     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
718     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
719     if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
720       return UnableToLegalize;
721     LegalizeResult Status = conversionLibcall(
722         MI, MIRBuilder,
723         ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
724         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
725     if (Status != Legalized)
726       return Status;
727     break;
728   }
729   case TargetOpcode::G_SITOFP:
730   case TargetOpcode::G_UITOFP: {
731     // FIXME: Support other types
732     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
733     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
734     if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
735       return UnableToLegalize;
736     LegalizeResult Status = conversionLibcall(
737         MI, MIRBuilder,
738         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
739         FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
740     if (Status != Legalized)
741       return Status;
742     break;
743   }
744   }
745 
746   MI.eraseFromParent();
747   return Legalized;
748 }
749 
750 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
751                                                               unsigned TypeIdx,
752                                                               LLT NarrowTy) {
753   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
754   uint64_t NarrowSize = NarrowTy.getSizeInBits();
755 
756   switch (MI.getOpcode()) {
757   default:
758     return UnableToLegalize;
759   case TargetOpcode::G_IMPLICIT_DEF: {
760     Register DstReg = MI.getOperand(0).getReg();
761     LLT DstTy = MRI.getType(DstReg);
762 
763     // If SizeOp0 is not an exact multiple of NarrowSize, emit
764     // G_ANYEXT(G_IMPLICIT_DEF). Cast result to vector if needed.
765     // FIXME: Although this would also be legal for the general case, it causes
766     //  a lot of regressions in the emitted code (superfluous COPYs, artifact
767     //  combines not being hit). This seems to be a problem related to the
768     //  artifact combiner.
769     if (SizeOp0 % NarrowSize != 0) {
770       LLT ImplicitTy = NarrowTy;
771       if (DstTy.isVector())
772         ImplicitTy = LLT::vector(DstTy.getNumElements(), ImplicitTy);
773 
774       Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0);
775       MIRBuilder.buildAnyExt(DstReg, ImplicitReg);
776 
777       MI.eraseFromParent();
778       return Legalized;
779     }
780 
781     int NumParts = SizeOp0 / NarrowSize;
782 
783     SmallVector<Register, 2> DstRegs;
784     for (int i = 0; i < NumParts; ++i)
785       DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0));
786 
787     if (DstTy.isVector())
788       MIRBuilder.buildBuildVector(DstReg, DstRegs);
789     else
790       MIRBuilder.buildMerge(DstReg, DstRegs);
791     MI.eraseFromParent();
792     return Legalized;
793   }
794   case TargetOpcode::G_CONSTANT: {
795     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
796     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
797     unsigned TotalSize = Ty.getSizeInBits();
798     unsigned NarrowSize = NarrowTy.getSizeInBits();
799     int NumParts = TotalSize / NarrowSize;
800 
801     SmallVector<Register, 4> PartRegs;
802     for (int I = 0; I != NumParts; ++I) {
803       unsigned Offset = I * NarrowSize;
804       auto K = MIRBuilder.buildConstant(NarrowTy,
805                                         Val.lshr(Offset).trunc(NarrowSize));
806       PartRegs.push_back(K.getReg(0));
807     }
808 
809     LLT LeftoverTy;
810     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
811     SmallVector<Register, 1> LeftoverRegs;
812     if (LeftoverBits != 0) {
813       LeftoverTy = LLT::scalar(LeftoverBits);
814       auto K = MIRBuilder.buildConstant(
815         LeftoverTy,
816         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
817       LeftoverRegs.push_back(K.getReg(0));
818     }
819 
820     insertParts(MI.getOperand(0).getReg(),
821                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
822 
823     MI.eraseFromParent();
824     return Legalized;
825   }
826   case TargetOpcode::G_SEXT:
827   case TargetOpcode::G_ZEXT:
828   case TargetOpcode::G_ANYEXT:
829     return narrowScalarExt(MI, TypeIdx, NarrowTy);
830   case TargetOpcode::G_TRUNC: {
831     if (TypeIdx != 1)
832       return UnableToLegalize;
833 
834     uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
835     if (NarrowTy.getSizeInBits() * 2 != SizeOp1) {
836       LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n");
837       return UnableToLegalize;
838     }
839 
840     auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1));
841     MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0));
842     MI.eraseFromParent();
843     return Legalized;
844   }
845 
846   case TargetOpcode::G_FREEZE:
847     return reduceOperationWidth(MI, TypeIdx, NarrowTy);
848 
849   case TargetOpcode::G_ADD: {
850     // FIXME: add support for when SizeOp0 isn't an exact multiple of
851     // NarrowSize.
852     if (SizeOp0 % NarrowSize != 0)
853       return UnableToLegalize;
854     // Expand in terms of carry-setting/consuming G_ADDE instructions.
855     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
856 
857     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
858     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
859     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
860 
861     Register CarryIn;
862     for (int i = 0; i < NumParts; ++i) {
863       Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
864       Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
865 
866       if (i == 0)
867         MIRBuilder.buildUAddo(DstReg, CarryOut, Src1Regs[i], Src2Regs[i]);
868       else {
869         MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
870                               Src2Regs[i], CarryIn);
871       }
872 
873       DstRegs.push_back(DstReg);
874       CarryIn = CarryOut;
875     }
876     Register DstReg = MI.getOperand(0).getReg();
877     if(MRI.getType(DstReg).isVector())
878       MIRBuilder.buildBuildVector(DstReg, DstRegs);
879     else
880       MIRBuilder.buildMerge(DstReg, DstRegs);
881     MI.eraseFromParent();
882     return Legalized;
883   }
884   case TargetOpcode::G_SUB: {
885     // FIXME: add support for when SizeOp0 isn't an exact multiple of
886     // NarrowSize.
887     if (SizeOp0 % NarrowSize != 0)
888       return UnableToLegalize;
889 
890     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
891 
892     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
893     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
894     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
895 
896     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
897     Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
898     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
899                           {Src1Regs[0], Src2Regs[0]});
900     DstRegs.push_back(DstReg);
901     Register BorrowIn = BorrowOut;
902     for (int i = 1; i < NumParts; ++i) {
903       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
904       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
905 
906       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
907                             {Src1Regs[i], Src2Regs[i], BorrowIn});
908 
909       DstRegs.push_back(DstReg);
910       BorrowIn = BorrowOut;
911     }
912     MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
913     MI.eraseFromParent();
914     return Legalized;
915   }
916   case TargetOpcode::G_MUL:
917   case TargetOpcode::G_UMULH:
918     return narrowScalarMul(MI, NarrowTy);
919   case TargetOpcode::G_EXTRACT:
920     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
921   case TargetOpcode::G_INSERT:
922     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
923   case TargetOpcode::G_LOAD: {
924     const auto &MMO = **MI.memoperands_begin();
925     Register DstReg = MI.getOperand(0).getReg();
926     LLT DstTy = MRI.getType(DstReg);
927     if (DstTy.isVector())
928       return UnableToLegalize;
929 
930     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
931       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
932       auto &MMO = **MI.memoperands_begin();
933       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1), MMO);
934       MIRBuilder.buildAnyExt(DstReg, TmpReg);
935       MI.eraseFromParent();
936       return Legalized;
937     }
938 
939     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
940   }
941   case TargetOpcode::G_ZEXTLOAD:
942   case TargetOpcode::G_SEXTLOAD: {
943     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
944     Register DstReg = MI.getOperand(0).getReg();
945     Register PtrReg = MI.getOperand(1).getReg();
946 
947     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
948     auto &MMO = **MI.memoperands_begin();
949     if (MMO.getSizeInBits() == NarrowSize) {
950       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
951     } else {
952       MIRBuilder.buildLoadInstr(MI.getOpcode(), TmpReg, PtrReg, MMO);
953     }
954 
955     if (ZExt)
956       MIRBuilder.buildZExt(DstReg, TmpReg);
957     else
958       MIRBuilder.buildSExt(DstReg, TmpReg);
959 
960     MI.eraseFromParent();
961     return Legalized;
962   }
963   case TargetOpcode::G_STORE: {
964     const auto &MMO = **MI.memoperands_begin();
965 
966     Register SrcReg = MI.getOperand(0).getReg();
967     LLT SrcTy = MRI.getType(SrcReg);
968     if (SrcTy.isVector())
969       return UnableToLegalize;
970 
971     int NumParts = SizeOp0 / NarrowSize;
972     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
973     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
974     if (SrcTy.isVector() && LeftoverBits != 0)
975       return UnableToLegalize;
976 
977     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
978       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
979       auto &MMO = **MI.memoperands_begin();
980       MIRBuilder.buildTrunc(TmpReg, SrcReg);
981       MIRBuilder.buildStore(TmpReg, MI.getOperand(1), MMO);
982       MI.eraseFromParent();
983       return Legalized;
984     }
985 
986     return reduceLoadStoreWidth(MI, 0, NarrowTy);
987   }
988   case TargetOpcode::G_SELECT:
989     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
990   case TargetOpcode::G_AND:
991   case TargetOpcode::G_OR:
992   case TargetOpcode::G_XOR: {
993     // Legalize bitwise operation:
994     // A = BinOp<Ty> B, C
995     // into:
996     // B1, ..., BN = G_UNMERGE_VALUES B
997     // C1, ..., CN = G_UNMERGE_VALUES C
998     // A1 = BinOp<Ty/N> B1, C2
999     // ...
1000     // AN = BinOp<Ty/N> BN, CN
1001     // A = G_MERGE_VALUES A1, ..., AN
1002     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
1003   }
1004   case TargetOpcode::G_SHL:
1005   case TargetOpcode::G_LSHR:
1006   case TargetOpcode::G_ASHR:
1007     return narrowScalarShift(MI, TypeIdx, NarrowTy);
1008   case TargetOpcode::G_CTLZ:
1009   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1010   case TargetOpcode::G_CTTZ:
1011   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1012   case TargetOpcode::G_CTPOP:
1013     if (TypeIdx == 1)
1014       switch (MI.getOpcode()) {
1015       case TargetOpcode::G_CTLZ:
1016       case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1017         return narrowScalarCTLZ(MI, TypeIdx, NarrowTy);
1018       case TargetOpcode::G_CTTZ:
1019       case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1020         return narrowScalarCTTZ(MI, TypeIdx, NarrowTy);
1021       case TargetOpcode::G_CTPOP:
1022         return narrowScalarCTPOP(MI, TypeIdx, NarrowTy);
1023       default:
1024         return UnableToLegalize;
1025       }
1026 
1027     Observer.changingInstr(MI);
1028     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
1029     Observer.changedInstr(MI);
1030     return Legalized;
1031   case TargetOpcode::G_INTTOPTR:
1032     if (TypeIdx != 1)
1033       return UnableToLegalize;
1034 
1035     Observer.changingInstr(MI);
1036     narrowScalarSrc(MI, NarrowTy, 1);
1037     Observer.changedInstr(MI);
1038     return Legalized;
1039   case TargetOpcode::G_PTRTOINT:
1040     if (TypeIdx != 0)
1041       return UnableToLegalize;
1042 
1043     Observer.changingInstr(MI);
1044     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
1045     Observer.changedInstr(MI);
1046     return Legalized;
1047   case TargetOpcode::G_PHI: {
1048     unsigned NumParts = SizeOp0 / NarrowSize;
1049     SmallVector<Register, 2> DstRegs(NumParts);
1050     SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2);
1051     Observer.changingInstr(MI);
1052     for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
1053       MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
1054       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1055       extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
1056                    SrcRegs[i / 2]);
1057     }
1058     MachineBasicBlock &MBB = *MI.getParent();
1059     MIRBuilder.setInsertPt(MBB, MI);
1060     for (unsigned i = 0; i < NumParts; ++i) {
1061       DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
1062       MachineInstrBuilder MIB =
1063           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
1064       for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
1065         MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
1066     }
1067     MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
1068     MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
1069     Observer.changedInstr(MI);
1070     MI.eraseFromParent();
1071     return Legalized;
1072   }
1073   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
1074   case TargetOpcode::G_INSERT_VECTOR_ELT: {
1075     if (TypeIdx != 2)
1076       return UnableToLegalize;
1077 
1078     int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
1079     Observer.changingInstr(MI);
1080     narrowScalarSrc(MI, NarrowTy, OpIdx);
1081     Observer.changedInstr(MI);
1082     return Legalized;
1083   }
1084   case TargetOpcode::G_ICMP: {
1085     uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
1086     if (NarrowSize * 2 != SrcSize)
1087       return UnableToLegalize;
1088 
1089     Observer.changingInstr(MI);
1090     Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
1091     Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
1092     MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2));
1093 
1094     Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
1095     Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
1096     MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3));
1097 
1098     CmpInst::Predicate Pred =
1099         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
1100     LLT ResTy = MRI.getType(MI.getOperand(0).getReg());
1101 
1102     if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) {
1103       MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
1104       MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
1105       MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
1106       MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
1107       MIRBuilder.buildICmp(Pred, MI.getOperand(0), Or, Zero);
1108     } else {
1109       MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
1110       MachineInstrBuilder CmpHEQ =
1111           MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
1112       MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
1113           ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
1114       MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH);
1115     }
1116     Observer.changedInstr(MI);
1117     MI.eraseFromParent();
1118     return Legalized;
1119   }
1120   case TargetOpcode::G_SEXT_INREG: {
1121     if (TypeIdx != 0)
1122       return UnableToLegalize;
1123 
1124     int64_t SizeInBits = MI.getOperand(2).getImm();
1125 
1126     // So long as the new type has more bits than the bits we're extending we
1127     // don't need to break it apart.
1128     if (NarrowTy.getScalarSizeInBits() >= SizeInBits) {
1129       Observer.changingInstr(MI);
1130       // We don't lose any non-extension bits by truncating the src and
1131       // sign-extending the dst.
1132       MachineOperand &MO1 = MI.getOperand(1);
1133       auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1);
1134       MO1.setReg(TruncMIB.getReg(0));
1135 
1136       MachineOperand &MO2 = MI.getOperand(0);
1137       Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
1138       MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1139       MIRBuilder.buildSExt(MO2, DstExt);
1140       MO2.setReg(DstExt);
1141       Observer.changedInstr(MI);
1142       return Legalized;
1143     }
1144 
1145     // Break it apart. Components below the extension point are unmodified. The
1146     // component containing the extension point becomes a narrower SEXT_INREG.
1147     // Components above it are ashr'd from the component containing the
1148     // extension point.
1149     if (SizeOp0 % NarrowSize != 0)
1150       return UnableToLegalize;
1151     int NumParts = SizeOp0 / NarrowSize;
1152 
1153     // List the registers where the destination will be scattered.
1154     SmallVector<Register, 2> DstRegs;
1155     // List the registers where the source will be split.
1156     SmallVector<Register, 2> SrcRegs;
1157 
1158     // Create all the temporary registers.
1159     for (int i = 0; i < NumParts; ++i) {
1160       Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy);
1161 
1162       SrcRegs.push_back(SrcReg);
1163     }
1164 
1165     // Explode the big arguments into smaller chunks.
1166     MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1));
1167 
1168     Register AshrCstReg =
1169         MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
1170             .getReg(0);
1171     Register FullExtensionReg = 0;
1172     Register PartialExtensionReg = 0;
1173 
1174     // Do the operation on each small part.
1175     for (int i = 0; i < NumParts; ++i) {
1176       if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits)
1177         DstRegs.push_back(SrcRegs[i]);
1178       else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) {
1179         assert(PartialExtensionReg &&
1180                "Expected to visit partial extension before full");
1181         if (FullExtensionReg) {
1182           DstRegs.push_back(FullExtensionReg);
1183           continue;
1184         }
1185         DstRegs.push_back(
1186             MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg)
1187                 .getReg(0));
1188         FullExtensionReg = DstRegs.back();
1189       } else {
1190         DstRegs.push_back(
1191             MIRBuilder
1192                 .buildInstr(
1193                     TargetOpcode::G_SEXT_INREG, {NarrowTy},
1194                     {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
1195                 .getReg(0));
1196         PartialExtensionReg = DstRegs.back();
1197       }
1198     }
1199 
1200     // Gather the destination registers into the final destination.
1201     Register DstReg = MI.getOperand(0).getReg();
1202     MIRBuilder.buildMerge(DstReg, DstRegs);
1203     MI.eraseFromParent();
1204     return Legalized;
1205   }
1206   case TargetOpcode::G_BSWAP:
1207   case TargetOpcode::G_BITREVERSE: {
1208     if (SizeOp0 % NarrowSize != 0)
1209       return UnableToLegalize;
1210 
1211     Observer.changingInstr(MI);
1212     SmallVector<Register, 2> SrcRegs, DstRegs;
1213     unsigned NumParts = SizeOp0 / NarrowSize;
1214     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
1215 
1216     for (unsigned i = 0; i < NumParts; ++i) {
1217       auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
1218                                            {SrcRegs[NumParts - 1 - i]});
1219       DstRegs.push_back(DstPart.getReg(0));
1220     }
1221 
1222     MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
1223 
1224     Observer.changedInstr(MI);
1225     MI.eraseFromParent();
1226     return Legalized;
1227   }
1228   case TargetOpcode::G_PTR_ADD:
1229   case TargetOpcode::G_PTRMASK: {
1230     if (TypeIdx != 1)
1231       return UnableToLegalize;
1232     Observer.changingInstr(MI);
1233     narrowScalarSrc(MI, NarrowTy, 2);
1234     Observer.changedInstr(MI);
1235     return Legalized;
1236   }
1237   case TargetOpcode::G_FPTOUI: {
1238     if (TypeIdx != 0)
1239       return UnableToLegalize;
1240     Observer.changingInstr(MI);
1241     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
1242     Observer.changedInstr(MI);
1243     return Legalized;
1244   }
1245   case TargetOpcode::G_FPTOSI: {
1246     if (TypeIdx != 0)
1247       return UnableToLegalize;
1248     Observer.changingInstr(MI);
1249     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_SEXT);
1250     Observer.changedInstr(MI);
1251     return Legalized;
1252   }
1253   case TargetOpcode::G_FPEXT:
1254     if (TypeIdx != 0)
1255       return UnableToLegalize;
1256     Observer.changingInstr(MI);
1257     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_FPEXT);
1258     Observer.changedInstr(MI);
1259     return Legalized;
1260   }
1261 }
1262 
1263 Register LegalizerHelper::coerceToScalar(Register Val) {
1264   LLT Ty = MRI.getType(Val);
1265   if (Ty.isScalar())
1266     return Val;
1267 
1268   const DataLayout &DL = MIRBuilder.getDataLayout();
1269   LLT NewTy = LLT::scalar(Ty.getSizeInBits());
1270   if (Ty.isPointer()) {
1271     if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace()))
1272       return Register();
1273     return MIRBuilder.buildPtrToInt(NewTy, Val).getReg(0);
1274   }
1275 
1276   Register NewVal = Val;
1277 
1278   assert(Ty.isVector());
1279   LLT EltTy = Ty.getElementType();
1280   if (EltTy.isPointer())
1281     NewVal = MIRBuilder.buildPtrToInt(NewTy, NewVal).getReg(0);
1282   return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0);
1283 }
1284 
1285 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
1286                                      unsigned OpIdx, unsigned ExtOpcode) {
1287   MachineOperand &MO = MI.getOperand(OpIdx);
1288   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO});
1289   MO.setReg(ExtB.getReg(0));
1290 }
1291 
1292 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
1293                                       unsigned OpIdx) {
1294   MachineOperand &MO = MI.getOperand(OpIdx);
1295   auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO);
1296   MO.setReg(ExtB.getReg(0));
1297 }
1298 
1299 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
1300                                      unsigned OpIdx, unsigned TruncOpcode) {
1301   MachineOperand &MO = MI.getOperand(OpIdx);
1302   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1303   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1304   MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt});
1305   MO.setReg(DstExt);
1306 }
1307 
1308 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
1309                                       unsigned OpIdx, unsigned ExtOpcode) {
1310   MachineOperand &MO = MI.getOperand(OpIdx);
1311   Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
1312   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1313   MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc});
1314   MO.setReg(DstTrunc);
1315 }
1316 
1317 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
1318                                             unsigned OpIdx) {
1319   MachineOperand &MO = MI.getOperand(OpIdx);
1320   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1321   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1322   MIRBuilder.buildExtract(MO, DstExt, 0);
1323   MO.setReg(DstExt);
1324 }
1325 
1326 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
1327                                             unsigned OpIdx) {
1328   MachineOperand &MO = MI.getOperand(OpIdx);
1329 
1330   LLT OldTy = MRI.getType(MO.getReg());
1331   unsigned OldElts = OldTy.getNumElements();
1332   unsigned NewElts = MoreTy.getNumElements();
1333 
1334   unsigned NumParts = NewElts / OldElts;
1335 
1336   // Use concat_vectors if the result is a multiple of the number of elements.
1337   if (NumParts * OldElts == NewElts) {
1338     SmallVector<Register, 8> Parts;
1339     Parts.push_back(MO.getReg());
1340 
1341     Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
1342     for (unsigned I = 1; I != NumParts; ++I)
1343       Parts.push_back(ImpDef);
1344 
1345     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
1346     MO.setReg(Concat.getReg(0));
1347     return;
1348   }
1349 
1350   Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
1351   Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
1352   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
1353   MO.setReg(MoreReg);
1354 }
1355 
1356 void LegalizerHelper::bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx) {
1357   MachineOperand &Op = MI.getOperand(OpIdx);
1358   Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0));
1359 }
1360 
1361 void LegalizerHelper::bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx) {
1362   MachineOperand &MO = MI.getOperand(OpIdx);
1363   Register CastDst = MRI.createGenericVirtualRegister(CastTy);
1364   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1365   MIRBuilder.buildBitcast(MO, CastDst);
1366   MO.setReg(CastDst);
1367 }
1368 
1369 LegalizerHelper::LegalizeResult
1370 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
1371                                         LLT WideTy) {
1372   if (TypeIdx != 1)
1373     return UnableToLegalize;
1374 
1375   Register DstReg = MI.getOperand(0).getReg();
1376   LLT DstTy = MRI.getType(DstReg);
1377   if (DstTy.isVector())
1378     return UnableToLegalize;
1379 
1380   Register Src1 = MI.getOperand(1).getReg();
1381   LLT SrcTy = MRI.getType(Src1);
1382   const int DstSize = DstTy.getSizeInBits();
1383   const int SrcSize = SrcTy.getSizeInBits();
1384   const int WideSize = WideTy.getSizeInBits();
1385   const int NumMerge = (DstSize + WideSize - 1) / WideSize;
1386 
1387   unsigned NumOps = MI.getNumOperands();
1388   unsigned NumSrc = MI.getNumOperands() - 1;
1389   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
1390 
1391   if (WideSize >= DstSize) {
1392     // Directly pack the bits in the target type.
1393     Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1394 
1395     for (unsigned I = 2; I != NumOps; ++I) {
1396       const unsigned Offset = (I - 1) * PartSize;
1397 
1398       Register SrcReg = MI.getOperand(I).getReg();
1399       assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
1400 
1401       auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
1402 
1403       Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
1404         MRI.createGenericVirtualRegister(WideTy);
1405 
1406       auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
1407       auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
1408       MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1409       ResultReg = NextResult;
1410     }
1411 
1412     if (WideSize > DstSize)
1413       MIRBuilder.buildTrunc(DstReg, ResultReg);
1414     else if (DstTy.isPointer())
1415       MIRBuilder.buildIntToPtr(DstReg, ResultReg);
1416 
1417     MI.eraseFromParent();
1418     return Legalized;
1419   }
1420 
1421   // Unmerge the original values to the GCD type, and recombine to the next
1422   // multiple greater than the original type.
1423   //
1424   // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6
1425   // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0
1426   // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1
1427   // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2
1428   // %10:_(s6) = G_MERGE_VALUES %4, %5, %6
1429   // %11:_(s6) = G_MERGE_VALUES %7, %8, %9
1430   // %12:_(s12) = G_MERGE_VALUES %10, %11
1431   //
1432   // Padding with undef if necessary:
1433   //
1434   // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6
1435   // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0
1436   // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1
1437   // %7:_(s2) = G_IMPLICIT_DEF
1438   // %8:_(s6) = G_MERGE_VALUES %3, %4, %5
1439   // %9:_(s6) = G_MERGE_VALUES %6, %7, %7
1440   // %10:_(s12) = G_MERGE_VALUES %8, %9
1441 
1442   const int GCD = greatestCommonDivisor(SrcSize, WideSize);
1443   LLT GCDTy = LLT::scalar(GCD);
1444 
1445   SmallVector<Register, 8> Parts;
1446   SmallVector<Register, 8> NewMergeRegs;
1447   SmallVector<Register, 8> Unmerges;
1448   LLT WideDstTy = LLT::scalar(NumMerge * WideSize);
1449 
1450   // Decompose the original operands if they don't evenly divide.
1451   for (int I = 1, E = MI.getNumOperands(); I != E; ++I) {
1452     Register SrcReg = MI.getOperand(I).getReg();
1453     if (GCD == SrcSize) {
1454       Unmerges.push_back(SrcReg);
1455     } else {
1456       auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
1457       for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J)
1458         Unmerges.push_back(Unmerge.getReg(J));
1459     }
1460   }
1461 
1462   // Pad with undef to the next size that is a multiple of the requested size.
1463   if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) {
1464     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1465     for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I)
1466       Unmerges.push_back(UndefReg);
1467   }
1468 
1469   const int PartsPerGCD = WideSize / GCD;
1470 
1471   // Build merges of each piece.
1472   ArrayRef<Register> Slicer(Unmerges);
1473   for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) {
1474     auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
1475     NewMergeRegs.push_back(Merge.getReg(0));
1476   }
1477 
1478   // A truncate may be necessary if the requested type doesn't evenly divide the
1479   // original result type.
1480   if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
1481     MIRBuilder.buildMerge(DstReg, NewMergeRegs);
1482   } else {
1483     auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
1484     MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
1485   }
1486 
1487   MI.eraseFromParent();
1488   return Legalized;
1489 }
1490 
1491 LegalizerHelper::LegalizeResult
1492 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
1493                                           LLT WideTy) {
1494   if (TypeIdx != 0)
1495     return UnableToLegalize;
1496 
1497   int NumDst = MI.getNumOperands() - 1;
1498   Register SrcReg = MI.getOperand(NumDst).getReg();
1499   LLT SrcTy = MRI.getType(SrcReg);
1500   if (SrcTy.isVector())
1501     return UnableToLegalize;
1502 
1503   Register Dst0Reg = MI.getOperand(0).getReg();
1504   LLT DstTy = MRI.getType(Dst0Reg);
1505   if (!DstTy.isScalar())
1506     return UnableToLegalize;
1507 
1508   if (WideTy.getSizeInBits() >= SrcTy.getSizeInBits()) {
1509     if (SrcTy.isPointer()) {
1510       const DataLayout &DL = MIRBuilder.getDataLayout();
1511       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) {
1512         LLVM_DEBUG(
1513             dbgs() << "Not casting non-integral address space integer\n");
1514         return UnableToLegalize;
1515       }
1516 
1517       SrcTy = LLT::scalar(SrcTy.getSizeInBits());
1518       SrcReg = MIRBuilder.buildPtrToInt(SrcTy, SrcReg).getReg(0);
1519     }
1520 
1521     // Widen SrcTy to WideTy. This does not affect the result, but since the
1522     // user requested this size, it is probably better handled than SrcTy and
1523     // should reduce the total number of legalization artifacts
1524     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1525       SrcTy = WideTy;
1526       SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0);
1527     }
1528 
1529     // Theres no unmerge type to target. Directly extract the bits from the
1530     // source type
1531     unsigned DstSize = DstTy.getSizeInBits();
1532 
1533     MIRBuilder.buildTrunc(Dst0Reg, SrcReg);
1534     for (int I = 1; I != NumDst; ++I) {
1535       auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I);
1536       auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt);
1537       MIRBuilder.buildTrunc(MI.getOperand(I), Shr);
1538     }
1539 
1540     MI.eraseFromParent();
1541     return Legalized;
1542   }
1543 
1544   // Extend the source to a wider type.
1545   LLT LCMTy = getLCMType(SrcTy, WideTy);
1546 
1547   Register WideSrc = SrcReg;
1548   if (LCMTy.getSizeInBits() != SrcTy.getSizeInBits()) {
1549     // TODO: If this is an integral address space, cast to integer and anyext.
1550     if (SrcTy.isPointer()) {
1551       LLVM_DEBUG(dbgs() << "Widening pointer source types not implemented\n");
1552       return UnableToLegalize;
1553     }
1554 
1555     WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0);
1556   }
1557 
1558   auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc);
1559 
1560   // Create a sequence of unmerges to the original results. since we may have
1561   // widened the source, we will need to pad the results with dead defs to cover
1562   // the source register.
1563   // e.g. widen s16 to s32:
1564   // %1:_(s16), %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0:_(s48)
1565   //
1566   // =>
1567   //  %4:_(s64) = G_ANYEXT %0:_(s48)
1568   //  %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %4 ; Requested unmerge
1569   //  %1:_(s16), %2:_(s16) = G_UNMERGE_VALUES %5 ; unpack to original regs
1570   //  %3:_(s16), dead %7 = G_UNMERGE_VALUES %6 ; original reg + extra dead def
1571 
1572   const int NumUnmerge = Unmerge->getNumOperands() - 1;
1573   const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits();
1574 
1575   for (int I = 0; I != NumUnmerge; ++I) {
1576     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
1577 
1578     for (int J = 0; J != PartsPerUnmerge; ++J) {
1579       int Idx = I * PartsPerUnmerge + J;
1580       if (Idx < NumDst)
1581         MIB.addDef(MI.getOperand(Idx).getReg());
1582       else {
1583         // Create dead def for excess components.
1584         MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
1585       }
1586     }
1587 
1588     MIB.addUse(Unmerge.getReg(I));
1589   }
1590 
1591   MI.eraseFromParent();
1592   return Legalized;
1593 }
1594 
1595 LegalizerHelper::LegalizeResult
1596 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
1597                                     LLT WideTy) {
1598   Register DstReg = MI.getOperand(0).getReg();
1599   Register SrcReg = MI.getOperand(1).getReg();
1600   LLT SrcTy = MRI.getType(SrcReg);
1601 
1602   LLT DstTy = MRI.getType(DstReg);
1603   unsigned Offset = MI.getOperand(2).getImm();
1604 
1605   if (TypeIdx == 0) {
1606     if (SrcTy.isVector() || DstTy.isVector())
1607       return UnableToLegalize;
1608 
1609     SrcOp Src(SrcReg);
1610     if (SrcTy.isPointer()) {
1611       // Extracts from pointers can be handled only if they are really just
1612       // simple integers.
1613       const DataLayout &DL = MIRBuilder.getDataLayout();
1614       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
1615         return UnableToLegalize;
1616 
1617       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
1618       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
1619       SrcTy = SrcAsIntTy;
1620     }
1621 
1622     if (DstTy.isPointer())
1623       return UnableToLegalize;
1624 
1625     if (Offset == 0) {
1626       // Avoid a shift in the degenerate case.
1627       MIRBuilder.buildTrunc(DstReg,
1628                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
1629       MI.eraseFromParent();
1630       return Legalized;
1631     }
1632 
1633     // Do a shift in the source type.
1634     LLT ShiftTy = SrcTy;
1635     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1636       Src = MIRBuilder.buildAnyExt(WideTy, Src);
1637       ShiftTy = WideTy;
1638     }
1639 
1640     auto LShr = MIRBuilder.buildLShr(
1641       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
1642     MIRBuilder.buildTrunc(DstReg, LShr);
1643     MI.eraseFromParent();
1644     return Legalized;
1645   }
1646 
1647   if (SrcTy.isScalar()) {
1648     Observer.changingInstr(MI);
1649     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1650     Observer.changedInstr(MI);
1651     return Legalized;
1652   }
1653 
1654   if (!SrcTy.isVector())
1655     return UnableToLegalize;
1656 
1657   if (DstTy != SrcTy.getElementType())
1658     return UnableToLegalize;
1659 
1660   if (Offset % SrcTy.getScalarSizeInBits() != 0)
1661     return UnableToLegalize;
1662 
1663   Observer.changingInstr(MI);
1664   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1665 
1666   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
1667                           Offset);
1668   widenScalarDst(MI, WideTy.getScalarType(), 0);
1669   Observer.changedInstr(MI);
1670   return Legalized;
1671 }
1672 
1673 LegalizerHelper::LegalizeResult
1674 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
1675                                    LLT WideTy) {
1676   if (TypeIdx != 0 || WideTy.isVector())
1677     return UnableToLegalize;
1678   Observer.changingInstr(MI);
1679   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1680   widenScalarDst(MI, WideTy);
1681   Observer.changedInstr(MI);
1682   return Legalized;
1683 }
1684 
1685 LegalizerHelper::LegalizeResult
1686 LegalizerHelper::widenScalarAddSubSat(MachineInstr &MI, unsigned TypeIdx,
1687                                       LLT WideTy) {
1688   bool IsSigned = MI.getOpcode() == TargetOpcode::G_SADDSAT ||
1689                   MI.getOpcode() == TargetOpcode::G_SSUBSAT;
1690   // We can convert this to:
1691   //   1. Any extend iN to iM
1692   //   2. SHL by M-N
1693   //   3. [US][ADD|SUB]SAT
1694   //   4. L/ASHR by M-N
1695   //
1696   // It may be more efficient to lower this to a min and a max operation in
1697   // the higher precision arithmetic if the promoted operation isn't legal,
1698   // but this decision is up to the target's lowering request.
1699   Register DstReg = MI.getOperand(0).getReg();
1700 
1701   unsigned NewBits = WideTy.getScalarSizeInBits();
1702   unsigned SHLAmount = NewBits - MRI.getType(DstReg).getScalarSizeInBits();
1703 
1704   auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1));
1705   auto RHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2));
1706   auto ShiftK = MIRBuilder.buildConstant(WideTy, SHLAmount);
1707   auto ShiftL = MIRBuilder.buildShl(WideTy, LHS, ShiftK);
1708   auto ShiftR = MIRBuilder.buildShl(WideTy, RHS, ShiftK);
1709 
1710   auto WideInst = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy},
1711                                         {ShiftL, ShiftR}, MI.getFlags());
1712 
1713   // Use a shift that will preserve the number of sign bits when the trunc is
1714   // folded away.
1715   auto Result = IsSigned ? MIRBuilder.buildAShr(WideTy, WideInst, ShiftK)
1716                          : MIRBuilder.buildLShr(WideTy, WideInst, ShiftK);
1717 
1718   MIRBuilder.buildTrunc(DstReg, Result);
1719   MI.eraseFromParent();
1720   return Legalized;
1721 }
1722 
1723 LegalizerHelper::LegalizeResult
1724 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
1725   switch (MI.getOpcode()) {
1726   default:
1727     return UnableToLegalize;
1728   case TargetOpcode::G_EXTRACT:
1729     return widenScalarExtract(MI, TypeIdx, WideTy);
1730   case TargetOpcode::G_INSERT:
1731     return widenScalarInsert(MI, TypeIdx, WideTy);
1732   case TargetOpcode::G_MERGE_VALUES:
1733     return widenScalarMergeValues(MI, TypeIdx, WideTy);
1734   case TargetOpcode::G_UNMERGE_VALUES:
1735     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
1736   case TargetOpcode::G_UADDO:
1737   case TargetOpcode::G_USUBO: {
1738     if (TypeIdx == 1)
1739       return UnableToLegalize; // TODO
1740     auto LHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(2));
1741     auto RHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(3));
1742     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1743                           ? TargetOpcode::G_ADD
1744                           : TargetOpcode::G_SUB;
1745     // Do the arithmetic in the larger type.
1746     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1747     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1748     APInt Mask =
1749         APInt::getLowBitsSet(WideTy.getSizeInBits(), OrigTy.getSizeInBits());
1750     auto AndOp = MIRBuilder.buildAnd(
1751         WideTy, NewOp, MIRBuilder.buildConstant(WideTy, Mask));
1752     // There is no overflow if the AndOp is the same as NewOp.
1753     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, AndOp);
1754     // Now trunc the NewOp to the original result.
1755     MIRBuilder.buildTrunc(MI.getOperand(0), NewOp);
1756     MI.eraseFromParent();
1757     return Legalized;
1758   }
1759   case TargetOpcode::G_SADDSAT:
1760   case TargetOpcode::G_SSUBSAT:
1761   case TargetOpcode::G_UADDSAT:
1762   case TargetOpcode::G_USUBSAT:
1763     return widenScalarAddSubSat(MI, TypeIdx, WideTy);
1764   case TargetOpcode::G_CTTZ:
1765   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1766   case TargetOpcode::G_CTLZ:
1767   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1768   case TargetOpcode::G_CTPOP: {
1769     if (TypeIdx == 0) {
1770       Observer.changingInstr(MI);
1771       widenScalarDst(MI, WideTy, 0);
1772       Observer.changedInstr(MI);
1773       return Legalized;
1774     }
1775 
1776     Register SrcReg = MI.getOperand(1).getReg();
1777 
1778     // First ZEXT the input.
1779     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1780     LLT CurTy = MRI.getType(SrcReg);
1781     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1782       // The count is the same in the larger type except if the original
1783       // value was zero.  This can be handled by setting the bit just off
1784       // the top of the original type.
1785       auto TopBit =
1786           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1787       MIBSrc = MIRBuilder.buildOr(
1788         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1789     }
1790 
1791     // Perform the operation at the larger size.
1792     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1793     // This is already the correct result for CTPOP and CTTZs
1794     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1795         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1796       // The correct result is NewOp - (Difference in widety and current ty).
1797       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1798       MIBNewOp = MIRBuilder.buildSub(
1799           WideTy, MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff));
1800     }
1801 
1802     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1803     MI.eraseFromParent();
1804     return Legalized;
1805   }
1806   case TargetOpcode::G_BSWAP: {
1807     Observer.changingInstr(MI);
1808     Register DstReg = MI.getOperand(0).getReg();
1809 
1810     Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1811     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1812     Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1813     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1814 
1815     MI.getOperand(0).setReg(DstExt);
1816 
1817     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1818 
1819     LLT Ty = MRI.getType(DstReg);
1820     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1821     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1822     MIRBuilder.buildLShr(ShrReg, DstExt, ShiftAmtReg);
1823 
1824     MIRBuilder.buildTrunc(DstReg, ShrReg);
1825     Observer.changedInstr(MI);
1826     return Legalized;
1827   }
1828   case TargetOpcode::G_BITREVERSE: {
1829     Observer.changingInstr(MI);
1830 
1831     Register DstReg = MI.getOperand(0).getReg();
1832     LLT Ty = MRI.getType(DstReg);
1833     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1834 
1835     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1836     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1837     MI.getOperand(0).setReg(DstExt);
1838     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1839 
1840     auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
1841     auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt);
1842     MIRBuilder.buildTrunc(DstReg, Shift);
1843     Observer.changedInstr(MI);
1844     return Legalized;
1845   }
1846   case TargetOpcode::G_FREEZE:
1847     Observer.changingInstr(MI);
1848     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1849     widenScalarDst(MI, WideTy);
1850     Observer.changedInstr(MI);
1851     return Legalized;
1852 
1853   case TargetOpcode::G_ADD:
1854   case TargetOpcode::G_AND:
1855   case TargetOpcode::G_MUL:
1856   case TargetOpcode::G_OR:
1857   case TargetOpcode::G_XOR:
1858   case TargetOpcode::G_SUB:
1859     // Perform operation at larger width (any extension is fines here, high bits
1860     // don't affect the result) and then truncate the result back to the
1861     // original type.
1862     Observer.changingInstr(MI);
1863     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1864     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1865     widenScalarDst(MI, WideTy);
1866     Observer.changedInstr(MI);
1867     return Legalized;
1868 
1869   case TargetOpcode::G_SHL:
1870     Observer.changingInstr(MI);
1871 
1872     if (TypeIdx == 0) {
1873       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1874       widenScalarDst(MI, WideTy);
1875     } else {
1876       assert(TypeIdx == 1);
1877       // The "number of bits to shift" operand must preserve its value as an
1878       // unsigned integer:
1879       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1880     }
1881 
1882     Observer.changedInstr(MI);
1883     return Legalized;
1884 
1885   case TargetOpcode::G_SDIV:
1886   case TargetOpcode::G_SREM:
1887   case TargetOpcode::G_SMIN:
1888   case TargetOpcode::G_SMAX:
1889     Observer.changingInstr(MI);
1890     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1891     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1892     widenScalarDst(MI, WideTy);
1893     Observer.changedInstr(MI);
1894     return Legalized;
1895 
1896   case TargetOpcode::G_ASHR:
1897   case TargetOpcode::G_LSHR:
1898     Observer.changingInstr(MI);
1899 
1900     if (TypeIdx == 0) {
1901       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1902         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1903 
1904       widenScalarSrc(MI, WideTy, 1, CvtOp);
1905       widenScalarDst(MI, WideTy);
1906     } else {
1907       assert(TypeIdx == 1);
1908       // The "number of bits to shift" operand must preserve its value as an
1909       // unsigned integer:
1910       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1911     }
1912 
1913     Observer.changedInstr(MI);
1914     return Legalized;
1915   case TargetOpcode::G_UDIV:
1916   case TargetOpcode::G_UREM:
1917   case TargetOpcode::G_UMIN:
1918   case TargetOpcode::G_UMAX:
1919     Observer.changingInstr(MI);
1920     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1921     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1922     widenScalarDst(MI, WideTy);
1923     Observer.changedInstr(MI);
1924     return Legalized;
1925 
1926   case TargetOpcode::G_SELECT:
1927     Observer.changingInstr(MI);
1928     if (TypeIdx == 0) {
1929       // Perform operation at larger width (any extension is fine here, high
1930       // bits don't affect the result) and then truncate the result back to the
1931       // original type.
1932       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1933       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1934       widenScalarDst(MI, WideTy);
1935     } else {
1936       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1937       // Explicit extension is required here since high bits affect the result.
1938       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1939     }
1940     Observer.changedInstr(MI);
1941     return Legalized;
1942 
1943   case TargetOpcode::G_FPTOSI:
1944   case TargetOpcode::G_FPTOUI:
1945     Observer.changingInstr(MI);
1946 
1947     if (TypeIdx == 0)
1948       widenScalarDst(MI, WideTy);
1949     else
1950       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT);
1951 
1952     Observer.changedInstr(MI);
1953     return Legalized;
1954   case TargetOpcode::G_SITOFP:
1955     Observer.changingInstr(MI);
1956 
1957     if (TypeIdx == 0)
1958       widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1959     else
1960       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1961 
1962     Observer.changedInstr(MI);
1963     return Legalized;
1964   case TargetOpcode::G_UITOFP:
1965     Observer.changingInstr(MI);
1966 
1967     if (TypeIdx == 0)
1968       widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1969     else
1970       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1971 
1972     Observer.changedInstr(MI);
1973     return Legalized;
1974   case TargetOpcode::G_LOAD:
1975   case TargetOpcode::G_SEXTLOAD:
1976   case TargetOpcode::G_ZEXTLOAD:
1977     Observer.changingInstr(MI);
1978     widenScalarDst(MI, WideTy);
1979     Observer.changedInstr(MI);
1980     return Legalized;
1981 
1982   case TargetOpcode::G_STORE: {
1983     if (TypeIdx != 0)
1984       return UnableToLegalize;
1985 
1986     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1987     if (!isPowerOf2_32(Ty.getSizeInBits()))
1988       return UnableToLegalize;
1989 
1990     Observer.changingInstr(MI);
1991 
1992     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1993       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1994     widenScalarSrc(MI, WideTy, 0, ExtType);
1995 
1996     Observer.changedInstr(MI);
1997     return Legalized;
1998   }
1999   case TargetOpcode::G_CONSTANT: {
2000     MachineOperand &SrcMO = MI.getOperand(1);
2001     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
2002     unsigned ExtOpc = LI.getExtOpcodeForWideningConstant(
2003         MRI.getType(MI.getOperand(0).getReg()));
2004     assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT ||
2005             ExtOpc == TargetOpcode::G_ANYEXT) &&
2006            "Illegal Extend");
2007     const APInt &SrcVal = SrcMO.getCImm()->getValue();
2008     const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT)
2009                            ? SrcVal.sext(WideTy.getSizeInBits())
2010                            : SrcVal.zext(WideTy.getSizeInBits());
2011     Observer.changingInstr(MI);
2012     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
2013 
2014     widenScalarDst(MI, WideTy);
2015     Observer.changedInstr(MI);
2016     return Legalized;
2017   }
2018   case TargetOpcode::G_FCONSTANT: {
2019     MachineOperand &SrcMO = MI.getOperand(1);
2020     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
2021     APFloat Val = SrcMO.getFPImm()->getValueAPF();
2022     bool LosesInfo;
2023     switch (WideTy.getSizeInBits()) {
2024     case 32:
2025       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
2026                   &LosesInfo);
2027       break;
2028     case 64:
2029       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
2030                   &LosesInfo);
2031       break;
2032     default:
2033       return UnableToLegalize;
2034     }
2035 
2036     assert(!LosesInfo && "extend should always be lossless");
2037 
2038     Observer.changingInstr(MI);
2039     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
2040 
2041     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
2042     Observer.changedInstr(MI);
2043     return Legalized;
2044   }
2045   case TargetOpcode::G_IMPLICIT_DEF: {
2046     Observer.changingInstr(MI);
2047     widenScalarDst(MI, WideTy);
2048     Observer.changedInstr(MI);
2049     return Legalized;
2050   }
2051   case TargetOpcode::G_BRCOND:
2052     Observer.changingInstr(MI);
2053     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
2054     Observer.changedInstr(MI);
2055     return Legalized;
2056 
2057   case TargetOpcode::G_FCMP:
2058     Observer.changingInstr(MI);
2059     if (TypeIdx == 0)
2060       widenScalarDst(MI, WideTy);
2061     else {
2062       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
2063       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
2064     }
2065     Observer.changedInstr(MI);
2066     return Legalized;
2067 
2068   case TargetOpcode::G_ICMP:
2069     Observer.changingInstr(MI);
2070     if (TypeIdx == 0)
2071       widenScalarDst(MI, WideTy);
2072     else {
2073       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
2074                                MI.getOperand(1).getPredicate()))
2075                                ? TargetOpcode::G_SEXT
2076                                : TargetOpcode::G_ZEXT;
2077       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
2078       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
2079     }
2080     Observer.changedInstr(MI);
2081     return Legalized;
2082 
2083   case TargetOpcode::G_PTR_ADD:
2084     assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD");
2085     Observer.changingInstr(MI);
2086     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
2087     Observer.changedInstr(MI);
2088     return Legalized;
2089 
2090   case TargetOpcode::G_PHI: {
2091     assert(TypeIdx == 0 && "Expecting only Idx 0");
2092 
2093     Observer.changingInstr(MI);
2094     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
2095       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2096       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2097       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
2098     }
2099 
2100     MachineBasicBlock &MBB = *MI.getParent();
2101     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
2102     widenScalarDst(MI, WideTy);
2103     Observer.changedInstr(MI);
2104     return Legalized;
2105   }
2106   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
2107     if (TypeIdx == 0) {
2108       Register VecReg = MI.getOperand(1).getReg();
2109       LLT VecTy = MRI.getType(VecReg);
2110       Observer.changingInstr(MI);
2111 
2112       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
2113                                      WideTy.getSizeInBits()),
2114                      1, TargetOpcode::G_SEXT);
2115 
2116       widenScalarDst(MI, WideTy, 0);
2117       Observer.changedInstr(MI);
2118       return Legalized;
2119     }
2120 
2121     if (TypeIdx != 2)
2122       return UnableToLegalize;
2123     Observer.changingInstr(MI);
2124     // TODO: Probably should be zext
2125     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
2126     Observer.changedInstr(MI);
2127     return Legalized;
2128   }
2129   case TargetOpcode::G_INSERT_VECTOR_ELT: {
2130     if (TypeIdx == 1) {
2131       Observer.changingInstr(MI);
2132 
2133       Register VecReg = MI.getOperand(1).getReg();
2134       LLT VecTy = MRI.getType(VecReg);
2135       LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy);
2136 
2137       widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT);
2138       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
2139       widenScalarDst(MI, WideVecTy, 0);
2140       Observer.changedInstr(MI);
2141       return Legalized;
2142     }
2143 
2144     if (TypeIdx == 2) {
2145       Observer.changingInstr(MI);
2146       // TODO: Probably should be zext
2147       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT);
2148       Observer.changedInstr(MI);
2149       return Legalized;
2150     }
2151 
2152     return UnableToLegalize;
2153   }
2154   case TargetOpcode::G_FADD:
2155   case TargetOpcode::G_FMUL:
2156   case TargetOpcode::G_FSUB:
2157   case TargetOpcode::G_FMA:
2158   case TargetOpcode::G_FMAD:
2159   case TargetOpcode::G_FNEG:
2160   case TargetOpcode::G_FABS:
2161   case TargetOpcode::G_FCANONICALIZE:
2162   case TargetOpcode::G_FMINNUM:
2163   case TargetOpcode::G_FMAXNUM:
2164   case TargetOpcode::G_FMINNUM_IEEE:
2165   case TargetOpcode::G_FMAXNUM_IEEE:
2166   case TargetOpcode::G_FMINIMUM:
2167   case TargetOpcode::G_FMAXIMUM:
2168   case TargetOpcode::G_FDIV:
2169   case TargetOpcode::G_FREM:
2170   case TargetOpcode::G_FCEIL:
2171   case TargetOpcode::G_FFLOOR:
2172   case TargetOpcode::G_FCOS:
2173   case TargetOpcode::G_FSIN:
2174   case TargetOpcode::G_FLOG10:
2175   case TargetOpcode::G_FLOG:
2176   case TargetOpcode::G_FLOG2:
2177   case TargetOpcode::G_FRINT:
2178   case TargetOpcode::G_FNEARBYINT:
2179   case TargetOpcode::G_FSQRT:
2180   case TargetOpcode::G_FEXP:
2181   case TargetOpcode::G_FEXP2:
2182   case TargetOpcode::G_FPOW:
2183   case TargetOpcode::G_INTRINSIC_TRUNC:
2184   case TargetOpcode::G_INTRINSIC_ROUND:
2185   case TargetOpcode::G_INTRINSIC_ROUNDEVEN:
2186     assert(TypeIdx == 0);
2187     Observer.changingInstr(MI);
2188 
2189     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
2190       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
2191 
2192     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
2193     Observer.changedInstr(MI);
2194     return Legalized;
2195   case TargetOpcode::G_FPOWI: {
2196     if (TypeIdx != 0)
2197       return UnableToLegalize;
2198     Observer.changingInstr(MI);
2199     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT);
2200     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
2201     Observer.changedInstr(MI);
2202     return Legalized;
2203   }
2204   case TargetOpcode::G_INTTOPTR:
2205     if (TypeIdx != 1)
2206       return UnableToLegalize;
2207 
2208     Observer.changingInstr(MI);
2209     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
2210     Observer.changedInstr(MI);
2211     return Legalized;
2212   case TargetOpcode::G_PTRTOINT:
2213     if (TypeIdx != 0)
2214       return UnableToLegalize;
2215 
2216     Observer.changingInstr(MI);
2217     widenScalarDst(MI, WideTy, 0);
2218     Observer.changedInstr(MI);
2219     return Legalized;
2220   case TargetOpcode::G_BUILD_VECTOR: {
2221     Observer.changingInstr(MI);
2222 
2223     const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
2224     for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
2225       widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT);
2226 
2227     // Avoid changing the result vector type if the source element type was
2228     // requested.
2229     if (TypeIdx == 1) {
2230       MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
2231     } else {
2232       widenScalarDst(MI, WideTy, 0);
2233     }
2234 
2235     Observer.changedInstr(MI);
2236     return Legalized;
2237   }
2238   case TargetOpcode::G_SEXT_INREG:
2239     if (TypeIdx != 0)
2240       return UnableToLegalize;
2241 
2242     Observer.changingInstr(MI);
2243     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
2244     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC);
2245     Observer.changedInstr(MI);
2246     return Legalized;
2247   case TargetOpcode::G_PTRMASK: {
2248     if (TypeIdx != 1)
2249       return UnableToLegalize;
2250     Observer.changingInstr(MI);
2251     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
2252     Observer.changedInstr(MI);
2253     return Legalized;
2254   }
2255   }
2256 }
2257 
2258 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces,
2259                              MachineIRBuilder &B, Register Src, LLT Ty) {
2260   auto Unmerge = B.buildUnmerge(Ty, Src);
2261   for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
2262     Pieces.push_back(Unmerge.getReg(I));
2263 }
2264 
2265 LegalizerHelper::LegalizeResult
2266 LegalizerHelper::lowerBitcast(MachineInstr &MI) {
2267   Register Dst = MI.getOperand(0).getReg();
2268   Register Src = MI.getOperand(1).getReg();
2269   LLT DstTy = MRI.getType(Dst);
2270   LLT SrcTy = MRI.getType(Src);
2271 
2272   if (SrcTy.isVector()) {
2273     LLT SrcEltTy = SrcTy.getElementType();
2274     SmallVector<Register, 8> SrcRegs;
2275 
2276     if (DstTy.isVector()) {
2277       int NumDstElt = DstTy.getNumElements();
2278       int NumSrcElt = SrcTy.getNumElements();
2279 
2280       LLT DstEltTy = DstTy.getElementType();
2281       LLT DstCastTy = DstEltTy; // Intermediate bitcast result type
2282       LLT SrcPartTy = SrcEltTy; // Original unmerge result type.
2283 
2284       // If there's an element size mismatch, insert intermediate casts to match
2285       // the result element type.
2286       if (NumSrcElt < NumDstElt) { // Source element type is larger.
2287         // %1:_(<4 x s8>) = G_BITCAST %0:_(<2 x s16>)
2288         //
2289         // =>
2290         //
2291         // %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0
2292         // %3:_(<2 x s8>) = G_BITCAST %2
2293         // %4:_(<2 x s8>) = G_BITCAST %3
2294         // %1:_(<4 x s16>) = G_CONCAT_VECTORS %3, %4
2295         DstCastTy = LLT::vector(NumDstElt / NumSrcElt, DstEltTy);
2296         SrcPartTy = SrcEltTy;
2297       } else if (NumSrcElt > NumDstElt) { // Source element type is smaller.
2298         //
2299         // %1:_(<2 x s16>) = G_BITCAST %0:_(<4 x s8>)
2300         //
2301         // =>
2302         //
2303         // %2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %0
2304         // %3:_(s16) = G_BITCAST %2
2305         // %4:_(s16) = G_BITCAST %3
2306         // %1:_(<2 x s16>) = G_BUILD_VECTOR %3, %4
2307         SrcPartTy = LLT::vector(NumSrcElt / NumDstElt, SrcEltTy);
2308         DstCastTy = DstEltTy;
2309       }
2310 
2311       getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcPartTy);
2312       for (Register &SrcReg : SrcRegs)
2313         SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0);
2314     } else
2315       getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcEltTy);
2316 
2317     MIRBuilder.buildMerge(Dst, SrcRegs);
2318     MI.eraseFromParent();
2319     return Legalized;
2320   }
2321 
2322   if (DstTy.isVector()) {
2323     SmallVector<Register, 8> SrcRegs;
2324     getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType());
2325     MIRBuilder.buildMerge(Dst, SrcRegs);
2326     MI.eraseFromParent();
2327     return Legalized;
2328   }
2329 
2330   return UnableToLegalize;
2331 }
2332 
2333 LegalizerHelper::LegalizeResult
2334 LegalizerHelper::bitcast(MachineInstr &MI, unsigned TypeIdx, LLT CastTy) {
2335   switch (MI.getOpcode()) {
2336   case TargetOpcode::G_LOAD: {
2337     if (TypeIdx != 0)
2338       return UnableToLegalize;
2339 
2340     Observer.changingInstr(MI);
2341     bitcastDst(MI, CastTy, 0);
2342     Observer.changedInstr(MI);
2343     return Legalized;
2344   }
2345   case TargetOpcode::G_STORE: {
2346     if (TypeIdx != 0)
2347       return UnableToLegalize;
2348 
2349     Observer.changingInstr(MI);
2350     bitcastSrc(MI, CastTy, 0);
2351     Observer.changedInstr(MI);
2352     return Legalized;
2353   }
2354   case TargetOpcode::G_SELECT: {
2355     if (TypeIdx != 0)
2356       return UnableToLegalize;
2357 
2358     if (MRI.getType(MI.getOperand(1).getReg()).isVector()) {
2359       LLVM_DEBUG(
2360           dbgs() << "bitcast action not implemented for vector select\n");
2361       return UnableToLegalize;
2362     }
2363 
2364     Observer.changingInstr(MI);
2365     bitcastSrc(MI, CastTy, 2);
2366     bitcastSrc(MI, CastTy, 3);
2367     bitcastDst(MI, CastTy, 0);
2368     Observer.changedInstr(MI);
2369     return Legalized;
2370   }
2371   case TargetOpcode::G_AND:
2372   case TargetOpcode::G_OR:
2373   case TargetOpcode::G_XOR: {
2374     Observer.changingInstr(MI);
2375     bitcastSrc(MI, CastTy, 1);
2376     bitcastSrc(MI, CastTy, 2);
2377     bitcastDst(MI, CastTy, 0);
2378     Observer.changedInstr(MI);
2379     return Legalized;
2380   }
2381   default:
2382     return UnableToLegalize;
2383   }
2384 }
2385 
2386 // Legalize an instruction by changing the opcode in place.
2387 void LegalizerHelper::changeOpcode(MachineInstr &MI, unsigned NewOpcode) {
2388     Observer.changingInstr(MI);
2389     MI.setDesc(MIRBuilder.getTII().get(NewOpcode));
2390     Observer.changedInstr(MI);
2391 }
2392 
2393 LegalizerHelper::LegalizeResult
2394 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
2395   using namespace TargetOpcode;
2396 
2397   switch(MI.getOpcode()) {
2398   default:
2399     return UnableToLegalize;
2400   case TargetOpcode::G_BITCAST:
2401     return lowerBitcast(MI);
2402   case TargetOpcode::G_SREM:
2403   case TargetOpcode::G_UREM: {
2404     auto Quot =
2405         MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {Ty},
2406                               {MI.getOperand(1), MI.getOperand(2)});
2407 
2408     auto Prod = MIRBuilder.buildMul(Ty, Quot, MI.getOperand(2));
2409     MIRBuilder.buildSub(MI.getOperand(0), MI.getOperand(1), Prod);
2410     MI.eraseFromParent();
2411     return Legalized;
2412   }
2413   case TargetOpcode::G_SADDO:
2414   case TargetOpcode::G_SSUBO:
2415     return lowerSADDO_SSUBO(MI);
2416   case TargetOpcode::G_SMULO:
2417   case TargetOpcode::G_UMULO: {
2418     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
2419     // result.
2420     Register Res = MI.getOperand(0).getReg();
2421     Register Overflow = MI.getOperand(1).getReg();
2422     Register LHS = MI.getOperand(2).getReg();
2423     Register RHS = MI.getOperand(3).getReg();
2424 
2425     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
2426                           ? TargetOpcode::G_SMULH
2427                           : TargetOpcode::G_UMULH;
2428 
2429     Observer.changingInstr(MI);
2430     const auto &TII = MIRBuilder.getTII();
2431     MI.setDesc(TII.get(TargetOpcode::G_MUL));
2432     MI.RemoveOperand(1);
2433     Observer.changedInstr(MI);
2434 
2435     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
2436 
2437     auto HiPart = MIRBuilder.buildInstr(Opcode, {Ty}, {LHS, RHS});
2438     auto Zero = MIRBuilder.buildConstant(Ty, 0);
2439 
2440     // For *signed* multiply, overflow is detected by checking:
2441     // (hi != (lo >> bitwidth-1))
2442     if (Opcode == TargetOpcode::G_SMULH) {
2443       auto ShiftAmt = MIRBuilder.buildConstant(Ty, Ty.getSizeInBits() - 1);
2444       auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt);
2445       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
2446     } else {
2447       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
2448     }
2449     return Legalized;
2450   }
2451   case TargetOpcode::G_FNEG: {
2452     // TODO: Handle vector types once we are able to
2453     // represent them.
2454     if (Ty.isVector())
2455       return UnableToLegalize;
2456     Register Res = MI.getOperand(0).getReg();
2457     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
2458     Type *ZeroTy = getFloatTypeForLLT(Ctx, Ty);
2459     if (!ZeroTy)
2460       return UnableToLegalize;
2461     ConstantFP &ZeroForNegation =
2462         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
2463     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
2464     Register SubByReg = MI.getOperand(1).getReg();
2465     Register ZeroReg = Zero.getReg(0);
2466     MIRBuilder.buildFSub(Res, ZeroReg, SubByReg, MI.getFlags());
2467     MI.eraseFromParent();
2468     return Legalized;
2469   }
2470   case TargetOpcode::G_FSUB: {
2471     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
2472     // First, check if G_FNEG is marked as Lower. If so, we may
2473     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
2474     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
2475       return UnableToLegalize;
2476     Register Res = MI.getOperand(0).getReg();
2477     Register LHS = MI.getOperand(1).getReg();
2478     Register RHS = MI.getOperand(2).getReg();
2479     Register Neg = MRI.createGenericVirtualRegister(Ty);
2480     MIRBuilder.buildFNeg(Neg, RHS);
2481     MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags());
2482     MI.eraseFromParent();
2483     return Legalized;
2484   }
2485   case TargetOpcode::G_FMAD:
2486     return lowerFMad(MI);
2487   case TargetOpcode::G_FFLOOR:
2488     return lowerFFloor(MI);
2489   case TargetOpcode::G_INTRINSIC_ROUND:
2490     return lowerIntrinsicRound(MI);
2491   case TargetOpcode::G_INTRINSIC_ROUNDEVEN: {
2492     // Since round even is the assumed rounding mode for unconstrained FP
2493     // operations, rint and roundeven are the same operation.
2494     changeOpcode(MI, TargetOpcode::G_FRINT);
2495     return Legalized;
2496   }
2497   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
2498     Register OldValRes = MI.getOperand(0).getReg();
2499     Register SuccessRes = MI.getOperand(1).getReg();
2500     Register Addr = MI.getOperand(2).getReg();
2501     Register CmpVal = MI.getOperand(3).getReg();
2502     Register NewVal = MI.getOperand(4).getReg();
2503     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
2504                                   **MI.memoperands_begin());
2505     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
2506     MI.eraseFromParent();
2507     return Legalized;
2508   }
2509   case TargetOpcode::G_LOAD:
2510   case TargetOpcode::G_SEXTLOAD:
2511   case TargetOpcode::G_ZEXTLOAD: {
2512     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
2513     Register DstReg = MI.getOperand(0).getReg();
2514     Register PtrReg = MI.getOperand(1).getReg();
2515     LLT DstTy = MRI.getType(DstReg);
2516     auto &MMO = **MI.memoperands_begin();
2517 
2518     if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
2519       if (MI.getOpcode() == TargetOpcode::G_LOAD) {
2520         // This load needs splitting into power of 2 sized loads.
2521         if (DstTy.isVector())
2522           return UnableToLegalize;
2523         if (isPowerOf2_32(DstTy.getSizeInBits()))
2524           return UnableToLegalize; // Don't know what we're being asked to do.
2525 
2526         // Our strategy here is to generate anyextending loads for the smaller
2527         // types up to next power-2 result type, and then combine the two larger
2528         // result values together, before truncating back down to the non-pow-2
2529         // type.
2530         // E.g. v1 = i24 load =>
2531         // v2 = i32 zextload (2 byte)
2532         // v3 = i32 load (1 byte)
2533         // v4 = i32 shl v3, 16
2534         // v5 = i32 or v4, v2
2535         // v1 = i24 trunc v5
2536         // By doing this we generate the correct truncate which should get
2537         // combined away as an artifact with a matching extend.
2538         uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits());
2539         uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize;
2540 
2541         MachineFunction &MF = MIRBuilder.getMF();
2542         MachineMemOperand *LargeMMO =
2543             MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2544         MachineMemOperand *SmallMMO = MF.getMachineMemOperand(
2545             &MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2546 
2547         LLT PtrTy = MRI.getType(PtrReg);
2548         unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits());
2549         LLT AnyExtTy = LLT::scalar(AnyExtSize);
2550         Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2551         Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2552         auto LargeLoad = MIRBuilder.buildLoadInstr(
2553             TargetOpcode::G_ZEXTLOAD, LargeLdReg, PtrReg, *LargeMMO);
2554 
2555         auto OffsetCst = MIRBuilder.buildConstant(
2556             LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8);
2557         Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2558         auto SmallPtr =
2559             MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2560         auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
2561                                               *SmallMMO);
2562 
2563         auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
2564         auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt);
2565         auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
2566         MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)});
2567         MI.eraseFromParent();
2568         return Legalized;
2569       }
2570       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
2571       MI.eraseFromParent();
2572       return Legalized;
2573     }
2574 
2575     if (DstTy.isScalar()) {
2576       Register TmpReg =
2577           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
2578       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
2579       switch (MI.getOpcode()) {
2580       default:
2581         llvm_unreachable("Unexpected opcode");
2582       case TargetOpcode::G_LOAD:
2583         MIRBuilder.buildExtOrTrunc(TargetOpcode::G_ANYEXT, DstReg, TmpReg);
2584         break;
2585       case TargetOpcode::G_SEXTLOAD:
2586         MIRBuilder.buildSExt(DstReg, TmpReg);
2587         break;
2588       case TargetOpcode::G_ZEXTLOAD:
2589         MIRBuilder.buildZExt(DstReg, TmpReg);
2590         break;
2591       }
2592       MI.eraseFromParent();
2593       return Legalized;
2594     }
2595 
2596     return UnableToLegalize;
2597   }
2598   case TargetOpcode::G_STORE: {
2599     // Lower a non-power of 2 store into multiple pow-2 stores.
2600     // E.g. split an i24 store into an i16 store + i8 store.
2601     // We do this by first extending the stored value to the next largest power
2602     // of 2 type, and then using truncating stores to store the components.
2603     // By doing this, likewise with G_LOAD, generate an extend that can be
2604     // artifact-combined away instead of leaving behind extracts.
2605     Register SrcReg = MI.getOperand(0).getReg();
2606     Register PtrReg = MI.getOperand(1).getReg();
2607     LLT SrcTy = MRI.getType(SrcReg);
2608     MachineMemOperand &MMO = **MI.memoperands_begin();
2609     if (SrcTy.getSizeInBits() != MMO.getSizeInBits())
2610       return UnableToLegalize;
2611     if (SrcTy.isVector())
2612       return UnableToLegalize;
2613     if (isPowerOf2_32(SrcTy.getSizeInBits()))
2614       return UnableToLegalize; // Don't know what we're being asked to do.
2615 
2616     // Extend to the next pow-2.
2617     const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits()));
2618     auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg);
2619 
2620     // Obtain the smaller value by shifting away the larger value.
2621     uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits());
2622     uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize;
2623     auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize);
2624     auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt);
2625 
2626     // Generate the PtrAdd and truncating stores.
2627     LLT PtrTy = MRI.getType(PtrReg);
2628     auto OffsetCst = MIRBuilder.buildConstant(
2629             LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8);
2630     Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2631     auto SmallPtr =
2632         MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2633 
2634     MachineFunction &MF = MIRBuilder.getMF();
2635     MachineMemOperand *LargeMMO =
2636         MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2637     MachineMemOperand *SmallMMO =
2638         MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2639     MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO);
2640     MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO);
2641     MI.eraseFromParent();
2642     return Legalized;
2643   }
2644   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
2645   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
2646   case TargetOpcode::G_CTLZ:
2647   case TargetOpcode::G_CTTZ:
2648   case TargetOpcode::G_CTPOP:
2649     return lowerBitCount(MI, TypeIdx, Ty);
2650   case G_UADDO: {
2651     Register Res = MI.getOperand(0).getReg();
2652     Register CarryOut = MI.getOperand(1).getReg();
2653     Register LHS = MI.getOperand(2).getReg();
2654     Register RHS = MI.getOperand(3).getReg();
2655 
2656     MIRBuilder.buildAdd(Res, LHS, RHS);
2657     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
2658 
2659     MI.eraseFromParent();
2660     return Legalized;
2661   }
2662   case G_UADDE: {
2663     Register Res = MI.getOperand(0).getReg();
2664     Register CarryOut = MI.getOperand(1).getReg();
2665     Register LHS = MI.getOperand(2).getReg();
2666     Register RHS = MI.getOperand(3).getReg();
2667     Register CarryIn = MI.getOperand(4).getReg();
2668     LLT Ty = MRI.getType(Res);
2669 
2670     auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS);
2671     auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn);
2672     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
2673     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
2674 
2675     MI.eraseFromParent();
2676     return Legalized;
2677   }
2678   case G_USUBO: {
2679     Register Res = MI.getOperand(0).getReg();
2680     Register BorrowOut = MI.getOperand(1).getReg();
2681     Register LHS = MI.getOperand(2).getReg();
2682     Register RHS = MI.getOperand(3).getReg();
2683 
2684     MIRBuilder.buildSub(Res, LHS, RHS);
2685     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
2686 
2687     MI.eraseFromParent();
2688     return Legalized;
2689   }
2690   case G_USUBE: {
2691     Register Res = MI.getOperand(0).getReg();
2692     Register BorrowOut = MI.getOperand(1).getReg();
2693     Register LHS = MI.getOperand(2).getReg();
2694     Register RHS = MI.getOperand(3).getReg();
2695     Register BorrowIn = MI.getOperand(4).getReg();
2696     const LLT CondTy = MRI.getType(BorrowOut);
2697     const LLT Ty = MRI.getType(Res);
2698 
2699     auto TmpRes = MIRBuilder.buildSub(Ty, LHS, RHS);
2700     auto ZExtBorrowIn = MIRBuilder.buildZExt(Ty, BorrowIn);
2701     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
2702 
2703     auto LHS_EQ_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, LHS, RHS);
2704     auto LHS_ULT_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, LHS, RHS);
2705     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
2706 
2707     MI.eraseFromParent();
2708     return Legalized;
2709   }
2710   case G_UITOFP:
2711     return lowerUITOFP(MI, TypeIdx, Ty);
2712   case G_SITOFP:
2713     return lowerSITOFP(MI, TypeIdx, Ty);
2714   case G_FPTOUI:
2715     return lowerFPTOUI(MI, TypeIdx, Ty);
2716   case G_FPTOSI:
2717     return lowerFPTOSI(MI);
2718   case G_FPTRUNC:
2719     return lowerFPTRUNC(MI, TypeIdx, Ty);
2720   case G_FPOWI:
2721     return lowerFPOWI(MI);
2722   case G_SMIN:
2723   case G_SMAX:
2724   case G_UMIN:
2725   case G_UMAX:
2726     return lowerMinMax(MI, TypeIdx, Ty);
2727   case G_FCOPYSIGN:
2728     return lowerFCopySign(MI, TypeIdx, Ty);
2729   case G_FMINNUM:
2730   case G_FMAXNUM:
2731     return lowerFMinNumMaxNum(MI);
2732   case G_MERGE_VALUES:
2733     return lowerMergeValues(MI);
2734   case G_UNMERGE_VALUES:
2735     return lowerUnmergeValues(MI);
2736   case TargetOpcode::G_SEXT_INREG: {
2737     assert(MI.getOperand(2).isImm() && "Expected immediate");
2738     int64_t SizeInBits = MI.getOperand(2).getImm();
2739 
2740     Register DstReg = MI.getOperand(0).getReg();
2741     Register SrcReg = MI.getOperand(1).getReg();
2742     LLT DstTy = MRI.getType(DstReg);
2743     Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
2744 
2745     auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
2746     MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0));
2747     MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0));
2748     MI.eraseFromParent();
2749     return Legalized;
2750   }
2751   case G_EXTRACT_VECTOR_ELT:
2752     return lowerExtractVectorElt(MI);
2753   case G_SHUFFLE_VECTOR:
2754     return lowerShuffleVector(MI);
2755   case G_DYN_STACKALLOC:
2756     return lowerDynStackAlloc(MI);
2757   case G_EXTRACT:
2758     return lowerExtract(MI);
2759   case G_INSERT:
2760     return lowerInsert(MI);
2761   case G_BSWAP:
2762     return lowerBswap(MI);
2763   case G_BITREVERSE:
2764     return lowerBitreverse(MI);
2765   case G_READ_REGISTER:
2766   case G_WRITE_REGISTER:
2767     return lowerReadWriteRegister(MI);
2768   case G_UADDSAT:
2769   case G_USUBSAT: {
2770     // Try to make a reasonable guess about which lowering strategy to use. The
2771     // target can override this with custom lowering and calling the
2772     // implementation functions.
2773     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
2774     if (LI.isLegalOrCustom({G_UMIN, Ty}))
2775       return lowerAddSubSatToMinMax(MI);
2776     return lowerAddSubSatToAddoSubo(MI);
2777   }
2778   case G_SADDSAT:
2779   case G_SSUBSAT: {
2780     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
2781 
2782     // FIXME: It would probably make more sense to see if G_SADDO is preferred,
2783     // since it's a shorter expansion. However, we would need to figure out the
2784     // preferred boolean type for the carry out for the query.
2785     if (LI.isLegalOrCustom({G_SMIN, Ty}) && LI.isLegalOrCustom({G_SMAX, Ty}))
2786       return lowerAddSubSatToMinMax(MI);
2787     return lowerAddSubSatToAddoSubo(MI);
2788   }
2789   }
2790 }
2791 
2792 Align LegalizerHelper::getStackTemporaryAlignment(LLT Ty,
2793                                                   Align MinAlign) const {
2794   // FIXME: We're missing a way to go back from LLT to llvm::Type to query the
2795   // datalayout for the preferred alignment. Also there should be a target hook
2796   // for this to allow targets to reduce the alignment and ignore the
2797   // datalayout. e.g. AMDGPU should always use a 4-byte alignment, regardless of
2798   // the type.
2799   return std::max(Align(PowerOf2Ceil(Ty.getSizeInBytes())), MinAlign);
2800 }
2801 
2802 MachineInstrBuilder
2803 LegalizerHelper::createStackTemporary(TypeSize Bytes, Align Alignment,
2804                                       MachinePointerInfo &PtrInfo) {
2805   MachineFunction &MF = MIRBuilder.getMF();
2806   const DataLayout &DL = MIRBuilder.getDataLayout();
2807   int FrameIdx = MF.getFrameInfo().CreateStackObject(Bytes, Alignment, false);
2808 
2809   unsigned AddrSpace = DL.getAllocaAddrSpace();
2810   LLT FramePtrTy = LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace));
2811 
2812   PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIdx);
2813   return MIRBuilder.buildFrameIndex(FramePtrTy, FrameIdx);
2814 }
2815 
2816 static Register clampDynamicVectorIndex(MachineIRBuilder &B, Register IdxReg,
2817                                         LLT VecTy) {
2818   int64_t IdxVal;
2819   if (mi_match(IdxReg, *B.getMRI(), m_ICst(IdxVal)))
2820     return IdxReg;
2821 
2822   LLT IdxTy = B.getMRI()->getType(IdxReg);
2823   unsigned NElts = VecTy.getNumElements();
2824   if (isPowerOf2_32(NElts)) {
2825     APInt Imm = APInt::getLowBitsSet(IdxTy.getSizeInBits(), Log2_32(NElts));
2826     return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0);
2827   }
2828 
2829   return B.buildUMin(IdxTy, IdxReg, B.buildConstant(IdxTy, NElts - 1))
2830       .getReg(0);
2831 }
2832 
2833 Register LegalizerHelper::getVectorElementPointer(Register VecPtr, LLT VecTy,
2834                                                   Register Index) {
2835   LLT EltTy = VecTy.getElementType();
2836 
2837   // Calculate the element offset and add it to the pointer.
2838   unsigned EltSize = EltTy.getSizeInBits() / 8; // FIXME: should be ABI size.
2839   assert(EltSize * 8 == EltTy.getSizeInBits() &&
2840          "Converting bits to bytes lost precision");
2841 
2842   Index = clampDynamicVectorIndex(MIRBuilder, Index, VecTy);
2843 
2844   LLT IdxTy = MRI.getType(Index);
2845   auto Mul = MIRBuilder.buildMul(IdxTy, Index,
2846                                  MIRBuilder.buildConstant(IdxTy, EltSize));
2847 
2848   LLT PtrTy = MRI.getType(VecPtr);
2849   return MIRBuilder.buildPtrAdd(PtrTy, VecPtr, Mul).getReg(0);
2850 }
2851 
2852 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
2853     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
2854   SmallVector<Register, 2> DstRegs;
2855 
2856   unsigned NarrowSize = NarrowTy.getSizeInBits();
2857   Register DstReg = MI.getOperand(0).getReg();
2858   unsigned Size = MRI.getType(DstReg).getSizeInBits();
2859   int NumParts = Size / NarrowSize;
2860   // FIXME: Don't know how to handle the situation where the small vectors
2861   // aren't all the same size yet.
2862   if (Size % NarrowSize != 0)
2863     return UnableToLegalize;
2864 
2865   for (int i = 0; i < NumParts; ++i) {
2866     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
2867     MIRBuilder.buildUndef(TmpReg);
2868     DstRegs.push_back(TmpReg);
2869   }
2870 
2871   if (NarrowTy.isVector())
2872     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2873   else
2874     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2875 
2876   MI.eraseFromParent();
2877   return Legalized;
2878 }
2879 
2880 // Handle splitting vector operations which need to have the same number of
2881 // elements in each type index, but each type index may have a different element
2882 // type.
2883 //
2884 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
2885 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2886 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2887 //
2888 // Also handles some irregular breakdown cases, e.g.
2889 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
2890 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2891 //             s64 = G_SHL s64, s32
2892 LegalizerHelper::LegalizeResult
2893 LegalizerHelper::fewerElementsVectorMultiEltType(
2894   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
2895   if (TypeIdx != 0)
2896     return UnableToLegalize;
2897 
2898   const LLT NarrowTy0 = NarrowTyArg;
2899   const unsigned NewNumElts =
2900       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
2901 
2902   const Register DstReg = MI.getOperand(0).getReg();
2903   LLT DstTy = MRI.getType(DstReg);
2904   LLT LeftoverTy0;
2905 
2906   // All of the operands need to have the same number of elements, so if we can
2907   // determine a type breakdown for the result type, we can for all of the
2908   // source types.
2909   int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first;
2910   if (NumParts < 0)
2911     return UnableToLegalize;
2912 
2913   SmallVector<MachineInstrBuilder, 4> NewInsts;
2914 
2915   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2916   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2917 
2918   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2919     Register SrcReg = MI.getOperand(I).getReg();
2920     LLT SrcTyI = MRI.getType(SrcReg);
2921     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
2922     LLT LeftoverTyI;
2923 
2924     // Split this operand into the requested typed registers, and any leftover
2925     // required to reproduce the original type.
2926     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
2927                       LeftoverRegs))
2928       return UnableToLegalize;
2929 
2930     if (I == 1) {
2931       // For the first operand, create an instruction for each part and setup
2932       // the result.
2933       for (Register PartReg : PartRegs) {
2934         Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2935         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2936                                .addDef(PartDstReg)
2937                                .addUse(PartReg));
2938         DstRegs.push_back(PartDstReg);
2939       }
2940 
2941       for (Register LeftoverReg : LeftoverRegs) {
2942         Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
2943         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2944                                .addDef(PartDstReg)
2945                                .addUse(LeftoverReg));
2946         LeftoverDstRegs.push_back(PartDstReg);
2947       }
2948     } else {
2949       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
2950 
2951       // Add the newly created operand splits to the existing instructions. The
2952       // odd-sized pieces are ordered after the requested NarrowTyArg sized
2953       // pieces.
2954       unsigned InstCount = 0;
2955       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
2956         NewInsts[InstCount++].addUse(PartRegs[J]);
2957       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
2958         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
2959     }
2960 
2961     PartRegs.clear();
2962     LeftoverRegs.clear();
2963   }
2964 
2965   // Insert the newly built operations and rebuild the result register.
2966   for (auto &MIB : NewInsts)
2967     MIRBuilder.insertInstr(MIB);
2968 
2969   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
2970 
2971   MI.eraseFromParent();
2972   return Legalized;
2973 }
2974 
2975 LegalizerHelper::LegalizeResult
2976 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
2977                                           LLT NarrowTy) {
2978   if (TypeIdx != 0)
2979     return UnableToLegalize;
2980 
2981   Register DstReg = MI.getOperand(0).getReg();
2982   Register SrcReg = MI.getOperand(1).getReg();
2983   LLT DstTy = MRI.getType(DstReg);
2984   LLT SrcTy = MRI.getType(SrcReg);
2985 
2986   LLT NarrowTy0 = NarrowTy;
2987   LLT NarrowTy1;
2988   unsigned NumParts;
2989 
2990   if (NarrowTy.isVector()) {
2991     // Uneven breakdown not handled.
2992     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
2993     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
2994       return UnableToLegalize;
2995 
2996     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
2997   } else {
2998     NumParts = DstTy.getNumElements();
2999     NarrowTy1 = SrcTy.getElementType();
3000   }
3001 
3002   SmallVector<Register, 4> SrcRegs, DstRegs;
3003   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
3004 
3005   for (unsigned I = 0; I < NumParts; ++I) {
3006     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
3007     MachineInstr *NewInst =
3008         MIRBuilder.buildInstr(MI.getOpcode(), {DstReg}, {SrcRegs[I]});
3009 
3010     NewInst->setFlags(MI.getFlags());
3011     DstRegs.push_back(DstReg);
3012   }
3013 
3014   if (NarrowTy.isVector())
3015     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
3016   else
3017     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3018 
3019   MI.eraseFromParent();
3020   return Legalized;
3021 }
3022 
3023 LegalizerHelper::LegalizeResult
3024 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
3025                                         LLT NarrowTy) {
3026   Register DstReg = MI.getOperand(0).getReg();
3027   Register Src0Reg = MI.getOperand(2).getReg();
3028   LLT DstTy = MRI.getType(DstReg);
3029   LLT SrcTy = MRI.getType(Src0Reg);
3030 
3031   unsigned NumParts;
3032   LLT NarrowTy0, NarrowTy1;
3033 
3034   if (TypeIdx == 0) {
3035     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
3036     unsigned OldElts = DstTy.getNumElements();
3037 
3038     NarrowTy0 = NarrowTy;
3039     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
3040     NarrowTy1 = NarrowTy.isVector() ?
3041       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
3042       SrcTy.getElementType();
3043 
3044   } else {
3045     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
3046     unsigned OldElts = SrcTy.getNumElements();
3047 
3048     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
3049       NarrowTy.getNumElements();
3050     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
3051                             DstTy.getScalarSizeInBits());
3052     NarrowTy1 = NarrowTy;
3053   }
3054 
3055   // FIXME: Don't know how to handle the situation where the small vectors
3056   // aren't all the same size yet.
3057   if (NarrowTy1.isVector() &&
3058       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
3059     return UnableToLegalize;
3060 
3061   CmpInst::Predicate Pred
3062     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
3063 
3064   SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
3065   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
3066   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
3067 
3068   for (unsigned I = 0; I < NumParts; ++I) {
3069     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
3070     DstRegs.push_back(DstReg);
3071 
3072     if (MI.getOpcode() == TargetOpcode::G_ICMP)
3073       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
3074     else {
3075       MachineInstr *NewCmp
3076         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
3077       NewCmp->setFlags(MI.getFlags());
3078     }
3079   }
3080 
3081   if (NarrowTy1.isVector())
3082     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
3083   else
3084     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3085 
3086   MI.eraseFromParent();
3087   return Legalized;
3088 }
3089 
3090 LegalizerHelper::LegalizeResult
3091 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
3092                                            LLT NarrowTy) {
3093   Register DstReg = MI.getOperand(0).getReg();
3094   Register CondReg = MI.getOperand(1).getReg();
3095 
3096   unsigned NumParts = 0;
3097   LLT NarrowTy0, NarrowTy1;
3098 
3099   LLT DstTy = MRI.getType(DstReg);
3100   LLT CondTy = MRI.getType(CondReg);
3101   unsigned Size = DstTy.getSizeInBits();
3102 
3103   assert(TypeIdx == 0 || CondTy.isVector());
3104 
3105   if (TypeIdx == 0) {
3106     NarrowTy0 = NarrowTy;
3107     NarrowTy1 = CondTy;
3108 
3109     unsigned NarrowSize = NarrowTy0.getSizeInBits();
3110     // FIXME: Don't know how to handle the situation where the small vectors
3111     // aren't all the same size yet.
3112     if (Size % NarrowSize != 0)
3113       return UnableToLegalize;
3114 
3115     NumParts = Size / NarrowSize;
3116 
3117     // Need to break down the condition type
3118     if (CondTy.isVector()) {
3119       if (CondTy.getNumElements() == NumParts)
3120         NarrowTy1 = CondTy.getElementType();
3121       else
3122         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
3123                                 CondTy.getScalarSizeInBits());
3124     }
3125   } else {
3126     NumParts = CondTy.getNumElements();
3127     if (NarrowTy.isVector()) {
3128       // TODO: Handle uneven breakdown.
3129       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
3130         return UnableToLegalize;
3131 
3132       return UnableToLegalize;
3133     } else {
3134       NarrowTy0 = DstTy.getElementType();
3135       NarrowTy1 = NarrowTy;
3136     }
3137   }
3138 
3139   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
3140   if (CondTy.isVector())
3141     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
3142 
3143   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
3144   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
3145 
3146   for (unsigned i = 0; i < NumParts; ++i) {
3147     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
3148     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
3149                            Src1Regs[i], Src2Regs[i]);
3150     DstRegs.push_back(DstReg);
3151   }
3152 
3153   if (NarrowTy0.isVector())
3154     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
3155   else
3156     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3157 
3158   MI.eraseFromParent();
3159   return Legalized;
3160 }
3161 
3162 LegalizerHelper::LegalizeResult
3163 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
3164                                         LLT NarrowTy) {
3165   const Register DstReg = MI.getOperand(0).getReg();
3166   LLT PhiTy = MRI.getType(DstReg);
3167   LLT LeftoverTy;
3168 
3169   // All of the operands need to have the same number of elements, so if we can
3170   // determine a type breakdown for the result type, we can for all of the
3171   // source types.
3172   int NumParts, NumLeftover;
3173   std::tie(NumParts, NumLeftover)
3174     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
3175   if (NumParts < 0)
3176     return UnableToLegalize;
3177 
3178   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
3179   SmallVector<MachineInstrBuilder, 4> NewInsts;
3180 
3181   const int TotalNumParts = NumParts + NumLeftover;
3182 
3183   // Insert the new phis in the result block first.
3184   for (int I = 0; I != TotalNumParts; ++I) {
3185     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
3186     Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
3187     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
3188                        .addDef(PartDstReg));
3189     if (I < NumParts)
3190       DstRegs.push_back(PartDstReg);
3191     else
3192       LeftoverDstRegs.push_back(PartDstReg);
3193   }
3194 
3195   MachineBasicBlock *MBB = MI.getParent();
3196   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
3197   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
3198 
3199   SmallVector<Register, 4> PartRegs, LeftoverRegs;
3200 
3201   // Insert code to extract the incoming values in each predecessor block.
3202   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
3203     PartRegs.clear();
3204     LeftoverRegs.clear();
3205 
3206     Register SrcReg = MI.getOperand(I).getReg();
3207     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
3208     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
3209 
3210     LLT Unused;
3211     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
3212                       LeftoverRegs))
3213       return UnableToLegalize;
3214 
3215     // Add the newly created operand splits to the existing instructions. The
3216     // odd-sized pieces are ordered after the requested NarrowTyArg sized
3217     // pieces.
3218     for (int J = 0; J != TotalNumParts; ++J) {
3219       MachineInstrBuilder MIB = NewInsts[J];
3220       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
3221       MIB.addMBB(&OpMBB);
3222     }
3223   }
3224 
3225   MI.eraseFromParent();
3226   return Legalized;
3227 }
3228 
3229 LegalizerHelper::LegalizeResult
3230 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
3231                                                   unsigned TypeIdx,
3232                                                   LLT NarrowTy) {
3233   if (TypeIdx != 1)
3234     return UnableToLegalize;
3235 
3236   const int NumDst = MI.getNumOperands() - 1;
3237   const Register SrcReg = MI.getOperand(NumDst).getReg();
3238   LLT SrcTy = MRI.getType(SrcReg);
3239 
3240   LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
3241 
3242   // TODO: Create sequence of extracts.
3243   if (DstTy == NarrowTy)
3244     return UnableToLegalize;
3245 
3246   LLT GCDTy = getGCDType(SrcTy, NarrowTy);
3247   if (DstTy == GCDTy) {
3248     // This would just be a copy of the same unmerge.
3249     // TODO: Create extracts, pad with undef and create intermediate merges.
3250     return UnableToLegalize;
3251   }
3252 
3253   auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
3254   const int NumUnmerge = Unmerge->getNumOperands() - 1;
3255   const int PartsPerUnmerge = NumDst / NumUnmerge;
3256 
3257   for (int I = 0; I != NumUnmerge; ++I) {
3258     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
3259 
3260     for (int J = 0; J != PartsPerUnmerge; ++J)
3261       MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg());
3262     MIB.addUse(Unmerge.getReg(I));
3263   }
3264 
3265   MI.eraseFromParent();
3266   return Legalized;
3267 }
3268 
3269 LegalizerHelper::LegalizeResult
3270 LegalizerHelper::fewerElementsVectorBuildVector(MachineInstr &MI,
3271                                                 unsigned TypeIdx,
3272                                                 LLT NarrowTy) {
3273   assert(TypeIdx == 0 && "not a vector type index");
3274   Register DstReg = MI.getOperand(0).getReg();
3275   LLT DstTy = MRI.getType(DstReg);
3276   LLT SrcTy = DstTy.getElementType();
3277 
3278   int DstNumElts = DstTy.getNumElements();
3279   int NarrowNumElts = NarrowTy.getNumElements();
3280   int NumConcat = (DstNumElts + NarrowNumElts - 1) / NarrowNumElts;
3281   LLT WidenedDstTy = LLT::vector(NarrowNumElts * NumConcat, SrcTy);
3282 
3283   SmallVector<Register, 8> ConcatOps;
3284   SmallVector<Register, 8> SubBuildVector;
3285 
3286   Register UndefReg;
3287   if (WidenedDstTy != DstTy)
3288     UndefReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
3289 
3290   // Create a G_CONCAT_VECTORS of NarrowTy pieces, padding with undef as
3291   // necessary.
3292   //
3293   // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2
3294   //   -> <2 x s16>
3295   //
3296   // %4:_(s16) = G_IMPLICIT_DEF
3297   // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1
3298   // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4
3299   // %7:_(<4 x s16>) = G_CONCAT_VECTORS %5, %6
3300   // %3:_(<3 x s16>) = G_EXTRACT %7, 0
3301   for (int I = 0; I != NumConcat; ++I) {
3302     for (int J = 0; J != NarrowNumElts; ++J) {
3303       int SrcIdx = NarrowNumElts * I + J;
3304 
3305       if (SrcIdx < DstNumElts) {
3306         Register SrcReg = MI.getOperand(SrcIdx + 1).getReg();
3307         SubBuildVector.push_back(SrcReg);
3308       } else
3309         SubBuildVector.push_back(UndefReg);
3310     }
3311 
3312     auto BuildVec = MIRBuilder.buildBuildVector(NarrowTy, SubBuildVector);
3313     ConcatOps.push_back(BuildVec.getReg(0));
3314     SubBuildVector.clear();
3315   }
3316 
3317   if (DstTy == WidenedDstTy)
3318     MIRBuilder.buildConcatVectors(DstReg, ConcatOps);
3319   else {
3320     auto Concat = MIRBuilder.buildConcatVectors(WidenedDstTy, ConcatOps);
3321     MIRBuilder.buildExtract(DstReg, Concat, 0);
3322   }
3323 
3324   MI.eraseFromParent();
3325   return Legalized;
3326 }
3327 
3328 LegalizerHelper::LegalizeResult
3329 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
3330                                       LLT NarrowTy) {
3331   // FIXME: Don't know how to handle secondary types yet.
3332   if (TypeIdx != 0)
3333     return UnableToLegalize;
3334 
3335   MachineMemOperand *MMO = *MI.memoperands_begin();
3336 
3337   // This implementation doesn't work for atomics. Give up instead of doing
3338   // something invalid.
3339   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
3340       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
3341     return UnableToLegalize;
3342 
3343   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
3344   Register ValReg = MI.getOperand(0).getReg();
3345   Register AddrReg = MI.getOperand(1).getReg();
3346   LLT ValTy = MRI.getType(ValReg);
3347 
3348   // FIXME: Do we need a distinct NarrowMemory legalize action?
3349   if (ValTy.getSizeInBits() != 8 * MMO->getSize()) {
3350     LLVM_DEBUG(dbgs() << "Can't narrow extload/truncstore\n");
3351     return UnableToLegalize;
3352   }
3353 
3354   int NumParts = -1;
3355   int NumLeftover = -1;
3356   LLT LeftoverTy;
3357   SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
3358   if (IsLoad) {
3359     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
3360   } else {
3361     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
3362                      NarrowLeftoverRegs)) {
3363       NumParts = NarrowRegs.size();
3364       NumLeftover = NarrowLeftoverRegs.size();
3365     }
3366   }
3367 
3368   if (NumParts == -1)
3369     return UnableToLegalize;
3370 
3371   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
3372 
3373   unsigned TotalSize = ValTy.getSizeInBits();
3374 
3375   // Split the load/store into PartTy sized pieces starting at Offset. If this
3376   // is a load, return the new registers in ValRegs. For a store, each elements
3377   // of ValRegs should be PartTy. Returns the next offset that needs to be
3378   // handled.
3379   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
3380                              unsigned Offset) -> unsigned {
3381     MachineFunction &MF = MIRBuilder.getMF();
3382     unsigned PartSize = PartTy.getSizeInBits();
3383     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
3384          Offset += PartSize, ++Idx) {
3385       unsigned ByteSize = PartSize / 8;
3386       unsigned ByteOffset = Offset / 8;
3387       Register NewAddrReg;
3388 
3389       MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
3390 
3391       MachineMemOperand *NewMMO =
3392         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
3393 
3394       if (IsLoad) {
3395         Register Dst = MRI.createGenericVirtualRegister(PartTy);
3396         ValRegs.push_back(Dst);
3397         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
3398       } else {
3399         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
3400       }
3401     }
3402 
3403     return Offset;
3404   };
3405 
3406   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
3407 
3408   // Handle the rest of the register if this isn't an even type breakdown.
3409   if (LeftoverTy.isValid())
3410     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
3411 
3412   if (IsLoad) {
3413     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
3414                 LeftoverTy, NarrowLeftoverRegs);
3415   }
3416 
3417   MI.eraseFromParent();
3418   return Legalized;
3419 }
3420 
3421 LegalizerHelper::LegalizeResult
3422 LegalizerHelper::reduceOperationWidth(MachineInstr &MI, unsigned int TypeIdx,
3423                                       LLT NarrowTy) {
3424   assert(TypeIdx == 0 && "only one type index expected");
3425 
3426   const unsigned Opc = MI.getOpcode();
3427   const int NumOps = MI.getNumOperands() - 1;
3428   const Register DstReg = MI.getOperand(0).getReg();
3429   const unsigned Flags = MI.getFlags();
3430   const unsigned NarrowSize = NarrowTy.getSizeInBits();
3431   const LLT NarrowScalarTy = LLT::scalar(NarrowSize);
3432 
3433   assert(NumOps <= 3 && "expected instruction with 1 result and 1-3 sources");
3434 
3435   // First of all check whether we are narrowing (changing the element type)
3436   // or reducing the vector elements
3437   const LLT DstTy = MRI.getType(DstReg);
3438   const bool IsNarrow = NarrowTy.getScalarType() != DstTy.getScalarType();
3439 
3440   SmallVector<Register, 8> ExtractedRegs[3];
3441   SmallVector<Register, 8> Parts;
3442 
3443   unsigned NarrowElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
3444 
3445   // Break down all the sources into NarrowTy pieces we can operate on. This may
3446   // involve creating merges to a wider type, padded with undef.
3447   for (int I = 0; I != NumOps; ++I) {
3448     Register SrcReg = MI.getOperand(I + 1).getReg();
3449     LLT SrcTy = MRI.getType(SrcReg);
3450 
3451     // The type to narrow SrcReg to. For narrowing, this is a smaller scalar.
3452     // For fewerElements, this is a smaller vector with the same element type.
3453     LLT OpNarrowTy;
3454     if (IsNarrow) {
3455       OpNarrowTy = NarrowScalarTy;
3456 
3457       // In case of narrowing, we need to cast vectors to scalars for this to
3458       // work properly
3459       // FIXME: Can we do without the bitcast here if we're narrowing?
3460       if (SrcTy.isVector()) {
3461         SrcTy = LLT::scalar(SrcTy.getSizeInBits());
3462         SrcReg = MIRBuilder.buildBitcast(SrcTy, SrcReg).getReg(0);
3463       }
3464     } else {
3465       OpNarrowTy = LLT::scalarOrVector(NarrowElts, SrcTy.getScalarType());
3466     }
3467 
3468     LLT GCDTy = extractGCDType(ExtractedRegs[I], SrcTy, OpNarrowTy, SrcReg);
3469 
3470     // Build a sequence of NarrowTy pieces in ExtractedRegs for this operand.
3471     buildLCMMergePieces(SrcTy, OpNarrowTy, GCDTy, ExtractedRegs[I],
3472                         TargetOpcode::G_ANYEXT);
3473   }
3474 
3475   SmallVector<Register, 8> ResultRegs;
3476 
3477   // Input operands for each sub-instruction.
3478   SmallVector<SrcOp, 4> InputRegs(NumOps, Register());
3479 
3480   int NumParts = ExtractedRegs[0].size();
3481   const unsigned DstSize = DstTy.getSizeInBits();
3482   const LLT DstScalarTy = LLT::scalar(DstSize);
3483 
3484   // Narrowing needs to use scalar types
3485   LLT DstLCMTy, NarrowDstTy;
3486   if (IsNarrow) {
3487     DstLCMTy = getLCMType(DstScalarTy, NarrowScalarTy);
3488     NarrowDstTy = NarrowScalarTy;
3489   } else {
3490     DstLCMTy = getLCMType(DstTy, NarrowTy);
3491     NarrowDstTy = NarrowTy;
3492   }
3493 
3494   // We widened the source registers to satisfy merge/unmerge size
3495   // constraints. We'll have some extra fully undef parts.
3496   const int NumRealParts = (DstSize + NarrowSize - 1) / NarrowSize;
3497 
3498   for (int I = 0; I != NumRealParts; ++I) {
3499     // Emit this instruction on each of the split pieces.
3500     for (int J = 0; J != NumOps; ++J)
3501       InputRegs[J] = ExtractedRegs[J][I];
3502 
3503     auto Inst = MIRBuilder.buildInstr(Opc, {NarrowDstTy}, InputRegs, Flags);
3504     ResultRegs.push_back(Inst.getReg(0));
3505   }
3506 
3507   // Fill out the widened result with undef instead of creating instructions
3508   // with undef inputs.
3509   int NumUndefParts = NumParts - NumRealParts;
3510   if (NumUndefParts != 0)
3511     ResultRegs.append(NumUndefParts,
3512                       MIRBuilder.buildUndef(NarrowDstTy).getReg(0));
3513 
3514   // Extract the possibly padded result. Use a scratch register if we need to do
3515   // a final bitcast, otherwise use the original result register.
3516   Register MergeDstReg;
3517   if (IsNarrow && DstTy.isVector())
3518     MergeDstReg = MRI.createGenericVirtualRegister(DstScalarTy);
3519   else
3520     MergeDstReg = DstReg;
3521 
3522   buildWidenedRemergeToDst(MergeDstReg, DstLCMTy, ResultRegs);
3523 
3524   // Recast to vector if we narrowed a vector
3525   if (IsNarrow && DstTy.isVector())
3526     MIRBuilder.buildBitcast(DstReg, MergeDstReg);
3527 
3528   MI.eraseFromParent();
3529   return Legalized;
3530 }
3531 
3532 LegalizerHelper::LegalizeResult
3533 LegalizerHelper::fewerElementsVectorSextInReg(MachineInstr &MI, unsigned TypeIdx,
3534                                               LLT NarrowTy) {
3535   Register DstReg = MI.getOperand(0).getReg();
3536   Register SrcReg = MI.getOperand(1).getReg();
3537   int64_t Imm = MI.getOperand(2).getImm();
3538 
3539   LLT DstTy = MRI.getType(DstReg);
3540 
3541   SmallVector<Register, 8> Parts;
3542   LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg);
3543   LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts);
3544 
3545   for (Register &R : Parts)
3546     R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0);
3547 
3548   buildWidenedRemergeToDst(DstReg, LCMTy, Parts);
3549 
3550   MI.eraseFromParent();
3551   return Legalized;
3552 }
3553 
3554 LegalizerHelper::LegalizeResult
3555 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
3556                                      LLT NarrowTy) {
3557   using namespace TargetOpcode;
3558 
3559   switch (MI.getOpcode()) {
3560   case G_IMPLICIT_DEF:
3561     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
3562   case G_TRUNC:
3563   case G_AND:
3564   case G_OR:
3565   case G_XOR:
3566   case G_ADD:
3567   case G_SUB:
3568   case G_MUL:
3569   case G_PTR_ADD:
3570   case G_SMULH:
3571   case G_UMULH:
3572   case G_FADD:
3573   case G_FMUL:
3574   case G_FSUB:
3575   case G_FNEG:
3576   case G_FABS:
3577   case G_FCANONICALIZE:
3578   case G_FDIV:
3579   case G_FREM:
3580   case G_FMA:
3581   case G_FMAD:
3582   case G_FPOW:
3583   case G_FEXP:
3584   case G_FEXP2:
3585   case G_FLOG:
3586   case G_FLOG2:
3587   case G_FLOG10:
3588   case G_FNEARBYINT:
3589   case G_FCEIL:
3590   case G_FFLOOR:
3591   case G_FRINT:
3592   case G_INTRINSIC_ROUND:
3593   case G_INTRINSIC_ROUNDEVEN:
3594   case G_INTRINSIC_TRUNC:
3595   case G_FCOS:
3596   case G_FSIN:
3597   case G_FSQRT:
3598   case G_BSWAP:
3599   case G_BITREVERSE:
3600   case G_SDIV:
3601   case G_UDIV:
3602   case G_SREM:
3603   case G_UREM:
3604   case G_SMIN:
3605   case G_SMAX:
3606   case G_UMIN:
3607   case G_UMAX:
3608   case G_FMINNUM:
3609   case G_FMAXNUM:
3610   case G_FMINNUM_IEEE:
3611   case G_FMAXNUM_IEEE:
3612   case G_FMINIMUM:
3613   case G_FMAXIMUM:
3614   case G_FSHL:
3615   case G_FSHR:
3616   case G_FREEZE:
3617   case G_SADDSAT:
3618   case G_SSUBSAT:
3619   case G_UADDSAT:
3620   case G_USUBSAT:
3621     return reduceOperationWidth(MI, TypeIdx, NarrowTy);
3622   case G_SHL:
3623   case G_LSHR:
3624   case G_ASHR:
3625   case G_CTLZ:
3626   case G_CTLZ_ZERO_UNDEF:
3627   case G_CTTZ:
3628   case G_CTTZ_ZERO_UNDEF:
3629   case G_CTPOP:
3630   case G_FCOPYSIGN:
3631     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
3632   case G_ZEXT:
3633   case G_SEXT:
3634   case G_ANYEXT:
3635   case G_FPEXT:
3636   case G_FPTRUNC:
3637   case G_SITOFP:
3638   case G_UITOFP:
3639   case G_FPTOSI:
3640   case G_FPTOUI:
3641   case G_INTTOPTR:
3642   case G_PTRTOINT:
3643   case G_ADDRSPACE_CAST:
3644     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
3645   case G_ICMP:
3646   case G_FCMP:
3647     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
3648   case G_SELECT:
3649     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
3650   case G_PHI:
3651     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
3652   case G_UNMERGE_VALUES:
3653     return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy);
3654   case G_BUILD_VECTOR:
3655     return fewerElementsVectorBuildVector(MI, TypeIdx, NarrowTy);
3656   case G_LOAD:
3657   case G_STORE:
3658     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
3659   case G_SEXT_INREG:
3660     return fewerElementsVectorSextInReg(MI, TypeIdx, NarrowTy);
3661   default:
3662     return UnableToLegalize;
3663   }
3664 }
3665 
3666 LegalizerHelper::LegalizeResult
3667 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
3668                                              const LLT HalfTy, const LLT AmtTy) {
3669 
3670   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3671   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3672   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1));
3673 
3674   if (Amt.isNullValue()) {
3675     MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH});
3676     MI.eraseFromParent();
3677     return Legalized;
3678   }
3679 
3680   LLT NVT = HalfTy;
3681   unsigned NVTBits = HalfTy.getSizeInBits();
3682   unsigned VTBits = 2 * NVTBits;
3683 
3684   SrcOp Lo(Register(0)), Hi(Register(0));
3685   if (MI.getOpcode() == TargetOpcode::G_SHL) {
3686     if (Amt.ugt(VTBits)) {
3687       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3688     } else if (Amt.ugt(NVTBits)) {
3689       Lo = MIRBuilder.buildConstant(NVT, 0);
3690       Hi = MIRBuilder.buildShl(NVT, InL,
3691                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3692     } else if (Amt == NVTBits) {
3693       Lo = MIRBuilder.buildConstant(NVT, 0);
3694       Hi = InL;
3695     } else {
3696       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
3697       auto OrLHS =
3698           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
3699       auto OrRHS = MIRBuilder.buildLShr(
3700           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3701       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3702     }
3703   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3704     if (Amt.ugt(VTBits)) {
3705       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3706     } else if (Amt.ugt(NVTBits)) {
3707       Lo = MIRBuilder.buildLShr(NVT, InH,
3708                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3709       Hi = MIRBuilder.buildConstant(NVT, 0);
3710     } else if (Amt == NVTBits) {
3711       Lo = InH;
3712       Hi = MIRBuilder.buildConstant(NVT, 0);
3713     } else {
3714       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3715 
3716       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3717       auto OrRHS = MIRBuilder.buildShl(
3718           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3719 
3720       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3721       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
3722     }
3723   } else {
3724     if (Amt.ugt(VTBits)) {
3725       Hi = Lo = MIRBuilder.buildAShr(
3726           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3727     } else if (Amt.ugt(NVTBits)) {
3728       Lo = MIRBuilder.buildAShr(NVT, InH,
3729                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3730       Hi = MIRBuilder.buildAShr(NVT, InH,
3731                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3732     } else if (Amt == NVTBits) {
3733       Lo = InH;
3734       Hi = MIRBuilder.buildAShr(NVT, InH,
3735                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3736     } else {
3737       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3738 
3739       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3740       auto OrRHS = MIRBuilder.buildShl(
3741           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3742 
3743       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3744       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
3745     }
3746   }
3747 
3748   MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi});
3749   MI.eraseFromParent();
3750 
3751   return Legalized;
3752 }
3753 
3754 // TODO: Optimize if constant shift amount.
3755 LegalizerHelper::LegalizeResult
3756 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
3757                                    LLT RequestedTy) {
3758   if (TypeIdx == 1) {
3759     Observer.changingInstr(MI);
3760     narrowScalarSrc(MI, RequestedTy, 2);
3761     Observer.changedInstr(MI);
3762     return Legalized;
3763   }
3764 
3765   Register DstReg = MI.getOperand(0).getReg();
3766   LLT DstTy = MRI.getType(DstReg);
3767   if (DstTy.isVector())
3768     return UnableToLegalize;
3769 
3770   Register Amt = MI.getOperand(2).getReg();
3771   LLT ShiftAmtTy = MRI.getType(Amt);
3772   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
3773   if (DstEltSize % 2 != 0)
3774     return UnableToLegalize;
3775 
3776   // Ignore the input type. We can only go to exactly half the size of the
3777   // input. If that isn't small enough, the resulting pieces will be further
3778   // legalized.
3779   const unsigned NewBitSize = DstEltSize / 2;
3780   const LLT HalfTy = LLT::scalar(NewBitSize);
3781   const LLT CondTy = LLT::scalar(1);
3782 
3783   if (const MachineInstr *KShiftAmt =
3784           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
3785     return narrowScalarShiftByConstant(
3786         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
3787   }
3788 
3789   // TODO: Expand with known bits.
3790 
3791   // Handle the fully general expansion by an unknown amount.
3792   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
3793 
3794   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3795   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3796   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1));
3797 
3798   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
3799   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
3800 
3801   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
3802   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
3803   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
3804 
3805   Register ResultRegs[2];
3806   switch (MI.getOpcode()) {
3807   case TargetOpcode::G_SHL: {
3808     // Short: ShAmt < NewBitSize
3809     auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt);
3810 
3811     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
3812     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt);
3813     auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3814 
3815     // Long: ShAmt >= NewBitSize
3816     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
3817     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
3818 
3819     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
3820     auto Hi = MIRBuilder.buildSelect(
3821         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
3822 
3823     ResultRegs[0] = Lo.getReg(0);
3824     ResultRegs[1] = Hi.getReg(0);
3825     break;
3826   }
3827   case TargetOpcode::G_LSHR:
3828   case TargetOpcode::G_ASHR: {
3829     // Short: ShAmt < NewBitSize
3830     auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt});
3831 
3832     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt);
3833     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
3834     auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3835 
3836     // Long: ShAmt >= NewBitSize
3837     MachineInstrBuilder HiL;
3838     if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3839       HiL = MIRBuilder.buildConstant(HalfTy, 0);            // Hi part is zero.
3840     } else {
3841       auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1);
3842       HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt);    // Sign of Hi part.
3843     }
3844     auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy},
3845                                      {InH, AmtExcess});     // Lo from Hi part.
3846 
3847     auto Lo = MIRBuilder.buildSelect(
3848         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
3849 
3850     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
3851 
3852     ResultRegs[0] = Lo.getReg(0);
3853     ResultRegs[1] = Hi.getReg(0);
3854     break;
3855   }
3856   default:
3857     llvm_unreachable("not a shift");
3858   }
3859 
3860   MIRBuilder.buildMerge(DstReg, ResultRegs);
3861   MI.eraseFromParent();
3862   return Legalized;
3863 }
3864 
3865 LegalizerHelper::LegalizeResult
3866 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
3867                                        LLT MoreTy) {
3868   assert(TypeIdx == 0 && "Expecting only Idx 0");
3869 
3870   Observer.changingInstr(MI);
3871   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
3872     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
3873     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
3874     moreElementsVectorSrc(MI, MoreTy, I);
3875   }
3876 
3877   MachineBasicBlock &MBB = *MI.getParent();
3878   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
3879   moreElementsVectorDst(MI, MoreTy, 0);
3880   Observer.changedInstr(MI);
3881   return Legalized;
3882 }
3883 
3884 LegalizerHelper::LegalizeResult
3885 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
3886                                     LLT MoreTy) {
3887   unsigned Opc = MI.getOpcode();
3888   switch (Opc) {
3889   case TargetOpcode::G_IMPLICIT_DEF:
3890   case TargetOpcode::G_LOAD: {
3891     if (TypeIdx != 0)
3892       return UnableToLegalize;
3893     Observer.changingInstr(MI);
3894     moreElementsVectorDst(MI, MoreTy, 0);
3895     Observer.changedInstr(MI);
3896     return Legalized;
3897   }
3898   case TargetOpcode::G_STORE:
3899     if (TypeIdx != 0)
3900       return UnableToLegalize;
3901     Observer.changingInstr(MI);
3902     moreElementsVectorSrc(MI, MoreTy, 0);
3903     Observer.changedInstr(MI);
3904     return Legalized;
3905   case TargetOpcode::G_AND:
3906   case TargetOpcode::G_OR:
3907   case TargetOpcode::G_XOR:
3908   case TargetOpcode::G_SMIN:
3909   case TargetOpcode::G_SMAX:
3910   case TargetOpcode::G_UMIN:
3911   case TargetOpcode::G_UMAX:
3912   case TargetOpcode::G_FMINNUM:
3913   case TargetOpcode::G_FMAXNUM:
3914   case TargetOpcode::G_FMINNUM_IEEE:
3915   case TargetOpcode::G_FMAXNUM_IEEE:
3916   case TargetOpcode::G_FMINIMUM:
3917   case TargetOpcode::G_FMAXIMUM: {
3918     Observer.changingInstr(MI);
3919     moreElementsVectorSrc(MI, MoreTy, 1);
3920     moreElementsVectorSrc(MI, MoreTy, 2);
3921     moreElementsVectorDst(MI, MoreTy, 0);
3922     Observer.changedInstr(MI);
3923     return Legalized;
3924   }
3925   case TargetOpcode::G_EXTRACT:
3926     if (TypeIdx != 1)
3927       return UnableToLegalize;
3928     Observer.changingInstr(MI);
3929     moreElementsVectorSrc(MI, MoreTy, 1);
3930     Observer.changedInstr(MI);
3931     return Legalized;
3932   case TargetOpcode::G_INSERT:
3933   case TargetOpcode::G_FREEZE:
3934     if (TypeIdx != 0)
3935       return UnableToLegalize;
3936     Observer.changingInstr(MI);
3937     moreElementsVectorSrc(MI, MoreTy, 1);
3938     moreElementsVectorDst(MI, MoreTy, 0);
3939     Observer.changedInstr(MI);
3940     return Legalized;
3941   case TargetOpcode::G_SELECT:
3942     if (TypeIdx != 0)
3943       return UnableToLegalize;
3944     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
3945       return UnableToLegalize;
3946 
3947     Observer.changingInstr(MI);
3948     moreElementsVectorSrc(MI, MoreTy, 2);
3949     moreElementsVectorSrc(MI, MoreTy, 3);
3950     moreElementsVectorDst(MI, MoreTy, 0);
3951     Observer.changedInstr(MI);
3952     return Legalized;
3953   case TargetOpcode::G_UNMERGE_VALUES: {
3954     if (TypeIdx != 1)
3955       return UnableToLegalize;
3956 
3957     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
3958     int NumDst = MI.getNumOperands() - 1;
3959     moreElementsVectorSrc(MI, MoreTy, NumDst);
3960 
3961     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
3962     for (int I = 0; I != NumDst; ++I)
3963       MIB.addDef(MI.getOperand(I).getReg());
3964 
3965     int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits();
3966     for (int I = NumDst; I != NewNumDst; ++I)
3967       MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
3968 
3969     MIB.addUse(MI.getOperand(NumDst).getReg());
3970     MI.eraseFromParent();
3971     return Legalized;
3972   }
3973   case TargetOpcode::G_PHI:
3974     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
3975   default:
3976     return UnableToLegalize;
3977   }
3978 }
3979 
3980 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
3981                                         ArrayRef<Register> Src1Regs,
3982                                         ArrayRef<Register> Src2Regs,
3983                                         LLT NarrowTy) {
3984   MachineIRBuilder &B = MIRBuilder;
3985   unsigned SrcParts = Src1Regs.size();
3986   unsigned DstParts = DstRegs.size();
3987 
3988   unsigned DstIdx = 0; // Low bits of the result.
3989   Register FactorSum =
3990       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
3991   DstRegs[DstIdx] = FactorSum;
3992 
3993   unsigned CarrySumPrevDstIdx;
3994   SmallVector<Register, 4> Factors;
3995 
3996   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
3997     // Collect low parts of muls for DstIdx.
3998     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
3999          i <= std::min(DstIdx, SrcParts - 1); ++i) {
4000       MachineInstrBuilder Mul =
4001           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
4002       Factors.push_back(Mul.getReg(0));
4003     }
4004     // Collect high parts of muls from previous DstIdx.
4005     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
4006          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
4007       MachineInstrBuilder Umulh =
4008           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
4009       Factors.push_back(Umulh.getReg(0));
4010     }
4011     // Add CarrySum from additions calculated for previous DstIdx.
4012     if (DstIdx != 1) {
4013       Factors.push_back(CarrySumPrevDstIdx);
4014     }
4015 
4016     Register CarrySum;
4017     // Add all factors and accumulate all carries into CarrySum.
4018     if (DstIdx != DstParts - 1) {
4019       MachineInstrBuilder Uaddo =
4020           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
4021       FactorSum = Uaddo.getReg(0);
4022       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
4023       for (unsigned i = 2; i < Factors.size(); ++i) {
4024         MachineInstrBuilder Uaddo =
4025             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
4026         FactorSum = Uaddo.getReg(0);
4027         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
4028         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
4029       }
4030     } else {
4031       // Since value for the next index is not calculated, neither is CarrySum.
4032       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
4033       for (unsigned i = 2; i < Factors.size(); ++i)
4034         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
4035     }
4036 
4037     CarrySumPrevDstIdx = CarrySum;
4038     DstRegs[DstIdx] = FactorSum;
4039     Factors.clear();
4040   }
4041 }
4042 
4043 LegalizerHelper::LegalizeResult
4044 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
4045   Register DstReg = MI.getOperand(0).getReg();
4046   Register Src1 = MI.getOperand(1).getReg();
4047   Register Src2 = MI.getOperand(2).getReg();
4048 
4049   LLT Ty = MRI.getType(DstReg);
4050   if (Ty.isVector())
4051     return UnableToLegalize;
4052 
4053   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
4054   unsigned DstSize = Ty.getSizeInBits();
4055   unsigned NarrowSize = NarrowTy.getSizeInBits();
4056   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
4057     return UnableToLegalize;
4058 
4059   unsigned NumDstParts = DstSize / NarrowSize;
4060   unsigned NumSrcParts = SrcSize / NarrowSize;
4061   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
4062   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
4063 
4064   SmallVector<Register, 2> Src1Parts, Src2Parts;
4065   SmallVector<Register, 2> DstTmpRegs(DstTmpParts);
4066   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
4067   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
4068   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
4069 
4070   // Take only high half of registers if this is high mul.
4071   ArrayRef<Register> DstRegs(
4072       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
4073   MIRBuilder.buildMerge(DstReg, DstRegs);
4074   MI.eraseFromParent();
4075   return Legalized;
4076 }
4077 
4078 LegalizerHelper::LegalizeResult
4079 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
4080                                      LLT NarrowTy) {
4081   if (TypeIdx != 1)
4082     return UnableToLegalize;
4083 
4084   uint64_t NarrowSize = NarrowTy.getSizeInBits();
4085 
4086   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
4087   // FIXME: add support for when SizeOp1 isn't an exact multiple of
4088   // NarrowSize.
4089   if (SizeOp1 % NarrowSize != 0)
4090     return UnableToLegalize;
4091   int NumParts = SizeOp1 / NarrowSize;
4092 
4093   SmallVector<Register, 2> SrcRegs, DstRegs;
4094   SmallVector<uint64_t, 2> Indexes;
4095   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
4096 
4097   Register OpReg = MI.getOperand(0).getReg();
4098   uint64_t OpStart = MI.getOperand(2).getImm();
4099   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
4100   for (int i = 0; i < NumParts; ++i) {
4101     unsigned SrcStart = i * NarrowSize;
4102 
4103     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
4104       // No part of the extract uses this subregister, ignore it.
4105       continue;
4106     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
4107       // The entire subregister is extracted, forward the value.
4108       DstRegs.push_back(SrcRegs[i]);
4109       continue;
4110     }
4111 
4112     // OpSegStart is where this destination segment would start in OpReg if it
4113     // extended infinitely in both directions.
4114     int64_t ExtractOffset;
4115     uint64_t SegSize;
4116     if (OpStart < SrcStart) {
4117       ExtractOffset = 0;
4118       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
4119     } else {
4120       ExtractOffset = OpStart - SrcStart;
4121       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
4122     }
4123 
4124     Register SegReg = SrcRegs[i];
4125     if (ExtractOffset != 0 || SegSize != NarrowSize) {
4126       // A genuine extract is needed.
4127       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
4128       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
4129     }
4130 
4131     DstRegs.push_back(SegReg);
4132   }
4133 
4134   Register DstReg = MI.getOperand(0).getReg();
4135   if (MRI.getType(DstReg).isVector())
4136     MIRBuilder.buildBuildVector(DstReg, DstRegs);
4137   else if (DstRegs.size() > 1)
4138     MIRBuilder.buildMerge(DstReg, DstRegs);
4139   else
4140     MIRBuilder.buildCopy(DstReg, DstRegs[0]);
4141   MI.eraseFromParent();
4142   return Legalized;
4143 }
4144 
4145 LegalizerHelper::LegalizeResult
4146 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
4147                                     LLT NarrowTy) {
4148   // FIXME: Don't know how to handle secondary types yet.
4149   if (TypeIdx != 0)
4150     return UnableToLegalize;
4151 
4152   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
4153   uint64_t NarrowSize = NarrowTy.getSizeInBits();
4154 
4155   // FIXME: add support for when SizeOp0 isn't an exact multiple of
4156   // NarrowSize.
4157   if (SizeOp0 % NarrowSize != 0)
4158     return UnableToLegalize;
4159 
4160   int NumParts = SizeOp0 / NarrowSize;
4161 
4162   SmallVector<Register, 2> SrcRegs, DstRegs;
4163   SmallVector<uint64_t, 2> Indexes;
4164   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
4165 
4166   Register OpReg = MI.getOperand(2).getReg();
4167   uint64_t OpStart = MI.getOperand(3).getImm();
4168   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
4169   for (int i = 0; i < NumParts; ++i) {
4170     unsigned DstStart = i * NarrowSize;
4171 
4172     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
4173       // No part of the insert affects this subregister, forward the original.
4174       DstRegs.push_back(SrcRegs[i]);
4175       continue;
4176     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
4177       // The entire subregister is defined by this insert, forward the new
4178       // value.
4179       DstRegs.push_back(OpReg);
4180       continue;
4181     }
4182 
4183     // OpSegStart is where this destination segment would start in OpReg if it
4184     // extended infinitely in both directions.
4185     int64_t ExtractOffset, InsertOffset;
4186     uint64_t SegSize;
4187     if (OpStart < DstStart) {
4188       InsertOffset = 0;
4189       ExtractOffset = DstStart - OpStart;
4190       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
4191     } else {
4192       InsertOffset = OpStart - DstStart;
4193       ExtractOffset = 0;
4194       SegSize =
4195         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
4196     }
4197 
4198     Register SegReg = OpReg;
4199     if (ExtractOffset != 0 || SegSize != OpSize) {
4200       // A genuine extract is needed.
4201       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
4202       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
4203     }
4204 
4205     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
4206     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
4207     DstRegs.push_back(DstReg);
4208   }
4209 
4210   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
4211   Register DstReg = MI.getOperand(0).getReg();
4212   if(MRI.getType(DstReg).isVector())
4213     MIRBuilder.buildBuildVector(DstReg, DstRegs);
4214   else
4215     MIRBuilder.buildMerge(DstReg, DstRegs);
4216   MI.eraseFromParent();
4217   return Legalized;
4218 }
4219 
4220 LegalizerHelper::LegalizeResult
4221 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
4222                                    LLT NarrowTy) {
4223   Register DstReg = MI.getOperand(0).getReg();
4224   LLT DstTy = MRI.getType(DstReg);
4225 
4226   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
4227 
4228   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
4229   SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
4230   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
4231   LLT LeftoverTy;
4232   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
4233                     Src0Regs, Src0LeftoverRegs))
4234     return UnableToLegalize;
4235 
4236   LLT Unused;
4237   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
4238                     Src1Regs, Src1LeftoverRegs))
4239     llvm_unreachable("inconsistent extractParts result");
4240 
4241   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
4242     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
4243                                         {Src0Regs[I], Src1Regs[I]});
4244     DstRegs.push_back(Inst.getReg(0));
4245   }
4246 
4247   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
4248     auto Inst = MIRBuilder.buildInstr(
4249       MI.getOpcode(),
4250       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
4251     DstLeftoverRegs.push_back(Inst.getReg(0));
4252   }
4253 
4254   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
4255               LeftoverTy, DstLeftoverRegs);
4256 
4257   MI.eraseFromParent();
4258   return Legalized;
4259 }
4260 
4261 LegalizerHelper::LegalizeResult
4262 LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx,
4263                                  LLT NarrowTy) {
4264   if (TypeIdx != 0)
4265     return UnableToLegalize;
4266 
4267   Register DstReg = MI.getOperand(0).getReg();
4268   Register SrcReg = MI.getOperand(1).getReg();
4269 
4270   LLT DstTy = MRI.getType(DstReg);
4271   if (DstTy.isVector())
4272     return UnableToLegalize;
4273 
4274   SmallVector<Register, 8> Parts;
4275   LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg);
4276   LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, MI.getOpcode());
4277   buildWidenedRemergeToDst(DstReg, LCMTy, Parts);
4278 
4279   MI.eraseFromParent();
4280   return Legalized;
4281 }
4282 
4283 LegalizerHelper::LegalizeResult
4284 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
4285                                     LLT NarrowTy) {
4286   if (TypeIdx != 0)
4287     return UnableToLegalize;
4288 
4289   Register CondReg = MI.getOperand(1).getReg();
4290   LLT CondTy = MRI.getType(CondReg);
4291   if (CondTy.isVector()) // TODO: Handle vselect
4292     return UnableToLegalize;
4293 
4294   Register DstReg = MI.getOperand(0).getReg();
4295   LLT DstTy = MRI.getType(DstReg);
4296 
4297   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
4298   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
4299   SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
4300   LLT LeftoverTy;
4301   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
4302                     Src1Regs, Src1LeftoverRegs))
4303     return UnableToLegalize;
4304 
4305   LLT Unused;
4306   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
4307                     Src2Regs, Src2LeftoverRegs))
4308     llvm_unreachable("inconsistent extractParts result");
4309 
4310   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
4311     auto Select = MIRBuilder.buildSelect(NarrowTy,
4312                                          CondReg, Src1Regs[I], Src2Regs[I]);
4313     DstRegs.push_back(Select.getReg(0));
4314   }
4315 
4316   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
4317     auto Select = MIRBuilder.buildSelect(
4318       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
4319     DstLeftoverRegs.push_back(Select.getReg(0));
4320   }
4321 
4322   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
4323               LeftoverTy, DstLeftoverRegs);
4324 
4325   MI.eraseFromParent();
4326   return Legalized;
4327 }
4328 
4329 LegalizerHelper::LegalizeResult
4330 LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx,
4331                                   LLT NarrowTy) {
4332   if (TypeIdx != 1)
4333     return UnableToLegalize;
4334 
4335   Register DstReg = MI.getOperand(0).getReg();
4336   Register SrcReg = MI.getOperand(1).getReg();
4337   LLT DstTy = MRI.getType(DstReg);
4338   LLT SrcTy = MRI.getType(SrcReg);
4339   unsigned NarrowSize = NarrowTy.getSizeInBits();
4340 
4341   if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
4342     const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF;
4343 
4344     MachineIRBuilder &B = MIRBuilder;
4345     auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg);
4346     // ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi)
4347     auto C_0 = B.buildConstant(NarrowTy, 0);
4348     auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
4349                                 UnmergeSrc.getReg(1), C_0);
4350     auto LoCTLZ = IsUndef ?
4351       B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)) :
4352       B.buildCTLZ(DstTy, UnmergeSrc.getReg(0));
4353     auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize);
4354     auto HiIsZeroCTLZ = B.buildAdd(DstTy, LoCTLZ, C_NarrowSize);
4355     auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1));
4356     B.buildSelect(DstReg, HiIsZero, HiIsZeroCTLZ, HiCTLZ);
4357 
4358     MI.eraseFromParent();
4359     return Legalized;
4360   }
4361 
4362   return UnableToLegalize;
4363 }
4364 
4365 LegalizerHelper::LegalizeResult
4366 LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx,
4367                                   LLT NarrowTy) {
4368   if (TypeIdx != 1)
4369     return UnableToLegalize;
4370 
4371   Register DstReg = MI.getOperand(0).getReg();
4372   Register SrcReg = MI.getOperand(1).getReg();
4373   LLT DstTy = MRI.getType(DstReg);
4374   LLT SrcTy = MRI.getType(SrcReg);
4375   unsigned NarrowSize = NarrowTy.getSizeInBits();
4376 
4377   if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
4378     const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF;
4379 
4380     MachineIRBuilder &B = MIRBuilder;
4381     auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg);
4382     // cttz(Hi:Lo) -> Lo == 0 ? (cttz(Hi) + NarrowSize) : cttz(Lo)
4383     auto C_0 = B.buildConstant(NarrowTy, 0);
4384     auto LoIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
4385                                 UnmergeSrc.getReg(0), C_0);
4386     auto HiCTTZ = IsUndef ?
4387       B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)) :
4388       B.buildCTTZ(DstTy, UnmergeSrc.getReg(1));
4389     auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize);
4390     auto LoIsZeroCTTZ = B.buildAdd(DstTy, HiCTTZ, C_NarrowSize);
4391     auto LoCTTZ = B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0));
4392     B.buildSelect(DstReg, LoIsZero, LoIsZeroCTTZ, LoCTTZ);
4393 
4394     MI.eraseFromParent();
4395     return Legalized;
4396   }
4397 
4398   return UnableToLegalize;
4399 }
4400 
4401 LegalizerHelper::LegalizeResult
4402 LegalizerHelper::narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx,
4403                                    LLT NarrowTy) {
4404   if (TypeIdx != 1)
4405     return UnableToLegalize;
4406 
4407   Register DstReg = MI.getOperand(0).getReg();
4408   LLT DstTy = MRI.getType(DstReg);
4409   LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
4410   unsigned NarrowSize = NarrowTy.getSizeInBits();
4411 
4412   if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
4413     auto UnmergeSrc = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1));
4414 
4415     auto LoCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(0));
4416     auto HiCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(1));
4417     MIRBuilder.buildAdd(DstReg, HiCTPOP, LoCTPOP);
4418 
4419     MI.eraseFromParent();
4420     return Legalized;
4421   }
4422 
4423   return UnableToLegalize;
4424 }
4425 
4426 LegalizerHelper::LegalizeResult
4427 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4428   unsigned Opc = MI.getOpcode();
4429   const auto &TII = MIRBuilder.getTII();
4430   auto isSupported = [this](const LegalityQuery &Q) {
4431     auto QAction = LI.getAction(Q).Action;
4432     return QAction == Legal || QAction == Libcall || QAction == Custom;
4433   };
4434   switch (Opc) {
4435   default:
4436     return UnableToLegalize;
4437   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
4438     // This trivially expands to CTLZ.
4439     Observer.changingInstr(MI);
4440     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
4441     Observer.changedInstr(MI);
4442     return Legalized;
4443   }
4444   case TargetOpcode::G_CTLZ: {
4445     Register DstReg = MI.getOperand(0).getReg();
4446     Register SrcReg = MI.getOperand(1).getReg();
4447     LLT DstTy = MRI.getType(DstReg);
4448     LLT SrcTy = MRI.getType(SrcReg);
4449     unsigned Len = SrcTy.getSizeInBits();
4450 
4451     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) {
4452       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
4453       auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg);
4454       auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0);
4455       auto ICmp = MIRBuilder.buildICmp(
4456           CmpInst::ICMP_EQ, SrcTy.changeElementSize(1), SrcReg, ZeroSrc);
4457       auto LenConst = MIRBuilder.buildConstant(DstTy, Len);
4458       MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CtlzZU);
4459       MI.eraseFromParent();
4460       return Legalized;
4461     }
4462     // for now, we do this:
4463     // NewLen = NextPowerOf2(Len);
4464     // x = x | (x >> 1);
4465     // x = x | (x >> 2);
4466     // ...
4467     // x = x | (x >>16);
4468     // x = x | (x >>32); // for 64-bit input
4469     // Upto NewLen/2
4470     // return Len - popcount(x);
4471     //
4472     // Ref: "Hacker's Delight" by Henry Warren
4473     Register Op = SrcReg;
4474     unsigned NewLen = PowerOf2Ceil(Len);
4475     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
4476       auto MIBShiftAmt = MIRBuilder.buildConstant(SrcTy, 1ULL << i);
4477       auto MIBOp = MIRBuilder.buildOr(
4478           SrcTy, Op, MIRBuilder.buildLShr(SrcTy, Op, MIBShiftAmt));
4479       Op = MIBOp.getReg(0);
4480     }
4481     auto MIBPop = MIRBuilder.buildCTPOP(DstTy, Op);
4482     MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(DstTy, Len),
4483                         MIBPop);
4484     MI.eraseFromParent();
4485     return Legalized;
4486   }
4487   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
4488     // This trivially expands to CTTZ.
4489     Observer.changingInstr(MI);
4490     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
4491     Observer.changedInstr(MI);
4492     return Legalized;
4493   }
4494   case TargetOpcode::G_CTTZ: {
4495     Register DstReg = MI.getOperand(0).getReg();
4496     Register SrcReg = MI.getOperand(1).getReg();
4497     LLT DstTy = MRI.getType(DstReg);
4498     LLT SrcTy = MRI.getType(SrcReg);
4499 
4500     unsigned Len = SrcTy.getSizeInBits();
4501     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) {
4502       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
4503       // zero.
4504       auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg);
4505       auto Zero = MIRBuilder.buildConstant(SrcTy, 0);
4506       auto ICmp = MIRBuilder.buildICmp(
4507           CmpInst::ICMP_EQ, DstTy.changeElementSize(1), SrcReg, Zero);
4508       auto LenConst = MIRBuilder.buildConstant(DstTy, Len);
4509       MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CttzZU);
4510       MI.eraseFromParent();
4511       return Legalized;
4512     }
4513     // for now, we use: { return popcount(~x & (x - 1)); }
4514     // unless the target has ctlz but not ctpop, in which case we use:
4515     // { return 32 - nlz(~x & (x-1)); }
4516     // Ref: "Hacker's Delight" by Henry Warren
4517     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
4518     auto MIBNot = MIRBuilder.buildXor(Ty, SrcReg, MIBCstNeg1);
4519     auto MIBTmp = MIRBuilder.buildAnd(
4520         Ty, MIBNot, MIRBuilder.buildAdd(Ty, SrcReg, MIBCstNeg1));
4521     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
4522         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
4523       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
4524       MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen,
4525                           MIRBuilder.buildCTLZ(Ty, MIBTmp));
4526       MI.eraseFromParent();
4527       return Legalized;
4528     }
4529     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
4530     MI.getOperand(1).setReg(MIBTmp.getReg(0));
4531     return Legalized;
4532   }
4533   case TargetOpcode::G_CTPOP: {
4534     unsigned Size = Ty.getSizeInBits();
4535     MachineIRBuilder &B = MIRBuilder;
4536 
4537     // Count set bits in blocks of 2 bits. Default approach would be
4538     // B2Count = { val & 0x55555555 } + { (val >> 1) & 0x55555555 }
4539     // We use following formula instead:
4540     // B2Count = val - { (val >> 1) & 0x55555555 }
4541     // since it gives same result in blocks of 2 with one instruction less.
4542     auto C_1 = B.buildConstant(Ty, 1);
4543     auto B2Set1LoTo1Hi = B.buildLShr(Ty, MI.getOperand(1).getReg(), C_1);
4544     APInt B2Mask1HiTo0 = APInt::getSplat(Size, APInt(8, 0x55));
4545     auto C_B2Mask1HiTo0 = B.buildConstant(Ty, B2Mask1HiTo0);
4546     auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0);
4547     auto B2Count = B.buildSub(Ty, MI.getOperand(1).getReg(), B2Count1Hi);
4548 
4549     // In order to get count in blocks of 4 add values from adjacent block of 2.
4550     // B4Count = { B2Count & 0x33333333 } + { (B2Count >> 2) & 0x33333333 }
4551     auto C_2 = B.buildConstant(Ty, 2);
4552     auto B4Set2LoTo2Hi = B.buildLShr(Ty, B2Count, C_2);
4553     APInt B4Mask2HiTo0 = APInt::getSplat(Size, APInt(8, 0x33));
4554     auto C_B4Mask2HiTo0 = B.buildConstant(Ty, B4Mask2HiTo0);
4555     auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0);
4556     auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0);
4557     auto B4Count = B.buildAdd(Ty, B4HiB2Count, B4LoB2Count);
4558 
4559     // For count in blocks of 8 bits we don't have to mask high 4 bits before
4560     // addition since count value sits in range {0,...,8} and 4 bits are enough
4561     // to hold such binary values. After addition high 4 bits still hold count
4562     // of set bits in high 4 bit block, set them to zero and get 8 bit result.
4563     // B8Count = { B4Count + (B4Count >> 4) } & 0x0F0F0F0F
4564     auto C_4 = B.buildConstant(Ty, 4);
4565     auto B8HiB4Count = B.buildLShr(Ty, B4Count, C_4);
4566     auto B8CountDirty4Hi = B.buildAdd(Ty, B8HiB4Count, B4Count);
4567     APInt B8Mask4HiTo0 = APInt::getSplat(Size, APInt(8, 0x0F));
4568     auto C_B8Mask4HiTo0 = B.buildConstant(Ty, B8Mask4HiTo0);
4569     auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0);
4570 
4571     assert(Size<=128 && "Scalar size is too large for CTPOP lower algorithm");
4572     // 8 bits can hold CTPOP result of 128 bit int or smaller. Mul with this
4573     // bitmask will set 8 msb in ResTmp to sum of all B8Counts in 8 bit blocks.
4574     auto MulMask = B.buildConstant(Ty, APInt::getSplat(Size, APInt(8, 0x01)));
4575     auto ResTmp = B.buildMul(Ty, B8Count, MulMask);
4576 
4577     // Shift count result from 8 high bits to low bits.
4578     auto C_SizeM8 = B.buildConstant(Ty, Size - 8);
4579     B.buildLShr(MI.getOperand(0).getReg(), ResTmp, C_SizeM8);
4580 
4581     MI.eraseFromParent();
4582     return Legalized;
4583   }
4584   }
4585 }
4586 
4587 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
4588 // representation.
4589 LegalizerHelper::LegalizeResult
4590 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
4591   Register Dst = MI.getOperand(0).getReg();
4592   Register Src = MI.getOperand(1).getReg();
4593   const LLT S64 = LLT::scalar(64);
4594   const LLT S32 = LLT::scalar(32);
4595   const LLT S1 = LLT::scalar(1);
4596 
4597   assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
4598 
4599   // unsigned cul2f(ulong u) {
4600   //   uint lz = clz(u);
4601   //   uint e = (u != 0) ? 127U + 63U - lz : 0;
4602   //   u = (u << lz) & 0x7fffffffffffffffUL;
4603   //   ulong t = u & 0xffffffffffUL;
4604   //   uint v = (e << 23) | (uint)(u >> 40);
4605   //   uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
4606   //   return as_float(v + r);
4607   // }
4608 
4609   auto Zero32 = MIRBuilder.buildConstant(S32, 0);
4610   auto Zero64 = MIRBuilder.buildConstant(S64, 0);
4611 
4612   auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
4613 
4614   auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
4615   auto Sub = MIRBuilder.buildSub(S32, K, LZ);
4616 
4617   auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
4618   auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
4619 
4620   auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
4621   auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
4622 
4623   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
4624 
4625   auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
4626   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
4627 
4628   auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
4629   auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
4630   auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
4631 
4632   auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
4633   auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
4634   auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
4635   auto One = MIRBuilder.buildConstant(S32, 1);
4636 
4637   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
4638   auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
4639   auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
4640   MIRBuilder.buildAdd(Dst, V, R);
4641 
4642   MI.eraseFromParent();
4643   return Legalized;
4644 }
4645 
4646 LegalizerHelper::LegalizeResult
4647 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4648   Register Dst = MI.getOperand(0).getReg();
4649   Register Src = MI.getOperand(1).getReg();
4650   LLT DstTy = MRI.getType(Dst);
4651   LLT SrcTy = MRI.getType(Src);
4652 
4653   if (SrcTy == LLT::scalar(1)) {
4654     auto True = MIRBuilder.buildFConstant(DstTy, 1.0);
4655     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
4656     MIRBuilder.buildSelect(Dst, Src, True, False);
4657     MI.eraseFromParent();
4658     return Legalized;
4659   }
4660 
4661   if (SrcTy != LLT::scalar(64))
4662     return UnableToLegalize;
4663 
4664   if (DstTy == LLT::scalar(32)) {
4665     // TODO: SelectionDAG has several alternative expansions to port which may
4666     // be more reasonble depending on the available instructions. If a target
4667     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
4668     // intermediate type, this is probably worse.
4669     return lowerU64ToF32BitOps(MI);
4670   }
4671 
4672   return UnableToLegalize;
4673 }
4674 
4675 LegalizerHelper::LegalizeResult
4676 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4677   Register Dst = MI.getOperand(0).getReg();
4678   Register Src = MI.getOperand(1).getReg();
4679   LLT DstTy = MRI.getType(Dst);
4680   LLT SrcTy = MRI.getType(Src);
4681 
4682   const LLT S64 = LLT::scalar(64);
4683   const LLT S32 = LLT::scalar(32);
4684   const LLT S1 = LLT::scalar(1);
4685 
4686   if (SrcTy == S1) {
4687     auto True = MIRBuilder.buildFConstant(DstTy, -1.0);
4688     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
4689     MIRBuilder.buildSelect(Dst, Src, True, False);
4690     MI.eraseFromParent();
4691     return Legalized;
4692   }
4693 
4694   if (SrcTy != S64)
4695     return UnableToLegalize;
4696 
4697   if (DstTy == S32) {
4698     // signed cl2f(long l) {
4699     //   long s = l >> 63;
4700     //   float r = cul2f((l + s) ^ s);
4701     //   return s ? -r : r;
4702     // }
4703     Register L = Src;
4704     auto SignBit = MIRBuilder.buildConstant(S64, 63);
4705     auto S = MIRBuilder.buildAShr(S64, L, SignBit);
4706 
4707     auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
4708     auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
4709     auto R = MIRBuilder.buildUITOFP(S32, Xor);
4710 
4711     auto RNeg = MIRBuilder.buildFNeg(S32, R);
4712     auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
4713                                             MIRBuilder.buildConstant(S64, 0));
4714     MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
4715     MI.eraseFromParent();
4716     return Legalized;
4717   }
4718 
4719   return UnableToLegalize;
4720 }
4721 
4722 LegalizerHelper::LegalizeResult
4723 LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4724   Register Dst = MI.getOperand(0).getReg();
4725   Register Src = MI.getOperand(1).getReg();
4726   LLT DstTy = MRI.getType(Dst);
4727   LLT SrcTy = MRI.getType(Src);
4728   const LLT S64 = LLT::scalar(64);
4729   const LLT S32 = LLT::scalar(32);
4730 
4731   if (SrcTy != S64 && SrcTy != S32)
4732     return UnableToLegalize;
4733   if (DstTy != S32 && DstTy != S64)
4734     return UnableToLegalize;
4735 
4736   // FPTOSI gives same result as FPTOUI for positive signed integers.
4737   // FPTOUI needs to deal with fp values that convert to unsigned integers
4738   // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp.
4739 
4740   APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits());
4741   APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle()
4742                                                 : APFloat::IEEEdouble(),
4743                     APInt::getNullValue(SrcTy.getSizeInBits()));
4744   TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven);
4745 
4746   MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src);
4747 
4748   MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP);
4749   // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on
4750   // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1.
4751   MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold);
4752   MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub);
4753   MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt);
4754   MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit);
4755 
4756   const LLT S1 = LLT::scalar(1);
4757 
4758   MachineInstrBuilder FCMP =
4759       MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold);
4760   MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res);
4761 
4762   MI.eraseFromParent();
4763   return Legalized;
4764 }
4765 
4766 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) {
4767   Register Dst = MI.getOperand(0).getReg();
4768   Register Src = MI.getOperand(1).getReg();
4769   LLT DstTy = MRI.getType(Dst);
4770   LLT SrcTy = MRI.getType(Src);
4771   const LLT S64 = LLT::scalar(64);
4772   const LLT S32 = LLT::scalar(32);
4773 
4774   // FIXME: Only f32 to i64 conversions are supported.
4775   if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64)
4776     return UnableToLegalize;
4777 
4778   // Expand f32 -> i64 conversion
4779   // This algorithm comes from compiler-rt's implementation of fixsfdi:
4780   // https://github.com/llvm/llvm-project/blob/master/compiler-rt/lib/builtins/fixsfdi.c
4781 
4782   unsigned SrcEltBits = SrcTy.getScalarSizeInBits();
4783 
4784   auto ExponentMask = MIRBuilder.buildConstant(SrcTy, 0x7F800000);
4785   auto ExponentLoBit = MIRBuilder.buildConstant(SrcTy, 23);
4786 
4787   auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask);
4788   auto ExponentBits = MIRBuilder.buildLShr(SrcTy, AndExpMask, ExponentLoBit);
4789 
4790   auto SignMask = MIRBuilder.buildConstant(SrcTy,
4791                                            APInt::getSignMask(SrcEltBits));
4792   auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask);
4793   auto SignLowBit = MIRBuilder.buildConstant(SrcTy, SrcEltBits - 1);
4794   auto Sign = MIRBuilder.buildAShr(SrcTy, AndSignMask, SignLowBit);
4795   Sign = MIRBuilder.buildSExt(DstTy, Sign);
4796 
4797   auto MantissaMask = MIRBuilder.buildConstant(SrcTy, 0x007FFFFF);
4798   auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask);
4799   auto K = MIRBuilder.buildConstant(SrcTy, 0x00800000);
4800 
4801   auto R = MIRBuilder.buildOr(SrcTy, AndMantissaMask, K);
4802   R = MIRBuilder.buildZExt(DstTy, R);
4803 
4804   auto Bias = MIRBuilder.buildConstant(SrcTy, 127);
4805   auto Exponent = MIRBuilder.buildSub(SrcTy, ExponentBits, Bias);
4806   auto SubExponent = MIRBuilder.buildSub(SrcTy, Exponent, ExponentLoBit);
4807   auto ExponentSub = MIRBuilder.buildSub(SrcTy, ExponentLoBit, Exponent);
4808 
4809   auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent);
4810   auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub);
4811 
4812   const LLT S1 = LLT::scalar(1);
4813   auto CmpGt = MIRBuilder.buildICmp(CmpInst::ICMP_SGT,
4814                                     S1, Exponent, ExponentLoBit);
4815 
4816   R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl);
4817 
4818   auto XorSign = MIRBuilder.buildXor(DstTy, R, Sign);
4819   auto Ret = MIRBuilder.buildSub(DstTy, XorSign, Sign);
4820 
4821   auto ZeroSrcTy = MIRBuilder.buildConstant(SrcTy, 0);
4822 
4823   auto ExponentLt0 = MIRBuilder.buildICmp(CmpInst::ICMP_SLT,
4824                                           S1, Exponent, ZeroSrcTy);
4825 
4826   auto ZeroDstTy = MIRBuilder.buildConstant(DstTy, 0);
4827   MIRBuilder.buildSelect(Dst, ExponentLt0, ZeroDstTy, Ret);
4828 
4829   MI.eraseFromParent();
4830   return Legalized;
4831 }
4832 
4833 // f64 -> f16 conversion using round-to-nearest-even rounding mode.
4834 LegalizerHelper::LegalizeResult
4835 LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
4836   Register Dst = MI.getOperand(0).getReg();
4837   Register Src = MI.getOperand(1).getReg();
4838 
4839   if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly.
4840     return UnableToLegalize;
4841 
4842   const unsigned ExpMask = 0x7ff;
4843   const unsigned ExpBiasf64 = 1023;
4844   const unsigned ExpBiasf16 = 15;
4845   const LLT S32 = LLT::scalar(32);
4846   const LLT S1 = LLT::scalar(1);
4847 
4848   auto Unmerge = MIRBuilder.buildUnmerge(S32, Src);
4849   Register U = Unmerge.getReg(0);
4850   Register UH = Unmerge.getReg(1);
4851 
4852   auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20));
4853   E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask));
4854 
4855   // Subtract the fp64 exponent bias (1023) to get the real exponent and
4856   // add the f16 bias (15) to get the biased exponent for the f16 format.
4857   E = MIRBuilder.buildAdd(
4858     S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16));
4859 
4860   auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8));
4861   M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe));
4862 
4863   auto MaskedSig = MIRBuilder.buildAnd(S32, UH,
4864                                        MIRBuilder.buildConstant(S32, 0x1ff));
4865   MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U);
4866 
4867   auto Zero = MIRBuilder.buildConstant(S32, 0);
4868   auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero);
4869   auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0);
4870   M = MIRBuilder.buildOr(S32, M, Lo40Set);
4871 
4872   // (M != 0 ? 0x0200 : 0) | 0x7c00;
4873   auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200);
4874   auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero);
4875   auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero);
4876 
4877   auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00);
4878   auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00);
4879 
4880   // N = M | (E << 12);
4881   auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12));
4882   auto N = MIRBuilder.buildOr(S32, M, EShl12);
4883 
4884   // B = clamp(1-E, 0, 13);
4885   auto One = MIRBuilder.buildConstant(S32, 1);
4886   auto OneSubExp = MIRBuilder.buildSub(S32, One, E);
4887   auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero);
4888   B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13));
4889 
4890   auto SigSetHigh = MIRBuilder.buildOr(S32, M,
4891                                        MIRBuilder.buildConstant(S32, 0x1000));
4892 
4893   auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B);
4894   auto D0 = MIRBuilder.buildShl(S32, D, B);
4895 
4896   auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1,
4897                                              D0, SigSetHigh);
4898   auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh);
4899   D = MIRBuilder.buildOr(S32, D, D1);
4900 
4901   auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One);
4902   auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N);
4903 
4904   auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7));
4905   V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2));
4906 
4907   auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3,
4908                                        MIRBuilder.buildConstant(S32, 3));
4909   auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3);
4910 
4911   auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3,
4912                                        MIRBuilder.buildConstant(S32, 5));
4913   auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5);
4914 
4915   V1 = MIRBuilder.buildOr(S32, V0, V1);
4916   V = MIRBuilder.buildAdd(S32, V, V1);
4917 
4918   auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT,  S1,
4919                                        E, MIRBuilder.buildConstant(S32, 30));
4920   V = MIRBuilder.buildSelect(S32, CmpEGt30,
4921                              MIRBuilder.buildConstant(S32, 0x7c00), V);
4922 
4923   auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1,
4924                                          E, MIRBuilder.buildConstant(S32, 1039));
4925   V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V);
4926 
4927   // Extract the sign bit.
4928   auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16));
4929   Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000));
4930 
4931   // Insert the sign bit
4932   V = MIRBuilder.buildOr(S32, Sign, V);
4933 
4934   MIRBuilder.buildTrunc(Dst, V);
4935   MI.eraseFromParent();
4936   return Legalized;
4937 }
4938 
4939 LegalizerHelper::LegalizeResult
4940 LegalizerHelper::lowerFPTRUNC(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4941   Register Dst = MI.getOperand(0).getReg();
4942   Register Src = MI.getOperand(1).getReg();
4943 
4944   LLT DstTy = MRI.getType(Dst);
4945   LLT SrcTy = MRI.getType(Src);
4946   const LLT S64 = LLT::scalar(64);
4947   const LLT S16 = LLT::scalar(16);
4948 
4949   if (DstTy.getScalarType() == S16 && SrcTy.getScalarType() == S64)
4950     return lowerFPTRUNC_F64_TO_F16(MI);
4951 
4952   return UnableToLegalize;
4953 }
4954 
4955 // TODO: If RHS is a constant SelectionDAGBuilder expands this into a
4956 // multiplication tree.
4957 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPOWI(MachineInstr &MI) {
4958   Register Dst = MI.getOperand(0).getReg();
4959   Register Src0 = MI.getOperand(1).getReg();
4960   Register Src1 = MI.getOperand(2).getReg();
4961   LLT Ty = MRI.getType(Dst);
4962 
4963   auto CvtSrc1 = MIRBuilder.buildSITOFP(Ty, Src1);
4964   MIRBuilder.buildFPow(Dst, Src0, CvtSrc1, MI.getFlags());
4965   MI.eraseFromParent();
4966   return Legalized;
4967 }
4968 
4969 static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
4970   switch (Opc) {
4971   case TargetOpcode::G_SMIN:
4972     return CmpInst::ICMP_SLT;
4973   case TargetOpcode::G_SMAX:
4974     return CmpInst::ICMP_SGT;
4975   case TargetOpcode::G_UMIN:
4976     return CmpInst::ICMP_ULT;
4977   case TargetOpcode::G_UMAX:
4978     return CmpInst::ICMP_UGT;
4979   default:
4980     llvm_unreachable("not in integer min/max");
4981   }
4982 }
4983 
4984 LegalizerHelper::LegalizeResult
4985 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4986   Register Dst = MI.getOperand(0).getReg();
4987   Register Src0 = MI.getOperand(1).getReg();
4988   Register Src1 = MI.getOperand(2).getReg();
4989 
4990   const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
4991   LLT CmpType = MRI.getType(Dst).changeElementSize(1);
4992 
4993   auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
4994   MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
4995 
4996   MI.eraseFromParent();
4997   return Legalized;
4998 }
4999 
5000 LegalizerHelper::LegalizeResult
5001 LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
5002   Register Dst = MI.getOperand(0).getReg();
5003   Register Src0 = MI.getOperand(1).getReg();
5004   Register Src1 = MI.getOperand(2).getReg();
5005 
5006   const LLT Src0Ty = MRI.getType(Src0);
5007   const LLT Src1Ty = MRI.getType(Src1);
5008 
5009   const int Src0Size = Src0Ty.getScalarSizeInBits();
5010   const int Src1Size = Src1Ty.getScalarSizeInBits();
5011 
5012   auto SignBitMask = MIRBuilder.buildConstant(
5013     Src0Ty, APInt::getSignMask(Src0Size));
5014 
5015   auto NotSignBitMask = MIRBuilder.buildConstant(
5016     Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
5017 
5018   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
5019   MachineInstr *Or;
5020 
5021   if (Src0Ty == Src1Ty) {
5022     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask);
5023     Or = MIRBuilder.buildOr(Dst, And0, And1);
5024   } else if (Src0Size > Src1Size) {
5025     auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
5026     auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
5027     auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
5028     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
5029     Or = MIRBuilder.buildOr(Dst, And0, And1);
5030   } else {
5031     auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
5032     auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
5033     auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
5034     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
5035     Or = MIRBuilder.buildOr(Dst, And0, And1);
5036   }
5037 
5038   // Be careful about setting nsz/nnan/ninf on every instruction, since the
5039   // constants are a nan and -0.0, but the final result should preserve
5040   // everything.
5041   if (unsigned Flags = MI.getFlags())
5042     Or->setFlags(Flags);
5043 
5044   MI.eraseFromParent();
5045   return Legalized;
5046 }
5047 
5048 LegalizerHelper::LegalizeResult
5049 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
5050   unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ?
5051     TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE;
5052 
5053   Register Dst = MI.getOperand(0).getReg();
5054   Register Src0 = MI.getOperand(1).getReg();
5055   Register Src1 = MI.getOperand(2).getReg();
5056   LLT Ty = MRI.getType(Dst);
5057 
5058   if (!MI.getFlag(MachineInstr::FmNoNans)) {
5059     // Insert canonicalizes if it's possible we need to quiet to get correct
5060     // sNaN behavior.
5061 
5062     // Note this must be done here, and not as an optimization combine in the
5063     // absence of a dedicate quiet-snan instruction as we're using an
5064     // omni-purpose G_FCANONICALIZE.
5065     if (!isKnownNeverSNaN(Src0, MRI))
5066       Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0);
5067 
5068     if (!isKnownNeverSNaN(Src1, MRI))
5069       Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0);
5070   }
5071 
5072   // If there are no nans, it's safe to simply replace this with the non-IEEE
5073   // version.
5074   MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags());
5075   MI.eraseFromParent();
5076   return Legalized;
5077 }
5078 
5079 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) {
5080   // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c
5081   Register DstReg = MI.getOperand(0).getReg();
5082   LLT Ty = MRI.getType(DstReg);
5083   unsigned Flags = MI.getFlags();
5084 
5085   auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2),
5086                                   Flags);
5087   MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags);
5088   MI.eraseFromParent();
5089   return Legalized;
5090 }
5091 
5092 LegalizerHelper::LegalizeResult
5093 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) {
5094   Register DstReg = MI.getOperand(0).getReg();
5095   Register X = MI.getOperand(1).getReg();
5096   const unsigned Flags = MI.getFlags();
5097   const LLT Ty = MRI.getType(DstReg);
5098   const LLT CondTy = Ty.changeElementSize(1);
5099 
5100   // round(x) =>
5101   //  t = trunc(x);
5102   //  d = fabs(x - t);
5103   //  o = copysign(1.0f, x);
5104   //  return t + (d >= 0.5 ? o : 0.0);
5105 
5106   auto T = MIRBuilder.buildIntrinsicTrunc(Ty, X, Flags);
5107 
5108   auto Diff = MIRBuilder.buildFSub(Ty, X, T, Flags);
5109   auto AbsDiff = MIRBuilder.buildFAbs(Ty, Diff, Flags);
5110   auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
5111   auto One = MIRBuilder.buildFConstant(Ty, 1.0);
5112   auto Half = MIRBuilder.buildFConstant(Ty, 0.5);
5113   auto SignOne = MIRBuilder.buildFCopysign(Ty, One, X);
5114 
5115   auto Cmp = MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half,
5116                                   Flags);
5117   auto Sel = MIRBuilder.buildSelect(Ty, Cmp, SignOne, Zero, Flags);
5118 
5119   MIRBuilder.buildFAdd(DstReg, T, Sel, Flags);
5120 
5121   MI.eraseFromParent();
5122   return Legalized;
5123 }
5124 
5125 LegalizerHelper::LegalizeResult
5126 LegalizerHelper::lowerFFloor(MachineInstr &MI) {
5127   Register DstReg = MI.getOperand(0).getReg();
5128   Register SrcReg = MI.getOperand(1).getReg();
5129   unsigned Flags = MI.getFlags();
5130   LLT Ty = MRI.getType(DstReg);
5131   const LLT CondTy = Ty.changeElementSize(1);
5132 
5133   // result = trunc(src);
5134   // if (src < 0.0 && src != result)
5135   //   result += -1.0.
5136 
5137   auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags);
5138   auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
5139 
5140   auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy,
5141                                   SrcReg, Zero, Flags);
5142   auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy,
5143                                       SrcReg, Trunc, Flags);
5144   auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc);
5145   auto AddVal = MIRBuilder.buildSITOFP(Ty, And);
5146 
5147   MIRBuilder.buildFAdd(DstReg, Trunc, AddVal, Flags);
5148   MI.eraseFromParent();
5149   return Legalized;
5150 }
5151 
5152 LegalizerHelper::LegalizeResult
5153 LegalizerHelper::lowerMergeValues(MachineInstr &MI) {
5154   const unsigned NumOps = MI.getNumOperands();
5155   Register DstReg = MI.getOperand(0).getReg();
5156   Register Src0Reg = MI.getOperand(1).getReg();
5157   LLT DstTy = MRI.getType(DstReg);
5158   LLT SrcTy = MRI.getType(Src0Reg);
5159   unsigned PartSize = SrcTy.getSizeInBits();
5160 
5161   LLT WideTy = LLT::scalar(DstTy.getSizeInBits());
5162   Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0);
5163 
5164   for (unsigned I = 2; I != NumOps; ++I) {
5165     const unsigned Offset = (I - 1) * PartSize;
5166 
5167     Register SrcReg = MI.getOperand(I).getReg();
5168     auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
5169 
5170     Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
5171       MRI.createGenericVirtualRegister(WideTy);
5172 
5173     auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
5174     auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
5175     MIRBuilder.buildOr(NextResult, ResultReg, Shl);
5176     ResultReg = NextResult;
5177   }
5178 
5179   if (DstTy.isPointer()) {
5180     if (MIRBuilder.getDataLayout().isNonIntegralAddressSpace(
5181           DstTy.getAddressSpace())) {
5182       LLVM_DEBUG(dbgs() << "Not casting nonintegral address space\n");
5183       return UnableToLegalize;
5184     }
5185 
5186     MIRBuilder.buildIntToPtr(DstReg, ResultReg);
5187   }
5188 
5189   MI.eraseFromParent();
5190   return Legalized;
5191 }
5192 
5193 LegalizerHelper::LegalizeResult
5194 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
5195   const unsigned NumDst = MI.getNumOperands() - 1;
5196   Register SrcReg = MI.getOperand(NumDst).getReg();
5197   Register Dst0Reg = MI.getOperand(0).getReg();
5198   LLT DstTy = MRI.getType(Dst0Reg);
5199   if (DstTy.isPointer())
5200     return UnableToLegalize; // TODO
5201 
5202   SrcReg = coerceToScalar(SrcReg);
5203   if (!SrcReg)
5204     return UnableToLegalize;
5205 
5206   // Expand scalarizing unmerge as bitcast to integer and shift.
5207   LLT IntTy = MRI.getType(SrcReg);
5208 
5209   MIRBuilder.buildTrunc(Dst0Reg, SrcReg);
5210 
5211   const unsigned DstSize = DstTy.getSizeInBits();
5212   unsigned Offset = DstSize;
5213   for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
5214     auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
5215     auto Shift = MIRBuilder.buildLShr(IntTy, SrcReg, ShiftAmt);
5216     MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
5217   }
5218 
5219   MI.eraseFromParent();
5220   return Legalized;
5221 }
5222 
5223 /// Lower a vector extract by writing the vector to a stack temporary and
5224 /// reloading the element.
5225 ///
5226 /// %dst = G_EXTRACT_VECTOR_ELT %vec, %idx
5227 ///  =>
5228 ///  %stack_temp = G_FRAME_INDEX
5229 ///  G_STORE %vec, %stack_temp
5230 ///  %idx = clamp(%idx, %vec.getNumElements())
5231 ///  %element_ptr = G_PTR_ADD %stack_temp, %idx
5232 ///  %dst = G_LOAD %element_ptr
5233 LegalizerHelper::LegalizeResult
5234 LegalizerHelper::lowerExtractVectorElt(MachineInstr &MI) {
5235   Register DstReg = MI.getOperand(0).getReg();
5236   Register SrcVec = MI.getOperand(1).getReg();
5237   Register Idx = MI.getOperand(2).getReg();
5238   LLT VecTy = MRI.getType(SrcVec);
5239   LLT EltTy = VecTy.getElementType();
5240   if (!EltTy.isByteSized()) { // Not implemented.
5241     LLVM_DEBUG(dbgs() << "Can't handle non-byte element vectors yet\n");
5242     return UnableToLegalize;
5243   }
5244 
5245   unsigned EltBytes = EltTy.getSizeInBytes();
5246   Align StoreAlign = getStackTemporaryAlignment(VecTy);
5247   Align LoadAlign;
5248 
5249   MachinePointerInfo PtrInfo;
5250   auto StackTemp = createStackTemporary(TypeSize::Fixed(VecTy.getSizeInBytes()),
5251                                         StoreAlign, PtrInfo);
5252   MIRBuilder.buildStore(SrcVec, StackTemp, PtrInfo, StoreAlign);
5253 
5254   // Get the pointer to the element, and be sure not to hit undefined behavior
5255   // if the index is out of bounds.
5256   Register LoadPtr = getVectorElementPointer(StackTemp.getReg(0), VecTy, Idx);
5257 
5258   int64_t IdxVal;
5259   if (mi_match(Idx, MRI, m_ICst(IdxVal))) {
5260     int64_t Offset = IdxVal * EltBytes;
5261     PtrInfo = PtrInfo.getWithOffset(Offset);
5262     LoadAlign = commonAlignment(StoreAlign, Offset);
5263   } else {
5264     // We lose information with a variable offset.
5265     LoadAlign = getStackTemporaryAlignment(EltTy);
5266     PtrInfo = MachinePointerInfo(MRI.getType(LoadPtr).getAddressSpace());
5267   }
5268 
5269   MIRBuilder.buildLoad(DstReg, LoadPtr, PtrInfo, LoadAlign);
5270   MI.eraseFromParent();
5271   return Legalized;
5272 }
5273 
5274 LegalizerHelper::LegalizeResult
5275 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
5276   Register DstReg = MI.getOperand(0).getReg();
5277   Register Src0Reg = MI.getOperand(1).getReg();
5278   Register Src1Reg = MI.getOperand(2).getReg();
5279   LLT Src0Ty = MRI.getType(Src0Reg);
5280   LLT DstTy = MRI.getType(DstReg);
5281   LLT IdxTy = LLT::scalar(32);
5282 
5283   ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
5284 
5285   if (DstTy.isScalar()) {
5286     if (Src0Ty.isVector())
5287       return UnableToLegalize;
5288 
5289     // This is just a SELECT.
5290     assert(Mask.size() == 1 && "Expected a single mask element");
5291     Register Val;
5292     if (Mask[0] < 0 || Mask[0] > 1)
5293       Val = MIRBuilder.buildUndef(DstTy).getReg(0);
5294     else
5295       Val = Mask[0] == 0 ? Src0Reg : Src1Reg;
5296     MIRBuilder.buildCopy(DstReg, Val);
5297     MI.eraseFromParent();
5298     return Legalized;
5299   }
5300 
5301   Register Undef;
5302   SmallVector<Register, 32> BuildVec;
5303   LLT EltTy = DstTy.getElementType();
5304 
5305   for (int Idx : Mask) {
5306     if (Idx < 0) {
5307       if (!Undef.isValid())
5308         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);
5309       BuildVec.push_back(Undef);
5310       continue;
5311     }
5312 
5313     if (Src0Ty.isScalar()) {
5314       BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
5315     } else {
5316       int NumElts = Src0Ty.getNumElements();
5317       Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
5318       int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
5319       auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
5320       auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
5321       BuildVec.push_back(Extract.getReg(0));
5322     }
5323   }
5324 
5325   MIRBuilder.buildBuildVector(DstReg, BuildVec);
5326   MI.eraseFromParent();
5327   return Legalized;
5328 }
5329 
5330 LegalizerHelper::LegalizeResult
5331 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) {
5332   const auto &MF = *MI.getMF();
5333   const auto &TFI = *MF.getSubtarget().getFrameLowering();
5334   if (TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp)
5335     return UnableToLegalize;
5336 
5337   Register Dst = MI.getOperand(0).getReg();
5338   Register AllocSize = MI.getOperand(1).getReg();
5339   Align Alignment = assumeAligned(MI.getOperand(2).getImm());
5340 
5341   LLT PtrTy = MRI.getType(Dst);
5342   LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
5343 
5344   const auto &TLI = *MF.getSubtarget().getTargetLowering();
5345   Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
5346   auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg);
5347   SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp);
5348 
5349   // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't
5350   // have to generate an extra instruction to negate the alloc and then use
5351   // G_PTR_ADD to add the negative offset.
5352   auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize);
5353   if (Alignment > Align(1)) {
5354     APInt AlignMask(IntPtrTy.getSizeInBits(), Alignment.value(), true);
5355     AlignMask.negate();
5356     auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask);
5357     Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst);
5358   }
5359 
5360   SPTmp = MIRBuilder.buildCast(PtrTy, Alloc);
5361   MIRBuilder.buildCopy(SPReg, SPTmp);
5362   MIRBuilder.buildCopy(Dst, SPTmp);
5363 
5364   MI.eraseFromParent();
5365   return Legalized;
5366 }
5367 
5368 LegalizerHelper::LegalizeResult
5369 LegalizerHelper::lowerExtract(MachineInstr &MI) {
5370   Register Dst = MI.getOperand(0).getReg();
5371   Register Src = MI.getOperand(1).getReg();
5372   unsigned Offset = MI.getOperand(2).getImm();
5373 
5374   LLT DstTy = MRI.getType(Dst);
5375   LLT SrcTy = MRI.getType(Src);
5376 
5377   if (DstTy.isScalar() &&
5378       (SrcTy.isScalar() ||
5379        (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
5380     LLT SrcIntTy = SrcTy;
5381     if (!SrcTy.isScalar()) {
5382       SrcIntTy = LLT::scalar(SrcTy.getSizeInBits());
5383       Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0);
5384     }
5385 
5386     if (Offset == 0)
5387       MIRBuilder.buildTrunc(Dst, Src);
5388     else {
5389       auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset);
5390       auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt);
5391       MIRBuilder.buildTrunc(Dst, Shr);
5392     }
5393 
5394     MI.eraseFromParent();
5395     return Legalized;
5396   }
5397 
5398   return UnableToLegalize;
5399 }
5400 
5401 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
5402   Register Dst = MI.getOperand(0).getReg();
5403   Register Src = MI.getOperand(1).getReg();
5404   Register InsertSrc = MI.getOperand(2).getReg();
5405   uint64_t Offset = MI.getOperand(3).getImm();
5406 
5407   LLT DstTy = MRI.getType(Src);
5408   LLT InsertTy = MRI.getType(InsertSrc);
5409 
5410   if (InsertTy.isVector() ||
5411       (DstTy.isVector() && DstTy.getElementType() != InsertTy))
5412     return UnableToLegalize;
5413 
5414   const DataLayout &DL = MIRBuilder.getDataLayout();
5415   if ((DstTy.isPointer() &&
5416        DL.isNonIntegralAddressSpace(DstTy.getAddressSpace())) ||
5417       (InsertTy.isPointer() &&
5418        DL.isNonIntegralAddressSpace(InsertTy.getAddressSpace()))) {
5419     LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n");
5420     return UnableToLegalize;
5421   }
5422 
5423   LLT IntDstTy = DstTy;
5424 
5425   if (!DstTy.isScalar()) {
5426     IntDstTy = LLT::scalar(DstTy.getSizeInBits());
5427     Src = MIRBuilder.buildCast(IntDstTy, Src).getReg(0);
5428   }
5429 
5430   if (!InsertTy.isScalar()) {
5431     const LLT IntInsertTy = LLT::scalar(InsertTy.getSizeInBits());
5432     InsertSrc = MIRBuilder.buildPtrToInt(IntInsertTy, InsertSrc).getReg(0);
5433   }
5434 
5435   Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0);
5436   if (Offset != 0) {
5437     auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset);
5438     ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0);
5439   }
5440 
5441   APInt MaskVal = APInt::getBitsSetWithWrap(
5442       DstTy.getSizeInBits(), Offset + InsertTy.getSizeInBits(), Offset);
5443 
5444   auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal);
5445   auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);
5446   auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc);
5447 
5448   MIRBuilder.buildCast(Dst, Or);
5449   MI.eraseFromParent();
5450   return Legalized;
5451 }
5452 
5453 LegalizerHelper::LegalizeResult
5454 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {
5455   Register Dst0 = MI.getOperand(0).getReg();
5456   Register Dst1 = MI.getOperand(1).getReg();
5457   Register LHS = MI.getOperand(2).getReg();
5458   Register RHS = MI.getOperand(3).getReg();
5459   const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO;
5460 
5461   LLT Ty = MRI.getType(Dst0);
5462   LLT BoolTy = MRI.getType(Dst1);
5463 
5464   if (IsAdd)
5465     MIRBuilder.buildAdd(Dst0, LHS, RHS);
5466   else
5467     MIRBuilder.buildSub(Dst0, LHS, RHS);
5468 
5469   // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
5470 
5471   auto Zero = MIRBuilder.buildConstant(Ty, 0);
5472 
5473   // For an addition, the result should be less than one of the operands (LHS)
5474   // if and only if the other operand (RHS) is negative, otherwise there will
5475   // be overflow.
5476   // For a subtraction, the result should be less than one of the operands
5477   // (LHS) if and only if the other operand (RHS) is (non-zero) positive,
5478   // otherwise there will be overflow.
5479   auto ResultLowerThanLHS =
5480       MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS);
5481   auto ConditionRHS = MIRBuilder.buildICmp(
5482       IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero);
5483 
5484   MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS);
5485   MI.eraseFromParent();
5486   return Legalized;
5487 }
5488 
5489 LegalizerHelper::LegalizeResult
5490 LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI) {
5491   Register Res = MI.getOperand(0).getReg();
5492   Register LHS = MI.getOperand(1).getReg();
5493   Register RHS = MI.getOperand(2).getReg();
5494   LLT Ty = MRI.getType(Res);
5495   bool IsSigned;
5496   bool IsAdd;
5497   unsigned BaseOp;
5498   switch (MI.getOpcode()) {
5499   default:
5500     llvm_unreachable("unexpected addsat/subsat opcode");
5501   case TargetOpcode::G_UADDSAT:
5502     IsSigned = false;
5503     IsAdd = true;
5504     BaseOp = TargetOpcode::G_ADD;
5505     break;
5506   case TargetOpcode::G_SADDSAT:
5507     IsSigned = true;
5508     IsAdd = true;
5509     BaseOp = TargetOpcode::G_ADD;
5510     break;
5511   case TargetOpcode::G_USUBSAT:
5512     IsSigned = false;
5513     IsAdd = false;
5514     BaseOp = TargetOpcode::G_SUB;
5515     break;
5516   case TargetOpcode::G_SSUBSAT:
5517     IsSigned = true;
5518     IsAdd = false;
5519     BaseOp = TargetOpcode::G_SUB;
5520     break;
5521   }
5522 
5523   if (IsSigned) {
5524     // sadd.sat(a, b) ->
5525     //   hi = 0x7fffffff - smax(a, 0)
5526     //   lo = 0x80000000 - smin(a, 0)
5527     //   a + smin(smax(lo, b), hi)
5528     // ssub.sat(a, b) ->
5529     //   lo = smax(a, -1) - 0x7fffffff
5530     //   hi = smin(a, -1) - 0x80000000
5531     //   a - smin(smax(lo, b), hi)
5532     // TODO: AMDGPU can use a "median of 3" instruction here:
5533     //   a +/- med3(lo, b, hi)
5534     uint64_t NumBits = Ty.getScalarSizeInBits();
5535     auto MaxVal =
5536         MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(NumBits));
5537     auto MinVal =
5538         MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits));
5539     MachineInstrBuilder Hi, Lo;
5540     if (IsAdd) {
5541       auto Zero = MIRBuilder.buildConstant(Ty, 0);
5542       Hi = MIRBuilder.buildSub(Ty, MaxVal, MIRBuilder.buildSMax(Ty, LHS, Zero));
5543       Lo = MIRBuilder.buildSub(Ty, MinVal, MIRBuilder.buildSMin(Ty, LHS, Zero));
5544     } else {
5545       auto NegOne = MIRBuilder.buildConstant(Ty, -1);
5546       Lo = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMax(Ty, LHS, NegOne),
5547                                MaxVal);
5548       Hi = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMin(Ty, LHS, NegOne),
5549                                MinVal);
5550     }
5551     auto RHSClamped =
5552         MIRBuilder.buildSMin(Ty, MIRBuilder.buildSMax(Ty, Lo, RHS), Hi);
5553     MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped});
5554   } else {
5555     // uadd.sat(a, b) -> a + umin(~a, b)
5556     // usub.sat(a, b) -> a - umin(a, b)
5557     Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS;
5558     auto Min = MIRBuilder.buildUMin(Ty, Not, RHS);
5559     MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min});
5560   }
5561 
5562   MI.eraseFromParent();
5563   return Legalized;
5564 }
5565 
5566 LegalizerHelper::LegalizeResult
5567 LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) {
5568   Register Res = MI.getOperand(0).getReg();
5569   Register LHS = MI.getOperand(1).getReg();
5570   Register RHS = MI.getOperand(2).getReg();
5571   LLT Ty = MRI.getType(Res);
5572   LLT BoolTy = Ty.changeElementSize(1);
5573   bool IsSigned;
5574   bool IsAdd;
5575   unsigned OverflowOp;
5576   switch (MI.getOpcode()) {
5577   default:
5578     llvm_unreachable("unexpected addsat/subsat opcode");
5579   case TargetOpcode::G_UADDSAT:
5580     IsSigned = false;
5581     IsAdd = true;
5582     OverflowOp = TargetOpcode::G_UADDO;
5583     break;
5584   case TargetOpcode::G_SADDSAT:
5585     IsSigned = true;
5586     IsAdd = true;
5587     OverflowOp = TargetOpcode::G_SADDO;
5588     break;
5589   case TargetOpcode::G_USUBSAT:
5590     IsSigned = false;
5591     IsAdd = false;
5592     OverflowOp = TargetOpcode::G_USUBO;
5593     break;
5594   case TargetOpcode::G_SSUBSAT:
5595     IsSigned = true;
5596     IsAdd = false;
5597     OverflowOp = TargetOpcode::G_SSUBO;
5598     break;
5599   }
5600 
5601   auto OverflowRes =
5602       MIRBuilder.buildInstr(OverflowOp, {Ty, BoolTy}, {LHS, RHS});
5603   Register Tmp = OverflowRes.getReg(0);
5604   Register Ov = OverflowRes.getReg(1);
5605   MachineInstrBuilder Clamp;
5606   if (IsSigned) {
5607     // sadd.sat(a, b) ->
5608     //   {tmp, ov} = saddo(a, b)
5609     //   ov ? (tmp >>s 31) + 0x80000000 : r
5610     // ssub.sat(a, b) ->
5611     //   {tmp, ov} = ssubo(a, b)
5612     //   ov ? (tmp >>s 31) + 0x80000000 : r
5613     uint64_t NumBits = Ty.getScalarSizeInBits();
5614     auto ShiftAmount = MIRBuilder.buildConstant(Ty, NumBits - 1);
5615     auto Sign = MIRBuilder.buildAShr(Ty, Tmp, ShiftAmount);
5616     auto MinVal =
5617         MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits));
5618     Clamp = MIRBuilder.buildAdd(Ty, Sign, MinVal);
5619   } else {
5620     // uadd.sat(a, b) ->
5621     //   {tmp, ov} = uaddo(a, b)
5622     //   ov ? 0xffffffff : tmp
5623     // usub.sat(a, b) ->
5624     //   {tmp, ov} = usubo(a, b)
5625     //   ov ? 0 : tmp
5626     Clamp = MIRBuilder.buildConstant(Ty, IsAdd ? -1 : 0);
5627   }
5628   MIRBuilder.buildSelect(Res, Ov, Clamp, Tmp);
5629 
5630   MI.eraseFromParent();
5631   return Legalized;
5632 }
5633 
5634 LegalizerHelper::LegalizeResult
5635 LegalizerHelper::lowerBswap(MachineInstr &MI) {
5636   Register Dst = MI.getOperand(0).getReg();
5637   Register Src = MI.getOperand(1).getReg();
5638   const LLT Ty = MRI.getType(Src);
5639   unsigned SizeInBytes = (Ty.getScalarSizeInBits() + 7) / 8;
5640   unsigned BaseShiftAmt = (SizeInBytes - 1) * 8;
5641 
5642   // Swap most and least significant byte, set remaining bytes in Res to zero.
5643   auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt);
5644   auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt);
5645   auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
5646   auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft);
5647 
5648   // Set i-th high/low byte in Res to i-th low/high byte from Src.
5649   for (unsigned i = 1; i < SizeInBytes / 2; ++i) {
5650     // AND with Mask leaves byte i unchanged and sets remaining bytes to 0.
5651     APInt APMask(SizeInBytes * 8, 0xFF << (i * 8));
5652     auto Mask = MIRBuilder.buildConstant(Ty, APMask);
5653     auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i);
5654     // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt.
5655     auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask);
5656     auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt);
5657     Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft);
5658     // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask.
5659     auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
5660     auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask);
5661     Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight);
5662   }
5663   Res.getInstr()->getOperand(0).setReg(Dst);
5664 
5665   MI.eraseFromParent();
5666   return Legalized;
5667 }
5668 
5669 //{ (Src & Mask) >> N } | { (Src << N) & Mask }
5670 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B,
5671                                  MachineInstrBuilder Src, APInt Mask) {
5672   const LLT Ty = Dst.getLLTTy(*B.getMRI());
5673   MachineInstrBuilder C_N = B.buildConstant(Ty, N);
5674   MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask);
5675   auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N);
5676   auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0);
5677   return B.buildOr(Dst, LHS, RHS);
5678 }
5679 
5680 LegalizerHelper::LegalizeResult
5681 LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
5682   Register Dst = MI.getOperand(0).getReg();
5683   Register Src = MI.getOperand(1).getReg();
5684   const LLT Ty = MRI.getType(Src);
5685   unsigned Size = Ty.getSizeInBits();
5686 
5687   MachineInstrBuilder BSWAP =
5688       MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src});
5689 
5690   // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654
5691   //    [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4]
5692   // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0]
5693   MachineInstrBuilder Swap4 =
5694       SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0)));
5695 
5696   // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76
5697   //    [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2]
5698   // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC]
5699   MachineInstrBuilder Swap2 =
5700       SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC)));
5701 
5702   // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7
5703   //    [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1]
5704   // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA]
5705   SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA)));
5706 
5707   MI.eraseFromParent();
5708   return Legalized;
5709 }
5710 
5711 LegalizerHelper::LegalizeResult
5712 LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) {
5713   MachineFunction &MF = MIRBuilder.getMF();
5714   const TargetSubtargetInfo &STI = MF.getSubtarget();
5715   const TargetLowering *TLI = STI.getTargetLowering();
5716 
5717   bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER;
5718   int NameOpIdx = IsRead ? 1 : 0;
5719   int ValRegIndex = IsRead ? 0 : 1;
5720 
5721   Register ValReg = MI.getOperand(ValRegIndex).getReg();
5722   const LLT Ty = MRI.getType(ValReg);
5723   const MDString *RegStr = cast<MDString>(
5724     cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0));
5725 
5726   Register PhysReg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
5727   if (!PhysReg.isValid())
5728     return UnableToLegalize;
5729 
5730   if (IsRead)
5731     MIRBuilder.buildCopy(ValReg, PhysReg);
5732   else
5733     MIRBuilder.buildCopy(PhysReg, ValReg);
5734 
5735   MI.eraseFromParent();
5736   return Legalized;
5737 }
5738