1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetFrameLowering.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetLowering.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 
28 #define DEBUG_TYPE "legalizer"
29 
30 using namespace llvm;
31 using namespace LegalizeActions;
32 
33 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
34 ///
35 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
36 /// with any leftover piece as type \p LeftoverTy
37 ///
38 /// Returns -1 in the first element of the pair if the breakdown is not
39 /// satisfiable.
40 static std::pair<int, int>
41 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
42   assert(!LeftoverTy.isValid() && "this is an out argument");
43 
44   unsigned Size = OrigTy.getSizeInBits();
45   unsigned NarrowSize = NarrowTy.getSizeInBits();
46   unsigned NumParts = Size / NarrowSize;
47   unsigned LeftoverSize = Size - NumParts * NarrowSize;
48   assert(Size > NarrowSize);
49 
50   if (LeftoverSize == 0)
51     return {NumParts, 0};
52 
53   if (NarrowTy.isVector()) {
54     unsigned EltSize = OrigTy.getScalarSizeInBits();
55     if (LeftoverSize % EltSize != 0)
56       return {-1, -1};
57     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
58   } else {
59     LeftoverTy = LLT::scalar(LeftoverSize);
60   }
61 
62   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
63   return std::make_pair(NumParts, NumLeftover);
64 }
65 
66 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
67                                  GISelChangeObserver &Observer,
68                                  MachineIRBuilder &Builder)
69     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
70       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
71   MIRBuilder.setMF(MF);
72   MIRBuilder.setChangeObserver(Observer);
73 }
74 
75 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
76                                  GISelChangeObserver &Observer,
77                                  MachineIRBuilder &B)
78     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
79   MIRBuilder.setMF(MF);
80   MIRBuilder.setChangeObserver(Observer);
81 }
82 LegalizerHelper::LegalizeResult
83 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
84   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
85 
86   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
87       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
88     return LI.legalizeIntrinsic(MI, MRI, MIRBuilder) ? Legalized
89                                                      : UnableToLegalize;
90   auto Step = LI.getAction(MI, MRI);
91   switch (Step.Action) {
92   case Legal:
93     LLVM_DEBUG(dbgs() << ".. Already legal\n");
94     return AlreadyLegal;
95   case Libcall:
96     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
97     return libcall(MI);
98   case NarrowScalar:
99     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
100     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
101   case WidenScalar:
102     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
103     return widenScalar(MI, Step.TypeIdx, Step.NewType);
104   case Lower:
105     LLVM_DEBUG(dbgs() << ".. Lower\n");
106     return lower(MI, Step.TypeIdx, Step.NewType);
107   case FewerElements:
108     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
109     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
110   case MoreElements:
111     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
112     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
113   case Custom:
114     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
115     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
116                                                             : UnableToLegalize;
117   default:
118     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
119     return UnableToLegalize;
120   }
121 }
122 
123 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
124                                    SmallVectorImpl<Register> &VRegs) {
125   for (int i = 0; i < NumParts; ++i)
126     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
127   MIRBuilder.buildUnmerge(VRegs, Reg);
128 }
129 
130 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
131                                    LLT MainTy, LLT &LeftoverTy,
132                                    SmallVectorImpl<Register> &VRegs,
133                                    SmallVectorImpl<Register> &LeftoverRegs) {
134   assert(!LeftoverTy.isValid() && "this is an out argument");
135 
136   unsigned RegSize = RegTy.getSizeInBits();
137   unsigned MainSize = MainTy.getSizeInBits();
138   unsigned NumParts = RegSize / MainSize;
139   unsigned LeftoverSize = RegSize - NumParts * MainSize;
140 
141   // Use an unmerge when possible.
142   if (LeftoverSize == 0) {
143     for (unsigned I = 0; I < NumParts; ++I)
144       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
145     MIRBuilder.buildUnmerge(VRegs, Reg);
146     return true;
147   }
148 
149   if (MainTy.isVector()) {
150     unsigned EltSize = MainTy.getScalarSizeInBits();
151     if (LeftoverSize % EltSize != 0)
152       return false;
153     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
154   } else {
155     LeftoverTy = LLT::scalar(LeftoverSize);
156   }
157 
158   // For irregular sizes, extract the individual parts.
159   for (unsigned I = 0; I != NumParts; ++I) {
160     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
161     VRegs.push_back(NewReg);
162     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
163   }
164 
165   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
166        Offset += LeftoverSize) {
167     Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
168     LeftoverRegs.push_back(NewReg);
169     MIRBuilder.buildExtract(NewReg, Reg, Offset);
170   }
171 
172   return true;
173 }
174 
175 static LLT getGCDType(LLT OrigTy, LLT TargetTy) {
176   if (OrigTy.isVector() && TargetTy.isVector()) {
177     assert(OrigTy.getElementType() == TargetTy.getElementType());
178     int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
179                                     TargetTy.getNumElements());
180     return LLT::scalarOrVector(GCD, OrigTy.getElementType());
181   }
182 
183   if (OrigTy.isVector() && !TargetTy.isVector()) {
184     assert(OrigTy.getElementType() == TargetTy);
185     return TargetTy;
186   }
187 
188   assert(!OrigTy.isVector() && !TargetTy.isVector());
189 
190   int GCD = greatestCommonDivisor(OrigTy.getSizeInBits(),
191                                   TargetTy.getSizeInBits());
192   return LLT::scalar(GCD);
193 }
194 
195 void LegalizerHelper::insertParts(Register DstReg,
196                                   LLT ResultTy, LLT PartTy,
197                                   ArrayRef<Register> PartRegs,
198                                   LLT LeftoverTy,
199                                   ArrayRef<Register> LeftoverRegs) {
200   if (!LeftoverTy.isValid()) {
201     assert(LeftoverRegs.empty());
202 
203     if (!ResultTy.isVector()) {
204       MIRBuilder.buildMerge(DstReg, PartRegs);
205       return;
206     }
207 
208     if (PartTy.isVector())
209       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
210     else
211       MIRBuilder.buildBuildVector(DstReg, PartRegs);
212     return;
213   }
214 
215   unsigned PartSize = PartTy.getSizeInBits();
216   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
217 
218   Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
219   MIRBuilder.buildUndef(CurResultReg);
220 
221   unsigned Offset = 0;
222   for (Register PartReg : PartRegs) {
223     Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
224     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
225     CurResultReg = NewResultReg;
226     Offset += PartSize;
227   }
228 
229   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
230     // Use the original output register for the final insert to avoid a copy.
231     Register NewResultReg = (I + 1 == E) ?
232       DstReg : MRI.createGenericVirtualRegister(ResultTy);
233 
234     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
235     CurResultReg = NewResultReg;
236     Offset += LeftoverPartSize;
237   }
238 }
239 
240 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
241   switch (Opcode) {
242   case TargetOpcode::G_SDIV:
243     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
244     switch (Size) {
245     case 32:
246       return RTLIB::SDIV_I32;
247     case 64:
248       return RTLIB::SDIV_I64;
249     case 128:
250       return RTLIB::SDIV_I128;
251     default:
252       llvm_unreachable("unexpected size");
253     }
254   case TargetOpcode::G_UDIV:
255     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
256     switch (Size) {
257     case 32:
258       return RTLIB::UDIV_I32;
259     case 64:
260       return RTLIB::UDIV_I64;
261     case 128:
262       return RTLIB::UDIV_I128;
263     default:
264       llvm_unreachable("unexpected size");
265     }
266   case TargetOpcode::G_SREM:
267     assert((Size == 32 || Size == 64) && "Unsupported size");
268     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
269   case TargetOpcode::G_UREM:
270     assert((Size == 32 || Size == 64) && "Unsupported size");
271     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
272   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
273     assert(Size == 32 && "Unsupported size");
274     return RTLIB::CTLZ_I32;
275   case TargetOpcode::G_FADD:
276     assert((Size == 32 || Size == 64) && "Unsupported size");
277     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
278   case TargetOpcode::G_FSUB:
279     assert((Size == 32 || Size == 64) && "Unsupported size");
280     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
281   case TargetOpcode::G_FMUL:
282     assert((Size == 32 || Size == 64) && "Unsupported size");
283     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
284   case TargetOpcode::G_FDIV:
285     assert((Size == 32 || Size == 64) && "Unsupported size");
286     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
287   case TargetOpcode::G_FEXP:
288     assert((Size == 32 || Size == 64) && "Unsupported size");
289     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
290   case TargetOpcode::G_FEXP2:
291     assert((Size == 32 || Size == 64) && "Unsupported size");
292     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
293   case TargetOpcode::G_FREM:
294     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
295   case TargetOpcode::G_FPOW:
296     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
297   case TargetOpcode::G_FMA:
298     assert((Size == 32 || Size == 64) && "Unsupported size");
299     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
300   case TargetOpcode::G_FSIN:
301     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
302     return Size == 128 ? RTLIB::SIN_F128
303                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
304   case TargetOpcode::G_FCOS:
305     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
306     return Size == 128 ? RTLIB::COS_F128
307                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
308   case TargetOpcode::G_FLOG10:
309     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
310     return Size == 128 ? RTLIB::LOG10_F128
311                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
312   case TargetOpcode::G_FLOG:
313     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
314     return Size == 128 ? RTLIB::LOG_F128
315                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
316   case TargetOpcode::G_FLOG2:
317     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
318     return Size == 128 ? RTLIB::LOG2_F128
319                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
320   case TargetOpcode::G_FCEIL:
321     assert((Size == 32 || Size == 64) && "Unsupported size");
322     return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
323   case TargetOpcode::G_FFLOOR:
324     assert((Size == 32 || Size == 64) && "Unsupported size");
325     return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
326   }
327   llvm_unreachable("Unknown libcall function");
328 }
329 
330 /// True if an instruction is in tail position in its caller. Intended for
331 /// legalizing libcalls as tail calls when possible.
332 static bool isLibCallInTailPosition(MachineInstr &MI) {
333   const Function &F = MI.getParent()->getParent()->getFunction();
334 
335   // Conservatively require the attributes of the call to match those of
336   // the return. Ignore NoAlias and NonNull because they don't affect the
337   // call sequence.
338   AttributeList CallerAttrs = F.getAttributes();
339   if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
340           .removeAttribute(Attribute::NoAlias)
341           .removeAttribute(Attribute::NonNull)
342           .hasAttributes())
343     return false;
344 
345   // It's not safe to eliminate the sign / zero extension of the return value.
346   if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
347       CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
348     return false;
349 
350   // Only tail call if the following instruction is a standard return.
351   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
352   MachineInstr *Next = MI.getNextNode();
353   if (!Next || TII.isTailCall(*Next) || !Next->isReturn())
354     return false;
355 
356   return true;
357 }
358 
359 LegalizerHelper::LegalizeResult
360 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
361                     const CallLowering::ArgInfo &Result,
362                     ArrayRef<CallLowering::ArgInfo> Args) {
363   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
364   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
365   const char *Name = TLI.getLibcallName(Libcall);
366 
367   CallLowering::CallLoweringInfo Info;
368   Info.CallConv = TLI.getLibcallCallingConv(Libcall);
369   Info.Callee = MachineOperand::CreateES(Name);
370   Info.OrigRet = Result;
371   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
372   if (!CLI.lowerCall(MIRBuilder, Info))
373     return LegalizerHelper::UnableToLegalize;
374 
375   return LegalizerHelper::Legalized;
376 }
377 
378 // Useful for libcalls where all operands have the same type.
379 static LegalizerHelper::LegalizeResult
380 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
381               Type *OpType) {
382   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
383 
384   SmallVector<CallLowering::ArgInfo, 3> Args;
385   for (unsigned i = 1; i < MI.getNumOperands(); i++)
386     Args.push_back({MI.getOperand(i).getReg(), OpType});
387   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
388                        Args);
389 }
390 
391 LegalizerHelper::LegalizeResult
392 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
393                        MachineInstr &MI) {
394   assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
395   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
396 
397   SmallVector<CallLowering::ArgInfo, 3> Args;
398   // Add all the args, except for the last which is an imm denoting 'tail'.
399   for (unsigned i = 1; i < MI.getNumOperands() - 1; i++) {
400     Register Reg = MI.getOperand(i).getReg();
401 
402     // Need derive an IR type for call lowering.
403     LLT OpLLT = MRI.getType(Reg);
404     Type *OpTy = nullptr;
405     if (OpLLT.isPointer())
406       OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace());
407     else
408       OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits());
409     Args.push_back({Reg, OpTy});
410   }
411 
412   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
413   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
414   Intrinsic::ID ID = MI.getOperand(0).getIntrinsicID();
415   RTLIB::Libcall RTLibcall;
416   switch (ID) {
417   case Intrinsic::memcpy:
418     RTLibcall = RTLIB::MEMCPY;
419     break;
420   case Intrinsic::memset:
421     RTLibcall = RTLIB::MEMSET;
422     break;
423   case Intrinsic::memmove:
424     RTLibcall = RTLIB::MEMMOVE;
425     break;
426   default:
427     return LegalizerHelper::UnableToLegalize;
428   }
429   const char *Name = TLI.getLibcallName(RTLibcall);
430 
431   MIRBuilder.setInstr(MI);
432 
433   CallLowering::CallLoweringInfo Info;
434   Info.CallConv = TLI.getLibcallCallingConv(RTLibcall);
435   Info.Callee = MachineOperand::CreateES(Name);
436   Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx));
437   Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() == 1 &&
438                     isLibCallInTailPosition(MI);
439 
440   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
441   if (!CLI.lowerCall(MIRBuilder, Info))
442     return LegalizerHelper::UnableToLegalize;
443 
444   if (Info.LoweredTailCall) {
445     assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?");
446     // We must have a return following the call to get past
447     // isLibCallInTailPosition.
448     assert(MI.getNextNode() && MI.getNextNode()->isReturn() &&
449            "Expected instr following MI to be a return?");
450 
451     // We lowered a tail call, so the call is now the return from the block.
452     // Delete the old return.
453     MI.getNextNode()->eraseFromParent();
454   }
455 
456   return LegalizerHelper::Legalized;
457 }
458 
459 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
460                                        Type *FromType) {
461   auto ToMVT = MVT::getVT(ToType);
462   auto FromMVT = MVT::getVT(FromType);
463 
464   switch (Opcode) {
465   case TargetOpcode::G_FPEXT:
466     return RTLIB::getFPEXT(FromMVT, ToMVT);
467   case TargetOpcode::G_FPTRUNC:
468     return RTLIB::getFPROUND(FromMVT, ToMVT);
469   case TargetOpcode::G_FPTOSI:
470     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
471   case TargetOpcode::G_FPTOUI:
472     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
473   case TargetOpcode::G_SITOFP:
474     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
475   case TargetOpcode::G_UITOFP:
476     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
477   }
478   llvm_unreachable("Unsupported libcall function");
479 }
480 
481 static LegalizerHelper::LegalizeResult
482 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
483                   Type *FromType) {
484   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
485   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
486                        {{MI.getOperand(1).getReg(), FromType}});
487 }
488 
489 LegalizerHelper::LegalizeResult
490 LegalizerHelper::libcall(MachineInstr &MI) {
491   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
492   unsigned Size = LLTy.getSizeInBits();
493   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
494 
495   MIRBuilder.setInstr(MI);
496 
497   switch (MI.getOpcode()) {
498   default:
499     return UnableToLegalize;
500   case TargetOpcode::G_SDIV:
501   case TargetOpcode::G_UDIV:
502   case TargetOpcode::G_SREM:
503   case TargetOpcode::G_UREM:
504   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
505     Type *HLTy = IntegerType::get(Ctx, Size);
506     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
507     if (Status != Legalized)
508       return Status;
509     break;
510   }
511   case TargetOpcode::G_FADD:
512   case TargetOpcode::G_FSUB:
513   case TargetOpcode::G_FMUL:
514   case TargetOpcode::G_FDIV:
515   case TargetOpcode::G_FMA:
516   case TargetOpcode::G_FPOW:
517   case TargetOpcode::G_FREM:
518   case TargetOpcode::G_FCOS:
519   case TargetOpcode::G_FSIN:
520   case TargetOpcode::G_FLOG10:
521   case TargetOpcode::G_FLOG:
522   case TargetOpcode::G_FLOG2:
523   case TargetOpcode::G_FEXP:
524   case TargetOpcode::G_FEXP2:
525   case TargetOpcode::G_FCEIL:
526   case TargetOpcode::G_FFLOOR: {
527     if (Size > 64) {
528       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
529       return UnableToLegalize;
530     }
531     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
532     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
533     if (Status != Legalized)
534       return Status;
535     break;
536   }
537   case TargetOpcode::G_FPEXT: {
538     // FIXME: Support other floating point types (half, fp128 etc)
539     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
540     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
541     if (ToSize != 64 || FromSize != 32)
542       return UnableToLegalize;
543     LegalizeResult Status = conversionLibcall(
544         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
545     if (Status != Legalized)
546       return Status;
547     break;
548   }
549   case TargetOpcode::G_FPTRUNC: {
550     // FIXME: Support other floating point types (half, fp128 etc)
551     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
552     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
553     if (ToSize != 32 || FromSize != 64)
554       return UnableToLegalize;
555     LegalizeResult Status = conversionLibcall(
556         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
557     if (Status != Legalized)
558       return Status;
559     break;
560   }
561   case TargetOpcode::G_FPTOSI:
562   case TargetOpcode::G_FPTOUI: {
563     // FIXME: Support other types
564     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
565     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
566     if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
567       return UnableToLegalize;
568     LegalizeResult Status = conversionLibcall(
569         MI, MIRBuilder,
570         ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
571         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
572     if (Status != Legalized)
573       return Status;
574     break;
575   }
576   case TargetOpcode::G_SITOFP:
577   case TargetOpcode::G_UITOFP: {
578     // FIXME: Support other types
579     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
580     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
581     if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
582       return UnableToLegalize;
583     LegalizeResult Status = conversionLibcall(
584         MI, MIRBuilder,
585         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
586         FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
587     if (Status != Legalized)
588       return Status;
589     break;
590   }
591   }
592 
593   MI.eraseFromParent();
594   return Legalized;
595 }
596 
597 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
598                                                               unsigned TypeIdx,
599                                                               LLT NarrowTy) {
600   MIRBuilder.setInstr(MI);
601 
602   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
603   uint64_t NarrowSize = NarrowTy.getSizeInBits();
604 
605   switch (MI.getOpcode()) {
606   default:
607     return UnableToLegalize;
608   case TargetOpcode::G_IMPLICIT_DEF: {
609     // FIXME: add support for when SizeOp0 isn't an exact multiple of
610     // NarrowSize.
611     if (SizeOp0 % NarrowSize != 0)
612       return UnableToLegalize;
613     int NumParts = SizeOp0 / NarrowSize;
614 
615     SmallVector<Register, 2> DstRegs;
616     for (int i = 0; i < NumParts; ++i)
617       DstRegs.push_back(
618           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
619 
620     Register DstReg = MI.getOperand(0).getReg();
621     if(MRI.getType(DstReg).isVector())
622       MIRBuilder.buildBuildVector(DstReg, DstRegs);
623     else
624       MIRBuilder.buildMerge(DstReg, DstRegs);
625     MI.eraseFromParent();
626     return Legalized;
627   }
628   case TargetOpcode::G_CONSTANT: {
629     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
630     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
631     unsigned TotalSize = Ty.getSizeInBits();
632     unsigned NarrowSize = NarrowTy.getSizeInBits();
633     int NumParts = TotalSize / NarrowSize;
634 
635     SmallVector<Register, 4> PartRegs;
636     for (int I = 0; I != NumParts; ++I) {
637       unsigned Offset = I * NarrowSize;
638       auto K = MIRBuilder.buildConstant(NarrowTy,
639                                         Val.lshr(Offset).trunc(NarrowSize));
640       PartRegs.push_back(K.getReg(0));
641     }
642 
643     LLT LeftoverTy;
644     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
645     SmallVector<Register, 1> LeftoverRegs;
646     if (LeftoverBits != 0) {
647       LeftoverTy = LLT::scalar(LeftoverBits);
648       auto K = MIRBuilder.buildConstant(
649         LeftoverTy,
650         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
651       LeftoverRegs.push_back(K.getReg(0));
652     }
653 
654     insertParts(MI.getOperand(0).getReg(),
655                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
656 
657     MI.eraseFromParent();
658     return Legalized;
659   }
660   case TargetOpcode::G_SEXT: {
661     if (TypeIdx != 0)
662       return UnableToLegalize;
663 
664     Register SrcReg = MI.getOperand(1).getReg();
665     LLT SrcTy = MRI.getType(SrcReg);
666 
667     // FIXME: support the general case where the requested NarrowTy may not be
668     // the same as the source type. E.g. s128 = sext(s32)
669     if ((SrcTy.getSizeInBits() != SizeOp0 / 2) ||
670         SrcTy.getSizeInBits() != NarrowTy.getSizeInBits()) {
671       LLVM_DEBUG(dbgs() << "Can't narrow sext to type " << NarrowTy << "\n");
672       return UnableToLegalize;
673     }
674 
675     // Shift the sign bit of the low register through the high register.
676     auto ShiftAmt =
677         MIRBuilder.buildConstant(LLT::scalar(64), NarrowTy.getSizeInBits() - 1);
678     auto Shift = MIRBuilder.buildAShr(NarrowTy, SrcReg, ShiftAmt);
679     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)});
680     MI.eraseFromParent();
681     return Legalized;
682   }
683   case TargetOpcode::G_ZEXT: {
684     if (TypeIdx != 0)
685       return UnableToLegalize;
686 
687     LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
688     uint64_t SizeOp1 = SrcTy.getSizeInBits();
689     if (SizeOp0 % SizeOp1 != 0)
690       return UnableToLegalize;
691 
692     // Generate a merge where the bottom bits are taken from the source, and
693     // zero everything else.
694     Register ZeroReg = MIRBuilder.buildConstant(SrcTy, 0).getReg(0);
695     unsigned NumParts = SizeOp0 / SizeOp1;
696     SmallVector<Register, 4> Srcs = {MI.getOperand(1).getReg()};
697     for (unsigned Part = 1; Part < NumParts; ++Part)
698       Srcs.push_back(ZeroReg);
699     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs);
700     MI.eraseFromParent();
701     return Legalized;
702   }
703   case TargetOpcode::G_TRUNC: {
704     if (TypeIdx != 1)
705       return UnableToLegalize;
706 
707     uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
708     if (NarrowTy.getSizeInBits() * 2 != SizeOp1) {
709       LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n");
710       return UnableToLegalize;
711     }
712 
713     auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg());
714     MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0));
715     MI.eraseFromParent();
716     return Legalized;
717   }
718 
719   case TargetOpcode::G_ADD: {
720     // FIXME: add support for when SizeOp0 isn't an exact multiple of
721     // NarrowSize.
722     if (SizeOp0 % NarrowSize != 0)
723       return UnableToLegalize;
724     // Expand in terms of carry-setting/consuming G_ADDE instructions.
725     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
726 
727     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
728     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
729     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
730 
731     Register CarryIn;
732     for (int i = 0; i < NumParts; ++i) {
733       Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
734       Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
735 
736       if (i == 0)
737         MIRBuilder.buildUAddo(DstReg, CarryOut, Src1Regs[i], Src2Regs[i]);
738       else {
739         MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
740                               Src2Regs[i], CarryIn);
741       }
742 
743       DstRegs.push_back(DstReg);
744       CarryIn = CarryOut;
745     }
746     Register DstReg = MI.getOperand(0).getReg();
747     if(MRI.getType(DstReg).isVector())
748       MIRBuilder.buildBuildVector(DstReg, DstRegs);
749     else
750       MIRBuilder.buildMerge(DstReg, DstRegs);
751     MI.eraseFromParent();
752     return Legalized;
753   }
754   case TargetOpcode::G_SUB: {
755     // FIXME: add support for when SizeOp0 isn't an exact multiple of
756     // NarrowSize.
757     if (SizeOp0 % NarrowSize != 0)
758       return UnableToLegalize;
759 
760     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
761 
762     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
763     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
764     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
765 
766     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
767     Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
768     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
769                           {Src1Regs[0], Src2Regs[0]});
770     DstRegs.push_back(DstReg);
771     Register BorrowIn = BorrowOut;
772     for (int i = 1; i < NumParts; ++i) {
773       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
774       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
775 
776       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
777                             {Src1Regs[i], Src2Regs[i], BorrowIn});
778 
779       DstRegs.push_back(DstReg);
780       BorrowIn = BorrowOut;
781     }
782     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
783     MI.eraseFromParent();
784     return Legalized;
785   }
786   case TargetOpcode::G_MUL:
787   case TargetOpcode::G_UMULH:
788     return narrowScalarMul(MI, NarrowTy);
789   case TargetOpcode::G_EXTRACT:
790     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
791   case TargetOpcode::G_INSERT:
792     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
793   case TargetOpcode::G_LOAD: {
794     const auto &MMO = **MI.memoperands_begin();
795     Register DstReg = MI.getOperand(0).getReg();
796     LLT DstTy = MRI.getType(DstReg);
797     if (DstTy.isVector())
798       return UnableToLegalize;
799 
800     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
801       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
802       auto &MMO = **MI.memoperands_begin();
803       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
804       MIRBuilder.buildAnyExt(DstReg, TmpReg);
805       MI.eraseFromParent();
806       return Legalized;
807     }
808 
809     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
810   }
811   case TargetOpcode::G_ZEXTLOAD:
812   case TargetOpcode::G_SEXTLOAD: {
813     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
814     Register DstReg = MI.getOperand(0).getReg();
815     Register PtrReg = MI.getOperand(1).getReg();
816 
817     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
818     auto &MMO = **MI.memoperands_begin();
819     if (MMO.getSizeInBits() == NarrowSize) {
820       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
821     } else {
822       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
823         : TargetOpcode::G_SEXTLOAD;
824       MIRBuilder.buildInstr(ExtLoad)
825         .addDef(TmpReg)
826         .addUse(PtrReg)
827         .addMemOperand(&MMO);
828     }
829 
830     if (ZExt)
831       MIRBuilder.buildZExt(DstReg, TmpReg);
832     else
833       MIRBuilder.buildSExt(DstReg, TmpReg);
834 
835     MI.eraseFromParent();
836     return Legalized;
837   }
838   case TargetOpcode::G_STORE: {
839     const auto &MMO = **MI.memoperands_begin();
840 
841     Register SrcReg = MI.getOperand(0).getReg();
842     LLT SrcTy = MRI.getType(SrcReg);
843     if (SrcTy.isVector())
844       return UnableToLegalize;
845 
846     int NumParts = SizeOp0 / NarrowSize;
847     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
848     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
849     if (SrcTy.isVector() && LeftoverBits != 0)
850       return UnableToLegalize;
851 
852     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
853       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
854       auto &MMO = **MI.memoperands_begin();
855       MIRBuilder.buildTrunc(TmpReg, SrcReg);
856       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
857       MI.eraseFromParent();
858       return Legalized;
859     }
860 
861     return reduceLoadStoreWidth(MI, 0, NarrowTy);
862   }
863   case TargetOpcode::G_SELECT:
864     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
865   case TargetOpcode::G_AND:
866   case TargetOpcode::G_OR:
867   case TargetOpcode::G_XOR: {
868     // Legalize bitwise operation:
869     // A = BinOp<Ty> B, C
870     // into:
871     // B1, ..., BN = G_UNMERGE_VALUES B
872     // C1, ..., CN = G_UNMERGE_VALUES C
873     // A1 = BinOp<Ty/N> B1, C2
874     // ...
875     // AN = BinOp<Ty/N> BN, CN
876     // A = G_MERGE_VALUES A1, ..., AN
877     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
878   }
879   case TargetOpcode::G_SHL:
880   case TargetOpcode::G_LSHR:
881   case TargetOpcode::G_ASHR:
882     return narrowScalarShift(MI, TypeIdx, NarrowTy);
883   case TargetOpcode::G_CTLZ:
884   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
885   case TargetOpcode::G_CTTZ:
886   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
887   case TargetOpcode::G_CTPOP:
888     if (TypeIdx != 0)
889       return UnableToLegalize; // TODO
890 
891     Observer.changingInstr(MI);
892     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
893     Observer.changedInstr(MI);
894     return Legalized;
895   case TargetOpcode::G_INTTOPTR:
896     if (TypeIdx != 1)
897       return UnableToLegalize;
898 
899     Observer.changingInstr(MI);
900     narrowScalarSrc(MI, NarrowTy, 1);
901     Observer.changedInstr(MI);
902     return Legalized;
903   case TargetOpcode::G_PTRTOINT:
904     if (TypeIdx != 0)
905       return UnableToLegalize;
906 
907     Observer.changingInstr(MI);
908     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
909     Observer.changedInstr(MI);
910     return Legalized;
911   case TargetOpcode::G_PHI: {
912     unsigned NumParts = SizeOp0 / NarrowSize;
913     SmallVector<Register, 2> DstRegs;
914     SmallVector<SmallVector<Register, 2>, 2> SrcRegs;
915     DstRegs.resize(NumParts);
916     SrcRegs.resize(MI.getNumOperands() / 2);
917     Observer.changingInstr(MI);
918     for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
919       MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
920       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
921       extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
922                    SrcRegs[i / 2]);
923     }
924     MachineBasicBlock &MBB = *MI.getParent();
925     MIRBuilder.setInsertPt(MBB, MI);
926     for (unsigned i = 0; i < NumParts; ++i) {
927       DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
928       MachineInstrBuilder MIB =
929           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
930       for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
931         MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
932     }
933     MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
934     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
935     Observer.changedInstr(MI);
936     MI.eraseFromParent();
937     return Legalized;
938   }
939   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
940   case TargetOpcode::G_INSERT_VECTOR_ELT: {
941     if (TypeIdx != 2)
942       return UnableToLegalize;
943 
944     int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
945     Observer.changingInstr(MI);
946     narrowScalarSrc(MI, NarrowTy, OpIdx);
947     Observer.changedInstr(MI);
948     return Legalized;
949   }
950   case TargetOpcode::G_ICMP: {
951     uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
952     if (NarrowSize * 2 != SrcSize)
953       return UnableToLegalize;
954 
955     Observer.changingInstr(MI);
956     Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
957     Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
958     MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg());
959 
960     Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
961     Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
962     MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg());
963 
964     CmpInst::Predicate Pred =
965         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
966     LLT ResTy = MRI.getType(MI.getOperand(0).getReg());
967 
968     if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) {
969       MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
970       MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
971       MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
972       MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
973       MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero);
974     } else {
975       MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
976       MachineInstrBuilder CmpHEQ =
977           MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
978       MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
979           ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
980       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH);
981     }
982     Observer.changedInstr(MI);
983     MI.eraseFromParent();
984     return Legalized;
985   }
986   case TargetOpcode::G_SEXT_INREG: {
987     if (TypeIdx != 0)
988       return UnableToLegalize;
989 
990     if (!MI.getOperand(2).isImm())
991       return UnableToLegalize;
992     int64_t SizeInBits = MI.getOperand(2).getImm();
993 
994     // So long as the new type has more bits than the bits we're extending we
995     // don't need to break it apart.
996     if (NarrowTy.getScalarSizeInBits() >= SizeInBits) {
997       Observer.changingInstr(MI);
998       // We don't lose any non-extension bits by truncating the src and
999       // sign-extending the dst.
1000       MachineOperand &MO1 = MI.getOperand(1);
1001       auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1.getReg());
1002       MO1.setReg(TruncMIB->getOperand(0).getReg());
1003 
1004       MachineOperand &MO2 = MI.getOperand(0);
1005       Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
1006       MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1007       MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt});
1008       MO2.setReg(DstExt);
1009       Observer.changedInstr(MI);
1010       return Legalized;
1011     }
1012 
1013     // Break it apart. Components below the extension point are unmodified. The
1014     // component containing the extension point becomes a narrower SEXT_INREG.
1015     // Components above it are ashr'd from the component containing the
1016     // extension point.
1017     if (SizeOp0 % NarrowSize != 0)
1018       return UnableToLegalize;
1019     int NumParts = SizeOp0 / NarrowSize;
1020 
1021     // List the registers where the destination will be scattered.
1022     SmallVector<Register, 2> DstRegs;
1023     // List the registers where the source will be split.
1024     SmallVector<Register, 2> SrcRegs;
1025 
1026     // Create all the temporary registers.
1027     for (int i = 0; i < NumParts; ++i) {
1028       Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy);
1029 
1030       SrcRegs.push_back(SrcReg);
1031     }
1032 
1033     // Explode the big arguments into smaller chunks.
1034     MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg());
1035 
1036     Register AshrCstReg =
1037         MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
1038             ->getOperand(0)
1039             .getReg();
1040     Register FullExtensionReg = 0;
1041     Register PartialExtensionReg = 0;
1042 
1043     // Do the operation on each small part.
1044     for (int i = 0; i < NumParts; ++i) {
1045       if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits)
1046         DstRegs.push_back(SrcRegs[i]);
1047       else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) {
1048         assert(PartialExtensionReg &&
1049                "Expected to visit partial extension before full");
1050         if (FullExtensionReg) {
1051           DstRegs.push_back(FullExtensionReg);
1052           continue;
1053         }
1054         DstRegs.push_back(MIRBuilder
1055                               .buildInstr(TargetOpcode::G_ASHR, {NarrowTy},
1056                                           {PartialExtensionReg, AshrCstReg})
1057                               ->getOperand(0)
1058                               .getReg());
1059         FullExtensionReg = DstRegs.back();
1060       } else {
1061         DstRegs.push_back(
1062             MIRBuilder
1063                 .buildInstr(
1064                     TargetOpcode::G_SEXT_INREG, {NarrowTy},
1065                     {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
1066                 ->getOperand(0)
1067                 .getReg());
1068         PartialExtensionReg = DstRegs.back();
1069       }
1070     }
1071 
1072     // Gather the destination registers into the final destination.
1073     Register DstReg = MI.getOperand(0).getReg();
1074     MIRBuilder.buildMerge(DstReg, DstRegs);
1075     MI.eraseFromParent();
1076     return Legalized;
1077   }
1078   case TargetOpcode::G_BSWAP:
1079   case TargetOpcode::G_BITREVERSE: {
1080     if (SizeOp0 % NarrowSize != 0)
1081       return UnableToLegalize;
1082 
1083     Observer.changingInstr(MI);
1084     SmallVector<Register, 2> SrcRegs, DstRegs;
1085     unsigned NumParts = SizeOp0 / NarrowSize;
1086     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
1087 
1088     for (unsigned i = 0; i < NumParts; ++i) {
1089       auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
1090                                            {SrcRegs[NumParts - 1 - i]});
1091       DstRegs.push_back(DstPart.getReg(0));
1092     }
1093 
1094     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
1095 
1096     Observer.changedInstr(MI);
1097     MI.eraseFromParent();
1098     return Legalized;
1099   }
1100   }
1101 }
1102 
1103 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
1104                                      unsigned OpIdx, unsigned ExtOpcode) {
1105   MachineOperand &MO = MI.getOperand(OpIdx);
1106   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
1107   MO.setReg(ExtB->getOperand(0).getReg());
1108 }
1109 
1110 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
1111                                       unsigned OpIdx) {
1112   MachineOperand &MO = MI.getOperand(OpIdx);
1113   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
1114                                     {MO.getReg()});
1115   MO.setReg(ExtB->getOperand(0).getReg());
1116 }
1117 
1118 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
1119                                      unsigned OpIdx, unsigned TruncOpcode) {
1120   MachineOperand &MO = MI.getOperand(OpIdx);
1121   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1122   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1123   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
1124   MO.setReg(DstExt);
1125 }
1126 
1127 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
1128                                       unsigned OpIdx, unsigned ExtOpcode) {
1129   MachineOperand &MO = MI.getOperand(OpIdx);
1130   Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
1131   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1132   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
1133   MO.setReg(DstTrunc);
1134 }
1135 
1136 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
1137                                             unsigned OpIdx) {
1138   MachineOperand &MO = MI.getOperand(OpIdx);
1139   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1140   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1141   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
1142   MO.setReg(DstExt);
1143 }
1144 
1145 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
1146                                             unsigned OpIdx) {
1147   MachineOperand &MO = MI.getOperand(OpIdx);
1148 
1149   LLT OldTy = MRI.getType(MO.getReg());
1150   unsigned OldElts = OldTy.getNumElements();
1151   unsigned NewElts = MoreTy.getNumElements();
1152 
1153   unsigned NumParts = NewElts / OldElts;
1154 
1155   // Use concat_vectors if the result is a multiple of the number of elements.
1156   if (NumParts * OldElts == NewElts) {
1157     SmallVector<Register, 8> Parts;
1158     Parts.push_back(MO.getReg());
1159 
1160     Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
1161     for (unsigned I = 1; I != NumParts; ++I)
1162       Parts.push_back(ImpDef);
1163 
1164     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
1165     MO.setReg(Concat.getReg(0));
1166     return;
1167   }
1168 
1169   Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
1170   Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
1171   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
1172   MO.setReg(MoreReg);
1173 }
1174 
1175 LegalizerHelper::LegalizeResult
1176 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
1177                                         LLT WideTy) {
1178   if (TypeIdx != 1)
1179     return UnableToLegalize;
1180 
1181   Register DstReg = MI.getOperand(0).getReg();
1182   LLT DstTy = MRI.getType(DstReg);
1183   if (DstTy.isVector())
1184     return UnableToLegalize;
1185 
1186   Register Src1 = MI.getOperand(1).getReg();
1187   LLT SrcTy = MRI.getType(Src1);
1188   const int DstSize = DstTy.getSizeInBits();
1189   const int SrcSize = SrcTy.getSizeInBits();
1190   const int WideSize = WideTy.getSizeInBits();
1191   const int NumMerge = (DstSize + WideSize - 1) / WideSize;
1192 
1193   unsigned NumOps = MI.getNumOperands();
1194   unsigned NumSrc = MI.getNumOperands() - 1;
1195   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
1196 
1197   if (WideSize >= DstSize) {
1198     // Directly pack the bits in the target type.
1199     Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1200 
1201     for (unsigned I = 2; I != NumOps; ++I) {
1202       const unsigned Offset = (I - 1) * PartSize;
1203 
1204       Register SrcReg = MI.getOperand(I).getReg();
1205       assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
1206 
1207       auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
1208 
1209       Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
1210         MRI.createGenericVirtualRegister(WideTy);
1211 
1212       auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
1213       auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
1214       MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1215       ResultReg = NextResult;
1216     }
1217 
1218     if (WideSize > DstSize)
1219       MIRBuilder.buildTrunc(DstReg, ResultReg);
1220     else if (DstTy.isPointer())
1221       MIRBuilder.buildIntToPtr(DstReg, ResultReg);
1222 
1223     MI.eraseFromParent();
1224     return Legalized;
1225   }
1226 
1227   // Unmerge the original values to the GCD type, and recombine to the next
1228   // multiple greater than the original type.
1229   //
1230   // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6
1231   // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0
1232   // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1
1233   // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2
1234   // %10:_(s6) = G_MERGE_VALUES %4, %5, %6
1235   // %11:_(s6) = G_MERGE_VALUES %7, %8, %9
1236   // %12:_(s12) = G_MERGE_VALUES %10, %11
1237   //
1238   // Padding with undef if necessary:
1239   //
1240   // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6
1241   // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0
1242   // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1
1243   // %7:_(s2) = G_IMPLICIT_DEF
1244   // %8:_(s6) = G_MERGE_VALUES %3, %4, %5
1245   // %9:_(s6) = G_MERGE_VALUES %6, %7, %7
1246   // %10:_(s12) = G_MERGE_VALUES %8, %9
1247 
1248   const int GCD = greatestCommonDivisor(SrcSize, WideSize);
1249   LLT GCDTy = LLT::scalar(GCD);
1250 
1251   SmallVector<Register, 8> Parts;
1252   SmallVector<Register, 8> NewMergeRegs;
1253   SmallVector<Register, 8> Unmerges;
1254   LLT WideDstTy = LLT::scalar(NumMerge * WideSize);
1255 
1256   // Decompose the original operands if they don't evenly divide.
1257   for (int I = 1, E = MI.getNumOperands(); I != E; ++I) {
1258     Register SrcReg = MI.getOperand(I).getReg();
1259     if (GCD == SrcSize) {
1260       Unmerges.push_back(SrcReg);
1261     } else {
1262       auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
1263       for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J)
1264         Unmerges.push_back(Unmerge.getReg(J));
1265     }
1266   }
1267 
1268   // Pad with undef to the next size that is a multiple of the requested size.
1269   if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) {
1270     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1271     for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I)
1272       Unmerges.push_back(UndefReg);
1273   }
1274 
1275   const int PartsPerGCD = WideSize / GCD;
1276 
1277   // Build merges of each piece.
1278   ArrayRef<Register> Slicer(Unmerges);
1279   for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) {
1280     auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
1281     NewMergeRegs.push_back(Merge.getReg(0));
1282   }
1283 
1284   // A truncate may be necessary if the requested type doesn't evenly divide the
1285   // original result type.
1286   if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
1287     MIRBuilder.buildMerge(DstReg, NewMergeRegs);
1288   } else {
1289     auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
1290     MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
1291   }
1292 
1293   MI.eraseFromParent();
1294   return Legalized;
1295 }
1296 
1297 LegalizerHelper::LegalizeResult
1298 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
1299                                           LLT WideTy) {
1300   if (TypeIdx != 0)
1301     return UnableToLegalize;
1302 
1303   unsigned NumDst = MI.getNumOperands() - 1;
1304   Register SrcReg = MI.getOperand(NumDst).getReg();
1305   LLT SrcTy = MRI.getType(SrcReg);
1306   if (!SrcTy.isScalar())
1307     return UnableToLegalize;
1308 
1309   Register Dst0Reg = MI.getOperand(0).getReg();
1310   LLT DstTy = MRI.getType(Dst0Reg);
1311   if (!DstTy.isScalar())
1312     return UnableToLegalize;
1313 
1314   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
1315   LLT NewSrcTy = LLT::scalar(NewSrcSize);
1316   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
1317 
1318   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
1319 
1320   for (unsigned I = 1; I != NumDst; ++I) {
1321     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
1322     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
1323     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
1324   }
1325 
1326   Observer.changingInstr(MI);
1327 
1328   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
1329   for (unsigned I = 0; I != NumDst; ++I)
1330     widenScalarDst(MI, WideTy, I);
1331 
1332   Observer.changedInstr(MI);
1333 
1334   return Legalized;
1335 }
1336 
1337 LegalizerHelper::LegalizeResult
1338 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
1339                                     LLT WideTy) {
1340   Register DstReg = MI.getOperand(0).getReg();
1341   Register SrcReg = MI.getOperand(1).getReg();
1342   LLT SrcTy = MRI.getType(SrcReg);
1343 
1344   LLT DstTy = MRI.getType(DstReg);
1345   unsigned Offset = MI.getOperand(2).getImm();
1346 
1347   if (TypeIdx == 0) {
1348     if (SrcTy.isVector() || DstTy.isVector())
1349       return UnableToLegalize;
1350 
1351     SrcOp Src(SrcReg);
1352     if (SrcTy.isPointer()) {
1353       // Extracts from pointers can be handled only if they are really just
1354       // simple integers.
1355       const DataLayout &DL = MIRBuilder.getDataLayout();
1356       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
1357         return UnableToLegalize;
1358 
1359       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
1360       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
1361       SrcTy = SrcAsIntTy;
1362     }
1363 
1364     if (DstTy.isPointer())
1365       return UnableToLegalize;
1366 
1367     if (Offset == 0) {
1368       // Avoid a shift in the degenerate case.
1369       MIRBuilder.buildTrunc(DstReg,
1370                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
1371       MI.eraseFromParent();
1372       return Legalized;
1373     }
1374 
1375     // Do a shift in the source type.
1376     LLT ShiftTy = SrcTy;
1377     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1378       Src = MIRBuilder.buildAnyExt(WideTy, Src);
1379       ShiftTy = WideTy;
1380     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
1381       return UnableToLegalize;
1382 
1383     auto LShr = MIRBuilder.buildLShr(
1384       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
1385     MIRBuilder.buildTrunc(DstReg, LShr);
1386     MI.eraseFromParent();
1387     return Legalized;
1388   }
1389 
1390   if (SrcTy.isScalar()) {
1391     Observer.changingInstr(MI);
1392     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1393     Observer.changedInstr(MI);
1394     return Legalized;
1395   }
1396 
1397   if (!SrcTy.isVector())
1398     return UnableToLegalize;
1399 
1400   if (DstTy != SrcTy.getElementType())
1401     return UnableToLegalize;
1402 
1403   if (Offset % SrcTy.getScalarSizeInBits() != 0)
1404     return UnableToLegalize;
1405 
1406   Observer.changingInstr(MI);
1407   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1408 
1409   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
1410                           Offset);
1411   widenScalarDst(MI, WideTy.getScalarType(), 0);
1412   Observer.changedInstr(MI);
1413   return Legalized;
1414 }
1415 
1416 LegalizerHelper::LegalizeResult
1417 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
1418                                    LLT WideTy) {
1419   if (TypeIdx != 0)
1420     return UnableToLegalize;
1421   Observer.changingInstr(MI);
1422   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1423   widenScalarDst(MI, WideTy);
1424   Observer.changedInstr(MI);
1425   return Legalized;
1426 }
1427 
1428 LegalizerHelper::LegalizeResult
1429 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
1430   MIRBuilder.setInstr(MI);
1431 
1432   switch (MI.getOpcode()) {
1433   default:
1434     return UnableToLegalize;
1435   case TargetOpcode::G_EXTRACT:
1436     return widenScalarExtract(MI, TypeIdx, WideTy);
1437   case TargetOpcode::G_INSERT:
1438     return widenScalarInsert(MI, TypeIdx, WideTy);
1439   case TargetOpcode::G_MERGE_VALUES:
1440     return widenScalarMergeValues(MI, TypeIdx, WideTy);
1441   case TargetOpcode::G_UNMERGE_VALUES:
1442     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
1443   case TargetOpcode::G_UADDO:
1444   case TargetOpcode::G_USUBO: {
1445     if (TypeIdx == 1)
1446       return UnableToLegalize; // TODO
1447     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1448                                          {MI.getOperand(2).getReg()});
1449     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1450                                          {MI.getOperand(3).getReg()});
1451     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1452                           ? TargetOpcode::G_ADD
1453                           : TargetOpcode::G_SUB;
1454     // Do the arithmetic in the larger type.
1455     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1456     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1457     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
1458     auto AndOp = MIRBuilder.buildInstr(
1459         TargetOpcode::G_AND, {WideTy},
1460         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
1461     // There is no overflow if the AndOp is the same as NewOp.
1462     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
1463                          AndOp);
1464     // Now trunc the NewOp to the original result.
1465     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
1466     MI.eraseFromParent();
1467     return Legalized;
1468   }
1469   case TargetOpcode::G_CTTZ:
1470   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1471   case TargetOpcode::G_CTLZ:
1472   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1473   case TargetOpcode::G_CTPOP: {
1474     if (TypeIdx == 0) {
1475       Observer.changingInstr(MI);
1476       widenScalarDst(MI, WideTy, 0);
1477       Observer.changedInstr(MI);
1478       return Legalized;
1479     }
1480 
1481     Register SrcReg = MI.getOperand(1).getReg();
1482 
1483     // First ZEXT the input.
1484     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1485     LLT CurTy = MRI.getType(SrcReg);
1486     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1487       // The count is the same in the larger type except if the original
1488       // value was zero.  This can be handled by setting the bit just off
1489       // the top of the original type.
1490       auto TopBit =
1491           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1492       MIBSrc = MIRBuilder.buildOr(
1493         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1494     }
1495 
1496     // Perform the operation at the larger size.
1497     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1498     // This is already the correct result for CTPOP and CTTZs
1499     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1500         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1501       // The correct result is NewOp - (Difference in widety and current ty).
1502       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1503       MIBNewOp = MIRBuilder.buildInstr(
1504           TargetOpcode::G_SUB, {WideTy},
1505           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1506     }
1507 
1508     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1509     MI.eraseFromParent();
1510     return Legalized;
1511   }
1512   case TargetOpcode::G_BSWAP: {
1513     Observer.changingInstr(MI);
1514     Register DstReg = MI.getOperand(0).getReg();
1515 
1516     Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1517     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1518     Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1519     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1520 
1521     MI.getOperand(0).setReg(DstExt);
1522 
1523     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1524 
1525     LLT Ty = MRI.getType(DstReg);
1526     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1527     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1528     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1529       .addDef(ShrReg)
1530       .addUse(DstExt)
1531       .addUse(ShiftAmtReg);
1532 
1533     MIRBuilder.buildTrunc(DstReg, ShrReg);
1534     Observer.changedInstr(MI);
1535     return Legalized;
1536   }
1537   case TargetOpcode::G_BITREVERSE: {
1538     Observer.changingInstr(MI);
1539 
1540     Register DstReg = MI.getOperand(0).getReg();
1541     LLT Ty = MRI.getType(DstReg);
1542     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1543 
1544     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1545     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1546     MI.getOperand(0).setReg(DstExt);
1547     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1548 
1549     auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
1550     auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt);
1551     MIRBuilder.buildTrunc(DstReg, Shift);
1552     Observer.changedInstr(MI);
1553     return Legalized;
1554   }
1555   case TargetOpcode::G_ADD:
1556   case TargetOpcode::G_AND:
1557   case TargetOpcode::G_MUL:
1558   case TargetOpcode::G_OR:
1559   case TargetOpcode::G_XOR:
1560   case TargetOpcode::G_SUB:
1561     // Perform operation at larger width (any extension is fines here, high bits
1562     // don't affect the result) and then truncate the result back to the
1563     // original type.
1564     Observer.changingInstr(MI);
1565     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1566     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1567     widenScalarDst(MI, WideTy);
1568     Observer.changedInstr(MI);
1569     return Legalized;
1570 
1571   case TargetOpcode::G_SHL:
1572     Observer.changingInstr(MI);
1573 
1574     if (TypeIdx == 0) {
1575       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1576       widenScalarDst(MI, WideTy);
1577     } else {
1578       assert(TypeIdx == 1);
1579       // The "number of bits to shift" operand must preserve its value as an
1580       // unsigned integer:
1581       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1582     }
1583 
1584     Observer.changedInstr(MI);
1585     return Legalized;
1586 
1587   case TargetOpcode::G_SDIV:
1588   case TargetOpcode::G_SREM:
1589   case TargetOpcode::G_SMIN:
1590   case TargetOpcode::G_SMAX:
1591     Observer.changingInstr(MI);
1592     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1593     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1594     widenScalarDst(MI, WideTy);
1595     Observer.changedInstr(MI);
1596     return Legalized;
1597 
1598   case TargetOpcode::G_ASHR:
1599   case TargetOpcode::G_LSHR:
1600     Observer.changingInstr(MI);
1601 
1602     if (TypeIdx == 0) {
1603       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1604         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1605 
1606       widenScalarSrc(MI, WideTy, 1, CvtOp);
1607       widenScalarDst(MI, WideTy);
1608     } else {
1609       assert(TypeIdx == 1);
1610       // The "number of bits to shift" operand must preserve its value as an
1611       // unsigned integer:
1612       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1613     }
1614 
1615     Observer.changedInstr(MI);
1616     return Legalized;
1617   case TargetOpcode::G_UDIV:
1618   case TargetOpcode::G_UREM:
1619   case TargetOpcode::G_UMIN:
1620   case TargetOpcode::G_UMAX:
1621     Observer.changingInstr(MI);
1622     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1623     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1624     widenScalarDst(MI, WideTy);
1625     Observer.changedInstr(MI);
1626     return Legalized;
1627 
1628   case TargetOpcode::G_SELECT:
1629     Observer.changingInstr(MI);
1630     if (TypeIdx == 0) {
1631       // Perform operation at larger width (any extension is fine here, high
1632       // bits don't affect the result) and then truncate the result back to the
1633       // original type.
1634       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1635       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1636       widenScalarDst(MI, WideTy);
1637     } else {
1638       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1639       // Explicit extension is required here since high bits affect the result.
1640       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1641     }
1642     Observer.changedInstr(MI);
1643     return Legalized;
1644 
1645   case TargetOpcode::G_FPTOSI:
1646   case TargetOpcode::G_FPTOUI:
1647     Observer.changingInstr(MI);
1648 
1649     if (TypeIdx == 0)
1650       widenScalarDst(MI, WideTy);
1651     else
1652       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT);
1653 
1654     Observer.changedInstr(MI);
1655     return Legalized;
1656   case TargetOpcode::G_SITOFP:
1657     if (TypeIdx != 1)
1658       return UnableToLegalize;
1659     Observer.changingInstr(MI);
1660     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1661     Observer.changedInstr(MI);
1662     return Legalized;
1663 
1664   case TargetOpcode::G_UITOFP:
1665     if (TypeIdx != 1)
1666       return UnableToLegalize;
1667     Observer.changingInstr(MI);
1668     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1669     Observer.changedInstr(MI);
1670     return Legalized;
1671 
1672   case TargetOpcode::G_LOAD:
1673   case TargetOpcode::G_SEXTLOAD:
1674   case TargetOpcode::G_ZEXTLOAD:
1675     Observer.changingInstr(MI);
1676     widenScalarDst(MI, WideTy);
1677     Observer.changedInstr(MI);
1678     return Legalized;
1679 
1680   case TargetOpcode::G_STORE: {
1681     if (TypeIdx != 0)
1682       return UnableToLegalize;
1683 
1684     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1685     if (!isPowerOf2_32(Ty.getSizeInBits()))
1686       return UnableToLegalize;
1687 
1688     Observer.changingInstr(MI);
1689 
1690     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1691       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1692     widenScalarSrc(MI, WideTy, 0, ExtType);
1693 
1694     Observer.changedInstr(MI);
1695     return Legalized;
1696   }
1697   case TargetOpcode::G_CONSTANT: {
1698     MachineOperand &SrcMO = MI.getOperand(1);
1699     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1700     unsigned ExtOpc = LI.getExtOpcodeForWideningConstant(
1701         MRI.getType(MI.getOperand(0).getReg()));
1702     assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT ||
1703             ExtOpc == TargetOpcode::G_ANYEXT) &&
1704            "Illegal Extend");
1705     const APInt &SrcVal = SrcMO.getCImm()->getValue();
1706     const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT)
1707                            ? SrcVal.sext(WideTy.getSizeInBits())
1708                            : SrcVal.zext(WideTy.getSizeInBits());
1709     Observer.changingInstr(MI);
1710     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1711 
1712     widenScalarDst(MI, WideTy);
1713     Observer.changedInstr(MI);
1714     return Legalized;
1715   }
1716   case TargetOpcode::G_FCONSTANT: {
1717     MachineOperand &SrcMO = MI.getOperand(1);
1718     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1719     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1720     bool LosesInfo;
1721     switch (WideTy.getSizeInBits()) {
1722     case 32:
1723       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1724                   &LosesInfo);
1725       break;
1726     case 64:
1727       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1728                   &LosesInfo);
1729       break;
1730     default:
1731       return UnableToLegalize;
1732     }
1733 
1734     assert(!LosesInfo && "extend should always be lossless");
1735 
1736     Observer.changingInstr(MI);
1737     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1738 
1739     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1740     Observer.changedInstr(MI);
1741     return Legalized;
1742   }
1743   case TargetOpcode::G_IMPLICIT_DEF: {
1744     Observer.changingInstr(MI);
1745     widenScalarDst(MI, WideTy);
1746     Observer.changedInstr(MI);
1747     return Legalized;
1748   }
1749   case TargetOpcode::G_BRCOND:
1750     Observer.changingInstr(MI);
1751     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1752     Observer.changedInstr(MI);
1753     return Legalized;
1754 
1755   case TargetOpcode::G_FCMP:
1756     Observer.changingInstr(MI);
1757     if (TypeIdx == 0)
1758       widenScalarDst(MI, WideTy);
1759     else {
1760       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1761       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1762     }
1763     Observer.changedInstr(MI);
1764     return Legalized;
1765 
1766   case TargetOpcode::G_ICMP:
1767     Observer.changingInstr(MI);
1768     if (TypeIdx == 0)
1769       widenScalarDst(MI, WideTy);
1770     else {
1771       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1772                                MI.getOperand(1).getPredicate()))
1773                                ? TargetOpcode::G_SEXT
1774                                : TargetOpcode::G_ZEXT;
1775       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1776       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1777     }
1778     Observer.changedInstr(MI);
1779     return Legalized;
1780 
1781   case TargetOpcode::G_PTR_ADD:
1782     assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD");
1783     Observer.changingInstr(MI);
1784     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1785     Observer.changedInstr(MI);
1786     return Legalized;
1787 
1788   case TargetOpcode::G_PHI: {
1789     assert(TypeIdx == 0 && "Expecting only Idx 0");
1790 
1791     Observer.changingInstr(MI);
1792     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1793       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1794       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1795       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1796     }
1797 
1798     MachineBasicBlock &MBB = *MI.getParent();
1799     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1800     widenScalarDst(MI, WideTy);
1801     Observer.changedInstr(MI);
1802     return Legalized;
1803   }
1804   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1805     if (TypeIdx == 0) {
1806       Register VecReg = MI.getOperand(1).getReg();
1807       LLT VecTy = MRI.getType(VecReg);
1808       Observer.changingInstr(MI);
1809 
1810       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1811                                      WideTy.getSizeInBits()),
1812                      1, TargetOpcode::G_SEXT);
1813 
1814       widenScalarDst(MI, WideTy, 0);
1815       Observer.changedInstr(MI);
1816       return Legalized;
1817     }
1818 
1819     if (TypeIdx != 2)
1820       return UnableToLegalize;
1821     Observer.changingInstr(MI);
1822     // TODO: Probably should be zext
1823     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1824     Observer.changedInstr(MI);
1825     return Legalized;
1826   }
1827   case TargetOpcode::G_INSERT_VECTOR_ELT: {
1828     if (TypeIdx == 1) {
1829       Observer.changingInstr(MI);
1830 
1831       Register VecReg = MI.getOperand(1).getReg();
1832       LLT VecTy = MRI.getType(VecReg);
1833       LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy);
1834 
1835       widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT);
1836       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1837       widenScalarDst(MI, WideVecTy, 0);
1838       Observer.changedInstr(MI);
1839       return Legalized;
1840     }
1841 
1842     if (TypeIdx == 2) {
1843       Observer.changingInstr(MI);
1844       // TODO: Probably should be zext
1845       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT);
1846       Observer.changedInstr(MI);
1847     }
1848 
1849     return Legalized;
1850   }
1851   case TargetOpcode::G_FADD:
1852   case TargetOpcode::G_FMUL:
1853   case TargetOpcode::G_FSUB:
1854   case TargetOpcode::G_FMA:
1855   case TargetOpcode::G_FMAD:
1856   case TargetOpcode::G_FNEG:
1857   case TargetOpcode::G_FABS:
1858   case TargetOpcode::G_FCANONICALIZE:
1859   case TargetOpcode::G_FMINNUM:
1860   case TargetOpcode::G_FMAXNUM:
1861   case TargetOpcode::G_FMINNUM_IEEE:
1862   case TargetOpcode::G_FMAXNUM_IEEE:
1863   case TargetOpcode::G_FMINIMUM:
1864   case TargetOpcode::G_FMAXIMUM:
1865   case TargetOpcode::G_FDIV:
1866   case TargetOpcode::G_FREM:
1867   case TargetOpcode::G_FCEIL:
1868   case TargetOpcode::G_FFLOOR:
1869   case TargetOpcode::G_FCOS:
1870   case TargetOpcode::G_FSIN:
1871   case TargetOpcode::G_FLOG10:
1872   case TargetOpcode::G_FLOG:
1873   case TargetOpcode::G_FLOG2:
1874   case TargetOpcode::G_FRINT:
1875   case TargetOpcode::G_FNEARBYINT:
1876   case TargetOpcode::G_FSQRT:
1877   case TargetOpcode::G_FEXP:
1878   case TargetOpcode::G_FEXP2:
1879   case TargetOpcode::G_FPOW:
1880   case TargetOpcode::G_INTRINSIC_TRUNC:
1881   case TargetOpcode::G_INTRINSIC_ROUND:
1882     assert(TypeIdx == 0);
1883     Observer.changingInstr(MI);
1884 
1885     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1886       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1887 
1888     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1889     Observer.changedInstr(MI);
1890     return Legalized;
1891   case TargetOpcode::G_INTTOPTR:
1892     if (TypeIdx != 1)
1893       return UnableToLegalize;
1894 
1895     Observer.changingInstr(MI);
1896     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1897     Observer.changedInstr(MI);
1898     return Legalized;
1899   case TargetOpcode::G_PTRTOINT:
1900     if (TypeIdx != 0)
1901       return UnableToLegalize;
1902 
1903     Observer.changingInstr(MI);
1904     widenScalarDst(MI, WideTy, 0);
1905     Observer.changedInstr(MI);
1906     return Legalized;
1907   case TargetOpcode::G_BUILD_VECTOR: {
1908     Observer.changingInstr(MI);
1909 
1910     const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
1911     for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
1912       widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT);
1913 
1914     // Avoid changing the result vector type if the source element type was
1915     // requested.
1916     if (TypeIdx == 1) {
1917       auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
1918       MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
1919     } else {
1920       widenScalarDst(MI, WideTy, 0);
1921     }
1922 
1923     Observer.changedInstr(MI);
1924     return Legalized;
1925   }
1926   case TargetOpcode::G_SEXT_INREG:
1927     if (TypeIdx != 0)
1928       return UnableToLegalize;
1929 
1930     Observer.changingInstr(MI);
1931     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1932     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC);
1933     Observer.changedInstr(MI);
1934     return Legalized;
1935   }
1936 }
1937 
1938 LegalizerHelper::LegalizeResult
1939 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1940   using namespace TargetOpcode;
1941   MIRBuilder.setInstr(MI);
1942 
1943   switch(MI.getOpcode()) {
1944   default:
1945     return UnableToLegalize;
1946   case TargetOpcode::G_SREM:
1947   case TargetOpcode::G_UREM: {
1948     Register QuotReg = MRI.createGenericVirtualRegister(Ty);
1949     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1950         .addDef(QuotReg)
1951         .addUse(MI.getOperand(1).getReg())
1952         .addUse(MI.getOperand(2).getReg());
1953 
1954     Register ProdReg = MRI.createGenericVirtualRegister(Ty);
1955     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1956     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1957                         ProdReg);
1958     MI.eraseFromParent();
1959     return Legalized;
1960   }
1961   case TargetOpcode::G_SADDO:
1962   case TargetOpcode::G_SSUBO:
1963     return lowerSADDO_SSUBO(MI);
1964   case TargetOpcode::G_SMULO:
1965   case TargetOpcode::G_UMULO: {
1966     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
1967     // result.
1968     Register Res = MI.getOperand(0).getReg();
1969     Register Overflow = MI.getOperand(1).getReg();
1970     Register LHS = MI.getOperand(2).getReg();
1971     Register RHS = MI.getOperand(3).getReg();
1972 
1973     MIRBuilder.buildMul(Res, LHS, RHS);
1974 
1975     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
1976                           ? TargetOpcode::G_SMULH
1977                           : TargetOpcode::G_UMULH;
1978 
1979     Register HiPart = MRI.createGenericVirtualRegister(Ty);
1980     MIRBuilder.buildInstr(Opcode)
1981       .addDef(HiPart)
1982       .addUse(LHS)
1983       .addUse(RHS);
1984 
1985     Register Zero = MRI.createGenericVirtualRegister(Ty);
1986     MIRBuilder.buildConstant(Zero, 0);
1987 
1988     // For *signed* multiply, overflow is detected by checking:
1989     // (hi != (lo >> bitwidth-1))
1990     if (Opcode == TargetOpcode::G_SMULH) {
1991       Register Shifted = MRI.createGenericVirtualRegister(Ty);
1992       Register ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1993       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
1994       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
1995         .addDef(Shifted)
1996         .addUse(Res)
1997         .addUse(ShiftAmt);
1998       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
1999     } else {
2000       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
2001     }
2002     MI.eraseFromParent();
2003     return Legalized;
2004   }
2005   case TargetOpcode::G_FNEG: {
2006     // TODO: Handle vector types once we are able to
2007     // represent them.
2008     if (Ty.isVector())
2009       return UnableToLegalize;
2010     Register Res = MI.getOperand(0).getReg();
2011     Type *ZeroTy;
2012     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
2013     switch (Ty.getSizeInBits()) {
2014     case 16:
2015       ZeroTy = Type::getHalfTy(Ctx);
2016       break;
2017     case 32:
2018       ZeroTy = Type::getFloatTy(Ctx);
2019       break;
2020     case 64:
2021       ZeroTy = Type::getDoubleTy(Ctx);
2022       break;
2023     case 128:
2024       ZeroTy = Type::getFP128Ty(Ctx);
2025       break;
2026     default:
2027       llvm_unreachable("unexpected floating-point type");
2028     }
2029     ConstantFP &ZeroForNegation =
2030         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
2031     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
2032     Register SubByReg = MI.getOperand(1).getReg();
2033     Register ZeroReg = Zero->getOperand(0).getReg();
2034     MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
2035                           MI.getFlags());
2036     MI.eraseFromParent();
2037     return Legalized;
2038   }
2039   case TargetOpcode::G_FSUB: {
2040     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
2041     // First, check if G_FNEG is marked as Lower. If so, we may
2042     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
2043     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
2044       return UnableToLegalize;
2045     Register Res = MI.getOperand(0).getReg();
2046     Register LHS = MI.getOperand(1).getReg();
2047     Register RHS = MI.getOperand(2).getReg();
2048     Register Neg = MRI.createGenericVirtualRegister(Ty);
2049     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
2050     MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
2051     MI.eraseFromParent();
2052     return Legalized;
2053   }
2054   case TargetOpcode::G_FMAD:
2055     return lowerFMad(MI);
2056   case TargetOpcode::G_INTRINSIC_ROUND:
2057     return lowerIntrinsicRound(MI);
2058   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
2059     Register OldValRes = MI.getOperand(0).getReg();
2060     Register SuccessRes = MI.getOperand(1).getReg();
2061     Register Addr = MI.getOperand(2).getReg();
2062     Register CmpVal = MI.getOperand(3).getReg();
2063     Register NewVal = MI.getOperand(4).getReg();
2064     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
2065                                   **MI.memoperands_begin());
2066     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
2067     MI.eraseFromParent();
2068     return Legalized;
2069   }
2070   case TargetOpcode::G_LOAD:
2071   case TargetOpcode::G_SEXTLOAD:
2072   case TargetOpcode::G_ZEXTLOAD: {
2073     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
2074     Register DstReg = MI.getOperand(0).getReg();
2075     Register PtrReg = MI.getOperand(1).getReg();
2076     LLT DstTy = MRI.getType(DstReg);
2077     auto &MMO = **MI.memoperands_begin();
2078 
2079     if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
2080       if (MI.getOpcode() == TargetOpcode::G_LOAD) {
2081         // This load needs splitting into power of 2 sized loads.
2082         if (DstTy.isVector())
2083           return UnableToLegalize;
2084         if (isPowerOf2_32(DstTy.getSizeInBits()))
2085           return UnableToLegalize; // Don't know what we're being asked to do.
2086 
2087         // Our strategy here is to generate anyextending loads for the smaller
2088         // types up to next power-2 result type, and then combine the two larger
2089         // result values together, before truncating back down to the non-pow-2
2090         // type.
2091         // E.g. v1 = i24 load =>
2092         // v2 = i32 load (2 byte)
2093         // v3 = i32 load (1 byte)
2094         // v4 = i32 shl v3, 16
2095         // v5 = i32 or v4, v2
2096         // v1 = i24 trunc v5
2097         // By doing this we generate the correct truncate which should get
2098         // combined away as an artifact with a matching extend.
2099         uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits());
2100         uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize;
2101 
2102         MachineFunction &MF = MIRBuilder.getMF();
2103         MachineMemOperand *LargeMMO =
2104             MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2105         MachineMemOperand *SmallMMO = MF.getMachineMemOperand(
2106             &MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2107 
2108         LLT PtrTy = MRI.getType(PtrReg);
2109         unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits());
2110         LLT AnyExtTy = LLT::scalar(AnyExtSize);
2111         Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2112         Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2113         auto LargeLoad =
2114             MIRBuilder.buildLoad(LargeLdReg, PtrReg, *LargeMMO);
2115 
2116         auto OffsetCst =
2117             MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2118         Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2119         auto SmallPtr =
2120             MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2121         auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
2122                                               *SmallMMO);
2123 
2124         auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
2125         auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt);
2126         auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
2127         MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)});
2128         MI.eraseFromParent();
2129         return Legalized;
2130       }
2131       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
2132       MI.eraseFromParent();
2133       return Legalized;
2134     }
2135 
2136     if (DstTy.isScalar()) {
2137       Register TmpReg =
2138           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
2139       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
2140       switch (MI.getOpcode()) {
2141       default:
2142         llvm_unreachable("Unexpected opcode");
2143       case TargetOpcode::G_LOAD:
2144         MIRBuilder.buildExtOrTrunc(TargetOpcode::G_ANYEXT, DstReg, TmpReg);
2145         break;
2146       case TargetOpcode::G_SEXTLOAD:
2147         MIRBuilder.buildSExt(DstReg, TmpReg);
2148         break;
2149       case TargetOpcode::G_ZEXTLOAD:
2150         MIRBuilder.buildZExt(DstReg, TmpReg);
2151         break;
2152       }
2153       MI.eraseFromParent();
2154       return Legalized;
2155     }
2156 
2157     return UnableToLegalize;
2158   }
2159   case TargetOpcode::G_STORE: {
2160     // Lower a non-power of 2 store into multiple pow-2 stores.
2161     // E.g. split an i24 store into an i16 store + i8 store.
2162     // We do this by first extending the stored value to the next largest power
2163     // of 2 type, and then using truncating stores to store the components.
2164     // By doing this, likewise with G_LOAD, generate an extend that can be
2165     // artifact-combined away instead of leaving behind extracts.
2166     Register SrcReg = MI.getOperand(0).getReg();
2167     Register PtrReg = MI.getOperand(1).getReg();
2168     LLT SrcTy = MRI.getType(SrcReg);
2169     MachineMemOperand &MMO = **MI.memoperands_begin();
2170     if (SrcTy.getSizeInBits() != MMO.getSizeInBits())
2171       return UnableToLegalize;
2172     if (SrcTy.isVector())
2173       return UnableToLegalize;
2174     if (isPowerOf2_32(SrcTy.getSizeInBits()))
2175       return UnableToLegalize; // Don't know what we're being asked to do.
2176 
2177     // Extend to the next pow-2.
2178     const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits()));
2179     auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg);
2180 
2181     // Obtain the smaller value by shifting away the larger value.
2182     uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits());
2183     uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize;
2184     auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize);
2185     auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt);
2186 
2187     // Generate the PtrAdd and truncating stores.
2188     LLT PtrTy = MRI.getType(PtrReg);
2189     auto OffsetCst =
2190         MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2191     Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2192     auto SmallPtr =
2193         MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2194 
2195     MachineFunction &MF = MIRBuilder.getMF();
2196     MachineMemOperand *LargeMMO =
2197         MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2198     MachineMemOperand *SmallMMO =
2199         MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2200     MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO);
2201     MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO);
2202     MI.eraseFromParent();
2203     return Legalized;
2204   }
2205   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
2206   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
2207   case TargetOpcode::G_CTLZ:
2208   case TargetOpcode::G_CTTZ:
2209   case TargetOpcode::G_CTPOP:
2210     return lowerBitCount(MI, TypeIdx, Ty);
2211   case G_UADDO: {
2212     Register Res = MI.getOperand(0).getReg();
2213     Register CarryOut = MI.getOperand(1).getReg();
2214     Register LHS = MI.getOperand(2).getReg();
2215     Register RHS = MI.getOperand(3).getReg();
2216 
2217     MIRBuilder.buildAdd(Res, LHS, RHS);
2218     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
2219 
2220     MI.eraseFromParent();
2221     return Legalized;
2222   }
2223   case G_UADDE: {
2224     Register Res = MI.getOperand(0).getReg();
2225     Register CarryOut = MI.getOperand(1).getReg();
2226     Register LHS = MI.getOperand(2).getReg();
2227     Register RHS = MI.getOperand(3).getReg();
2228     Register CarryIn = MI.getOperand(4).getReg();
2229 
2230     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2231     Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
2232 
2233     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
2234     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
2235     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
2236     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
2237 
2238     MI.eraseFromParent();
2239     return Legalized;
2240   }
2241   case G_USUBO: {
2242     Register Res = MI.getOperand(0).getReg();
2243     Register BorrowOut = MI.getOperand(1).getReg();
2244     Register LHS = MI.getOperand(2).getReg();
2245     Register RHS = MI.getOperand(3).getReg();
2246 
2247     MIRBuilder.buildSub(Res, LHS, RHS);
2248     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
2249 
2250     MI.eraseFromParent();
2251     return Legalized;
2252   }
2253   case G_USUBE: {
2254     Register Res = MI.getOperand(0).getReg();
2255     Register BorrowOut = MI.getOperand(1).getReg();
2256     Register LHS = MI.getOperand(2).getReg();
2257     Register RHS = MI.getOperand(3).getReg();
2258     Register BorrowIn = MI.getOperand(4).getReg();
2259 
2260     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2261     Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
2262     Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2263     Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2264 
2265     MIRBuilder.buildSub(TmpRes, LHS, RHS);
2266     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
2267     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
2268     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
2269     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
2270     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
2271 
2272     MI.eraseFromParent();
2273     return Legalized;
2274   }
2275   case G_UITOFP:
2276     return lowerUITOFP(MI, TypeIdx, Ty);
2277   case G_SITOFP:
2278     return lowerSITOFP(MI, TypeIdx, Ty);
2279   case G_FPTOUI:
2280     return lowerFPTOUI(MI, TypeIdx, Ty);
2281   case G_SMIN:
2282   case G_SMAX:
2283   case G_UMIN:
2284   case G_UMAX:
2285     return lowerMinMax(MI, TypeIdx, Ty);
2286   case G_FCOPYSIGN:
2287     return lowerFCopySign(MI, TypeIdx, Ty);
2288   case G_FMINNUM:
2289   case G_FMAXNUM:
2290     return lowerFMinNumMaxNum(MI);
2291   case G_UNMERGE_VALUES:
2292     return lowerUnmergeValues(MI);
2293   case TargetOpcode::G_SEXT_INREG: {
2294     assert(MI.getOperand(2).isImm() && "Expected immediate");
2295     int64_t SizeInBits = MI.getOperand(2).getImm();
2296 
2297     Register DstReg = MI.getOperand(0).getReg();
2298     Register SrcReg = MI.getOperand(1).getReg();
2299     LLT DstTy = MRI.getType(DstReg);
2300     Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
2301 
2302     auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
2303     MIRBuilder.buildInstr(TargetOpcode::G_SHL, {TmpRes}, {SrcReg, MIBSz->getOperand(0).getReg()});
2304     MIRBuilder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {TmpRes, MIBSz->getOperand(0).getReg()});
2305     MI.eraseFromParent();
2306     return Legalized;
2307   }
2308   case G_SHUFFLE_VECTOR:
2309     return lowerShuffleVector(MI);
2310   case G_DYN_STACKALLOC:
2311     return lowerDynStackAlloc(MI);
2312   case G_EXTRACT:
2313     return lowerExtract(MI);
2314   case G_INSERT:
2315     return lowerInsert(MI);
2316   case G_BSWAP:
2317     return lowerBswap(MI);
2318   case G_BITREVERSE:
2319     return lowerBitreverse(MI);
2320   }
2321 }
2322 
2323 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
2324     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
2325   SmallVector<Register, 2> DstRegs;
2326 
2327   unsigned NarrowSize = NarrowTy.getSizeInBits();
2328   Register DstReg = MI.getOperand(0).getReg();
2329   unsigned Size = MRI.getType(DstReg).getSizeInBits();
2330   int NumParts = Size / NarrowSize;
2331   // FIXME: Don't know how to handle the situation where the small vectors
2332   // aren't all the same size yet.
2333   if (Size % NarrowSize != 0)
2334     return UnableToLegalize;
2335 
2336   for (int i = 0; i < NumParts; ++i) {
2337     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
2338     MIRBuilder.buildUndef(TmpReg);
2339     DstRegs.push_back(TmpReg);
2340   }
2341 
2342   if (NarrowTy.isVector())
2343     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2344   else
2345     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2346 
2347   MI.eraseFromParent();
2348   return Legalized;
2349 }
2350 
2351 LegalizerHelper::LegalizeResult
2352 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
2353                                           LLT NarrowTy) {
2354   const unsigned Opc = MI.getOpcode();
2355   const unsigned NumOps = MI.getNumOperands() - 1;
2356   const unsigned NarrowSize = NarrowTy.getSizeInBits();
2357   const Register DstReg = MI.getOperand(0).getReg();
2358   const unsigned Flags = MI.getFlags();
2359   const LLT DstTy = MRI.getType(DstReg);
2360   const unsigned Size = DstTy.getSizeInBits();
2361   const int NumParts = Size / NarrowSize;
2362   const LLT EltTy = DstTy.getElementType();
2363   const unsigned EltSize = EltTy.getSizeInBits();
2364   const unsigned BitsForNumParts = NarrowSize * NumParts;
2365 
2366   // Check if we have any leftovers. If we do, then only handle the case where
2367   // the leftover is one element.
2368   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
2369     return UnableToLegalize;
2370 
2371   if (BitsForNumParts != Size) {
2372     Register AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
2373     MIRBuilder.buildUndef(AccumDstReg);
2374 
2375     // Handle the pieces which evenly divide into the requested type with
2376     // extract/op/insert sequence.
2377     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
2378       SmallVector<SrcOp, 4> SrcOps;
2379       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2380         Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
2381         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
2382         SrcOps.push_back(PartOpReg);
2383       }
2384 
2385       Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
2386       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2387 
2388       Register PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
2389       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
2390       AccumDstReg = PartInsertReg;
2391     }
2392 
2393     // Handle the remaining element sized leftover piece.
2394     SmallVector<SrcOp, 4> SrcOps;
2395     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2396       Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
2397       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
2398                               BitsForNumParts);
2399       SrcOps.push_back(PartOpReg);
2400     }
2401 
2402     Register PartDstReg = MRI.createGenericVirtualRegister(EltTy);
2403     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2404     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
2405     MI.eraseFromParent();
2406 
2407     return Legalized;
2408   }
2409 
2410   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2411 
2412   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
2413 
2414   if (NumOps >= 2)
2415     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
2416 
2417   if (NumOps >= 3)
2418     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
2419 
2420   for (int i = 0; i < NumParts; ++i) {
2421     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2422 
2423     if (NumOps == 1)
2424       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
2425     else if (NumOps == 2) {
2426       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
2427     } else if (NumOps == 3) {
2428       MIRBuilder.buildInstr(Opc, {DstReg},
2429                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
2430     }
2431 
2432     DstRegs.push_back(DstReg);
2433   }
2434 
2435   if (NarrowTy.isVector())
2436     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2437   else
2438     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2439 
2440   MI.eraseFromParent();
2441   return Legalized;
2442 }
2443 
2444 // Handle splitting vector operations which need to have the same number of
2445 // elements in each type index, but each type index may have a different element
2446 // type.
2447 //
2448 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
2449 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2450 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2451 //
2452 // Also handles some irregular breakdown cases, e.g.
2453 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
2454 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2455 //             s64 = G_SHL s64, s32
2456 LegalizerHelper::LegalizeResult
2457 LegalizerHelper::fewerElementsVectorMultiEltType(
2458   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
2459   if (TypeIdx != 0)
2460     return UnableToLegalize;
2461 
2462   const LLT NarrowTy0 = NarrowTyArg;
2463   const unsigned NewNumElts =
2464       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
2465 
2466   const Register DstReg = MI.getOperand(0).getReg();
2467   LLT DstTy = MRI.getType(DstReg);
2468   LLT LeftoverTy0;
2469 
2470   // All of the operands need to have the same number of elements, so if we can
2471   // determine a type breakdown for the result type, we can for all of the
2472   // source types.
2473   int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first;
2474   if (NumParts < 0)
2475     return UnableToLegalize;
2476 
2477   SmallVector<MachineInstrBuilder, 4> NewInsts;
2478 
2479   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2480   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2481 
2482   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2483     LLT LeftoverTy;
2484     Register SrcReg = MI.getOperand(I).getReg();
2485     LLT SrcTyI = MRI.getType(SrcReg);
2486     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
2487     LLT LeftoverTyI;
2488 
2489     // Split this operand into the requested typed registers, and any leftover
2490     // required to reproduce the original type.
2491     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
2492                       LeftoverRegs))
2493       return UnableToLegalize;
2494 
2495     if (I == 1) {
2496       // For the first operand, create an instruction for each part and setup
2497       // the result.
2498       for (Register PartReg : PartRegs) {
2499         Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2500         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2501                                .addDef(PartDstReg)
2502                                .addUse(PartReg));
2503         DstRegs.push_back(PartDstReg);
2504       }
2505 
2506       for (Register LeftoverReg : LeftoverRegs) {
2507         Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
2508         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2509                                .addDef(PartDstReg)
2510                                .addUse(LeftoverReg));
2511         LeftoverDstRegs.push_back(PartDstReg);
2512       }
2513     } else {
2514       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
2515 
2516       // Add the newly created operand splits to the existing instructions. The
2517       // odd-sized pieces are ordered after the requested NarrowTyArg sized
2518       // pieces.
2519       unsigned InstCount = 0;
2520       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
2521         NewInsts[InstCount++].addUse(PartRegs[J]);
2522       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
2523         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
2524     }
2525 
2526     PartRegs.clear();
2527     LeftoverRegs.clear();
2528   }
2529 
2530   // Insert the newly built operations and rebuild the result register.
2531   for (auto &MIB : NewInsts)
2532     MIRBuilder.insertInstr(MIB);
2533 
2534   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
2535 
2536   MI.eraseFromParent();
2537   return Legalized;
2538 }
2539 
2540 LegalizerHelper::LegalizeResult
2541 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
2542                                           LLT NarrowTy) {
2543   if (TypeIdx != 0)
2544     return UnableToLegalize;
2545 
2546   Register DstReg = MI.getOperand(0).getReg();
2547   Register SrcReg = MI.getOperand(1).getReg();
2548   LLT DstTy = MRI.getType(DstReg);
2549   LLT SrcTy = MRI.getType(SrcReg);
2550 
2551   LLT NarrowTy0 = NarrowTy;
2552   LLT NarrowTy1;
2553   unsigned NumParts;
2554 
2555   if (NarrowTy.isVector()) {
2556     // Uneven breakdown not handled.
2557     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
2558     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
2559       return UnableToLegalize;
2560 
2561     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
2562   } else {
2563     NumParts = DstTy.getNumElements();
2564     NarrowTy1 = SrcTy.getElementType();
2565   }
2566 
2567   SmallVector<Register, 4> SrcRegs, DstRegs;
2568   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
2569 
2570   for (unsigned I = 0; I < NumParts; ++I) {
2571     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2572     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
2573       .addDef(DstReg)
2574       .addUse(SrcRegs[I]);
2575 
2576     NewInst->setFlags(MI.getFlags());
2577     DstRegs.push_back(DstReg);
2578   }
2579 
2580   if (NarrowTy.isVector())
2581     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2582   else
2583     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2584 
2585   MI.eraseFromParent();
2586   return Legalized;
2587 }
2588 
2589 LegalizerHelper::LegalizeResult
2590 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
2591                                         LLT NarrowTy) {
2592   Register DstReg = MI.getOperand(0).getReg();
2593   Register Src0Reg = MI.getOperand(2).getReg();
2594   LLT DstTy = MRI.getType(DstReg);
2595   LLT SrcTy = MRI.getType(Src0Reg);
2596 
2597   unsigned NumParts;
2598   LLT NarrowTy0, NarrowTy1;
2599 
2600   if (TypeIdx == 0) {
2601     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2602     unsigned OldElts = DstTy.getNumElements();
2603 
2604     NarrowTy0 = NarrowTy;
2605     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
2606     NarrowTy1 = NarrowTy.isVector() ?
2607       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
2608       SrcTy.getElementType();
2609 
2610   } else {
2611     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2612     unsigned OldElts = SrcTy.getNumElements();
2613 
2614     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
2615       NarrowTy.getNumElements();
2616     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
2617                             DstTy.getScalarSizeInBits());
2618     NarrowTy1 = NarrowTy;
2619   }
2620 
2621   // FIXME: Don't know how to handle the situation where the small vectors
2622   // aren't all the same size yet.
2623   if (NarrowTy1.isVector() &&
2624       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
2625     return UnableToLegalize;
2626 
2627   CmpInst::Predicate Pred
2628     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
2629 
2630   SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
2631   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
2632   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
2633 
2634   for (unsigned I = 0; I < NumParts; ++I) {
2635     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2636     DstRegs.push_back(DstReg);
2637 
2638     if (MI.getOpcode() == TargetOpcode::G_ICMP)
2639       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2640     else {
2641       MachineInstr *NewCmp
2642         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2643       NewCmp->setFlags(MI.getFlags());
2644     }
2645   }
2646 
2647   if (NarrowTy1.isVector())
2648     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2649   else
2650     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2651 
2652   MI.eraseFromParent();
2653   return Legalized;
2654 }
2655 
2656 LegalizerHelper::LegalizeResult
2657 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
2658                                            LLT NarrowTy) {
2659   Register DstReg = MI.getOperand(0).getReg();
2660   Register CondReg = MI.getOperand(1).getReg();
2661 
2662   unsigned NumParts = 0;
2663   LLT NarrowTy0, NarrowTy1;
2664 
2665   LLT DstTy = MRI.getType(DstReg);
2666   LLT CondTy = MRI.getType(CondReg);
2667   unsigned Size = DstTy.getSizeInBits();
2668 
2669   assert(TypeIdx == 0 || CondTy.isVector());
2670 
2671   if (TypeIdx == 0) {
2672     NarrowTy0 = NarrowTy;
2673     NarrowTy1 = CondTy;
2674 
2675     unsigned NarrowSize = NarrowTy0.getSizeInBits();
2676     // FIXME: Don't know how to handle the situation where the small vectors
2677     // aren't all the same size yet.
2678     if (Size % NarrowSize != 0)
2679       return UnableToLegalize;
2680 
2681     NumParts = Size / NarrowSize;
2682 
2683     // Need to break down the condition type
2684     if (CondTy.isVector()) {
2685       if (CondTy.getNumElements() == NumParts)
2686         NarrowTy1 = CondTy.getElementType();
2687       else
2688         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
2689                                 CondTy.getScalarSizeInBits());
2690     }
2691   } else {
2692     NumParts = CondTy.getNumElements();
2693     if (NarrowTy.isVector()) {
2694       // TODO: Handle uneven breakdown.
2695       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
2696         return UnableToLegalize;
2697 
2698       return UnableToLegalize;
2699     } else {
2700       NarrowTy0 = DstTy.getElementType();
2701       NarrowTy1 = NarrowTy;
2702     }
2703   }
2704 
2705   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2706   if (CondTy.isVector())
2707     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2708 
2709   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2710   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2711 
2712   for (unsigned i = 0; i < NumParts; ++i) {
2713     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2714     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
2715                            Src1Regs[i], Src2Regs[i]);
2716     DstRegs.push_back(DstReg);
2717   }
2718 
2719   if (NarrowTy0.isVector())
2720     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2721   else
2722     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2723 
2724   MI.eraseFromParent();
2725   return Legalized;
2726 }
2727 
2728 LegalizerHelper::LegalizeResult
2729 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2730                                         LLT NarrowTy) {
2731   const Register DstReg = MI.getOperand(0).getReg();
2732   LLT PhiTy = MRI.getType(DstReg);
2733   LLT LeftoverTy;
2734 
2735   // All of the operands need to have the same number of elements, so if we can
2736   // determine a type breakdown for the result type, we can for all of the
2737   // source types.
2738   int NumParts, NumLeftover;
2739   std::tie(NumParts, NumLeftover)
2740     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2741   if (NumParts < 0)
2742     return UnableToLegalize;
2743 
2744   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2745   SmallVector<MachineInstrBuilder, 4> NewInsts;
2746 
2747   const int TotalNumParts = NumParts + NumLeftover;
2748 
2749   // Insert the new phis in the result block first.
2750   for (int I = 0; I != TotalNumParts; ++I) {
2751     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2752     Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
2753     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2754                        .addDef(PartDstReg));
2755     if (I < NumParts)
2756       DstRegs.push_back(PartDstReg);
2757     else
2758       LeftoverDstRegs.push_back(PartDstReg);
2759   }
2760 
2761   MachineBasicBlock *MBB = MI.getParent();
2762   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2763   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2764 
2765   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2766 
2767   // Insert code to extract the incoming values in each predecessor block.
2768   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2769     PartRegs.clear();
2770     LeftoverRegs.clear();
2771 
2772     Register SrcReg = MI.getOperand(I).getReg();
2773     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2774     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2775 
2776     LLT Unused;
2777     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2778                       LeftoverRegs))
2779       return UnableToLegalize;
2780 
2781     // Add the newly created operand splits to the existing instructions. The
2782     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2783     // pieces.
2784     for (int J = 0; J != TotalNumParts; ++J) {
2785       MachineInstrBuilder MIB = NewInsts[J];
2786       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2787       MIB.addMBB(&OpMBB);
2788     }
2789   }
2790 
2791   MI.eraseFromParent();
2792   return Legalized;
2793 }
2794 
2795 LegalizerHelper::LegalizeResult
2796 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
2797                                                   unsigned TypeIdx,
2798                                                   LLT NarrowTy) {
2799   if (TypeIdx != 1)
2800     return UnableToLegalize;
2801 
2802   const int NumDst = MI.getNumOperands() - 1;
2803   const Register SrcReg = MI.getOperand(NumDst).getReg();
2804   LLT SrcTy = MRI.getType(SrcReg);
2805 
2806   LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2807 
2808   // TODO: Create sequence of extracts.
2809   if (DstTy == NarrowTy)
2810     return UnableToLegalize;
2811 
2812   LLT GCDTy = getGCDType(SrcTy, NarrowTy);
2813   if (DstTy == GCDTy) {
2814     // This would just be a copy of the same unmerge.
2815     // TODO: Create extracts, pad with undef and create intermediate merges.
2816     return UnableToLegalize;
2817   }
2818 
2819   auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
2820   const int NumUnmerge = Unmerge->getNumOperands() - 1;
2821   const int PartsPerUnmerge = NumDst / NumUnmerge;
2822 
2823   for (int I = 0; I != NumUnmerge; ++I) {
2824     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
2825 
2826     for (int J = 0; J != PartsPerUnmerge; ++J)
2827       MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg());
2828     MIB.addUse(Unmerge.getReg(I));
2829   }
2830 
2831   MI.eraseFromParent();
2832   return Legalized;
2833 }
2834 
2835 LegalizerHelper::LegalizeResult
2836 LegalizerHelper::fewerElementsVectorBuildVector(MachineInstr &MI,
2837                                                 unsigned TypeIdx,
2838                                                 LLT NarrowTy) {
2839   assert(TypeIdx == 0 && "not a vector type index");
2840   Register DstReg = MI.getOperand(0).getReg();
2841   LLT DstTy = MRI.getType(DstReg);
2842   LLT SrcTy = DstTy.getElementType();
2843 
2844   int DstNumElts = DstTy.getNumElements();
2845   int NarrowNumElts = NarrowTy.getNumElements();
2846   int NumConcat = (DstNumElts + NarrowNumElts - 1) / NarrowNumElts;
2847   LLT WidenedDstTy = LLT::vector(NarrowNumElts * NumConcat, SrcTy);
2848 
2849   SmallVector<Register, 8> ConcatOps;
2850   SmallVector<Register, 8> SubBuildVector;
2851 
2852   Register UndefReg;
2853   if (WidenedDstTy != DstTy)
2854     UndefReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
2855 
2856   // Create a G_CONCAT_VECTORS of NarrowTy pieces, padding with undef as
2857   // necessary.
2858   //
2859   // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2
2860   //   -> <2 x s16>
2861   //
2862   // %4:_(s16) = G_IMPLICIT_DEF
2863   // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1
2864   // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4
2865   // %7:_(<4 x s16>) = G_CONCAT_VECTORS %5, %6
2866   // %3:_(<3 x s16>) = G_EXTRACT %7, 0
2867   for (int I = 0; I != NumConcat; ++I) {
2868     for (int J = 0; J != NarrowNumElts; ++J) {
2869       int SrcIdx = NarrowNumElts * I + J;
2870 
2871       if (SrcIdx < DstNumElts) {
2872         Register SrcReg = MI.getOperand(SrcIdx + 1).getReg();
2873         SubBuildVector.push_back(SrcReg);
2874       } else
2875         SubBuildVector.push_back(UndefReg);
2876     }
2877 
2878     auto BuildVec = MIRBuilder.buildBuildVector(NarrowTy, SubBuildVector);
2879     ConcatOps.push_back(BuildVec.getReg(0));
2880     SubBuildVector.clear();
2881   }
2882 
2883   if (DstTy == WidenedDstTy)
2884     MIRBuilder.buildConcatVectors(DstReg, ConcatOps);
2885   else {
2886     auto Concat = MIRBuilder.buildConcatVectors(WidenedDstTy, ConcatOps);
2887     MIRBuilder.buildExtract(DstReg, Concat, 0);
2888   }
2889 
2890   MI.eraseFromParent();
2891   return Legalized;
2892 }
2893 
2894 LegalizerHelper::LegalizeResult
2895 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2896                                       LLT NarrowTy) {
2897   // FIXME: Don't know how to handle secondary types yet.
2898   if (TypeIdx != 0)
2899     return UnableToLegalize;
2900 
2901   MachineMemOperand *MMO = *MI.memoperands_begin();
2902 
2903   // This implementation doesn't work for atomics. Give up instead of doing
2904   // something invalid.
2905   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2906       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2907     return UnableToLegalize;
2908 
2909   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2910   Register ValReg = MI.getOperand(0).getReg();
2911   Register AddrReg = MI.getOperand(1).getReg();
2912   LLT ValTy = MRI.getType(ValReg);
2913 
2914   int NumParts = -1;
2915   int NumLeftover = -1;
2916   LLT LeftoverTy;
2917   SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
2918   if (IsLoad) {
2919     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2920   } else {
2921     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2922                      NarrowLeftoverRegs)) {
2923       NumParts = NarrowRegs.size();
2924       NumLeftover = NarrowLeftoverRegs.size();
2925     }
2926   }
2927 
2928   if (NumParts == -1)
2929     return UnableToLegalize;
2930 
2931   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2932 
2933   unsigned TotalSize = ValTy.getSizeInBits();
2934 
2935   // Split the load/store into PartTy sized pieces starting at Offset. If this
2936   // is a load, return the new registers in ValRegs. For a store, each elements
2937   // of ValRegs should be PartTy. Returns the next offset that needs to be
2938   // handled.
2939   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
2940                              unsigned Offset) -> unsigned {
2941     MachineFunction &MF = MIRBuilder.getMF();
2942     unsigned PartSize = PartTy.getSizeInBits();
2943     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2944          Offset += PartSize, ++Idx) {
2945       unsigned ByteSize = PartSize / 8;
2946       unsigned ByteOffset = Offset / 8;
2947       Register NewAddrReg;
2948 
2949       MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2950 
2951       MachineMemOperand *NewMMO =
2952         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2953 
2954       if (IsLoad) {
2955         Register Dst = MRI.createGenericVirtualRegister(PartTy);
2956         ValRegs.push_back(Dst);
2957         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
2958       } else {
2959         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
2960       }
2961     }
2962 
2963     return Offset;
2964   };
2965 
2966   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
2967 
2968   // Handle the rest of the register if this isn't an even type breakdown.
2969   if (LeftoverTy.isValid())
2970     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
2971 
2972   if (IsLoad) {
2973     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
2974                 LeftoverTy, NarrowLeftoverRegs);
2975   }
2976 
2977   MI.eraseFromParent();
2978   return Legalized;
2979 }
2980 
2981 LegalizerHelper::LegalizeResult
2982 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
2983                                      LLT NarrowTy) {
2984   using namespace TargetOpcode;
2985 
2986   MIRBuilder.setInstr(MI);
2987   switch (MI.getOpcode()) {
2988   case G_IMPLICIT_DEF:
2989     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
2990   case G_AND:
2991   case G_OR:
2992   case G_XOR:
2993   case G_ADD:
2994   case G_SUB:
2995   case G_MUL:
2996   case G_SMULH:
2997   case G_UMULH:
2998   case G_FADD:
2999   case G_FMUL:
3000   case G_FSUB:
3001   case G_FNEG:
3002   case G_FABS:
3003   case G_FCANONICALIZE:
3004   case G_FDIV:
3005   case G_FREM:
3006   case G_FMA:
3007   case G_FMAD:
3008   case G_FPOW:
3009   case G_FEXP:
3010   case G_FEXP2:
3011   case G_FLOG:
3012   case G_FLOG2:
3013   case G_FLOG10:
3014   case G_FNEARBYINT:
3015   case G_FCEIL:
3016   case G_FFLOOR:
3017   case G_FRINT:
3018   case G_INTRINSIC_ROUND:
3019   case G_INTRINSIC_TRUNC:
3020   case G_FCOS:
3021   case G_FSIN:
3022   case G_FSQRT:
3023   case G_BSWAP:
3024   case G_BITREVERSE:
3025   case G_SDIV:
3026   case G_UDIV:
3027   case G_SREM:
3028   case G_UREM:
3029   case G_SMIN:
3030   case G_SMAX:
3031   case G_UMIN:
3032   case G_UMAX:
3033   case G_FMINNUM:
3034   case G_FMAXNUM:
3035   case G_FMINNUM_IEEE:
3036   case G_FMAXNUM_IEEE:
3037   case G_FMINIMUM:
3038   case G_FMAXIMUM:
3039     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
3040   case G_SHL:
3041   case G_LSHR:
3042   case G_ASHR:
3043   case G_CTLZ:
3044   case G_CTLZ_ZERO_UNDEF:
3045   case G_CTTZ:
3046   case G_CTTZ_ZERO_UNDEF:
3047   case G_CTPOP:
3048   case G_FCOPYSIGN:
3049     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
3050   case G_ZEXT:
3051   case G_SEXT:
3052   case G_ANYEXT:
3053   case G_FPEXT:
3054   case G_FPTRUNC:
3055   case G_SITOFP:
3056   case G_UITOFP:
3057   case G_FPTOSI:
3058   case G_FPTOUI:
3059   case G_INTTOPTR:
3060   case G_PTRTOINT:
3061   case G_ADDRSPACE_CAST:
3062     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
3063   case G_ICMP:
3064   case G_FCMP:
3065     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
3066   case G_SELECT:
3067     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
3068   case G_PHI:
3069     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
3070   case G_UNMERGE_VALUES:
3071     return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy);
3072   case G_BUILD_VECTOR:
3073     return fewerElementsVectorBuildVector(MI, TypeIdx, NarrowTy);
3074   case G_LOAD:
3075   case G_STORE:
3076     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
3077   default:
3078     return UnableToLegalize;
3079   }
3080 }
3081 
3082 LegalizerHelper::LegalizeResult
3083 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
3084                                              const LLT HalfTy, const LLT AmtTy) {
3085 
3086   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3087   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3088   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3089 
3090   if (Amt.isNullValue()) {
3091     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
3092     MI.eraseFromParent();
3093     return Legalized;
3094   }
3095 
3096   LLT NVT = HalfTy;
3097   unsigned NVTBits = HalfTy.getSizeInBits();
3098   unsigned VTBits = 2 * NVTBits;
3099 
3100   SrcOp Lo(Register(0)), Hi(Register(0));
3101   if (MI.getOpcode() == TargetOpcode::G_SHL) {
3102     if (Amt.ugt(VTBits)) {
3103       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3104     } else if (Amt.ugt(NVTBits)) {
3105       Lo = MIRBuilder.buildConstant(NVT, 0);
3106       Hi = MIRBuilder.buildShl(NVT, InL,
3107                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3108     } else if (Amt == NVTBits) {
3109       Lo = MIRBuilder.buildConstant(NVT, 0);
3110       Hi = InL;
3111     } else {
3112       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
3113       auto OrLHS =
3114           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
3115       auto OrRHS = MIRBuilder.buildLShr(
3116           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3117       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3118     }
3119   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3120     if (Amt.ugt(VTBits)) {
3121       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3122     } else if (Amt.ugt(NVTBits)) {
3123       Lo = MIRBuilder.buildLShr(NVT, InH,
3124                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3125       Hi = MIRBuilder.buildConstant(NVT, 0);
3126     } else if (Amt == NVTBits) {
3127       Lo = InH;
3128       Hi = MIRBuilder.buildConstant(NVT, 0);
3129     } else {
3130       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3131 
3132       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3133       auto OrRHS = MIRBuilder.buildShl(
3134           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3135 
3136       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3137       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
3138     }
3139   } else {
3140     if (Amt.ugt(VTBits)) {
3141       Hi = Lo = MIRBuilder.buildAShr(
3142           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3143     } else if (Amt.ugt(NVTBits)) {
3144       Lo = MIRBuilder.buildAShr(NVT, InH,
3145                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3146       Hi = MIRBuilder.buildAShr(NVT, InH,
3147                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3148     } else if (Amt == NVTBits) {
3149       Lo = InH;
3150       Hi = MIRBuilder.buildAShr(NVT, InH,
3151                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3152     } else {
3153       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3154 
3155       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3156       auto OrRHS = MIRBuilder.buildShl(
3157           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3158 
3159       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3160       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
3161     }
3162   }
3163 
3164   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
3165   MI.eraseFromParent();
3166 
3167   return Legalized;
3168 }
3169 
3170 // TODO: Optimize if constant shift amount.
3171 LegalizerHelper::LegalizeResult
3172 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
3173                                    LLT RequestedTy) {
3174   if (TypeIdx == 1) {
3175     Observer.changingInstr(MI);
3176     narrowScalarSrc(MI, RequestedTy, 2);
3177     Observer.changedInstr(MI);
3178     return Legalized;
3179   }
3180 
3181   Register DstReg = MI.getOperand(0).getReg();
3182   LLT DstTy = MRI.getType(DstReg);
3183   if (DstTy.isVector())
3184     return UnableToLegalize;
3185 
3186   Register Amt = MI.getOperand(2).getReg();
3187   LLT ShiftAmtTy = MRI.getType(Amt);
3188   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
3189   if (DstEltSize % 2 != 0)
3190     return UnableToLegalize;
3191 
3192   // Ignore the input type. We can only go to exactly half the size of the
3193   // input. If that isn't small enough, the resulting pieces will be further
3194   // legalized.
3195   const unsigned NewBitSize = DstEltSize / 2;
3196   const LLT HalfTy = LLT::scalar(NewBitSize);
3197   const LLT CondTy = LLT::scalar(1);
3198 
3199   if (const MachineInstr *KShiftAmt =
3200           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
3201     return narrowScalarShiftByConstant(
3202         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
3203   }
3204 
3205   // TODO: Expand with known bits.
3206 
3207   // Handle the fully general expansion by an unknown amount.
3208   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
3209 
3210   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3211   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3212   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3213 
3214   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
3215   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
3216 
3217   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
3218   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
3219   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
3220 
3221   Register ResultRegs[2];
3222   switch (MI.getOpcode()) {
3223   case TargetOpcode::G_SHL: {
3224     // Short: ShAmt < NewBitSize
3225     auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt);
3226 
3227     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
3228     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt);
3229     auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3230 
3231     // Long: ShAmt >= NewBitSize
3232     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
3233     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
3234 
3235     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
3236     auto Hi = MIRBuilder.buildSelect(
3237         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
3238 
3239     ResultRegs[0] = Lo.getReg(0);
3240     ResultRegs[1] = Hi.getReg(0);
3241     break;
3242   }
3243   case TargetOpcode::G_LSHR:
3244   case TargetOpcode::G_ASHR: {
3245     // Short: ShAmt < NewBitSize
3246     auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt});
3247 
3248     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt);
3249     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
3250     auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3251 
3252     // Long: ShAmt >= NewBitSize
3253     MachineInstrBuilder HiL;
3254     if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3255       HiL = MIRBuilder.buildConstant(HalfTy, 0);            // Hi part is zero.
3256     } else {
3257       auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1);
3258       HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt);    // Sign of Hi part.
3259     }
3260     auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy},
3261                                      {InH, AmtExcess});     // Lo from Hi part.
3262 
3263     auto Lo = MIRBuilder.buildSelect(
3264         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
3265 
3266     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
3267 
3268     ResultRegs[0] = Lo.getReg(0);
3269     ResultRegs[1] = Hi.getReg(0);
3270     break;
3271   }
3272   default:
3273     llvm_unreachable("not a shift");
3274   }
3275 
3276   MIRBuilder.buildMerge(DstReg, ResultRegs);
3277   MI.eraseFromParent();
3278   return Legalized;
3279 }
3280 
3281 LegalizerHelper::LegalizeResult
3282 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
3283                                        LLT MoreTy) {
3284   assert(TypeIdx == 0 && "Expecting only Idx 0");
3285 
3286   Observer.changingInstr(MI);
3287   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
3288     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
3289     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
3290     moreElementsVectorSrc(MI, MoreTy, I);
3291   }
3292 
3293   MachineBasicBlock &MBB = *MI.getParent();
3294   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
3295   moreElementsVectorDst(MI, MoreTy, 0);
3296   Observer.changedInstr(MI);
3297   return Legalized;
3298 }
3299 
3300 LegalizerHelper::LegalizeResult
3301 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
3302                                     LLT MoreTy) {
3303   MIRBuilder.setInstr(MI);
3304   unsigned Opc = MI.getOpcode();
3305   switch (Opc) {
3306   case TargetOpcode::G_IMPLICIT_DEF:
3307   case TargetOpcode::G_LOAD: {
3308     if (TypeIdx != 0)
3309       return UnableToLegalize;
3310     Observer.changingInstr(MI);
3311     moreElementsVectorDst(MI, MoreTy, 0);
3312     Observer.changedInstr(MI);
3313     return Legalized;
3314   }
3315   case TargetOpcode::G_STORE:
3316     if (TypeIdx != 0)
3317       return UnableToLegalize;
3318     Observer.changingInstr(MI);
3319     moreElementsVectorSrc(MI, MoreTy, 0);
3320     Observer.changedInstr(MI);
3321     return Legalized;
3322   case TargetOpcode::G_AND:
3323   case TargetOpcode::G_OR:
3324   case TargetOpcode::G_XOR:
3325   case TargetOpcode::G_SMIN:
3326   case TargetOpcode::G_SMAX:
3327   case TargetOpcode::G_UMIN:
3328   case TargetOpcode::G_UMAX:
3329   case TargetOpcode::G_FMINNUM:
3330   case TargetOpcode::G_FMAXNUM:
3331   case TargetOpcode::G_FMINNUM_IEEE:
3332   case TargetOpcode::G_FMAXNUM_IEEE:
3333   case TargetOpcode::G_FMINIMUM:
3334   case TargetOpcode::G_FMAXIMUM: {
3335     Observer.changingInstr(MI);
3336     moreElementsVectorSrc(MI, MoreTy, 1);
3337     moreElementsVectorSrc(MI, MoreTy, 2);
3338     moreElementsVectorDst(MI, MoreTy, 0);
3339     Observer.changedInstr(MI);
3340     return Legalized;
3341   }
3342   case TargetOpcode::G_EXTRACT:
3343     if (TypeIdx != 1)
3344       return UnableToLegalize;
3345     Observer.changingInstr(MI);
3346     moreElementsVectorSrc(MI, MoreTy, 1);
3347     Observer.changedInstr(MI);
3348     return Legalized;
3349   case TargetOpcode::G_INSERT:
3350     if (TypeIdx != 0)
3351       return UnableToLegalize;
3352     Observer.changingInstr(MI);
3353     moreElementsVectorSrc(MI, MoreTy, 1);
3354     moreElementsVectorDst(MI, MoreTy, 0);
3355     Observer.changedInstr(MI);
3356     return Legalized;
3357   case TargetOpcode::G_SELECT:
3358     if (TypeIdx != 0)
3359       return UnableToLegalize;
3360     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
3361       return UnableToLegalize;
3362 
3363     Observer.changingInstr(MI);
3364     moreElementsVectorSrc(MI, MoreTy, 2);
3365     moreElementsVectorSrc(MI, MoreTy, 3);
3366     moreElementsVectorDst(MI, MoreTy, 0);
3367     Observer.changedInstr(MI);
3368     return Legalized;
3369   case TargetOpcode::G_UNMERGE_VALUES: {
3370     if (TypeIdx != 1)
3371       return UnableToLegalize;
3372 
3373     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
3374     int NumDst = MI.getNumOperands() - 1;
3375     moreElementsVectorSrc(MI, MoreTy, NumDst);
3376 
3377     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
3378     for (int I = 0; I != NumDst; ++I)
3379       MIB.addDef(MI.getOperand(I).getReg());
3380 
3381     int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits();
3382     for (int I = NumDst; I != NewNumDst; ++I)
3383       MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
3384 
3385     MIB.addUse(MI.getOperand(NumDst).getReg());
3386     MI.eraseFromParent();
3387     return Legalized;
3388   }
3389   case TargetOpcode::G_PHI:
3390     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
3391   default:
3392     return UnableToLegalize;
3393   }
3394 }
3395 
3396 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
3397                                         ArrayRef<Register> Src1Regs,
3398                                         ArrayRef<Register> Src2Regs,
3399                                         LLT NarrowTy) {
3400   MachineIRBuilder &B = MIRBuilder;
3401   unsigned SrcParts = Src1Regs.size();
3402   unsigned DstParts = DstRegs.size();
3403 
3404   unsigned DstIdx = 0; // Low bits of the result.
3405   Register FactorSum =
3406       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
3407   DstRegs[DstIdx] = FactorSum;
3408 
3409   unsigned CarrySumPrevDstIdx;
3410   SmallVector<Register, 4> Factors;
3411 
3412   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
3413     // Collect low parts of muls for DstIdx.
3414     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
3415          i <= std::min(DstIdx, SrcParts - 1); ++i) {
3416       MachineInstrBuilder Mul =
3417           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
3418       Factors.push_back(Mul.getReg(0));
3419     }
3420     // Collect high parts of muls from previous DstIdx.
3421     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
3422          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
3423       MachineInstrBuilder Umulh =
3424           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
3425       Factors.push_back(Umulh.getReg(0));
3426     }
3427     // Add CarrySum from additions calculated for previous DstIdx.
3428     if (DstIdx != 1) {
3429       Factors.push_back(CarrySumPrevDstIdx);
3430     }
3431 
3432     Register CarrySum;
3433     // Add all factors and accumulate all carries into CarrySum.
3434     if (DstIdx != DstParts - 1) {
3435       MachineInstrBuilder Uaddo =
3436           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
3437       FactorSum = Uaddo.getReg(0);
3438       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
3439       for (unsigned i = 2; i < Factors.size(); ++i) {
3440         MachineInstrBuilder Uaddo =
3441             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
3442         FactorSum = Uaddo.getReg(0);
3443         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
3444         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
3445       }
3446     } else {
3447       // Since value for the next index is not calculated, neither is CarrySum.
3448       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
3449       for (unsigned i = 2; i < Factors.size(); ++i)
3450         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
3451     }
3452 
3453     CarrySumPrevDstIdx = CarrySum;
3454     DstRegs[DstIdx] = FactorSum;
3455     Factors.clear();
3456   }
3457 }
3458 
3459 LegalizerHelper::LegalizeResult
3460 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
3461   Register DstReg = MI.getOperand(0).getReg();
3462   Register Src1 = MI.getOperand(1).getReg();
3463   Register Src2 = MI.getOperand(2).getReg();
3464 
3465   LLT Ty = MRI.getType(DstReg);
3466   if (Ty.isVector())
3467     return UnableToLegalize;
3468 
3469   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
3470   unsigned DstSize = Ty.getSizeInBits();
3471   unsigned NarrowSize = NarrowTy.getSizeInBits();
3472   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
3473     return UnableToLegalize;
3474 
3475   unsigned NumDstParts = DstSize / NarrowSize;
3476   unsigned NumSrcParts = SrcSize / NarrowSize;
3477   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
3478   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
3479 
3480   SmallVector<Register, 2> Src1Parts, Src2Parts, DstTmpRegs;
3481   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
3482   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
3483   DstTmpRegs.resize(DstTmpParts);
3484   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
3485 
3486   // Take only high half of registers if this is high mul.
3487   ArrayRef<Register> DstRegs(
3488       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
3489   MIRBuilder.buildMerge(DstReg, DstRegs);
3490   MI.eraseFromParent();
3491   return Legalized;
3492 }
3493 
3494 LegalizerHelper::LegalizeResult
3495 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
3496                                      LLT NarrowTy) {
3497   if (TypeIdx != 1)
3498     return UnableToLegalize;
3499 
3500   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3501 
3502   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
3503   // FIXME: add support for when SizeOp1 isn't an exact multiple of
3504   // NarrowSize.
3505   if (SizeOp1 % NarrowSize != 0)
3506     return UnableToLegalize;
3507   int NumParts = SizeOp1 / NarrowSize;
3508 
3509   SmallVector<Register, 2> SrcRegs, DstRegs;
3510   SmallVector<uint64_t, 2> Indexes;
3511   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3512 
3513   Register OpReg = MI.getOperand(0).getReg();
3514   uint64_t OpStart = MI.getOperand(2).getImm();
3515   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3516   for (int i = 0; i < NumParts; ++i) {
3517     unsigned SrcStart = i * NarrowSize;
3518 
3519     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
3520       // No part of the extract uses this subregister, ignore it.
3521       continue;
3522     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3523       // The entire subregister is extracted, forward the value.
3524       DstRegs.push_back(SrcRegs[i]);
3525       continue;
3526     }
3527 
3528     // OpSegStart is where this destination segment would start in OpReg if it
3529     // extended infinitely in both directions.
3530     int64_t ExtractOffset;
3531     uint64_t SegSize;
3532     if (OpStart < SrcStart) {
3533       ExtractOffset = 0;
3534       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
3535     } else {
3536       ExtractOffset = OpStart - SrcStart;
3537       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
3538     }
3539 
3540     Register SegReg = SrcRegs[i];
3541     if (ExtractOffset != 0 || SegSize != NarrowSize) {
3542       // A genuine extract is needed.
3543       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3544       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
3545     }
3546 
3547     DstRegs.push_back(SegReg);
3548   }
3549 
3550   Register DstReg = MI.getOperand(0).getReg();
3551   if(MRI.getType(DstReg).isVector())
3552     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3553   else
3554     MIRBuilder.buildMerge(DstReg, DstRegs);
3555   MI.eraseFromParent();
3556   return Legalized;
3557 }
3558 
3559 LegalizerHelper::LegalizeResult
3560 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
3561                                     LLT NarrowTy) {
3562   // FIXME: Don't know how to handle secondary types yet.
3563   if (TypeIdx != 0)
3564     return UnableToLegalize;
3565 
3566   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
3567   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3568 
3569   // FIXME: add support for when SizeOp0 isn't an exact multiple of
3570   // NarrowSize.
3571   if (SizeOp0 % NarrowSize != 0)
3572     return UnableToLegalize;
3573 
3574   int NumParts = SizeOp0 / NarrowSize;
3575 
3576   SmallVector<Register, 2> SrcRegs, DstRegs;
3577   SmallVector<uint64_t, 2> Indexes;
3578   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3579 
3580   Register OpReg = MI.getOperand(2).getReg();
3581   uint64_t OpStart = MI.getOperand(3).getImm();
3582   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3583   for (int i = 0; i < NumParts; ++i) {
3584     unsigned DstStart = i * NarrowSize;
3585 
3586     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
3587       // No part of the insert affects this subregister, forward the original.
3588       DstRegs.push_back(SrcRegs[i]);
3589       continue;
3590     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3591       // The entire subregister is defined by this insert, forward the new
3592       // value.
3593       DstRegs.push_back(OpReg);
3594       continue;
3595     }
3596 
3597     // OpSegStart is where this destination segment would start in OpReg if it
3598     // extended infinitely in both directions.
3599     int64_t ExtractOffset, InsertOffset;
3600     uint64_t SegSize;
3601     if (OpStart < DstStart) {
3602       InsertOffset = 0;
3603       ExtractOffset = DstStart - OpStart;
3604       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
3605     } else {
3606       InsertOffset = OpStart - DstStart;
3607       ExtractOffset = 0;
3608       SegSize =
3609         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
3610     }
3611 
3612     Register SegReg = OpReg;
3613     if (ExtractOffset != 0 || SegSize != OpSize) {
3614       // A genuine extract is needed.
3615       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3616       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
3617     }
3618 
3619     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
3620     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
3621     DstRegs.push_back(DstReg);
3622   }
3623 
3624   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
3625   Register DstReg = MI.getOperand(0).getReg();
3626   if(MRI.getType(DstReg).isVector())
3627     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3628   else
3629     MIRBuilder.buildMerge(DstReg, DstRegs);
3630   MI.eraseFromParent();
3631   return Legalized;
3632 }
3633 
3634 LegalizerHelper::LegalizeResult
3635 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
3636                                    LLT NarrowTy) {
3637   Register DstReg = MI.getOperand(0).getReg();
3638   LLT DstTy = MRI.getType(DstReg);
3639 
3640   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
3641 
3642   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3643   SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
3644   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3645   LLT LeftoverTy;
3646   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
3647                     Src0Regs, Src0LeftoverRegs))
3648     return UnableToLegalize;
3649 
3650   LLT Unused;
3651   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
3652                     Src1Regs, Src1LeftoverRegs))
3653     llvm_unreachable("inconsistent extractParts result");
3654 
3655   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3656     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
3657                                         {Src0Regs[I], Src1Regs[I]});
3658     DstRegs.push_back(Inst->getOperand(0).getReg());
3659   }
3660 
3661   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3662     auto Inst = MIRBuilder.buildInstr(
3663       MI.getOpcode(),
3664       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
3665     DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
3666   }
3667 
3668   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3669               LeftoverTy, DstLeftoverRegs);
3670 
3671   MI.eraseFromParent();
3672   return Legalized;
3673 }
3674 
3675 LegalizerHelper::LegalizeResult
3676 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
3677                                     LLT NarrowTy) {
3678   if (TypeIdx != 0)
3679     return UnableToLegalize;
3680 
3681   Register CondReg = MI.getOperand(1).getReg();
3682   LLT CondTy = MRI.getType(CondReg);
3683   if (CondTy.isVector()) // TODO: Handle vselect
3684     return UnableToLegalize;
3685 
3686   Register DstReg = MI.getOperand(0).getReg();
3687   LLT DstTy = MRI.getType(DstReg);
3688 
3689   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3690   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3691   SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
3692   LLT LeftoverTy;
3693   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
3694                     Src1Regs, Src1LeftoverRegs))
3695     return UnableToLegalize;
3696 
3697   LLT Unused;
3698   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
3699                     Src2Regs, Src2LeftoverRegs))
3700     llvm_unreachable("inconsistent extractParts result");
3701 
3702   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3703     auto Select = MIRBuilder.buildSelect(NarrowTy,
3704                                          CondReg, Src1Regs[I], Src2Regs[I]);
3705     DstRegs.push_back(Select->getOperand(0).getReg());
3706   }
3707 
3708   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3709     auto Select = MIRBuilder.buildSelect(
3710       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
3711     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
3712   }
3713 
3714   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3715               LeftoverTy, DstLeftoverRegs);
3716 
3717   MI.eraseFromParent();
3718   return Legalized;
3719 }
3720 
3721 LegalizerHelper::LegalizeResult
3722 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3723   unsigned Opc = MI.getOpcode();
3724   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
3725   auto isSupported = [this](const LegalityQuery &Q) {
3726     auto QAction = LI.getAction(Q).Action;
3727     return QAction == Legal || QAction == Libcall || QAction == Custom;
3728   };
3729   switch (Opc) {
3730   default:
3731     return UnableToLegalize;
3732   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
3733     // This trivially expands to CTLZ.
3734     Observer.changingInstr(MI);
3735     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
3736     Observer.changedInstr(MI);
3737     return Legalized;
3738   }
3739   case TargetOpcode::G_CTLZ: {
3740     Register SrcReg = MI.getOperand(1).getReg();
3741     unsigned Len = Ty.getSizeInBits();
3742     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
3743       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
3744       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
3745                                              {Ty}, {SrcReg});
3746       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3747       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3748       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3749                                           SrcReg, MIBZero);
3750       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3751                              MIBCtlzZU);
3752       MI.eraseFromParent();
3753       return Legalized;
3754     }
3755     // for now, we do this:
3756     // NewLen = NextPowerOf2(Len);
3757     // x = x | (x >> 1);
3758     // x = x | (x >> 2);
3759     // ...
3760     // x = x | (x >>16);
3761     // x = x | (x >>32); // for 64-bit input
3762     // Upto NewLen/2
3763     // return Len - popcount(x);
3764     //
3765     // Ref: "Hacker's Delight" by Henry Warren
3766     Register Op = SrcReg;
3767     unsigned NewLen = PowerOf2Ceil(Len);
3768     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
3769       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
3770       auto MIBOp = MIRBuilder.buildInstr(
3771           TargetOpcode::G_OR, {Ty},
3772           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
3773                                      {Op, MIBShiftAmt})});
3774       Op = MIBOp->getOperand(0).getReg();
3775     }
3776     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
3777     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3778                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
3779     MI.eraseFromParent();
3780     return Legalized;
3781   }
3782   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
3783     // This trivially expands to CTTZ.
3784     Observer.changingInstr(MI);
3785     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
3786     Observer.changedInstr(MI);
3787     return Legalized;
3788   }
3789   case TargetOpcode::G_CTTZ: {
3790     Register SrcReg = MI.getOperand(1).getReg();
3791     unsigned Len = Ty.getSizeInBits();
3792     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
3793       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
3794       // zero.
3795       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
3796                                              {Ty}, {SrcReg});
3797       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3798       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3799       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3800                                           SrcReg, MIBZero);
3801       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3802                              MIBCttzZU);
3803       MI.eraseFromParent();
3804       return Legalized;
3805     }
3806     // for now, we use: { return popcount(~x & (x - 1)); }
3807     // unless the target has ctlz but not ctpop, in which case we use:
3808     // { return 32 - nlz(~x & (x-1)); }
3809     // Ref: "Hacker's Delight" by Henry Warren
3810     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
3811     auto MIBNot =
3812         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
3813     auto MIBTmp = MIRBuilder.buildInstr(
3814         TargetOpcode::G_AND, {Ty},
3815         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
3816                                        {SrcReg, MIBCstNeg1})});
3817     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
3818         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
3819       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
3820       MIRBuilder.buildInstr(
3821           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3822           {MIBCstLen,
3823            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
3824       MI.eraseFromParent();
3825       return Legalized;
3826     }
3827     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
3828     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3829     return Legalized;
3830   }
3831   }
3832 }
3833 
3834 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
3835 // representation.
3836 LegalizerHelper::LegalizeResult
3837 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
3838   Register Dst = MI.getOperand(0).getReg();
3839   Register Src = MI.getOperand(1).getReg();
3840   const LLT S64 = LLT::scalar(64);
3841   const LLT S32 = LLT::scalar(32);
3842   const LLT S1 = LLT::scalar(1);
3843 
3844   assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
3845 
3846   // unsigned cul2f(ulong u) {
3847   //   uint lz = clz(u);
3848   //   uint e = (u != 0) ? 127U + 63U - lz : 0;
3849   //   u = (u << lz) & 0x7fffffffffffffffUL;
3850   //   ulong t = u & 0xffffffffffUL;
3851   //   uint v = (e << 23) | (uint)(u >> 40);
3852   //   uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
3853   //   return as_float(v + r);
3854   // }
3855 
3856   auto Zero32 = MIRBuilder.buildConstant(S32, 0);
3857   auto Zero64 = MIRBuilder.buildConstant(S64, 0);
3858 
3859   auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
3860 
3861   auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
3862   auto Sub = MIRBuilder.buildSub(S32, K, LZ);
3863 
3864   auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
3865   auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
3866 
3867   auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
3868   auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
3869 
3870   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
3871 
3872   auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
3873   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
3874 
3875   auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
3876   auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
3877   auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
3878 
3879   auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
3880   auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
3881   auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
3882   auto One = MIRBuilder.buildConstant(S32, 1);
3883 
3884   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
3885   auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
3886   auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
3887   MIRBuilder.buildAdd(Dst, V, R);
3888 
3889   return Legalized;
3890 }
3891 
3892 LegalizerHelper::LegalizeResult
3893 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3894   Register Dst = MI.getOperand(0).getReg();
3895   Register Src = MI.getOperand(1).getReg();
3896   LLT DstTy = MRI.getType(Dst);
3897   LLT SrcTy = MRI.getType(Src);
3898 
3899   if (SrcTy == LLT::scalar(1)) {
3900     auto True = MIRBuilder.buildFConstant(DstTy, 1.0);
3901     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
3902     MIRBuilder.buildSelect(Dst, Src, True, False);
3903     MI.eraseFromParent();
3904     return Legalized;
3905   }
3906 
3907   if (SrcTy != LLT::scalar(64))
3908     return UnableToLegalize;
3909 
3910   if (DstTy == LLT::scalar(32)) {
3911     // TODO: SelectionDAG has several alternative expansions to port which may
3912     // be more reasonble depending on the available instructions. If a target
3913     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
3914     // intermediate type, this is probably worse.
3915     return lowerU64ToF32BitOps(MI);
3916   }
3917 
3918   return UnableToLegalize;
3919 }
3920 
3921 LegalizerHelper::LegalizeResult
3922 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3923   Register Dst = MI.getOperand(0).getReg();
3924   Register Src = MI.getOperand(1).getReg();
3925   LLT DstTy = MRI.getType(Dst);
3926   LLT SrcTy = MRI.getType(Src);
3927 
3928   const LLT S64 = LLT::scalar(64);
3929   const LLT S32 = LLT::scalar(32);
3930   const LLT S1 = LLT::scalar(1);
3931 
3932   if (SrcTy == S1) {
3933     auto True = MIRBuilder.buildFConstant(DstTy, -1.0);
3934     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
3935     MIRBuilder.buildSelect(Dst, Src, True, False);
3936     MI.eraseFromParent();
3937     return Legalized;
3938   }
3939 
3940   if (SrcTy != S64)
3941     return UnableToLegalize;
3942 
3943   if (DstTy == S32) {
3944     // signed cl2f(long l) {
3945     //   long s = l >> 63;
3946     //   float r = cul2f((l + s) ^ s);
3947     //   return s ? -r : r;
3948     // }
3949     Register L = Src;
3950     auto SignBit = MIRBuilder.buildConstant(S64, 63);
3951     auto S = MIRBuilder.buildAShr(S64, L, SignBit);
3952 
3953     auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
3954     auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
3955     auto R = MIRBuilder.buildUITOFP(S32, Xor);
3956 
3957     auto RNeg = MIRBuilder.buildFNeg(S32, R);
3958     auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
3959                                             MIRBuilder.buildConstant(S64, 0));
3960     MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
3961     return Legalized;
3962   }
3963 
3964   return UnableToLegalize;
3965 }
3966 
3967 LegalizerHelper::LegalizeResult
3968 LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3969   Register Dst = MI.getOperand(0).getReg();
3970   Register Src = MI.getOperand(1).getReg();
3971   LLT DstTy = MRI.getType(Dst);
3972   LLT SrcTy = MRI.getType(Src);
3973   const LLT S64 = LLT::scalar(64);
3974   const LLT S32 = LLT::scalar(32);
3975 
3976   if (SrcTy != S64 && SrcTy != S32)
3977     return UnableToLegalize;
3978   if (DstTy != S32 && DstTy != S64)
3979     return UnableToLegalize;
3980 
3981   // FPTOSI gives same result as FPTOUI for positive signed integers.
3982   // FPTOUI needs to deal with fp values that convert to unsigned integers
3983   // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp.
3984 
3985   APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits());
3986   APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle()
3987                                                 : APFloat::IEEEdouble(),
3988                     APInt::getNullValue(SrcTy.getSizeInBits()));
3989   TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven);
3990 
3991   MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src);
3992 
3993   MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP);
3994   // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on
3995   // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1.
3996   MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold);
3997   MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub);
3998   MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt);
3999   MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit);
4000 
4001   const LLT S1 = LLT::scalar(1);
4002 
4003   MachineInstrBuilder FCMP =
4004       MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold);
4005   MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res);
4006 
4007   MI.eraseFromParent();
4008   return Legalized;
4009 }
4010 
4011 static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
4012   switch (Opc) {
4013   case TargetOpcode::G_SMIN:
4014     return CmpInst::ICMP_SLT;
4015   case TargetOpcode::G_SMAX:
4016     return CmpInst::ICMP_SGT;
4017   case TargetOpcode::G_UMIN:
4018     return CmpInst::ICMP_ULT;
4019   case TargetOpcode::G_UMAX:
4020     return CmpInst::ICMP_UGT;
4021   default:
4022     llvm_unreachable("not in integer min/max");
4023   }
4024 }
4025 
4026 LegalizerHelper::LegalizeResult
4027 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4028   Register Dst = MI.getOperand(0).getReg();
4029   Register Src0 = MI.getOperand(1).getReg();
4030   Register Src1 = MI.getOperand(2).getReg();
4031 
4032   const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
4033   LLT CmpType = MRI.getType(Dst).changeElementSize(1);
4034 
4035   auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
4036   MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
4037 
4038   MI.eraseFromParent();
4039   return Legalized;
4040 }
4041 
4042 LegalizerHelper::LegalizeResult
4043 LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4044   Register Dst = MI.getOperand(0).getReg();
4045   Register Src0 = MI.getOperand(1).getReg();
4046   Register Src1 = MI.getOperand(2).getReg();
4047 
4048   const LLT Src0Ty = MRI.getType(Src0);
4049   const LLT Src1Ty = MRI.getType(Src1);
4050 
4051   const int Src0Size = Src0Ty.getScalarSizeInBits();
4052   const int Src1Size = Src1Ty.getScalarSizeInBits();
4053 
4054   auto SignBitMask = MIRBuilder.buildConstant(
4055     Src0Ty, APInt::getSignMask(Src0Size));
4056 
4057   auto NotSignBitMask = MIRBuilder.buildConstant(
4058     Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
4059 
4060   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
4061   MachineInstr *Or;
4062 
4063   if (Src0Ty == Src1Ty) {
4064     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
4065     Or = MIRBuilder.buildOr(Dst, And0, And1);
4066   } else if (Src0Size > Src1Size) {
4067     auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
4068     auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
4069     auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
4070     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
4071     Or = MIRBuilder.buildOr(Dst, And0, And1);
4072   } else {
4073     auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
4074     auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
4075     auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
4076     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
4077     Or = MIRBuilder.buildOr(Dst, And0, And1);
4078   }
4079 
4080   // Be careful about setting nsz/nnan/ninf on every instruction, since the
4081   // constants are a nan and -0.0, but the final result should preserve
4082   // everything.
4083   if (unsigned Flags = MI.getFlags())
4084     Or->setFlags(Flags);
4085 
4086   MI.eraseFromParent();
4087   return Legalized;
4088 }
4089 
4090 LegalizerHelper::LegalizeResult
4091 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
4092   unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ?
4093     TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE;
4094 
4095   Register Dst = MI.getOperand(0).getReg();
4096   Register Src0 = MI.getOperand(1).getReg();
4097   Register Src1 = MI.getOperand(2).getReg();
4098   LLT Ty = MRI.getType(Dst);
4099 
4100   if (!MI.getFlag(MachineInstr::FmNoNans)) {
4101     // Insert canonicalizes if it's possible we need to quiet to get correct
4102     // sNaN behavior.
4103 
4104     // Note this must be done here, and not as an optimization combine in the
4105     // absence of a dedicate quiet-snan instruction as we're using an
4106     // omni-purpose G_FCANONICALIZE.
4107     if (!isKnownNeverSNaN(Src0, MRI))
4108       Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0);
4109 
4110     if (!isKnownNeverSNaN(Src1, MRI))
4111       Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0);
4112   }
4113 
4114   // If there are no nans, it's safe to simply replace this with the non-IEEE
4115   // version.
4116   MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags());
4117   MI.eraseFromParent();
4118   return Legalized;
4119 }
4120 
4121 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) {
4122   // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c
4123   Register DstReg = MI.getOperand(0).getReg();
4124   LLT Ty = MRI.getType(DstReg);
4125   unsigned Flags = MI.getFlags();
4126 
4127   auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2),
4128                                   Flags);
4129   MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags);
4130   MI.eraseFromParent();
4131   return Legalized;
4132 }
4133 
4134 LegalizerHelper::LegalizeResult
4135 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) {
4136   Register DstReg = MI.getOperand(0).getReg();
4137   Register SrcReg = MI.getOperand(1).getReg();
4138   unsigned Flags = MI.getFlags();
4139   LLT Ty = MRI.getType(DstReg);
4140   const LLT CondTy = Ty.changeElementSize(1);
4141 
4142   // result = trunc(src);
4143   // if (src < 0.0 && src != result)
4144   //   result += -1.0.
4145 
4146   auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
4147   auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags);
4148 
4149   auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy,
4150                                   SrcReg, Zero, Flags);
4151   auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy,
4152                                       SrcReg, Trunc, Flags);
4153   auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc);
4154   auto AddVal = MIRBuilder.buildSITOFP(Ty, And);
4155 
4156   MIRBuilder.buildFAdd(DstReg, Trunc, AddVal);
4157   MI.eraseFromParent();
4158   return Legalized;
4159 }
4160 
4161 LegalizerHelper::LegalizeResult
4162 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
4163   const unsigned NumDst = MI.getNumOperands() - 1;
4164   const Register SrcReg = MI.getOperand(NumDst).getReg();
4165   LLT SrcTy = MRI.getType(SrcReg);
4166 
4167   Register Dst0Reg = MI.getOperand(0).getReg();
4168   LLT DstTy = MRI.getType(Dst0Reg);
4169 
4170 
4171   // Expand scalarizing unmerge as bitcast to integer and shift.
4172   if (!DstTy.isVector() && SrcTy.isVector() &&
4173       SrcTy.getElementType() == DstTy) {
4174     LLT IntTy = LLT::scalar(SrcTy.getSizeInBits());
4175     Register Cast = MIRBuilder.buildBitcast(IntTy, SrcReg).getReg(0);
4176 
4177     MIRBuilder.buildTrunc(Dst0Reg, Cast);
4178 
4179     const unsigned DstSize = DstTy.getSizeInBits();
4180     unsigned Offset = DstSize;
4181     for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
4182       auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
4183       auto Shift = MIRBuilder.buildLShr(IntTy, Cast, ShiftAmt);
4184       MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
4185     }
4186 
4187     MI.eraseFromParent();
4188     return Legalized;
4189   }
4190 
4191   return UnableToLegalize;
4192 }
4193 
4194 LegalizerHelper::LegalizeResult
4195 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
4196   Register DstReg = MI.getOperand(0).getReg();
4197   Register Src0Reg = MI.getOperand(1).getReg();
4198   Register Src1Reg = MI.getOperand(2).getReg();
4199   LLT Src0Ty = MRI.getType(Src0Reg);
4200   LLT DstTy = MRI.getType(DstReg);
4201   LLT IdxTy = LLT::scalar(32);
4202 
4203   const Constant *ShufMask = MI.getOperand(3).getShuffleMask();
4204 
4205   SmallVector<int, 32> Mask;
4206   ShuffleVectorInst::getShuffleMask(ShufMask, Mask);
4207 
4208   if (DstTy.isScalar()) {
4209     if (Src0Ty.isVector())
4210       return UnableToLegalize;
4211 
4212     // This is just a SELECT.
4213     assert(Mask.size() == 1 && "Expected a single mask element");
4214     Register Val;
4215     if (Mask[0] < 0 || Mask[0] > 1)
4216       Val = MIRBuilder.buildUndef(DstTy).getReg(0);
4217     else
4218       Val = Mask[0] == 0 ? Src0Reg : Src1Reg;
4219     MIRBuilder.buildCopy(DstReg, Val);
4220     MI.eraseFromParent();
4221     return Legalized;
4222   }
4223 
4224   Register Undef;
4225   SmallVector<Register, 32> BuildVec;
4226   LLT EltTy = DstTy.getElementType();
4227 
4228   for (int Idx : Mask) {
4229     if (Idx < 0) {
4230       if (!Undef.isValid())
4231         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);
4232       BuildVec.push_back(Undef);
4233       continue;
4234     }
4235 
4236     if (Src0Ty.isScalar()) {
4237       BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
4238     } else {
4239       int NumElts = Src0Ty.getNumElements();
4240       Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
4241       int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
4242       auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
4243       auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
4244       BuildVec.push_back(Extract.getReg(0));
4245     }
4246   }
4247 
4248   MIRBuilder.buildBuildVector(DstReg, BuildVec);
4249   MI.eraseFromParent();
4250   return Legalized;
4251 }
4252 
4253 LegalizerHelper::LegalizeResult
4254 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) {
4255   Register Dst = MI.getOperand(0).getReg();
4256   Register AllocSize = MI.getOperand(1).getReg();
4257   unsigned Align = MI.getOperand(2).getImm();
4258 
4259   const auto &MF = *MI.getMF();
4260   const auto &TLI = *MF.getSubtarget().getTargetLowering();
4261 
4262   LLT PtrTy = MRI.getType(Dst);
4263   LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
4264 
4265   Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
4266   auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg);
4267   SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp);
4268 
4269   // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't
4270   // have to generate an extra instruction to negate the alloc and then use
4271   // G_PTR_ADD to add the negative offset.
4272   auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize);
4273   if (Align) {
4274     APInt AlignMask(IntPtrTy.getSizeInBits(), Align, true);
4275     AlignMask.negate();
4276     auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask);
4277     Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst);
4278   }
4279 
4280   SPTmp = MIRBuilder.buildCast(PtrTy, Alloc);
4281   MIRBuilder.buildCopy(SPReg, SPTmp);
4282   MIRBuilder.buildCopy(Dst, SPTmp);
4283 
4284   MI.eraseFromParent();
4285   return Legalized;
4286 }
4287 
4288 LegalizerHelper::LegalizeResult
4289 LegalizerHelper::lowerExtract(MachineInstr &MI) {
4290   Register Dst = MI.getOperand(0).getReg();
4291   Register Src = MI.getOperand(1).getReg();
4292   unsigned Offset = MI.getOperand(2).getImm();
4293 
4294   LLT DstTy = MRI.getType(Dst);
4295   LLT SrcTy = MRI.getType(Src);
4296 
4297   if (DstTy.isScalar() &&
4298       (SrcTy.isScalar() ||
4299        (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
4300     LLT SrcIntTy = SrcTy;
4301     if (!SrcTy.isScalar()) {
4302       SrcIntTy = LLT::scalar(SrcTy.getSizeInBits());
4303       Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0);
4304     }
4305 
4306     if (Offset == 0)
4307       MIRBuilder.buildTrunc(Dst, Src);
4308     else {
4309       auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset);
4310       auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt);
4311       MIRBuilder.buildTrunc(Dst, Shr);
4312     }
4313 
4314     MI.eraseFromParent();
4315     return Legalized;
4316   }
4317 
4318   return UnableToLegalize;
4319 }
4320 
4321 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
4322   Register Dst = MI.getOperand(0).getReg();
4323   Register Src = MI.getOperand(1).getReg();
4324   Register InsertSrc = MI.getOperand(2).getReg();
4325   uint64_t Offset = MI.getOperand(3).getImm();
4326 
4327   LLT DstTy = MRI.getType(Src);
4328   LLT InsertTy = MRI.getType(InsertSrc);
4329 
4330   if (InsertTy.isScalar() &&
4331       (DstTy.isScalar() ||
4332        (DstTy.isVector() && DstTy.getElementType() == InsertTy))) {
4333     LLT IntDstTy = DstTy;
4334     if (!DstTy.isScalar()) {
4335       IntDstTy = LLT::scalar(DstTy.getSizeInBits());
4336       Src = MIRBuilder.buildBitcast(IntDstTy, Src).getReg(0);
4337     }
4338 
4339     Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0);
4340     if (Offset != 0) {
4341       auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset);
4342       ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0);
4343     }
4344 
4345     APInt MaskVal = ~APInt::getBitsSet(DstTy.getSizeInBits(), Offset,
4346                                        InsertTy.getSizeInBits());
4347 
4348     auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal);
4349     auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);
4350     auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc);
4351 
4352     MIRBuilder.buildBitcast(Dst, Or);
4353     MI.eraseFromParent();
4354     return Legalized;
4355   }
4356 
4357   return UnableToLegalize;
4358 }
4359 
4360 LegalizerHelper::LegalizeResult
4361 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {
4362   Register Dst0 = MI.getOperand(0).getReg();
4363   Register Dst1 = MI.getOperand(1).getReg();
4364   Register LHS = MI.getOperand(2).getReg();
4365   Register RHS = MI.getOperand(3).getReg();
4366   const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO;
4367 
4368   LLT Ty = MRI.getType(Dst0);
4369   LLT BoolTy = MRI.getType(Dst1);
4370 
4371   if (IsAdd)
4372     MIRBuilder.buildAdd(Dst0, LHS, RHS);
4373   else
4374     MIRBuilder.buildSub(Dst0, LHS, RHS);
4375 
4376   // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
4377 
4378   auto Zero = MIRBuilder.buildConstant(Ty, 0);
4379 
4380   // For an addition, the result should be less than one of the operands (LHS)
4381   // if and only if the other operand (RHS) is negative, otherwise there will
4382   // be overflow.
4383   // For a subtraction, the result should be less than one of the operands
4384   // (LHS) if and only if the other operand (RHS) is (non-zero) positive,
4385   // otherwise there will be overflow.
4386   auto ResultLowerThanLHS =
4387       MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS);
4388   auto ConditionRHS = MIRBuilder.buildICmp(
4389       IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero);
4390 
4391   MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS);
4392   MI.eraseFromParent();
4393   return Legalized;
4394 }
4395 
4396 LegalizerHelper::LegalizeResult
4397 LegalizerHelper::lowerBswap(MachineInstr &MI) {
4398   Register Dst = MI.getOperand(0).getReg();
4399   Register Src = MI.getOperand(1).getReg();
4400   const LLT Ty = MRI.getType(Src);
4401   unsigned SizeInBytes = Ty.getSizeInBytes();
4402   unsigned BaseShiftAmt = (SizeInBytes - 1) * 8;
4403 
4404   // Swap most and least significant byte, set remaining bytes in Res to zero.
4405   auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt);
4406   auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt);
4407   auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
4408   auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft);
4409 
4410   // Set i-th high/low byte in Res to i-th low/high byte from Src.
4411   for (unsigned i = 1; i < SizeInBytes / 2; ++i) {
4412     // AND with Mask leaves byte i unchanged and sets remaining bytes to 0.
4413     APInt APMask(SizeInBytes * 8, 0xFF << (i * 8));
4414     auto Mask = MIRBuilder.buildConstant(Ty, APMask);
4415     auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i);
4416     // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt.
4417     auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask);
4418     auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt);
4419     Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft);
4420     // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask.
4421     auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
4422     auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask);
4423     Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight);
4424   }
4425   Res.getInstr()->getOperand(0).setReg(Dst);
4426 
4427   MI.eraseFromParent();
4428   return Legalized;
4429 }
4430 
4431 //{ (Src & Mask) >> N } | { (Src << N) & Mask }
4432 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B,
4433                                  MachineInstrBuilder Src, APInt Mask) {
4434   const LLT Ty = Dst.getLLTTy(*B.getMRI());
4435   MachineInstrBuilder C_N = B.buildConstant(Ty, N);
4436   MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask);
4437   auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N);
4438   auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0);
4439   return B.buildOr(Dst, LHS, RHS);
4440 }
4441 
4442 LegalizerHelper::LegalizeResult
4443 LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
4444   Register Dst = MI.getOperand(0).getReg();
4445   Register Src = MI.getOperand(1).getReg();
4446   const LLT Ty = MRI.getType(Src);
4447   unsigned Size = Ty.getSizeInBits();
4448 
4449   MachineInstrBuilder BSWAP =
4450       MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src});
4451 
4452   // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654
4453   //    [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4]
4454   // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0]
4455   MachineInstrBuilder Swap4 =
4456       SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0)));
4457 
4458   // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76
4459   //    [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2]
4460   // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC]
4461   MachineInstrBuilder Swap2 =
4462       SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC)));
4463 
4464   // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7
4465   //    [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1]
4466   // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA]
4467   SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA)));
4468 
4469   MI.eraseFromParent();
4470   return Legalized;
4471 }
4472