1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetFrameLowering.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetLowering.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 
28 #define DEBUG_TYPE "legalizer"
29 
30 using namespace llvm;
31 using namespace LegalizeActions;
32 
33 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
34 ///
35 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
36 /// with any leftover piece as type \p LeftoverTy
37 ///
38 /// Returns -1 in the first element of the pair if the breakdown is not
39 /// satisfiable.
40 static std::pair<int, int>
41 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
42   assert(!LeftoverTy.isValid() && "this is an out argument");
43 
44   unsigned Size = OrigTy.getSizeInBits();
45   unsigned NarrowSize = NarrowTy.getSizeInBits();
46   unsigned NumParts = Size / NarrowSize;
47   unsigned LeftoverSize = Size - NumParts * NarrowSize;
48   assert(Size > NarrowSize);
49 
50   if (LeftoverSize == 0)
51     return {NumParts, 0};
52 
53   if (NarrowTy.isVector()) {
54     unsigned EltSize = OrigTy.getScalarSizeInBits();
55     if (LeftoverSize % EltSize != 0)
56       return {-1, -1};
57     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
58   } else {
59     LeftoverTy = LLT::scalar(LeftoverSize);
60   }
61 
62   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
63   return std::make_pair(NumParts, NumLeftover);
64 }
65 
66 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
67                                  GISelChangeObserver &Observer,
68                                  MachineIRBuilder &Builder)
69     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
70       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
71   MIRBuilder.setMF(MF);
72   MIRBuilder.setChangeObserver(Observer);
73 }
74 
75 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
76                                  GISelChangeObserver &Observer,
77                                  MachineIRBuilder &B)
78     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
79   MIRBuilder.setMF(MF);
80   MIRBuilder.setChangeObserver(Observer);
81 }
82 LegalizerHelper::LegalizeResult
83 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
84   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
85 
86   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
87       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
88     return LI.legalizeIntrinsic(MI, MRI, MIRBuilder) ? Legalized
89                                                      : UnableToLegalize;
90   auto Step = LI.getAction(MI, MRI);
91   switch (Step.Action) {
92   case Legal:
93     LLVM_DEBUG(dbgs() << ".. Already legal\n");
94     return AlreadyLegal;
95   case Libcall:
96     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
97     return libcall(MI);
98   case NarrowScalar:
99     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
100     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
101   case WidenScalar:
102     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
103     return widenScalar(MI, Step.TypeIdx, Step.NewType);
104   case Lower:
105     LLVM_DEBUG(dbgs() << ".. Lower\n");
106     return lower(MI, Step.TypeIdx, Step.NewType);
107   case FewerElements:
108     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
109     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
110   case MoreElements:
111     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
112     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
113   case Custom:
114     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
115     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
116                                                             : UnableToLegalize;
117   default:
118     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
119     return UnableToLegalize;
120   }
121 }
122 
123 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
124                                    SmallVectorImpl<Register> &VRegs) {
125   for (int i = 0; i < NumParts; ++i)
126     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
127   MIRBuilder.buildUnmerge(VRegs, Reg);
128 }
129 
130 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
131                                    LLT MainTy, LLT &LeftoverTy,
132                                    SmallVectorImpl<Register> &VRegs,
133                                    SmallVectorImpl<Register> &LeftoverRegs) {
134   assert(!LeftoverTy.isValid() && "this is an out argument");
135 
136   unsigned RegSize = RegTy.getSizeInBits();
137   unsigned MainSize = MainTy.getSizeInBits();
138   unsigned NumParts = RegSize / MainSize;
139   unsigned LeftoverSize = RegSize - NumParts * MainSize;
140 
141   // Use an unmerge when possible.
142   if (LeftoverSize == 0) {
143     for (unsigned I = 0; I < NumParts; ++I)
144       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
145     MIRBuilder.buildUnmerge(VRegs, Reg);
146     return true;
147   }
148 
149   if (MainTy.isVector()) {
150     unsigned EltSize = MainTy.getScalarSizeInBits();
151     if (LeftoverSize % EltSize != 0)
152       return false;
153     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
154   } else {
155     LeftoverTy = LLT::scalar(LeftoverSize);
156   }
157 
158   // For irregular sizes, extract the individual parts.
159   for (unsigned I = 0; I != NumParts; ++I) {
160     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
161     VRegs.push_back(NewReg);
162     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
163   }
164 
165   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
166        Offset += LeftoverSize) {
167     Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
168     LeftoverRegs.push_back(NewReg);
169     MIRBuilder.buildExtract(NewReg, Reg, Offset);
170   }
171 
172   return true;
173 }
174 
175 static LLT getGCDType(LLT OrigTy, LLT TargetTy) {
176   if (OrigTy.isVector() && TargetTy.isVector()) {
177     assert(OrigTy.getElementType() == TargetTy.getElementType());
178     int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
179                                     TargetTy.getNumElements());
180     return LLT::scalarOrVector(GCD, OrigTy.getElementType());
181   }
182 
183   if (OrigTy.isVector() && !TargetTy.isVector()) {
184     assert(OrigTy.getElementType() == TargetTy);
185     return TargetTy;
186   }
187 
188   assert(!OrigTy.isVector() && !TargetTy.isVector());
189 
190   int GCD = greatestCommonDivisor(OrigTy.getSizeInBits(),
191                                   TargetTy.getSizeInBits());
192   return LLT::scalar(GCD);
193 }
194 
195 void LegalizerHelper::insertParts(Register DstReg,
196                                   LLT ResultTy, LLT PartTy,
197                                   ArrayRef<Register> PartRegs,
198                                   LLT LeftoverTy,
199                                   ArrayRef<Register> LeftoverRegs) {
200   if (!LeftoverTy.isValid()) {
201     assert(LeftoverRegs.empty());
202 
203     if (!ResultTy.isVector()) {
204       MIRBuilder.buildMerge(DstReg, PartRegs);
205       return;
206     }
207 
208     if (PartTy.isVector())
209       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
210     else
211       MIRBuilder.buildBuildVector(DstReg, PartRegs);
212     return;
213   }
214 
215   unsigned PartSize = PartTy.getSizeInBits();
216   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
217 
218   Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
219   MIRBuilder.buildUndef(CurResultReg);
220 
221   unsigned Offset = 0;
222   for (Register PartReg : PartRegs) {
223     Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
224     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
225     CurResultReg = NewResultReg;
226     Offset += PartSize;
227   }
228 
229   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
230     // Use the original output register for the final insert to avoid a copy.
231     Register NewResultReg = (I + 1 == E) ?
232       DstReg : MRI.createGenericVirtualRegister(ResultTy);
233 
234     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
235     CurResultReg = NewResultReg;
236     Offset += LeftoverPartSize;
237   }
238 }
239 
240 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
241   switch (Opcode) {
242   case TargetOpcode::G_SDIV:
243     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
244     switch (Size) {
245     case 32:
246       return RTLIB::SDIV_I32;
247     case 64:
248       return RTLIB::SDIV_I64;
249     case 128:
250       return RTLIB::SDIV_I128;
251     default:
252       llvm_unreachable("unexpected size");
253     }
254   case TargetOpcode::G_UDIV:
255     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
256     switch (Size) {
257     case 32:
258       return RTLIB::UDIV_I32;
259     case 64:
260       return RTLIB::UDIV_I64;
261     case 128:
262       return RTLIB::UDIV_I128;
263     default:
264       llvm_unreachable("unexpected size");
265     }
266   case TargetOpcode::G_SREM:
267     assert((Size == 32 || Size == 64) && "Unsupported size");
268     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
269   case TargetOpcode::G_UREM:
270     assert((Size == 32 || Size == 64) && "Unsupported size");
271     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
272   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
273     assert(Size == 32 && "Unsupported size");
274     return RTLIB::CTLZ_I32;
275   case TargetOpcode::G_FADD:
276     assert((Size == 32 || Size == 64) && "Unsupported size");
277     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
278   case TargetOpcode::G_FSUB:
279     assert((Size == 32 || Size == 64) && "Unsupported size");
280     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
281   case TargetOpcode::G_FMUL:
282     assert((Size == 32 || Size == 64) && "Unsupported size");
283     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
284   case TargetOpcode::G_FDIV:
285     assert((Size == 32 || Size == 64) && "Unsupported size");
286     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
287   case TargetOpcode::G_FEXP:
288     assert((Size == 32 || Size == 64) && "Unsupported size");
289     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
290   case TargetOpcode::G_FEXP2:
291     assert((Size == 32 || Size == 64) && "Unsupported size");
292     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
293   case TargetOpcode::G_FREM:
294     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
295   case TargetOpcode::G_FPOW:
296     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
297   case TargetOpcode::G_FMA:
298     assert((Size == 32 || Size == 64) && "Unsupported size");
299     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
300   case TargetOpcode::G_FSIN:
301     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
302     return Size == 128 ? RTLIB::SIN_F128
303                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
304   case TargetOpcode::G_FCOS:
305     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
306     return Size == 128 ? RTLIB::COS_F128
307                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
308   case TargetOpcode::G_FLOG10:
309     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
310     return Size == 128 ? RTLIB::LOG10_F128
311                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
312   case TargetOpcode::G_FLOG:
313     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
314     return Size == 128 ? RTLIB::LOG_F128
315                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
316   case TargetOpcode::G_FLOG2:
317     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
318     return Size == 128 ? RTLIB::LOG2_F128
319                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
320   case TargetOpcode::G_FCEIL:
321     assert((Size == 32 || Size == 64) && "Unsupported size");
322     return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
323   case TargetOpcode::G_FFLOOR:
324     assert((Size == 32 || Size == 64) && "Unsupported size");
325     return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
326   }
327   llvm_unreachable("Unknown libcall function");
328 }
329 
330 /// True if an instruction is in tail position in its caller. Intended for
331 /// legalizing libcalls as tail calls when possible.
332 static bool isLibCallInTailPosition(MachineInstr &MI) {
333   const Function &F = MI.getParent()->getParent()->getFunction();
334 
335   // Conservatively require the attributes of the call to match those of
336   // the return. Ignore NoAlias and NonNull because they don't affect the
337   // call sequence.
338   AttributeList CallerAttrs = F.getAttributes();
339   if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
340           .removeAttribute(Attribute::NoAlias)
341           .removeAttribute(Attribute::NonNull)
342           .hasAttributes())
343     return false;
344 
345   // It's not safe to eliminate the sign / zero extension of the return value.
346   if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
347       CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
348     return false;
349 
350   // Only tail call if the following instruction is a standard return.
351   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
352   MachineInstr *Next = MI.getNextNode();
353   if (!Next || TII.isTailCall(*Next) || !Next->isReturn())
354     return false;
355 
356   return true;
357 }
358 
359 LegalizerHelper::LegalizeResult
360 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
361                     const CallLowering::ArgInfo &Result,
362                     ArrayRef<CallLowering::ArgInfo> Args) {
363   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
364   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
365   const char *Name = TLI.getLibcallName(Libcall);
366 
367   CallLowering::CallLoweringInfo Info;
368   Info.CallConv = TLI.getLibcallCallingConv(Libcall);
369   Info.Callee = MachineOperand::CreateES(Name);
370   Info.OrigRet = Result;
371   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
372   if (!CLI.lowerCall(MIRBuilder, Info))
373     return LegalizerHelper::UnableToLegalize;
374 
375   return LegalizerHelper::Legalized;
376 }
377 
378 // Useful for libcalls where all operands have the same type.
379 static LegalizerHelper::LegalizeResult
380 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
381               Type *OpType) {
382   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
383 
384   SmallVector<CallLowering::ArgInfo, 3> Args;
385   for (unsigned i = 1; i < MI.getNumOperands(); i++)
386     Args.push_back({MI.getOperand(i).getReg(), OpType});
387   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
388                        Args);
389 }
390 
391 LegalizerHelper::LegalizeResult
392 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
393                        MachineInstr &MI) {
394   assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
395   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
396 
397   SmallVector<CallLowering::ArgInfo, 3> Args;
398   // Add all the args, except for the last which is an imm denoting 'tail'.
399   for (unsigned i = 1; i < MI.getNumOperands() - 1; i++) {
400     Register Reg = MI.getOperand(i).getReg();
401 
402     // Need derive an IR type for call lowering.
403     LLT OpLLT = MRI.getType(Reg);
404     Type *OpTy = nullptr;
405     if (OpLLT.isPointer())
406       OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace());
407     else
408       OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits());
409     Args.push_back({Reg, OpTy});
410   }
411 
412   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
413   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
414   Intrinsic::ID ID = MI.getOperand(0).getIntrinsicID();
415   RTLIB::Libcall RTLibcall;
416   switch (ID) {
417   case Intrinsic::memcpy:
418     RTLibcall = RTLIB::MEMCPY;
419     break;
420   case Intrinsic::memset:
421     RTLibcall = RTLIB::MEMSET;
422     break;
423   case Intrinsic::memmove:
424     RTLibcall = RTLIB::MEMMOVE;
425     break;
426   default:
427     return LegalizerHelper::UnableToLegalize;
428   }
429   const char *Name = TLI.getLibcallName(RTLibcall);
430 
431   MIRBuilder.setInstr(MI);
432 
433   CallLowering::CallLoweringInfo Info;
434   Info.CallConv = TLI.getLibcallCallingConv(RTLibcall);
435   Info.Callee = MachineOperand::CreateES(Name);
436   Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx));
437   Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() == 1 &&
438                     isLibCallInTailPosition(MI);
439 
440   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
441   if (!CLI.lowerCall(MIRBuilder, Info))
442     return LegalizerHelper::UnableToLegalize;
443 
444   if (Info.LoweredTailCall) {
445     assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?");
446     // We must have a return following the call to get past
447     // isLibCallInTailPosition.
448     assert(MI.getNextNode() && MI.getNextNode()->isReturn() &&
449            "Expected instr following MI to be a return?");
450 
451     // We lowered a tail call, so the call is now the return from the block.
452     // Delete the old return.
453     MI.getNextNode()->eraseFromParent();
454   }
455 
456   return LegalizerHelper::Legalized;
457 }
458 
459 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
460                                        Type *FromType) {
461   auto ToMVT = MVT::getVT(ToType);
462   auto FromMVT = MVT::getVT(FromType);
463 
464   switch (Opcode) {
465   case TargetOpcode::G_FPEXT:
466     return RTLIB::getFPEXT(FromMVT, ToMVT);
467   case TargetOpcode::G_FPTRUNC:
468     return RTLIB::getFPROUND(FromMVT, ToMVT);
469   case TargetOpcode::G_FPTOSI:
470     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
471   case TargetOpcode::G_FPTOUI:
472     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
473   case TargetOpcode::G_SITOFP:
474     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
475   case TargetOpcode::G_UITOFP:
476     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
477   }
478   llvm_unreachable("Unsupported libcall function");
479 }
480 
481 static LegalizerHelper::LegalizeResult
482 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
483                   Type *FromType) {
484   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
485   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
486                        {{MI.getOperand(1).getReg(), FromType}});
487 }
488 
489 LegalizerHelper::LegalizeResult
490 LegalizerHelper::libcall(MachineInstr &MI) {
491   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
492   unsigned Size = LLTy.getSizeInBits();
493   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
494 
495   MIRBuilder.setInstr(MI);
496 
497   switch (MI.getOpcode()) {
498   default:
499     return UnableToLegalize;
500   case TargetOpcode::G_SDIV:
501   case TargetOpcode::G_UDIV:
502   case TargetOpcode::G_SREM:
503   case TargetOpcode::G_UREM:
504   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
505     Type *HLTy = IntegerType::get(Ctx, Size);
506     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
507     if (Status != Legalized)
508       return Status;
509     break;
510   }
511   case TargetOpcode::G_FADD:
512   case TargetOpcode::G_FSUB:
513   case TargetOpcode::G_FMUL:
514   case TargetOpcode::G_FDIV:
515   case TargetOpcode::G_FMA:
516   case TargetOpcode::G_FPOW:
517   case TargetOpcode::G_FREM:
518   case TargetOpcode::G_FCOS:
519   case TargetOpcode::G_FSIN:
520   case TargetOpcode::G_FLOG10:
521   case TargetOpcode::G_FLOG:
522   case TargetOpcode::G_FLOG2:
523   case TargetOpcode::G_FEXP:
524   case TargetOpcode::G_FEXP2:
525   case TargetOpcode::G_FCEIL:
526   case TargetOpcode::G_FFLOOR: {
527     if (Size > 64) {
528       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
529       return UnableToLegalize;
530     }
531     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
532     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
533     if (Status != Legalized)
534       return Status;
535     break;
536   }
537   case TargetOpcode::G_FPEXT: {
538     // FIXME: Support other floating point types (half, fp128 etc)
539     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
540     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
541     if (ToSize != 64 || FromSize != 32)
542       return UnableToLegalize;
543     LegalizeResult Status = conversionLibcall(
544         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
545     if (Status != Legalized)
546       return Status;
547     break;
548   }
549   case TargetOpcode::G_FPTRUNC: {
550     // FIXME: Support other floating point types (half, fp128 etc)
551     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
552     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
553     if (ToSize != 32 || FromSize != 64)
554       return UnableToLegalize;
555     LegalizeResult Status = conversionLibcall(
556         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
557     if (Status != Legalized)
558       return Status;
559     break;
560   }
561   case TargetOpcode::G_FPTOSI:
562   case TargetOpcode::G_FPTOUI: {
563     // FIXME: Support other types
564     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
565     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
566     if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
567       return UnableToLegalize;
568     LegalizeResult Status = conversionLibcall(
569         MI, MIRBuilder,
570         ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
571         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
572     if (Status != Legalized)
573       return Status;
574     break;
575   }
576   case TargetOpcode::G_SITOFP:
577   case TargetOpcode::G_UITOFP: {
578     // FIXME: Support other types
579     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
580     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
581     if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
582       return UnableToLegalize;
583     LegalizeResult Status = conversionLibcall(
584         MI, MIRBuilder,
585         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
586         FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
587     if (Status != Legalized)
588       return Status;
589     break;
590   }
591   }
592 
593   MI.eraseFromParent();
594   return Legalized;
595 }
596 
597 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
598                                                               unsigned TypeIdx,
599                                                               LLT NarrowTy) {
600   MIRBuilder.setInstr(MI);
601 
602   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
603   uint64_t NarrowSize = NarrowTy.getSizeInBits();
604 
605   switch (MI.getOpcode()) {
606   default:
607     return UnableToLegalize;
608   case TargetOpcode::G_IMPLICIT_DEF: {
609     // FIXME: add support for when SizeOp0 isn't an exact multiple of
610     // NarrowSize.
611     if (SizeOp0 % NarrowSize != 0)
612       return UnableToLegalize;
613     int NumParts = SizeOp0 / NarrowSize;
614 
615     SmallVector<Register, 2> DstRegs;
616     for (int i = 0; i < NumParts; ++i)
617       DstRegs.push_back(
618           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
619 
620     Register DstReg = MI.getOperand(0).getReg();
621     if(MRI.getType(DstReg).isVector())
622       MIRBuilder.buildBuildVector(DstReg, DstRegs);
623     else
624       MIRBuilder.buildMerge(DstReg, DstRegs);
625     MI.eraseFromParent();
626     return Legalized;
627   }
628   case TargetOpcode::G_CONSTANT: {
629     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
630     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
631     unsigned TotalSize = Ty.getSizeInBits();
632     unsigned NarrowSize = NarrowTy.getSizeInBits();
633     int NumParts = TotalSize / NarrowSize;
634 
635     SmallVector<Register, 4> PartRegs;
636     for (int I = 0; I != NumParts; ++I) {
637       unsigned Offset = I * NarrowSize;
638       auto K = MIRBuilder.buildConstant(NarrowTy,
639                                         Val.lshr(Offset).trunc(NarrowSize));
640       PartRegs.push_back(K.getReg(0));
641     }
642 
643     LLT LeftoverTy;
644     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
645     SmallVector<Register, 1> LeftoverRegs;
646     if (LeftoverBits != 0) {
647       LeftoverTy = LLT::scalar(LeftoverBits);
648       auto K = MIRBuilder.buildConstant(
649         LeftoverTy,
650         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
651       LeftoverRegs.push_back(K.getReg(0));
652     }
653 
654     insertParts(MI.getOperand(0).getReg(),
655                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
656 
657     MI.eraseFromParent();
658     return Legalized;
659   }
660   case TargetOpcode::G_SEXT: {
661     if (TypeIdx != 0)
662       return UnableToLegalize;
663 
664     Register SrcReg = MI.getOperand(1).getReg();
665     LLT SrcTy = MRI.getType(SrcReg);
666 
667     // FIXME: support the general case where the requested NarrowTy may not be
668     // the same as the source type. E.g. s128 = sext(s32)
669     if ((SrcTy.getSizeInBits() != SizeOp0 / 2) ||
670         SrcTy.getSizeInBits() != NarrowTy.getSizeInBits()) {
671       LLVM_DEBUG(dbgs() << "Can't narrow sext to type " << NarrowTy << "\n");
672       return UnableToLegalize;
673     }
674 
675     // Shift the sign bit of the low register through the high register.
676     auto ShiftAmt =
677         MIRBuilder.buildConstant(LLT::scalar(64), NarrowTy.getSizeInBits() - 1);
678     auto Shift = MIRBuilder.buildAShr(NarrowTy, SrcReg, ShiftAmt);
679     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)});
680     MI.eraseFromParent();
681     return Legalized;
682   }
683   case TargetOpcode::G_ZEXT: {
684     if (TypeIdx != 0)
685       return UnableToLegalize;
686 
687     LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
688     uint64_t SizeOp1 = SrcTy.getSizeInBits();
689     if (SizeOp0 % SizeOp1 != 0)
690       return UnableToLegalize;
691 
692     // Generate a merge where the bottom bits are taken from the source, and
693     // zero everything else.
694     Register ZeroReg = MIRBuilder.buildConstant(SrcTy, 0).getReg(0);
695     unsigned NumParts = SizeOp0 / SizeOp1;
696     SmallVector<Register, 4> Srcs = {MI.getOperand(1).getReg()};
697     for (unsigned Part = 1; Part < NumParts; ++Part)
698       Srcs.push_back(ZeroReg);
699     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs);
700     MI.eraseFromParent();
701     return Legalized;
702   }
703   case TargetOpcode::G_TRUNC: {
704     if (TypeIdx != 1)
705       return UnableToLegalize;
706 
707     uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
708     if (NarrowTy.getSizeInBits() * 2 != SizeOp1) {
709       LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n");
710       return UnableToLegalize;
711     }
712 
713     auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg());
714     MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0));
715     MI.eraseFromParent();
716     return Legalized;
717   }
718 
719   case TargetOpcode::G_ADD: {
720     // FIXME: add support for when SizeOp0 isn't an exact multiple of
721     // NarrowSize.
722     if (SizeOp0 % NarrowSize != 0)
723       return UnableToLegalize;
724     // Expand in terms of carry-setting/consuming G_ADDE instructions.
725     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
726 
727     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
728     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
729     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
730 
731     Register CarryIn;
732     for (int i = 0; i < NumParts; ++i) {
733       Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
734       Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
735 
736       if (i == 0)
737         MIRBuilder.buildUAddo(DstReg, CarryOut, Src1Regs[i], Src2Regs[i]);
738       else {
739         MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
740                               Src2Regs[i], CarryIn);
741       }
742 
743       DstRegs.push_back(DstReg);
744       CarryIn = CarryOut;
745     }
746     Register DstReg = MI.getOperand(0).getReg();
747     if(MRI.getType(DstReg).isVector())
748       MIRBuilder.buildBuildVector(DstReg, DstRegs);
749     else
750       MIRBuilder.buildMerge(DstReg, DstRegs);
751     MI.eraseFromParent();
752     return Legalized;
753   }
754   case TargetOpcode::G_SUB: {
755     // FIXME: add support for when SizeOp0 isn't an exact multiple of
756     // NarrowSize.
757     if (SizeOp0 % NarrowSize != 0)
758       return UnableToLegalize;
759 
760     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
761 
762     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
763     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
764     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
765 
766     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
767     Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
768     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
769                           {Src1Regs[0], Src2Regs[0]});
770     DstRegs.push_back(DstReg);
771     Register BorrowIn = BorrowOut;
772     for (int i = 1; i < NumParts; ++i) {
773       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
774       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
775 
776       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
777                             {Src1Regs[i], Src2Regs[i], BorrowIn});
778 
779       DstRegs.push_back(DstReg);
780       BorrowIn = BorrowOut;
781     }
782     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
783     MI.eraseFromParent();
784     return Legalized;
785   }
786   case TargetOpcode::G_MUL:
787   case TargetOpcode::G_UMULH:
788     return narrowScalarMul(MI, NarrowTy);
789   case TargetOpcode::G_EXTRACT:
790     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
791   case TargetOpcode::G_INSERT:
792     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
793   case TargetOpcode::G_LOAD: {
794     const auto &MMO = **MI.memoperands_begin();
795     Register DstReg = MI.getOperand(0).getReg();
796     LLT DstTy = MRI.getType(DstReg);
797     if (DstTy.isVector())
798       return UnableToLegalize;
799 
800     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
801       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
802       auto &MMO = **MI.memoperands_begin();
803       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
804       MIRBuilder.buildAnyExt(DstReg, TmpReg);
805       MI.eraseFromParent();
806       return Legalized;
807     }
808 
809     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
810   }
811   case TargetOpcode::G_ZEXTLOAD:
812   case TargetOpcode::G_SEXTLOAD: {
813     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
814     Register DstReg = MI.getOperand(0).getReg();
815     Register PtrReg = MI.getOperand(1).getReg();
816 
817     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
818     auto &MMO = **MI.memoperands_begin();
819     if (MMO.getSizeInBits() == NarrowSize) {
820       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
821     } else {
822       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
823         : TargetOpcode::G_SEXTLOAD;
824       MIRBuilder.buildInstr(ExtLoad)
825         .addDef(TmpReg)
826         .addUse(PtrReg)
827         .addMemOperand(&MMO);
828     }
829 
830     if (ZExt)
831       MIRBuilder.buildZExt(DstReg, TmpReg);
832     else
833       MIRBuilder.buildSExt(DstReg, TmpReg);
834 
835     MI.eraseFromParent();
836     return Legalized;
837   }
838   case TargetOpcode::G_STORE: {
839     const auto &MMO = **MI.memoperands_begin();
840 
841     Register SrcReg = MI.getOperand(0).getReg();
842     LLT SrcTy = MRI.getType(SrcReg);
843     if (SrcTy.isVector())
844       return UnableToLegalize;
845 
846     int NumParts = SizeOp0 / NarrowSize;
847     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
848     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
849     if (SrcTy.isVector() && LeftoverBits != 0)
850       return UnableToLegalize;
851 
852     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
853       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
854       auto &MMO = **MI.memoperands_begin();
855       MIRBuilder.buildTrunc(TmpReg, SrcReg);
856       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
857       MI.eraseFromParent();
858       return Legalized;
859     }
860 
861     return reduceLoadStoreWidth(MI, 0, NarrowTy);
862   }
863   case TargetOpcode::G_SELECT:
864     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
865   case TargetOpcode::G_AND:
866   case TargetOpcode::G_OR:
867   case TargetOpcode::G_XOR: {
868     // Legalize bitwise operation:
869     // A = BinOp<Ty> B, C
870     // into:
871     // B1, ..., BN = G_UNMERGE_VALUES B
872     // C1, ..., CN = G_UNMERGE_VALUES C
873     // A1 = BinOp<Ty/N> B1, C2
874     // ...
875     // AN = BinOp<Ty/N> BN, CN
876     // A = G_MERGE_VALUES A1, ..., AN
877     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
878   }
879   case TargetOpcode::G_SHL:
880   case TargetOpcode::G_LSHR:
881   case TargetOpcode::G_ASHR:
882     return narrowScalarShift(MI, TypeIdx, NarrowTy);
883   case TargetOpcode::G_CTLZ:
884   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
885   case TargetOpcode::G_CTTZ:
886   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
887   case TargetOpcode::G_CTPOP:
888     if (TypeIdx != 0)
889       return UnableToLegalize; // TODO
890 
891     Observer.changingInstr(MI);
892     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
893     Observer.changedInstr(MI);
894     return Legalized;
895   case TargetOpcode::G_INTTOPTR:
896     if (TypeIdx != 1)
897       return UnableToLegalize;
898 
899     Observer.changingInstr(MI);
900     narrowScalarSrc(MI, NarrowTy, 1);
901     Observer.changedInstr(MI);
902     return Legalized;
903   case TargetOpcode::G_PTRTOINT:
904     if (TypeIdx != 0)
905       return UnableToLegalize;
906 
907     Observer.changingInstr(MI);
908     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
909     Observer.changedInstr(MI);
910     return Legalized;
911   case TargetOpcode::G_PHI: {
912     unsigned NumParts = SizeOp0 / NarrowSize;
913     SmallVector<Register, 2> DstRegs;
914     SmallVector<SmallVector<Register, 2>, 2> SrcRegs;
915     DstRegs.resize(NumParts);
916     SrcRegs.resize(MI.getNumOperands() / 2);
917     Observer.changingInstr(MI);
918     for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
919       MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
920       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
921       extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
922                    SrcRegs[i / 2]);
923     }
924     MachineBasicBlock &MBB = *MI.getParent();
925     MIRBuilder.setInsertPt(MBB, MI);
926     for (unsigned i = 0; i < NumParts; ++i) {
927       DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
928       MachineInstrBuilder MIB =
929           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
930       for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
931         MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
932     }
933     MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
934     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
935     Observer.changedInstr(MI);
936     MI.eraseFromParent();
937     return Legalized;
938   }
939   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
940   case TargetOpcode::G_INSERT_VECTOR_ELT: {
941     if (TypeIdx != 2)
942       return UnableToLegalize;
943 
944     int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
945     Observer.changingInstr(MI);
946     narrowScalarSrc(MI, NarrowTy, OpIdx);
947     Observer.changedInstr(MI);
948     return Legalized;
949   }
950   case TargetOpcode::G_ICMP: {
951     uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
952     if (NarrowSize * 2 != SrcSize)
953       return UnableToLegalize;
954 
955     Observer.changingInstr(MI);
956     Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
957     Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
958     MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg());
959 
960     Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
961     Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
962     MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg());
963 
964     CmpInst::Predicate Pred =
965         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
966     LLT ResTy = MRI.getType(MI.getOperand(0).getReg());
967 
968     if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) {
969       MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
970       MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
971       MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
972       MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
973       MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero);
974     } else {
975       MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
976       MachineInstrBuilder CmpHEQ =
977           MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
978       MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
979           ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
980       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH);
981     }
982     Observer.changedInstr(MI);
983     MI.eraseFromParent();
984     return Legalized;
985   }
986   case TargetOpcode::G_SEXT_INREG: {
987     if (TypeIdx != 0)
988       return UnableToLegalize;
989 
990     if (!MI.getOperand(2).isImm())
991       return UnableToLegalize;
992     int64_t SizeInBits = MI.getOperand(2).getImm();
993 
994     // So long as the new type has more bits than the bits we're extending we
995     // don't need to break it apart.
996     if (NarrowTy.getScalarSizeInBits() >= SizeInBits) {
997       Observer.changingInstr(MI);
998       // We don't lose any non-extension bits by truncating the src and
999       // sign-extending the dst.
1000       MachineOperand &MO1 = MI.getOperand(1);
1001       auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1.getReg());
1002       MO1.setReg(TruncMIB->getOperand(0).getReg());
1003 
1004       MachineOperand &MO2 = MI.getOperand(0);
1005       Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
1006       MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1007       MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt});
1008       MO2.setReg(DstExt);
1009       Observer.changedInstr(MI);
1010       return Legalized;
1011     }
1012 
1013     // Break it apart. Components below the extension point are unmodified. The
1014     // component containing the extension point becomes a narrower SEXT_INREG.
1015     // Components above it are ashr'd from the component containing the
1016     // extension point.
1017     if (SizeOp0 % NarrowSize != 0)
1018       return UnableToLegalize;
1019     int NumParts = SizeOp0 / NarrowSize;
1020 
1021     // List the registers where the destination will be scattered.
1022     SmallVector<Register, 2> DstRegs;
1023     // List the registers where the source will be split.
1024     SmallVector<Register, 2> SrcRegs;
1025 
1026     // Create all the temporary registers.
1027     for (int i = 0; i < NumParts; ++i) {
1028       Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy);
1029 
1030       SrcRegs.push_back(SrcReg);
1031     }
1032 
1033     // Explode the big arguments into smaller chunks.
1034     MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg());
1035 
1036     Register AshrCstReg =
1037         MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
1038             ->getOperand(0)
1039             .getReg();
1040     Register FullExtensionReg = 0;
1041     Register PartialExtensionReg = 0;
1042 
1043     // Do the operation on each small part.
1044     for (int i = 0; i < NumParts; ++i) {
1045       if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits)
1046         DstRegs.push_back(SrcRegs[i]);
1047       else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) {
1048         assert(PartialExtensionReg &&
1049                "Expected to visit partial extension before full");
1050         if (FullExtensionReg) {
1051           DstRegs.push_back(FullExtensionReg);
1052           continue;
1053         }
1054         DstRegs.push_back(MIRBuilder
1055                               .buildInstr(TargetOpcode::G_ASHR, {NarrowTy},
1056                                           {PartialExtensionReg, AshrCstReg})
1057                               ->getOperand(0)
1058                               .getReg());
1059         FullExtensionReg = DstRegs.back();
1060       } else {
1061         DstRegs.push_back(
1062             MIRBuilder
1063                 .buildInstr(
1064                     TargetOpcode::G_SEXT_INREG, {NarrowTy},
1065                     {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
1066                 ->getOperand(0)
1067                 .getReg());
1068         PartialExtensionReg = DstRegs.back();
1069       }
1070     }
1071 
1072     // Gather the destination registers into the final destination.
1073     Register DstReg = MI.getOperand(0).getReg();
1074     MIRBuilder.buildMerge(DstReg, DstRegs);
1075     MI.eraseFromParent();
1076     return Legalized;
1077   }
1078   case TargetOpcode::G_BSWAP:
1079   case TargetOpcode::G_BITREVERSE: {
1080     if (SizeOp0 % NarrowSize != 0)
1081       return UnableToLegalize;
1082 
1083     Observer.changingInstr(MI);
1084     SmallVector<Register, 2> SrcRegs, DstRegs;
1085     unsigned NumParts = SizeOp0 / NarrowSize;
1086     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
1087 
1088     for (unsigned i = 0; i < NumParts; ++i) {
1089       auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
1090                                            {SrcRegs[NumParts - 1 - i]});
1091       DstRegs.push_back(DstPart.getReg(0));
1092     }
1093 
1094     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
1095 
1096     Observer.changedInstr(MI);
1097     MI.eraseFromParent();
1098     return Legalized;
1099   }
1100   }
1101 }
1102 
1103 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
1104                                      unsigned OpIdx, unsigned ExtOpcode) {
1105   MachineOperand &MO = MI.getOperand(OpIdx);
1106   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
1107   MO.setReg(ExtB->getOperand(0).getReg());
1108 }
1109 
1110 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
1111                                       unsigned OpIdx) {
1112   MachineOperand &MO = MI.getOperand(OpIdx);
1113   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
1114                                     {MO.getReg()});
1115   MO.setReg(ExtB->getOperand(0).getReg());
1116 }
1117 
1118 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
1119                                      unsigned OpIdx, unsigned TruncOpcode) {
1120   MachineOperand &MO = MI.getOperand(OpIdx);
1121   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1122   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1123   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
1124   MO.setReg(DstExt);
1125 }
1126 
1127 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
1128                                       unsigned OpIdx, unsigned ExtOpcode) {
1129   MachineOperand &MO = MI.getOperand(OpIdx);
1130   Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
1131   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1132   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
1133   MO.setReg(DstTrunc);
1134 }
1135 
1136 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
1137                                             unsigned OpIdx) {
1138   MachineOperand &MO = MI.getOperand(OpIdx);
1139   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1140   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1141   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
1142   MO.setReg(DstExt);
1143 }
1144 
1145 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
1146                                             unsigned OpIdx) {
1147   MachineOperand &MO = MI.getOperand(OpIdx);
1148 
1149   LLT OldTy = MRI.getType(MO.getReg());
1150   unsigned OldElts = OldTy.getNumElements();
1151   unsigned NewElts = MoreTy.getNumElements();
1152 
1153   unsigned NumParts = NewElts / OldElts;
1154 
1155   // Use concat_vectors if the result is a multiple of the number of elements.
1156   if (NumParts * OldElts == NewElts) {
1157     SmallVector<Register, 8> Parts;
1158     Parts.push_back(MO.getReg());
1159 
1160     Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
1161     for (unsigned I = 1; I != NumParts; ++I)
1162       Parts.push_back(ImpDef);
1163 
1164     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
1165     MO.setReg(Concat.getReg(0));
1166     return;
1167   }
1168 
1169   Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
1170   Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
1171   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
1172   MO.setReg(MoreReg);
1173 }
1174 
1175 LegalizerHelper::LegalizeResult
1176 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
1177                                         LLT WideTy) {
1178   if (TypeIdx != 1)
1179     return UnableToLegalize;
1180 
1181   Register DstReg = MI.getOperand(0).getReg();
1182   LLT DstTy = MRI.getType(DstReg);
1183   if (DstTy.isVector())
1184     return UnableToLegalize;
1185 
1186   Register Src1 = MI.getOperand(1).getReg();
1187   LLT SrcTy = MRI.getType(Src1);
1188   const int DstSize = DstTy.getSizeInBits();
1189   const int SrcSize = SrcTy.getSizeInBits();
1190   const int WideSize = WideTy.getSizeInBits();
1191   const int NumMerge = (DstSize + WideSize - 1) / WideSize;
1192 
1193   unsigned NumOps = MI.getNumOperands();
1194   unsigned NumSrc = MI.getNumOperands() - 1;
1195   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
1196 
1197   if (WideSize >= DstSize) {
1198     // Directly pack the bits in the target type.
1199     Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1200 
1201     for (unsigned I = 2; I != NumOps; ++I) {
1202       const unsigned Offset = (I - 1) * PartSize;
1203 
1204       Register SrcReg = MI.getOperand(I).getReg();
1205       assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
1206 
1207       auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
1208 
1209       Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
1210         MRI.createGenericVirtualRegister(WideTy);
1211 
1212       auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
1213       auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
1214       MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1215       ResultReg = NextResult;
1216     }
1217 
1218     if (WideSize > DstSize)
1219       MIRBuilder.buildTrunc(DstReg, ResultReg);
1220     else if (DstTy.isPointer())
1221       MIRBuilder.buildIntToPtr(DstReg, ResultReg);
1222 
1223     MI.eraseFromParent();
1224     return Legalized;
1225   }
1226 
1227   // Unmerge the original values to the GCD type, and recombine to the next
1228   // multiple greater than the original type.
1229   //
1230   // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6
1231   // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0
1232   // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1
1233   // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2
1234   // %10:_(s6) = G_MERGE_VALUES %4, %5, %6
1235   // %11:_(s6) = G_MERGE_VALUES %7, %8, %9
1236   // %12:_(s12) = G_MERGE_VALUES %10, %11
1237   //
1238   // Padding with undef if necessary:
1239   //
1240   // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6
1241   // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0
1242   // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1
1243   // %7:_(s2) = G_IMPLICIT_DEF
1244   // %8:_(s6) = G_MERGE_VALUES %3, %4, %5
1245   // %9:_(s6) = G_MERGE_VALUES %6, %7, %7
1246   // %10:_(s12) = G_MERGE_VALUES %8, %9
1247 
1248   const int GCD = greatestCommonDivisor(SrcSize, WideSize);
1249   LLT GCDTy = LLT::scalar(GCD);
1250 
1251   SmallVector<Register, 8> Parts;
1252   SmallVector<Register, 8> NewMergeRegs;
1253   SmallVector<Register, 8> Unmerges;
1254   LLT WideDstTy = LLT::scalar(NumMerge * WideSize);
1255 
1256   // Decompose the original operands if they don't evenly divide.
1257   for (int I = 1, E = MI.getNumOperands(); I != E; ++I) {
1258     Register SrcReg = MI.getOperand(I).getReg();
1259     if (GCD == SrcSize) {
1260       Unmerges.push_back(SrcReg);
1261     } else {
1262       auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
1263       for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J)
1264         Unmerges.push_back(Unmerge.getReg(J));
1265     }
1266   }
1267 
1268   // Pad with undef to the next size that is a multiple of the requested size.
1269   if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) {
1270     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1271     for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I)
1272       Unmerges.push_back(UndefReg);
1273   }
1274 
1275   const int PartsPerGCD = WideSize / GCD;
1276 
1277   // Build merges of each piece.
1278   ArrayRef<Register> Slicer(Unmerges);
1279   for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) {
1280     auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
1281     NewMergeRegs.push_back(Merge.getReg(0));
1282   }
1283 
1284   // A truncate may be necessary if the requested type doesn't evenly divide the
1285   // original result type.
1286   if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
1287     MIRBuilder.buildMerge(DstReg, NewMergeRegs);
1288   } else {
1289     auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
1290     MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
1291   }
1292 
1293   MI.eraseFromParent();
1294   return Legalized;
1295 }
1296 
1297 LegalizerHelper::LegalizeResult
1298 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
1299                                           LLT WideTy) {
1300   if (TypeIdx != 0)
1301     return UnableToLegalize;
1302 
1303   unsigned NumDst = MI.getNumOperands() - 1;
1304   Register SrcReg = MI.getOperand(NumDst).getReg();
1305   LLT SrcTy = MRI.getType(SrcReg);
1306   if (!SrcTy.isScalar())
1307     return UnableToLegalize;
1308 
1309   Register Dst0Reg = MI.getOperand(0).getReg();
1310   LLT DstTy = MRI.getType(Dst0Reg);
1311   if (!DstTy.isScalar())
1312     return UnableToLegalize;
1313 
1314   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
1315   LLT NewSrcTy = LLT::scalar(NewSrcSize);
1316   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
1317 
1318   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
1319 
1320   for (unsigned I = 1; I != NumDst; ++I) {
1321     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
1322     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
1323     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
1324   }
1325 
1326   Observer.changingInstr(MI);
1327 
1328   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
1329   for (unsigned I = 0; I != NumDst; ++I)
1330     widenScalarDst(MI, WideTy, I);
1331 
1332   Observer.changedInstr(MI);
1333 
1334   return Legalized;
1335 }
1336 
1337 LegalizerHelper::LegalizeResult
1338 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
1339                                     LLT WideTy) {
1340   Register DstReg = MI.getOperand(0).getReg();
1341   Register SrcReg = MI.getOperand(1).getReg();
1342   LLT SrcTy = MRI.getType(SrcReg);
1343 
1344   LLT DstTy = MRI.getType(DstReg);
1345   unsigned Offset = MI.getOperand(2).getImm();
1346 
1347   if (TypeIdx == 0) {
1348     if (SrcTy.isVector() || DstTy.isVector())
1349       return UnableToLegalize;
1350 
1351     SrcOp Src(SrcReg);
1352     if (SrcTy.isPointer()) {
1353       // Extracts from pointers can be handled only if they are really just
1354       // simple integers.
1355       const DataLayout &DL = MIRBuilder.getDataLayout();
1356       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
1357         return UnableToLegalize;
1358 
1359       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
1360       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
1361       SrcTy = SrcAsIntTy;
1362     }
1363 
1364     if (DstTy.isPointer())
1365       return UnableToLegalize;
1366 
1367     if (Offset == 0) {
1368       // Avoid a shift in the degenerate case.
1369       MIRBuilder.buildTrunc(DstReg,
1370                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
1371       MI.eraseFromParent();
1372       return Legalized;
1373     }
1374 
1375     // Do a shift in the source type.
1376     LLT ShiftTy = SrcTy;
1377     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1378       Src = MIRBuilder.buildAnyExt(WideTy, Src);
1379       ShiftTy = WideTy;
1380     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
1381       return UnableToLegalize;
1382 
1383     auto LShr = MIRBuilder.buildLShr(
1384       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
1385     MIRBuilder.buildTrunc(DstReg, LShr);
1386     MI.eraseFromParent();
1387     return Legalized;
1388   }
1389 
1390   if (SrcTy.isScalar()) {
1391     Observer.changingInstr(MI);
1392     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1393     Observer.changedInstr(MI);
1394     return Legalized;
1395   }
1396 
1397   if (!SrcTy.isVector())
1398     return UnableToLegalize;
1399 
1400   if (DstTy != SrcTy.getElementType())
1401     return UnableToLegalize;
1402 
1403   if (Offset % SrcTy.getScalarSizeInBits() != 0)
1404     return UnableToLegalize;
1405 
1406   Observer.changingInstr(MI);
1407   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1408 
1409   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
1410                           Offset);
1411   widenScalarDst(MI, WideTy.getScalarType(), 0);
1412   Observer.changedInstr(MI);
1413   return Legalized;
1414 }
1415 
1416 LegalizerHelper::LegalizeResult
1417 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
1418                                    LLT WideTy) {
1419   if (TypeIdx != 0)
1420     return UnableToLegalize;
1421   Observer.changingInstr(MI);
1422   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1423   widenScalarDst(MI, WideTy);
1424   Observer.changedInstr(MI);
1425   return Legalized;
1426 }
1427 
1428 LegalizerHelper::LegalizeResult
1429 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
1430   MIRBuilder.setInstr(MI);
1431 
1432   switch (MI.getOpcode()) {
1433   default:
1434     return UnableToLegalize;
1435   case TargetOpcode::G_EXTRACT:
1436     return widenScalarExtract(MI, TypeIdx, WideTy);
1437   case TargetOpcode::G_INSERT:
1438     return widenScalarInsert(MI, TypeIdx, WideTy);
1439   case TargetOpcode::G_MERGE_VALUES:
1440     return widenScalarMergeValues(MI, TypeIdx, WideTy);
1441   case TargetOpcode::G_UNMERGE_VALUES:
1442     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
1443   case TargetOpcode::G_UADDO:
1444   case TargetOpcode::G_USUBO: {
1445     if (TypeIdx == 1)
1446       return UnableToLegalize; // TODO
1447     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1448                                          {MI.getOperand(2).getReg()});
1449     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1450                                          {MI.getOperand(3).getReg()});
1451     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1452                           ? TargetOpcode::G_ADD
1453                           : TargetOpcode::G_SUB;
1454     // Do the arithmetic in the larger type.
1455     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1456     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1457     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
1458     auto AndOp = MIRBuilder.buildInstr(
1459         TargetOpcode::G_AND, {WideTy},
1460         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
1461     // There is no overflow if the AndOp is the same as NewOp.
1462     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
1463                          AndOp);
1464     // Now trunc the NewOp to the original result.
1465     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
1466     MI.eraseFromParent();
1467     return Legalized;
1468   }
1469   case TargetOpcode::G_CTTZ:
1470   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1471   case TargetOpcode::G_CTLZ:
1472   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1473   case TargetOpcode::G_CTPOP: {
1474     if (TypeIdx == 0) {
1475       Observer.changingInstr(MI);
1476       widenScalarDst(MI, WideTy, 0);
1477       Observer.changedInstr(MI);
1478       return Legalized;
1479     }
1480 
1481     Register SrcReg = MI.getOperand(1).getReg();
1482 
1483     // First ZEXT the input.
1484     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1485     LLT CurTy = MRI.getType(SrcReg);
1486     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1487       // The count is the same in the larger type except if the original
1488       // value was zero.  This can be handled by setting the bit just off
1489       // the top of the original type.
1490       auto TopBit =
1491           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1492       MIBSrc = MIRBuilder.buildOr(
1493         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1494     }
1495 
1496     // Perform the operation at the larger size.
1497     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1498     // This is already the correct result for CTPOP and CTTZs
1499     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1500         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1501       // The correct result is NewOp - (Difference in widety and current ty).
1502       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1503       MIBNewOp = MIRBuilder.buildInstr(
1504           TargetOpcode::G_SUB, {WideTy},
1505           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1506     }
1507 
1508     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1509     MI.eraseFromParent();
1510     return Legalized;
1511   }
1512   case TargetOpcode::G_BSWAP: {
1513     Observer.changingInstr(MI);
1514     Register DstReg = MI.getOperand(0).getReg();
1515 
1516     Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1517     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1518     Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1519     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1520 
1521     MI.getOperand(0).setReg(DstExt);
1522 
1523     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1524 
1525     LLT Ty = MRI.getType(DstReg);
1526     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1527     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1528     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1529       .addDef(ShrReg)
1530       .addUse(DstExt)
1531       .addUse(ShiftAmtReg);
1532 
1533     MIRBuilder.buildTrunc(DstReg, ShrReg);
1534     Observer.changedInstr(MI);
1535     return Legalized;
1536   }
1537   case TargetOpcode::G_BITREVERSE: {
1538     Observer.changingInstr(MI);
1539 
1540     Register DstReg = MI.getOperand(0).getReg();
1541     LLT Ty = MRI.getType(DstReg);
1542     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1543 
1544     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1545     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1546     MI.getOperand(0).setReg(DstExt);
1547     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1548 
1549     auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
1550     auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt);
1551     MIRBuilder.buildTrunc(DstReg, Shift);
1552     Observer.changedInstr(MI);
1553     return Legalized;
1554   }
1555   case TargetOpcode::G_ADD:
1556   case TargetOpcode::G_AND:
1557   case TargetOpcode::G_MUL:
1558   case TargetOpcode::G_OR:
1559   case TargetOpcode::G_XOR:
1560   case TargetOpcode::G_SUB:
1561     // Perform operation at larger width (any extension is fines here, high bits
1562     // don't affect the result) and then truncate the result back to the
1563     // original type.
1564     Observer.changingInstr(MI);
1565     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1566     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1567     widenScalarDst(MI, WideTy);
1568     Observer.changedInstr(MI);
1569     return Legalized;
1570 
1571   case TargetOpcode::G_SHL:
1572     Observer.changingInstr(MI);
1573 
1574     if (TypeIdx == 0) {
1575       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1576       widenScalarDst(MI, WideTy);
1577     } else {
1578       assert(TypeIdx == 1);
1579       // The "number of bits to shift" operand must preserve its value as an
1580       // unsigned integer:
1581       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1582     }
1583 
1584     Observer.changedInstr(MI);
1585     return Legalized;
1586 
1587   case TargetOpcode::G_SDIV:
1588   case TargetOpcode::G_SREM:
1589   case TargetOpcode::G_SMIN:
1590   case TargetOpcode::G_SMAX:
1591     Observer.changingInstr(MI);
1592     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1593     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1594     widenScalarDst(MI, WideTy);
1595     Observer.changedInstr(MI);
1596     return Legalized;
1597 
1598   case TargetOpcode::G_ASHR:
1599   case TargetOpcode::G_LSHR:
1600     Observer.changingInstr(MI);
1601 
1602     if (TypeIdx == 0) {
1603       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1604         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1605 
1606       widenScalarSrc(MI, WideTy, 1, CvtOp);
1607       widenScalarDst(MI, WideTy);
1608     } else {
1609       assert(TypeIdx == 1);
1610       // The "number of bits to shift" operand must preserve its value as an
1611       // unsigned integer:
1612       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1613     }
1614 
1615     Observer.changedInstr(MI);
1616     return Legalized;
1617   case TargetOpcode::G_UDIV:
1618   case TargetOpcode::G_UREM:
1619   case TargetOpcode::G_UMIN:
1620   case TargetOpcode::G_UMAX:
1621     Observer.changingInstr(MI);
1622     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1623     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1624     widenScalarDst(MI, WideTy);
1625     Observer.changedInstr(MI);
1626     return Legalized;
1627 
1628   case TargetOpcode::G_SELECT:
1629     Observer.changingInstr(MI);
1630     if (TypeIdx == 0) {
1631       // Perform operation at larger width (any extension is fine here, high
1632       // bits don't affect the result) and then truncate the result back to the
1633       // original type.
1634       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1635       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1636       widenScalarDst(MI, WideTy);
1637     } else {
1638       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1639       // Explicit extension is required here since high bits affect the result.
1640       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1641     }
1642     Observer.changedInstr(MI);
1643     return Legalized;
1644 
1645   case TargetOpcode::G_FPTOSI:
1646   case TargetOpcode::G_FPTOUI:
1647     Observer.changingInstr(MI);
1648 
1649     if (TypeIdx == 0)
1650       widenScalarDst(MI, WideTy);
1651     else
1652       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT);
1653 
1654     Observer.changedInstr(MI);
1655     return Legalized;
1656   case TargetOpcode::G_SITOFP:
1657     if (TypeIdx != 1)
1658       return UnableToLegalize;
1659     Observer.changingInstr(MI);
1660     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1661     Observer.changedInstr(MI);
1662     return Legalized;
1663 
1664   case TargetOpcode::G_UITOFP:
1665     if (TypeIdx != 1)
1666       return UnableToLegalize;
1667     Observer.changingInstr(MI);
1668     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1669     Observer.changedInstr(MI);
1670     return Legalized;
1671 
1672   case TargetOpcode::G_LOAD:
1673   case TargetOpcode::G_SEXTLOAD:
1674   case TargetOpcode::G_ZEXTLOAD:
1675     Observer.changingInstr(MI);
1676     widenScalarDst(MI, WideTy);
1677     Observer.changedInstr(MI);
1678     return Legalized;
1679 
1680   case TargetOpcode::G_STORE: {
1681     if (TypeIdx != 0)
1682       return UnableToLegalize;
1683 
1684     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1685     if (!isPowerOf2_32(Ty.getSizeInBits()))
1686       return UnableToLegalize;
1687 
1688     Observer.changingInstr(MI);
1689 
1690     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1691       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1692     widenScalarSrc(MI, WideTy, 0, ExtType);
1693 
1694     Observer.changedInstr(MI);
1695     return Legalized;
1696   }
1697   case TargetOpcode::G_CONSTANT: {
1698     MachineOperand &SrcMO = MI.getOperand(1);
1699     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1700     unsigned ExtOpc = LI.getExtOpcodeForWideningConstant(
1701         MRI.getType(MI.getOperand(0).getReg()));
1702     assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT ||
1703             ExtOpc == TargetOpcode::G_ANYEXT) &&
1704            "Illegal Extend");
1705     const APInt &SrcVal = SrcMO.getCImm()->getValue();
1706     const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT)
1707                            ? SrcVal.sext(WideTy.getSizeInBits())
1708                            : SrcVal.zext(WideTy.getSizeInBits());
1709     Observer.changingInstr(MI);
1710     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1711 
1712     widenScalarDst(MI, WideTy);
1713     Observer.changedInstr(MI);
1714     return Legalized;
1715   }
1716   case TargetOpcode::G_FCONSTANT: {
1717     MachineOperand &SrcMO = MI.getOperand(1);
1718     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1719     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1720     bool LosesInfo;
1721     switch (WideTy.getSizeInBits()) {
1722     case 32:
1723       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1724                   &LosesInfo);
1725       break;
1726     case 64:
1727       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1728                   &LosesInfo);
1729       break;
1730     default:
1731       return UnableToLegalize;
1732     }
1733 
1734     assert(!LosesInfo && "extend should always be lossless");
1735 
1736     Observer.changingInstr(MI);
1737     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1738 
1739     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1740     Observer.changedInstr(MI);
1741     return Legalized;
1742   }
1743   case TargetOpcode::G_IMPLICIT_DEF: {
1744     Observer.changingInstr(MI);
1745     widenScalarDst(MI, WideTy);
1746     Observer.changedInstr(MI);
1747     return Legalized;
1748   }
1749   case TargetOpcode::G_BRCOND:
1750     Observer.changingInstr(MI);
1751     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1752     Observer.changedInstr(MI);
1753     return Legalized;
1754 
1755   case TargetOpcode::G_FCMP:
1756     Observer.changingInstr(MI);
1757     if (TypeIdx == 0)
1758       widenScalarDst(MI, WideTy);
1759     else {
1760       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1761       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1762     }
1763     Observer.changedInstr(MI);
1764     return Legalized;
1765 
1766   case TargetOpcode::G_ICMP:
1767     Observer.changingInstr(MI);
1768     if (TypeIdx == 0)
1769       widenScalarDst(MI, WideTy);
1770     else {
1771       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1772                                MI.getOperand(1).getPredicate()))
1773                                ? TargetOpcode::G_SEXT
1774                                : TargetOpcode::G_ZEXT;
1775       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1776       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1777     }
1778     Observer.changedInstr(MI);
1779     return Legalized;
1780 
1781   case TargetOpcode::G_PTR_ADD:
1782     assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD");
1783     Observer.changingInstr(MI);
1784     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1785     Observer.changedInstr(MI);
1786     return Legalized;
1787 
1788   case TargetOpcode::G_PHI: {
1789     assert(TypeIdx == 0 && "Expecting only Idx 0");
1790 
1791     Observer.changingInstr(MI);
1792     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1793       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1794       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1795       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1796     }
1797 
1798     MachineBasicBlock &MBB = *MI.getParent();
1799     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1800     widenScalarDst(MI, WideTy);
1801     Observer.changedInstr(MI);
1802     return Legalized;
1803   }
1804   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1805     if (TypeIdx == 0) {
1806       Register VecReg = MI.getOperand(1).getReg();
1807       LLT VecTy = MRI.getType(VecReg);
1808       Observer.changingInstr(MI);
1809 
1810       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1811                                      WideTy.getSizeInBits()),
1812                      1, TargetOpcode::G_SEXT);
1813 
1814       widenScalarDst(MI, WideTy, 0);
1815       Observer.changedInstr(MI);
1816       return Legalized;
1817     }
1818 
1819     if (TypeIdx != 2)
1820       return UnableToLegalize;
1821     Observer.changingInstr(MI);
1822     // TODO: Probably should be zext
1823     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1824     Observer.changedInstr(MI);
1825     return Legalized;
1826   }
1827   case TargetOpcode::G_INSERT_VECTOR_ELT: {
1828     if (TypeIdx == 1) {
1829       Observer.changingInstr(MI);
1830 
1831       Register VecReg = MI.getOperand(1).getReg();
1832       LLT VecTy = MRI.getType(VecReg);
1833       LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy);
1834 
1835       widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT);
1836       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1837       widenScalarDst(MI, WideVecTy, 0);
1838       Observer.changedInstr(MI);
1839       return Legalized;
1840     }
1841 
1842     if (TypeIdx == 2) {
1843       Observer.changingInstr(MI);
1844       // TODO: Probably should be zext
1845       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT);
1846       Observer.changedInstr(MI);
1847     }
1848 
1849     return Legalized;
1850   }
1851   case TargetOpcode::G_FADD:
1852   case TargetOpcode::G_FMUL:
1853   case TargetOpcode::G_FSUB:
1854   case TargetOpcode::G_FMA:
1855   case TargetOpcode::G_FMAD:
1856   case TargetOpcode::G_FNEG:
1857   case TargetOpcode::G_FABS:
1858   case TargetOpcode::G_FCANONICALIZE:
1859   case TargetOpcode::G_FMINNUM:
1860   case TargetOpcode::G_FMAXNUM:
1861   case TargetOpcode::G_FMINNUM_IEEE:
1862   case TargetOpcode::G_FMAXNUM_IEEE:
1863   case TargetOpcode::G_FMINIMUM:
1864   case TargetOpcode::G_FMAXIMUM:
1865   case TargetOpcode::G_FDIV:
1866   case TargetOpcode::G_FREM:
1867   case TargetOpcode::G_FCEIL:
1868   case TargetOpcode::G_FFLOOR:
1869   case TargetOpcode::G_FCOS:
1870   case TargetOpcode::G_FSIN:
1871   case TargetOpcode::G_FLOG10:
1872   case TargetOpcode::G_FLOG:
1873   case TargetOpcode::G_FLOG2:
1874   case TargetOpcode::G_FRINT:
1875   case TargetOpcode::G_FNEARBYINT:
1876   case TargetOpcode::G_FSQRT:
1877   case TargetOpcode::G_FEXP:
1878   case TargetOpcode::G_FEXP2:
1879   case TargetOpcode::G_FPOW:
1880   case TargetOpcode::G_INTRINSIC_TRUNC:
1881   case TargetOpcode::G_INTRINSIC_ROUND:
1882     assert(TypeIdx == 0);
1883     Observer.changingInstr(MI);
1884 
1885     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1886       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1887 
1888     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1889     Observer.changedInstr(MI);
1890     return Legalized;
1891   case TargetOpcode::G_INTTOPTR:
1892     if (TypeIdx != 1)
1893       return UnableToLegalize;
1894 
1895     Observer.changingInstr(MI);
1896     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1897     Observer.changedInstr(MI);
1898     return Legalized;
1899   case TargetOpcode::G_PTRTOINT:
1900     if (TypeIdx != 0)
1901       return UnableToLegalize;
1902 
1903     Observer.changingInstr(MI);
1904     widenScalarDst(MI, WideTy, 0);
1905     Observer.changedInstr(MI);
1906     return Legalized;
1907   case TargetOpcode::G_BUILD_VECTOR: {
1908     Observer.changingInstr(MI);
1909 
1910     const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
1911     for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
1912       widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT);
1913 
1914     // Avoid changing the result vector type if the source element type was
1915     // requested.
1916     if (TypeIdx == 1) {
1917       auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
1918       MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
1919     } else {
1920       widenScalarDst(MI, WideTy, 0);
1921     }
1922 
1923     Observer.changedInstr(MI);
1924     return Legalized;
1925   }
1926   case TargetOpcode::G_SEXT_INREG:
1927     if (TypeIdx != 0)
1928       return UnableToLegalize;
1929 
1930     Observer.changingInstr(MI);
1931     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1932     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC);
1933     Observer.changedInstr(MI);
1934     return Legalized;
1935   }
1936 }
1937 
1938 LegalizerHelper::LegalizeResult
1939 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1940   using namespace TargetOpcode;
1941   MIRBuilder.setInstr(MI);
1942 
1943   switch(MI.getOpcode()) {
1944   default:
1945     return UnableToLegalize;
1946   case TargetOpcode::G_SREM:
1947   case TargetOpcode::G_UREM: {
1948     Register QuotReg = MRI.createGenericVirtualRegister(Ty);
1949     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1950         .addDef(QuotReg)
1951         .addUse(MI.getOperand(1).getReg())
1952         .addUse(MI.getOperand(2).getReg());
1953 
1954     Register ProdReg = MRI.createGenericVirtualRegister(Ty);
1955     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1956     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1957                         ProdReg);
1958     MI.eraseFromParent();
1959     return Legalized;
1960   }
1961   case TargetOpcode::G_SADDO:
1962   case TargetOpcode::G_SSUBO:
1963     return lowerSADDO_SSUBO(MI);
1964   case TargetOpcode::G_SMULO:
1965   case TargetOpcode::G_UMULO: {
1966     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
1967     // result.
1968     Register Res = MI.getOperand(0).getReg();
1969     Register Overflow = MI.getOperand(1).getReg();
1970     Register LHS = MI.getOperand(2).getReg();
1971     Register RHS = MI.getOperand(3).getReg();
1972 
1973     MIRBuilder.buildMul(Res, LHS, RHS);
1974 
1975     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
1976                           ? TargetOpcode::G_SMULH
1977                           : TargetOpcode::G_UMULH;
1978 
1979     Register HiPart = MRI.createGenericVirtualRegister(Ty);
1980     MIRBuilder.buildInstr(Opcode)
1981       .addDef(HiPart)
1982       .addUse(LHS)
1983       .addUse(RHS);
1984 
1985     Register Zero = MRI.createGenericVirtualRegister(Ty);
1986     MIRBuilder.buildConstant(Zero, 0);
1987 
1988     // For *signed* multiply, overflow is detected by checking:
1989     // (hi != (lo >> bitwidth-1))
1990     if (Opcode == TargetOpcode::G_SMULH) {
1991       Register Shifted = MRI.createGenericVirtualRegister(Ty);
1992       Register ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1993       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
1994       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
1995         .addDef(Shifted)
1996         .addUse(Res)
1997         .addUse(ShiftAmt);
1998       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
1999     } else {
2000       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
2001     }
2002     MI.eraseFromParent();
2003     return Legalized;
2004   }
2005   case TargetOpcode::G_FNEG: {
2006     // TODO: Handle vector types once we are able to
2007     // represent them.
2008     if (Ty.isVector())
2009       return UnableToLegalize;
2010     Register Res = MI.getOperand(0).getReg();
2011     Type *ZeroTy;
2012     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
2013     switch (Ty.getSizeInBits()) {
2014     case 16:
2015       ZeroTy = Type::getHalfTy(Ctx);
2016       break;
2017     case 32:
2018       ZeroTy = Type::getFloatTy(Ctx);
2019       break;
2020     case 64:
2021       ZeroTy = Type::getDoubleTy(Ctx);
2022       break;
2023     case 128:
2024       ZeroTy = Type::getFP128Ty(Ctx);
2025       break;
2026     default:
2027       llvm_unreachable("unexpected floating-point type");
2028     }
2029     ConstantFP &ZeroForNegation =
2030         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
2031     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
2032     Register SubByReg = MI.getOperand(1).getReg();
2033     Register ZeroReg = Zero->getOperand(0).getReg();
2034     MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
2035                           MI.getFlags());
2036     MI.eraseFromParent();
2037     return Legalized;
2038   }
2039   case TargetOpcode::G_FSUB: {
2040     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
2041     // First, check if G_FNEG is marked as Lower. If so, we may
2042     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
2043     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
2044       return UnableToLegalize;
2045     Register Res = MI.getOperand(0).getReg();
2046     Register LHS = MI.getOperand(1).getReg();
2047     Register RHS = MI.getOperand(2).getReg();
2048     Register Neg = MRI.createGenericVirtualRegister(Ty);
2049     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
2050     MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
2051     MI.eraseFromParent();
2052     return Legalized;
2053   }
2054   case TargetOpcode::G_FMAD:
2055     return lowerFMad(MI);
2056   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
2057     Register OldValRes = MI.getOperand(0).getReg();
2058     Register SuccessRes = MI.getOperand(1).getReg();
2059     Register Addr = MI.getOperand(2).getReg();
2060     Register CmpVal = MI.getOperand(3).getReg();
2061     Register NewVal = MI.getOperand(4).getReg();
2062     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
2063                                   **MI.memoperands_begin());
2064     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
2065     MI.eraseFromParent();
2066     return Legalized;
2067   }
2068   case TargetOpcode::G_LOAD:
2069   case TargetOpcode::G_SEXTLOAD:
2070   case TargetOpcode::G_ZEXTLOAD: {
2071     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
2072     Register DstReg = MI.getOperand(0).getReg();
2073     Register PtrReg = MI.getOperand(1).getReg();
2074     LLT DstTy = MRI.getType(DstReg);
2075     auto &MMO = **MI.memoperands_begin();
2076 
2077     if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
2078       if (MI.getOpcode() == TargetOpcode::G_LOAD) {
2079         // This load needs splitting into power of 2 sized loads.
2080         if (DstTy.isVector())
2081           return UnableToLegalize;
2082         if (isPowerOf2_32(DstTy.getSizeInBits()))
2083           return UnableToLegalize; // Don't know what we're being asked to do.
2084 
2085         // Our strategy here is to generate anyextending loads for the smaller
2086         // types up to next power-2 result type, and then combine the two larger
2087         // result values together, before truncating back down to the non-pow-2
2088         // type.
2089         // E.g. v1 = i24 load =>
2090         // v2 = i32 load (2 byte)
2091         // v3 = i32 load (1 byte)
2092         // v4 = i32 shl v3, 16
2093         // v5 = i32 or v4, v2
2094         // v1 = i24 trunc v5
2095         // By doing this we generate the correct truncate which should get
2096         // combined away as an artifact with a matching extend.
2097         uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits());
2098         uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize;
2099 
2100         MachineFunction &MF = MIRBuilder.getMF();
2101         MachineMemOperand *LargeMMO =
2102             MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2103         MachineMemOperand *SmallMMO = MF.getMachineMemOperand(
2104             &MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2105 
2106         LLT PtrTy = MRI.getType(PtrReg);
2107         unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits());
2108         LLT AnyExtTy = LLT::scalar(AnyExtSize);
2109         Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2110         Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2111         auto LargeLoad =
2112             MIRBuilder.buildLoad(LargeLdReg, PtrReg, *LargeMMO);
2113 
2114         auto OffsetCst =
2115             MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2116         Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2117         auto SmallPtr =
2118             MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2119         auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
2120                                               *SmallMMO);
2121 
2122         auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
2123         auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt);
2124         auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
2125         MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)});
2126         MI.eraseFromParent();
2127         return Legalized;
2128       }
2129       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
2130       MI.eraseFromParent();
2131       return Legalized;
2132     }
2133 
2134     if (DstTy.isScalar()) {
2135       Register TmpReg =
2136           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
2137       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
2138       switch (MI.getOpcode()) {
2139       default:
2140         llvm_unreachable("Unexpected opcode");
2141       case TargetOpcode::G_LOAD:
2142         MIRBuilder.buildExtOrTrunc(TargetOpcode::G_ANYEXT, DstReg, TmpReg);
2143         break;
2144       case TargetOpcode::G_SEXTLOAD:
2145         MIRBuilder.buildSExt(DstReg, TmpReg);
2146         break;
2147       case TargetOpcode::G_ZEXTLOAD:
2148         MIRBuilder.buildZExt(DstReg, TmpReg);
2149         break;
2150       }
2151       MI.eraseFromParent();
2152       return Legalized;
2153     }
2154 
2155     return UnableToLegalize;
2156   }
2157   case TargetOpcode::G_STORE: {
2158     // Lower a non-power of 2 store into multiple pow-2 stores.
2159     // E.g. split an i24 store into an i16 store + i8 store.
2160     // We do this by first extending the stored value to the next largest power
2161     // of 2 type, and then using truncating stores to store the components.
2162     // By doing this, likewise with G_LOAD, generate an extend that can be
2163     // artifact-combined away instead of leaving behind extracts.
2164     Register SrcReg = MI.getOperand(0).getReg();
2165     Register PtrReg = MI.getOperand(1).getReg();
2166     LLT SrcTy = MRI.getType(SrcReg);
2167     MachineMemOperand &MMO = **MI.memoperands_begin();
2168     if (SrcTy.getSizeInBits() != MMO.getSizeInBits())
2169       return UnableToLegalize;
2170     if (SrcTy.isVector())
2171       return UnableToLegalize;
2172     if (isPowerOf2_32(SrcTy.getSizeInBits()))
2173       return UnableToLegalize; // Don't know what we're being asked to do.
2174 
2175     // Extend to the next pow-2.
2176     const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits()));
2177     auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg);
2178 
2179     // Obtain the smaller value by shifting away the larger value.
2180     uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits());
2181     uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize;
2182     auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize);
2183     auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt);
2184 
2185     // Generate the PtrAdd and truncating stores.
2186     LLT PtrTy = MRI.getType(PtrReg);
2187     auto OffsetCst =
2188         MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2189     Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2190     auto SmallPtr =
2191         MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2192 
2193     MachineFunction &MF = MIRBuilder.getMF();
2194     MachineMemOperand *LargeMMO =
2195         MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2196     MachineMemOperand *SmallMMO =
2197         MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2198     MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO);
2199     MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO);
2200     MI.eraseFromParent();
2201     return Legalized;
2202   }
2203   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
2204   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
2205   case TargetOpcode::G_CTLZ:
2206   case TargetOpcode::G_CTTZ:
2207   case TargetOpcode::G_CTPOP:
2208     return lowerBitCount(MI, TypeIdx, Ty);
2209   case G_UADDO: {
2210     Register Res = MI.getOperand(0).getReg();
2211     Register CarryOut = MI.getOperand(1).getReg();
2212     Register LHS = MI.getOperand(2).getReg();
2213     Register RHS = MI.getOperand(3).getReg();
2214 
2215     MIRBuilder.buildAdd(Res, LHS, RHS);
2216     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
2217 
2218     MI.eraseFromParent();
2219     return Legalized;
2220   }
2221   case G_UADDE: {
2222     Register Res = MI.getOperand(0).getReg();
2223     Register CarryOut = MI.getOperand(1).getReg();
2224     Register LHS = MI.getOperand(2).getReg();
2225     Register RHS = MI.getOperand(3).getReg();
2226     Register CarryIn = MI.getOperand(4).getReg();
2227 
2228     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2229     Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
2230 
2231     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
2232     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
2233     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
2234     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
2235 
2236     MI.eraseFromParent();
2237     return Legalized;
2238   }
2239   case G_USUBO: {
2240     Register Res = MI.getOperand(0).getReg();
2241     Register BorrowOut = MI.getOperand(1).getReg();
2242     Register LHS = MI.getOperand(2).getReg();
2243     Register RHS = MI.getOperand(3).getReg();
2244 
2245     MIRBuilder.buildSub(Res, LHS, RHS);
2246     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
2247 
2248     MI.eraseFromParent();
2249     return Legalized;
2250   }
2251   case G_USUBE: {
2252     Register Res = MI.getOperand(0).getReg();
2253     Register BorrowOut = MI.getOperand(1).getReg();
2254     Register LHS = MI.getOperand(2).getReg();
2255     Register RHS = MI.getOperand(3).getReg();
2256     Register BorrowIn = MI.getOperand(4).getReg();
2257 
2258     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2259     Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
2260     Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2261     Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2262 
2263     MIRBuilder.buildSub(TmpRes, LHS, RHS);
2264     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
2265     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
2266     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
2267     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
2268     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
2269 
2270     MI.eraseFromParent();
2271     return Legalized;
2272   }
2273   case G_UITOFP:
2274     return lowerUITOFP(MI, TypeIdx, Ty);
2275   case G_SITOFP:
2276     return lowerSITOFP(MI, TypeIdx, Ty);
2277   case G_FPTOUI:
2278     return lowerFPTOUI(MI, TypeIdx, Ty);
2279   case G_SMIN:
2280   case G_SMAX:
2281   case G_UMIN:
2282   case G_UMAX:
2283     return lowerMinMax(MI, TypeIdx, Ty);
2284   case G_FCOPYSIGN:
2285     return lowerFCopySign(MI, TypeIdx, Ty);
2286   case G_FMINNUM:
2287   case G_FMAXNUM:
2288     return lowerFMinNumMaxNum(MI);
2289   case G_UNMERGE_VALUES:
2290     return lowerUnmergeValues(MI);
2291   case TargetOpcode::G_SEXT_INREG: {
2292     assert(MI.getOperand(2).isImm() && "Expected immediate");
2293     int64_t SizeInBits = MI.getOperand(2).getImm();
2294 
2295     Register DstReg = MI.getOperand(0).getReg();
2296     Register SrcReg = MI.getOperand(1).getReg();
2297     LLT DstTy = MRI.getType(DstReg);
2298     Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
2299 
2300     auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
2301     MIRBuilder.buildInstr(TargetOpcode::G_SHL, {TmpRes}, {SrcReg, MIBSz->getOperand(0).getReg()});
2302     MIRBuilder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {TmpRes, MIBSz->getOperand(0).getReg()});
2303     MI.eraseFromParent();
2304     return Legalized;
2305   }
2306   case G_SHUFFLE_VECTOR:
2307     return lowerShuffleVector(MI);
2308   case G_DYN_STACKALLOC:
2309     return lowerDynStackAlloc(MI);
2310   case G_EXTRACT:
2311     return lowerExtract(MI);
2312   case G_INSERT:
2313     return lowerInsert(MI);
2314   case G_BSWAP:
2315     return lowerBswap(MI);
2316   case G_BITREVERSE:
2317     return lowerBitreverse(MI);
2318   }
2319 }
2320 
2321 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
2322     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
2323   SmallVector<Register, 2> DstRegs;
2324 
2325   unsigned NarrowSize = NarrowTy.getSizeInBits();
2326   Register DstReg = MI.getOperand(0).getReg();
2327   unsigned Size = MRI.getType(DstReg).getSizeInBits();
2328   int NumParts = Size / NarrowSize;
2329   // FIXME: Don't know how to handle the situation where the small vectors
2330   // aren't all the same size yet.
2331   if (Size % NarrowSize != 0)
2332     return UnableToLegalize;
2333 
2334   for (int i = 0; i < NumParts; ++i) {
2335     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
2336     MIRBuilder.buildUndef(TmpReg);
2337     DstRegs.push_back(TmpReg);
2338   }
2339 
2340   if (NarrowTy.isVector())
2341     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2342   else
2343     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2344 
2345   MI.eraseFromParent();
2346   return Legalized;
2347 }
2348 
2349 LegalizerHelper::LegalizeResult
2350 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
2351                                           LLT NarrowTy) {
2352   const unsigned Opc = MI.getOpcode();
2353   const unsigned NumOps = MI.getNumOperands() - 1;
2354   const unsigned NarrowSize = NarrowTy.getSizeInBits();
2355   const Register DstReg = MI.getOperand(0).getReg();
2356   const unsigned Flags = MI.getFlags();
2357   const LLT DstTy = MRI.getType(DstReg);
2358   const unsigned Size = DstTy.getSizeInBits();
2359   const int NumParts = Size / NarrowSize;
2360   const LLT EltTy = DstTy.getElementType();
2361   const unsigned EltSize = EltTy.getSizeInBits();
2362   const unsigned BitsForNumParts = NarrowSize * NumParts;
2363 
2364   // Check if we have any leftovers. If we do, then only handle the case where
2365   // the leftover is one element.
2366   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
2367     return UnableToLegalize;
2368 
2369   if (BitsForNumParts != Size) {
2370     Register AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
2371     MIRBuilder.buildUndef(AccumDstReg);
2372 
2373     // Handle the pieces which evenly divide into the requested type with
2374     // extract/op/insert sequence.
2375     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
2376       SmallVector<SrcOp, 4> SrcOps;
2377       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2378         Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
2379         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
2380         SrcOps.push_back(PartOpReg);
2381       }
2382 
2383       Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
2384       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2385 
2386       Register PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
2387       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
2388       AccumDstReg = PartInsertReg;
2389     }
2390 
2391     // Handle the remaining element sized leftover piece.
2392     SmallVector<SrcOp, 4> SrcOps;
2393     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2394       Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
2395       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
2396                               BitsForNumParts);
2397       SrcOps.push_back(PartOpReg);
2398     }
2399 
2400     Register PartDstReg = MRI.createGenericVirtualRegister(EltTy);
2401     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2402     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
2403     MI.eraseFromParent();
2404 
2405     return Legalized;
2406   }
2407 
2408   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2409 
2410   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
2411 
2412   if (NumOps >= 2)
2413     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
2414 
2415   if (NumOps >= 3)
2416     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
2417 
2418   for (int i = 0; i < NumParts; ++i) {
2419     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2420 
2421     if (NumOps == 1)
2422       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
2423     else if (NumOps == 2) {
2424       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
2425     } else if (NumOps == 3) {
2426       MIRBuilder.buildInstr(Opc, {DstReg},
2427                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
2428     }
2429 
2430     DstRegs.push_back(DstReg);
2431   }
2432 
2433   if (NarrowTy.isVector())
2434     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2435   else
2436     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2437 
2438   MI.eraseFromParent();
2439   return Legalized;
2440 }
2441 
2442 // Handle splitting vector operations which need to have the same number of
2443 // elements in each type index, but each type index may have a different element
2444 // type.
2445 //
2446 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
2447 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2448 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2449 //
2450 // Also handles some irregular breakdown cases, e.g.
2451 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
2452 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2453 //             s64 = G_SHL s64, s32
2454 LegalizerHelper::LegalizeResult
2455 LegalizerHelper::fewerElementsVectorMultiEltType(
2456   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
2457   if (TypeIdx != 0)
2458     return UnableToLegalize;
2459 
2460   const LLT NarrowTy0 = NarrowTyArg;
2461   const unsigned NewNumElts =
2462       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
2463 
2464   const Register DstReg = MI.getOperand(0).getReg();
2465   LLT DstTy = MRI.getType(DstReg);
2466   LLT LeftoverTy0;
2467 
2468   // All of the operands need to have the same number of elements, so if we can
2469   // determine a type breakdown for the result type, we can for all of the
2470   // source types.
2471   int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first;
2472   if (NumParts < 0)
2473     return UnableToLegalize;
2474 
2475   SmallVector<MachineInstrBuilder, 4> NewInsts;
2476 
2477   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2478   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2479 
2480   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2481     LLT LeftoverTy;
2482     Register SrcReg = MI.getOperand(I).getReg();
2483     LLT SrcTyI = MRI.getType(SrcReg);
2484     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
2485     LLT LeftoverTyI;
2486 
2487     // Split this operand into the requested typed registers, and any leftover
2488     // required to reproduce the original type.
2489     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
2490                       LeftoverRegs))
2491       return UnableToLegalize;
2492 
2493     if (I == 1) {
2494       // For the first operand, create an instruction for each part and setup
2495       // the result.
2496       for (Register PartReg : PartRegs) {
2497         Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2498         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2499                                .addDef(PartDstReg)
2500                                .addUse(PartReg));
2501         DstRegs.push_back(PartDstReg);
2502       }
2503 
2504       for (Register LeftoverReg : LeftoverRegs) {
2505         Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
2506         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2507                                .addDef(PartDstReg)
2508                                .addUse(LeftoverReg));
2509         LeftoverDstRegs.push_back(PartDstReg);
2510       }
2511     } else {
2512       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
2513 
2514       // Add the newly created operand splits to the existing instructions. The
2515       // odd-sized pieces are ordered after the requested NarrowTyArg sized
2516       // pieces.
2517       unsigned InstCount = 0;
2518       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
2519         NewInsts[InstCount++].addUse(PartRegs[J]);
2520       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
2521         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
2522     }
2523 
2524     PartRegs.clear();
2525     LeftoverRegs.clear();
2526   }
2527 
2528   // Insert the newly built operations and rebuild the result register.
2529   for (auto &MIB : NewInsts)
2530     MIRBuilder.insertInstr(MIB);
2531 
2532   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
2533 
2534   MI.eraseFromParent();
2535   return Legalized;
2536 }
2537 
2538 LegalizerHelper::LegalizeResult
2539 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
2540                                           LLT NarrowTy) {
2541   if (TypeIdx != 0)
2542     return UnableToLegalize;
2543 
2544   Register DstReg = MI.getOperand(0).getReg();
2545   Register SrcReg = MI.getOperand(1).getReg();
2546   LLT DstTy = MRI.getType(DstReg);
2547   LLT SrcTy = MRI.getType(SrcReg);
2548 
2549   LLT NarrowTy0 = NarrowTy;
2550   LLT NarrowTy1;
2551   unsigned NumParts;
2552 
2553   if (NarrowTy.isVector()) {
2554     // Uneven breakdown not handled.
2555     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
2556     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
2557       return UnableToLegalize;
2558 
2559     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
2560   } else {
2561     NumParts = DstTy.getNumElements();
2562     NarrowTy1 = SrcTy.getElementType();
2563   }
2564 
2565   SmallVector<Register, 4> SrcRegs, DstRegs;
2566   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
2567 
2568   for (unsigned I = 0; I < NumParts; ++I) {
2569     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2570     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
2571       .addDef(DstReg)
2572       .addUse(SrcRegs[I]);
2573 
2574     NewInst->setFlags(MI.getFlags());
2575     DstRegs.push_back(DstReg);
2576   }
2577 
2578   if (NarrowTy.isVector())
2579     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2580   else
2581     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2582 
2583   MI.eraseFromParent();
2584   return Legalized;
2585 }
2586 
2587 LegalizerHelper::LegalizeResult
2588 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
2589                                         LLT NarrowTy) {
2590   Register DstReg = MI.getOperand(0).getReg();
2591   Register Src0Reg = MI.getOperand(2).getReg();
2592   LLT DstTy = MRI.getType(DstReg);
2593   LLT SrcTy = MRI.getType(Src0Reg);
2594 
2595   unsigned NumParts;
2596   LLT NarrowTy0, NarrowTy1;
2597 
2598   if (TypeIdx == 0) {
2599     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2600     unsigned OldElts = DstTy.getNumElements();
2601 
2602     NarrowTy0 = NarrowTy;
2603     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
2604     NarrowTy1 = NarrowTy.isVector() ?
2605       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
2606       SrcTy.getElementType();
2607 
2608   } else {
2609     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2610     unsigned OldElts = SrcTy.getNumElements();
2611 
2612     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
2613       NarrowTy.getNumElements();
2614     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
2615                             DstTy.getScalarSizeInBits());
2616     NarrowTy1 = NarrowTy;
2617   }
2618 
2619   // FIXME: Don't know how to handle the situation where the small vectors
2620   // aren't all the same size yet.
2621   if (NarrowTy1.isVector() &&
2622       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
2623     return UnableToLegalize;
2624 
2625   CmpInst::Predicate Pred
2626     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
2627 
2628   SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
2629   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
2630   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
2631 
2632   for (unsigned I = 0; I < NumParts; ++I) {
2633     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2634     DstRegs.push_back(DstReg);
2635 
2636     if (MI.getOpcode() == TargetOpcode::G_ICMP)
2637       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2638     else {
2639       MachineInstr *NewCmp
2640         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2641       NewCmp->setFlags(MI.getFlags());
2642     }
2643   }
2644 
2645   if (NarrowTy1.isVector())
2646     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2647   else
2648     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2649 
2650   MI.eraseFromParent();
2651   return Legalized;
2652 }
2653 
2654 LegalizerHelper::LegalizeResult
2655 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
2656                                            LLT NarrowTy) {
2657   Register DstReg = MI.getOperand(0).getReg();
2658   Register CondReg = MI.getOperand(1).getReg();
2659 
2660   unsigned NumParts = 0;
2661   LLT NarrowTy0, NarrowTy1;
2662 
2663   LLT DstTy = MRI.getType(DstReg);
2664   LLT CondTy = MRI.getType(CondReg);
2665   unsigned Size = DstTy.getSizeInBits();
2666 
2667   assert(TypeIdx == 0 || CondTy.isVector());
2668 
2669   if (TypeIdx == 0) {
2670     NarrowTy0 = NarrowTy;
2671     NarrowTy1 = CondTy;
2672 
2673     unsigned NarrowSize = NarrowTy0.getSizeInBits();
2674     // FIXME: Don't know how to handle the situation where the small vectors
2675     // aren't all the same size yet.
2676     if (Size % NarrowSize != 0)
2677       return UnableToLegalize;
2678 
2679     NumParts = Size / NarrowSize;
2680 
2681     // Need to break down the condition type
2682     if (CondTy.isVector()) {
2683       if (CondTy.getNumElements() == NumParts)
2684         NarrowTy1 = CondTy.getElementType();
2685       else
2686         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
2687                                 CondTy.getScalarSizeInBits());
2688     }
2689   } else {
2690     NumParts = CondTy.getNumElements();
2691     if (NarrowTy.isVector()) {
2692       // TODO: Handle uneven breakdown.
2693       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
2694         return UnableToLegalize;
2695 
2696       return UnableToLegalize;
2697     } else {
2698       NarrowTy0 = DstTy.getElementType();
2699       NarrowTy1 = NarrowTy;
2700     }
2701   }
2702 
2703   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2704   if (CondTy.isVector())
2705     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2706 
2707   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2708   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2709 
2710   for (unsigned i = 0; i < NumParts; ++i) {
2711     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2712     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
2713                            Src1Regs[i], Src2Regs[i]);
2714     DstRegs.push_back(DstReg);
2715   }
2716 
2717   if (NarrowTy0.isVector())
2718     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2719   else
2720     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2721 
2722   MI.eraseFromParent();
2723   return Legalized;
2724 }
2725 
2726 LegalizerHelper::LegalizeResult
2727 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2728                                         LLT NarrowTy) {
2729   const Register DstReg = MI.getOperand(0).getReg();
2730   LLT PhiTy = MRI.getType(DstReg);
2731   LLT LeftoverTy;
2732 
2733   // All of the operands need to have the same number of elements, so if we can
2734   // determine a type breakdown for the result type, we can for all of the
2735   // source types.
2736   int NumParts, NumLeftover;
2737   std::tie(NumParts, NumLeftover)
2738     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2739   if (NumParts < 0)
2740     return UnableToLegalize;
2741 
2742   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2743   SmallVector<MachineInstrBuilder, 4> NewInsts;
2744 
2745   const int TotalNumParts = NumParts + NumLeftover;
2746 
2747   // Insert the new phis in the result block first.
2748   for (int I = 0; I != TotalNumParts; ++I) {
2749     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2750     Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
2751     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2752                        .addDef(PartDstReg));
2753     if (I < NumParts)
2754       DstRegs.push_back(PartDstReg);
2755     else
2756       LeftoverDstRegs.push_back(PartDstReg);
2757   }
2758 
2759   MachineBasicBlock *MBB = MI.getParent();
2760   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2761   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2762 
2763   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2764 
2765   // Insert code to extract the incoming values in each predecessor block.
2766   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2767     PartRegs.clear();
2768     LeftoverRegs.clear();
2769 
2770     Register SrcReg = MI.getOperand(I).getReg();
2771     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2772     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2773 
2774     LLT Unused;
2775     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2776                       LeftoverRegs))
2777       return UnableToLegalize;
2778 
2779     // Add the newly created operand splits to the existing instructions. The
2780     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2781     // pieces.
2782     for (int J = 0; J != TotalNumParts; ++J) {
2783       MachineInstrBuilder MIB = NewInsts[J];
2784       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2785       MIB.addMBB(&OpMBB);
2786     }
2787   }
2788 
2789   MI.eraseFromParent();
2790   return Legalized;
2791 }
2792 
2793 LegalizerHelper::LegalizeResult
2794 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
2795                                                   unsigned TypeIdx,
2796                                                   LLT NarrowTy) {
2797   if (TypeIdx != 1)
2798     return UnableToLegalize;
2799 
2800   const int NumDst = MI.getNumOperands() - 1;
2801   const Register SrcReg = MI.getOperand(NumDst).getReg();
2802   LLT SrcTy = MRI.getType(SrcReg);
2803 
2804   LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2805 
2806   // TODO: Create sequence of extracts.
2807   if (DstTy == NarrowTy)
2808     return UnableToLegalize;
2809 
2810   LLT GCDTy = getGCDType(SrcTy, NarrowTy);
2811   if (DstTy == GCDTy) {
2812     // This would just be a copy of the same unmerge.
2813     // TODO: Create extracts, pad with undef and create intermediate merges.
2814     return UnableToLegalize;
2815   }
2816 
2817   auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
2818   const int NumUnmerge = Unmerge->getNumOperands() - 1;
2819   const int PartsPerUnmerge = NumDst / NumUnmerge;
2820 
2821   for (int I = 0; I != NumUnmerge; ++I) {
2822     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
2823 
2824     for (int J = 0; J != PartsPerUnmerge; ++J)
2825       MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg());
2826     MIB.addUse(Unmerge.getReg(I));
2827   }
2828 
2829   MI.eraseFromParent();
2830   return Legalized;
2831 }
2832 
2833 LegalizerHelper::LegalizeResult
2834 LegalizerHelper::fewerElementsVectorBuildVector(MachineInstr &MI,
2835                                                 unsigned TypeIdx,
2836                                                 LLT NarrowTy) {
2837   assert(TypeIdx == 0 && "not a vector type index");
2838   Register DstReg = MI.getOperand(0).getReg();
2839   LLT DstTy = MRI.getType(DstReg);
2840   LLT SrcTy = DstTy.getElementType();
2841 
2842   int DstNumElts = DstTy.getNumElements();
2843   int NarrowNumElts = NarrowTy.getNumElements();
2844   int NumConcat = (DstNumElts + NarrowNumElts - 1) / NarrowNumElts;
2845   LLT WidenedDstTy = LLT::vector(NarrowNumElts * NumConcat, SrcTy);
2846 
2847   SmallVector<Register, 8> ConcatOps;
2848   SmallVector<Register, 8> SubBuildVector;
2849 
2850   Register UndefReg;
2851   if (WidenedDstTy != DstTy)
2852     UndefReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
2853 
2854   // Create a G_CONCAT_VECTORS of NarrowTy pieces, padding with undef as
2855   // necessary.
2856   //
2857   // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2
2858   //   -> <2 x s16>
2859   //
2860   // %4:_(s16) = G_IMPLICIT_DEF
2861   // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1
2862   // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4
2863   // %7:_(<4 x s16>) = G_CONCAT_VECTORS %5, %6
2864   // %3:_(<3 x s16>) = G_EXTRACT %7, 0
2865   for (int I = 0; I != NumConcat; ++I) {
2866     for (int J = 0; J != NarrowNumElts; ++J) {
2867       int SrcIdx = NarrowNumElts * I + J;
2868 
2869       if (SrcIdx < DstNumElts) {
2870         Register SrcReg = MI.getOperand(SrcIdx + 1).getReg();
2871         SubBuildVector.push_back(SrcReg);
2872       } else
2873         SubBuildVector.push_back(UndefReg);
2874     }
2875 
2876     auto BuildVec = MIRBuilder.buildBuildVector(NarrowTy, SubBuildVector);
2877     ConcatOps.push_back(BuildVec.getReg(0));
2878     SubBuildVector.clear();
2879   }
2880 
2881   if (DstTy == WidenedDstTy)
2882     MIRBuilder.buildConcatVectors(DstReg, ConcatOps);
2883   else {
2884     auto Concat = MIRBuilder.buildConcatVectors(WidenedDstTy, ConcatOps);
2885     MIRBuilder.buildExtract(DstReg, Concat, 0);
2886   }
2887 
2888   MI.eraseFromParent();
2889   return Legalized;
2890 }
2891 
2892 LegalizerHelper::LegalizeResult
2893 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2894                                       LLT NarrowTy) {
2895   // FIXME: Don't know how to handle secondary types yet.
2896   if (TypeIdx != 0)
2897     return UnableToLegalize;
2898 
2899   MachineMemOperand *MMO = *MI.memoperands_begin();
2900 
2901   // This implementation doesn't work for atomics. Give up instead of doing
2902   // something invalid.
2903   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2904       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2905     return UnableToLegalize;
2906 
2907   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2908   Register ValReg = MI.getOperand(0).getReg();
2909   Register AddrReg = MI.getOperand(1).getReg();
2910   LLT ValTy = MRI.getType(ValReg);
2911 
2912   int NumParts = -1;
2913   int NumLeftover = -1;
2914   LLT LeftoverTy;
2915   SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
2916   if (IsLoad) {
2917     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2918   } else {
2919     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2920                      NarrowLeftoverRegs)) {
2921       NumParts = NarrowRegs.size();
2922       NumLeftover = NarrowLeftoverRegs.size();
2923     }
2924   }
2925 
2926   if (NumParts == -1)
2927     return UnableToLegalize;
2928 
2929   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2930 
2931   unsigned TotalSize = ValTy.getSizeInBits();
2932 
2933   // Split the load/store into PartTy sized pieces starting at Offset. If this
2934   // is a load, return the new registers in ValRegs. For a store, each elements
2935   // of ValRegs should be PartTy. Returns the next offset that needs to be
2936   // handled.
2937   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
2938                              unsigned Offset) -> unsigned {
2939     MachineFunction &MF = MIRBuilder.getMF();
2940     unsigned PartSize = PartTy.getSizeInBits();
2941     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2942          Offset += PartSize, ++Idx) {
2943       unsigned ByteSize = PartSize / 8;
2944       unsigned ByteOffset = Offset / 8;
2945       Register NewAddrReg;
2946 
2947       MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2948 
2949       MachineMemOperand *NewMMO =
2950         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2951 
2952       if (IsLoad) {
2953         Register Dst = MRI.createGenericVirtualRegister(PartTy);
2954         ValRegs.push_back(Dst);
2955         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
2956       } else {
2957         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
2958       }
2959     }
2960 
2961     return Offset;
2962   };
2963 
2964   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
2965 
2966   // Handle the rest of the register if this isn't an even type breakdown.
2967   if (LeftoverTy.isValid())
2968     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
2969 
2970   if (IsLoad) {
2971     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
2972                 LeftoverTy, NarrowLeftoverRegs);
2973   }
2974 
2975   MI.eraseFromParent();
2976   return Legalized;
2977 }
2978 
2979 LegalizerHelper::LegalizeResult
2980 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
2981                                      LLT NarrowTy) {
2982   using namespace TargetOpcode;
2983 
2984   MIRBuilder.setInstr(MI);
2985   switch (MI.getOpcode()) {
2986   case G_IMPLICIT_DEF:
2987     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
2988   case G_AND:
2989   case G_OR:
2990   case G_XOR:
2991   case G_ADD:
2992   case G_SUB:
2993   case G_MUL:
2994   case G_SMULH:
2995   case G_UMULH:
2996   case G_FADD:
2997   case G_FMUL:
2998   case G_FSUB:
2999   case G_FNEG:
3000   case G_FABS:
3001   case G_FCANONICALIZE:
3002   case G_FDIV:
3003   case G_FREM:
3004   case G_FMA:
3005   case G_FMAD:
3006   case G_FPOW:
3007   case G_FEXP:
3008   case G_FEXP2:
3009   case G_FLOG:
3010   case G_FLOG2:
3011   case G_FLOG10:
3012   case G_FNEARBYINT:
3013   case G_FCEIL:
3014   case G_FFLOOR:
3015   case G_FRINT:
3016   case G_INTRINSIC_ROUND:
3017   case G_INTRINSIC_TRUNC:
3018   case G_FCOS:
3019   case G_FSIN:
3020   case G_FSQRT:
3021   case G_BSWAP:
3022   case G_BITREVERSE:
3023   case G_SDIV:
3024   case G_SMIN:
3025   case G_SMAX:
3026   case G_UMIN:
3027   case G_UMAX:
3028   case G_FMINNUM:
3029   case G_FMAXNUM:
3030   case G_FMINNUM_IEEE:
3031   case G_FMAXNUM_IEEE:
3032   case G_FMINIMUM:
3033   case G_FMAXIMUM:
3034     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
3035   case G_SHL:
3036   case G_LSHR:
3037   case G_ASHR:
3038   case G_CTLZ:
3039   case G_CTLZ_ZERO_UNDEF:
3040   case G_CTTZ:
3041   case G_CTTZ_ZERO_UNDEF:
3042   case G_CTPOP:
3043   case G_FCOPYSIGN:
3044     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
3045   case G_ZEXT:
3046   case G_SEXT:
3047   case G_ANYEXT:
3048   case G_FPEXT:
3049   case G_FPTRUNC:
3050   case G_SITOFP:
3051   case G_UITOFP:
3052   case G_FPTOSI:
3053   case G_FPTOUI:
3054   case G_INTTOPTR:
3055   case G_PTRTOINT:
3056   case G_ADDRSPACE_CAST:
3057     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
3058   case G_ICMP:
3059   case G_FCMP:
3060     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
3061   case G_SELECT:
3062     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
3063   case G_PHI:
3064     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
3065   case G_UNMERGE_VALUES:
3066     return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy);
3067   case G_BUILD_VECTOR:
3068     return fewerElementsVectorBuildVector(MI, TypeIdx, NarrowTy);
3069   case G_LOAD:
3070   case G_STORE:
3071     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
3072   default:
3073     return UnableToLegalize;
3074   }
3075 }
3076 
3077 LegalizerHelper::LegalizeResult
3078 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
3079                                              const LLT HalfTy, const LLT AmtTy) {
3080 
3081   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3082   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3083   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3084 
3085   if (Amt.isNullValue()) {
3086     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
3087     MI.eraseFromParent();
3088     return Legalized;
3089   }
3090 
3091   LLT NVT = HalfTy;
3092   unsigned NVTBits = HalfTy.getSizeInBits();
3093   unsigned VTBits = 2 * NVTBits;
3094 
3095   SrcOp Lo(Register(0)), Hi(Register(0));
3096   if (MI.getOpcode() == TargetOpcode::G_SHL) {
3097     if (Amt.ugt(VTBits)) {
3098       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3099     } else if (Amt.ugt(NVTBits)) {
3100       Lo = MIRBuilder.buildConstant(NVT, 0);
3101       Hi = MIRBuilder.buildShl(NVT, InL,
3102                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3103     } else if (Amt == NVTBits) {
3104       Lo = MIRBuilder.buildConstant(NVT, 0);
3105       Hi = InL;
3106     } else {
3107       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
3108       auto OrLHS =
3109           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
3110       auto OrRHS = MIRBuilder.buildLShr(
3111           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3112       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3113     }
3114   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3115     if (Amt.ugt(VTBits)) {
3116       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3117     } else if (Amt.ugt(NVTBits)) {
3118       Lo = MIRBuilder.buildLShr(NVT, InH,
3119                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3120       Hi = MIRBuilder.buildConstant(NVT, 0);
3121     } else if (Amt == NVTBits) {
3122       Lo = InH;
3123       Hi = MIRBuilder.buildConstant(NVT, 0);
3124     } else {
3125       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3126 
3127       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3128       auto OrRHS = MIRBuilder.buildShl(
3129           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3130 
3131       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3132       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
3133     }
3134   } else {
3135     if (Amt.ugt(VTBits)) {
3136       Hi = Lo = MIRBuilder.buildAShr(
3137           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3138     } else if (Amt.ugt(NVTBits)) {
3139       Lo = MIRBuilder.buildAShr(NVT, InH,
3140                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3141       Hi = MIRBuilder.buildAShr(NVT, InH,
3142                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3143     } else if (Amt == NVTBits) {
3144       Lo = InH;
3145       Hi = MIRBuilder.buildAShr(NVT, InH,
3146                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3147     } else {
3148       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3149 
3150       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3151       auto OrRHS = MIRBuilder.buildShl(
3152           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3153 
3154       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3155       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
3156     }
3157   }
3158 
3159   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
3160   MI.eraseFromParent();
3161 
3162   return Legalized;
3163 }
3164 
3165 // TODO: Optimize if constant shift amount.
3166 LegalizerHelper::LegalizeResult
3167 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
3168                                    LLT RequestedTy) {
3169   if (TypeIdx == 1) {
3170     Observer.changingInstr(MI);
3171     narrowScalarSrc(MI, RequestedTy, 2);
3172     Observer.changedInstr(MI);
3173     return Legalized;
3174   }
3175 
3176   Register DstReg = MI.getOperand(0).getReg();
3177   LLT DstTy = MRI.getType(DstReg);
3178   if (DstTy.isVector())
3179     return UnableToLegalize;
3180 
3181   Register Amt = MI.getOperand(2).getReg();
3182   LLT ShiftAmtTy = MRI.getType(Amt);
3183   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
3184   if (DstEltSize % 2 != 0)
3185     return UnableToLegalize;
3186 
3187   // Ignore the input type. We can only go to exactly half the size of the
3188   // input. If that isn't small enough, the resulting pieces will be further
3189   // legalized.
3190   const unsigned NewBitSize = DstEltSize / 2;
3191   const LLT HalfTy = LLT::scalar(NewBitSize);
3192   const LLT CondTy = LLT::scalar(1);
3193 
3194   if (const MachineInstr *KShiftAmt =
3195           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
3196     return narrowScalarShiftByConstant(
3197         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
3198   }
3199 
3200   // TODO: Expand with known bits.
3201 
3202   // Handle the fully general expansion by an unknown amount.
3203   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
3204 
3205   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3206   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3207   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3208 
3209   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
3210   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
3211 
3212   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
3213   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
3214   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
3215 
3216   Register ResultRegs[2];
3217   switch (MI.getOpcode()) {
3218   case TargetOpcode::G_SHL: {
3219     // Short: ShAmt < NewBitSize
3220     auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt);
3221 
3222     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
3223     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt);
3224     auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3225 
3226     // Long: ShAmt >= NewBitSize
3227     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
3228     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
3229 
3230     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
3231     auto Hi = MIRBuilder.buildSelect(
3232         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
3233 
3234     ResultRegs[0] = Lo.getReg(0);
3235     ResultRegs[1] = Hi.getReg(0);
3236     break;
3237   }
3238   case TargetOpcode::G_LSHR:
3239   case TargetOpcode::G_ASHR: {
3240     // Short: ShAmt < NewBitSize
3241     auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt});
3242 
3243     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt);
3244     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
3245     auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3246 
3247     // Long: ShAmt >= NewBitSize
3248     MachineInstrBuilder HiL;
3249     if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3250       HiL = MIRBuilder.buildConstant(HalfTy, 0);            // Hi part is zero.
3251     } else {
3252       auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1);
3253       HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt);    // Sign of Hi part.
3254     }
3255     auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy},
3256                                      {InH, AmtExcess});     // Lo from Hi part.
3257 
3258     auto Lo = MIRBuilder.buildSelect(
3259         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
3260 
3261     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
3262 
3263     ResultRegs[0] = Lo.getReg(0);
3264     ResultRegs[1] = Hi.getReg(0);
3265     break;
3266   }
3267   default:
3268     llvm_unreachable("not a shift");
3269   }
3270 
3271   MIRBuilder.buildMerge(DstReg, ResultRegs);
3272   MI.eraseFromParent();
3273   return Legalized;
3274 }
3275 
3276 LegalizerHelper::LegalizeResult
3277 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
3278                                        LLT MoreTy) {
3279   assert(TypeIdx == 0 && "Expecting only Idx 0");
3280 
3281   Observer.changingInstr(MI);
3282   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
3283     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
3284     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
3285     moreElementsVectorSrc(MI, MoreTy, I);
3286   }
3287 
3288   MachineBasicBlock &MBB = *MI.getParent();
3289   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
3290   moreElementsVectorDst(MI, MoreTy, 0);
3291   Observer.changedInstr(MI);
3292   return Legalized;
3293 }
3294 
3295 LegalizerHelper::LegalizeResult
3296 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
3297                                     LLT MoreTy) {
3298   MIRBuilder.setInstr(MI);
3299   unsigned Opc = MI.getOpcode();
3300   switch (Opc) {
3301   case TargetOpcode::G_IMPLICIT_DEF:
3302   case TargetOpcode::G_LOAD: {
3303     if (TypeIdx != 0)
3304       return UnableToLegalize;
3305     Observer.changingInstr(MI);
3306     moreElementsVectorDst(MI, MoreTy, 0);
3307     Observer.changedInstr(MI);
3308     return Legalized;
3309   }
3310   case TargetOpcode::G_STORE:
3311     if (TypeIdx != 0)
3312       return UnableToLegalize;
3313     Observer.changingInstr(MI);
3314     moreElementsVectorSrc(MI, MoreTy, 0);
3315     Observer.changedInstr(MI);
3316     return Legalized;
3317   case TargetOpcode::G_AND:
3318   case TargetOpcode::G_OR:
3319   case TargetOpcode::G_XOR:
3320   case TargetOpcode::G_SMIN:
3321   case TargetOpcode::G_SMAX:
3322   case TargetOpcode::G_UMIN:
3323   case TargetOpcode::G_UMAX:
3324   case TargetOpcode::G_FMINNUM:
3325   case TargetOpcode::G_FMAXNUM:
3326   case TargetOpcode::G_FMINNUM_IEEE:
3327   case TargetOpcode::G_FMAXNUM_IEEE:
3328   case TargetOpcode::G_FMINIMUM:
3329   case TargetOpcode::G_FMAXIMUM: {
3330     Observer.changingInstr(MI);
3331     moreElementsVectorSrc(MI, MoreTy, 1);
3332     moreElementsVectorSrc(MI, MoreTy, 2);
3333     moreElementsVectorDst(MI, MoreTy, 0);
3334     Observer.changedInstr(MI);
3335     return Legalized;
3336   }
3337   case TargetOpcode::G_EXTRACT:
3338     if (TypeIdx != 1)
3339       return UnableToLegalize;
3340     Observer.changingInstr(MI);
3341     moreElementsVectorSrc(MI, MoreTy, 1);
3342     Observer.changedInstr(MI);
3343     return Legalized;
3344   case TargetOpcode::G_INSERT:
3345     if (TypeIdx != 0)
3346       return UnableToLegalize;
3347     Observer.changingInstr(MI);
3348     moreElementsVectorSrc(MI, MoreTy, 1);
3349     moreElementsVectorDst(MI, MoreTy, 0);
3350     Observer.changedInstr(MI);
3351     return Legalized;
3352   case TargetOpcode::G_SELECT:
3353     if (TypeIdx != 0)
3354       return UnableToLegalize;
3355     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
3356       return UnableToLegalize;
3357 
3358     Observer.changingInstr(MI);
3359     moreElementsVectorSrc(MI, MoreTy, 2);
3360     moreElementsVectorSrc(MI, MoreTy, 3);
3361     moreElementsVectorDst(MI, MoreTy, 0);
3362     Observer.changedInstr(MI);
3363     return Legalized;
3364   case TargetOpcode::G_UNMERGE_VALUES: {
3365     if (TypeIdx != 1)
3366       return UnableToLegalize;
3367 
3368     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
3369     int NumDst = MI.getNumOperands() - 1;
3370     moreElementsVectorSrc(MI, MoreTy, NumDst);
3371 
3372     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
3373     for (int I = 0; I != NumDst; ++I)
3374       MIB.addDef(MI.getOperand(I).getReg());
3375 
3376     int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits();
3377     for (int I = NumDst; I != NewNumDst; ++I)
3378       MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
3379 
3380     MIB.addUse(MI.getOperand(NumDst).getReg());
3381     MI.eraseFromParent();
3382     return Legalized;
3383   }
3384   case TargetOpcode::G_PHI:
3385     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
3386   default:
3387     return UnableToLegalize;
3388   }
3389 }
3390 
3391 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
3392                                         ArrayRef<Register> Src1Regs,
3393                                         ArrayRef<Register> Src2Regs,
3394                                         LLT NarrowTy) {
3395   MachineIRBuilder &B = MIRBuilder;
3396   unsigned SrcParts = Src1Regs.size();
3397   unsigned DstParts = DstRegs.size();
3398 
3399   unsigned DstIdx = 0; // Low bits of the result.
3400   Register FactorSum =
3401       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
3402   DstRegs[DstIdx] = FactorSum;
3403 
3404   unsigned CarrySumPrevDstIdx;
3405   SmallVector<Register, 4> Factors;
3406 
3407   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
3408     // Collect low parts of muls for DstIdx.
3409     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
3410          i <= std::min(DstIdx, SrcParts - 1); ++i) {
3411       MachineInstrBuilder Mul =
3412           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
3413       Factors.push_back(Mul.getReg(0));
3414     }
3415     // Collect high parts of muls from previous DstIdx.
3416     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
3417          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
3418       MachineInstrBuilder Umulh =
3419           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
3420       Factors.push_back(Umulh.getReg(0));
3421     }
3422     // Add CarrySum from additions calculated for previous DstIdx.
3423     if (DstIdx != 1) {
3424       Factors.push_back(CarrySumPrevDstIdx);
3425     }
3426 
3427     Register CarrySum;
3428     // Add all factors and accumulate all carries into CarrySum.
3429     if (DstIdx != DstParts - 1) {
3430       MachineInstrBuilder Uaddo =
3431           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
3432       FactorSum = Uaddo.getReg(0);
3433       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
3434       for (unsigned i = 2; i < Factors.size(); ++i) {
3435         MachineInstrBuilder Uaddo =
3436             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
3437         FactorSum = Uaddo.getReg(0);
3438         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
3439         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
3440       }
3441     } else {
3442       // Since value for the next index is not calculated, neither is CarrySum.
3443       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
3444       for (unsigned i = 2; i < Factors.size(); ++i)
3445         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
3446     }
3447 
3448     CarrySumPrevDstIdx = CarrySum;
3449     DstRegs[DstIdx] = FactorSum;
3450     Factors.clear();
3451   }
3452 }
3453 
3454 LegalizerHelper::LegalizeResult
3455 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
3456   Register DstReg = MI.getOperand(0).getReg();
3457   Register Src1 = MI.getOperand(1).getReg();
3458   Register Src2 = MI.getOperand(2).getReg();
3459 
3460   LLT Ty = MRI.getType(DstReg);
3461   if (Ty.isVector())
3462     return UnableToLegalize;
3463 
3464   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
3465   unsigned DstSize = Ty.getSizeInBits();
3466   unsigned NarrowSize = NarrowTy.getSizeInBits();
3467   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
3468     return UnableToLegalize;
3469 
3470   unsigned NumDstParts = DstSize / NarrowSize;
3471   unsigned NumSrcParts = SrcSize / NarrowSize;
3472   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
3473   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
3474 
3475   SmallVector<Register, 2> Src1Parts, Src2Parts, DstTmpRegs;
3476   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
3477   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
3478   DstTmpRegs.resize(DstTmpParts);
3479   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
3480 
3481   // Take only high half of registers if this is high mul.
3482   ArrayRef<Register> DstRegs(
3483       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
3484   MIRBuilder.buildMerge(DstReg, DstRegs);
3485   MI.eraseFromParent();
3486   return Legalized;
3487 }
3488 
3489 LegalizerHelper::LegalizeResult
3490 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
3491                                      LLT NarrowTy) {
3492   if (TypeIdx != 1)
3493     return UnableToLegalize;
3494 
3495   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3496 
3497   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
3498   // FIXME: add support for when SizeOp1 isn't an exact multiple of
3499   // NarrowSize.
3500   if (SizeOp1 % NarrowSize != 0)
3501     return UnableToLegalize;
3502   int NumParts = SizeOp1 / NarrowSize;
3503 
3504   SmallVector<Register, 2> SrcRegs, DstRegs;
3505   SmallVector<uint64_t, 2> Indexes;
3506   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3507 
3508   Register OpReg = MI.getOperand(0).getReg();
3509   uint64_t OpStart = MI.getOperand(2).getImm();
3510   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3511   for (int i = 0; i < NumParts; ++i) {
3512     unsigned SrcStart = i * NarrowSize;
3513 
3514     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
3515       // No part of the extract uses this subregister, ignore it.
3516       continue;
3517     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3518       // The entire subregister is extracted, forward the value.
3519       DstRegs.push_back(SrcRegs[i]);
3520       continue;
3521     }
3522 
3523     // OpSegStart is where this destination segment would start in OpReg if it
3524     // extended infinitely in both directions.
3525     int64_t ExtractOffset;
3526     uint64_t SegSize;
3527     if (OpStart < SrcStart) {
3528       ExtractOffset = 0;
3529       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
3530     } else {
3531       ExtractOffset = OpStart - SrcStart;
3532       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
3533     }
3534 
3535     Register SegReg = SrcRegs[i];
3536     if (ExtractOffset != 0 || SegSize != NarrowSize) {
3537       // A genuine extract is needed.
3538       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3539       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
3540     }
3541 
3542     DstRegs.push_back(SegReg);
3543   }
3544 
3545   Register DstReg = MI.getOperand(0).getReg();
3546   if(MRI.getType(DstReg).isVector())
3547     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3548   else
3549     MIRBuilder.buildMerge(DstReg, DstRegs);
3550   MI.eraseFromParent();
3551   return Legalized;
3552 }
3553 
3554 LegalizerHelper::LegalizeResult
3555 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
3556                                     LLT NarrowTy) {
3557   // FIXME: Don't know how to handle secondary types yet.
3558   if (TypeIdx != 0)
3559     return UnableToLegalize;
3560 
3561   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
3562   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3563 
3564   // FIXME: add support for when SizeOp0 isn't an exact multiple of
3565   // NarrowSize.
3566   if (SizeOp0 % NarrowSize != 0)
3567     return UnableToLegalize;
3568 
3569   int NumParts = SizeOp0 / NarrowSize;
3570 
3571   SmallVector<Register, 2> SrcRegs, DstRegs;
3572   SmallVector<uint64_t, 2> Indexes;
3573   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3574 
3575   Register OpReg = MI.getOperand(2).getReg();
3576   uint64_t OpStart = MI.getOperand(3).getImm();
3577   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3578   for (int i = 0; i < NumParts; ++i) {
3579     unsigned DstStart = i * NarrowSize;
3580 
3581     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
3582       // No part of the insert affects this subregister, forward the original.
3583       DstRegs.push_back(SrcRegs[i]);
3584       continue;
3585     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3586       // The entire subregister is defined by this insert, forward the new
3587       // value.
3588       DstRegs.push_back(OpReg);
3589       continue;
3590     }
3591 
3592     // OpSegStart is where this destination segment would start in OpReg if it
3593     // extended infinitely in both directions.
3594     int64_t ExtractOffset, InsertOffset;
3595     uint64_t SegSize;
3596     if (OpStart < DstStart) {
3597       InsertOffset = 0;
3598       ExtractOffset = DstStart - OpStart;
3599       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
3600     } else {
3601       InsertOffset = OpStart - DstStart;
3602       ExtractOffset = 0;
3603       SegSize =
3604         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
3605     }
3606 
3607     Register SegReg = OpReg;
3608     if (ExtractOffset != 0 || SegSize != OpSize) {
3609       // A genuine extract is needed.
3610       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3611       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
3612     }
3613 
3614     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
3615     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
3616     DstRegs.push_back(DstReg);
3617   }
3618 
3619   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
3620   Register DstReg = MI.getOperand(0).getReg();
3621   if(MRI.getType(DstReg).isVector())
3622     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3623   else
3624     MIRBuilder.buildMerge(DstReg, DstRegs);
3625   MI.eraseFromParent();
3626   return Legalized;
3627 }
3628 
3629 LegalizerHelper::LegalizeResult
3630 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
3631                                    LLT NarrowTy) {
3632   Register DstReg = MI.getOperand(0).getReg();
3633   LLT DstTy = MRI.getType(DstReg);
3634 
3635   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
3636 
3637   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3638   SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
3639   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3640   LLT LeftoverTy;
3641   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
3642                     Src0Regs, Src0LeftoverRegs))
3643     return UnableToLegalize;
3644 
3645   LLT Unused;
3646   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
3647                     Src1Regs, Src1LeftoverRegs))
3648     llvm_unreachable("inconsistent extractParts result");
3649 
3650   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3651     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
3652                                         {Src0Regs[I], Src1Regs[I]});
3653     DstRegs.push_back(Inst->getOperand(0).getReg());
3654   }
3655 
3656   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3657     auto Inst = MIRBuilder.buildInstr(
3658       MI.getOpcode(),
3659       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
3660     DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
3661   }
3662 
3663   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3664               LeftoverTy, DstLeftoverRegs);
3665 
3666   MI.eraseFromParent();
3667   return Legalized;
3668 }
3669 
3670 LegalizerHelper::LegalizeResult
3671 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
3672                                     LLT NarrowTy) {
3673   if (TypeIdx != 0)
3674     return UnableToLegalize;
3675 
3676   Register CondReg = MI.getOperand(1).getReg();
3677   LLT CondTy = MRI.getType(CondReg);
3678   if (CondTy.isVector()) // TODO: Handle vselect
3679     return UnableToLegalize;
3680 
3681   Register DstReg = MI.getOperand(0).getReg();
3682   LLT DstTy = MRI.getType(DstReg);
3683 
3684   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3685   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3686   SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
3687   LLT LeftoverTy;
3688   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
3689                     Src1Regs, Src1LeftoverRegs))
3690     return UnableToLegalize;
3691 
3692   LLT Unused;
3693   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
3694                     Src2Regs, Src2LeftoverRegs))
3695     llvm_unreachable("inconsistent extractParts result");
3696 
3697   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3698     auto Select = MIRBuilder.buildSelect(NarrowTy,
3699                                          CondReg, Src1Regs[I], Src2Regs[I]);
3700     DstRegs.push_back(Select->getOperand(0).getReg());
3701   }
3702 
3703   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3704     auto Select = MIRBuilder.buildSelect(
3705       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
3706     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
3707   }
3708 
3709   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3710               LeftoverTy, DstLeftoverRegs);
3711 
3712   MI.eraseFromParent();
3713   return Legalized;
3714 }
3715 
3716 LegalizerHelper::LegalizeResult
3717 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3718   unsigned Opc = MI.getOpcode();
3719   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
3720   auto isSupported = [this](const LegalityQuery &Q) {
3721     auto QAction = LI.getAction(Q).Action;
3722     return QAction == Legal || QAction == Libcall || QAction == Custom;
3723   };
3724   switch (Opc) {
3725   default:
3726     return UnableToLegalize;
3727   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
3728     // This trivially expands to CTLZ.
3729     Observer.changingInstr(MI);
3730     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
3731     Observer.changedInstr(MI);
3732     return Legalized;
3733   }
3734   case TargetOpcode::G_CTLZ: {
3735     Register SrcReg = MI.getOperand(1).getReg();
3736     unsigned Len = Ty.getSizeInBits();
3737     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
3738       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
3739       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
3740                                              {Ty}, {SrcReg});
3741       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3742       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3743       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3744                                           SrcReg, MIBZero);
3745       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3746                              MIBCtlzZU);
3747       MI.eraseFromParent();
3748       return Legalized;
3749     }
3750     // for now, we do this:
3751     // NewLen = NextPowerOf2(Len);
3752     // x = x | (x >> 1);
3753     // x = x | (x >> 2);
3754     // ...
3755     // x = x | (x >>16);
3756     // x = x | (x >>32); // for 64-bit input
3757     // Upto NewLen/2
3758     // return Len - popcount(x);
3759     //
3760     // Ref: "Hacker's Delight" by Henry Warren
3761     Register Op = SrcReg;
3762     unsigned NewLen = PowerOf2Ceil(Len);
3763     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
3764       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
3765       auto MIBOp = MIRBuilder.buildInstr(
3766           TargetOpcode::G_OR, {Ty},
3767           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
3768                                      {Op, MIBShiftAmt})});
3769       Op = MIBOp->getOperand(0).getReg();
3770     }
3771     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
3772     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3773                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
3774     MI.eraseFromParent();
3775     return Legalized;
3776   }
3777   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
3778     // This trivially expands to CTTZ.
3779     Observer.changingInstr(MI);
3780     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
3781     Observer.changedInstr(MI);
3782     return Legalized;
3783   }
3784   case TargetOpcode::G_CTTZ: {
3785     Register SrcReg = MI.getOperand(1).getReg();
3786     unsigned Len = Ty.getSizeInBits();
3787     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
3788       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
3789       // zero.
3790       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
3791                                              {Ty}, {SrcReg});
3792       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3793       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3794       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3795                                           SrcReg, MIBZero);
3796       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3797                              MIBCttzZU);
3798       MI.eraseFromParent();
3799       return Legalized;
3800     }
3801     // for now, we use: { return popcount(~x & (x - 1)); }
3802     // unless the target has ctlz but not ctpop, in which case we use:
3803     // { return 32 - nlz(~x & (x-1)); }
3804     // Ref: "Hacker's Delight" by Henry Warren
3805     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
3806     auto MIBNot =
3807         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
3808     auto MIBTmp = MIRBuilder.buildInstr(
3809         TargetOpcode::G_AND, {Ty},
3810         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
3811                                        {SrcReg, MIBCstNeg1})});
3812     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
3813         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
3814       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
3815       MIRBuilder.buildInstr(
3816           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3817           {MIBCstLen,
3818            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
3819       MI.eraseFromParent();
3820       return Legalized;
3821     }
3822     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
3823     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3824     return Legalized;
3825   }
3826   }
3827 }
3828 
3829 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
3830 // representation.
3831 LegalizerHelper::LegalizeResult
3832 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
3833   Register Dst = MI.getOperand(0).getReg();
3834   Register Src = MI.getOperand(1).getReg();
3835   const LLT S64 = LLT::scalar(64);
3836   const LLT S32 = LLT::scalar(32);
3837   const LLT S1 = LLT::scalar(1);
3838 
3839   assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
3840 
3841   // unsigned cul2f(ulong u) {
3842   //   uint lz = clz(u);
3843   //   uint e = (u != 0) ? 127U + 63U - lz : 0;
3844   //   u = (u << lz) & 0x7fffffffffffffffUL;
3845   //   ulong t = u & 0xffffffffffUL;
3846   //   uint v = (e << 23) | (uint)(u >> 40);
3847   //   uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
3848   //   return as_float(v + r);
3849   // }
3850 
3851   auto Zero32 = MIRBuilder.buildConstant(S32, 0);
3852   auto Zero64 = MIRBuilder.buildConstant(S64, 0);
3853 
3854   auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
3855 
3856   auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
3857   auto Sub = MIRBuilder.buildSub(S32, K, LZ);
3858 
3859   auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
3860   auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
3861 
3862   auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
3863   auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
3864 
3865   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
3866 
3867   auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
3868   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
3869 
3870   auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
3871   auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
3872   auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
3873 
3874   auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
3875   auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
3876   auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
3877   auto One = MIRBuilder.buildConstant(S32, 1);
3878 
3879   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
3880   auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
3881   auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
3882   MIRBuilder.buildAdd(Dst, V, R);
3883 
3884   return Legalized;
3885 }
3886 
3887 LegalizerHelper::LegalizeResult
3888 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3889   Register Dst = MI.getOperand(0).getReg();
3890   Register Src = MI.getOperand(1).getReg();
3891   LLT DstTy = MRI.getType(Dst);
3892   LLT SrcTy = MRI.getType(Src);
3893 
3894   if (SrcTy == LLT::scalar(1)) {
3895     auto True = MIRBuilder.buildFConstant(DstTy, 1.0);
3896     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
3897     MIRBuilder.buildSelect(Dst, Src, True, False);
3898     MI.eraseFromParent();
3899     return Legalized;
3900   }
3901 
3902   if (SrcTy != LLT::scalar(64))
3903     return UnableToLegalize;
3904 
3905   if (DstTy == LLT::scalar(32)) {
3906     // TODO: SelectionDAG has several alternative expansions to port which may
3907     // be more reasonble depending on the available instructions. If a target
3908     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
3909     // intermediate type, this is probably worse.
3910     return lowerU64ToF32BitOps(MI);
3911   }
3912 
3913   return UnableToLegalize;
3914 }
3915 
3916 LegalizerHelper::LegalizeResult
3917 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3918   Register Dst = MI.getOperand(0).getReg();
3919   Register Src = MI.getOperand(1).getReg();
3920   LLT DstTy = MRI.getType(Dst);
3921   LLT SrcTy = MRI.getType(Src);
3922 
3923   const LLT S64 = LLT::scalar(64);
3924   const LLT S32 = LLT::scalar(32);
3925   const LLT S1 = LLT::scalar(1);
3926 
3927   if (SrcTy == S1) {
3928     auto True = MIRBuilder.buildFConstant(DstTy, -1.0);
3929     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
3930     MIRBuilder.buildSelect(Dst, Src, True, False);
3931     MI.eraseFromParent();
3932     return Legalized;
3933   }
3934 
3935   if (SrcTy != S64)
3936     return UnableToLegalize;
3937 
3938   if (DstTy == S32) {
3939     // signed cl2f(long l) {
3940     //   long s = l >> 63;
3941     //   float r = cul2f((l + s) ^ s);
3942     //   return s ? -r : r;
3943     // }
3944     Register L = Src;
3945     auto SignBit = MIRBuilder.buildConstant(S64, 63);
3946     auto S = MIRBuilder.buildAShr(S64, L, SignBit);
3947 
3948     auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
3949     auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
3950     auto R = MIRBuilder.buildUITOFP(S32, Xor);
3951 
3952     auto RNeg = MIRBuilder.buildFNeg(S32, R);
3953     auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
3954                                             MIRBuilder.buildConstant(S64, 0));
3955     MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
3956     return Legalized;
3957   }
3958 
3959   return UnableToLegalize;
3960 }
3961 
3962 LegalizerHelper::LegalizeResult
3963 LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3964   Register Dst = MI.getOperand(0).getReg();
3965   Register Src = MI.getOperand(1).getReg();
3966   LLT DstTy = MRI.getType(Dst);
3967   LLT SrcTy = MRI.getType(Src);
3968   const LLT S64 = LLT::scalar(64);
3969   const LLT S32 = LLT::scalar(32);
3970 
3971   if (SrcTy != S64 && SrcTy != S32)
3972     return UnableToLegalize;
3973   if (DstTy != S32 && DstTy != S64)
3974     return UnableToLegalize;
3975 
3976   // FPTOSI gives same result as FPTOUI for positive signed integers.
3977   // FPTOUI needs to deal with fp values that convert to unsigned integers
3978   // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp.
3979 
3980   APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits());
3981   APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle()
3982                                                 : APFloat::IEEEdouble(),
3983                     APInt::getNullValue(SrcTy.getSizeInBits()));
3984   TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven);
3985 
3986   MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src);
3987 
3988   MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP);
3989   // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on
3990   // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1.
3991   MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold);
3992   MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub);
3993   MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt);
3994   MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit);
3995 
3996   MachineInstrBuilder FCMP =
3997       MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, DstTy, Src, Threshold);
3998   MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res);
3999 
4000   MI.eraseFromParent();
4001   return Legalized;
4002 }
4003 
4004 static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
4005   switch (Opc) {
4006   case TargetOpcode::G_SMIN:
4007     return CmpInst::ICMP_SLT;
4008   case TargetOpcode::G_SMAX:
4009     return CmpInst::ICMP_SGT;
4010   case TargetOpcode::G_UMIN:
4011     return CmpInst::ICMP_ULT;
4012   case TargetOpcode::G_UMAX:
4013     return CmpInst::ICMP_UGT;
4014   default:
4015     llvm_unreachable("not in integer min/max");
4016   }
4017 }
4018 
4019 LegalizerHelper::LegalizeResult
4020 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4021   Register Dst = MI.getOperand(0).getReg();
4022   Register Src0 = MI.getOperand(1).getReg();
4023   Register Src1 = MI.getOperand(2).getReg();
4024 
4025   const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
4026   LLT CmpType = MRI.getType(Dst).changeElementSize(1);
4027 
4028   auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
4029   MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
4030 
4031   MI.eraseFromParent();
4032   return Legalized;
4033 }
4034 
4035 LegalizerHelper::LegalizeResult
4036 LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4037   Register Dst = MI.getOperand(0).getReg();
4038   Register Src0 = MI.getOperand(1).getReg();
4039   Register Src1 = MI.getOperand(2).getReg();
4040 
4041   const LLT Src0Ty = MRI.getType(Src0);
4042   const LLT Src1Ty = MRI.getType(Src1);
4043 
4044   const int Src0Size = Src0Ty.getScalarSizeInBits();
4045   const int Src1Size = Src1Ty.getScalarSizeInBits();
4046 
4047   auto SignBitMask = MIRBuilder.buildConstant(
4048     Src0Ty, APInt::getSignMask(Src0Size));
4049 
4050   auto NotSignBitMask = MIRBuilder.buildConstant(
4051     Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
4052 
4053   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
4054   MachineInstr *Or;
4055 
4056   if (Src0Ty == Src1Ty) {
4057     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
4058     Or = MIRBuilder.buildOr(Dst, And0, And1);
4059   } else if (Src0Size > Src1Size) {
4060     auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
4061     auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
4062     auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
4063     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
4064     Or = MIRBuilder.buildOr(Dst, And0, And1);
4065   } else {
4066     auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
4067     auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
4068     auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
4069     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
4070     Or = MIRBuilder.buildOr(Dst, And0, And1);
4071   }
4072 
4073   // Be careful about setting nsz/nnan/ninf on every instruction, since the
4074   // constants are a nan and -0.0, but the final result should preserve
4075   // everything.
4076   if (unsigned Flags = MI.getFlags())
4077     Or->setFlags(Flags);
4078 
4079   MI.eraseFromParent();
4080   return Legalized;
4081 }
4082 
4083 LegalizerHelper::LegalizeResult
4084 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
4085   unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ?
4086     TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE;
4087 
4088   Register Dst = MI.getOperand(0).getReg();
4089   Register Src0 = MI.getOperand(1).getReg();
4090   Register Src1 = MI.getOperand(2).getReg();
4091   LLT Ty = MRI.getType(Dst);
4092 
4093   if (!MI.getFlag(MachineInstr::FmNoNans)) {
4094     // Insert canonicalizes if it's possible we need to quiet to get correct
4095     // sNaN behavior.
4096 
4097     // Note this must be done here, and not as an optimization combine in the
4098     // absence of a dedicate quiet-snan instruction as we're using an
4099     // omni-purpose G_FCANONICALIZE.
4100     if (!isKnownNeverSNaN(Src0, MRI))
4101       Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0);
4102 
4103     if (!isKnownNeverSNaN(Src1, MRI))
4104       Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0);
4105   }
4106 
4107   // If there are no nans, it's safe to simply replace this with the non-IEEE
4108   // version.
4109   MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags());
4110   MI.eraseFromParent();
4111   return Legalized;
4112 }
4113 
4114 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) {
4115   // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c
4116   Register DstReg = MI.getOperand(0).getReg();
4117   LLT Ty = MRI.getType(DstReg);
4118   unsigned Flags = MI.getFlags();
4119 
4120   auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2),
4121                                   Flags);
4122   MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags);
4123   MI.eraseFromParent();
4124   return Legalized;
4125 }
4126 
4127 LegalizerHelper::LegalizeResult
4128 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
4129   const unsigned NumDst = MI.getNumOperands() - 1;
4130   const Register SrcReg = MI.getOperand(NumDst).getReg();
4131   LLT SrcTy = MRI.getType(SrcReg);
4132 
4133   Register Dst0Reg = MI.getOperand(0).getReg();
4134   LLT DstTy = MRI.getType(Dst0Reg);
4135 
4136 
4137   // Expand scalarizing unmerge as bitcast to integer and shift.
4138   if (!DstTy.isVector() && SrcTy.isVector() &&
4139       SrcTy.getElementType() == DstTy) {
4140     LLT IntTy = LLT::scalar(SrcTy.getSizeInBits());
4141     Register Cast = MIRBuilder.buildBitcast(IntTy, SrcReg).getReg(0);
4142 
4143     MIRBuilder.buildTrunc(Dst0Reg, Cast);
4144 
4145     const unsigned DstSize = DstTy.getSizeInBits();
4146     unsigned Offset = DstSize;
4147     for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
4148       auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
4149       auto Shift = MIRBuilder.buildLShr(IntTy, Cast, ShiftAmt);
4150       MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
4151     }
4152 
4153     MI.eraseFromParent();
4154     return Legalized;
4155   }
4156 
4157   return UnableToLegalize;
4158 }
4159 
4160 LegalizerHelper::LegalizeResult
4161 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
4162   Register DstReg = MI.getOperand(0).getReg();
4163   Register Src0Reg = MI.getOperand(1).getReg();
4164   Register Src1Reg = MI.getOperand(2).getReg();
4165   LLT Src0Ty = MRI.getType(Src0Reg);
4166   LLT DstTy = MRI.getType(DstReg);
4167   LLT IdxTy = LLT::scalar(32);
4168 
4169   const Constant *ShufMask = MI.getOperand(3).getShuffleMask();
4170 
4171   SmallVector<int, 32> Mask;
4172   ShuffleVectorInst::getShuffleMask(ShufMask, Mask);
4173 
4174   if (DstTy.isScalar()) {
4175     if (Src0Ty.isVector())
4176       return UnableToLegalize;
4177 
4178     // This is just a SELECT.
4179     assert(Mask.size() == 1 && "Expected a single mask element");
4180     Register Val;
4181     if (Mask[0] < 0 || Mask[0] > 1)
4182       Val = MIRBuilder.buildUndef(DstTy).getReg(0);
4183     else
4184       Val = Mask[0] == 0 ? Src0Reg : Src1Reg;
4185     MIRBuilder.buildCopy(DstReg, Val);
4186     MI.eraseFromParent();
4187     return Legalized;
4188   }
4189 
4190   Register Undef;
4191   SmallVector<Register, 32> BuildVec;
4192   LLT EltTy = DstTy.getElementType();
4193 
4194   for (int Idx : Mask) {
4195     if (Idx < 0) {
4196       if (!Undef.isValid())
4197         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);
4198       BuildVec.push_back(Undef);
4199       continue;
4200     }
4201 
4202     if (Src0Ty.isScalar()) {
4203       BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
4204     } else {
4205       int NumElts = Src0Ty.getNumElements();
4206       Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
4207       int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
4208       auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
4209       auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
4210       BuildVec.push_back(Extract.getReg(0));
4211     }
4212   }
4213 
4214   MIRBuilder.buildBuildVector(DstReg, BuildVec);
4215   MI.eraseFromParent();
4216   return Legalized;
4217 }
4218 
4219 LegalizerHelper::LegalizeResult
4220 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) {
4221   Register Dst = MI.getOperand(0).getReg();
4222   Register AllocSize = MI.getOperand(1).getReg();
4223   unsigned Align = MI.getOperand(2).getImm();
4224 
4225   const auto &MF = *MI.getMF();
4226   const auto &TLI = *MF.getSubtarget().getTargetLowering();
4227 
4228   LLT PtrTy = MRI.getType(Dst);
4229   LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
4230 
4231   Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
4232   auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg);
4233   SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp);
4234 
4235   // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't
4236   // have to generate an extra instruction to negate the alloc and then use
4237   // G_PTR_ADD to add the negative offset.
4238   auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize);
4239   if (Align) {
4240     APInt AlignMask(IntPtrTy.getSizeInBits(), Align, true);
4241     AlignMask.negate();
4242     auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask);
4243     Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst);
4244   }
4245 
4246   SPTmp = MIRBuilder.buildCast(PtrTy, Alloc);
4247   MIRBuilder.buildCopy(SPReg, SPTmp);
4248   MIRBuilder.buildCopy(Dst, SPTmp);
4249 
4250   MI.eraseFromParent();
4251   return Legalized;
4252 }
4253 
4254 LegalizerHelper::LegalizeResult
4255 LegalizerHelper::lowerExtract(MachineInstr &MI) {
4256   Register Dst = MI.getOperand(0).getReg();
4257   Register Src = MI.getOperand(1).getReg();
4258   unsigned Offset = MI.getOperand(2).getImm();
4259 
4260   LLT DstTy = MRI.getType(Dst);
4261   LLT SrcTy = MRI.getType(Src);
4262 
4263   if (DstTy.isScalar() &&
4264       (SrcTy.isScalar() ||
4265        (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
4266     LLT SrcIntTy = SrcTy;
4267     if (!SrcTy.isScalar()) {
4268       SrcIntTy = LLT::scalar(SrcTy.getSizeInBits());
4269       Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0);
4270     }
4271 
4272     if (Offset == 0)
4273       MIRBuilder.buildTrunc(Dst, Src);
4274     else {
4275       auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset);
4276       auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt);
4277       MIRBuilder.buildTrunc(Dst, Shr);
4278     }
4279 
4280     MI.eraseFromParent();
4281     return Legalized;
4282   }
4283 
4284   return UnableToLegalize;
4285 }
4286 
4287 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
4288   Register Dst = MI.getOperand(0).getReg();
4289   Register Src = MI.getOperand(1).getReg();
4290   Register InsertSrc = MI.getOperand(2).getReg();
4291   uint64_t Offset = MI.getOperand(3).getImm();
4292 
4293   LLT DstTy = MRI.getType(Src);
4294   LLT InsertTy = MRI.getType(InsertSrc);
4295 
4296   if (InsertTy.isScalar() &&
4297       (DstTy.isScalar() ||
4298        (DstTy.isVector() && DstTy.getElementType() == InsertTy))) {
4299     LLT IntDstTy = DstTy;
4300     if (!DstTy.isScalar()) {
4301       IntDstTy = LLT::scalar(DstTy.getSizeInBits());
4302       Src = MIRBuilder.buildBitcast(IntDstTy, Src).getReg(0);
4303     }
4304 
4305     Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0);
4306     if (Offset != 0) {
4307       auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset);
4308       ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0);
4309     }
4310 
4311     APInt MaskVal = ~APInt::getBitsSet(DstTy.getSizeInBits(), Offset,
4312                                        InsertTy.getSizeInBits());
4313 
4314     auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal);
4315     auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);
4316     auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc);
4317 
4318     MIRBuilder.buildBitcast(Dst, Or);
4319     MI.eraseFromParent();
4320     return Legalized;
4321   }
4322 
4323   return UnableToLegalize;
4324 }
4325 
4326 LegalizerHelper::LegalizeResult
4327 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {
4328   Register Dst0 = MI.getOperand(0).getReg();
4329   Register Dst1 = MI.getOperand(1).getReg();
4330   Register LHS = MI.getOperand(2).getReg();
4331   Register RHS = MI.getOperand(3).getReg();
4332   const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO;
4333 
4334   LLT Ty = MRI.getType(Dst0);
4335   LLT BoolTy = MRI.getType(Dst1);
4336 
4337   if (IsAdd)
4338     MIRBuilder.buildAdd(Dst0, LHS, RHS);
4339   else
4340     MIRBuilder.buildSub(Dst0, LHS, RHS);
4341 
4342   // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
4343 
4344   auto Zero = MIRBuilder.buildConstant(Ty, 0);
4345 
4346   // For an addition, the result should be less than one of the operands (LHS)
4347   // if and only if the other operand (RHS) is negative, otherwise there will
4348   // be overflow.
4349   // For a subtraction, the result should be less than one of the operands
4350   // (LHS) if and only if the other operand (RHS) is (non-zero) positive,
4351   // otherwise there will be overflow.
4352   auto ResultLowerThanLHS =
4353       MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS);
4354   auto ConditionRHS = MIRBuilder.buildICmp(
4355       IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero);
4356 
4357   MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS);
4358   MI.eraseFromParent();
4359   return Legalized;
4360 }
4361 
4362 LegalizerHelper::LegalizeResult
4363 LegalizerHelper::lowerBswap(MachineInstr &MI) {
4364   Register Dst = MI.getOperand(0).getReg();
4365   Register Src = MI.getOperand(1).getReg();
4366   const LLT Ty = MRI.getType(Src);
4367   unsigned SizeInBytes = Ty.getSizeInBytes();
4368   unsigned BaseShiftAmt = (SizeInBytes - 1) * 8;
4369 
4370   // Swap most and least significant byte, set remaining bytes in Res to zero.
4371   auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt);
4372   auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt);
4373   auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
4374   auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft);
4375 
4376   // Set i-th high/low byte in Res to i-th low/high byte from Src.
4377   for (unsigned i = 1; i < SizeInBytes / 2; ++i) {
4378     // AND with Mask leaves byte i unchanged and sets remaining bytes to 0.
4379     APInt APMask(SizeInBytes * 8, 0xFF << (i * 8));
4380     auto Mask = MIRBuilder.buildConstant(Ty, APMask);
4381     auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i);
4382     // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt.
4383     auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask);
4384     auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt);
4385     Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft);
4386     // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask.
4387     auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
4388     auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask);
4389     Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight);
4390   }
4391   Res.getInstr()->getOperand(0).setReg(Dst);
4392 
4393   MI.eraseFromParent();
4394   return Legalized;
4395 }
4396 
4397 //{ (Src & Mask) >> N } | { (Src << N) & Mask }
4398 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B,
4399                                  MachineInstrBuilder Src, APInt Mask) {
4400   const LLT Ty = Dst.getLLTTy(*B.getMRI());
4401   MachineInstrBuilder C_N = B.buildConstant(Ty, N);
4402   MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask);
4403   auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N);
4404   auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0);
4405   return B.buildOr(Dst, LHS, RHS);
4406 }
4407 
4408 LegalizerHelper::LegalizeResult
4409 LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
4410   Register Dst = MI.getOperand(0).getReg();
4411   Register Src = MI.getOperand(1).getReg();
4412   const LLT Ty = MRI.getType(Src);
4413   unsigned Size = Ty.getSizeInBits();
4414 
4415   MachineInstrBuilder BSWAP =
4416       MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src});
4417 
4418   // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654
4419   //    [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4]
4420   // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0]
4421   MachineInstrBuilder Swap4 =
4422       SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0)));
4423 
4424   // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76
4425   //    [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2]
4426   // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC]
4427   MachineInstrBuilder Swap2 =
4428       SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC)));
4429 
4430   // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7
4431   //    [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1]
4432   // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA]
4433   SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA)));
4434 
4435   MI.eraseFromParent();
4436   return Legalized;
4437 }
4438