1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #include "llvm/CodeGen/TargetLowering.h"
22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/raw_ostream.h"
26 
27 #define DEBUG_TYPE "legalizer"
28 
29 using namespace llvm;
30 using namespace LegalizeActions;
31 
32 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
33 ///
34 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
35 /// with any leftover piece as type \p LeftoverTy
36 ///
37 /// Returns -1 in the first element of the pair if the breakdown is not
38 /// satisfiable.
39 static std::pair<int, int>
40 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
41   assert(!LeftoverTy.isValid() && "this is an out argument");
42 
43   unsigned Size = OrigTy.getSizeInBits();
44   unsigned NarrowSize = NarrowTy.getSizeInBits();
45   unsigned NumParts = Size / NarrowSize;
46   unsigned LeftoverSize = Size - NumParts * NarrowSize;
47   assert(Size > NarrowSize);
48 
49   if (LeftoverSize == 0)
50     return {NumParts, 0};
51 
52   if (NarrowTy.isVector()) {
53     unsigned EltSize = OrigTy.getScalarSizeInBits();
54     if (LeftoverSize % EltSize != 0)
55       return {-1, -1};
56     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
57   } else {
58     LeftoverTy = LLT::scalar(LeftoverSize);
59   }
60 
61   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
62   return std::make_pair(NumParts, NumLeftover);
63 }
64 
65 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
66                                  GISelChangeObserver &Observer,
67                                  MachineIRBuilder &Builder)
68     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
69       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
70   MIRBuilder.setMF(MF);
71   MIRBuilder.setChangeObserver(Observer);
72 }
73 
74 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
75                                  GISelChangeObserver &Observer,
76                                  MachineIRBuilder &B)
77     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
78   MIRBuilder.setMF(MF);
79   MIRBuilder.setChangeObserver(Observer);
80 }
81 LegalizerHelper::LegalizeResult
82 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
83   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
84 
85   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
86       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
87     return LI.legalizeIntrinsic(MI, MRI, MIRBuilder) ? Legalized
88                                                      : UnableToLegalize;
89   auto Step = LI.getAction(MI, MRI);
90   switch (Step.Action) {
91   case Legal:
92     LLVM_DEBUG(dbgs() << ".. Already legal\n");
93     return AlreadyLegal;
94   case Libcall:
95     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
96     return libcall(MI);
97   case NarrowScalar:
98     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
99     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
100   case WidenScalar:
101     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
102     return widenScalar(MI, Step.TypeIdx, Step.NewType);
103   case Lower:
104     LLVM_DEBUG(dbgs() << ".. Lower\n");
105     return lower(MI, Step.TypeIdx, Step.NewType);
106   case FewerElements:
107     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
108     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
109   case MoreElements:
110     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
111     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
112   case Custom:
113     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
114     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
115                                                             : UnableToLegalize;
116   default:
117     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
118     return UnableToLegalize;
119   }
120 }
121 
122 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
123                                    SmallVectorImpl<Register> &VRegs) {
124   for (int i = 0; i < NumParts; ++i)
125     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
126   MIRBuilder.buildUnmerge(VRegs, Reg);
127 }
128 
129 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
130                                    LLT MainTy, LLT &LeftoverTy,
131                                    SmallVectorImpl<Register> &VRegs,
132                                    SmallVectorImpl<Register> &LeftoverRegs) {
133   assert(!LeftoverTy.isValid() && "this is an out argument");
134 
135   unsigned RegSize = RegTy.getSizeInBits();
136   unsigned MainSize = MainTy.getSizeInBits();
137   unsigned NumParts = RegSize / MainSize;
138   unsigned LeftoverSize = RegSize - NumParts * MainSize;
139 
140   // Use an unmerge when possible.
141   if (LeftoverSize == 0) {
142     for (unsigned I = 0; I < NumParts; ++I)
143       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
144     MIRBuilder.buildUnmerge(VRegs, Reg);
145     return true;
146   }
147 
148   if (MainTy.isVector()) {
149     unsigned EltSize = MainTy.getScalarSizeInBits();
150     if (LeftoverSize % EltSize != 0)
151       return false;
152     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
153   } else {
154     LeftoverTy = LLT::scalar(LeftoverSize);
155   }
156 
157   // For irregular sizes, extract the individual parts.
158   for (unsigned I = 0; I != NumParts; ++I) {
159     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
160     VRegs.push_back(NewReg);
161     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
162   }
163 
164   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
165        Offset += LeftoverSize) {
166     Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
167     LeftoverRegs.push_back(NewReg);
168     MIRBuilder.buildExtract(NewReg, Reg, Offset);
169   }
170 
171   return true;
172 }
173 
174 void LegalizerHelper::insertParts(Register DstReg,
175                                   LLT ResultTy, LLT PartTy,
176                                   ArrayRef<Register> PartRegs,
177                                   LLT LeftoverTy,
178                                   ArrayRef<Register> LeftoverRegs) {
179   if (!LeftoverTy.isValid()) {
180     assert(LeftoverRegs.empty());
181 
182     if (!ResultTy.isVector()) {
183       MIRBuilder.buildMerge(DstReg, PartRegs);
184       return;
185     }
186 
187     if (PartTy.isVector())
188       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
189     else
190       MIRBuilder.buildBuildVector(DstReg, PartRegs);
191     return;
192   }
193 
194   unsigned PartSize = PartTy.getSizeInBits();
195   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
196 
197   Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
198   MIRBuilder.buildUndef(CurResultReg);
199 
200   unsigned Offset = 0;
201   for (Register PartReg : PartRegs) {
202     Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
203     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
204     CurResultReg = NewResultReg;
205     Offset += PartSize;
206   }
207 
208   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
209     // Use the original output register for the final insert to avoid a copy.
210     Register NewResultReg = (I + 1 == E) ?
211       DstReg : MRI.createGenericVirtualRegister(ResultTy);
212 
213     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
214     CurResultReg = NewResultReg;
215     Offset += LeftoverPartSize;
216   }
217 }
218 
219 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
220   switch (Opcode) {
221   case TargetOpcode::G_SDIV:
222     assert((Size == 32 || Size == 64) && "Unsupported size");
223     return Size == 64 ? RTLIB::SDIV_I64 : RTLIB::SDIV_I32;
224   case TargetOpcode::G_UDIV:
225     assert((Size == 32 || Size == 64) && "Unsupported size");
226     return Size == 64 ? RTLIB::UDIV_I64 : RTLIB::UDIV_I32;
227   case TargetOpcode::G_SREM:
228     assert((Size == 32 || Size == 64) && "Unsupported size");
229     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
230   case TargetOpcode::G_UREM:
231     assert((Size == 32 || Size == 64) && "Unsupported size");
232     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
233   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
234     assert(Size == 32 && "Unsupported size");
235     return RTLIB::CTLZ_I32;
236   case TargetOpcode::G_FADD:
237     assert((Size == 32 || Size == 64) && "Unsupported size");
238     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
239   case TargetOpcode::G_FSUB:
240     assert((Size == 32 || Size == 64) && "Unsupported size");
241     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
242   case TargetOpcode::G_FMUL:
243     assert((Size == 32 || Size == 64) && "Unsupported size");
244     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
245   case TargetOpcode::G_FDIV:
246     assert((Size == 32 || Size == 64) && "Unsupported size");
247     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
248   case TargetOpcode::G_FEXP:
249     assert((Size == 32 || Size == 64) && "Unsupported size");
250     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
251   case TargetOpcode::G_FEXP2:
252     assert((Size == 32 || Size == 64) && "Unsupported size");
253     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
254   case TargetOpcode::G_FREM:
255     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
256   case TargetOpcode::G_FPOW:
257     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
258   case TargetOpcode::G_FMA:
259     assert((Size == 32 || Size == 64) && "Unsupported size");
260     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
261   case TargetOpcode::G_FSIN:
262     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
263     return Size == 128 ? RTLIB::SIN_F128
264                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
265   case TargetOpcode::G_FCOS:
266     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
267     return Size == 128 ? RTLIB::COS_F128
268                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
269   case TargetOpcode::G_FLOG10:
270     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
271     return Size == 128 ? RTLIB::LOG10_F128
272                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
273   case TargetOpcode::G_FLOG:
274     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
275     return Size == 128 ? RTLIB::LOG_F128
276                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
277   case TargetOpcode::G_FLOG2:
278     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
279     return Size == 128 ? RTLIB::LOG2_F128
280                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
281   case TargetOpcode::G_FCEIL:
282     assert((Size == 32 || Size == 64) && "Unsupported size");
283     return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
284   case TargetOpcode::G_FFLOOR:
285     assert((Size == 32 || Size == 64) && "Unsupported size");
286     return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
287   }
288   llvm_unreachable("Unknown libcall function");
289 }
290 
291 LegalizerHelper::LegalizeResult
292 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
293                     const CallLowering::ArgInfo &Result,
294                     ArrayRef<CallLowering::ArgInfo> Args) {
295   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
296   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
297   const char *Name = TLI.getLibcallName(Libcall);
298 
299   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
300   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
301                      MachineOperand::CreateES(Name), Result, Args))
302     return LegalizerHelper::UnableToLegalize;
303 
304   return LegalizerHelper::Legalized;
305 }
306 
307 // Useful for libcalls where all operands have the same type.
308 static LegalizerHelper::LegalizeResult
309 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
310               Type *OpType) {
311   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
312 
313   SmallVector<CallLowering::ArgInfo, 3> Args;
314   for (unsigned i = 1; i < MI.getNumOperands(); i++)
315     Args.push_back({MI.getOperand(i).getReg(), OpType});
316   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
317                        Args);
318 }
319 
320 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
321                                        Type *FromType) {
322   auto ToMVT = MVT::getVT(ToType);
323   auto FromMVT = MVT::getVT(FromType);
324 
325   switch (Opcode) {
326   case TargetOpcode::G_FPEXT:
327     return RTLIB::getFPEXT(FromMVT, ToMVT);
328   case TargetOpcode::G_FPTRUNC:
329     return RTLIB::getFPROUND(FromMVT, ToMVT);
330   case TargetOpcode::G_FPTOSI:
331     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
332   case TargetOpcode::G_FPTOUI:
333     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
334   case TargetOpcode::G_SITOFP:
335     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
336   case TargetOpcode::G_UITOFP:
337     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
338   }
339   llvm_unreachable("Unsupported libcall function");
340 }
341 
342 static LegalizerHelper::LegalizeResult
343 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
344                   Type *FromType) {
345   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
346   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
347                        {{MI.getOperand(1).getReg(), FromType}});
348 }
349 
350 LegalizerHelper::LegalizeResult
351 LegalizerHelper::libcall(MachineInstr &MI) {
352   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
353   unsigned Size = LLTy.getSizeInBits();
354   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
355 
356   MIRBuilder.setInstr(MI);
357 
358   switch (MI.getOpcode()) {
359   default:
360     return UnableToLegalize;
361   case TargetOpcode::G_SDIV:
362   case TargetOpcode::G_UDIV:
363   case TargetOpcode::G_SREM:
364   case TargetOpcode::G_UREM:
365   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
366     Type *HLTy = IntegerType::get(Ctx, Size);
367     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
368     if (Status != Legalized)
369       return Status;
370     break;
371   }
372   case TargetOpcode::G_FADD:
373   case TargetOpcode::G_FSUB:
374   case TargetOpcode::G_FMUL:
375   case TargetOpcode::G_FDIV:
376   case TargetOpcode::G_FMA:
377   case TargetOpcode::G_FPOW:
378   case TargetOpcode::G_FREM:
379   case TargetOpcode::G_FCOS:
380   case TargetOpcode::G_FSIN:
381   case TargetOpcode::G_FLOG10:
382   case TargetOpcode::G_FLOG:
383   case TargetOpcode::G_FLOG2:
384   case TargetOpcode::G_FEXP:
385   case TargetOpcode::G_FEXP2:
386   case TargetOpcode::G_FCEIL:
387   case TargetOpcode::G_FFLOOR: {
388     if (Size > 64) {
389       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
390       return UnableToLegalize;
391     }
392     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
393     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
394     if (Status != Legalized)
395       return Status;
396     break;
397   }
398   case TargetOpcode::G_FPEXT: {
399     // FIXME: Support other floating point types (half, fp128 etc)
400     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
401     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
402     if (ToSize != 64 || FromSize != 32)
403       return UnableToLegalize;
404     LegalizeResult Status = conversionLibcall(
405         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
406     if (Status != Legalized)
407       return Status;
408     break;
409   }
410   case TargetOpcode::G_FPTRUNC: {
411     // FIXME: Support other floating point types (half, fp128 etc)
412     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
413     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
414     if (ToSize != 32 || FromSize != 64)
415       return UnableToLegalize;
416     LegalizeResult Status = conversionLibcall(
417         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
418     if (Status != Legalized)
419       return Status;
420     break;
421   }
422   case TargetOpcode::G_FPTOSI:
423   case TargetOpcode::G_FPTOUI: {
424     // FIXME: Support other types
425     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
426     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
427     if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
428       return UnableToLegalize;
429     LegalizeResult Status = conversionLibcall(
430         MI, MIRBuilder,
431         ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
432         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
433     if (Status != Legalized)
434       return Status;
435     break;
436   }
437   case TargetOpcode::G_SITOFP:
438   case TargetOpcode::G_UITOFP: {
439     // FIXME: Support other types
440     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
441     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
442     if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
443       return UnableToLegalize;
444     LegalizeResult Status = conversionLibcall(
445         MI, MIRBuilder,
446         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
447         FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
448     if (Status != Legalized)
449       return Status;
450     break;
451   }
452   }
453 
454   MI.eraseFromParent();
455   return Legalized;
456 }
457 
458 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
459                                                               unsigned TypeIdx,
460                                                               LLT NarrowTy) {
461   MIRBuilder.setInstr(MI);
462 
463   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
464   uint64_t NarrowSize = NarrowTy.getSizeInBits();
465 
466   switch (MI.getOpcode()) {
467   default:
468     return UnableToLegalize;
469   case TargetOpcode::G_IMPLICIT_DEF: {
470     // FIXME: add support for when SizeOp0 isn't an exact multiple of
471     // NarrowSize.
472     if (SizeOp0 % NarrowSize != 0)
473       return UnableToLegalize;
474     int NumParts = SizeOp0 / NarrowSize;
475 
476     SmallVector<Register, 2> DstRegs;
477     for (int i = 0; i < NumParts; ++i)
478       DstRegs.push_back(
479           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
480 
481     Register DstReg = MI.getOperand(0).getReg();
482     if(MRI.getType(DstReg).isVector())
483       MIRBuilder.buildBuildVector(DstReg, DstRegs);
484     else
485       MIRBuilder.buildMerge(DstReg, DstRegs);
486     MI.eraseFromParent();
487     return Legalized;
488   }
489   case TargetOpcode::G_CONSTANT: {
490     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
491     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
492     unsigned TotalSize = Ty.getSizeInBits();
493     unsigned NarrowSize = NarrowTy.getSizeInBits();
494     int NumParts = TotalSize / NarrowSize;
495 
496     SmallVector<Register, 4> PartRegs;
497     for (int I = 0; I != NumParts; ++I) {
498       unsigned Offset = I * NarrowSize;
499       auto K = MIRBuilder.buildConstant(NarrowTy,
500                                         Val.lshr(Offset).trunc(NarrowSize));
501       PartRegs.push_back(K.getReg(0));
502     }
503 
504     LLT LeftoverTy;
505     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
506     SmallVector<Register, 1> LeftoverRegs;
507     if (LeftoverBits != 0) {
508       LeftoverTy = LLT::scalar(LeftoverBits);
509       auto K = MIRBuilder.buildConstant(
510         LeftoverTy,
511         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
512       LeftoverRegs.push_back(K.getReg(0));
513     }
514 
515     insertParts(MI.getOperand(0).getReg(),
516                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
517 
518     MI.eraseFromParent();
519     return Legalized;
520   }
521   case TargetOpcode::G_ADD: {
522     // FIXME: add support for when SizeOp0 isn't an exact multiple of
523     // NarrowSize.
524     if (SizeOp0 % NarrowSize != 0)
525       return UnableToLegalize;
526     // Expand in terms of carry-setting/consuming G_ADDE instructions.
527     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
528 
529     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
530     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
531     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
532 
533     Register CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
534     MIRBuilder.buildConstant(CarryIn, 0);
535 
536     for (int i = 0; i < NumParts; ++i) {
537       Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
538       Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
539 
540       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
541                             Src2Regs[i], CarryIn);
542 
543       DstRegs.push_back(DstReg);
544       CarryIn = CarryOut;
545     }
546     Register DstReg = MI.getOperand(0).getReg();
547     if(MRI.getType(DstReg).isVector())
548       MIRBuilder.buildBuildVector(DstReg, DstRegs);
549     else
550       MIRBuilder.buildMerge(DstReg, DstRegs);
551     MI.eraseFromParent();
552     return Legalized;
553   }
554   case TargetOpcode::G_SUB: {
555     // FIXME: add support for when SizeOp0 isn't an exact multiple of
556     // NarrowSize.
557     if (SizeOp0 % NarrowSize != 0)
558       return UnableToLegalize;
559 
560     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
561 
562     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
563     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
564     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
565 
566     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
567     Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
568     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
569                           {Src1Regs[0], Src2Regs[0]});
570     DstRegs.push_back(DstReg);
571     Register BorrowIn = BorrowOut;
572     for (int i = 1; i < NumParts; ++i) {
573       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
574       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
575 
576       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
577                             {Src1Regs[i], Src2Regs[i], BorrowIn});
578 
579       DstRegs.push_back(DstReg);
580       BorrowIn = BorrowOut;
581     }
582     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
583     MI.eraseFromParent();
584     return Legalized;
585   }
586   case TargetOpcode::G_MUL:
587   case TargetOpcode::G_UMULH:
588     return narrowScalarMul(MI, NarrowTy);
589   case TargetOpcode::G_EXTRACT:
590     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
591   case TargetOpcode::G_INSERT:
592     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
593   case TargetOpcode::G_LOAD: {
594     const auto &MMO = **MI.memoperands_begin();
595     Register DstReg = MI.getOperand(0).getReg();
596     LLT DstTy = MRI.getType(DstReg);
597     if (DstTy.isVector())
598       return UnableToLegalize;
599 
600     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
601       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
602       auto &MMO = **MI.memoperands_begin();
603       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
604       MIRBuilder.buildAnyExt(DstReg, TmpReg);
605       MI.eraseFromParent();
606       return Legalized;
607     }
608 
609     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
610   }
611   case TargetOpcode::G_ZEXTLOAD:
612   case TargetOpcode::G_SEXTLOAD: {
613     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
614     Register DstReg = MI.getOperand(0).getReg();
615     Register PtrReg = MI.getOperand(1).getReg();
616 
617     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
618     auto &MMO = **MI.memoperands_begin();
619     if (MMO.getSizeInBits() == NarrowSize) {
620       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
621     } else {
622       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
623         : TargetOpcode::G_SEXTLOAD;
624       MIRBuilder.buildInstr(ExtLoad)
625         .addDef(TmpReg)
626         .addUse(PtrReg)
627         .addMemOperand(&MMO);
628     }
629 
630     if (ZExt)
631       MIRBuilder.buildZExt(DstReg, TmpReg);
632     else
633       MIRBuilder.buildSExt(DstReg, TmpReg);
634 
635     MI.eraseFromParent();
636     return Legalized;
637   }
638   case TargetOpcode::G_STORE: {
639     const auto &MMO = **MI.memoperands_begin();
640 
641     Register SrcReg = MI.getOperand(0).getReg();
642     LLT SrcTy = MRI.getType(SrcReg);
643     if (SrcTy.isVector())
644       return UnableToLegalize;
645 
646     int NumParts = SizeOp0 / NarrowSize;
647     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
648     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
649     if (SrcTy.isVector() && LeftoverBits != 0)
650       return UnableToLegalize;
651 
652     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
653       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
654       auto &MMO = **MI.memoperands_begin();
655       MIRBuilder.buildTrunc(TmpReg, SrcReg);
656       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
657       MI.eraseFromParent();
658       return Legalized;
659     }
660 
661     return reduceLoadStoreWidth(MI, 0, NarrowTy);
662   }
663   case TargetOpcode::G_SELECT:
664     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
665   case TargetOpcode::G_AND:
666   case TargetOpcode::G_OR:
667   case TargetOpcode::G_XOR: {
668     // Legalize bitwise operation:
669     // A = BinOp<Ty> B, C
670     // into:
671     // B1, ..., BN = G_UNMERGE_VALUES B
672     // C1, ..., CN = G_UNMERGE_VALUES C
673     // A1 = BinOp<Ty/N> B1, C2
674     // ...
675     // AN = BinOp<Ty/N> BN, CN
676     // A = G_MERGE_VALUES A1, ..., AN
677     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
678   }
679   case TargetOpcode::G_SHL:
680   case TargetOpcode::G_LSHR:
681   case TargetOpcode::G_ASHR:
682     return narrowScalarShift(MI, TypeIdx, NarrowTy);
683   case TargetOpcode::G_CTLZ:
684   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
685   case TargetOpcode::G_CTTZ:
686   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
687   case TargetOpcode::G_CTPOP:
688     if (TypeIdx != 0)
689       return UnableToLegalize; // TODO
690 
691     Observer.changingInstr(MI);
692     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
693     Observer.changedInstr(MI);
694     return Legalized;
695   case TargetOpcode::G_INTTOPTR:
696     if (TypeIdx != 1)
697       return UnableToLegalize;
698 
699     Observer.changingInstr(MI);
700     narrowScalarSrc(MI, NarrowTy, 1);
701     Observer.changedInstr(MI);
702     return Legalized;
703   case TargetOpcode::G_PTRTOINT:
704     if (TypeIdx != 0)
705       return UnableToLegalize;
706 
707     Observer.changingInstr(MI);
708     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
709     Observer.changedInstr(MI);
710     return Legalized;
711   case TargetOpcode::G_PHI: {
712     unsigned NumParts = SizeOp0 / NarrowSize;
713     SmallVector<Register, 2> DstRegs;
714     SmallVector<SmallVector<Register, 2>, 2> SrcRegs;
715     DstRegs.resize(NumParts);
716     SrcRegs.resize(MI.getNumOperands() / 2);
717     Observer.changingInstr(MI);
718     for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
719       MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
720       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
721       extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
722                    SrcRegs[i / 2]);
723     }
724     MachineBasicBlock &MBB = *MI.getParent();
725     MIRBuilder.setInsertPt(MBB, MI);
726     for (unsigned i = 0; i < NumParts; ++i) {
727       DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
728       MachineInstrBuilder MIB =
729           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
730       for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
731         MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
732     }
733     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
734     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
735     Observer.changedInstr(MI);
736     MI.eraseFromParent();
737     return Legalized;
738   }
739   }
740 }
741 
742 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
743                                      unsigned OpIdx, unsigned ExtOpcode) {
744   MachineOperand &MO = MI.getOperand(OpIdx);
745   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
746   MO.setReg(ExtB->getOperand(0).getReg());
747 }
748 
749 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
750                                       unsigned OpIdx) {
751   MachineOperand &MO = MI.getOperand(OpIdx);
752   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
753                                     {MO.getReg()});
754   MO.setReg(ExtB->getOperand(0).getReg());
755 }
756 
757 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
758                                      unsigned OpIdx, unsigned TruncOpcode) {
759   MachineOperand &MO = MI.getOperand(OpIdx);
760   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
761   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
762   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
763   MO.setReg(DstExt);
764 }
765 
766 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
767                                       unsigned OpIdx, unsigned ExtOpcode) {
768   MachineOperand &MO = MI.getOperand(OpIdx);
769   Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
770   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
771   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
772   MO.setReg(DstTrunc);
773 }
774 
775 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
776                                             unsigned OpIdx) {
777   MachineOperand &MO = MI.getOperand(OpIdx);
778   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
779   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
780   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
781   MO.setReg(DstExt);
782 }
783 
784 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
785                                             unsigned OpIdx) {
786   MachineOperand &MO = MI.getOperand(OpIdx);
787 
788   LLT OldTy = MRI.getType(MO.getReg());
789   unsigned OldElts = OldTy.getNumElements();
790   unsigned NewElts = MoreTy.getNumElements();
791 
792   unsigned NumParts = NewElts / OldElts;
793 
794   // Use concat_vectors if the result is a multiple of the number of elements.
795   if (NumParts * OldElts == NewElts) {
796     SmallVector<Register, 8> Parts;
797     Parts.push_back(MO.getReg());
798 
799     Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
800     for (unsigned I = 1; I != NumParts; ++I)
801       Parts.push_back(ImpDef);
802 
803     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
804     MO.setReg(Concat.getReg(0));
805     return;
806   }
807 
808   Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
809   Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
810   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
811   MO.setReg(MoreReg);
812 }
813 
814 LegalizerHelper::LegalizeResult
815 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
816                                         LLT WideTy) {
817   if (TypeIdx != 1)
818     return UnableToLegalize;
819 
820   Register DstReg = MI.getOperand(0).getReg();
821   LLT DstTy = MRI.getType(DstReg);
822   if (DstTy.isVector())
823     return UnableToLegalize;
824 
825   Register Src1 = MI.getOperand(1).getReg();
826   LLT SrcTy = MRI.getType(Src1);
827   int NumMerge = DstTy.getSizeInBits() / WideTy.getSizeInBits();
828 
829   // Try to turn this into a merge of merges if we can use the requested type as
830   // the source.
831 
832   // TODO: Pad with undef if DstTy > WideTy
833   if (NumMerge > 1 && WideTy.getSizeInBits() % SrcTy.getSizeInBits() == 0) {
834     int PartsPerMerge = WideTy.getSizeInBits() / SrcTy.getSizeInBits();
835     SmallVector<Register, 4> Parts;
836     SmallVector<Register, 4> SubMerges;
837 
838     for (int I = 0; I != NumMerge; ++I) {
839       for (int J = 0; J != PartsPerMerge; ++J)
840         Parts.push_back(MI.getOperand(I * PartsPerMerge + J + 1).getReg());
841 
842       auto SubMerge = MIRBuilder.buildMerge(WideTy, Parts);
843       SubMerges.push_back(SubMerge.getReg(0));
844       Parts.clear();
845     }
846 
847     MIRBuilder.buildMerge(DstReg, SubMerges);
848     MI.eraseFromParent();
849     return Legalized;
850   }
851 
852   unsigned NumOps = MI.getNumOperands();
853   unsigned NumSrc = MI.getNumOperands() - 1;
854   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
855 
856   Register ResultReg = MIRBuilder.buildZExt(DstTy, Src1).getReg(0);
857 
858   for (unsigned I = 2; I != NumOps; ++I) {
859     const unsigned Offset = (I - 1) * PartSize;
860 
861     Register SrcReg = MI.getOperand(I).getReg();
862     assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
863 
864     auto ZextInput = MIRBuilder.buildZExt(DstTy, SrcReg);
865 
866     Register NextResult = I + 1 == NumOps ? DstReg :
867       MRI.createGenericVirtualRegister(DstTy);
868 
869     auto ShiftAmt = MIRBuilder.buildConstant(DstTy, Offset);
870     auto Shl = MIRBuilder.buildShl(DstTy, ZextInput, ShiftAmt);
871     MIRBuilder.buildOr(NextResult, ResultReg, Shl);
872     ResultReg = NextResult;
873   }
874 
875   MI.eraseFromParent();
876   return Legalized;
877 }
878 
879 LegalizerHelper::LegalizeResult
880 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
881                                           LLT WideTy) {
882   if (TypeIdx != 0)
883     return UnableToLegalize;
884 
885   unsigned NumDst = MI.getNumOperands() - 1;
886   Register SrcReg = MI.getOperand(NumDst).getReg();
887   LLT SrcTy = MRI.getType(SrcReg);
888   if (!SrcTy.isScalar())
889     return UnableToLegalize;
890 
891   Register Dst0Reg = MI.getOperand(0).getReg();
892   LLT DstTy = MRI.getType(Dst0Reg);
893   if (!DstTy.isScalar())
894     return UnableToLegalize;
895 
896   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
897   LLT NewSrcTy = LLT::scalar(NewSrcSize);
898   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
899 
900   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
901 
902   for (unsigned I = 1; I != NumDst; ++I) {
903     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
904     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
905     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
906   }
907 
908   Observer.changingInstr(MI);
909 
910   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
911   for (unsigned I = 0; I != NumDst; ++I)
912     widenScalarDst(MI, WideTy, I);
913 
914   Observer.changedInstr(MI);
915 
916   return Legalized;
917 }
918 
919 LegalizerHelper::LegalizeResult
920 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
921                                     LLT WideTy) {
922   Register DstReg = MI.getOperand(0).getReg();
923   Register SrcReg = MI.getOperand(1).getReg();
924   LLT SrcTy = MRI.getType(SrcReg);
925 
926   LLT DstTy = MRI.getType(DstReg);
927   unsigned Offset = MI.getOperand(2).getImm();
928 
929   if (TypeIdx == 0) {
930     if (SrcTy.isVector() || DstTy.isVector())
931       return UnableToLegalize;
932 
933     SrcOp Src(SrcReg);
934     if (SrcTy.isPointer()) {
935       // Extracts from pointers can be handled only if they are really just
936       // simple integers.
937       const DataLayout &DL = MIRBuilder.getDataLayout();
938       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
939         return UnableToLegalize;
940 
941       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
942       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
943       SrcTy = SrcAsIntTy;
944     }
945 
946     if (DstTy.isPointer())
947       return UnableToLegalize;
948 
949     if (Offset == 0) {
950       // Avoid a shift in the degenerate case.
951       MIRBuilder.buildTrunc(DstReg,
952                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
953       MI.eraseFromParent();
954       return Legalized;
955     }
956 
957     // Do a shift in the source type.
958     LLT ShiftTy = SrcTy;
959     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
960       Src = MIRBuilder.buildAnyExt(WideTy, Src);
961       ShiftTy = WideTy;
962     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
963       return UnableToLegalize;
964 
965     auto LShr = MIRBuilder.buildLShr(
966       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
967     MIRBuilder.buildTrunc(DstReg, LShr);
968     MI.eraseFromParent();
969     return Legalized;
970   }
971 
972   if (SrcTy.isScalar()) {
973     Observer.changingInstr(MI);
974     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
975     Observer.changedInstr(MI);
976     return Legalized;
977   }
978 
979   if (!SrcTy.isVector())
980     return UnableToLegalize;
981 
982   if (DstTy != SrcTy.getElementType())
983     return UnableToLegalize;
984 
985   if (Offset % SrcTy.getScalarSizeInBits() != 0)
986     return UnableToLegalize;
987 
988   Observer.changingInstr(MI);
989   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
990 
991   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
992                           Offset);
993   widenScalarDst(MI, WideTy.getScalarType(), 0);
994   Observer.changedInstr(MI);
995   return Legalized;
996 }
997 
998 LegalizerHelper::LegalizeResult
999 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
1000                                    LLT WideTy) {
1001   if (TypeIdx != 0)
1002     return UnableToLegalize;
1003   Observer.changingInstr(MI);
1004   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1005   widenScalarDst(MI, WideTy);
1006   Observer.changedInstr(MI);
1007   return Legalized;
1008 }
1009 
1010 LegalizerHelper::LegalizeResult
1011 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
1012   MIRBuilder.setInstr(MI);
1013 
1014   switch (MI.getOpcode()) {
1015   default:
1016     return UnableToLegalize;
1017   case TargetOpcode::G_EXTRACT:
1018     return widenScalarExtract(MI, TypeIdx, WideTy);
1019   case TargetOpcode::G_INSERT:
1020     return widenScalarInsert(MI, TypeIdx, WideTy);
1021   case TargetOpcode::G_MERGE_VALUES:
1022     return widenScalarMergeValues(MI, TypeIdx, WideTy);
1023   case TargetOpcode::G_UNMERGE_VALUES:
1024     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
1025   case TargetOpcode::G_UADDO:
1026   case TargetOpcode::G_USUBO: {
1027     if (TypeIdx == 1)
1028       return UnableToLegalize; // TODO
1029     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1030                                          {MI.getOperand(2).getReg()});
1031     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1032                                          {MI.getOperand(3).getReg()});
1033     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1034                           ? TargetOpcode::G_ADD
1035                           : TargetOpcode::G_SUB;
1036     // Do the arithmetic in the larger type.
1037     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1038     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1039     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
1040     auto AndOp = MIRBuilder.buildInstr(
1041         TargetOpcode::G_AND, {WideTy},
1042         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
1043     // There is no overflow if the AndOp is the same as NewOp.
1044     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
1045                          AndOp);
1046     // Now trunc the NewOp to the original result.
1047     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
1048     MI.eraseFromParent();
1049     return Legalized;
1050   }
1051   case TargetOpcode::G_CTTZ:
1052   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1053   case TargetOpcode::G_CTLZ:
1054   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1055   case TargetOpcode::G_CTPOP: {
1056     if (TypeIdx == 0) {
1057       Observer.changingInstr(MI);
1058       widenScalarDst(MI, WideTy, 0);
1059       Observer.changedInstr(MI);
1060       return Legalized;
1061     }
1062 
1063     Register SrcReg = MI.getOperand(1).getReg();
1064 
1065     // First ZEXT the input.
1066     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1067     LLT CurTy = MRI.getType(SrcReg);
1068     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1069       // The count is the same in the larger type except if the original
1070       // value was zero.  This can be handled by setting the bit just off
1071       // the top of the original type.
1072       auto TopBit =
1073           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1074       MIBSrc = MIRBuilder.buildOr(
1075         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1076     }
1077 
1078     // Perform the operation at the larger size.
1079     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1080     // This is already the correct result for CTPOP and CTTZs
1081     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1082         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1083       // The correct result is NewOp - (Difference in widety and current ty).
1084       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1085       MIBNewOp = MIRBuilder.buildInstr(
1086           TargetOpcode::G_SUB, {WideTy},
1087           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1088     }
1089 
1090     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1091     MI.eraseFromParent();
1092     return Legalized;
1093   }
1094   case TargetOpcode::G_BSWAP: {
1095     Observer.changingInstr(MI);
1096     Register DstReg = MI.getOperand(0).getReg();
1097 
1098     Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1099     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1100     Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1101     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1102 
1103     MI.getOperand(0).setReg(DstExt);
1104 
1105     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1106 
1107     LLT Ty = MRI.getType(DstReg);
1108     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1109     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1110     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1111       .addDef(ShrReg)
1112       .addUse(DstExt)
1113       .addUse(ShiftAmtReg);
1114 
1115     MIRBuilder.buildTrunc(DstReg, ShrReg);
1116     Observer.changedInstr(MI);
1117     return Legalized;
1118   }
1119   case TargetOpcode::G_ADD:
1120   case TargetOpcode::G_AND:
1121   case TargetOpcode::G_MUL:
1122   case TargetOpcode::G_OR:
1123   case TargetOpcode::G_XOR:
1124   case TargetOpcode::G_SUB:
1125     // Perform operation at larger width (any extension is fines here, high bits
1126     // don't affect the result) and then truncate the result back to the
1127     // original type.
1128     Observer.changingInstr(MI);
1129     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1130     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1131     widenScalarDst(MI, WideTy);
1132     Observer.changedInstr(MI);
1133     return Legalized;
1134 
1135   case TargetOpcode::G_SHL:
1136     Observer.changingInstr(MI);
1137 
1138     if (TypeIdx == 0) {
1139       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1140       widenScalarDst(MI, WideTy);
1141     } else {
1142       assert(TypeIdx == 1);
1143       // The "number of bits to shift" operand must preserve its value as an
1144       // unsigned integer:
1145       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1146     }
1147 
1148     Observer.changedInstr(MI);
1149     return Legalized;
1150 
1151   case TargetOpcode::G_SDIV:
1152   case TargetOpcode::G_SREM:
1153   case TargetOpcode::G_SMIN:
1154   case TargetOpcode::G_SMAX:
1155     Observer.changingInstr(MI);
1156     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1157     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1158     widenScalarDst(MI, WideTy);
1159     Observer.changedInstr(MI);
1160     return Legalized;
1161 
1162   case TargetOpcode::G_ASHR:
1163   case TargetOpcode::G_LSHR:
1164     Observer.changingInstr(MI);
1165 
1166     if (TypeIdx == 0) {
1167       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1168         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1169 
1170       widenScalarSrc(MI, WideTy, 1, CvtOp);
1171       widenScalarDst(MI, WideTy);
1172     } else {
1173       assert(TypeIdx == 1);
1174       // The "number of bits to shift" operand must preserve its value as an
1175       // unsigned integer:
1176       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1177     }
1178 
1179     Observer.changedInstr(MI);
1180     return Legalized;
1181   case TargetOpcode::G_UDIV:
1182   case TargetOpcode::G_UREM:
1183   case TargetOpcode::G_UMIN:
1184   case TargetOpcode::G_UMAX:
1185     Observer.changingInstr(MI);
1186     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1187     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1188     widenScalarDst(MI, WideTy);
1189     Observer.changedInstr(MI);
1190     return Legalized;
1191 
1192   case TargetOpcode::G_SELECT:
1193     Observer.changingInstr(MI);
1194     if (TypeIdx == 0) {
1195       // Perform operation at larger width (any extension is fine here, high
1196       // bits don't affect the result) and then truncate the result back to the
1197       // original type.
1198       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1199       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1200       widenScalarDst(MI, WideTy);
1201     } else {
1202       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1203       // Explicit extension is required here since high bits affect the result.
1204       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1205     }
1206     Observer.changedInstr(MI);
1207     return Legalized;
1208 
1209   case TargetOpcode::G_FPTOSI:
1210   case TargetOpcode::G_FPTOUI:
1211     if (TypeIdx != 0)
1212       return UnableToLegalize;
1213     Observer.changingInstr(MI);
1214     widenScalarDst(MI, WideTy);
1215     Observer.changedInstr(MI);
1216     return Legalized;
1217 
1218   case TargetOpcode::G_SITOFP:
1219     if (TypeIdx != 1)
1220       return UnableToLegalize;
1221     Observer.changingInstr(MI);
1222     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1223     Observer.changedInstr(MI);
1224     return Legalized;
1225 
1226   case TargetOpcode::G_UITOFP:
1227     if (TypeIdx != 1)
1228       return UnableToLegalize;
1229     Observer.changingInstr(MI);
1230     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1231     Observer.changedInstr(MI);
1232     return Legalized;
1233 
1234   case TargetOpcode::G_LOAD:
1235   case TargetOpcode::G_SEXTLOAD:
1236   case TargetOpcode::G_ZEXTLOAD:
1237     Observer.changingInstr(MI);
1238     widenScalarDst(MI, WideTy);
1239     Observer.changedInstr(MI);
1240     return Legalized;
1241 
1242   case TargetOpcode::G_STORE: {
1243     if (TypeIdx != 0)
1244       return UnableToLegalize;
1245 
1246     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1247     if (!isPowerOf2_32(Ty.getSizeInBits()))
1248       return UnableToLegalize;
1249 
1250     Observer.changingInstr(MI);
1251 
1252     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1253       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1254     widenScalarSrc(MI, WideTy, 0, ExtType);
1255 
1256     Observer.changedInstr(MI);
1257     return Legalized;
1258   }
1259   case TargetOpcode::G_CONSTANT: {
1260     MachineOperand &SrcMO = MI.getOperand(1);
1261     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1262     const APInt &Val = SrcMO.getCImm()->getValue().sext(WideTy.getSizeInBits());
1263     Observer.changingInstr(MI);
1264     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1265 
1266     widenScalarDst(MI, WideTy);
1267     Observer.changedInstr(MI);
1268     return Legalized;
1269   }
1270   case TargetOpcode::G_FCONSTANT: {
1271     MachineOperand &SrcMO = MI.getOperand(1);
1272     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1273     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1274     bool LosesInfo;
1275     switch (WideTy.getSizeInBits()) {
1276     case 32:
1277       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1278                   &LosesInfo);
1279       break;
1280     case 64:
1281       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1282                   &LosesInfo);
1283       break;
1284     default:
1285       return UnableToLegalize;
1286     }
1287 
1288     assert(!LosesInfo && "extend should always be lossless");
1289 
1290     Observer.changingInstr(MI);
1291     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1292 
1293     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1294     Observer.changedInstr(MI);
1295     return Legalized;
1296   }
1297   case TargetOpcode::G_IMPLICIT_DEF: {
1298     Observer.changingInstr(MI);
1299     widenScalarDst(MI, WideTy);
1300     Observer.changedInstr(MI);
1301     return Legalized;
1302   }
1303   case TargetOpcode::G_BRCOND:
1304     Observer.changingInstr(MI);
1305     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1306     Observer.changedInstr(MI);
1307     return Legalized;
1308 
1309   case TargetOpcode::G_FCMP:
1310     Observer.changingInstr(MI);
1311     if (TypeIdx == 0)
1312       widenScalarDst(MI, WideTy);
1313     else {
1314       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1315       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1316     }
1317     Observer.changedInstr(MI);
1318     return Legalized;
1319 
1320   case TargetOpcode::G_ICMP:
1321     Observer.changingInstr(MI);
1322     if (TypeIdx == 0)
1323       widenScalarDst(MI, WideTy);
1324     else {
1325       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1326                                MI.getOperand(1).getPredicate()))
1327                                ? TargetOpcode::G_SEXT
1328                                : TargetOpcode::G_ZEXT;
1329       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1330       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1331     }
1332     Observer.changedInstr(MI);
1333     return Legalized;
1334 
1335   case TargetOpcode::G_GEP:
1336     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
1337     Observer.changingInstr(MI);
1338     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1339     Observer.changedInstr(MI);
1340     return Legalized;
1341 
1342   case TargetOpcode::G_PHI: {
1343     assert(TypeIdx == 0 && "Expecting only Idx 0");
1344 
1345     Observer.changingInstr(MI);
1346     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1347       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1348       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1349       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1350     }
1351 
1352     MachineBasicBlock &MBB = *MI.getParent();
1353     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1354     widenScalarDst(MI, WideTy);
1355     Observer.changedInstr(MI);
1356     return Legalized;
1357   }
1358   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1359     if (TypeIdx == 0) {
1360       Register VecReg = MI.getOperand(1).getReg();
1361       LLT VecTy = MRI.getType(VecReg);
1362       Observer.changingInstr(MI);
1363 
1364       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1365                                      WideTy.getSizeInBits()),
1366                      1, TargetOpcode::G_SEXT);
1367 
1368       widenScalarDst(MI, WideTy, 0);
1369       Observer.changedInstr(MI);
1370       return Legalized;
1371     }
1372 
1373     if (TypeIdx != 2)
1374       return UnableToLegalize;
1375     Observer.changingInstr(MI);
1376     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1377     Observer.changedInstr(MI);
1378     return Legalized;
1379   }
1380   case TargetOpcode::G_FADD:
1381   case TargetOpcode::G_FMUL:
1382   case TargetOpcode::G_FSUB:
1383   case TargetOpcode::G_FMA:
1384   case TargetOpcode::G_FNEG:
1385   case TargetOpcode::G_FABS:
1386   case TargetOpcode::G_FCANONICALIZE:
1387   case TargetOpcode::G_FMINNUM:
1388   case TargetOpcode::G_FMAXNUM:
1389   case TargetOpcode::G_FMINNUM_IEEE:
1390   case TargetOpcode::G_FMAXNUM_IEEE:
1391   case TargetOpcode::G_FMINIMUM:
1392   case TargetOpcode::G_FMAXIMUM:
1393   case TargetOpcode::G_FDIV:
1394   case TargetOpcode::G_FREM:
1395   case TargetOpcode::G_FCEIL:
1396   case TargetOpcode::G_FFLOOR:
1397   case TargetOpcode::G_FCOS:
1398   case TargetOpcode::G_FSIN:
1399   case TargetOpcode::G_FLOG10:
1400   case TargetOpcode::G_FLOG:
1401   case TargetOpcode::G_FLOG2:
1402   case TargetOpcode::G_FRINT:
1403   case TargetOpcode::G_FNEARBYINT:
1404   case TargetOpcode::G_FSQRT:
1405   case TargetOpcode::G_FEXP:
1406   case TargetOpcode::G_FEXP2:
1407   case TargetOpcode::G_FPOW:
1408   case TargetOpcode::G_INTRINSIC_TRUNC:
1409   case TargetOpcode::G_INTRINSIC_ROUND:
1410     assert(TypeIdx == 0);
1411     Observer.changingInstr(MI);
1412 
1413     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1414       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1415 
1416     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1417     Observer.changedInstr(MI);
1418     return Legalized;
1419   case TargetOpcode::G_INTTOPTR:
1420     if (TypeIdx != 1)
1421       return UnableToLegalize;
1422 
1423     Observer.changingInstr(MI);
1424     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1425     Observer.changedInstr(MI);
1426     return Legalized;
1427   case TargetOpcode::G_PTRTOINT:
1428     if (TypeIdx != 0)
1429       return UnableToLegalize;
1430 
1431     Observer.changingInstr(MI);
1432     widenScalarDst(MI, WideTy, 0);
1433     Observer.changedInstr(MI);
1434     return Legalized;
1435   case TargetOpcode::G_BUILD_VECTOR: {
1436     Observer.changingInstr(MI);
1437 
1438     const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
1439     for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
1440       widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT);
1441 
1442     // Avoid changing the result vector type if the source element type was
1443     // requested.
1444     if (TypeIdx == 1) {
1445       auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
1446       MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
1447     } else {
1448       widenScalarDst(MI, WideTy, 0);
1449     }
1450 
1451     Observer.changedInstr(MI);
1452     return Legalized;
1453   }
1454   }
1455 }
1456 
1457 LegalizerHelper::LegalizeResult
1458 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1459   using namespace TargetOpcode;
1460   MIRBuilder.setInstr(MI);
1461 
1462   switch(MI.getOpcode()) {
1463   default:
1464     return UnableToLegalize;
1465   case TargetOpcode::G_SREM:
1466   case TargetOpcode::G_UREM: {
1467     Register QuotReg = MRI.createGenericVirtualRegister(Ty);
1468     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1469         .addDef(QuotReg)
1470         .addUse(MI.getOperand(1).getReg())
1471         .addUse(MI.getOperand(2).getReg());
1472 
1473     Register ProdReg = MRI.createGenericVirtualRegister(Ty);
1474     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1475     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1476                         ProdReg);
1477     MI.eraseFromParent();
1478     return Legalized;
1479   }
1480   case TargetOpcode::G_SMULO:
1481   case TargetOpcode::G_UMULO: {
1482     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
1483     // result.
1484     Register Res = MI.getOperand(0).getReg();
1485     Register Overflow = MI.getOperand(1).getReg();
1486     Register LHS = MI.getOperand(2).getReg();
1487     Register RHS = MI.getOperand(3).getReg();
1488 
1489     MIRBuilder.buildMul(Res, LHS, RHS);
1490 
1491     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
1492                           ? TargetOpcode::G_SMULH
1493                           : TargetOpcode::G_UMULH;
1494 
1495     Register HiPart = MRI.createGenericVirtualRegister(Ty);
1496     MIRBuilder.buildInstr(Opcode)
1497       .addDef(HiPart)
1498       .addUse(LHS)
1499       .addUse(RHS);
1500 
1501     Register Zero = MRI.createGenericVirtualRegister(Ty);
1502     MIRBuilder.buildConstant(Zero, 0);
1503 
1504     // For *signed* multiply, overflow is detected by checking:
1505     // (hi != (lo >> bitwidth-1))
1506     if (Opcode == TargetOpcode::G_SMULH) {
1507       Register Shifted = MRI.createGenericVirtualRegister(Ty);
1508       Register ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1509       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
1510       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
1511         .addDef(Shifted)
1512         .addUse(Res)
1513         .addUse(ShiftAmt);
1514       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
1515     } else {
1516       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
1517     }
1518     MI.eraseFromParent();
1519     return Legalized;
1520   }
1521   case TargetOpcode::G_FNEG: {
1522     // TODO: Handle vector types once we are able to
1523     // represent them.
1524     if (Ty.isVector())
1525       return UnableToLegalize;
1526     Register Res = MI.getOperand(0).getReg();
1527     Type *ZeroTy;
1528     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1529     switch (Ty.getSizeInBits()) {
1530     case 16:
1531       ZeroTy = Type::getHalfTy(Ctx);
1532       break;
1533     case 32:
1534       ZeroTy = Type::getFloatTy(Ctx);
1535       break;
1536     case 64:
1537       ZeroTy = Type::getDoubleTy(Ctx);
1538       break;
1539     case 128:
1540       ZeroTy = Type::getFP128Ty(Ctx);
1541       break;
1542     default:
1543       llvm_unreachable("unexpected floating-point type");
1544     }
1545     ConstantFP &ZeroForNegation =
1546         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
1547     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
1548     Register SubByReg = MI.getOperand(1).getReg();
1549     Register ZeroReg = Zero->getOperand(0).getReg();
1550     MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
1551                           MI.getFlags());
1552     MI.eraseFromParent();
1553     return Legalized;
1554   }
1555   case TargetOpcode::G_FSUB: {
1556     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
1557     // First, check if G_FNEG is marked as Lower. If so, we may
1558     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
1559     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
1560       return UnableToLegalize;
1561     Register Res = MI.getOperand(0).getReg();
1562     Register LHS = MI.getOperand(1).getReg();
1563     Register RHS = MI.getOperand(2).getReg();
1564     Register Neg = MRI.createGenericVirtualRegister(Ty);
1565     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
1566     MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
1567     MI.eraseFromParent();
1568     return Legalized;
1569   }
1570   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
1571     Register OldValRes = MI.getOperand(0).getReg();
1572     Register SuccessRes = MI.getOperand(1).getReg();
1573     Register Addr = MI.getOperand(2).getReg();
1574     Register CmpVal = MI.getOperand(3).getReg();
1575     Register NewVal = MI.getOperand(4).getReg();
1576     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
1577                                   **MI.memoperands_begin());
1578     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
1579     MI.eraseFromParent();
1580     return Legalized;
1581   }
1582   case TargetOpcode::G_LOAD:
1583   case TargetOpcode::G_SEXTLOAD:
1584   case TargetOpcode::G_ZEXTLOAD: {
1585     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
1586     Register DstReg = MI.getOperand(0).getReg();
1587     Register PtrReg = MI.getOperand(1).getReg();
1588     LLT DstTy = MRI.getType(DstReg);
1589     auto &MMO = **MI.memoperands_begin();
1590 
1591     if (DstTy.getSizeInBits() == MMO.getSize() /* in bytes */ * 8) {
1592       // In the case of G_LOAD, this was a non-extending load already and we're
1593       // about to lower to the same instruction.
1594       if (MI.getOpcode() == TargetOpcode::G_LOAD)
1595           return UnableToLegalize;
1596       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
1597       MI.eraseFromParent();
1598       return Legalized;
1599     }
1600 
1601     if (DstTy.isScalar()) {
1602       Register TmpReg =
1603           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
1604       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
1605       switch (MI.getOpcode()) {
1606       default:
1607         llvm_unreachable("Unexpected opcode");
1608       case TargetOpcode::G_LOAD:
1609         MIRBuilder.buildAnyExt(DstReg, TmpReg);
1610         break;
1611       case TargetOpcode::G_SEXTLOAD:
1612         MIRBuilder.buildSExt(DstReg, TmpReg);
1613         break;
1614       case TargetOpcode::G_ZEXTLOAD:
1615         MIRBuilder.buildZExt(DstReg, TmpReg);
1616         break;
1617       }
1618       MI.eraseFromParent();
1619       return Legalized;
1620     }
1621 
1622     return UnableToLegalize;
1623   }
1624   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1625   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1626   case TargetOpcode::G_CTLZ:
1627   case TargetOpcode::G_CTTZ:
1628   case TargetOpcode::G_CTPOP:
1629     return lowerBitCount(MI, TypeIdx, Ty);
1630   case G_UADDO: {
1631     Register Res = MI.getOperand(0).getReg();
1632     Register CarryOut = MI.getOperand(1).getReg();
1633     Register LHS = MI.getOperand(2).getReg();
1634     Register RHS = MI.getOperand(3).getReg();
1635 
1636     MIRBuilder.buildAdd(Res, LHS, RHS);
1637     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
1638 
1639     MI.eraseFromParent();
1640     return Legalized;
1641   }
1642   case G_UADDE: {
1643     Register Res = MI.getOperand(0).getReg();
1644     Register CarryOut = MI.getOperand(1).getReg();
1645     Register LHS = MI.getOperand(2).getReg();
1646     Register RHS = MI.getOperand(3).getReg();
1647     Register CarryIn = MI.getOperand(4).getReg();
1648 
1649     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
1650     Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
1651 
1652     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
1653     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
1654     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
1655     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
1656 
1657     MI.eraseFromParent();
1658     return Legalized;
1659   }
1660   case G_USUBO: {
1661     Register Res = MI.getOperand(0).getReg();
1662     Register BorrowOut = MI.getOperand(1).getReg();
1663     Register LHS = MI.getOperand(2).getReg();
1664     Register RHS = MI.getOperand(3).getReg();
1665 
1666     MIRBuilder.buildSub(Res, LHS, RHS);
1667     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
1668 
1669     MI.eraseFromParent();
1670     return Legalized;
1671   }
1672   case G_USUBE: {
1673     Register Res = MI.getOperand(0).getReg();
1674     Register BorrowOut = MI.getOperand(1).getReg();
1675     Register LHS = MI.getOperand(2).getReg();
1676     Register RHS = MI.getOperand(3).getReg();
1677     Register BorrowIn = MI.getOperand(4).getReg();
1678 
1679     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
1680     Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
1681     Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1682     Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1683 
1684     MIRBuilder.buildSub(TmpRes, LHS, RHS);
1685     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
1686     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
1687     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
1688     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
1689     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
1690 
1691     MI.eraseFromParent();
1692     return Legalized;
1693   }
1694   case G_UITOFP:
1695     return lowerUITOFP(MI, TypeIdx, Ty);
1696   case G_SITOFP:
1697     return lowerSITOFP(MI, TypeIdx, Ty);
1698   case G_SMIN:
1699   case G_SMAX:
1700   case G_UMIN:
1701   case G_UMAX:
1702     return lowerMinMax(MI, TypeIdx, Ty);
1703   case G_FCOPYSIGN:
1704     return lowerFCopySign(MI, TypeIdx, Ty);
1705   case G_FMINNUM:
1706   case G_FMAXNUM:
1707     return lowerFMinNumMaxNum(MI);
1708   }
1709 }
1710 
1711 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
1712     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
1713   SmallVector<Register, 2> DstRegs;
1714 
1715   unsigned NarrowSize = NarrowTy.getSizeInBits();
1716   Register DstReg = MI.getOperand(0).getReg();
1717   unsigned Size = MRI.getType(DstReg).getSizeInBits();
1718   int NumParts = Size / NarrowSize;
1719   // FIXME: Don't know how to handle the situation where the small vectors
1720   // aren't all the same size yet.
1721   if (Size % NarrowSize != 0)
1722     return UnableToLegalize;
1723 
1724   for (int i = 0; i < NumParts; ++i) {
1725     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
1726     MIRBuilder.buildUndef(TmpReg);
1727     DstRegs.push_back(TmpReg);
1728   }
1729 
1730   if (NarrowTy.isVector())
1731     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1732   else
1733     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1734 
1735   MI.eraseFromParent();
1736   return Legalized;
1737 }
1738 
1739 LegalizerHelper::LegalizeResult
1740 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
1741                                           LLT NarrowTy) {
1742   const unsigned Opc = MI.getOpcode();
1743   const unsigned NumOps = MI.getNumOperands() - 1;
1744   const unsigned NarrowSize = NarrowTy.getSizeInBits();
1745   const Register DstReg = MI.getOperand(0).getReg();
1746   const unsigned Flags = MI.getFlags();
1747   const LLT DstTy = MRI.getType(DstReg);
1748   const unsigned Size = DstTy.getSizeInBits();
1749   const int NumParts = Size / NarrowSize;
1750   const LLT EltTy = DstTy.getElementType();
1751   const unsigned EltSize = EltTy.getSizeInBits();
1752   const unsigned BitsForNumParts = NarrowSize * NumParts;
1753 
1754   // Check if we have any leftovers. If we do, then only handle the case where
1755   // the leftover is one element.
1756   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
1757     return UnableToLegalize;
1758 
1759   if (BitsForNumParts != Size) {
1760     Register AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
1761     MIRBuilder.buildUndef(AccumDstReg);
1762 
1763     // Handle the pieces which evenly divide into the requested type with
1764     // extract/op/insert sequence.
1765     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
1766       SmallVector<SrcOp, 4> SrcOps;
1767       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1768         Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
1769         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
1770         SrcOps.push_back(PartOpReg);
1771       }
1772 
1773       Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
1774       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1775 
1776       Register PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
1777       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
1778       AccumDstReg = PartInsertReg;
1779     }
1780 
1781     // Handle the remaining element sized leftover piece.
1782     SmallVector<SrcOp, 4> SrcOps;
1783     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1784       Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
1785       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
1786                               BitsForNumParts);
1787       SrcOps.push_back(PartOpReg);
1788     }
1789 
1790     Register PartDstReg = MRI.createGenericVirtualRegister(EltTy);
1791     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1792     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
1793     MI.eraseFromParent();
1794 
1795     return Legalized;
1796   }
1797 
1798   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
1799 
1800   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
1801 
1802   if (NumOps >= 2)
1803     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
1804 
1805   if (NumOps >= 3)
1806     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
1807 
1808   for (int i = 0; i < NumParts; ++i) {
1809     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
1810 
1811     if (NumOps == 1)
1812       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
1813     else if (NumOps == 2) {
1814       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
1815     } else if (NumOps == 3) {
1816       MIRBuilder.buildInstr(Opc, {DstReg},
1817                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
1818     }
1819 
1820     DstRegs.push_back(DstReg);
1821   }
1822 
1823   if (NarrowTy.isVector())
1824     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1825   else
1826     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1827 
1828   MI.eraseFromParent();
1829   return Legalized;
1830 }
1831 
1832 // Handle splitting vector operations which need to have the same number of
1833 // elements in each type index, but each type index may have a different element
1834 // type.
1835 //
1836 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
1837 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1838 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1839 //
1840 // Also handles some irregular breakdown cases, e.g.
1841 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
1842 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1843 //             s64 = G_SHL s64, s32
1844 LegalizerHelper::LegalizeResult
1845 LegalizerHelper::fewerElementsVectorMultiEltType(
1846   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
1847   if (TypeIdx != 0)
1848     return UnableToLegalize;
1849 
1850   const LLT NarrowTy0 = NarrowTyArg;
1851   const unsigned NewNumElts =
1852       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
1853 
1854   const Register DstReg = MI.getOperand(0).getReg();
1855   LLT DstTy = MRI.getType(DstReg);
1856   LLT LeftoverTy0;
1857 
1858   int NumParts, NumLeftover;
1859   // All of the operands need to have the same number of elements, so if we can
1860   // determine a type breakdown for the result type, we can for all of the
1861   // source types.
1862   std::tie(NumParts, NumLeftover)
1863     = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0);
1864   if (NumParts < 0)
1865     return UnableToLegalize;
1866 
1867   SmallVector<MachineInstrBuilder, 4> NewInsts;
1868 
1869   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
1870   SmallVector<Register, 4> PartRegs, LeftoverRegs;
1871 
1872   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1873     LLT LeftoverTy;
1874     Register SrcReg = MI.getOperand(I).getReg();
1875     LLT SrcTyI = MRI.getType(SrcReg);
1876     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
1877     LLT LeftoverTyI;
1878 
1879     // Split this operand into the requested typed registers, and any leftover
1880     // required to reproduce the original type.
1881     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
1882                       LeftoverRegs))
1883       return UnableToLegalize;
1884 
1885     if (I == 1) {
1886       // For the first operand, create an instruction for each part and setup
1887       // the result.
1888       for (Register PartReg : PartRegs) {
1889         Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1890         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
1891                                .addDef(PartDstReg)
1892                                .addUse(PartReg));
1893         DstRegs.push_back(PartDstReg);
1894       }
1895 
1896       for (Register LeftoverReg : LeftoverRegs) {
1897         Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
1898         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
1899                                .addDef(PartDstReg)
1900                                .addUse(LeftoverReg));
1901         LeftoverDstRegs.push_back(PartDstReg);
1902       }
1903     } else {
1904       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
1905 
1906       // Add the newly created operand splits to the existing instructions. The
1907       // odd-sized pieces are ordered after the requested NarrowTyArg sized
1908       // pieces.
1909       unsigned InstCount = 0;
1910       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
1911         NewInsts[InstCount++].addUse(PartRegs[J]);
1912       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
1913         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
1914     }
1915 
1916     PartRegs.clear();
1917     LeftoverRegs.clear();
1918   }
1919 
1920   // Insert the newly built operations and rebuild the result register.
1921   for (auto &MIB : NewInsts)
1922     MIRBuilder.insertInstr(MIB);
1923 
1924   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
1925 
1926   MI.eraseFromParent();
1927   return Legalized;
1928 }
1929 
1930 LegalizerHelper::LegalizeResult
1931 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
1932                                           LLT NarrowTy) {
1933   if (TypeIdx != 0)
1934     return UnableToLegalize;
1935 
1936   Register DstReg = MI.getOperand(0).getReg();
1937   Register SrcReg = MI.getOperand(1).getReg();
1938   LLT DstTy = MRI.getType(DstReg);
1939   LLT SrcTy = MRI.getType(SrcReg);
1940 
1941   LLT NarrowTy0 = NarrowTy;
1942   LLT NarrowTy1;
1943   unsigned NumParts;
1944 
1945   if (NarrowTy.isVector()) {
1946     // Uneven breakdown not handled.
1947     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
1948     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
1949       return UnableToLegalize;
1950 
1951     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
1952   } else {
1953     NumParts = DstTy.getNumElements();
1954     NarrowTy1 = SrcTy.getElementType();
1955   }
1956 
1957   SmallVector<Register, 4> SrcRegs, DstRegs;
1958   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
1959 
1960   for (unsigned I = 0; I < NumParts; ++I) {
1961     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1962     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
1963       .addDef(DstReg)
1964       .addUse(SrcRegs[I]);
1965 
1966     NewInst->setFlags(MI.getFlags());
1967     DstRegs.push_back(DstReg);
1968   }
1969 
1970   if (NarrowTy.isVector())
1971     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1972   else
1973     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1974 
1975   MI.eraseFromParent();
1976   return Legalized;
1977 }
1978 
1979 LegalizerHelper::LegalizeResult
1980 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
1981                                         LLT NarrowTy) {
1982   Register DstReg = MI.getOperand(0).getReg();
1983   Register Src0Reg = MI.getOperand(2).getReg();
1984   LLT DstTy = MRI.getType(DstReg);
1985   LLT SrcTy = MRI.getType(Src0Reg);
1986 
1987   unsigned NumParts;
1988   LLT NarrowTy0, NarrowTy1;
1989 
1990   if (TypeIdx == 0) {
1991     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
1992     unsigned OldElts = DstTy.getNumElements();
1993 
1994     NarrowTy0 = NarrowTy;
1995     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
1996     NarrowTy1 = NarrowTy.isVector() ?
1997       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
1998       SrcTy.getElementType();
1999 
2000   } else {
2001     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2002     unsigned OldElts = SrcTy.getNumElements();
2003 
2004     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
2005       NarrowTy.getNumElements();
2006     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
2007                             DstTy.getScalarSizeInBits());
2008     NarrowTy1 = NarrowTy;
2009   }
2010 
2011   // FIXME: Don't know how to handle the situation where the small vectors
2012   // aren't all the same size yet.
2013   if (NarrowTy1.isVector() &&
2014       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
2015     return UnableToLegalize;
2016 
2017   CmpInst::Predicate Pred
2018     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
2019 
2020   SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
2021   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
2022   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
2023 
2024   for (unsigned I = 0; I < NumParts; ++I) {
2025     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2026     DstRegs.push_back(DstReg);
2027 
2028     if (MI.getOpcode() == TargetOpcode::G_ICMP)
2029       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2030     else {
2031       MachineInstr *NewCmp
2032         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2033       NewCmp->setFlags(MI.getFlags());
2034     }
2035   }
2036 
2037   if (NarrowTy1.isVector())
2038     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2039   else
2040     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2041 
2042   MI.eraseFromParent();
2043   return Legalized;
2044 }
2045 
2046 LegalizerHelper::LegalizeResult
2047 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
2048                                            LLT NarrowTy) {
2049   Register DstReg = MI.getOperand(0).getReg();
2050   Register CondReg = MI.getOperand(1).getReg();
2051 
2052   unsigned NumParts = 0;
2053   LLT NarrowTy0, NarrowTy1;
2054 
2055   LLT DstTy = MRI.getType(DstReg);
2056   LLT CondTy = MRI.getType(CondReg);
2057   unsigned Size = DstTy.getSizeInBits();
2058 
2059   assert(TypeIdx == 0 || CondTy.isVector());
2060 
2061   if (TypeIdx == 0) {
2062     NarrowTy0 = NarrowTy;
2063     NarrowTy1 = CondTy;
2064 
2065     unsigned NarrowSize = NarrowTy0.getSizeInBits();
2066     // FIXME: Don't know how to handle the situation where the small vectors
2067     // aren't all the same size yet.
2068     if (Size % NarrowSize != 0)
2069       return UnableToLegalize;
2070 
2071     NumParts = Size / NarrowSize;
2072 
2073     // Need to break down the condition type
2074     if (CondTy.isVector()) {
2075       if (CondTy.getNumElements() == NumParts)
2076         NarrowTy1 = CondTy.getElementType();
2077       else
2078         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
2079                                 CondTy.getScalarSizeInBits());
2080     }
2081   } else {
2082     NumParts = CondTy.getNumElements();
2083     if (NarrowTy.isVector()) {
2084       // TODO: Handle uneven breakdown.
2085       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
2086         return UnableToLegalize;
2087 
2088       return UnableToLegalize;
2089     } else {
2090       NarrowTy0 = DstTy.getElementType();
2091       NarrowTy1 = NarrowTy;
2092     }
2093   }
2094 
2095   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2096   if (CondTy.isVector())
2097     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2098 
2099   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2100   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2101 
2102   for (unsigned i = 0; i < NumParts; ++i) {
2103     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2104     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
2105                            Src1Regs[i], Src2Regs[i]);
2106     DstRegs.push_back(DstReg);
2107   }
2108 
2109   if (NarrowTy0.isVector())
2110     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2111   else
2112     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2113 
2114   MI.eraseFromParent();
2115   return Legalized;
2116 }
2117 
2118 LegalizerHelper::LegalizeResult
2119 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2120                                         LLT NarrowTy) {
2121   const Register DstReg = MI.getOperand(0).getReg();
2122   LLT PhiTy = MRI.getType(DstReg);
2123   LLT LeftoverTy;
2124 
2125   // All of the operands need to have the same number of elements, so if we can
2126   // determine a type breakdown for the result type, we can for all of the
2127   // source types.
2128   int NumParts, NumLeftover;
2129   std::tie(NumParts, NumLeftover)
2130     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2131   if (NumParts < 0)
2132     return UnableToLegalize;
2133 
2134   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2135   SmallVector<MachineInstrBuilder, 4> NewInsts;
2136 
2137   const int TotalNumParts = NumParts + NumLeftover;
2138 
2139   // Insert the new phis in the result block first.
2140   for (int I = 0; I != TotalNumParts; ++I) {
2141     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2142     Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
2143     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2144                        .addDef(PartDstReg));
2145     if (I < NumParts)
2146       DstRegs.push_back(PartDstReg);
2147     else
2148       LeftoverDstRegs.push_back(PartDstReg);
2149   }
2150 
2151   MachineBasicBlock *MBB = MI.getParent();
2152   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2153   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2154 
2155   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2156 
2157   // Insert code to extract the incoming values in each predecessor block.
2158   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2159     PartRegs.clear();
2160     LeftoverRegs.clear();
2161 
2162     Register SrcReg = MI.getOperand(I).getReg();
2163     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2164     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2165 
2166     LLT Unused;
2167     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2168                       LeftoverRegs))
2169       return UnableToLegalize;
2170 
2171     // Add the newly created operand splits to the existing instructions. The
2172     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2173     // pieces.
2174     for (int J = 0; J != TotalNumParts; ++J) {
2175       MachineInstrBuilder MIB = NewInsts[J];
2176       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2177       MIB.addMBB(&OpMBB);
2178     }
2179   }
2180 
2181   MI.eraseFromParent();
2182   return Legalized;
2183 }
2184 
2185 LegalizerHelper::LegalizeResult
2186 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2187                                       LLT NarrowTy) {
2188   // FIXME: Don't know how to handle secondary types yet.
2189   if (TypeIdx != 0)
2190     return UnableToLegalize;
2191 
2192   MachineMemOperand *MMO = *MI.memoperands_begin();
2193 
2194   // This implementation doesn't work for atomics. Give up instead of doing
2195   // something invalid.
2196   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2197       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2198     return UnableToLegalize;
2199 
2200   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2201   Register ValReg = MI.getOperand(0).getReg();
2202   Register AddrReg = MI.getOperand(1).getReg();
2203   LLT ValTy = MRI.getType(ValReg);
2204 
2205   int NumParts = -1;
2206   int NumLeftover = -1;
2207   LLT LeftoverTy;
2208   SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
2209   if (IsLoad) {
2210     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2211   } else {
2212     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2213                      NarrowLeftoverRegs)) {
2214       NumParts = NarrowRegs.size();
2215       NumLeftover = NarrowLeftoverRegs.size();
2216     }
2217   }
2218 
2219   if (NumParts == -1)
2220     return UnableToLegalize;
2221 
2222   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2223 
2224   unsigned TotalSize = ValTy.getSizeInBits();
2225 
2226   // Split the load/store into PartTy sized pieces starting at Offset. If this
2227   // is a load, return the new registers in ValRegs. For a store, each elements
2228   // of ValRegs should be PartTy. Returns the next offset that needs to be
2229   // handled.
2230   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
2231                              unsigned Offset) -> unsigned {
2232     MachineFunction &MF = MIRBuilder.getMF();
2233     unsigned PartSize = PartTy.getSizeInBits();
2234     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2235          Offset += PartSize, ++Idx) {
2236       unsigned ByteSize = PartSize / 8;
2237       unsigned ByteOffset = Offset / 8;
2238       Register NewAddrReg;
2239 
2240       MIRBuilder.materializeGEP(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2241 
2242       MachineMemOperand *NewMMO =
2243         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2244 
2245       if (IsLoad) {
2246         Register Dst = MRI.createGenericVirtualRegister(PartTy);
2247         ValRegs.push_back(Dst);
2248         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
2249       } else {
2250         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
2251       }
2252     }
2253 
2254     return Offset;
2255   };
2256 
2257   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
2258 
2259   // Handle the rest of the register if this isn't an even type breakdown.
2260   if (LeftoverTy.isValid())
2261     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
2262 
2263   if (IsLoad) {
2264     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
2265                 LeftoverTy, NarrowLeftoverRegs);
2266   }
2267 
2268   MI.eraseFromParent();
2269   return Legalized;
2270 }
2271 
2272 LegalizerHelper::LegalizeResult
2273 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
2274                                      LLT NarrowTy) {
2275   using namespace TargetOpcode;
2276 
2277   MIRBuilder.setInstr(MI);
2278   switch (MI.getOpcode()) {
2279   case G_IMPLICIT_DEF:
2280     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
2281   case G_AND:
2282   case G_OR:
2283   case G_XOR:
2284   case G_ADD:
2285   case G_SUB:
2286   case G_MUL:
2287   case G_SMULH:
2288   case G_UMULH:
2289   case G_FADD:
2290   case G_FMUL:
2291   case G_FSUB:
2292   case G_FNEG:
2293   case G_FABS:
2294   case G_FCANONICALIZE:
2295   case G_FDIV:
2296   case G_FREM:
2297   case G_FMA:
2298   case G_FPOW:
2299   case G_FEXP:
2300   case G_FEXP2:
2301   case G_FLOG:
2302   case G_FLOG2:
2303   case G_FLOG10:
2304   case G_FNEARBYINT:
2305   case G_FCEIL:
2306   case G_FFLOOR:
2307   case G_FRINT:
2308   case G_INTRINSIC_ROUND:
2309   case G_INTRINSIC_TRUNC:
2310   case G_FCOS:
2311   case G_FSIN:
2312   case G_FSQRT:
2313   case G_BSWAP:
2314   case G_SDIV:
2315   case G_SMIN:
2316   case G_SMAX:
2317   case G_UMIN:
2318   case G_UMAX:
2319   case G_FMINNUM:
2320   case G_FMAXNUM:
2321   case G_FMINNUM_IEEE:
2322   case G_FMAXNUM_IEEE:
2323   case G_FMINIMUM:
2324   case G_FMAXIMUM:
2325     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
2326   case G_SHL:
2327   case G_LSHR:
2328   case G_ASHR:
2329   case G_CTLZ:
2330   case G_CTLZ_ZERO_UNDEF:
2331   case G_CTTZ:
2332   case G_CTTZ_ZERO_UNDEF:
2333   case G_CTPOP:
2334   case G_FCOPYSIGN:
2335     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
2336   case G_ZEXT:
2337   case G_SEXT:
2338   case G_ANYEXT:
2339   case G_FPEXT:
2340   case G_FPTRUNC:
2341   case G_SITOFP:
2342   case G_UITOFP:
2343   case G_FPTOSI:
2344   case G_FPTOUI:
2345   case G_INTTOPTR:
2346   case G_PTRTOINT:
2347   case G_ADDRSPACE_CAST:
2348     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
2349   case G_ICMP:
2350   case G_FCMP:
2351     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
2352   case G_SELECT:
2353     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
2354   case G_PHI:
2355     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
2356   case G_LOAD:
2357   case G_STORE:
2358     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
2359   default:
2360     return UnableToLegalize;
2361   }
2362 }
2363 
2364 LegalizerHelper::LegalizeResult
2365 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
2366                                              const LLT HalfTy, const LLT AmtTy) {
2367 
2368   Register InL = MRI.createGenericVirtualRegister(HalfTy);
2369   Register InH = MRI.createGenericVirtualRegister(HalfTy);
2370   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2371 
2372   if (Amt.isNullValue()) {
2373     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
2374     MI.eraseFromParent();
2375     return Legalized;
2376   }
2377 
2378   LLT NVT = HalfTy;
2379   unsigned NVTBits = HalfTy.getSizeInBits();
2380   unsigned VTBits = 2 * NVTBits;
2381 
2382   SrcOp Lo(Register(0)), Hi(Register(0));
2383   if (MI.getOpcode() == TargetOpcode::G_SHL) {
2384     if (Amt.ugt(VTBits)) {
2385       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2386     } else if (Amt.ugt(NVTBits)) {
2387       Lo = MIRBuilder.buildConstant(NVT, 0);
2388       Hi = MIRBuilder.buildShl(NVT, InL,
2389                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2390     } else if (Amt == NVTBits) {
2391       Lo = MIRBuilder.buildConstant(NVT, 0);
2392       Hi = InL;
2393     } else {
2394       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
2395       auto OrLHS =
2396           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
2397       auto OrRHS = MIRBuilder.buildLShr(
2398           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2399       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2400     }
2401   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
2402     if (Amt.ugt(VTBits)) {
2403       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2404     } else if (Amt.ugt(NVTBits)) {
2405       Lo = MIRBuilder.buildLShr(NVT, InH,
2406                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2407       Hi = MIRBuilder.buildConstant(NVT, 0);
2408     } else if (Amt == NVTBits) {
2409       Lo = InH;
2410       Hi = MIRBuilder.buildConstant(NVT, 0);
2411     } else {
2412       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2413 
2414       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2415       auto OrRHS = MIRBuilder.buildShl(
2416           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2417 
2418       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2419       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
2420     }
2421   } else {
2422     if (Amt.ugt(VTBits)) {
2423       Hi = Lo = MIRBuilder.buildAShr(
2424           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2425     } else if (Amt.ugt(NVTBits)) {
2426       Lo = MIRBuilder.buildAShr(NVT, InH,
2427                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2428       Hi = MIRBuilder.buildAShr(NVT, InH,
2429                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2430     } else if (Amt == NVTBits) {
2431       Lo = InH;
2432       Hi = MIRBuilder.buildAShr(NVT, InH,
2433                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2434     } else {
2435       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2436 
2437       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2438       auto OrRHS = MIRBuilder.buildShl(
2439           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2440 
2441       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2442       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
2443     }
2444   }
2445 
2446   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
2447   MI.eraseFromParent();
2448 
2449   return Legalized;
2450 }
2451 
2452 // TODO: Optimize if constant shift amount.
2453 LegalizerHelper::LegalizeResult
2454 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
2455                                    LLT RequestedTy) {
2456   if (TypeIdx == 1) {
2457     Observer.changingInstr(MI);
2458     narrowScalarSrc(MI, RequestedTy, 2);
2459     Observer.changedInstr(MI);
2460     return Legalized;
2461   }
2462 
2463   Register DstReg = MI.getOperand(0).getReg();
2464   LLT DstTy = MRI.getType(DstReg);
2465   if (DstTy.isVector())
2466     return UnableToLegalize;
2467 
2468   Register Amt = MI.getOperand(2).getReg();
2469   LLT ShiftAmtTy = MRI.getType(Amt);
2470   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
2471   if (DstEltSize % 2 != 0)
2472     return UnableToLegalize;
2473 
2474   // Ignore the input type. We can only go to exactly half the size of the
2475   // input. If that isn't small enough, the resulting pieces will be further
2476   // legalized.
2477   const unsigned NewBitSize = DstEltSize / 2;
2478   const LLT HalfTy = LLT::scalar(NewBitSize);
2479   const LLT CondTy = LLT::scalar(1);
2480 
2481   if (const MachineInstr *KShiftAmt =
2482           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
2483     return narrowScalarShiftByConstant(
2484         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
2485   }
2486 
2487   // TODO: Expand with known bits.
2488 
2489   // Handle the fully general expansion by an unknown amount.
2490   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
2491 
2492   Register InL = MRI.createGenericVirtualRegister(HalfTy);
2493   Register InH = MRI.createGenericVirtualRegister(HalfTy);
2494   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2495 
2496   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
2497   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
2498 
2499   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
2500   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
2501   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
2502 
2503   Register ResultRegs[2];
2504   switch (MI.getOpcode()) {
2505   case TargetOpcode::G_SHL: {
2506     // Short: ShAmt < NewBitSize
2507     auto LoS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2508 
2509     auto OrLHS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2510     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
2511     auto HiS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2512 
2513     // Long: ShAmt >= NewBitSize
2514     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
2515     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
2516 
2517     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
2518     auto Hi = MIRBuilder.buildSelect(
2519         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
2520 
2521     ResultRegs[0] = Lo.getReg(0);
2522     ResultRegs[1] = Hi.getReg(0);
2523     break;
2524   }
2525   case TargetOpcode::G_LSHR: {
2526     // Short: ShAmt < NewBitSize
2527     auto HiS = MIRBuilder.buildLShr(HalfTy, InH, Amt);
2528 
2529     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2530     auto OrRHS = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
2531     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2532 
2533     // Long: ShAmt >= NewBitSize
2534     auto HiL = MIRBuilder.buildConstant(HalfTy, 0);          // Hi part is zero.
2535     auto LoL = MIRBuilder.buildLShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2536 
2537     auto Lo = MIRBuilder.buildSelect(
2538         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2539     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2540 
2541     ResultRegs[0] = Lo.getReg(0);
2542     ResultRegs[1] = Hi.getReg(0);
2543     break;
2544   }
2545   case TargetOpcode::G_ASHR: {
2546     // Short: ShAmt < NewBitSize
2547     auto HiS = MIRBuilder.buildAShr(HalfTy, InH, Amt);
2548 
2549     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2550     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InH, AmtLack);
2551     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2552 
2553     // Long: ShAmt >= NewBitSize
2554 
2555     // Sign of Hi part.
2556     auto HiL = MIRBuilder.buildAShr(
2557         HalfTy, InH, MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1));
2558 
2559     auto LoL = MIRBuilder.buildAShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2560 
2561     auto Lo = MIRBuilder.buildSelect(
2562         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2563 
2564     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2565 
2566     ResultRegs[0] = Lo.getReg(0);
2567     ResultRegs[1] = Hi.getReg(0);
2568     break;
2569   }
2570   default:
2571     llvm_unreachable("not a shift");
2572   }
2573 
2574   MIRBuilder.buildMerge(DstReg, ResultRegs);
2575   MI.eraseFromParent();
2576   return Legalized;
2577 }
2578 
2579 LegalizerHelper::LegalizeResult
2580 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2581                                        LLT MoreTy) {
2582   assert(TypeIdx == 0 && "Expecting only Idx 0");
2583 
2584   Observer.changingInstr(MI);
2585   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2586     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2587     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2588     moreElementsVectorSrc(MI, MoreTy, I);
2589   }
2590 
2591   MachineBasicBlock &MBB = *MI.getParent();
2592   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
2593   moreElementsVectorDst(MI, MoreTy, 0);
2594   Observer.changedInstr(MI);
2595   return Legalized;
2596 }
2597 
2598 LegalizerHelper::LegalizeResult
2599 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
2600                                     LLT MoreTy) {
2601   MIRBuilder.setInstr(MI);
2602   unsigned Opc = MI.getOpcode();
2603   switch (Opc) {
2604   case TargetOpcode::G_IMPLICIT_DEF: {
2605     Observer.changingInstr(MI);
2606     moreElementsVectorDst(MI, MoreTy, 0);
2607     Observer.changedInstr(MI);
2608     return Legalized;
2609   }
2610   case TargetOpcode::G_AND:
2611   case TargetOpcode::G_OR:
2612   case TargetOpcode::G_XOR:
2613   case TargetOpcode::G_SMIN:
2614   case TargetOpcode::G_SMAX:
2615   case TargetOpcode::G_UMIN:
2616   case TargetOpcode::G_UMAX: {
2617     Observer.changingInstr(MI);
2618     moreElementsVectorSrc(MI, MoreTy, 1);
2619     moreElementsVectorSrc(MI, MoreTy, 2);
2620     moreElementsVectorDst(MI, MoreTy, 0);
2621     Observer.changedInstr(MI);
2622     return Legalized;
2623   }
2624   case TargetOpcode::G_EXTRACT:
2625     if (TypeIdx != 1)
2626       return UnableToLegalize;
2627     Observer.changingInstr(MI);
2628     moreElementsVectorSrc(MI, MoreTy, 1);
2629     Observer.changedInstr(MI);
2630     return Legalized;
2631   case TargetOpcode::G_INSERT:
2632     if (TypeIdx != 0)
2633       return UnableToLegalize;
2634     Observer.changingInstr(MI);
2635     moreElementsVectorSrc(MI, MoreTy, 1);
2636     moreElementsVectorDst(MI, MoreTy, 0);
2637     Observer.changedInstr(MI);
2638     return Legalized;
2639   case TargetOpcode::G_SELECT:
2640     if (TypeIdx != 0)
2641       return UnableToLegalize;
2642     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
2643       return UnableToLegalize;
2644 
2645     Observer.changingInstr(MI);
2646     moreElementsVectorSrc(MI, MoreTy, 2);
2647     moreElementsVectorSrc(MI, MoreTy, 3);
2648     moreElementsVectorDst(MI, MoreTy, 0);
2649     Observer.changedInstr(MI);
2650     return Legalized;
2651   case TargetOpcode::G_PHI:
2652     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
2653   default:
2654     return UnableToLegalize;
2655   }
2656 }
2657 
2658 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
2659                                         ArrayRef<Register> Src1Regs,
2660                                         ArrayRef<Register> Src2Regs,
2661                                         LLT NarrowTy) {
2662   MachineIRBuilder &B = MIRBuilder;
2663   unsigned SrcParts = Src1Regs.size();
2664   unsigned DstParts = DstRegs.size();
2665 
2666   unsigned DstIdx = 0; // Low bits of the result.
2667   Register FactorSum =
2668       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
2669   DstRegs[DstIdx] = FactorSum;
2670 
2671   unsigned CarrySumPrevDstIdx;
2672   SmallVector<Register, 4> Factors;
2673 
2674   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
2675     // Collect low parts of muls for DstIdx.
2676     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
2677          i <= std::min(DstIdx, SrcParts - 1); ++i) {
2678       MachineInstrBuilder Mul =
2679           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
2680       Factors.push_back(Mul.getReg(0));
2681     }
2682     // Collect high parts of muls from previous DstIdx.
2683     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
2684          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
2685       MachineInstrBuilder Umulh =
2686           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
2687       Factors.push_back(Umulh.getReg(0));
2688     }
2689     // Add CarrySum from additons calculated for previous DstIdx.
2690     if (DstIdx != 1) {
2691       Factors.push_back(CarrySumPrevDstIdx);
2692     }
2693 
2694     Register CarrySum;
2695     // Add all factors and accumulate all carries into CarrySum.
2696     if (DstIdx != DstParts - 1) {
2697       MachineInstrBuilder Uaddo =
2698           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
2699       FactorSum = Uaddo.getReg(0);
2700       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
2701       for (unsigned i = 2; i < Factors.size(); ++i) {
2702         MachineInstrBuilder Uaddo =
2703             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
2704         FactorSum = Uaddo.getReg(0);
2705         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
2706         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
2707       }
2708     } else {
2709       // Since value for the next index is not calculated, neither is CarrySum.
2710       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
2711       for (unsigned i = 2; i < Factors.size(); ++i)
2712         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
2713     }
2714 
2715     CarrySumPrevDstIdx = CarrySum;
2716     DstRegs[DstIdx] = FactorSum;
2717     Factors.clear();
2718   }
2719 }
2720 
2721 LegalizerHelper::LegalizeResult
2722 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
2723   Register DstReg = MI.getOperand(0).getReg();
2724   Register Src1 = MI.getOperand(1).getReg();
2725   Register Src2 = MI.getOperand(2).getReg();
2726 
2727   LLT Ty = MRI.getType(DstReg);
2728   if (Ty.isVector())
2729     return UnableToLegalize;
2730 
2731   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
2732   unsigned DstSize = Ty.getSizeInBits();
2733   unsigned NarrowSize = NarrowTy.getSizeInBits();
2734   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
2735     return UnableToLegalize;
2736 
2737   unsigned NumDstParts = DstSize / NarrowSize;
2738   unsigned NumSrcParts = SrcSize / NarrowSize;
2739   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
2740   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
2741 
2742   SmallVector<Register, 2> Src1Parts, Src2Parts, DstTmpRegs;
2743   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
2744   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
2745   DstTmpRegs.resize(DstTmpParts);
2746   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
2747 
2748   // Take only high half of registers if this is high mul.
2749   ArrayRef<Register> DstRegs(
2750       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
2751   MIRBuilder.buildMerge(DstReg, DstRegs);
2752   MI.eraseFromParent();
2753   return Legalized;
2754 }
2755 
2756 LegalizerHelper::LegalizeResult
2757 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
2758                                      LLT NarrowTy) {
2759   if (TypeIdx != 1)
2760     return UnableToLegalize;
2761 
2762   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2763 
2764   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2765   // FIXME: add support for when SizeOp1 isn't an exact multiple of
2766   // NarrowSize.
2767   if (SizeOp1 % NarrowSize != 0)
2768     return UnableToLegalize;
2769   int NumParts = SizeOp1 / NarrowSize;
2770 
2771   SmallVector<Register, 2> SrcRegs, DstRegs;
2772   SmallVector<uint64_t, 2> Indexes;
2773   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
2774 
2775   Register OpReg = MI.getOperand(0).getReg();
2776   uint64_t OpStart = MI.getOperand(2).getImm();
2777   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
2778   for (int i = 0; i < NumParts; ++i) {
2779     unsigned SrcStart = i * NarrowSize;
2780 
2781     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
2782       // No part of the extract uses this subregister, ignore it.
2783       continue;
2784     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
2785       // The entire subregister is extracted, forward the value.
2786       DstRegs.push_back(SrcRegs[i]);
2787       continue;
2788     }
2789 
2790     // OpSegStart is where this destination segment would start in OpReg if it
2791     // extended infinitely in both directions.
2792     int64_t ExtractOffset;
2793     uint64_t SegSize;
2794     if (OpStart < SrcStart) {
2795       ExtractOffset = 0;
2796       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
2797     } else {
2798       ExtractOffset = OpStart - SrcStart;
2799       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
2800     }
2801 
2802     Register SegReg = SrcRegs[i];
2803     if (ExtractOffset != 0 || SegSize != NarrowSize) {
2804       // A genuine extract is needed.
2805       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
2806       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
2807     }
2808 
2809     DstRegs.push_back(SegReg);
2810   }
2811 
2812   Register DstReg = MI.getOperand(0).getReg();
2813   if(MRI.getType(DstReg).isVector())
2814     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2815   else
2816     MIRBuilder.buildMerge(DstReg, DstRegs);
2817   MI.eraseFromParent();
2818   return Legalized;
2819 }
2820 
2821 LegalizerHelper::LegalizeResult
2822 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
2823                                     LLT NarrowTy) {
2824   // FIXME: Don't know how to handle secondary types yet.
2825   if (TypeIdx != 0)
2826     return UnableToLegalize;
2827 
2828   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2829   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2830 
2831   // FIXME: add support for when SizeOp0 isn't an exact multiple of
2832   // NarrowSize.
2833   if (SizeOp0 % NarrowSize != 0)
2834     return UnableToLegalize;
2835 
2836   int NumParts = SizeOp0 / NarrowSize;
2837 
2838   SmallVector<Register, 2> SrcRegs, DstRegs;
2839   SmallVector<uint64_t, 2> Indexes;
2840   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
2841 
2842   Register OpReg = MI.getOperand(2).getReg();
2843   uint64_t OpStart = MI.getOperand(3).getImm();
2844   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
2845   for (int i = 0; i < NumParts; ++i) {
2846     unsigned DstStart = i * NarrowSize;
2847 
2848     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
2849       // No part of the insert affects this subregister, forward the original.
2850       DstRegs.push_back(SrcRegs[i]);
2851       continue;
2852     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
2853       // The entire subregister is defined by this insert, forward the new
2854       // value.
2855       DstRegs.push_back(OpReg);
2856       continue;
2857     }
2858 
2859     // OpSegStart is where this destination segment would start in OpReg if it
2860     // extended infinitely in both directions.
2861     int64_t ExtractOffset, InsertOffset;
2862     uint64_t SegSize;
2863     if (OpStart < DstStart) {
2864       InsertOffset = 0;
2865       ExtractOffset = DstStart - OpStart;
2866       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
2867     } else {
2868       InsertOffset = OpStart - DstStart;
2869       ExtractOffset = 0;
2870       SegSize =
2871         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
2872     }
2873 
2874     Register SegReg = OpReg;
2875     if (ExtractOffset != 0 || SegSize != OpSize) {
2876       // A genuine extract is needed.
2877       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
2878       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
2879     }
2880 
2881     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2882     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
2883     DstRegs.push_back(DstReg);
2884   }
2885 
2886   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
2887   Register DstReg = MI.getOperand(0).getReg();
2888   if(MRI.getType(DstReg).isVector())
2889     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2890   else
2891     MIRBuilder.buildMerge(DstReg, DstRegs);
2892   MI.eraseFromParent();
2893   return Legalized;
2894 }
2895 
2896 LegalizerHelper::LegalizeResult
2897 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
2898                                    LLT NarrowTy) {
2899   Register DstReg = MI.getOperand(0).getReg();
2900   LLT DstTy = MRI.getType(DstReg);
2901 
2902   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
2903 
2904   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
2905   SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
2906   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
2907   LLT LeftoverTy;
2908   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
2909                     Src0Regs, Src0LeftoverRegs))
2910     return UnableToLegalize;
2911 
2912   LLT Unused;
2913   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
2914                     Src1Regs, Src1LeftoverRegs))
2915     llvm_unreachable("inconsistent extractParts result");
2916 
2917   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
2918     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
2919                                         {Src0Regs[I], Src1Regs[I]});
2920     DstRegs.push_back(Inst->getOperand(0).getReg());
2921   }
2922 
2923   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
2924     auto Inst = MIRBuilder.buildInstr(
2925       MI.getOpcode(),
2926       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
2927     DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
2928   }
2929 
2930   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
2931               LeftoverTy, DstLeftoverRegs);
2932 
2933   MI.eraseFromParent();
2934   return Legalized;
2935 }
2936 
2937 LegalizerHelper::LegalizeResult
2938 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
2939                                     LLT NarrowTy) {
2940   if (TypeIdx != 0)
2941     return UnableToLegalize;
2942 
2943   Register CondReg = MI.getOperand(1).getReg();
2944   LLT CondTy = MRI.getType(CondReg);
2945   if (CondTy.isVector()) // TODO: Handle vselect
2946     return UnableToLegalize;
2947 
2948   Register DstReg = MI.getOperand(0).getReg();
2949   LLT DstTy = MRI.getType(DstReg);
2950 
2951   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
2952   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
2953   SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
2954   LLT LeftoverTy;
2955   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
2956                     Src1Regs, Src1LeftoverRegs))
2957     return UnableToLegalize;
2958 
2959   LLT Unused;
2960   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
2961                     Src2Regs, Src2LeftoverRegs))
2962     llvm_unreachable("inconsistent extractParts result");
2963 
2964   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
2965     auto Select = MIRBuilder.buildSelect(NarrowTy,
2966                                          CondReg, Src1Regs[I], Src2Regs[I]);
2967     DstRegs.push_back(Select->getOperand(0).getReg());
2968   }
2969 
2970   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
2971     auto Select = MIRBuilder.buildSelect(
2972       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
2973     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
2974   }
2975 
2976   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
2977               LeftoverTy, DstLeftoverRegs);
2978 
2979   MI.eraseFromParent();
2980   return Legalized;
2981 }
2982 
2983 LegalizerHelper::LegalizeResult
2984 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
2985   unsigned Opc = MI.getOpcode();
2986   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
2987   auto isSupported = [this](const LegalityQuery &Q) {
2988     auto QAction = LI.getAction(Q).Action;
2989     return QAction == Legal || QAction == Libcall || QAction == Custom;
2990   };
2991   switch (Opc) {
2992   default:
2993     return UnableToLegalize;
2994   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
2995     // This trivially expands to CTLZ.
2996     Observer.changingInstr(MI);
2997     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
2998     Observer.changedInstr(MI);
2999     return Legalized;
3000   }
3001   case TargetOpcode::G_CTLZ: {
3002     Register SrcReg = MI.getOperand(1).getReg();
3003     unsigned Len = Ty.getSizeInBits();
3004     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
3005       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
3006       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
3007                                              {Ty}, {SrcReg});
3008       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3009       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3010       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3011                                           SrcReg, MIBZero);
3012       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3013                              MIBCtlzZU);
3014       MI.eraseFromParent();
3015       return Legalized;
3016     }
3017     // for now, we do this:
3018     // NewLen = NextPowerOf2(Len);
3019     // x = x | (x >> 1);
3020     // x = x | (x >> 2);
3021     // ...
3022     // x = x | (x >>16);
3023     // x = x | (x >>32); // for 64-bit input
3024     // Upto NewLen/2
3025     // return Len - popcount(x);
3026     //
3027     // Ref: "Hacker's Delight" by Henry Warren
3028     Register Op = SrcReg;
3029     unsigned NewLen = PowerOf2Ceil(Len);
3030     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
3031       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
3032       auto MIBOp = MIRBuilder.buildInstr(
3033           TargetOpcode::G_OR, {Ty},
3034           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
3035                                      {Op, MIBShiftAmt})});
3036       Op = MIBOp->getOperand(0).getReg();
3037     }
3038     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
3039     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3040                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
3041     MI.eraseFromParent();
3042     return Legalized;
3043   }
3044   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
3045     // This trivially expands to CTTZ.
3046     Observer.changingInstr(MI);
3047     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
3048     Observer.changedInstr(MI);
3049     return Legalized;
3050   }
3051   case TargetOpcode::G_CTTZ: {
3052     Register SrcReg = MI.getOperand(1).getReg();
3053     unsigned Len = Ty.getSizeInBits();
3054     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
3055       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
3056       // zero.
3057       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
3058                                              {Ty}, {SrcReg});
3059       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3060       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3061       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3062                                           SrcReg, MIBZero);
3063       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3064                              MIBCttzZU);
3065       MI.eraseFromParent();
3066       return Legalized;
3067     }
3068     // for now, we use: { return popcount(~x & (x - 1)); }
3069     // unless the target has ctlz but not ctpop, in which case we use:
3070     // { return 32 - nlz(~x & (x-1)); }
3071     // Ref: "Hacker's Delight" by Henry Warren
3072     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
3073     auto MIBNot =
3074         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
3075     auto MIBTmp = MIRBuilder.buildInstr(
3076         TargetOpcode::G_AND, {Ty},
3077         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
3078                                        {SrcReg, MIBCstNeg1})});
3079     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
3080         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
3081       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
3082       MIRBuilder.buildInstr(
3083           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3084           {MIBCstLen,
3085            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
3086       MI.eraseFromParent();
3087       return Legalized;
3088     }
3089     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
3090     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3091     return Legalized;
3092   }
3093   }
3094 }
3095 
3096 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
3097 // representation.
3098 LegalizerHelper::LegalizeResult
3099 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
3100   Register Dst = MI.getOperand(0).getReg();
3101   Register Src = MI.getOperand(1).getReg();
3102   const LLT S64 = LLT::scalar(64);
3103   const LLT S32 = LLT::scalar(32);
3104   const LLT S1 = LLT::scalar(1);
3105 
3106   assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
3107 
3108   // unsigned cul2f(ulong u) {
3109   //   uint lz = clz(u);
3110   //   uint e = (u != 0) ? 127U + 63U - lz : 0;
3111   //   u = (u << lz) & 0x7fffffffffffffffUL;
3112   //   ulong t = u & 0xffffffffffUL;
3113   //   uint v = (e << 23) | (uint)(u >> 40);
3114   //   uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
3115   //   return as_float(v + r);
3116   // }
3117 
3118   auto Zero32 = MIRBuilder.buildConstant(S32, 0);
3119   auto Zero64 = MIRBuilder.buildConstant(S64, 0);
3120 
3121   auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
3122 
3123   auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
3124   auto Sub = MIRBuilder.buildSub(S32, K, LZ);
3125 
3126   auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
3127   auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
3128 
3129   auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
3130   auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
3131 
3132   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
3133 
3134   auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
3135   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
3136 
3137   auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
3138   auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
3139   auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
3140 
3141   auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
3142   auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
3143   auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
3144   auto One = MIRBuilder.buildConstant(S32, 1);
3145 
3146   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
3147   auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
3148   auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
3149   MIRBuilder.buildAdd(Dst, V, R);
3150 
3151   return Legalized;
3152 }
3153 
3154 LegalizerHelper::LegalizeResult
3155 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3156   Register Dst = MI.getOperand(0).getReg();
3157   Register Src = MI.getOperand(1).getReg();
3158   LLT DstTy = MRI.getType(Dst);
3159   LLT SrcTy = MRI.getType(Src);
3160 
3161   if (SrcTy != LLT::scalar(64))
3162     return UnableToLegalize;
3163 
3164   if (DstTy == LLT::scalar(32)) {
3165     // TODO: SelectionDAG has several alternative expansions to port which may
3166     // be more reasonble depending on the available instructions. If a target
3167     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
3168     // intermediate type, this is probably worse.
3169     return lowerU64ToF32BitOps(MI);
3170   }
3171 
3172   return UnableToLegalize;
3173 }
3174 
3175 LegalizerHelper::LegalizeResult
3176 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3177   Register Dst = MI.getOperand(0).getReg();
3178   Register Src = MI.getOperand(1).getReg();
3179   LLT DstTy = MRI.getType(Dst);
3180   LLT SrcTy = MRI.getType(Src);
3181 
3182   const LLT S64 = LLT::scalar(64);
3183   const LLT S32 = LLT::scalar(32);
3184   const LLT S1 = LLT::scalar(1);
3185 
3186   if (SrcTy != S64)
3187     return UnableToLegalize;
3188 
3189   if (DstTy == S32) {
3190     // signed cl2f(long l) {
3191     //   long s = l >> 63;
3192     //   float r = cul2f((l + s) ^ s);
3193     //   return s ? -r : r;
3194     // }
3195     Register L = Src;
3196     auto SignBit = MIRBuilder.buildConstant(S64, 63);
3197     auto S = MIRBuilder.buildAShr(S64, L, SignBit);
3198 
3199     auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
3200     auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
3201     auto R = MIRBuilder.buildUITOFP(S32, Xor);
3202 
3203     auto RNeg = MIRBuilder.buildFNeg(S32, R);
3204     auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
3205                                             MIRBuilder.buildConstant(S64, 0));
3206     MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
3207     return Legalized;
3208   }
3209 
3210   return UnableToLegalize;
3211 }
3212 
3213 static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
3214   switch (Opc) {
3215   case TargetOpcode::G_SMIN:
3216     return CmpInst::ICMP_SLT;
3217   case TargetOpcode::G_SMAX:
3218     return CmpInst::ICMP_SGT;
3219   case TargetOpcode::G_UMIN:
3220     return CmpInst::ICMP_ULT;
3221   case TargetOpcode::G_UMAX:
3222     return CmpInst::ICMP_UGT;
3223   default:
3224     llvm_unreachable("not in integer min/max");
3225   }
3226 }
3227 
3228 LegalizerHelper::LegalizeResult
3229 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3230   Register Dst = MI.getOperand(0).getReg();
3231   Register Src0 = MI.getOperand(1).getReg();
3232   Register Src1 = MI.getOperand(2).getReg();
3233 
3234   const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
3235   LLT CmpType = MRI.getType(Dst).changeElementSize(1);
3236 
3237   auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
3238   MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
3239 
3240   MI.eraseFromParent();
3241   return Legalized;
3242 }
3243 
3244 LegalizerHelper::LegalizeResult
3245 LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3246   Register Dst = MI.getOperand(0).getReg();
3247   Register Src0 = MI.getOperand(1).getReg();
3248   Register Src1 = MI.getOperand(2).getReg();
3249 
3250   const LLT Src0Ty = MRI.getType(Src0);
3251   const LLT Src1Ty = MRI.getType(Src1);
3252 
3253   const int Src0Size = Src0Ty.getScalarSizeInBits();
3254   const int Src1Size = Src1Ty.getScalarSizeInBits();
3255 
3256   auto SignBitMask = MIRBuilder.buildConstant(
3257     Src0Ty, APInt::getSignMask(Src0Size));
3258 
3259   auto NotSignBitMask = MIRBuilder.buildConstant(
3260     Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
3261 
3262   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
3263   MachineInstr *Or;
3264 
3265   if (Src0Ty == Src1Ty) {
3266     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
3267     Or = MIRBuilder.buildOr(Dst, And0, And1);
3268   } else if (Src0Size > Src1Size) {
3269     auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
3270     auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
3271     auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
3272     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
3273     Or = MIRBuilder.buildOr(Dst, And0, And1);
3274   } else {
3275     auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
3276     auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
3277     auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
3278     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
3279     Or = MIRBuilder.buildOr(Dst, And0, And1);
3280   }
3281 
3282   // Be careful about setting nsz/nnan/ninf on every instruction, since the
3283   // constants are a nan and -0.0, but the final result should preserve
3284   // everything.
3285   if (unsigned Flags = MI.getFlags())
3286     Or->setFlags(Flags);
3287 
3288   MI.eraseFromParent();
3289   return Legalized;
3290 }
3291 
3292 LegalizerHelper::LegalizeResult
3293 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
3294   unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ?
3295     TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE;
3296 
3297   Register Dst = MI.getOperand(0).getReg();
3298   Register Src0 = MI.getOperand(1).getReg();
3299   Register Src1 = MI.getOperand(2).getReg();
3300   LLT Ty = MRI.getType(Dst);
3301 
3302   if (!MI.getFlag(MachineInstr::FmNoNans)) {
3303     // Insert canonicalizes if it's possible we need to quiet to get correct
3304     // sNaN behavior.
3305 
3306     // Note this must be done here, and not as an optimization combine in the
3307     // absence of a dedicate quiet-snan instruction as we're using an
3308     // omni-purpose G_FCANONICALIZE.
3309     if (!isKnownNeverSNaN(Src0, MRI))
3310       Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0);
3311 
3312     if (!isKnownNeverSNaN(Src1, MRI))
3313       Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0);
3314   }
3315 
3316   // If there are no nans, it's safe to simply replace this with the non-IEEE
3317   // version.
3318   MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags());
3319   MI.eraseFromParent();
3320   return Legalized;
3321 }
3322