1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file implements the LegalizerHelper class to legalize
11 /// individual instructions and the LegalizeMachineIR wrapper pass for the
12 /// primary legalization.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
17 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
18 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
19 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetLowering.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 
28 #define DEBUG_TYPE "legalizer"
29 
30 using namespace llvm;
31 using namespace LegalizeActions;
32 
33 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
34                                  GISelChangeObserver &Observer)
35     : MRI(MF.getRegInfo()), LI(*MF.getSubtarget().getLegalizerInfo()),
36       Observer(Observer) {
37   MIRBuilder.setMF(MF);
38   MIRBuilder.setChangeObserver(Observer);
39 }
40 
41 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
42                                  GISelChangeObserver &Observer)
43     : MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
44   MIRBuilder.setMF(MF);
45   MIRBuilder.setChangeObserver(Observer);
46 }
47 LegalizerHelper::LegalizeResult
48 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
49   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
50 
51   auto Step = LI.getAction(MI, MRI);
52   switch (Step.Action) {
53   case Legal:
54     LLVM_DEBUG(dbgs() << ".. Already legal\n");
55     return AlreadyLegal;
56   case Libcall:
57     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
58     return libcall(MI);
59   case NarrowScalar:
60     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
61     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
62   case WidenScalar:
63     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
64     return widenScalar(MI, Step.TypeIdx, Step.NewType);
65   case Lower:
66     LLVM_DEBUG(dbgs() << ".. Lower\n");
67     return lower(MI, Step.TypeIdx, Step.NewType);
68   case FewerElements:
69     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
70     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
71   case Custom:
72     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
73     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
74                                                             : UnableToLegalize;
75   default:
76     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
77     return UnableToLegalize;
78   }
79 }
80 
81 void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
82                                    SmallVectorImpl<unsigned> &VRegs) {
83   for (int i = 0; i < NumParts; ++i)
84     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
85   MIRBuilder.buildUnmerge(VRegs, Reg);
86 }
87 
88 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
89   switch (Opcode) {
90   case TargetOpcode::G_SDIV:
91     assert(Size == 32 && "Unsupported size");
92     return RTLIB::SDIV_I32;
93   case TargetOpcode::G_UDIV:
94     assert(Size == 32 && "Unsupported size");
95     return RTLIB::UDIV_I32;
96   case TargetOpcode::G_SREM:
97     assert(Size == 32 && "Unsupported size");
98     return RTLIB::SREM_I32;
99   case TargetOpcode::G_UREM:
100     assert(Size == 32 && "Unsupported size");
101     return RTLIB::UREM_I32;
102   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
103     assert(Size == 32 && "Unsupported size");
104     return RTLIB::CTLZ_I32;
105   case TargetOpcode::G_FADD:
106     assert((Size == 32 || Size == 64) && "Unsupported size");
107     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
108   case TargetOpcode::G_FSUB:
109     assert((Size == 32 || Size == 64) && "Unsupported size");
110     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
111   case TargetOpcode::G_FMUL:
112     assert((Size == 32 || Size == 64) && "Unsupported size");
113     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
114   case TargetOpcode::G_FDIV:
115     assert((Size == 32 || Size == 64) && "Unsupported size");
116     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
117   case TargetOpcode::G_FREM:
118     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
119   case TargetOpcode::G_FPOW:
120     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
121   case TargetOpcode::G_FMA:
122     assert((Size == 32 || Size == 64) && "Unsupported size");
123     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
124   }
125   llvm_unreachable("Unknown libcall function");
126 }
127 
128 LegalizerHelper::LegalizeResult
129 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
130                     const CallLowering::ArgInfo &Result,
131                     ArrayRef<CallLowering::ArgInfo> Args) {
132   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
133   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
134   const char *Name = TLI.getLibcallName(Libcall);
135 
136   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
137   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
138                      MachineOperand::CreateES(Name), Result, Args))
139     return LegalizerHelper::UnableToLegalize;
140 
141   return LegalizerHelper::Legalized;
142 }
143 
144 // Useful for libcalls where all operands have the same type.
145 static LegalizerHelper::LegalizeResult
146 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
147               Type *OpType) {
148   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
149 
150   SmallVector<CallLowering::ArgInfo, 3> Args;
151   for (unsigned i = 1; i < MI.getNumOperands(); i++)
152     Args.push_back({MI.getOperand(i).getReg(), OpType});
153   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
154                        Args);
155 }
156 
157 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
158                                        Type *FromType) {
159   auto ToMVT = MVT::getVT(ToType);
160   auto FromMVT = MVT::getVT(FromType);
161 
162   switch (Opcode) {
163   case TargetOpcode::G_FPEXT:
164     return RTLIB::getFPEXT(FromMVT, ToMVT);
165   case TargetOpcode::G_FPTRUNC:
166     return RTLIB::getFPROUND(FromMVT, ToMVT);
167   case TargetOpcode::G_FPTOSI:
168     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
169   case TargetOpcode::G_FPTOUI:
170     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
171   case TargetOpcode::G_SITOFP:
172     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
173   case TargetOpcode::G_UITOFP:
174     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
175   }
176   llvm_unreachable("Unsupported libcall function");
177 }
178 
179 static LegalizerHelper::LegalizeResult
180 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
181                   Type *FromType) {
182   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
183   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
184                        {{MI.getOperand(1).getReg(), FromType}});
185 }
186 
187 LegalizerHelper::LegalizeResult
188 LegalizerHelper::libcall(MachineInstr &MI) {
189   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
190   unsigned Size = LLTy.getSizeInBits();
191   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
192 
193   MIRBuilder.setInstr(MI);
194 
195   switch (MI.getOpcode()) {
196   default:
197     return UnableToLegalize;
198   case TargetOpcode::G_SDIV:
199   case TargetOpcode::G_UDIV:
200   case TargetOpcode::G_SREM:
201   case TargetOpcode::G_UREM:
202   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
203     Type *HLTy = Type::getInt32Ty(Ctx);
204     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
205     if (Status != Legalized)
206       return Status;
207     break;
208   }
209   case TargetOpcode::G_FADD:
210   case TargetOpcode::G_FSUB:
211   case TargetOpcode::G_FMUL:
212   case TargetOpcode::G_FDIV:
213   case TargetOpcode::G_FMA:
214   case TargetOpcode::G_FPOW:
215   case TargetOpcode::G_FREM: {
216     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
217     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
218     if (Status != Legalized)
219       return Status;
220     break;
221   }
222   case TargetOpcode::G_FPEXT: {
223     // FIXME: Support other floating point types (half, fp128 etc)
224     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
225     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
226     if (ToSize != 64 || FromSize != 32)
227       return UnableToLegalize;
228     LegalizeResult Status = conversionLibcall(
229         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
230     if (Status != Legalized)
231       return Status;
232     break;
233   }
234   case TargetOpcode::G_FPTRUNC: {
235     // FIXME: Support other floating point types (half, fp128 etc)
236     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
237     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
238     if (ToSize != 32 || FromSize != 64)
239       return UnableToLegalize;
240     LegalizeResult Status = conversionLibcall(
241         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
242     if (Status != Legalized)
243       return Status;
244     break;
245   }
246   case TargetOpcode::G_FPTOSI:
247   case TargetOpcode::G_FPTOUI: {
248     // FIXME: Support other types
249     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
250     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
251     if (ToSize != 32 || (FromSize != 32 && FromSize != 64))
252       return UnableToLegalize;
253     LegalizeResult Status = conversionLibcall(
254         MI, MIRBuilder, Type::getInt32Ty(Ctx),
255         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
256     if (Status != Legalized)
257       return Status;
258     break;
259   }
260   case TargetOpcode::G_SITOFP:
261   case TargetOpcode::G_UITOFP: {
262     // FIXME: Support other types
263     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
264     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
265     if (FromSize != 32 || (ToSize != 32 && ToSize != 64))
266       return UnableToLegalize;
267     LegalizeResult Status = conversionLibcall(
268         MI, MIRBuilder,
269         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
270         Type::getInt32Ty(Ctx));
271     if (Status != Legalized)
272       return Status;
273     break;
274   }
275   }
276 
277   MI.eraseFromParent();
278   return Legalized;
279 }
280 
281 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
282                                                               unsigned TypeIdx,
283                                                               LLT NarrowTy) {
284   // FIXME: Don't know how to handle secondary types yet.
285   if (TypeIdx != 0 && MI.getOpcode() != TargetOpcode::G_EXTRACT)
286     return UnableToLegalize;
287 
288   MIRBuilder.setInstr(MI);
289 
290   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
291   uint64_t NarrowSize = NarrowTy.getSizeInBits();
292 
293   switch (MI.getOpcode()) {
294   default:
295     return UnableToLegalize;
296   case TargetOpcode::G_IMPLICIT_DEF: {
297     // FIXME: add support for when SizeOp0 isn't an exact multiple of
298     // NarrowSize.
299     if (SizeOp0 % NarrowSize != 0)
300       return UnableToLegalize;
301     int NumParts = SizeOp0 / NarrowSize;
302 
303     SmallVector<unsigned, 2> DstRegs;
304     for (int i = 0; i < NumParts; ++i)
305       DstRegs.push_back(
306           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
307 
308     unsigned DstReg = MI.getOperand(0).getReg();
309     if(MRI.getType(DstReg).isVector())
310       MIRBuilder.buildBuildVector(DstReg, DstRegs);
311     else
312       MIRBuilder.buildMerge(DstReg, DstRegs);
313     MI.eraseFromParent();
314     return Legalized;
315   }
316   case TargetOpcode::G_ADD: {
317     // FIXME: add support for when SizeOp0 isn't an exact multiple of
318     // NarrowSize.
319     if (SizeOp0 % NarrowSize != 0)
320       return UnableToLegalize;
321     // Expand in terms of carry-setting/consuming G_ADDE instructions.
322     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
323 
324     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
325     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
326     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
327 
328     unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
329     MIRBuilder.buildConstant(CarryIn, 0);
330 
331     for (int i = 0; i < NumParts; ++i) {
332       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
333       unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
334 
335       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
336                             Src2Regs[i], CarryIn);
337 
338       DstRegs.push_back(DstReg);
339       CarryIn = CarryOut;
340     }
341     unsigned DstReg = MI.getOperand(0).getReg();
342     if(MRI.getType(DstReg).isVector())
343       MIRBuilder.buildBuildVector(DstReg, DstRegs);
344     else
345       MIRBuilder.buildMerge(DstReg, DstRegs);
346     MI.eraseFromParent();
347     return Legalized;
348   }
349   case TargetOpcode::G_EXTRACT: {
350     if (TypeIdx != 1)
351       return UnableToLegalize;
352 
353     int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
354     // FIXME: add support for when SizeOp1 isn't an exact multiple of
355     // NarrowSize.
356     if (SizeOp1 % NarrowSize != 0)
357       return UnableToLegalize;
358     int NumParts = SizeOp1 / NarrowSize;
359 
360     SmallVector<unsigned, 2> SrcRegs, DstRegs;
361     SmallVector<uint64_t, 2> Indexes;
362     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
363 
364     unsigned OpReg = MI.getOperand(0).getReg();
365     uint64_t OpStart = MI.getOperand(2).getImm();
366     uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
367     for (int i = 0; i < NumParts; ++i) {
368       unsigned SrcStart = i * NarrowSize;
369 
370       if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
371         // No part of the extract uses this subregister, ignore it.
372         continue;
373       } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
374         // The entire subregister is extracted, forward the value.
375         DstRegs.push_back(SrcRegs[i]);
376         continue;
377       }
378 
379       // OpSegStart is where this destination segment would start in OpReg if it
380       // extended infinitely in both directions.
381       int64_t ExtractOffset;
382       uint64_t SegSize;
383       if (OpStart < SrcStart) {
384         ExtractOffset = 0;
385         SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
386       } else {
387         ExtractOffset = OpStart - SrcStart;
388         SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
389       }
390 
391       unsigned SegReg = SrcRegs[i];
392       if (ExtractOffset != 0 || SegSize != NarrowSize) {
393         // A genuine extract is needed.
394         SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
395         MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
396       }
397 
398       DstRegs.push_back(SegReg);
399     }
400 
401     unsigned DstReg = MI.getOperand(0).getReg();
402     if(MRI.getType(DstReg).isVector())
403       MIRBuilder.buildBuildVector(DstReg, DstRegs);
404     else
405       MIRBuilder.buildMerge(DstReg, DstRegs);
406     MI.eraseFromParent();
407     return Legalized;
408   }
409   case TargetOpcode::G_INSERT: {
410     // FIXME: add support for when SizeOp0 isn't an exact multiple of
411     // NarrowSize.
412     if (SizeOp0 % NarrowSize != 0)
413       return UnableToLegalize;
414 
415     int NumParts = SizeOp0 / NarrowSize;
416 
417     SmallVector<unsigned, 2> SrcRegs, DstRegs;
418     SmallVector<uint64_t, 2> Indexes;
419     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
420 
421     unsigned OpReg = MI.getOperand(2).getReg();
422     uint64_t OpStart = MI.getOperand(3).getImm();
423     uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
424     for (int i = 0; i < NumParts; ++i) {
425       unsigned DstStart = i * NarrowSize;
426 
427       if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
428         // No part of the insert affects this subregister, forward the original.
429         DstRegs.push_back(SrcRegs[i]);
430         continue;
431       } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
432         // The entire subregister is defined by this insert, forward the new
433         // value.
434         DstRegs.push_back(OpReg);
435         continue;
436       }
437 
438       // OpSegStart is where this destination segment would start in OpReg if it
439       // extended infinitely in both directions.
440       int64_t ExtractOffset, InsertOffset;
441       uint64_t SegSize;
442       if (OpStart < DstStart) {
443         InsertOffset = 0;
444         ExtractOffset = DstStart - OpStart;
445         SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
446       } else {
447         InsertOffset = OpStart - DstStart;
448         ExtractOffset = 0;
449         SegSize =
450             std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
451       }
452 
453       unsigned SegReg = OpReg;
454       if (ExtractOffset != 0 || SegSize != OpSize) {
455         // A genuine extract is needed.
456         SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
457         MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
458       }
459 
460       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
461       MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
462       DstRegs.push_back(DstReg);
463     }
464 
465     assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
466     unsigned DstReg = MI.getOperand(0).getReg();
467     if(MRI.getType(DstReg).isVector())
468       MIRBuilder.buildBuildVector(DstReg, DstRegs);
469     else
470       MIRBuilder.buildMerge(DstReg, DstRegs);
471     MI.eraseFromParent();
472     return Legalized;
473   }
474   case TargetOpcode::G_LOAD: {
475     // FIXME: add support for when SizeOp0 isn't an exact multiple of
476     // NarrowSize.
477     if (SizeOp0 % NarrowSize != 0)
478       return UnableToLegalize;
479 
480     const auto &MMO = **MI.memoperands_begin();
481     // This implementation doesn't work for atomics. Give up instead of doing
482     // something invalid.
483     if (MMO.getOrdering() != AtomicOrdering::NotAtomic ||
484         MMO.getFailureOrdering() != AtomicOrdering::NotAtomic)
485       return UnableToLegalize;
486 
487     int NumParts = SizeOp0 / NarrowSize;
488     LLT OffsetTy = LLT::scalar(
489         MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
490 
491     SmallVector<unsigned, 2> DstRegs;
492     for (int i = 0; i < NumParts; ++i) {
493       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
494       unsigned SrcReg = 0;
495       unsigned Adjustment = i * NarrowSize / 8;
496       unsigned Alignment = MinAlign(MMO.getAlignment(), Adjustment);
497 
498       MachineMemOperand *SplitMMO = MIRBuilder.getMF().getMachineMemOperand(
499           MMO.getPointerInfo().getWithOffset(Adjustment), MMO.getFlags(),
500           NarrowSize / 8, Alignment, MMO.getAAInfo(), MMO.getRanges(),
501           MMO.getSyncScopeID(), MMO.getOrdering(), MMO.getFailureOrdering());
502 
503       MIRBuilder.materializeGEP(SrcReg, MI.getOperand(1).getReg(), OffsetTy,
504                                 Adjustment);
505 
506       MIRBuilder.buildLoad(DstReg, SrcReg, *SplitMMO);
507 
508       DstRegs.push_back(DstReg);
509     }
510     unsigned DstReg = MI.getOperand(0).getReg();
511     if(MRI.getType(DstReg).isVector())
512       MIRBuilder.buildBuildVector(DstReg, DstRegs);
513     else
514       MIRBuilder.buildMerge(DstReg, DstRegs);
515     MI.eraseFromParent();
516     return Legalized;
517   }
518   case TargetOpcode::G_STORE: {
519     // FIXME: add support for when SizeOp0 isn't an exact multiple of
520     // NarrowSize.
521     if (SizeOp0 % NarrowSize != 0)
522       return UnableToLegalize;
523 
524     const auto &MMO = **MI.memoperands_begin();
525     // This implementation doesn't work for atomics. Give up instead of doing
526     // something invalid.
527     if (MMO.getOrdering() != AtomicOrdering::NotAtomic ||
528         MMO.getFailureOrdering() != AtomicOrdering::NotAtomic)
529       return UnableToLegalize;
530 
531     int NumParts = SizeOp0 / NarrowSize;
532     LLT OffsetTy = LLT::scalar(
533         MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
534 
535     SmallVector<unsigned, 2> SrcRegs;
536     extractParts(MI.getOperand(0).getReg(), NarrowTy, NumParts, SrcRegs);
537 
538     for (int i = 0; i < NumParts; ++i) {
539       unsigned DstReg = 0;
540       unsigned Adjustment = i * NarrowSize / 8;
541       unsigned Alignment = MinAlign(MMO.getAlignment(), Adjustment);
542 
543       MachineMemOperand *SplitMMO = MIRBuilder.getMF().getMachineMemOperand(
544           MMO.getPointerInfo().getWithOffset(Adjustment), MMO.getFlags(),
545           NarrowSize / 8, Alignment, MMO.getAAInfo(), MMO.getRanges(),
546           MMO.getSyncScopeID(), MMO.getOrdering(), MMO.getFailureOrdering());
547 
548       MIRBuilder.materializeGEP(DstReg, MI.getOperand(1).getReg(), OffsetTy,
549                                 Adjustment);
550 
551       MIRBuilder.buildStore(SrcRegs[i], DstReg, *SplitMMO);
552     }
553     MI.eraseFromParent();
554     return Legalized;
555   }
556   case TargetOpcode::G_CONSTANT: {
557     // FIXME: add support for when SizeOp0 isn't an exact multiple of
558     // NarrowSize.
559     if (SizeOp0 % NarrowSize != 0)
560       return UnableToLegalize;
561     int NumParts = SizeOp0 / NarrowSize;
562     const APInt &Cst = MI.getOperand(1).getCImm()->getValue();
563     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
564 
565     SmallVector<unsigned, 2> DstRegs;
566     for (int i = 0; i < NumParts; ++i) {
567       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
568       ConstantInt *CI =
569           ConstantInt::get(Ctx, Cst.lshr(NarrowSize * i).trunc(NarrowSize));
570       MIRBuilder.buildConstant(DstReg, *CI);
571       DstRegs.push_back(DstReg);
572     }
573     unsigned DstReg = MI.getOperand(0).getReg();
574     if(MRI.getType(DstReg).isVector())
575       MIRBuilder.buildBuildVector(DstReg, DstRegs);
576     else
577       MIRBuilder.buildMerge(DstReg, DstRegs);
578     MI.eraseFromParent();
579     return Legalized;
580   }
581   case TargetOpcode::G_OR: {
582     // Legalize bitwise operation:
583     // A = BinOp<Ty> B, C
584     // into:
585     // B1, ..., BN = G_UNMERGE_VALUES B
586     // C1, ..., CN = G_UNMERGE_VALUES C
587     // A1 = BinOp<Ty/N> B1, C2
588     // ...
589     // AN = BinOp<Ty/N> BN, CN
590     // A = G_MERGE_VALUES A1, ..., AN
591 
592     // FIXME: add support for when SizeOp0 isn't an exact multiple of
593     // NarrowSize.
594     if (SizeOp0 % NarrowSize != 0)
595       return UnableToLegalize;
596     int NumParts = SizeOp0 / NarrowSize;
597 
598     // List the registers where the destination will be scattered.
599     SmallVector<unsigned, 2> DstRegs;
600     // List the registers where the first argument will be split.
601     SmallVector<unsigned, 2> SrcsReg1;
602     // List the registers where the second argument will be split.
603     SmallVector<unsigned, 2> SrcsReg2;
604     // Create all the temporary registers.
605     for (int i = 0; i < NumParts; ++i) {
606       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
607       unsigned SrcReg1 = MRI.createGenericVirtualRegister(NarrowTy);
608       unsigned SrcReg2 = MRI.createGenericVirtualRegister(NarrowTy);
609 
610       DstRegs.push_back(DstReg);
611       SrcsReg1.push_back(SrcReg1);
612       SrcsReg2.push_back(SrcReg2);
613     }
614     // Explode the big arguments into smaller chunks.
615     MIRBuilder.buildUnmerge(SrcsReg1, MI.getOperand(1).getReg());
616     MIRBuilder.buildUnmerge(SrcsReg2, MI.getOperand(2).getReg());
617 
618     // Do the operation on each small part.
619     for (int i = 0; i < NumParts; ++i)
620       MIRBuilder.buildOr(DstRegs[i], SrcsReg1[i], SrcsReg2[i]);
621 
622     // Gather the destination registers into the final destination.
623     unsigned DstReg = MI.getOperand(0).getReg();
624     if(MRI.getType(DstReg).isVector())
625       MIRBuilder.buildBuildVector(DstReg, DstRegs);
626     else
627       MIRBuilder.buildMerge(DstReg, DstRegs);
628     MI.eraseFromParent();
629     return Legalized;
630   }
631   }
632 }
633 
634 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
635                                      unsigned OpIdx, unsigned ExtOpcode) {
636   MachineOperand &MO = MI.getOperand(OpIdx);
637   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
638   MO.setReg(ExtB->getOperand(0).getReg());
639 }
640 
641 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
642                                      unsigned OpIdx, unsigned TruncOpcode) {
643   MachineOperand &MO = MI.getOperand(OpIdx);
644   unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
645   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
646   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
647   MO.setReg(DstExt);
648 }
649 
650 LegalizerHelper::LegalizeResult
651 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
652   MIRBuilder.setInstr(MI);
653 
654   switch (MI.getOpcode()) {
655   default:
656     return UnableToLegalize;
657   case TargetOpcode::G_UADDO:
658   case TargetOpcode::G_USUBO: {
659     if (TypeIdx == 1)
660       return UnableToLegalize; // TODO
661     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
662                                          {MI.getOperand(2).getReg()});
663     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
664                                          {MI.getOperand(3).getReg()});
665     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
666                           ? TargetOpcode::G_ADD
667                           : TargetOpcode::G_SUB;
668     // Do the arithmetic in the larger type.
669     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
670     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
671     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
672     auto AndOp = MIRBuilder.buildInstr(
673         TargetOpcode::G_AND, {WideTy},
674         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
675     // There is no overflow if the AndOp is the same as NewOp.
676     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
677                          AndOp);
678     // Now trunc the NewOp to the original result.
679     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
680     MI.eraseFromParent();
681     return Legalized;
682   }
683   case TargetOpcode::G_CTTZ:
684   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
685   case TargetOpcode::G_CTLZ:
686   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
687   case TargetOpcode::G_CTPOP: {
688     // First ZEXT the input.
689     auto MIBSrc = MIRBuilder.buildZExt(WideTy, MI.getOperand(1).getReg());
690     LLT CurTy = MRI.getType(MI.getOperand(0).getReg());
691     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
692       // The count is the same in the larger type except if the original
693       // value was zero.  This can be handled by setting the bit just off
694       // the top of the original type.
695       auto TopBit =
696           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
697       MIBSrc = MIRBuilder.buildInstr(
698           TargetOpcode::G_OR, {WideTy},
699           {MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit.getSExtValue())});
700     }
701     // Perform the operation at the larger size.
702     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
703     // This is already the correct result for CTPOP and CTTZs
704     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
705         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
706       // The correct result is NewOp - (Difference in widety and current ty).
707       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
708       MIBNewOp = MIRBuilder.buildInstr(
709           TargetOpcode::G_SUB, {WideTy},
710           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
711     }
712     auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
713     // Make the original instruction a trunc now, and update its source.
714     MI.setDesc(TII.get(TargetOpcode::G_TRUNC));
715     MI.getOperand(1).setReg(MIBNewOp->getOperand(0).getReg());
716     Observer.changedInstr(MI);
717     return Legalized;
718   }
719 
720   case TargetOpcode::G_ADD:
721   case TargetOpcode::G_AND:
722   case TargetOpcode::G_MUL:
723   case TargetOpcode::G_OR:
724   case TargetOpcode::G_XOR:
725   case TargetOpcode::G_SUB:
726     // Perform operation at larger width (any extension is fine here, high bits
727     // don't affect the result) and then truncate the result back to the
728     // original type.
729     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
730     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
731     widenScalarDst(MI, WideTy);
732     Observer.changedInstr(MI);
733     return Legalized;
734 
735   case TargetOpcode::G_SHL:
736     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
737     // The "number of bits to shift" operand must preserve its value as an
738     // unsigned integer:
739     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
740     widenScalarDst(MI, WideTy);
741     Observer.changedInstr(MI);
742     return Legalized;
743 
744   case TargetOpcode::G_SDIV:
745   case TargetOpcode::G_SREM:
746     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
747     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
748     widenScalarDst(MI, WideTy);
749     Observer.changedInstr(MI);
750     return Legalized;
751 
752   case TargetOpcode::G_ASHR:
753     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
754     // The "number of bits to shift" operand must preserve its value as an
755     // unsigned integer:
756     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
757     widenScalarDst(MI, WideTy);
758     Observer.changedInstr(MI);
759     return Legalized;
760 
761   case TargetOpcode::G_UDIV:
762   case TargetOpcode::G_UREM:
763   case TargetOpcode::G_LSHR:
764     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
765     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
766     widenScalarDst(MI, WideTy);
767     Observer.changedInstr(MI);
768     return Legalized;
769 
770   case TargetOpcode::G_SELECT:
771     if (TypeIdx != 0)
772       return UnableToLegalize;
773     // Perform operation at larger width (any extension is fine here, high bits
774     // don't affect the result) and then truncate the result back to the
775     // original type.
776     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
777     widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
778     widenScalarDst(MI, WideTy);
779     Observer.changedInstr(MI);
780     return Legalized;
781 
782   case TargetOpcode::G_FPTOSI:
783   case TargetOpcode::G_FPTOUI:
784     if (TypeIdx != 0)
785       return UnableToLegalize;
786     widenScalarDst(MI, WideTy);
787     Observer.changedInstr(MI);
788     return Legalized;
789 
790   case TargetOpcode::G_SITOFP:
791     if (TypeIdx != 1)
792       return UnableToLegalize;
793     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
794     Observer.changedInstr(MI);
795     return Legalized;
796 
797   case TargetOpcode::G_UITOFP:
798     if (TypeIdx != 1)
799       return UnableToLegalize;
800     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
801     Observer.changedInstr(MI);
802     return Legalized;
803 
804   case TargetOpcode::G_INSERT:
805     if (TypeIdx != 0)
806       return UnableToLegalize;
807     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
808     widenScalarDst(MI, WideTy);
809     Observer.changedInstr(MI);
810     return Legalized;
811 
812   case TargetOpcode::G_LOAD:
813     // For some types like i24, we might try to widen to i32. To properly handle
814     // this we should be using a dedicated extending load, until then avoid
815     // trying to legalize.
816     if (alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) !=
817         WideTy.getSizeInBits())
818       return UnableToLegalize;
819     LLVM_FALLTHROUGH;
820   case TargetOpcode::G_SEXTLOAD:
821   case TargetOpcode::G_ZEXTLOAD:
822     widenScalarDst(MI, WideTy);
823     Observer.changedInstr(MI);
824     return Legalized;
825 
826   case TargetOpcode::G_STORE: {
827     if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(1) ||
828         WideTy != LLT::scalar(8))
829       return UnableToLegalize;
830 
831     widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ZEXT);
832     Observer.changedInstr(MI);
833     return Legalized;
834   }
835   case TargetOpcode::G_CONSTANT: {
836     MachineOperand &SrcMO = MI.getOperand(1);
837     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
838     const APInt &Val = SrcMO.getCImm()->getValue().sext(WideTy.getSizeInBits());
839     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
840 
841     widenScalarDst(MI, WideTy);
842     Observer.changedInstr(MI);
843     return Legalized;
844   }
845   case TargetOpcode::G_FCONSTANT: {
846     MachineOperand &SrcMO = MI.getOperand(1);
847     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
848     APFloat Val = SrcMO.getFPImm()->getValueAPF();
849     bool LosesInfo;
850     switch (WideTy.getSizeInBits()) {
851     case 32:
852       Val.convert(APFloat::IEEEsingle(), APFloat::rmTowardZero, &LosesInfo);
853       break;
854     case 64:
855       Val.convert(APFloat::IEEEdouble(), APFloat::rmTowardZero, &LosesInfo);
856       break;
857     default:
858       llvm_unreachable("Unhandled fp widen type");
859     }
860     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
861 
862     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
863     Observer.changedInstr(MI);
864     return Legalized;
865   }
866   case TargetOpcode::G_BRCOND:
867     widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ANYEXT);
868     Observer.changedInstr(MI);
869     return Legalized;
870 
871   case TargetOpcode::G_FCMP:
872     if (TypeIdx == 0)
873       widenScalarDst(MI, WideTy);
874     else {
875       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
876       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
877     }
878     Observer.changedInstr(MI);
879     return Legalized;
880 
881   case TargetOpcode::G_ICMP:
882     if (TypeIdx == 0)
883       widenScalarDst(MI, WideTy);
884     else {
885       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
886                                MI.getOperand(1).getPredicate()))
887                                ? TargetOpcode::G_SEXT
888                                : TargetOpcode::G_ZEXT;
889       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
890       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
891     }
892     Observer.changedInstr(MI);
893     return Legalized;
894 
895   case TargetOpcode::G_GEP:
896     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
897     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
898     Observer.changedInstr(MI);
899     return Legalized;
900 
901   case TargetOpcode::G_PHI: {
902     assert(TypeIdx == 0 && "Expecting only Idx 0");
903 
904     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
905       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
906       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
907       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
908     }
909 
910     MachineBasicBlock &MBB = *MI.getParent();
911     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
912     widenScalarDst(MI, WideTy);
913     Observer.changedInstr(MI);
914     return Legalized;
915   }
916   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
917     if (TypeIdx != 2)
918       return UnableToLegalize;
919     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
920     Observer.changedInstr(MI);
921     return Legalized;
922   }
923 }
924 
925 LegalizerHelper::LegalizeResult
926 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
927   using namespace TargetOpcode;
928   MIRBuilder.setInstr(MI);
929 
930   switch(MI.getOpcode()) {
931   default:
932     return UnableToLegalize;
933   case TargetOpcode::G_SREM:
934   case TargetOpcode::G_UREM: {
935     unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
936     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
937         .addDef(QuotReg)
938         .addUse(MI.getOperand(1).getReg())
939         .addUse(MI.getOperand(2).getReg());
940 
941     unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
942     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
943     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
944                         ProdReg);
945     MI.eraseFromParent();
946     return Legalized;
947   }
948   case TargetOpcode::G_SMULO:
949   case TargetOpcode::G_UMULO: {
950     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
951     // result.
952     unsigned Res = MI.getOperand(0).getReg();
953     unsigned Overflow = MI.getOperand(1).getReg();
954     unsigned LHS = MI.getOperand(2).getReg();
955     unsigned RHS = MI.getOperand(3).getReg();
956 
957     MIRBuilder.buildMul(Res, LHS, RHS);
958 
959     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
960                           ? TargetOpcode::G_SMULH
961                           : TargetOpcode::G_UMULH;
962 
963     unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
964     MIRBuilder.buildInstr(Opcode)
965       .addDef(HiPart)
966       .addUse(LHS)
967       .addUse(RHS);
968 
969     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
970     MIRBuilder.buildConstant(Zero, 0);
971 
972     // For *signed* multiply, overflow is detected by checking:
973     // (hi != (lo >> bitwidth-1))
974     if (Opcode == TargetOpcode::G_SMULH) {
975       unsigned Shifted = MRI.createGenericVirtualRegister(Ty);
976       unsigned ShiftAmt = MRI.createGenericVirtualRegister(Ty);
977       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
978       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
979         .addDef(Shifted)
980         .addUse(Res)
981         .addUse(ShiftAmt);
982       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
983     } else {
984       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
985     }
986     MI.eraseFromParent();
987     return Legalized;
988   }
989   case TargetOpcode::G_FNEG: {
990     // TODO: Handle vector types once we are able to
991     // represent them.
992     if (Ty.isVector())
993       return UnableToLegalize;
994     unsigned Res = MI.getOperand(0).getReg();
995     Type *ZeroTy;
996     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
997     switch (Ty.getSizeInBits()) {
998     case 16:
999       ZeroTy = Type::getHalfTy(Ctx);
1000       break;
1001     case 32:
1002       ZeroTy = Type::getFloatTy(Ctx);
1003       break;
1004     case 64:
1005       ZeroTy = Type::getDoubleTy(Ctx);
1006       break;
1007     case 128:
1008       ZeroTy = Type::getFP128Ty(Ctx);
1009       break;
1010     default:
1011       llvm_unreachable("unexpected floating-point type");
1012     }
1013     ConstantFP &ZeroForNegation =
1014         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
1015     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
1016     MIRBuilder.buildInstr(TargetOpcode::G_FSUB)
1017         .addDef(Res)
1018         .addUse(Zero->getOperand(0).getReg())
1019         .addUse(MI.getOperand(1).getReg());
1020     MI.eraseFromParent();
1021     return Legalized;
1022   }
1023   case TargetOpcode::G_FSUB: {
1024     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
1025     // First, check if G_FNEG is marked as Lower. If so, we may
1026     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
1027     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
1028       return UnableToLegalize;
1029     unsigned Res = MI.getOperand(0).getReg();
1030     unsigned LHS = MI.getOperand(1).getReg();
1031     unsigned RHS = MI.getOperand(2).getReg();
1032     unsigned Neg = MRI.createGenericVirtualRegister(Ty);
1033     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
1034     MIRBuilder.buildInstr(TargetOpcode::G_FADD)
1035         .addDef(Res)
1036         .addUse(LHS)
1037         .addUse(Neg);
1038     MI.eraseFromParent();
1039     return Legalized;
1040   }
1041   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
1042     unsigned OldValRes = MI.getOperand(0).getReg();
1043     unsigned SuccessRes = MI.getOperand(1).getReg();
1044     unsigned Addr = MI.getOperand(2).getReg();
1045     unsigned CmpVal = MI.getOperand(3).getReg();
1046     unsigned NewVal = MI.getOperand(4).getReg();
1047     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
1048                                   **MI.memoperands_begin());
1049     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
1050     MI.eraseFromParent();
1051     return Legalized;
1052   }
1053   case TargetOpcode::G_LOAD:
1054   case TargetOpcode::G_SEXTLOAD:
1055   case TargetOpcode::G_ZEXTLOAD: {
1056     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
1057     unsigned DstReg = MI.getOperand(0).getReg();
1058     unsigned PtrReg = MI.getOperand(1).getReg();
1059     LLT DstTy = MRI.getType(DstReg);
1060     auto &MMO = **MI.memoperands_begin();
1061 
1062     if (DstTy.getSizeInBits() == MMO.getSize() /* in bytes */ * 8) {
1063       // In the case of G_LOAD, this was a non-extending load already and we're
1064       // about to lower to the same instruction.
1065       if (MI.getOpcode() == TargetOpcode::G_LOAD)
1066           return UnableToLegalize;
1067       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
1068       MI.eraseFromParent();
1069       return Legalized;
1070     }
1071 
1072     if (DstTy.isScalar()) {
1073       unsigned TmpReg = MRI.createGenericVirtualRegister(
1074           LLT::scalar(MMO.getSize() /* in bytes */ * 8));
1075       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
1076       switch (MI.getOpcode()) {
1077       default:
1078         llvm_unreachable("Unexpected opcode");
1079       case TargetOpcode::G_LOAD:
1080         MIRBuilder.buildAnyExt(DstReg, TmpReg);
1081         break;
1082       case TargetOpcode::G_SEXTLOAD:
1083         MIRBuilder.buildSExt(DstReg, TmpReg);
1084         break;
1085       case TargetOpcode::G_ZEXTLOAD:
1086         MIRBuilder.buildZExt(DstReg, TmpReg);
1087         break;
1088       }
1089       MI.eraseFromParent();
1090       return Legalized;
1091     }
1092 
1093     return UnableToLegalize;
1094   }
1095   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1096   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1097   case TargetOpcode::G_CTLZ:
1098   case TargetOpcode::G_CTTZ:
1099   case TargetOpcode::G_CTPOP:
1100     return lowerBitCount(MI, TypeIdx, Ty);
1101   }
1102 }
1103 
1104 LegalizerHelper::LegalizeResult
1105 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
1106                                      LLT NarrowTy) {
1107   // FIXME: Don't know how to handle secondary types yet.
1108   if (TypeIdx != 0)
1109     return UnableToLegalize;
1110   switch (MI.getOpcode()) {
1111   default:
1112     return UnableToLegalize;
1113   case TargetOpcode::G_ADD: {
1114     unsigned NarrowSize = NarrowTy.getSizeInBits();
1115     unsigned DstReg = MI.getOperand(0).getReg();
1116     unsigned Size = MRI.getType(DstReg).getSizeInBits();
1117     int NumParts = Size / NarrowSize;
1118     // FIXME: Don't know how to handle the situation where the small vectors
1119     // aren't all the same size yet.
1120     if (Size % NarrowSize != 0)
1121       return UnableToLegalize;
1122 
1123     MIRBuilder.setInstr(MI);
1124 
1125     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
1126     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
1127     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
1128 
1129     for (int i = 0; i < NumParts; ++i) {
1130       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
1131       MIRBuilder.buildAdd(DstReg, Src1Regs[i], Src2Regs[i]);
1132       DstRegs.push_back(DstReg);
1133     }
1134 
1135     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1136     MI.eraseFromParent();
1137     return Legalized;
1138   }
1139   }
1140 }
1141 
1142 LegalizerHelper::LegalizeResult
1143 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1144   unsigned Opc = MI.getOpcode();
1145   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
1146   auto isSupported = [this](const LegalityQuery &Q) {
1147     auto QAction = LI.getAction(Q).Action;
1148     return QAction == Legal || QAction == Libcall || QAction == Custom;
1149   };
1150   switch (Opc) {
1151   default:
1152     return UnableToLegalize;
1153   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
1154     // This trivially expands to CTLZ.
1155     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
1156     Observer.changedInstr(MI);
1157     return Legalized;
1158   }
1159   case TargetOpcode::G_CTLZ: {
1160     unsigned SrcReg = MI.getOperand(1).getReg();
1161     unsigned Len = Ty.getSizeInBits();
1162     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty}})) {
1163       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
1164       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
1165                                              {Ty}, {SrcReg});
1166       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
1167       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
1168       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
1169                                           SrcReg, MIBZero);
1170       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
1171                              MIBCtlzZU);
1172       MI.eraseFromParent();
1173       return Legalized;
1174     }
1175     // for now, we do this:
1176     // NewLen = NextPowerOf2(Len);
1177     // x = x | (x >> 1);
1178     // x = x | (x >> 2);
1179     // ...
1180     // x = x | (x >>16);
1181     // x = x | (x >>32); // for 64-bit input
1182     // Upto NewLen/2
1183     // return Len - popcount(x);
1184     //
1185     // Ref: "Hacker's Delight" by Henry Warren
1186     unsigned Op = SrcReg;
1187     unsigned NewLen = PowerOf2Ceil(Len);
1188     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
1189       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
1190       auto MIBOp = MIRBuilder.buildInstr(
1191           TargetOpcode::G_OR, {Ty},
1192           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
1193                                      {Op, MIBShiftAmt})});
1194       Op = MIBOp->getOperand(0).getReg();
1195     }
1196     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
1197     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
1198                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
1199     MI.eraseFromParent();
1200     return Legalized;
1201   }
1202   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
1203     // This trivially expands to CTTZ.
1204     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
1205     Observer.changedInstr(MI);
1206     return Legalized;
1207   }
1208   case TargetOpcode::G_CTTZ: {
1209     unsigned SrcReg = MI.getOperand(1).getReg();
1210     unsigned Len = Ty.getSizeInBits();
1211     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty}})) {
1212       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
1213       // zero.
1214       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
1215                                              {Ty}, {SrcReg});
1216       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
1217       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
1218       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
1219                                           SrcReg, MIBZero);
1220       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
1221                              MIBCttzZU);
1222       MI.eraseFromParent();
1223       return Legalized;
1224     }
1225     // for now, we use: { return popcount(~x & (x - 1)); }
1226     // unless the target has ctlz but not ctpop, in which case we use:
1227     // { return 32 - nlz(~x & (x-1)); }
1228     // Ref: "Hacker's Delight" by Henry Warren
1229     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
1230     auto MIBNot =
1231         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
1232     auto MIBTmp = MIRBuilder.buildInstr(
1233         TargetOpcode::G_AND, {Ty},
1234         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
1235                                        {SrcReg, MIBCstNeg1})});
1236     if (!isSupported({TargetOpcode::G_CTPOP, {Ty}}) &&
1237         isSupported({TargetOpcode::G_CTLZ, {Ty}})) {
1238       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
1239       MIRBuilder.buildInstr(
1240           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
1241           {MIBCstLen,
1242            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
1243       MI.eraseFromParent();
1244       return Legalized;
1245     }
1246     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
1247     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
1248     return Legalized;
1249   }
1250   }
1251 }
1252