1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file implements the LegalizerHelper class to legalize
11 /// individual instructions and the LegalizeMachineIR wrapper pass for the
12 /// primary legalization.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
17 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
24 
25 #include <sstream>
26 
27 #define DEBUG_TYPE "legalizer"
28 
29 using namespace llvm;
30 
31 LegalizerHelper::LegalizerHelper(MachineFunction &MF)
32     : MRI(MF.getRegInfo()), LI(*MF.getSubtarget().getLegalizerInfo()) {
33   MIRBuilder.setMF(MF);
34 }
35 
36 LegalizerHelper::LegalizeResult
37 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
38   DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
39 
40   auto Action = LI.getAction(MI, MRI);
41   switch (std::get<0>(Action)) {
42   case LegalizerInfo::Legal:
43     DEBUG(dbgs() << ".. Already legal\n");
44     return AlreadyLegal;
45   case LegalizerInfo::Libcall:
46     DEBUG(dbgs() << ".. Convert to libcall\n");
47     return libcall(MI);
48   case LegalizerInfo::NarrowScalar:
49     DEBUG(dbgs() << ".. Narrow scalar\n");
50     return narrowScalar(MI, std::get<1>(Action), std::get<2>(Action));
51   case LegalizerInfo::WidenScalar:
52     DEBUG(dbgs() << ".. Widen scalar\n");
53     return widenScalar(MI, std::get<1>(Action), std::get<2>(Action));
54   case LegalizerInfo::Lower:
55     DEBUG(dbgs() << ".. Lower\n");
56     return lower(MI, std::get<1>(Action), std::get<2>(Action));
57   case LegalizerInfo::FewerElements:
58     DEBUG(dbgs() << ".. Reduce number of elements\n");
59     return fewerElementsVector(MI, std::get<1>(Action), std::get<2>(Action));
60   case LegalizerInfo::Custom:
61     DEBUG(dbgs() << ".. Custom legalization\n");
62     return LI.legalizeCustom(MI, MRI, MIRBuilder) ? Legalized
63                                                   : UnableToLegalize;
64   default:
65     DEBUG(dbgs() << ".. Unable to legalize\n");
66     return UnableToLegalize;
67   }
68 }
69 
70 void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
71                                    SmallVectorImpl<unsigned> &VRegs) {
72   for (int i = 0; i < NumParts; ++i)
73     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
74   MIRBuilder.buildUnmerge(VRegs, Reg);
75 }
76 
77 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
78   switch (Opcode) {
79   case TargetOpcode::G_SDIV:
80     assert(Size == 32 && "Unsupported size");
81     return RTLIB::SDIV_I32;
82   case TargetOpcode::G_UDIV:
83     assert(Size == 32 && "Unsupported size");
84     return RTLIB::UDIV_I32;
85   case TargetOpcode::G_SREM:
86     assert(Size == 32 && "Unsupported size");
87     return RTLIB::SREM_I32;
88   case TargetOpcode::G_UREM:
89     assert(Size == 32 && "Unsupported size");
90     return RTLIB::UREM_I32;
91   case TargetOpcode::G_FADD:
92     assert((Size == 32 || Size == 64) && "Unsupported size");
93     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
94   case TargetOpcode::G_FREM:
95     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
96   case TargetOpcode::G_FPOW:
97     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
98   }
99   llvm_unreachable("Unknown libcall function");
100 }
101 
102 LegalizerHelper::LegalizeResult llvm::replaceWithLibcall(
103     MachineInstr &MI, MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
104     const CallLowering::ArgInfo &Result, ArrayRef<CallLowering::ArgInfo> Args) {
105   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
106   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
107   const char *Name = TLI.getLibcallName(Libcall);
108   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
109   MIRBuilder.setInstr(MI);
110   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
111                      MachineOperand::CreateES(Name), Result, Args))
112     return LegalizerHelper::UnableToLegalize;
113 
114   // We're about to remove MI, so move the insert point after it.
115   MIRBuilder.setInsertPt(MIRBuilder.getMBB(),
116                          std::next(MIRBuilder.getInsertPt()));
117 
118   MI.eraseFromParent();
119   return LegalizerHelper::Legalized;
120 }
121 
122 static LegalizerHelper::LegalizeResult
123 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
124               Type *OpType) {
125   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
126   return replaceWithLibcall(MI, MIRBuilder, Libcall,
127                             {MI.getOperand(0).getReg(), OpType},
128                             {{MI.getOperand(1).getReg(), OpType},
129                              {MI.getOperand(2).getReg(), OpType}});
130 }
131 
132 LegalizerHelper::LegalizeResult
133 LegalizerHelper::libcall(MachineInstr &MI) {
134   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
135   unsigned Size = LLTy.getSizeInBits();
136   auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
137 
138   switch (MI.getOpcode()) {
139   default:
140     return UnableToLegalize;
141   case TargetOpcode::G_SDIV:
142   case TargetOpcode::G_UDIV:
143   case TargetOpcode::G_SREM:
144   case TargetOpcode::G_UREM: {
145     Type *HLTy = Type::getInt32Ty(Ctx);
146     return simpleLibcall(MI, MIRBuilder, Size, HLTy);
147   }
148   case TargetOpcode::G_FADD:
149   case TargetOpcode::G_FPOW:
150   case TargetOpcode::G_FREM: {
151     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
152     return simpleLibcall(MI, MIRBuilder, Size, HLTy);
153   }
154   }
155 }
156 
157 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
158                                                               unsigned TypeIdx,
159                                                               LLT NarrowTy) {
160   // FIXME: Don't know how to handle secondary types yet.
161   if (TypeIdx != 0)
162     return UnableToLegalize;
163 
164   MIRBuilder.setInstr(MI);
165 
166   switch (MI.getOpcode()) {
167   default:
168     return UnableToLegalize;
169   case TargetOpcode::G_ADD: {
170     // Expand in terms of carry-setting/consuming G_ADDE instructions.
171     int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
172                    NarrowTy.getSizeInBits();
173 
174     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
175     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
176     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
177 
178     unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
179     MIRBuilder.buildConstant(CarryIn, 0);
180 
181     for (int i = 0; i < NumParts; ++i) {
182       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
183       unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
184 
185       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
186                             Src2Regs[i], CarryIn);
187 
188       DstRegs.push_back(DstReg);
189       CarryIn = CarryOut;
190     }
191     unsigned DstReg = MI.getOperand(0).getReg();
192     MIRBuilder.buildMerge(DstReg, DstRegs);
193     MI.eraseFromParent();
194     return Legalized;
195   }
196   case TargetOpcode::G_INSERT: {
197     if (TypeIdx != 0)
198       return UnableToLegalize;
199 
200     int64_t NarrowSize = NarrowTy.getSizeInBits();
201     int NumParts =
202         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
203 
204     SmallVector<unsigned, 2> SrcRegs, DstRegs;
205     SmallVector<uint64_t, 2> Indexes;
206     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
207 
208     unsigned OpReg = MI.getOperand(2).getReg();
209     int64_t OpStart = MI.getOperand(3).getImm();
210     int64_t OpSize = MRI.getType(OpReg).getSizeInBits();
211     for (int i = 0; i < NumParts; ++i) {
212       unsigned DstStart = i * NarrowSize;
213 
214       if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
215         // No part of the insert affects this subregister, forward the original.
216         DstRegs.push_back(SrcRegs[i]);
217         continue;
218       } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
219         // The entire subregister is defined by this insert, forward the new
220         // value.
221         DstRegs.push_back(OpReg);
222         continue;
223       }
224 
225       // OpSegStart is where this destination segment would start in OpReg if it
226       // extended infinitely in both directions.
227       int64_t ExtractOffset, InsertOffset, SegSize;
228       if (OpStart < DstStart) {
229         InsertOffset = 0;
230         ExtractOffset = DstStart - OpStart;
231         SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
232       } else {
233         InsertOffset = OpStart - DstStart;
234         ExtractOffset = 0;
235         SegSize =
236             std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
237       }
238 
239       unsigned SegReg = OpReg;
240       if (ExtractOffset != 0 || SegSize != OpSize) {
241         // A genuine extract is needed.
242         SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
243         MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
244       }
245 
246       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
247       MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
248       DstRegs.push_back(DstReg);
249     }
250 
251     assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
252     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
253     MI.eraseFromParent();
254     return Legalized;
255   }
256   case TargetOpcode::G_LOAD: {
257     unsigned NarrowSize = NarrowTy.getSizeInBits();
258     int NumParts =
259         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
260     LLT OffsetTy = LLT::scalar(
261         MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
262 
263     SmallVector<unsigned, 2> DstRegs;
264     for (int i = 0; i < NumParts; ++i) {
265       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
266       unsigned SrcReg = 0;
267       unsigned Adjustment = i * NarrowSize / 8;
268 
269       MIRBuilder.materializeGEP(SrcReg, MI.getOperand(1).getReg(), OffsetTy,
270                                 Adjustment);
271 
272       // TODO: This is conservatively correct, but we probably want to split the
273       // memory operands in the future.
274       MIRBuilder.buildLoad(DstReg, SrcReg, **MI.memoperands_begin());
275 
276       DstRegs.push_back(DstReg);
277     }
278     unsigned DstReg = MI.getOperand(0).getReg();
279     MIRBuilder.buildMerge(DstReg, DstRegs);
280     MI.eraseFromParent();
281     return Legalized;
282   }
283   case TargetOpcode::G_STORE: {
284     unsigned NarrowSize = NarrowTy.getSizeInBits();
285     int NumParts =
286         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
287     LLT OffsetTy = LLT::scalar(
288         MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
289 
290     SmallVector<unsigned, 2> SrcRegs;
291     extractParts(MI.getOperand(0).getReg(), NarrowTy, NumParts, SrcRegs);
292 
293     for (int i = 0; i < NumParts; ++i) {
294       unsigned DstReg = 0;
295       unsigned Adjustment = i * NarrowSize / 8;
296 
297       MIRBuilder.materializeGEP(DstReg, MI.getOperand(1).getReg(), OffsetTy,
298                                 Adjustment);
299 
300       // TODO: This is conservatively correct, but we probably want to split the
301       // memory operands in the future.
302       MIRBuilder.buildStore(SrcRegs[i], DstReg, **MI.memoperands_begin());
303     }
304     MI.eraseFromParent();
305     return Legalized;
306   }
307   case TargetOpcode::G_CONSTANT: {
308     unsigned NarrowSize = NarrowTy.getSizeInBits();
309     int NumParts =
310         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
311     const APInt &Cst = MI.getOperand(1).getCImm()->getValue();
312     LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
313 
314     SmallVector<unsigned, 2> DstRegs;
315     for (int i = 0; i < NumParts; ++i) {
316       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
317       ConstantInt *CI =
318           ConstantInt::get(Ctx, Cst.lshr(NarrowSize * i).trunc(NarrowSize));
319       MIRBuilder.buildConstant(DstReg, *CI);
320       DstRegs.push_back(DstReg);
321     }
322     unsigned DstReg = MI.getOperand(0).getReg();
323     MIRBuilder.buildMerge(DstReg, DstRegs);
324     MI.eraseFromParent();
325     return Legalized;
326   }
327   }
328 }
329 
330 LegalizerHelper::LegalizeResult
331 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
332   MIRBuilder.setInstr(MI);
333 
334   switch (MI.getOpcode()) {
335   default:
336     return UnableToLegalize;
337   case TargetOpcode::G_ADD:
338   case TargetOpcode::G_AND:
339   case TargetOpcode::G_MUL:
340   case TargetOpcode::G_OR:
341   case TargetOpcode::G_XOR:
342   case TargetOpcode::G_SUB:
343   case TargetOpcode::G_SHL: {
344     // Perform operation at larger width (any extension is fine here, high bits
345     // don't affect the result) and then truncate the result back to the
346     // original type.
347     unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
348     unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
349     MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(1).getReg());
350     MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(2).getReg());
351 
352     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
353     MIRBuilder.buildInstr(MI.getOpcode())
354         .addDef(DstExt)
355         .addUse(Src1Ext)
356         .addUse(Src2Ext);
357 
358     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
359     MI.eraseFromParent();
360     return Legalized;
361   }
362   case TargetOpcode::G_SDIV:
363   case TargetOpcode::G_UDIV:
364   case TargetOpcode::G_ASHR:
365   case TargetOpcode::G_LSHR: {
366     unsigned ExtOp = MI.getOpcode() == TargetOpcode::G_SDIV ||
367                              MI.getOpcode() == TargetOpcode::G_ASHR
368                          ? TargetOpcode::G_SEXT
369                          : TargetOpcode::G_ZEXT;
370 
371     unsigned LHSExt = MRI.createGenericVirtualRegister(WideTy);
372     MIRBuilder.buildInstr(ExtOp).addDef(LHSExt).addUse(
373         MI.getOperand(1).getReg());
374 
375     unsigned RHSExt = MRI.createGenericVirtualRegister(WideTy);
376     MIRBuilder.buildInstr(ExtOp).addDef(RHSExt).addUse(
377         MI.getOperand(2).getReg());
378 
379     unsigned ResExt = MRI.createGenericVirtualRegister(WideTy);
380     MIRBuilder.buildInstr(MI.getOpcode())
381         .addDef(ResExt)
382         .addUse(LHSExt)
383         .addUse(RHSExt);
384 
385     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), ResExt);
386     MI.eraseFromParent();
387     return Legalized;
388   }
389   case TargetOpcode::G_SELECT: {
390     if (TypeIdx != 0)
391       return UnableToLegalize;
392 
393     // Perform operation at larger width (any extension is fine here, high bits
394     // don't affect the result) and then truncate the result back to the
395     // original type.
396     unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
397     unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
398     MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(2).getReg());
399     MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(3).getReg());
400 
401     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
402     MIRBuilder.buildInstr(TargetOpcode::G_SELECT)
403         .addDef(DstExt)
404         .addReg(MI.getOperand(1).getReg())
405         .addUse(Src1Ext)
406         .addUse(Src2Ext);
407 
408     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
409     MI.eraseFromParent();
410     return Legalized;
411   }
412   case TargetOpcode::G_FPTOSI:
413   case TargetOpcode::G_FPTOUI: {
414     if (TypeIdx != 0)
415       return UnableToLegalize;
416 
417     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
418     MIRBuilder.buildInstr(MI.getOpcode())
419         .addDef(DstExt)
420         .addUse(MI.getOperand(1).getReg());
421 
422     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
423     MI.eraseFromParent();
424     return Legalized;
425   }
426   case TargetOpcode::G_SITOFP:
427   case TargetOpcode::G_UITOFP: {
428     if (TypeIdx != 1)
429       return UnableToLegalize;
430 
431     unsigned Src = MI.getOperand(1).getReg();
432     unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
433 
434     if (MI.getOpcode() == TargetOpcode::G_SITOFP) {
435       MIRBuilder.buildSExt(SrcExt, Src);
436     } else {
437       assert(MI.getOpcode() == TargetOpcode::G_UITOFP && "Unexpected conv op");
438       MIRBuilder.buildZExt(SrcExt, Src);
439     }
440 
441     MIRBuilder.buildInstr(MI.getOpcode())
442         .addDef(MI.getOperand(0).getReg())
443         .addUse(SrcExt);
444 
445     MI.eraseFromParent();
446     return Legalized;
447   }
448   case TargetOpcode::G_INSERT: {
449     if (TypeIdx != 0)
450       return UnableToLegalize;
451 
452     unsigned Src = MI.getOperand(1).getReg();
453     unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
454     MIRBuilder.buildAnyExt(SrcExt, Src);
455 
456     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
457     auto MIB = MIRBuilder.buildInsert(DstExt, SrcExt, MI.getOperand(2).getReg(),
458                                       MI.getOperand(3).getImm());
459     for (unsigned OpNum = 4; OpNum < MI.getNumOperands(); OpNum += 2) {
460       MIB.addReg(MI.getOperand(OpNum).getReg());
461       MIB.addImm(MI.getOperand(OpNum + 1).getImm());
462     }
463 
464     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
465     MI.eraseFromParent();
466     return Legalized;
467   }
468   case TargetOpcode::G_LOAD: {
469     assert(alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) ==
470                WideTy.getSizeInBits() &&
471            "illegal to increase number of bytes loaded");
472 
473     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
474     MIRBuilder.buildLoad(DstExt, MI.getOperand(1).getReg(),
475                          **MI.memoperands_begin());
476     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
477     MI.eraseFromParent();
478     return Legalized;
479   }
480   case TargetOpcode::G_STORE: {
481     if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(1) ||
482         WideTy != LLT::scalar(8))
483       return UnableToLegalize;
484 
485     auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
486     auto Content = TLI.getBooleanContents(false, false);
487 
488     unsigned ExtOp = TargetOpcode::G_ANYEXT;
489     if (Content == TargetLoweringBase::ZeroOrOneBooleanContent)
490       ExtOp = TargetOpcode::G_ZEXT;
491     else if (Content == TargetLoweringBase::ZeroOrNegativeOneBooleanContent)
492       ExtOp = TargetOpcode::G_SEXT;
493     else
494       ExtOp = TargetOpcode::G_ANYEXT;
495 
496     unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
497     MIRBuilder.buildInstr(ExtOp).addDef(SrcExt).addUse(
498         MI.getOperand(0).getReg());
499     MIRBuilder.buildStore(SrcExt, MI.getOperand(1).getReg(),
500                           **MI.memoperands_begin());
501     MI.eraseFromParent();
502     return Legalized;
503   }
504   case TargetOpcode::G_CONSTANT: {
505     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
506     MIRBuilder.buildConstant(DstExt, *MI.getOperand(1).getCImm());
507     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
508     MI.eraseFromParent();
509     return Legalized;
510   }
511   case TargetOpcode::G_FCONSTANT: {
512     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
513     MIRBuilder.buildFConstant(DstExt, *MI.getOperand(1).getFPImm());
514     MIRBuilder.buildFPTrunc(MI.getOperand(0).getReg(), DstExt);
515     MI.eraseFromParent();
516     return Legalized;
517   }
518   case TargetOpcode::G_BRCOND: {
519     unsigned TstExt = MRI.createGenericVirtualRegister(WideTy);
520     MIRBuilder.buildAnyExt(TstExt, MI.getOperand(0).getReg());
521     MIRBuilder.buildBrCond(TstExt, *MI.getOperand(1).getMBB());
522     MI.eraseFromParent();
523     return Legalized;
524   }
525   case TargetOpcode::G_ICMP: {
526     assert(TypeIdx == 1 && "unable to legalize predicate");
527     bool IsSigned = CmpInst::isSigned(
528         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
529     unsigned Op0Ext = MRI.createGenericVirtualRegister(WideTy);
530     unsigned Op1Ext = MRI.createGenericVirtualRegister(WideTy);
531     if (IsSigned) {
532       MIRBuilder.buildSExt(Op0Ext, MI.getOperand(2).getReg());
533       MIRBuilder.buildSExt(Op1Ext, MI.getOperand(3).getReg());
534     } else {
535       MIRBuilder.buildZExt(Op0Ext, MI.getOperand(2).getReg());
536       MIRBuilder.buildZExt(Op1Ext, MI.getOperand(3).getReg());
537     }
538     MIRBuilder.buildICmp(
539         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
540         MI.getOperand(0).getReg(), Op0Ext, Op1Ext);
541     MI.eraseFromParent();
542     return Legalized;
543   }
544   case TargetOpcode::G_GEP: {
545     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
546     unsigned OffsetExt = MRI.createGenericVirtualRegister(WideTy);
547     MIRBuilder.buildSExt(OffsetExt, MI.getOperand(2).getReg());
548     MI.getOperand(2).setReg(OffsetExt);
549     return Legalized;
550   }
551   }
552 }
553 
554 LegalizerHelper::LegalizeResult
555 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
556   using namespace TargetOpcode;
557   MIRBuilder.setInstr(MI);
558 
559   switch(MI.getOpcode()) {
560   default:
561     return UnableToLegalize;
562   case TargetOpcode::G_SREM:
563   case TargetOpcode::G_UREM: {
564     unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
565     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
566         .addDef(QuotReg)
567         .addUse(MI.getOperand(1).getReg())
568         .addUse(MI.getOperand(2).getReg());
569 
570     unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
571     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
572     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
573                         ProdReg);
574     MI.eraseFromParent();
575     return Legalized;
576   }
577   case TargetOpcode::G_SMULO:
578   case TargetOpcode::G_UMULO: {
579     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
580     // result.
581     unsigned Res = MI.getOperand(0).getReg();
582     unsigned Overflow = MI.getOperand(1).getReg();
583     unsigned LHS = MI.getOperand(2).getReg();
584     unsigned RHS = MI.getOperand(3).getReg();
585 
586     MIRBuilder.buildMul(Res, LHS, RHS);
587 
588     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
589                           ? TargetOpcode::G_SMULH
590                           : TargetOpcode::G_UMULH;
591 
592     unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
593     MIRBuilder.buildInstr(Opcode)
594       .addDef(HiPart)
595       .addUse(LHS)
596       .addUse(RHS);
597 
598     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
599     MIRBuilder.buildConstant(Zero, 0);
600     MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
601     MI.eraseFromParent();
602     return Legalized;
603   }
604   case TargetOpcode::G_FNEG: {
605     // TODO: Handle vector types once we are able to
606     // represent them.
607     if (Ty.isVector())
608       return UnableToLegalize;
609     unsigned Res = MI.getOperand(0).getReg();
610     Type *ZeroTy;
611     LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
612     switch (Ty.getSizeInBits()) {
613     case 16:
614       ZeroTy = Type::getHalfTy(Ctx);
615       break;
616     case 32:
617       ZeroTy = Type::getFloatTy(Ctx);
618       break;
619     case 64:
620       ZeroTy = Type::getDoubleTy(Ctx);
621       break;
622     default:
623       llvm_unreachable("unexpected floating-point type");
624     }
625     ConstantFP &ZeroForNegation =
626         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
627     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
628     MIRBuilder.buildFConstant(Zero, ZeroForNegation);
629     MIRBuilder.buildInstr(TargetOpcode::G_FSUB)
630         .addDef(Res)
631         .addUse(Zero)
632         .addUse(MI.getOperand(1).getReg());
633     MI.eraseFromParent();
634     return Legalized;
635   }
636   case TargetOpcode::G_FSUB: {
637     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
638     // First, check if G_FNEG is marked as Lower. If so, we may
639     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
640     if (LI.getAction({G_FNEG, Ty}).first == LegalizerInfo::Lower)
641       return UnableToLegalize;
642     unsigned Res = MI.getOperand(0).getReg();
643     unsigned LHS = MI.getOperand(1).getReg();
644     unsigned RHS = MI.getOperand(2).getReg();
645     unsigned Neg = MRI.createGenericVirtualRegister(Ty);
646     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
647     MIRBuilder.buildInstr(TargetOpcode::G_FADD)
648         .addDef(Res)
649         .addUse(LHS)
650         .addUse(Neg);
651     MI.eraseFromParent();
652     return Legalized;
653   }
654   }
655 }
656 
657 LegalizerHelper::LegalizeResult
658 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
659                                      LLT NarrowTy) {
660   // FIXME: Don't know how to handle secondary types yet.
661   if (TypeIdx != 0)
662     return UnableToLegalize;
663   switch (MI.getOpcode()) {
664   default:
665     return UnableToLegalize;
666   case TargetOpcode::G_ADD: {
667     unsigned NarrowSize = NarrowTy.getSizeInBits();
668     unsigned DstReg = MI.getOperand(0).getReg();
669     int NumParts = MRI.getType(DstReg).getSizeInBits() / NarrowSize;
670 
671     MIRBuilder.setInstr(MI);
672 
673     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
674     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
675     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
676 
677     for (int i = 0; i < NumParts; ++i) {
678       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
679       MIRBuilder.buildAdd(DstReg, Src1Regs[i], Src2Regs[i]);
680       DstRegs.push_back(DstReg);
681     }
682 
683     MIRBuilder.buildMerge(DstReg, DstRegs);
684     MI.eraseFromParent();
685     return Legalized;
686   }
687   }
688 }
689