1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetFrameLowering.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetLowering.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 
28 #define DEBUG_TYPE "legalizer"
29 
30 using namespace llvm;
31 using namespace LegalizeActions;
32 
33 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
34 ///
35 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
36 /// with any leftover piece as type \p LeftoverTy
37 ///
38 /// Returns -1 in the first element of the pair if the breakdown is not
39 /// satisfiable.
40 static std::pair<int, int>
41 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
42   assert(!LeftoverTy.isValid() && "this is an out argument");
43 
44   unsigned Size = OrigTy.getSizeInBits();
45   unsigned NarrowSize = NarrowTy.getSizeInBits();
46   unsigned NumParts = Size / NarrowSize;
47   unsigned LeftoverSize = Size - NumParts * NarrowSize;
48   assert(Size > NarrowSize);
49 
50   if (LeftoverSize == 0)
51     return {NumParts, 0};
52 
53   if (NarrowTy.isVector()) {
54     unsigned EltSize = OrigTy.getScalarSizeInBits();
55     if (LeftoverSize % EltSize != 0)
56       return {-1, -1};
57     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
58   } else {
59     LeftoverTy = LLT::scalar(LeftoverSize);
60   }
61 
62   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
63   return std::make_pair(NumParts, NumLeftover);
64 }
65 
66 static LLT getGCDType(LLT OrigTy, LLT TargetTy) {
67   if (OrigTy.isVector() && TargetTy.isVector()) {
68     assert(OrigTy.getElementType() == TargetTy.getElementType());
69     int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
70                                     TargetTy.getNumElements());
71     return LLT::scalarOrVector(GCD, OrigTy.getElementType());
72   }
73 
74   if (OrigTy.isVector() && !TargetTy.isVector()) {
75     assert(OrigTy.getElementType() == TargetTy);
76     return TargetTy;
77   }
78 
79   assert(!OrigTy.isVector() && !TargetTy.isVector() &&
80          "GCD type of vector and scalar not implemented");
81 
82   int GCD = greatestCommonDivisor(OrigTy.getSizeInBits(),
83                                   TargetTy.getSizeInBits());
84   return LLT::scalar(GCD);
85 }
86 
87 static LLT getLCMType(LLT Ty0, LLT Ty1) {
88   if (!Ty0.isVector() && !Ty1.isVector()) {
89     unsigned Mul = Ty0.getSizeInBits() * Ty1.getSizeInBits();
90     int GCDSize = greatestCommonDivisor(Ty0.getSizeInBits(),
91                                         Ty1.getSizeInBits());
92     return LLT::scalar(Mul / GCDSize);
93   }
94 
95   if (Ty0.isVector() && !Ty1.isVector()) {
96     assert(Ty0.getElementType() == Ty1 && "not yet handled");
97     return Ty0;
98   }
99 
100   if (Ty1.isVector() && !Ty0.isVector()) {
101     assert(Ty1.getElementType() == Ty0 && "not yet handled");
102     return Ty1;
103   }
104 
105   if (Ty0.isVector() && Ty1.isVector()) {
106     assert(Ty0.getElementType() == Ty1.getElementType() && "not yet handled");
107 
108     int GCDElts = greatestCommonDivisor(Ty0.getNumElements(),
109                                         Ty1.getNumElements());
110 
111     int Mul = Ty0.getNumElements() * Ty1.getNumElements();
112     return LLT::vector(Mul / GCDElts, Ty0.getElementType());
113   }
114 
115   llvm_unreachable("not yet handled");
116 }
117 
118 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) {
119 
120   if (!Ty.isScalar())
121     return nullptr;
122 
123   switch (Ty.getSizeInBits()) {
124   case 16:
125     return Type::getHalfTy(Ctx);
126   case 32:
127     return Type::getFloatTy(Ctx);
128   case 64:
129     return Type::getDoubleTy(Ctx);
130   case 128:
131     return Type::getFP128Ty(Ctx);
132   default:
133     return nullptr;
134   }
135 }
136 
137 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
138                                  GISelChangeObserver &Observer,
139                                  MachineIRBuilder &Builder)
140     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
141       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
142   MIRBuilder.setMF(MF);
143   MIRBuilder.setChangeObserver(Observer);
144 }
145 
146 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
147                                  GISelChangeObserver &Observer,
148                                  MachineIRBuilder &B)
149     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
150   MIRBuilder.setMF(MF);
151   MIRBuilder.setChangeObserver(Observer);
152 }
153 LegalizerHelper::LegalizeResult
154 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
155   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
156 
157   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
158       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
159     return LI.legalizeIntrinsic(MI, MIRBuilder, Observer) ? Legalized
160                                                           : UnableToLegalize;
161   auto Step = LI.getAction(MI, MRI);
162   switch (Step.Action) {
163   case Legal:
164     LLVM_DEBUG(dbgs() << ".. Already legal\n");
165     return AlreadyLegal;
166   case Libcall:
167     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
168     return libcall(MI);
169   case NarrowScalar:
170     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
171     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
172   case WidenScalar:
173     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
174     return widenScalar(MI, Step.TypeIdx, Step.NewType);
175   case Lower:
176     LLVM_DEBUG(dbgs() << ".. Lower\n");
177     return lower(MI, Step.TypeIdx, Step.NewType);
178   case FewerElements:
179     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
180     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
181   case MoreElements:
182     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
183     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
184   case Custom:
185     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
186     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
187                                                             : UnableToLegalize;
188   default:
189     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
190     return UnableToLegalize;
191   }
192 }
193 
194 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
195                                    SmallVectorImpl<Register> &VRegs) {
196   for (int i = 0; i < NumParts; ++i)
197     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
198   MIRBuilder.buildUnmerge(VRegs, Reg);
199 }
200 
201 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
202                                    LLT MainTy, LLT &LeftoverTy,
203                                    SmallVectorImpl<Register> &VRegs,
204                                    SmallVectorImpl<Register> &LeftoverRegs) {
205   assert(!LeftoverTy.isValid() && "this is an out argument");
206 
207   unsigned RegSize = RegTy.getSizeInBits();
208   unsigned MainSize = MainTy.getSizeInBits();
209   unsigned NumParts = RegSize / MainSize;
210   unsigned LeftoverSize = RegSize - NumParts * MainSize;
211 
212   // Use an unmerge when possible.
213   if (LeftoverSize == 0) {
214     for (unsigned I = 0; I < NumParts; ++I)
215       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
216     MIRBuilder.buildUnmerge(VRegs, Reg);
217     return true;
218   }
219 
220   if (MainTy.isVector()) {
221     unsigned EltSize = MainTy.getScalarSizeInBits();
222     if (LeftoverSize % EltSize != 0)
223       return false;
224     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
225   } else {
226     LeftoverTy = LLT::scalar(LeftoverSize);
227   }
228 
229   // For irregular sizes, extract the individual parts.
230   for (unsigned I = 0; I != NumParts; ++I) {
231     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
232     VRegs.push_back(NewReg);
233     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
234   }
235 
236   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
237        Offset += LeftoverSize) {
238     Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
239     LeftoverRegs.push_back(NewReg);
240     MIRBuilder.buildExtract(NewReg, Reg, Offset);
241   }
242 
243   return true;
244 }
245 
246 void LegalizerHelper::insertParts(Register DstReg,
247                                   LLT ResultTy, LLT PartTy,
248                                   ArrayRef<Register> PartRegs,
249                                   LLT LeftoverTy,
250                                   ArrayRef<Register> LeftoverRegs) {
251   if (!LeftoverTy.isValid()) {
252     assert(LeftoverRegs.empty());
253 
254     if (!ResultTy.isVector()) {
255       MIRBuilder.buildMerge(DstReg, PartRegs);
256       return;
257     }
258 
259     if (PartTy.isVector())
260       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
261     else
262       MIRBuilder.buildBuildVector(DstReg, PartRegs);
263     return;
264   }
265 
266   unsigned PartSize = PartTy.getSizeInBits();
267   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
268 
269   Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
270   MIRBuilder.buildUndef(CurResultReg);
271 
272   unsigned Offset = 0;
273   for (Register PartReg : PartRegs) {
274     Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
275     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
276     CurResultReg = NewResultReg;
277     Offset += PartSize;
278   }
279 
280   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
281     // Use the original output register for the final insert to avoid a copy.
282     Register NewResultReg = (I + 1 == E) ?
283       DstReg : MRI.createGenericVirtualRegister(ResultTy);
284 
285     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
286     CurResultReg = NewResultReg;
287     Offset += LeftoverPartSize;
288   }
289 }
290 
291 /// Return the result registers of G_UNMERGE_VALUES \p MI in \p Regs
292 static void getUnmergeResults(SmallVectorImpl<Register> &Regs,
293                               const MachineInstr &MI) {
294   assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES);
295 
296   const int NumResults = MI.getNumOperands() - 1;
297   Regs.resize(NumResults);
298   for (int I = 0; I != NumResults; ++I)
299     Regs[I] = MI.getOperand(I).getReg();
300 }
301 
302 LLT LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy,
303                                     LLT NarrowTy, Register SrcReg) {
304   LLT SrcTy = MRI.getType(SrcReg);
305 
306   LLT GCDTy = getGCDType(DstTy, getGCDType(SrcTy, NarrowTy));
307   if (SrcTy == GCDTy) {
308     // If the source already evenly divides the result type, we don't need to do
309     // anything.
310     Parts.push_back(SrcReg);
311   } else {
312     // Need to split into common type sized pieces.
313     auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
314     getUnmergeResults(Parts, *Unmerge);
315   }
316 
317   return GCDTy;
318 }
319 
320 LLT LegalizerHelper::buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy,
321                                          SmallVectorImpl<Register> &VRegs,
322                                          unsigned PadStrategy) {
323   LLT LCMTy = getLCMType(DstTy, NarrowTy);
324 
325   int NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits();
326   int NumSubParts = NarrowTy.getSizeInBits() / GCDTy.getSizeInBits();
327   int NumOrigSrc = VRegs.size();
328 
329   Register PadReg;
330 
331   // Get a value we can use to pad the source value if the sources won't evenly
332   // cover the result type.
333   if (NumOrigSrc < NumParts * NumSubParts) {
334     if (PadStrategy == TargetOpcode::G_ZEXT)
335       PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0);
336     else if (PadStrategy == TargetOpcode::G_ANYEXT)
337       PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
338     else {
339       assert(PadStrategy == TargetOpcode::G_SEXT);
340 
341       // Shift the sign bit of the low register through the high register.
342       auto ShiftAmt =
343         MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1);
344       PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0);
345     }
346   }
347 
348   // Registers for the final merge to be produced.
349   SmallVector<Register, 4> Remerge(NumParts);
350 
351   // Registers needed for intermediate merges, which will be merged into a
352   // source for Remerge.
353   SmallVector<Register, 4> SubMerge(NumSubParts);
354 
355   // Once we've fully read off the end of the original source bits, we can reuse
356   // the same high bits for remaining padding elements.
357   Register AllPadReg;
358 
359   // Build merges to the LCM type to cover the original result type.
360   for (int I = 0; I != NumParts; ++I) {
361     bool AllMergePartsArePadding = true;
362 
363     // Build the requested merges to the requested type.
364     for (int J = 0; J != NumSubParts; ++J) {
365       int Idx = I * NumSubParts + J;
366       if (Idx >= NumOrigSrc) {
367         SubMerge[J] = PadReg;
368         continue;
369       }
370 
371       SubMerge[J] = VRegs[Idx];
372 
373       // There are meaningful bits here we can't reuse later.
374       AllMergePartsArePadding = false;
375     }
376 
377     // If we've filled up a complete piece with padding bits, we can directly
378     // emit the natural sized constant if applicable, rather than a merge of
379     // smaller constants.
380     if (AllMergePartsArePadding && !AllPadReg) {
381       if (PadStrategy == TargetOpcode::G_ANYEXT)
382         AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0);
383       else if (PadStrategy == TargetOpcode::G_ZEXT)
384         AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0);
385 
386       // If this is a sign extension, we can't materialize a trivial constant
387       // with the right type and have to produce a merge.
388     }
389 
390     if (AllPadReg) {
391       // Avoid creating additional instructions if we're just adding additional
392       // copies of padding bits.
393       Remerge[I] = AllPadReg;
394       continue;
395     }
396 
397     if (NumSubParts == 1)
398       Remerge[I] = SubMerge[0];
399     else
400       Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0);
401 
402     // In the sign extend padding case, re-use the first all-signbit merge.
403     if (AllMergePartsArePadding && !AllPadReg)
404       AllPadReg = Remerge[I];
405   }
406 
407   VRegs = std::move(Remerge);
408   return LCMTy;
409 }
410 
411 void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy,
412                                                ArrayRef<Register> RemergeRegs) {
413   LLT DstTy = MRI.getType(DstReg);
414 
415   // Create the merge to the widened source, and extract the relevant bits into
416   // the result.
417 
418   if (DstTy == LCMTy) {
419     MIRBuilder.buildMerge(DstReg, RemergeRegs);
420     return;
421   }
422 
423   auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs);
424   if (DstTy.isScalar() && LCMTy.isScalar()) {
425     MIRBuilder.buildTrunc(DstReg, Remerge);
426     return;
427   }
428 
429   if (LCMTy.isVector()) {
430     MIRBuilder.buildExtract(DstReg, Remerge, 0);
431     return;
432   }
433 
434   llvm_unreachable("unhandled case");
435 }
436 
437 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
438   switch (Opcode) {
439   case TargetOpcode::G_SDIV:
440     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
441     switch (Size) {
442     case 32:
443       return RTLIB::SDIV_I32;
444     case 64:
445       return RTLIB::SDIV_I64;
446     case 128:
447       return RTLIB::SDIV_I128;
448     default:
449       llvm_unreachable("unexpected size");
450     }
451   case TargetOpcode::G_UDIV:
452     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
453     switch (Size) {
454     case 32:
455       return RTLIB::UDIV_I32;
456     case 64:
457       return RTLIB::UDIV_I64;
458     case 128:
459       return RTLIB::UDIV_I128;
460     default:
461       llvm_unreachable("unexpected size");
462     }
463   case TargetOpcode::G_SREM:
464     assert((Size == 32 || Size == 64) && "Unsupported size");
465     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
466   case TargetOpcode::G_UREM:
467     assert((Size == 32 || Size == 64) && "Unsupported size");
468     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
469   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
470     assert(Size == 32 && "Unsupported size");
471     return RTLIB::CTLZ_I32;
472   case TargetOpcode::G_FADD:
473     assert((Size == 32 || Size == 64) && "Unsupported size");
474     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
475   case TargetOpcode::G_FSUB:
476     assert((Size == 32 || Size == 64) && "Unsupported size");
477     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
478   case TargetOpcode::G_FMUL:
479     assert((Size == 32 || Size == 64) && "Unsupported size");
480     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
481   case TargetOpcode::G_FDIV:
482     assert((Size == 32 || Size == 64) && "Unsupported size");
483     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
484   case TargetOpcode::G_FEXP:
485     assert((Size == 32 || Size == 64) && "Unsupported size");
486     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
487   case TargetOpcode::G_FEXP2:
488     assert((Size == 32 || Size == 64) && "Unsupported size");
489     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
490   case TargetOpcode::G_FREM:
491     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
492   case TargetOpcode::G_FPOW:
493     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
494   case TargetOpcode::G_FMA:
495     assert((Size == 32 || Size == 64) && "Unsupported size");
496     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
497   case TargetOpcode::G_FSIN:
498     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
499     return Size == 128 ? RTLIB::SIN_F128
500                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
501   case TargetOpcode::G_FCOS:
502     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
503     return Size == 128 ? RTLIB::COS_F128
504                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
505   case TargetOpcode::G_FLOG10:
506     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
507     return Size == 128 ? RTLIB::LOG10_F128
508                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
509   case TargetOpcode::G_FLOG:
510     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
511     return Size == 128 ? RTLIB::LOG_F128
512                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
513   case TargetOpcode::G_FLOG2:
514     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
515     return Size == 128 ? RTLIB::LOG2_F128
516                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
517   case TargetOpcode::G_FCEIL:
518     assert((Size == 32 || Size == 64) && "Unsupported size");
519     return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
520   case TargetOpcode::G_FFLOOR:
521     assert((Size == 32 || Size == 64) && "Unsupported size");
522     return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
523   }
524   llvm_unreachable("Unknown libcall function");
525 }
526 
527 /// True if an instruction is in tail position in its caller. Intended for
528 /// legalizing libcalls as tail calls when possible.
529 static bool isLibCallInTailPosition(MachineInstr &MI) {
530   const Function &F = MI.getParent()->getParent()->getFunction();
531 
532   // Conservatively require the attributes of the call to match those of
533   // the return. Ignore NoAlias and NonNull because they don't affect the
534   // call sequence.
535   AttributeList CallerAttrs = F.getAttributes();
536   if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
537           .removeAttribute(Attribute::NoAlias)
538           .removeAttribute(Attribute::NonNull)
539           .hasAttributes())
540     return false;
541 
542   // It's not safe to eliminate the sign / zero extension of the return value.
543   if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
544       CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
545     return false;
546 
547   // Only tail call if the following instruction is a standard return.
548   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
549   MachineInstr *Next = MI.getNextNode();
550   if (!Next || TII.isTailCall(*Next) || !Next->isReturn())
551     return false;
552 
553   return true;
554 }
555 
556 LegalizerHelper::LegalizeResult
557 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
558                     const CallLowering::ArgInfo &Result,
559                     ArrayRef<CallLowering::ArgInfo> Args) {
560   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
561   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
562   const char *Name = TLI.getLibcallName(Libcall);
563 
564   CallLowering::CallLoweringInfo Info;
565   Info.CallConv = TLI.getLibcallCallingConv(Libcall);
566   Info.Callee = MachineOperand::CreateES(Name);
567   Info.OrigRet = Result;
568   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
569   if (!CLI.lowerCall(MIRBuilder, Info))
570     return LegalizerHelper::UnableToLegalize;
571 
572   return LegalizerHelper::Legalized;
573 }
574 
575 // Useful for libcalls where all operands have the same type.
576 static LegalizerHelper::LegalizeResult
577 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
578               Type *OpType) {
579   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
580 
581   SmallVector<CallLowering::ArgInfo, 3> Args;
582   for (unsigned i = 1; i < MI.getNumOperands(); i++)
583     Args.push_back({MI.getOperand(i).getReg(), OpType});
584   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
585                        Args);
586 }
587 
588 LegalizerHelper::LegalizeResult
589 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
590                        MachineInstr &MI) {
591   assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
592   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
593 
594   SmallVector<CallLowering::ArgInfo, 3> Args;
595   // Add all the args, except for the last which is an imm denoting 'tail'.
596   for (unsigned i = 1; i < MI.getNumOperands() - 1; i++) {
597     Register Reg = MI.getOperand(i).getReg();
598 
599     // Need derive an IR type for call lowering.
600     LLT OpLLT = MRI.getType(Reg);
601     Type *OpTy = nullptr;
602     if (OpLLT.isPointer())
603       OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace());
604     else
605       OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits());
606     Args.push_back({Reg, OpTy});
607   }
608 
609   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
610   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
611   Intrinsic::ID ID = MI.getOperand(0).getIntrinsicID();
612   RTLIB::Libcall RTLibcall;
613   switch (ID) {
614   case Intrinsic::memcpy:
615     RTLibcall = RTLIB::MEMCPY;
616     break;
617   case Intrinsic::memset:
618     RTLibcall = RTLIB::MEMSET;
619     break;
620   case Intrinsic::memmove:
621     RTLibcall = RTLIB::MEMMOVE;
622     break;
623   default:
624     return LegalizerHelper::UnableToLegalize;
625   }
626   const char *Name = TLI.getLibcallName(RTLibcall);
627 
628   MIRBuilder.setInstr(MI);
629 
630   CallLowering::CallLoweringInfo Info;
631   Info.CallConv = TLI.getLibcallCallingConv(RTLibcall);
632   Info.Callee = MachineOperand::CreateES(Name);
633   Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx));
634   Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() == 1 &&
635                     isLibCallInTailPosition(MI);
636 
637   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
638   if (!CLI.lowerCall(MIRBuilder, Info))
639     return LegalizerHelper::UnableToLegalize;
640 
641   if (Info.LoweredTailCall) {
642     assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?");
643     // We must have a return following the call to get past
644     // isLibCallInTailPosition.
645     assert(MI.getNextNode() && MI.getNextNode()->isReturn() &&
646            "Expected instr following MI to be a return?");
647 
648     // We lowered a tail call, so the call is now the return from the block.
649     // Delete the old return.
650     MI.getNextNode()->eraseFromParent();
651   }
652 
653   return LegalizerHelper::Legalized;
654 }
655 
656 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
657                                        Type *FromType) {
658   auto ToMVT = MVT::getVT(ToType);
659   auto FromMVT = MVT::getVT(FromType);
660 
661   switch (Opcode) {
662   case TargetOpcode::G_FPEXT:
663     return RTLIB::getFPEXT(FromMVT, ToMVT);
664   case TargetOpcode::G_FPTRUNC:
665     return RTLIB::getFPROUND(FromMVT, ToMVT);
666   case TargetOpcode::G_FPTOSI:
667     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
668   case TargetOpcode::G_FPTOUI:
669     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
670   case TargetOpcode::G_SITOFP:
671     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
672   case TargetOpcode::G_UITOFP:
673     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
674   }
675   llvm_unreachable("Unsupported libcall function");
676 }
677 
678 static LegalizerHelper::LegalizeResult
679 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
680                   Type *FromType) {
681   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
682   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
683                        {{MI.getOperand(1).getReg(), FromType}});
684 }
685 
686 LegalizerHelper::LegalizeResult
687 LegalizerHelper::libcall(MachineInstr &MI) {
688   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
689   unsigned Size = LLTy.getSizeInBits();
690   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
691 
692   MIRBuilder.setInstr(MI);
693 
694   switch (MI.getOpcode()) {
695   default:
696     return UnableToLegalize;
697   case TargetOpcode::G_SDIV:
698   case TargetOpcode::G_UDIV:
699   case TargetOpcode::G_SREM:
700   case TargetOpcode::G_UREM:
701   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
702     Type *HLTy = IntegerType::get(Ctx, Size);
703     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
704     if (Status != Legalized)
705       return Status;
706     break;
707   }
708   case TargetOpcode::G_FADD:
709   case TargetOpcode::G_FSUB:
710   case TargetOpcode::G_FMUL:
711   case TargetOpcode::G_FDIV:
712   case TargetOpcode::G_FMA:
713   case TargetOpcode::G_FPOW:
714   case TargetOpcode::G_FREM:
715   case TargetOpcode::G_FCOS:
716   case TargetOpcode::G_FSIN:
717   case TargetOpcode::G_FLOG10:
718   case TargetOpcode::G_FLOG:
719   case TargetOpcode::G_FLOG2:
720   case TargetOpcode::G_FEXP:
721   case TargetOpcode::G_FEXP2:
722   case TargetOpcode::G_FCEIL:
723   case TargetOpcode::G_FFLOOR: {
724     Type *HLTy = getFloatTypeForLLT(Ctx, LLTy);
725     if (!HLTy || (Size != 32 && Size != 64)) {
726       LLVM_DEBUG(dbgs() << "No libcall available for size " << Size << ".\n");
727       return UnableToLegalize;
728     }
729     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
730     if (Status != Legalized)
731       return Status;
732     break;
733   }
734   case TargetOpcode::G_FPEXT:
735   case TargetOpcode::G_FPTRUNC: {
736     Type *FromTy = getFloatTypeForLLT(Ctx,  MRI.getType(MI.getOperand(1).getReg()));
737     Type *ToTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(0).getReg()));
738     if (!FromTy || !ToTy)
739       return UnableToLegalize;
740     LegalizeResult Status = conversionLibcall(MI, MIRBuilder, ToTy, FromTy );
741     if (Status != Legalized)
742       return Status;
743     break;
744   }
745   case TargetOpcode::G_FPTOSI:
746   case TargetOpcode::G_FPTOUI: {
747     // FIXME: Support other types
748     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
749     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
750     if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
751       return UnableToLegalize;
752     LegalizeResult Status = conversionLibcall(
753         MI, MIRBuilder,
754         ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
755         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
756     if (Status != Legalized)
757       return Status;
758     break;
759   }
760   case TargetOpcode::G_SITOFP:
761   case TargetOpcode::G_UITOFP: {
762     // FIXME: Support other types
763     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
764     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
765     if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
766       return UnableToLegalize;
767     LegalizeResult Status = conversionLibcall(
768         MI, MIRBuilder,
769         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
770         FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
771     if (Status != Legalized)
772       return Status;
773     break;
774   }
775   }
776 
777   MI.eraseFromParent();
778   return Legalized;
779 }
780 
781 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
782                                                               unsigned TypeIdx,
783                                                               LLT NarrowTy) {
784   MIRBuilder.setInstr(MI);
785 
786   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
787   uint64_t NarrowSize = NarrowTy.getSizeInBits();
788 
789   switch (MI.getOpcode()) {
790   default:
791     return UnableToLegalize;
792   case TargetOpcode::G_IMPLICIT_DEF: {
793     // FIXME: add support for when SizeOp0 isn't an exact multiple of
794     // NarrowSize.
795     if (SizeOp0 % NarrowSize != 0)
796       return UnableToLegalize;
797     int NumParts = SizeOp0 / NarrowSize;
798 
799     SmallVector<Register, 2> DstRegs;
800     for (int i = 0; i < NumParts; ++i)
801       DstRegs.push_back(
802           MIRBuilder.buildUndef(NarrowTy).getReg(0));
803 
804     Register DstReg = MI.getOperand(0).getReg();
805     if(MRI.getType(DstReg).isVector())
806       MIRBuilder.buildBuildVector(DstReg, DstRegs);
807     else
808       MIRBuilder.buildMerge(DstReg, DstRegs);
809     MI.eraseFromParent();
810     return Legalized;
811   }
812   case TargetOpcode::G_CONSTANT: {
813     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
814     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
815     unsigned TotalSize = Ty.getSizeInBits();
816     unsigned NarrowSize = NarrowTy.getSizeInBits();
817     int NumParts = TotalSize / NarrowSize;
818 
819     SmallVector<Register, 4> PartRegs;
820     for (int I = 0; I != NumParts; ++I) {
821       unsigned Offset = I * NarrowSize;
822       auto K = MIRBuilder.buildConstant(NarrowTy,
823                                         Val.lshr(Offset).trunc(NarrowSize));
824       PartRegs.push_back(K.getReg(0));
825     }
826 
827     LLT LeftoverTy;
828     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
829     SmallVector<Register, 1> LeftoverRegs;
830     if (LeftoverBits != 0) {
831       LeftoverTy = LLT::scalar(LeftoverBits);
832       auto K = MIRBuilder.buildConstant(
833         LeftoverTy,
834         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
835       LeftoverRegs.push_back(K.getReg(0));
836     }
837 
838     insertParts(MI.getOperand(0).getReg(),
839                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
840 
841     MI.eraseFromParent();
842     return Legalized;
843   }
844   case TargetOpcode::G_SEXT:
845   case TargetOpcode::G_ZEXT:
846   case TargetOpcode::G_ANYEXT:
847     return narrowScalarExt(MI, TypeIdx, NarrowTy);
848   case TargetOpcode::G_TRUNC: {
849     if (TypeIdx != 1)
850       return UnableToLegalize;
851 
852     uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
853     if (NarrowTy.getSizeInBits() * 2 != SizeOp1) {
854       LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n");
855       return UnableToLegalize;
856     }
857 
858     auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1));
859     MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0));
860     MI.eraseFromParent();
861     return Legalized;
862   }
863 
864   case TargetOpcode::G_ADD: {
865     // FIXME: add support for when SizeOp0 isn't an exact multiple of
866     // NarrowSize.
867     if (SizeOp0 % NarrowSize != 0)
868       return UnableToLegalize;
869     // Expand in terms of carry-setting/consuming G_ADDE instructions.
870     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
871 
872     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
873     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
874     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
875 
876     Register CarryIn;
877     for (int i = 0; i < NumParts; ++i) {
878       Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
879       Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
880 
881       if (i == 0)
882         MIRBuilder.buildUAddo(DstReg, CarryOut, Src1Regs[i], Src2Regs[i]);
883       else {
884         MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
885                               Src2Regs[i], CarryIn);
886       }
887 
888       DstRegs.push_back(DstReg);
889       CarryIn = CarryOut;
890     }
891     Register DstReg = MI.getOperand(0).getReg();
892     if(MRI.getType(DstReg).isVector())
893       MIRBuilder.buildBuildVector(DstReg, DstRegs);
894     else
895       MIRBuilder.buildMerge(DstReg, DstRegs);
896     MI.eraseFromParent();
897     return Legalized;
898   }
899   case TargetOpcode::G_SUB: {
900     // FIXME: add support for when SizeOp0 isn't an exact multiple of
901     // NarrowSize.
902     if (SizeOp0 % NarrowSize != 0)
903       return UnableToLegalize;
904 
905     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
906 
907     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
908     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
909     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
910 
911     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
912     Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
913     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
914                           {Src1Regs[0], Src2Regs[0]});
915     DstRegs.push_back(DstReg);
916     Register BorrowIn = BorrowOut;
917     for (int i = 1; i < NumParts; ++i) {
918       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
919       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
920 
921       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
922                             {Src1Regs[i], Src2Regs[i], BorrowIn});
923 
924       DstRegs.push_back(DstReg);
925       BorrowIn = BorrowOut;
926     }
927     MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
928     MI.eraseFromParent();
929     return Legalized;
930   }
931   case TargetOpcode::G_MUL:
932   case TargetOpcode::G_UMULH:
933     return narrowScalarMul(MI, NarrowTy);
934   case TargetOpcode::G_EXTRACT:
935     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
936   case TargetOpcode::G_INSERT:
937     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
938   case TargetOpcode::G_LOAD: {
939     const auto &MMO = **MI.memoperands_begin();
940     Register DstReg = MI.getOperand(0).getReg();
941     LLT DstTy = MRI.getType(DstReg);
942     if (DstTy.isVector())
943       return UnableToLegalize;
944 
945     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
946       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
947       auto &MMO = **MI.memoperands_begin();
948       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1), MMO);
949       MIRBuilder.buildAnyExt(DstReg, TmpReg);
950       MI.eraseFromParent();
951       return Legalized;
952     }
953 
954     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
955   }
956   case TargetOpcode::G_ZEXTLOAD:
957   case TargetOpcode::G_SEXTLOAD: {
958     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
959     Register DstReg = MI.getOperand(0).getReg();
960     Register PtrReg = MI.getOperand(1).getReg();
961 
962     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
963     auto &MMO = **MI.memoperands_begin();
964     if (MMO.getSizeInBits() == NarrowSize) {
965       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
966     } else {
967       MIRBuilder.buildLoadInstr(MI.getOpcode(), TmpReg, PtrReg, MMO);
968     }
969 
970     if (ZExt)
971       MIRBuilder.buildZExt(DstReg, TmpReg);
972     else
973       MIRBuilder.buildSExt(DstReg, TmpReg);
974 
975     MI.eraseFromParent();
976     return Legalized;
977   }
978   case TargetOpcode::G_STORE: {
979     const auto &MMO = **MI.memoperands_begin();
980 
981     Register SrcReg = MI.getOperand(0).getReg();
982     LLT SrcTy = MRI.getType(SrcReg);
983     if (SrcTy.isVector())
984       return UnableToLegalize;
985 
986     int NumParts = SizeOp0 / NarrowSize;
987     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
988     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
989     if (SrcTy.isVector() && LeftoverBits != 0)
990       return UnableToLegalize;
991 
992     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
993       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
994       auto &MMO = **MI.memoperands_begin();
995       MIRBuilder.buildTrunc(TmpReg, SrcReg);
996       MIRBuilder.buildStore(TmpReg, MI.getOperand(1), MMO);
997       MI.eraseFromParent();
998       return Legalized;
999     }
1000 
1001     return reduceLoadStoreWidth(MI, 0, NarrowTy);
1002   }
1003   case TargetOpcode::G_SELECT:
1004     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
1005   case TargetOpcode::G_AND:
1006   case TargetOpcode::G_OR:
1007   case TargetOpcode::G_XOR: {
1008     // Legalize bitwise operation:
1009     // A = BinOp<Ty> B, C
1010     // into:
1011     // B1, ..., BN = G_UNMERGE_VALUES B
1012     // C1, ..., CN = G_UNMERGE_VALUES C
1013     // A1 = BinOp<Ty/N> B1, C2
1014     // ...
1015     // AN = BinOp<Ty/N> BN, CN
1016     // A = G_MERGE_VALUES A1, ..., AN
1017     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
1018   }
1019   case TargetOpcode::G_SHL:
1020   case TargetOpcode::G_LSHR:
1021   case TargetOpcode::G_ASHR:
1022     return narrowScalarShift(MI, TypeIdx, NarrowTy);
1023   case TargetOpcode::G_CTLZ:
1024   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1025   case TargetOpcode::G_CTTZ:
1026   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1027   case TargetOpcode::G_CTPOP:
1028     if (TypeIdx == 1)
1029       switch (MI.getOpcode()) {
1030       case TargetOpcode::G_CTLZ:
1031       case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1032         return narrowScalarCTLZ(MI, TypeIdx, NarrowTy);
1033       case TargetOpcode::G_CTTZ:
1034       case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1035         return narrowScalarCTTZ(MI, TypeIdx, NarrowTy);
1036       case TargetOpcode::G_CTPOP:
1037         return narrowScalarCTPOP(MI, TypeIdx, NarrowTy);
1038       default:
1039         return UnableToLegalize;
1040       }
1041 
1042     Observer.changingInstr(MI);
1043     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
1044     Observer.changedInstr(MI);
1045     return Legalized;
1046   case TargetOpcode::G_INTTOPTR:
1047     if (TypeIdx != 1)
1048       return UnableToLegalize;
1049 
1050     Observer.changingInstr(MI);
1051     narrowScalarSrc(MI, NarrowTy, 1);
1052     Observer.changedInstr(MI);
1053     return Legalized;
1054   case TargetOpcode::G_PTRTOINT:
1055     if (TypeIdx != 0)
1056       return UnableToLegalize;
1057 
1058     Observer.changingInstr(MI);
1059     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
1060     Observer.changedInstr(MI);
1061     return Legalized;
1062   case TargetOpcode::G_PHI: {
1063     unsigned NumParts = SizeOp0 / NarrowSize;
1064     SmallVector<Register, 2> DstRegs(NumParts);
1065     SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2);
1066     Observer.changingInstr(MI);
1067     for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
1068       MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
1069       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1070       extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
1071                    SrcRegs[i / 2]);
1072     }
1073     MachineBasicBlock &MBB = *MI.getParent();
1074     MIRBuilder.setInsertPt(MBB, MI);
1075     for (unsigned i = 0; i < NumParts; ++i) {
1076       DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
1077       MachineInstrBuilder MIB =
1078           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
1079       for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
1080         MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
1081     }
1082     MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
1083     MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
1084     Observer.changedInstr(MI);
1085     MI.eraseFromParent();
1086     return Legalized;
1087   }
1088   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
1089   case TargetOpcode::G_INSERT_VECTOR_ELT: {
1090     if (TypeIdx != 2)
1091       return UnableToLegalize;
1092 
1093     int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
1094     Observer.changingInstr(MI);
1095     narrowScalarSrc(MI, NarrowTy, OpIdx);
1096     Observer.changedInstr(MI);
1097     return Legalized;
1098   }
1099   case TargetOpcode::G_ICMP: {
1100     uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
1101     if (NarrowSize * 2 != SrcSize)
1102       return UnableToLegalize;
1103 
1104     Observer.changingInstr(MI);
1105     Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
1106     Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
1107     MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2));
1108 
1109     Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
1110     Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
1111     MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3));
1112 
1113     CmpInst::Predicate Pred =
1114         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
1115     LLT ResTy = MRI.getType(MI.getOperand(0).getReg());
1116 
1117     if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) {
1118       MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
1119       MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
1120       MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
1121       MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
1122       MIRBuilder.buildICmp(Pred, MI.getOperand(0), Or, Zero);
1123     } else {
1124       MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
1125       MachineInstrBuilder CmpHEQ =
1126           MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
1127       MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
1128           ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
1129       MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH);
1130     }
1131     Observer.changedInstr(MI);
1132     MI.eraseFromParent();
1133     return Legalized;
1134   }
1135   case TargetOpcode::G_SEXT_INREG: {
1136     if (TypeIdx != 0)
1137       return UnableToLegalize;
1138 
1139     int64_t SizeInBits = MI.getOperand(2).getImm();
1140 
1141     // So long as the new type has more bits than the bits we're extending we
1142     // don't need to break it apart.
1143     if (NarrowTy.getScalarSizeInBits() >= SizeInBits) {
1144       Observer.changingInstr(MI);
1145       // We don't lose any non-extension bits by truncating the src and
1146       // sign-extending the dst.
1147       MachineOperand &MO1 = MI.getOperand(1);
1148       auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1);
1149       MO1.setReg(TruncMIB.getReg(0));
1150 
1151       MachineOperand &MO2 = MI.getOperand(0);
1152       Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
1153       MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1154       MIRBuilder.buildSExt(MO2, DstExt);
1155       MO2.setReg(DstExt);
1156       Observer.changedInstr(MI);
1157       return Legalized;
1158     }
1159 
1160     // Break it apart. Components below the extension point are unmodified. The
1161     // component containing the extension point becomes a narrower SEXT_INREG.
1162     // Components above it are ashr'd from the component containing the
1163     // extension point.
1164     if (SizeOp0 % NarrowSize != 0)
1165       return UnableToLegalize;
1166     int NumParts = SizeOp0 / NarrowSize;
1167 
1168     // List the registers where the destination will be scattered.
1169     SmallVector<Register, 2> DstRegs;
1170     // List the registers where the source will be split.
1171     SmallVector<Register, 2> SrcRegs;
1172 
1173     // Create all the temporary registers.
1174     for (int i = 0; i < NumParts; ++i) {
1175       Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy);
1176 
1177       SrcRegs.push_back(SrcReg);
1178     }
1179 
1180     // Explode the big arguments into smaller chunks.
1181     MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1));
1182 
1183     Register AshrCstReg =
1184         MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
1185             .getReg(0);
1186     Register FullExtensionReg = 0;
1187     Register PartialExtensionReg = 0;
1188 
1189     // Do the operation on each small part.
1190     for (int i = 0; i < NumParts; ++i) {
1191       if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits)
1192         DstRegs.push_back(SrcRegs[i]);
1193       else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) {
1194         assert(PartialExtensionReg &&
1195                "Expected to visit partial extension before full");
1196         if (FullExtensionReg) {
1197           DstRegs.push_back(FullExtensionReg);
1198           continue;
1199         }
1200         DstRegs.push_back(
1201             MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg)
1202                 .getReg(0));
1203         FullExtensionReg = DstRegs.back();
1204       } else {
1205         DstRegs.push_back(
1206             MIRBuilder
1207                 .buildInstr(
1208                     TargetOpcode::G_SEXT_INREG, {NarrowTy},
1209                     {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
1210                 .getReg(0));
1211         PartialExtensionReg = DstRegs.back();
1212       }
1213     }
1214 
1215     // Gather the destination registers into the final destination.
1216     Register DstReg = MI.getOperand(0).getReg();
1217     MIRBuilder.buildMerge(DstReg, DstRegs);
1218     MI.eraseFromParent();
1219     return Legalized;
1220   }
1221   case TargetOpcode::G_BSWAP:
1222   case TargetOpcode::G_BITREVERSE: {
1223     if (SizeOp0 % NarrowSize != 0)
1224       return UnableToLegalize;
1225 
1226     Observer.changingInstr(MI);
1227     SmallVector<Register, 2> SrcRegs, DstRegs;
1228     unsigned NumParts = SizeOp0 / NarrowSize;
1229     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
1230 
1231     for (unsigned i = 0; i < NumParts; ++i) {
1232       auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
1233                                            {SrcRegs[NumParts - 1 - i]});
1234       DstRegs.push_back(DstPart.getReg(0));
1235     }
1236 
1237     MIRBuilder.buildMerge(MI.getOperand(0), DstRegs);
1238 
1239     Observer.changedInstr(MI);
1240     MI.eraseFromParent();
1241     return Legalized;
1242   }
1243   }
1244 }
1245 
1246 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
1247                                      unsigned OpIdx, unsigned ExtOpcode) {
1248   MachineOperand &MO = MI.getOperand(OpIdx);
1249   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO});
1250   MO.setReg(ExtB.getReg(0));
1251 }
1252 
1253 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
1254                                       unsigned OpIdx) {
1255   MachineOperand &MO = MI.getOperand(OpIdx);
1256   auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO);
1257   MO.setReg(ExtB.getReg(0));
1258 }
1259 
1260 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
1261                                      unsigned OpIdx, unsigned TruncOpcode) {
1262   MachineOperand &MO = MI.getOperand(OpIdx);
1263   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1264   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1265   MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt});
1266   MO.setReg(DstExt);
1267 }
1268 
1269 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
1270                                       unsigned OpIdx, unsigned ExtOpcode) {
1271   MachineOperand &MO = MI.getOperand(OpIdx);
1272   Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
1273   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1274   MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc});
1275   MO.setReg(DstTrunc);
1276 }
1277 
1278 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
1279                                             unsigned OpIdx) {
1280   MachineOperand &MO = MI.getOperand(OpIdx);
1281   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1282   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1283   MIRBuilder.buildExtract(MO, DstExt, 0);
1284   MO.setReg(DstExt);
1285 }
1286 
1287 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
1288                                             unsigned OpIdx) {
1289   MachineOperand &MO = MI.getOperand(OpIdx);
1290 
1291   LLT OldTy = MRI.getType(MO.getReg());
1292   unsigned OldElts = OldTy.getNumElements();
1293   unsigned NewElts = MoreTy.getNumElements();
1294 
1295   unsigned NumParts = NewElts / OldElts;
1296 
1297   // Use concat_vectors if the result is a multiple of the number of elements.
1298   if (NumParts * OldElts == NewElts) {
1299     SmallVector<Register, 8> Parts;
1300     Parts.push_back(MO.getReg());
1301 
1302     Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
1303     for (unsigned I = 1; I != NumParts; ++I)
1304       Parts.push_back(ImpDef);
1305 
1306     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
1307     MO.setReg(Concat.getReg(0));
1308     return;
1309   }
1310 
1311   Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
1312   Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
1313   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
1314   MO.setReg(MoreReg);
1315 }
1316 
1317 LegalizerHelper::LegalizeResult
1318 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
1319                                         LLT WideTy) {
1320   if (TypeIdx != 1)
1321     return UnableToLegalize;
1322 
1323   Register DstReg = MI.getOperand(0).getReg();
1324   LLT DstTy = MRI.getType(DstReg);
1325   if (DstTy.isVector())
1326     return UnableToLegalize;
1327 
1328   Register Src1 = MI.getOperand(1).getReg();
1329   LLT SrcTy = MRI.getType(Src1);
1330   const int DstSize = DstTy.getSizeInBits();
1331   const int SrcSize = SrcTy.getSizeInBits();
1332   const int WideSize = WideTy.getSizeInBits();
1333   const int NumMerge = (DstSize + WideSize - 1) / WideSize;
1334 
1335   unsigned NumOps = MI.getNumOperands();
1336   unsigned NumSrc = MI.getNumOperands() - 1;
1337   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
1338 
1339   if (WideSize >= DstSize) {
1340     // Directly pack the bits in the target type.
1341     Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1342 
1343     for (unsigned I = 2; I != NumOps; ++I) {
1344       const unsigned Offset = (I - 1) * PartSize;
1345 
1346       Register SrcReg = MI.getOperand(I).getReg();
1347       assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
1348 
1349       auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
1350 
1351       Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
1352         MRI.createGenericVirtualRegister(WideTy);
1353 
1354       auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
1355       auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
1356       MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1357       ResultReg = NextResult;
1358     }
1359 
1360     if (WideSize > DstSize)
1361       MIRBuilder.buildTrunc(DstReg, ResultReg);
1362     else if (DstTy.isPointer())
1363       MIRBuilder.buildIntToPtr(DstReg, ResultReg);
1364 
1365     MI.eraseFromParent();
1366     return Legalized;
1367   }
1368 
1369   // Unmerge the original values to the GCD type, and recombine to the next
1370   // multiple greater than the original type.
1371   //
1372   // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6
1373   // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0
1374   // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1
1375   // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2
1376   // %10:_(s6) = G_MERGE_VALUES %4, %5, %6
1377   // %11:_(s6) = G_MERGE_VALUES %7, %8, %9
1378   // %12:_(s12) = G_MERGE_VALUES %10, %11
1379   //
1380   // Padding with undef if necessary:
1381   //
1382   // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6
1383   // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0
1384   // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1
1385   // %7:_(s2) = G_IMPLICIT_DEF
1386   // %8:_(s6) = G_MERGE_VALUES %3, %4, %5
1387   // %9:_(s6) = G_MERGE_VALUES %6, %7, %7
1388   // %10:_(s12) = G_MERGE_VALUES %8, %9
1389 
1390   const int GCD = greatestCommonDivisor(SrcSize, WideSize);
1391   LLT GCDTy = LLT::scalar(GCD);
1392 
1393   SmallVector<Register, 8> Parts;
1394   SmallVector<Register, 8> NewMergeRegs;
1395   SmallVector<Register, 8> Unmerges;
1396   LLT WideDstTy = LLT::scalar(NumMerge * WideSize);
1397 
1398   // Decompose the original operands if they don't evenly divide.
1399   for (int I = 1, E = MI.getNumOperands(); I != E; ++I) {
1400     Register SrcReg = MI.getOperand(I).getReg();
1401     if (GCD == SrcSize) {
1402       Unmerges.push_back(SrcReg);
1403     } else {
1404       auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
1405       for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J)
1406         Unmerges.push_back(Unmerge.getReg(J));
1407     }
1408   }
1409 
1410   // Pad with undef to the next size that is a multiple of the requested size.
1411   if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) {
1412     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1413     for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I)
1414       Unmerges.push_back(UndefReg);
1415   }
1416 
1417   const int PartsPerGCD = WideSize / GCD;
1418 
1419   // Build merges of each piece.
1420   ArrayRef<Register> Slicer(Unmerges);
1421   for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) {
1422     auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
1423     NewMergeRegs.push_back(Merge.getReg(0));
1424   }
1425 
1426   // A truncate may be necessary if the requested type doesn't evenly divide the
1427   // original result type.
1428   if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
1429     MIRBuilder.buildMerge(DstReg, NewMergeRegs);
1430   } else {
1431     auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
1432     MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
1433   }
1434 
1435   MI.eraseFromParent();
1436   return Legalized;
1437 }
1438 
1439 LegalizerHelper::LegalizeResult
1440 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
1441                                           LLT WideTy) {
1442   if (TypeIdx != 0)
1443     return UnableToLegalize;
1444 
1445   int NumDst = MI.getNumOperands() - 1;
1446   Register SrcReg = MI.getOperand(NumDst).getReg();
1447   LLT SrcTy = MRI.getType(SrcReg);
1448   if (SrcTy.isVector())
1449     return UnableToLegalize;
1450 
1451   Register Dst0Reg = MI.getOperand(0).getReg();
1452   LLT DstTy = MRI.getType(Dst0Reg);
1453   if (!DstTy.isScalar())
1454     return UnableToLegalize;
1455 
1456   if (WideTy.getSizeInBits() == SrcTy.getSizeInBits()) {
1457     if (SrcTy.isPointer()) {
1458       const DataLayout &DL = MIRBuilder.getDataLayout();
1459       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) {
1460         LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n");
1461         return UnableToLegalize;
1462       }
1463 
1464       SrcTy = LLT::scalar(SrcTy.getSizeInBits());
1465       SrcReg = MIRBuilder.buildPtrToInt(SrcTy, SrcReg).getReg(0);
1466     }
1467 
1468     // Theres no unmerge type to target. Directly extract the bits from the
1469     // source type
1470     unsigned DstSize = DstTy.getSizeInBits();
1471 
1472     MIRBuilder.buildTrunc(Dst0Reg, SrcReg);
1473     for (int I = 1; I != NumDst; ++I) {
1474       auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I);
1475       auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt);
1476       MIRBuilder.buildTrunc(MI.getOperand(I), Shr);
1477     }
1478 
1479     MI.eraseFromParent();
1480     return Legalized;
1481   }
1482 
1483   // TODO
1484   if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
1485     return UnableToLegalize;
1486 
1487   // Extend the source to a wider type.
1488   LLT LCMTy = getLCMType(SrcTy, WideTy);
1489 
1490   Register WideSrc = SrcReg;
1491   if (LCMTy.getSizeInBits() != SrcTy.getSizeInBits()) {
1492     // TODO: If this is an integral address space, cast to integer and anyext.
1493     if (SrcTy.isPointer()) {
1494       LLVM_DEBUG(dbgs() << "Widening pointer source types not implemented\n");
1495       return UnableToLegalize;
1496     }
1497 
1498     WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0);
1499   }
1500 
1501   auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc);
1502 
1503   // Create a sequence of unmerges to the original results. since we may have
1504   // widened the source, we will need to pad the results with dead defs to cover
1505   // the source register.
1506   // e.g. widen s16 to s32:
1507   // %1:_(s16), %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0:_(s48)
1508   //
1509   // =>
1510   //  %4:_(s64) = G_ANYEXT %0:_(s48)
1511   //  %5:_(s32), %6:_(s32) = G_UNMERGE_VALUES %4 ; Requested unmerge
1512   //  %1:_(s16), %2:_(s16) = G_UNMERGE_VALUES %5 ; unpack to original regs
1513   //  %3:_(s16), dead %7 = G_UNMERGE_VALUES %6 ; original reg + extra dead def
1514 
1515   const int NumUnmerge = Unmerge->getNumOperands() - 1;
1516   const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits();
1517 
1518   for (int I = 0; I != NumUnmerge; ++I) {
1519     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
1520 
1521     for (int J = 0; J != PartsPerUnmerge; ++J) {
1522       int Idx = I * PartsPerUnmerge + J;
1523       if (Idx < NumDst)
1524         MIB.addDef(MI.getOperand(Idx).getReg());
1525       else {
1526         // Create dead def for excess components.
1527         MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
1528       }
1529     }
1530 
1531     MIB.addUse(Unmerge.getReg(I));
1532   }
1533 
1534   MI.eraseFromParent();
1535   return Legalized;
1536 }
1537 
1538 LegalizerHelper::LegalizeResult
1539 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
1540                                     LLT WideTy) {
1541   Register DstReg = MI.getOperand(0).getReg();
1542   Register SrcReg = MI.getOperand(1).getReg();
1543   LLT SrcTy = MRI.getType(SrcReg);
1544 
1545   LLT DstTy = MRI.getType(DstReg);
1546   unsigned Offset = MI.getOperand(2).getImm();
1547 
1548   if (TypeIdx == 0) {
1549     if (SrcTy.isVector() || DstTy.isVector())
1550       return UnableToLegalize;
1551 
1552     SrcOp Src(SrcReg);
1553     if (SrcTy.isPointer()) {
1554       // Extracts from pointers can be handled only if they are really just
1555       // simple integers.
1556       const DataLayout &DL = MIRBuilder.getDataLayout();
1557       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
1558         return UnableToLegalize;
1559 
1560       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
1561       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
1562       SrcTy = SrcAsIntTy;
1563     }
1564 
1565     if (DstTy.isPointer())
1566       return UnableToLegalize;
1567 
1568     if (Offset == 0) {
1569       // Avoid a shift in the degenerate case.
1570       MIRBuilder.buildTrunc(DstReg,
1571                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
1572       MI.eraseFromParent();
1573       return Legalized;
1574     }
1575 
1576     // Do a shift in the source type.
1577     LLT ShiftTy = SrcTy;
1578     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1579       Src = MIRBuilder.buildAnyExt(WideTy, Src);
1580       ShiftTy = WideTy;
1581     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
1582       return UnableToLegalize;
1583 
1584     auto LShr = MIRBuilder.buildLShr(
1585       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
1586     MIRBuilder.buildTrunc(DstReg, LShr);
1587     MI.eraseFromParent();
1588     return Legalized;
1589   }
1590 
1591   if (SrcTy.isScalar()) {
1592     Observer.changingInstr(MI);
1593     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1594     Observer.changedInstr(MI);
1595     return Legalized;
1596   }
1597 
1598   if (!SrcTy.isVector())
1599     return UnableToLegalize;
1600 
1601   if (DstTy != SrcTy.getElementType())
1602     return UnableToLegalize;
1603 
1604   if (Offset % SrcTy.getScalarSizeInBits() != 0)
1605     return UnableToLegalize;
1606 
1607   Observer.changingInstr(MI);
1608   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1609 
1610   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
1611                           Offset);
1612   widenScalarDst(MI, WideTy.getScalarType(), 0);
1613   Observer.changedInstr(MI);
1614   return Legalized;
1615 }
1616 
1617 LegalizerHelper::LegalizeResult
1618 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
1619                                    LLT WideTy) {
1620   if (TypeIdx != 0)
1621     return UnableToLegalize;
1622   Observer.changingInstr(MI);
1623   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1624   widenScalarDst(MI, WideTy);
1625   Observer.changedInstr(MI);
1626   return Legalized;
1627 }
1628 
1629 LegalizerHelper::LegalizeResult
1630 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
1631   MIRBuilder.setInstr(MI);
1632 
1633   switch (MI.getOpcode()) {
1634   default:
1635     return UnableToLegalize;
1636   case TargetOpcode::G_EXTRACT:
1637     return widenScalarExtract(MI, TypeIdx, WideTy);
1638   case TargetOpcode::G_INSERT:
1639     return widenScalarInsert(MI, TypeIdx, WideTy);
1640   case TargetOpcode::G_MERGE_VALUES:
1641     return widenScalarMergeValues(MI, TypeIdx, WideTy);
1642   case TargetOpcode::G_UNMERGE_VALUES:
1643     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
1644   case TargetOpcode::G_UADDO:
1645   case TargetOpcode::G_USUBO: {
1646     if (TypeIdx == 1)
1647       return UnableToLegalize; // TODO
1648     auto LHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(2));
1649     auto RHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(3));
1650     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1651                           ? TargetOpcode::G_ADD
1652                           : TargetOpcode::G_SUB;
1653     // Do the arithmetic in the larger type.
1654     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1655     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1656     APInt Mask =
1657         APInt::getLowBitsSet(WideTy.getSizeInBits(), OrigTy.getSizeInBits());
1658     auto AndOp = MIRBuilder.buildAnd(
1659         WideTy, NewOp, MIRBuilder.buildConstant(WideTy, Mask));
1660     // There is no overflow if the AndOp is the same as NewOp.
1661     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, AndOp);
1662     // Now trunc the NewOp to the original result.
1663     MIRBuilder.buildTrunc(MI.getOperand(0), NewOp);
1664     MI.eraseFromParent();
1665     return Legalized;
1666   }
1667   case TargetOpcode::G_CTTZ:
1668   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1669   case TargetOpcode::G_CTLZ:
1670   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1671   case TargetOpcode::G_CTPOP: {
1672     if (TypeIdx == 0) {
1673       Observer.changingInstr(MI);
1674       widenScalarDst(MI, WideTy, 0);
1675       Observer.changedInstr(MI);
1676       return Legalized;
1677     }
1678 
1679     Register SrcReg = MI.getOperand(1).getReg();
1680 
1681     // First ZEXT the input.
1682     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1683     LLT CurTy = MRI.getType(SrcReg);
1684     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1685       // The count is the same in the larger type except if the original
1686       // value was zero.  This can be handled by setting the bit just off
1687       // the top of the original type.
1688       auto TopBit =
1689           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1690       MIBSrc = MIRBuilder.buildOr(
1691         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1692     }
1693 
1694     // Perform the operation at the larger size.
1695     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1696     // This is already the correct result for CTPOP and CTTZs
1697     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1698         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1699       // The correct result is NewOp - (Difference in widety and current ty).
1700       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1701       MIBNewOp = MIRBuilder.buildSub(
1702           WideTy, MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff));
1703     }
1704 
1705     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1706     MI.eraseFromParent();
1707     return Legalized;
1708   }
1709   case TargetOpcode::G_BSWAP: {
1710     Observer.changingInstr(MI);
1711     Register DstReg = MI.getOperand(0).getReg();
1712 
1713     Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1714     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1715     Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1716     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1717 
1718     MI.getOperand(0).setReg(DstExt);
1719 
1720     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1721 
1722     LLT Ty = MRI.getType(DstReg);
1723     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1724     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1725     MIRBuilder.buildLShr(ShrReg, DstExt, ShiftAmtReg);
1726 
1727     MIRBuilder.buildTrunc(DstReg, ShrReg);
1728     Observer.changedInstr(MI);
1729     return Legalized;
1730   }
1731   case TargetOpcode::G_BITREVERSE: {
1732     Observer.changingInstr(MI);
1733 
1734     Register DstReg = MI.getOperand(0).getReg();
1735     LLT Ty = MRI.getType(DstReg);
1736     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1737 
1738     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1739     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1740     MI.getOperand(0).setReg(DstExt);
1741     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1742 
1743     auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
1744     auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt);
1745     MIRBuilder.buildTrunc(DstReg, Shift);
1746     Observer.changedInstr(MI);
1747     return Legalized;
1748   }
1749   case TargetOpcode::G_ADD:
1750   case TargetOpcode::G_AND:
1751   case TargetOpcode::G_MUL:
1752   case TargetOpcode::G_OR:
1753   case TargetOpcode::G_XOR:
1754   case TargetOpcode::G_SUB:
1755     // Perform operation at larger width (any extension is fines here, high bits
1756     // don't affect the result) and then truncate the result back to the
1757     // original type.
1758     Observer.changingInstr(MI);
1759     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1760     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1761     widenScalarDst(MI, WideTy);
1762     Observer.changedInstr(MI);
1763     return Legalized;
1764 
1765   case TargetOpcode::G_SHL:
1766     Observer.changingInstr(MI);
1767 
1768     if (TypeIdx == 0) {
1769       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1770       widenScalarDst(MI, WideTy);
1771     } else {
1772       assert(TypeIdx == 1);
1773       // The "number of bits to shift" operand must preserve its value as an
1774       // unsigned integer:
1775       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1776     }
1777 
1778     Observer.changedInstr(MI);
1779     return Legalized;
1780 
1781   case TargetOpcode::G_SDIV:
1782   case TargetOpcode::G_SREM:
1783   case TargetOpcode::G_SMIN:
1784   case TargetOpcode::G_SMAX:
1785     Observer.changingInstr(MI);
1786     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1787     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1788     widenScalarDst(MI, WideTy);
1789     Observer.changedInstr(MI);
1790     return Legalized;
1791 
1792   case TargetOpcode::G_ASHR:
1793   case TargetOpcode::G_LSHR:
1794     Observer.changingInstr(MI);
1795 
1796     if (TypeIdx == 0) {
1797       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1798         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1799 
1800       widenScalarSrc(MI, WideTy, 1, CvtOp);
1801       widenScalarDst(MI, WideTy);
1802     } else {
1803       assert(TypeIdx == 1);
1804       // The "number of bits to shift" operand must preserve its value as an
1805       // unsigned integer:
1806       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1807     }
1808 
1809     Observer.changedInstr(MI);
1810     return Legalized;
1811   case TargetOpcode::G_UDIV:
1812   case TargetOpcode::G_UREM:
1813   case TargetOpcode::G_UMIN:
1814   case TargetOpcode::G_UMAX:
1815     Observer.changingInstr(MI);
1816     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1817     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1818     widenScalarDst(MI, WideTy);
1819     Observer.changedInstr(MI);
1820     return Legalized;
1821 
1822   case TargetOpcode::G_SELECT:
1823     Observer.changingInstr(MI);
1824     if (TypeIdx == 0) {
1825       // Perform operation at larger width (any extension is fine here, high
1826       // bits don't affect the result) and then truncate the result back to the
1827       // original type.
1828       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1829       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1830       widenScalarDst(MI, WideTy);
1831     } else {
1832       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1833       // Explicit extension is required here since high bits affect the result.
1834       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1835     }
1836     Observer.changedInstr(MI);
1837     return Legalized;
1838 
1839   case TargetOpcode::G_FPTOSI:
1840   case TargetOpcode::G_FPTOUI:
1841     Observer.changingInstr(MI);
1842 
1843     if (TypeIdx == 0)
1844       widenScalarDst(MI, WideTy);
1845     else
1846       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT);
1847 
1848     Observer.changedInstr(MI);
1849     return Legalized;
1850   case TargetOpcode::G_SITOFP:
1851     if (TypeIdx != 1)
1852       return UnableToLegalize;
1853     Observer.changingInstr(MI);
1854     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1855     Observer.changedInstr(MI);
1856     return Legalized;
1857 
1858   case TargetOpcode::G_UITOFP:
1859     if (TypeIdx != 1)
1860       return UnableToLegalize;
1861     Observer.changingInstr(MI);
1862     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1863     Observer.changedInstr(MI);
1864     return Legalized;
1865 
1866   case TargetOpcode::G_LOAD:
1867   case TargetOpcode::G_SEXTLOAD:
1868   case TargetOpcode::G_ZEXTLOAD:
1869     Observer.changingInstr(MI);
1870     widenScalarDst(MI, WideTy);
1871     Observer.changedInstr(MI);
1872     return Legalized;
1873 
1874   case TargetOpcode::G_STORE: {
1875     if (TypeIdx != 0)
1876       return UnableToLegalize;
1877 
1878     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1879     if (!isPowerOf2_32(Ty.getSizeInBits()))
1880       return UnableToLegalize;
1881 
1882     Observer.changingInstr(MI);
1883 
1884     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1885       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1886     widenScalarSrc(MI, WideTy, 0, ExtType);
1887 
1888     Observer.changedInstr(MI);
1889     return Legalized;
1890   }
1891   case TargetOpcode::G_CONSTANT: {
1892     MachineOperand &SrcMO = MI.getOperand(1);
1893     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1894     unsigned ExtOpc = LI.getExtOpcodeForWideningConstant(
1895         MRI.getType(MI.getOperand(0).getReg()));
1896     assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT ||
1897             ExtOpc == TargetOpcode::G_ANYEXT) &&
1898            "Illegal Extend");
1899     const APInt &SrcVal = SrcMO.getCImm()->getValue();
1900     const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT)
1901                            ? SrcVal.sext(WideTy.getSizeInBits())
1902                            : SrcVal.zext(WideTy.getSizeInBits());
1903     Observer.changingInstr(MI);
1904     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1905 
1906     widenScalarDst(MI, WideTy);
1907     Observer.changedInstr(MI);
1908     return Legalized;
1909   }
1910   case TargetOpcode::G_FCONSTANT: {
1911     MachineOperand &SrcMO = MI.getOperand(1);
1912     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1913     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1914     bool LosesInfo;
1915     switch (WideTy.getSizeInBits()) {
1916     case 32:
1917       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1918                   &LosesInfo);
1919       break;
1920     case 64:
1921       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1922                   &LosesInfo);
1923       break;
1924     default:
1925       return UnableToLegalize;
1926     }
1927 
1928     assert(!LosesInfo && "extend should always be lossless");
1929 
1930     Observer.changingInstr(MI);
1931     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1932 
1933     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1934     Observer.changedInstr(MI);
1935     return Legalized;
1936   }
1937   case TargetOpcode::G_IMPLICIT_DEF: {
1938     Observer.changingInstr(MI);
1939     widenScalarDst(MI, WideTy);
1940     Observer.changedInstr(MI);
1941     return Legalized;
1942   }
1943   case TargetOpcode::G_BRCOND:
1944     Observer.changingInstr(MI);
1945     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1946     Observer.changedInstr(MI);
1947     return Legalized;
1948 
1949   case TargetOpcode::G_FCMP:
1950     Observer.changingInstr(MI);
1951     if (TypeIdx == 0)
1952       widenScalarDst(MI, WideTy);
1953     else {
1954       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1955       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1956     }
1957     Observer.changedInstr(MI);
1958     return Legalized;
1959 
1960   case TargetOpcode::G_ICMP:
1961     Observer.changingInstr(MI);
1962     if (TypeIdx == 0)
1963       widenScalarDst(MI, WideTy);
1964     else {
1965       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1966                                MI.getOperand(1).getPredicate()))
1967                                ? TargetOpcode::G_SEXT
1968                                : TargetOpcode::G_ZEXT;
1969       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1970       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1971     }
1972     Observer.changedInstr(MI);
1973     return Legalized;
1974 
1975   case TargetOpcode::G_PTR_ADD:
1976     assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD");
1977     Observer.changingInstr(MI);
1978     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1979     Observer.changedInstr(MI);
1980     return Legalized;
1981 
1982   case TargetOpcode::G_PHI: {
1983     assert(TypeIdx == 0 && "Expecting only Idx 0");
1984 
1985     Observer.changingInstr(MI);
1986     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1987       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1988       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1989       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1990     }
1991 
1992     MachineBasicBlock &MBB = *MI.getParent();
1993     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1994     widenScalarDst(MI, WideTy);
1995     Observer.changedInstr(MI);
1996     return Legalized;
1997   }
1998   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1999     if (TypeIdx == 0) {
2000       Register VecReg = MI.getOperand(1).getReg();
2001       LLT VecTy = MRI.getType(VecReg);
2002       Observer.changingInstr(MI);
2003 
2004       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
2005                                      WideTy.getSizeInBits()),
2006                      1, TargetOpcode::G_SEXT);
2007 
2008       widenScalarDst(MI, WideTy, 0);
2009       Observer.changedInstr(MI);
2010       return Legalized;
2011     }
2012 
2013     if (TypeIdx != 2)
2014       return UnableToLegalize;
2015     Observer.changingInstr(MI);
2016     // TODO: Probably should be zext
2017     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
2018     Observer.changedInstr(MI);
2019     return Legalized;
2020   }
2021   case TargetOpcode::G_INSERT_VECTOR_ELT: {
2022     if (TypeIdx == 1) {
2023       Observer.changingInstr(MI);
2024 
2025       Register VecReg = MI.getOperand(1).getReg();
2026       LLT VecTy = MRI.getType(VecReg);
2027       LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy);
2028 
2029       widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT);
2030       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
2031       widenScalarDst(MI, WideVecTy, 0);
2032       Observer.changedInstr(MI);
2033       return Legalized;
2034     }
2035 
2036     if (TypeIdx == 2) {
2037       Observer.changingInstr(MI);
2038       // TODO: Probably should be zext
2039       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT);
2040       Observer.changedInstr(MI);
2041     }
2042 
2043     return Legalized;
2044   }
2045   case TargetOpcode::G_FADD:
2046   case TargetOpcode::G_FMUL:
2047   case TargetOpcode::G_FSUB:
2048   case TargetOpcode::G_FMA:
2049   case TargetOpcode::G_FMAD:
2050   case TargetOpcode::G_FNEG:
2051   case TargetOpcode::G_FABS:
2052   case TargetOpcode::G_FCANONICALIZE:
2053   case TargetOpcode::G_FMINNUM:
2054   case TargetOpcode::G_FMAXNUM:
2055   case TargetOpcode::G_FMINNUM_IEEE:
2056   case TargetOpcode::G_FMAXNUM_IEEE:
2057   case TargetOpcode::G_FMINIMUM:
2058   case TargetOpcode::G_FMAXIMUM:
2059   case TargetOpcode::G_FDIV:
2060   case TargetOpcode::G_FREM:
2061   case TargetOpcode::G_FCEIL:
2062   case TargetOpcode::G_FFLOOR:
2063   case TargetOpcode::G_FCOS:
2064   case TargetOpcode::G_FSIN:
2065   case TargetOpcode::G_FLOG10:
2066   case TargetOpcode::G_FLOG:
2067   case TargetOpcode::G_FLOG2:
2068   case TargetOpcode::G_FRINT:
2069   case TargetOpcode::G_FNEARBYINT:
2070   case TargetOpcode::G_FSQRT:
2071   case TargetOpcode::G_FEXP:
2072   case TargetOpcode::G_FEXP2:
2073   case TargetOpcode::G_FPOW:
2074   case TargetOpcode::G_INTRINSIC_TRUNC:
2075   case TargetOpcode::G_INTRINSIC_ROUND:
2076     assert(TypeIdx == 0);
2077     Observer.changingInstr(MI);
2078 
2079     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
2080       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
2081 
2082     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
2083     Observer.changedInstr(MI);
2084     return Legalized;
2085   case TargetOpcode::G_INTTOPTR:
2086     if (TypeIdx != 1)
2087       return UnableToLegalize;
2088 
2089     Observer.changingInstr(MI);
2090     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
2091     Observer.changedInstr(MI);
2092     return Legalized;
2093   case TargetOpcode::G_PTRTOINT:
2094     if (TypeIdx != 0)
2095       return UnableToLegalize;
2096 
2097     Observer.changingInstr(MI);
2098     widenScalarDst(MI, WideTy, 0);
2099     Observer.changedInstr(MI);
2100     return Legalized;
2101   case TargetOpcode::G_BUILD_VECTOR: {
2102     Observer.changingInstr(MI);
2103 
2104     const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
2105     for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
2106       widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT);
2107 
2108     // Avoid changing the result vector type if the source element type was
2109     // requested.
2110     if (TypeIdx == 1) {
2111       auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
2112       MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
2113     } else {
2114       widenScalarDst(MI, WideTy, 0);
2115     }
2116 
2117     Observer.changedInstr(MI);
2118     return Legalized;
2119   }
2120   case TargetOpcode::G_SEXT_INREG:
2121     if (TypeIdx != 0)
2122       return UnableToLegalize;
2123 
2124     Observer.changingInstr(MI);
2125     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
2126     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC);
2127     Observer.changedInstr(MI);
2128     return Legalized;
2129   }
2130 }
2131 
2132 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces,
2133                              MachineIRBuilder &B, Register Src, LLT Ty) {
2134   auto Unmerge = B.buildUnmerge(Ty, Src);
2135   for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
2136     Pieces.push_back(Unmerge.getReg(I));
2137 }
2138 
2139 LegalizerHelper::LegalizeResult
2140 LegalizerHelper::lowerBitcast(MachineInstr &MI) {
2141   Register Dst = MI.getOperand(0).getReg();
2142   Register Src = MI.getOperand(1).getReg();
2143   LLT DstTy = MRI.getType(Dst);
2144   LLT SrcTy = MRI.getType(Src);
2145 
2146   if (SrcTy.isVector() && !DstTy.isVector()) {
2147     SmallVector<Register, 8> SrcRegs;
2148     getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcTy.getElementType());
2149     MIRBuilder.buildMerge(Dst, SrcRegs);
2150     MI.eraseFromParent();
2151     return Legalized;
2152   }
2153 
2154   if (DstTy.isVector() && !SrcTy.isVector()) {
2155     SmallVector<Register, 8> SrcRegs;
2156     getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType());
2157     MIRBuilder.buildMerge(Dst, SrcRegs);
2158     MI.eraseFromParent();
2159     return Legalized;
2160   }
2161 
2162   return UnableToLegalize;
2163 }
2164 
2165 LegalizerHelper::LegalizeResult
2166 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
2167   using namespace TargetOpcode;
2168   MIRBuilder.setInstr(MI);
2169 
2170   switch(MI.getOpcode()) {
2171   default:
2172     return UnableToLegalize;
2173   case TargetOpcode::G_BITCAST:
2174     return lowerBitcast(MI);
2175   case TargetOpcode::G_SREM:
2176   case TargetOpcode::G_UREM: {
2177     Register QuotReg = MRI.createGenericVirtualRegister(Ty);
2178     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {QuotReg},
2179                           {MI.getOperand(1), MI.getOperand(2)});
2180 
2181     Register ProdReg = MRI.createGenericVirtualRegister(Ty);
2182     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2));
2183     MIRBuilder.buildSub(MI.getOperand(0), MI.getOperand(1), ProdReg);
2184     MI.eraseFromParent();
2185     return Legalized;
2186   }
2187   case TargetOpcode::G_SADDO:
2188   case TargetOpcode::G_SSUBO:
2189     return lowerSADDO_SSUBO(MI);
2190   case TargetOpcode::G_SMULO:
2191   case TargetOpcode::G_UMULO: {
2192     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
2193     // result.
2194     Register Res = MI.getOperand(0).getReg();
2195     Register Overflow = MI.getOperand(1).getReg();
2196     Register LHS = MI.getOperand(2).getReg();
2197     Register RHS = MI.getOperand(3).getReg();
2198 
2199     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
2200                           ? TargetOpcode::G_SMULH
2201                           : TargetOpcode::G_UMULH;
2202 
2203     Observer.changingInstr(MI);
2204     const auto &TII = MIRBuilder.getTII();
2205     MI.setDesc(TII.get(TargetOpcode::G_MUL));
2206     MI.RemoveOperand(1);
2207     Observer.changedInstr(MI);
2208 
2209     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
2210 
2211     auto HiPart = MIRBuilder.buildInstr(Opcode, {Ty}, {LHS, RHS});
2212 
2213     Register Zero = MRI.createGenericVirtualRegister(Ty);
2214     MIRBuilder.buildConstant(Zero, 0);
2215 
2216     // For *signed* multiply, overflow is detected by checking:
2217     // (hi != (lo >> bitwidth-1))
2218     if (Opcode == TargetOpcode::G_SMULH) {
2219       auto ShiftAmt = MIRBuilder.buildConstant(Ty, Ty.getSizeInBits() - 1);
2220       auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt);
2221       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
2222     } else {
2223       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
2224     }
2225     return Legalized;
2226   }
2227   case TargetOpcode::G_FNEG: {
2228     // TODO: Handle vector types once we are able to
2229     // represent them.
2230     if (Ty.isVector())
2231       return UnableToLegalize;
2232     Register Res = MI.getOperand(0).getReg();
2233     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
2234     Type *ZeroTy = getFloatTypeForLLT(Ctx, Ty);
2235     if (!ZeroTy)
2236       return UnableToLegalize;
2237     ConstantFP &ZeroForNegation =
2238         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
2239     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
2240     Register SubByReg = MI.getOperand(1).getReg();
2241     Register ZeroReg = Zero.getReg(0);
2242     MIRBuilder.buildFSub(Res, ZeroReg, SubByReg, MI.getFlags());
2243     MI.eraseFromParent();
2244     return Legalized;
2245   }
2246   case TargetOpcode::G_FSUB: {
2247     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
2248     // First, check if G_FNEG is marked as Lower. If so, we may
2249     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
2250     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
2251       return UnableToLegalize;
2252     Register Res = MI.getOperand(0).getReg();
2253     Register LHS = MI.getOperand(1).getReg();
2254     Register RHS = MI.getOperand(2).getReg();
2255     Register Neg = MRI.createGenericVirtualRegister(Ty);
2256     MIRBuilder.buildFNeg(Neg, RHS);
2257     MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags());
2258     MI.eraseFromParent();
2259     return Legalized;
2260   }
2261   case TargetOpcode::G_FMAD:
2262     return lowerFMad(MI);
2263   case TargetOpcode::G_INTRINSIC_ROUND:
2264     return lowerIntrinsicRound(MI);
2265   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
2266     Register OldValRes = MI.getOperand(0).getReg();
2267     Register SuccessRes = MI.getOperand(1).getReg();
2268     Register Addr = MI.getOperand(2).getReg();
2269     Register CmpVal = MI.getOperand(3).getReg();
2270     Register NewVal = MI.getOperand(4).getReg();
2271     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
2272                                   **MI.memoperands_begin());
2273     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
2274     MI.eraseFromParent();
2275     return Legalized;
2276   }
2277   case TargetOpcode::G_LOAD:
2278   case TargetOpcode::G_SEXTLOAD:
2279   case TargetOpcode::G_ZEXTLOAD: {
2280     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
2281     Register DstReg = MI.getOperand(0).getReg();
2282     Register PtrReg = MI.getOperand(1).getReg();
2283     LLT DstTy = MRI.getType(DstReg);
2284     auto &MMO = **MI.memoperands_begin();
2285 
2286     if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
2287       if (MI.getOpcode() == TargetOpcode::G_LOAD) {
2288         // This load needs splitting into power of 2 sized loads.
2289         if (DstTy.isVector())
2290           return UnableToLegalize;
2291         if (isPowerOf2_32(DstTy.getSizeInBits()))
2292           return UnableToLegalize; // Don't know what we're being asked to do.
2293 
2294         // Our strategy here is to generate anyextending loads for the smaller
2295         // types up to next power-2 result type, and then combine the two larger
2296         // result values together, before truncating back down to the non-pow-2
2297         // type.
2298         // E.g. v1 = i24 load =>
2299         // v2 = i32 zextload (2 byte)
2300         // v3 = i32 load (1 byte)
2301         // v4 = i32 shl v3, 16
2302         // v5 = i32 or v4, v2
2303         // v1 = i24 trunc v5
2304         // By doing this we generate the correct truncate which should get
2305         // combined away as an artifact with a matching extend.
2306         uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits());
2307         uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize;
2308 
2309         MachineFunction &MF = MIRBuilder.getMF();
2310         MachineMemOperand *LargeMMO =
2311             MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2312         MachineMemOperand *SmallMMO = MF.getMachineMemOperand(
2313             &MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2314 
2315         LLT PtrTy = MRI.getType(PtrReg);
2316         unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits());
2317         LLT AnyExtTy = LLT::scalar(AnyExtSize);
2318         Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2319         Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2320         auto LargeLoad = MIRBuilder.buildLoadInstr(
2321             TargetOpcode::G_ZEXTLOAD, LargeLdReg, PtrReg, *LargeMMO);
2322 
2323         auto OffsetCst = MIRBuilder.buildConstant(
2324             LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8);
2325         Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2326         auto SmallPtr =
2327             MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2328         auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
2329                                               *SmallMMO);
2330 
2331         auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
2332         auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt);
2333         auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
2334         MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)});
2335         MI.eraseFromParent();
2336         return Legalized;
2337       }
2338       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
2339       MI.eraseFromParent();
2340       return Legalized;
2341     }
2342 
2343     if (DstTy.isScalar()) {
2344       Register TmpReg =
2345           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
2346       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
2347       switch (MI.getOpcode()) {
2348       default:
2349         llvm_unreachable("Unexpected opcode");
2350       case TargetOpcode::G_LOAD:
2351         MIRBuilder.buildExtOrTrunc(TargetOpcode::G_ANYEXT, DstReg, TmpReg);
2352         break;
2353       case TargetOpcode::G_SEXTLOAD:
2354         MIRBuilder.buildSExt(DstReg, TmpReg);
2355         break;
2356       case TargetOpcode::G_ZEXTLOAD:
2357         MIRBuilder.buildZExt(DstReg, TmpReg);
2358         break;
2359       }
2360       MI.eraseFromParent();
2361       return Legalized;
2362     }
2363 
2364     return UnableToLegalize;
2365   }
2366   case TargetOpcode::G_STORE: {
2367     // Lower a non-power of 2 store into multiple pow-2 stores.
2368     // E.g. split an i24 store into an i16 store + i8 store.
2369     // We do this by first extending the stored value to the next largest power
2370     // of 2 type, and then using truncating stores to store the components.
2371     // By doing this, likewise with G_LOAD, generate an extend that can be
2372     // artifact-combined away instead of leaving behind extracts.
2373     Register SrcReg = MI.getOperand(0).getReg();
2374     Register PtrReg = MI.getOperand(1).getReg();
2375     LLT SrcTy = MRI.getType(SrcReg);
2376     MachineMemOperand &MMO = **MI.memoperands_begin();
2377     if (SrcTy.getSizeInBits() != MMO.getSizeInBits())
2378       return UnableToLegalize;
2379     if (SrcTy.isVector())
2380       return UnableToLegalize;
2381     if (isPowerOf2_32(SrcTy.getSizeInBits()))
2382       return UnableToLegalize; // Don't know what we're being asked to do.
2383 
2384     // Extend to the next pow-2.
2385     const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits()));
2386     auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg);
2387 
2388     // Obtain the smaller value by shifting away the larger value.
2389     uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits());
2390     uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize;
2391     auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize);
2392     auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt);
2393 
2394     // Generate the PtrAdd and truncating stores.
2395     LLT PtrTy = MRI.getType(PtrReg);
2396     auto OffsetCst = MIRBuilder.buildConstant(
2397             LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8);
2398     Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2399     auto SmallPtr =
2400         MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2401 
2402     MachineFunction &MF = MIRBuilder.getMF();
2403     MachineMemOperand *LargeMMO =
2404         MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2405     MachineMemOperand *SmallMMO =
2406         MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2407     MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO);
2408     MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO);
2409     MI.eraseFromParent();
2410     return Legalized;
2411   }
2412   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
2413   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
2414   case TargetOpcode::G_CTLZ:
2415   case TargetOpcode::G_CTTZ:
2416   case TargetOpcode::G_CTPOP:
2417     return lowerBitCount(MI, TypeIdx, Ty);
2418   case G_UADDO: {
2419     Register Res = MI.getOperand(0).getReg();
2420     Register CarryOut = MI.getOperand(1).getReg();
2421     Register LHS = MI.getOperand(2).getReg();
2422     Register RHS = MI.getOperand(3).getReg();
2423 
2424     MIRBuilder.buildAdd(Res, LHS, RHS);
2425     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
2426 
2427     MI.eraseFromParent();
2428     return Legalized;
2429   }
2430   case G_UADDE: {
2431     Register Res = MI.getOperand(0).getReg();
2432     Register CarryOut = MI.getOperand(1).getReg();
2433     Register LHS = MI.getOperand(2).getReg();
2434     Register RHS = MI.getOperand(3).getReg();
2435     Register CarryIn = MI.getOperand(4).getReg();
2436 
2437     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2438     Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
2439 
2440     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
2441     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
2442     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
2443     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
2444 
2445     MI.eraseFromParent();
2446     return Legalized;
2447   }
2448   case G_USUBO: {
2449     Register Res = MI.getOperand(0).getReg();
2450     Register BorrowOut = MI.getOperand(1).getReg();
2451     Register LHS = MI.getOperand(2).getReg();
2452     Register RHS = MI.getOperand(3).getReg();
2453 
2454     MIRBuilder.buildSub(Res, LHS, RHS);
2455     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
2456 
2457     MI.eraseFromParent();
2458     return Legalized;
2459   }
2460   case G_USUBE: {
2461     Register Res = MI.getOperand(0).getReg();
2462     Register BorrowOut = MI.getOperand(1).getReg();
2463     Register LHS = MI.getOperand(2).getReg();
2464     Register RHS = MI.getOperand(3).getReg();
2465     Register BorrowIn = MI.getOperand(4).getReg();
2466 
2467     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2468     Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
2469     Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2470     Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2471 
2472     MIRBuilder.buildSub(TmpRes, LHS, RHS);
2473     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
2474     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
2475     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
2476     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
2477     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
2478 
2479     MI.eraseFromParent();
2480     return Legalized;
2481   }
2482   case G_UITOFP:
2483     return lowerUITOFP(MI, TypeIdx, Ty);
2484   case G_SITOFP:
2485     return lowerSITOFP(MI, TypeIdx, Ty);
2486   case G_FPTOUI:
2487     return lowerFPTOUI(MI, TypeIdx, Ty);
2488   case G_FPTOSI:
2489     return lowerFPTOSI(MI);
2490   case G_FPTRUNC:
2491     return lowerFPTRUNC(MI, TypeIdx, Ty);
2492   case G_SMIN:
2493   case G_SMAX:
2494   case G_UMIN:
2495   case G_UMAX:
2496     return lowerMinMax(MI, TypeIdx, Ty);
2497   case G_FCOPYSIGN:
2498     return lowerFCopySign(MI, TypeIdx, Ty);
2499   case G_FMINNUM:
2500   case G_FMAXNUM:
2501     return lowerFMinNumMaxNum(MI);
2502   case G_UNMERGE_VALUES:
2503     return lowerUnmergeValues(MI);
2504   case TargetOpcode::G_SEXT_INREG: {
2505     assert(MI.getOperand(2).isImm() && "Expected immediate");
2506     int64_t SizeInBits = MI.getOperand(2).getImm();
2507 
2508     Register DstReg = MI.getOperand(0).getReg();
2509     Register SrcReg = MI.getOperand(1).getReg();
2510     LLT DstTy = MRI.getType(DstReg);
2511     Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
2512 
2513     auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
2514     MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0));
2515     MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0));
2516     MI.eraseFromParent();
2517     return Legalized;
2518   }
2519   case G_SHUFFLE_VECTOR:
2520     return lowerShuffleVector(MI);
2521   case G_DYN_STACKALLOC:
2522     return lowerDynStackAlloc(MI);
2523   case G_EXTRACT:
2524     return lowerExtract(MI);
2525   case G_INSERT:
2526     return lowerInsert(MI);
2527   case G_BSWAP:
2528     return lowerBswap(MI);
2529   case G_BITREVERSE:
2530     return lowerBitreverse(MI);
2531   case G_READ_REGISTER:
2532   case G_WRITE_REGISTER:
2533     return lowerReadWriteRegister(MI);
2534   }
2535 }
2536 
2537 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
2538     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
2539   SmallVector<Register, 2> DstRegs;
2540 
2541   unsigned NarrowSize = NarrowTy.getSizeInBits();
2542   Register DstReg = MI.getOperand(0).getReg();
2543   unsigned Size = MRI.getType(DstReg).getSizeInBits();
2544   int NumParts = Size / NarrowSize;
2545   // FIXME: Don't know how to handle the situation where the small vectors
2546   // aren't all the same size yet.
2547   if (Size % NarrowSize != 0)
2548     return UnableToLegalize;
2549 
2550   for (int i = 0; i < NumParts; ++i) {
2551     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
2552     MIRBuilder.buildUndef(TmpReg);
2553     DstRegs.push_back(TmpReg);
2554   }
2555 
2556   if (NarrowTy.isVector())
2557     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2558   else
2559     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2560 
2561   MI.eraseFromParent();
2562   return Legalized;
2563 }
2564 
2565 LegalizerHelper::LegalizeResult
2566 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
2567                                           LLT NarrowTy) {
2568   assert(TypeIdx == 0 && "only one type index expected");
2569 
2570   const unsigned Opc = MI.getOpcode();
2571   const int NumOps = MI.getNumOperands() - 1;
2572   const Register DstReg = MI.getOperand(0).getReg();
2573   const unsigned Flags = MI.getFlags();
2574 
2575   assert(NumOps <= 3 && "expected instrution with 1 result and 1-3 sources");
2576 
2577   SmallVector<Register, 8> ExtractedRegs[3];
2578   SmallVector<Register, 8> Parts;
2579 
2580   // Break down all the sources into NarrowTy pieces we can operate on. This may
2581   // involve creating merges to a wider type, padded with undef.
2582   for (int I = 0; I != NumOps; ++I) {
2583     Register SrcReg =  MI.getOperand(I + 1).getReg();
2584     LLT SrcTy = MRI.getType(SrcReg);
2585     LLT GCDTy = extractGCDType(ExtractedRegs[I], SrcTy, NarrowTy, SrcReg);
2586 
2587     // Build a sequence of NarrowTy pieces in ExtractedRegs for this operand.
2588     buildLCMMergePieces(SrcTy, NarrowTy, GCDTy, ExtractedRegs[I],
2589                         TargetOpcode::G_ANYEXT);
2590   }
2591 
2592   SmallVector<Register, 8> ResultRegs;
2593 
2594   // Input operands for each sub-instruction.
2595   SmallVector<SrcOp, 4> InputRegs(NumOps, Register());
2596 
2597   int NumParts = ExtractedRegs[0].size();
2598   const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
2599   const unsigned NarrowSize = NarrowTy.getSizeInBits();
2600 
2601   // We widened the source registers to satisfy merge/unmerge size
2602   // constraints. We'll have some extra fully undef parts.
2603   const int NumRealParts = (DstSize + NarrowSize - 1) / NarrowSize;
2604 
2605   for (int I = 0; I != NumRealParts; ++I) {
2606     // Emit this instruction on each of the split pieces.
2607     for (int J = 0; J != NumOps; ++J)
2608       InputRegs[J] = ExtractedRegs[J][I];
2609 
2610     auto Inst = MIRBuilder.buildInstr(Opc, {NarrowTy}, InputRegs, Flags);
2611     ResultRegs.push_back(Inst.getReg(0));
2612   }
2613 
2614   // Fill out the widened result with undef instead of creating instructions
2615   // with undef inputs.
2616   int NumUndefParts = NumParts - NumRealParts;
2617   if (NumUndefParts != 0)
2618     ResultRegs.append(NumUndefParts, MIRBuilder.buildUndef(NarrowTy).getReg(0));
2619 
2620   // Extract the possibly padded result to the original result register.
2621   LLT DstTy = MRI.getType(DstReg);
2622   LLT LCMTy = getLCMType(DstTy, NarrowTy);
2623   buildWidenedRemergeToDst(DstReg, LCMTy, ResultRegs);
2624 
2625   MI.eraseFromParent();
2626   return Legalized;
2627 }
2628 
2629 // Handle splitting vector operations which need to have the same number of
2630 // elements in each type index, but each type index may have a different element
2631 // type.
2632 //
2633 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
2634 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2635 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2636 //
2637 // Also handles some irregular breakdown cases, e.g.
2638 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
2639 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2640 //             s64 = G_SHL s64, s32
2641 LegalizerHelper::LegalizeResult
2642 LegalizerHelper::fewerElementsVectorMultiEltType(
2643   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
2644   if (TypeIdx != 0)
2645     return UnableToLegalize;
2646 
2647   const LLT NarrowTy0 = NarrowTyArg;
2648   const unsigned NewNumElts =
2649       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
2650 
2651   const Register DstReg = MI.getOperand(0).getReg();
2652   LLT DstTy = MRI.getType(DstReg);
2653   LLT LeftoverTy0;
2654 
2655   // All of the operands need to have the same number of elements, so if we can
2656   // determine a type breakdown for the result type, we can for all of the
2657   // source types.
2658   int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first;
2659   if (NumParts < 0)
2660     return UnableToLegalize;
2661 
2662   SmallVector<MachineInstrBuilder, 4> NewInsts;
2663 
2664   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2665   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2666 
2667   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2668     LLT LeftoverTy;
2669     Register SrcReg = MI.getOperand(I).getReg();
2670     LLT SrcTyI = MRI.getType(SrcReg);
2671     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
2672     LLT LeftoverTyI;
2673 
2674     // Split this operand into the requested typed registers, and any leftover
2675     // required to reproduce the original type.
2676     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
2677                       LeftoverRegs))
2678       return UnableToLegalize;
2679 
2680     if (I == 1) {
2681       // For the first operand, create an instruction for each part and setup
2682       // the result.
2683       for (Register PartReg : PartRegs) {
2684         Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2685         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2686                                .addDef(PartDstReg)
2687                                .addUse(PartReg));
2688         DstRegs.push_back(PartDstReg);
2689       }
2690 
2691       for (Register LeftoverReg : LeftoverRegs) {
2692         Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
2693         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2694                                .addDef(PartDstReg)
2695                                .addUse(LeftoverReg));
2696         LeftoverDstRegs.push_back(PartDstReg);
2697       }
2698     } else {
2699       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
2700 
2701       // Add the newly created operand splits to the existing instructions. The
2702       // odd-sized pieces are ordered after the requested NarrowTyArg sized
2703       // pieces.
2704       unsigned InstCount = 0;
2705       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
2706         NewInsts[InstCount++].addUse(PartRegs[J]);
2707       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
2708         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
2709     }
2710 
2711     PartRegs.clear();
2712     LeftoverRegs.clear();
2713   }
2714 
2715   // Insert the newly built operations and rebuild the result register.
2716   for (auto &MIB : NewInsts)
2717     MIRBuilder.insertInstr(MIB);
2718 
2719   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
2720 
2721   MI.eraseFromParent();
2722   return Legalized;
2723 }
2724 
2725 LegalizerHelper::LegalizeResult
2726 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
2727                                           LLT NarrowTy) {
2728   if (TypeIdx != 0)
2729     return UnableToLegalize;
2730 
2731   Register DstReg = MI.getOperand(0).getReg();
2732   Register SrcReg = MI.getOperand(1).getReg();
2733   LLT DstTy = MRI.getType(DstReg);
2734   LLT SrcTy = MRI.getType(SrcReg);
2735 
2736   LLT NarrowTy0 = NarrowTy;
2737   LLT NarrowTy1;
2738   unsigned NumParts;
2739 
2740   if (NarrowTy.isVector()) {
2741     // Uneven breakdown not handled.
2742     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
2743     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
2744       return UnableToLegalize;
2745 
2746     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
2747   } else {
2748     NumParts = DstTy.getNumElements();
2749     NarrowTy1 = SrcTy.getElementType();
2750   }
2751 
2752   SmallVector<Register, 4> SrcRegs, DstRegs;
2753   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
2754 
2755   for (unsigned I = 0; I < NumParts; ++I) {
2756     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2757     MachineInstr *NewInst =
2758         MIRBuilder.buildInstr(MI.getOpcode(), {DstReg}, {SrcRegs[I]});
2759 
2760     NewInst->setFlags(MI.getFlags());
2761     DstRegs.push_back(DstReg);
2762   }
2763 
2764   if (NarrowTy.isVector())
2765     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2766   else
2767     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2768 
2769   MI.eraseFromParent();
2770   return Legalized;
2771 }
2772 
2773 LegalizerHelper::LegalizeResult
2774 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
2775                                         LLT NarrowTy) {
2776   Register DstReg = MI.getOperand(0).getReg();
2777   Register Src0Reg = MI.getOperand(2).getReg();
2778   LLT DstTy = MRI.getType(DstReg);
2779   LLT SrcTy = MRI.getType(Src0Reg);
2780 
2781   unsigned NumParts;
2782   LLT NarrowTy0, NarrowTy1;
2783 
2784   if (TypeIdx == 0) {
2785     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2786     unsigned OldElts = DstTy.getNumElements();
2787 
2788     NarrowTy0 = NarrowTy;
2789     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
2790     NarrowTy1 = NarrowTy.isVector() ?
2791       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
2792       SrcTy.getElementType();
2793 
2794   } else {
2795     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2796     unsigned OldElts = SrcTy.getNumElements();
2797 
2798     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
2799       NarrowTy.getNumElements();
2800     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
2801                             DstTy.getScalarSizeInBits());
2802     NarrowTy1 = NarrowTy;
2803   }
2804 
2805   // FIXME: Don't know how to handle the situation where the small vectors
2806   // aren't all the same size yet.
2807   if (NarrowTy1.isVector() &&
2808       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
2809     return UnableToLegalize;
2810 
2811   CmpInst::Predicate Pred
2812     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
2813 
2814   SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
2815   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
2816   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
2817 
2818   for (unsigned I = 0; I < NumParts; ++I) {
2819     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2820     DstRegs.push_back(DstReg);
2821 
2822     if (MI.getOpcode() == TargetOpcode::G_ICMP)
2823       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2824     else {
2825       MachineInstr *NewCmp
2826         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2827       NewCmp->setFlags(MI.getFlags());
2828     }
2829   }
2830 
2831   if (NarrowTy1.isVector())
2832     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2833   else
2834     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2835 
2836   MI.eraseFromParent();
2837   return Legalized;
2838 }
2839 
2840 LegalizerHelper::LegalizeResult
2841 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
2842                                            LLT NarrowTy) {
2843   Register DstReg = MI.getOperand(0).getReg();
2844   Register CondReg = MI.getOperand(1).getReg();
2845 
2846   unsigned NumParts = 0;
2847   LLT NarrowTy0, NarrowTy1;
2848 
2849   LLT DstTy = MRI.getType(DstReg);
2850   LLT CondTy = MRI.getType(CondReg);
2851   unsigned Size = DstTy.getSizeInBits();
2852 
2853   assert(TypeIdx == 0 || CondTy.isVector());
2854 
2855   if (TypeIdx == 0) {
2856     NarrowTy0 = NarrowTy;
2857     NarrowTy1 = CondTy;
2858 
2859     unsigned NarrowSize = NarrowTy0.getSizeInBits();
2860     // FIXME: Don't know how to handle the situation where the small vectors
2861     // aren't all the same size yet.
2862     if (Size % NarrowSize != 0)
2863       return UnableToLegalize;
2864 
2865     NumParts = Size / NarrowSize;
2866 
2867     // Need to break down the condition type
2868     if (CondTy.isVector()) {
2869       if (CondTy.getNumElements() == NumParts)
2870         NarrowTy1 = CondTy.getElementType();
2871       else
2872         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
2873                                 CondTy.getScalarSizeInBits());
2874     }
2875   } else {
2876     NumParts = CondTy.getNumElements();
2877     if (NarrowTy.isVector()) {
2878       // TODO: Handle uneven breakdown.
2879       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
2880         return UnableToLegalize;
2881 
2882       return UnableToLegalize;
2883     } else {
2884       NarrowTy0 = DstTy.getElementType();
2885       NarrowTy1 = NarrowTy;
2886     }
2887   }
2888 
2889   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2890   if (CondTy.isVector())
2891     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2892 
2893   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2894   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2895 
2896   for (unsigned i = 0; i < NumParts; ++i) {
2897     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2898     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
2899                            Src1Regs[i], Src2Regs[i]);
2900     DstRegs.push_back(DstReg);
2901   }
2902 
2903   if (NarrowTy0.isVector())
2904     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2905   else
2906     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2907 
2908   MI.eraseFromParent();
2909   return Legalized;
2910 }
2911 
2912 LegalizerHelper::LegalizeResult
2913 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2914                                         LLT NarrowTy) {
2915   const Register DstReg = MI.getOperand(0).getReg();
2916   LLT PhiTy = MRI.getType(DstReg);
2917   LLT LeftoverTy;
2918 
2919   // All of the operands need to have the same number of elements, so if we can
2920   // determine a type breakdown for the result type, we can for all of the
2921   // source types.
2922   int NumParts, NumLeftover;
2923   std::tie(NumParts, NumLeftover)
2924     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2925   if (NumParts < 0)
2926     return UnableToLegalize;
2927 
2928   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2929   SmallVector<MachineInstrBuilder, 4> NewInsts;
2930 
2931   const int TotalNumParts = NumParts + NumLeftover;
2932 
2933   // Insert the new phis in the result block first.
2934   for (int I = 0; I != TotalNumParts; ++I) {
2935     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2936     Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
2937     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2938                        .addDef(PartDstReg));
2939     if (I < NumParts)
2940       DstRegs.push_back(PartDstReg);
2941     else
2942       LeftoverDstRegs.push_back(PartDstReg);
2943   }
2944 
2945   MachineBasicBlock *MBB = MI.getParent();
2946   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2947   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2948 
2949   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2950 
2951   // Insert code to extract the incoming values in each predecessor block.
2952   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2953     PartRegs.clear();
2954     LeftoverRegs.clear();
2955 
2956     Register SrcReg = MI.getOperand(I).getReg();
2957     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2958     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2959 
2960     LLT Unused;
2961     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2962                       LeftoverRegs))
2963       return UnableToLegalize;
2964 
2965     // Add the newly created operand splits to the existing instructions. The
2966     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2967     // pieces.
2968     for (int J = 0; J != TotalNumParts; ++J) {
2969       MachineInstrBuilder MIB = NewInsts[J];
2970       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2971       MIB.addMBB(&OpMBB);
2972     }
2973   }
2974 
2975   MI.eraseFromParent();
2976   return Legalized;
2977 }
2978 
2979 LegalizerHelper::LegalizeResult
2980 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
2981                                                   unsigned TypeIdx,
2982                                                   LLT NarrowTy) {
2983   if (TypeIdx != 1)
2984     return UnableToLegalize;
2985 
2986   const int NumDst = MI.getNumOperands() - 1;
2987   const Register SrcReg = MI.getOperand(NumDst).getReg();
2988   LLT SrcTy = MRI.getType(SrcReg);
2989 
2990   LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2991 
2992   // TODO: Create sequence of extracts.
2993   if (DstTy == NarrowTy)
2994     return UnableToLegalize;
2995 
2996   LLT GCDTy = getGCDType(SrcTy, NarrowTy);
2997   if (DstTy == GCDTy) {
2998     // This would just be a copy of the same unmerge.
2999     // TODO: Create extracts, pad with undef and create intermediate merges.
3000     return UnableToLegalize;
3001   }
3002 
3003   auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
3004   const int NumUnmerge = Unmerge->getNumOperands() - 1;
3005   const int PartsPerUnmerge = NumDst / NumUnmerge;
3006 
3007   for (int I = 0; I != NumUnmerge; ++I) {
3008     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
3009 
3010     for (int J = 0; J != PartsPerUnmerge; ++J)
3011       MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg());
3012     MIB.addUse(Unmerge.getReg(I));
3013   }
3014 
3015   MI.eraseFromParent();
3016   return Legalized;
3017 }
3018 
3019 LegalizerHelper::LegalizeResult
3020 LegalizerHelper::fewerElementsVectorBuildVector(MachineInstr &MI,
3021                                                 unsigned TypeIdx,
3022                                                 LLT NarrowTy) {
3023   assert(TypeIdx == 0 && "not a vector type index");
3024   Register DstReg = MI.getOperand(0).getReg();
3025   LLT DstTy = MRI.getType(DstReg);
3026   LLT SrcTy = DstTy.getElementType();
3027 
3028   int DstNumElts = DstTy.getNumElements();
3029   int NarrowNumElts = NarrowTy.getNumElements();
3030   int NumConcat = (DstNumElts + NarrowNumElts - 1) / NarrowNumElts;
3031   LLT WidenedDstTy = LLT::vector(NarrowNumElts * NumConcat, SrcTy);
3032 
3033   SmallVector<Register, 8> ConcatOps;
3034   SmallVector<Register, 8> SubBuildVector;
3035 
3036   Register UndefReg;
3037   if (WidenedDstTy != DstTy)
3038     UndefReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
3039 
3040   // Create a G_CONCAT_VECTORS of NarrowTy pieces, padding with undef as
3041   // necessary.
3042   //
3043   // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2
3044   //   -> <2 x s16>
3045   //
3046   // %4:_(s16) = G_IMPLICIT_DEF
3047   // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1
3048   // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4
3049   // %7:_(<4 x s16>) = G_CONCAT_VECTORS %5, %6
3050   // %3:_(<3 x s16>) = G_EXTRACT %7, 0
3051   for (int I = 0; I != NumConcat; ++I) {
3052     for (int J = 0; J != NarrowNumElts; ++J) {
3053       int SrcIdx = NarrowNumElts * I + J;
3054 
3055       if (SrcIdx < DstNumElts) {
3056         Register SrcReg = MI.getOperand(SrcIdx + 1).getReg();
3057         SubBuildVector.push_back(SrcReg);
3058       } else
3059         SubBuildVector.push_back(UndefReg);
3060     }
3061 
3062     auto BuildVec = MIRBuilder.buildBuildVector(NarrowTy, SubBuildVector);
3063     ConcatOps.push_back(BuildVec.getReg(0));
3064     SubBuildVector.clear();
3065   }
3066 
3067   if (DstTy == WidenedDstTy)
3068     MIRBuilder.buildConcatVectors(DstReg, ConcatOps);
3069   else {
3070     auto Concat = MIRBuilder.buildConcatVectors(WidenedDstTy, ConcatOps);
3071     MIRBuilder.buildExtract(DstReg, Concat, 0);
3072   }
3073 
3074   MI.eraseFromParent();
3075   return Legalized;
3076 }
3077 
3078 LegalizerHelper::LegalizeResult
3079 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
3080                                       LLT NarrowTy) {
3081   // FIXME: Don't know how to handle secondary types yet.
3082   if (TypeIdx != 0)
3083     return UnableToLegalize;
3084 
3085   MachineMemOperand *MMO = *MI.memoperands_begin();
3086 
3087   // This implementation doesn't work for atomics. Give up instead of doing
3088   // something invalid.
3089   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
3090       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
3091     return UnableToLegalize;
3092 
3093   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
3094   Register ValReg = MI.getOperand(0).getReg();
3095   Register AddrReg = MI.getOperand(1).getReg();
3096   LLT ValTy = MRI.getType(ValReg);
3097 
3098   int NumParts = -1;
3099   int NumLeftover = -1;
3100   LLT LeftoverTy;
3101   SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
3102   if (IsLoad) {
3103     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
3104   } else {
3105     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
3106                      NarrowLeftoverRegs)) {
3107       NumParts = NarrowRegs.size();
3108       NumLeftover = NarrowLeftoverRegs.size();
3109     }
3110   }
3111 
3112   if (NumParts == -1)
3113     return UnableToLegalize;
3114 
3115   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
3116 
3117   unsigned TotalSize = ValTy.getSizeInBits();
3118 
3119   // Split the load/store into PartTy sized pieces starting at Offset. If this
3120   // is a load, return the new registers in ValRegs. For a store, each elements
3121   // of ValRegs should be PartTy. Returns the next offset that needs to be
3122   // handled.
3123   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
3124                              unsigned Offset) -> unsigned {
3125     MachineFunction &MF = MIRBuilder.getMF();
3126     unsigned PartSize = PartTy.getSizeInBits();
3127     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
3128          Offset += PartSize, ++Idx) {
3129       unsigned ByteSize = PartSize / 8;
3130       unsigned ByteOffset = Offset / 8;
3131       Register NewAddrReg;
3132 
3133       MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
3134 
3135       MachineMemOperand *NewMMO =
3136         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
3137 
3138       if (IsLoad) {
3139         Register Dst = MRI.createGenericVirtualRegister(PartTy);
3140         ValRegs.push_back(Dst);
3141         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
3142       } else {
3143         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
3144       }
3145     }
3146 
3147     return Offset;
3148   };
3149 
3150   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
3151 
3152   // Handle the rest of the register if this isn't an even type breakdown.
3153   if (LeftoverTy.isValid())
3154     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
3155 
3156   if (IsLoad) {
3157     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
3158                 LeftoverTy, NarrowLeftoverRegs);
3159   }
3160 
3161   MI.eraseFromParent();
3162   return Legalized;
3163 }
3164 
3165 LegalizerHelper::LegalizeResult
3166 LegalizerHelper::fewerElementsVectorSextInReg(MachineInstr &MI, unsigned TypeIdx,
3167                                               LLT NarrowTy) {
3168   Register DstReg = MI.getOperand(0).getReg();
3169   Register SrcReg = MI.getOperand(1).getReg();
3170   int64_t Imm = MI.getOperand(2).getImm();
3171 
3172   LLT DstTy = MRI.getType(DstReg);
3173 
3174   SmallVector<Register, 8> Parts;
3175   LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg);
3176   LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts);
3177 
3178   for (Register &R : Parts)
3179     R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0);
3180 
3181   buildWidenedRemergeToDst(DstReg, LCMTy, Parts);
3182 
3183   MI.eraseFromParent();
3184   return Legalized;
3185 }
3186 
3187 LegalizerHelper::LegalizeResult
3188 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
3189                                      LLT NarrowTy) {
3190   using namespace TargetOpcode;
3191 
3192   MIRBuilder.setInstr(MI);
3193   switch (MI.getOpcode()) {
3194   case G_IMPLICIT_DEF:
3195     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
3196   case G_AND:
3197   case G_OR:
3198   case G_XOR:
3199   case G_ADD:
3200   case G_SUB:
3201   case G_MUL:
3202   case G_SMULH:
3203   case G_UMULH:
3204   case G_FADD:
3205   case G_FMUL:
3206   case G_FSUB:
3207   case G_FNEG:
3208   case G_FABS:
3209   case G_FCANONICALIZE:
3210   case G_FDIV:
3211   case G_FREM:
3212   case G_FMA:
3213   case G_FMAD:
3214   case G_FPOW:
3215   case G_FEXP:
3216   case G_FEXP2:
3217   case G_FLOG:
3218   case G_FLOG2:
3219   case G_FLOG10:
3220   case G_FNEARBYINT:
3221   case G_FCEIL:
3222   case G_FFLOOR:
3223   case G_FRINT:
3224   case G_INTRINSIC_ROUND:
3225   case G_INTRINSIC_TRUNC:
3226   case G_FCOS:
3227   case G_FSIN:
3228   case G_FSQRT:
3229   case G_BSWAP:
3230   case G_BITREVERSE:
3231   case G_SDIV:
3232   case G_UDIV:
3233   case G_SREM:
3234   case G_UREM:
3235   case G_SMIN:
3236   case G_SMAX:
3237   case G_UMIN:
3238   case G_UMAX:
3239   case G_FMINNUM:
3240   case G_FMAXNUM:
3241   case G_FMINNUM_IEEE:
3242   case G_FMAXNUM_IEEE:
3243   case G_FMINIMUM:
3244   case G_FMAXIMUM:
3245     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
3246   case G_SHL:
3247   case G_LSHR:
3248   case G_ASHR:
3249   case G_CTLZ:
3250   case G_CTLZ_ZERO_UNDEF:
3251   case G_CTTZ:
3252   case G_CTTZ_ZERO_UNDEF:
3253   case G_CTPOP:
3254   case G_FCOPYSIGN:
3255     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
3256   case G_ZEXT:
3257   case G_SEXT:
3258   case G_ANYEXT:
3259   case G_FPEXT:
3260   case G_FPTRUNC:
3261   case G_SITOFP:
3262   case G_UITOFP:
3263   case G_FPTOSI:
3264   case G_FPTOUI:
3265   case G_INTTOPTR:
3266   case G_PTRTOINT:
3267   case G_ADDRSPACE_CAST:
3268     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
3269   case G_ICMP:
3270   case G_FCMP:
3271     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
3272   case G_SELECT:
3273     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
3274   case G_PHI:
3275     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
3276   case G_UNMERGE_VALUES:
3277     return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy);
3278   case G_BUILD_VECTOR:
3279     return fewerElementsVectorBuildVector(MI, TypeIdx, NarrowTy);
3280   case G_LOAD:
3281   case G_STORE:
3282     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
3283   case G_SEXT_INREG:
3284     return fewerElementsVectorSextInReg(MI, TypeIdx, NarrowTy);
3285   default:
3286     return UnableToLegalize;
3287   }
3288 }
3289 
3290 LegalizerHelper::LegalizeResult
3291 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
3292                                              const LLT HalfTy, const LLT AmtTy) {
3293 
3294   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3295   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3296   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1));
3297 
3298   if (Amt.isNullValue()) {
3299     MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH});
3300     MI.eraseFromParent();
3301     return Legalized;
3302   }
3303 
3304   LLT NVT = HalfTy;
3305   unsigned NVTBits = HalfTy.getSizeInBits();
3306   unsigned VTBits = 2 * NVTBits;
3307 
3308   SrcOp Lo(Register(0)), Hi(Register(0));
3309   if (MI.getOpcode() == TargetOpcode::G_SHL) {
3310     if (Amt.ugt(VTBits)) {
3311       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3312     } else if (Amt.ugt(NVTBits)) {
3313       Lo = MIRBuilder.buildConstant(NVT, 0);
3314       Hi = MIRBuilder.buildShl(NVT, InL,
3315                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3316     } else if (Amt == NVTBits) {
3317       Lo = MIRBuilder.buildConstant(NVT, 0);
3318       Hi = InL;
3319     } else {
3320       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
3321       auto OrLHS =
3322           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
3323       auto OrRHS = MIRBuilder.buildLShr(
3324           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3325       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3326     }
3327   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3328     if (Amt.ugt(VTBits)) {
3329       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3330     } else if (Amt.ugt(NVTBits)) {
3331       Lo = MIRBuilder.buildLShr(NVT, InH,
3332                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3333       Hi = MIRBuilder.buildConstant(NVT, 0);
3334     } else if (Amt == NVTBits) {
3335       Lo = InH;
3336       Hi = MIRBuilder.buildConstant(NVT, 0);
3337     } else {
3338       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3339 
3340       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3341       auto OrRHS = MIRBuilder.buildShl(
3342           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3343 
3344       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3345       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
3346     }
3347   } else {
3348     if (Amt.ugt(VTBits)) {
3349       Hi = Lo = MIRBuilder.buildAShr(
3350           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3351     } else if (Amt.ugt(NVTBits)) {
3352       Lo = MIRBuilder.buildAShr(NVT, InH,
3353                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3354       Hi = MIRBuilder.buildAShr(NVT, InH,
3355                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3356     } else if (Amt == NVTBits) {
3357       Lo = InH;
3358       Hi = MIRBuilder.buildAShr(NVT, InH,
3359                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3360     } else {
3361       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3362 
3363       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3364       auto OrRHS = MIRBuilder.buildShl(
3365           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3366 
3367       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3368       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
3369     }
3370   }
3371 
3372   MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi});
3373   MI.eraseFromParent();
3374 
3375   return Legalized;
3376 }
3377 
3378 // TODO: Optimize if constant shift amount.
3379 LegalizerHelper::LegalizeResult
3380 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
3381                                    LLT RequestedTy) {
3382   if (TypeIdx == 1) {
3383     Observer.changingInstr(MI);
3384     narrowScalarSrc(MI, RequestedTy, 2);
3385     Observer.changedInstr(MI);
3386     return Legalized;
3387   }
3388 
3389   Register DstReg = MI.getOperand(0).getReg();
3390   LLT DstTy = MRI.getType(DstReg);
3391   if (DstTy.isVector())
3392     return UnableToLegalize;
3393 
3394   Register Amt = MI.getOperand(2).getReg();
3395   LLT ShiftAmtTy = MRI.getType(Amt);
3396   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
3397   if (DstEltSize % 2 != 0)
3398     return UnableToLegalize;
3399 
3400   // Ignore the input type. We can only go to exactly half the size of the
3401   // input. If that isn't small enough, the resulting pieces will be further
3402   // legalized.
3403   const unsigned NewBitSize = DstEltSize / 2;
3404   const LLT HalfTy = LLT::scalar(NewBitSize);
3405   const LLT CondTy = LLT::scalar(1);
3406 
3407   if (const MachineInstr *KShiftAmt =
3408           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
3409     return narrowScalarShiftByConstant(
3410         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
3411   }
3412 
3413   // TODO: Expand with known bits.
3414 
3415   // Handle the fully general expansion by an unknown amount.
3416   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
3417 
3418   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3419   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3420   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1));
3421 
3422   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
3423   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
3424 
3425   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
3426   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
3427   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
3428 
3429   Register ResultRegs[2];
3430   switch (MI.getOpcode()) {
3431   case TargetOpcode::G_SHL: {
3432     // Short: ShAmt < NewBitSize
3433     auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt);
3434 
3435     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
3436     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt);
3437     auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3438 
3439     // Long: ShAmt >= NewBitSize
3440     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
3441     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
3442 
3443     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
3444     auto Hi = MIRBuilder.buildSelect(
3445         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
3446 
3447     ResultRegs[0] = Lo.getReg(0);
3448     ResultRegs[1] = Hi.getReg(0);
3449     break;
3450   }
3451   case TargetOpcode::G_LSHR:
3452   case TargetOpcode::G_ASHR: {
3453     // Short: ShAmt < NewBitSize
3454     auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt});
3455 
3456     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt);
3457     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
3458     auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3459 
3460     // Long: ShAmt >= NewBitSize
3461     MachineInstrBuilder HiL;
3462     if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3463       HiL = MIRBuilder.buildConstant(HalfTy, 0);            // Hi part is zero.
3464     } else {
3465       auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1);
3466       HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt);    // Sign of Hi part.
3467     }
3468     auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy},
3469                                      {InH, AmtExcess});     // Lo from Hi part.
3470 
3471     auto Lo = MIRBuilder.buildSelect(
3472         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
3473 
3474     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
3475 
3476     ResultRegs[0] = Lo.getReg(0);
3477     ResultRegs[1] = Hi.getReg(0);
3478     break;
3479   }
3480   default:
3481     llvm_unreachable("not a shift");
3482   }
3483 
3484   MIRBuilder.buildMerge(DstReg, ResultRegs);
3485   MI.eraseFromParent();
3486   return Legalized;
3487 }
3488 
3489 LegalizerHelper::LegalizeResult
3490 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
3491                                        LLT MoreTy) {
3492   assert(TypeIdx == 0 && "Expecting only Idx 0");
3493 
3494   Observer.changingInstr(MI);
3495   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
3496     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
3497     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
3498     moreElementsVectorSrc(MI, MoreTy, I);
3499   }
3500 
3501   MachineBasicBlock &MBB = *MI.getParent();
3502   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
3503   moreElementsVectorDst(MI, MoreTy, 0);
3504   Observer.changedInstr(MI);
3505   return Legalized;
3506 }
3507 
3508 LegalizerHelper::LegalizeResult
3509 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
3510                                     LLT MoreTy) {
3511   MIRBuilder.setInstr(MI);
3512   unsigned Opc = MI.getOpcode();
3513   switch (Opc) {
3514   case TargetOpcode::G_IMPLICIT_DEF:
3515   case TargetOpcode::G_LOAD: {
3516     if (TypeIdx != 0)
3517       return UnableToLegalize;
3518     Observer.changingInstr(MI);
3519     moreElementsVectorDst(MI, MoreTy, 0);
3520     Observer.changedInstr(MI);
3521     return Legalized;
3522   }
3523   case TargetOpcode::G_STORE:
3524     if (TypeIdx != 0)
3525       return UnableToLegalize;
3526     Observer.changingInstr(MI);
3527     moreElementsVectorSrc(MI, MoreTy, 0);
3528     Observer.changedInstr(MI);
3529     return Legalized;
3530   case TargetOpcode::G_AND:
3531   case TargetOpcode::G_OR:
3532   case TargetOpcode::G_XOR:
3533   case TargetOpcode::G_SMIN:
3534   case TargetOpcode::G_SMAX:
3535   case TargetOpcode::G_UMIN:
3536   case TargetOpcode::G_UMAX:
3537   case TargetOpcode::G_FMINNUM:
3538   case TargetOpcode::G_FMAXNUM:
3539   case TargetOpcode::G_FMINNUM_IEEE:
3540   case TargetOpcode::G_FMAXNUM_IEEE:
3541   case TargetOpcode::G_FMINIMUM:
3542   case TargetOpcode::G_FMAXIMUM: {
3543     Observer.changingInstr(MI);
3544     moreElementsVectorSrc(MI, MoreTy, 1);
3545     moreElementsVectorSrc(MI, MoreTy, 2);
3546     moreElementsVectorDst(MI, MoreTy, 0);
3547     Observer.changedInstr(MI);
3548     return Legalized;
3549   }
3550   case TargetOpcode::G_EXTRACT:
3551     if (TypeIdx != 1)
3552       return UnableToLegalize;
3553     Observer.changingInstr(MI);
3554     moreElementsVectorSrc(MI, MoreTy, 1);
3555     Observer.changedInstr(MI);
3556     return Legalized;
3557   case TargetOpcode::G_INSERT:
3558     if (TypeIdx != 0)
3559       return UnableToLegalize;
3560     Observer.changingInstr(MI);
3561     moreElementsVectorSrc(MI, MoreTy, 1);
3562     moreElementsVectorDst(MI, MoreTy, 0);
3563     Observer.changedInstr(MI);
3564     return Legalized;
3565   case TargetOpcode::G_SELECT:
3566     if (TypeIdx != 0)
3567       return UnableToLegalize;
3568     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
3569       return UnableToLegalize;
3570 
3571     Observer.changingInstr(MI);
3572     moreElementsVectorSrc(MI, MoreTy, 2);
3573     moreElementsVectorSrc(MI, MoreTy, 3);
3574     moreElementsVectorDst(MI, MoreTy, 0);
3575     Observer.changedInstr(MI);
3576     return Legalized;
3577   case TargetOpcode::G_UNMERGE_VALUES: {
3578     if (TypeIdx != 1)
3579       return UnableToLegalize;
3580 
3581     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
3582     int NumDst = MI.getNumOperands() - 1;
3583     moreElementsVectorSrc(MI, MoreTy, NumDst);
3584 
3585     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
3586     for (int I = 0; I != NumDst; ++I)
3587       MIB.addDef(MI.getOperand(I).getReg());
3588 
3589     int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits();
3590     for (int I = NumDst; I != NewNumDst; ++I)
3591       MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
3592 
3593     MIB.addUse(MI.getOperand(NumDst).getReg());
3594     MI.eraseFromParent();
3595     return Legalized;
3596   }
3597   case TargetOpcode::G_PHI:
3598     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
3599   default:
3600     return UnableToLegalize;
3601   }
3602 }
3603 
3604 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
3605                                         ArrayRef<Register> Src1Regs,
3606                                         ArrayRef<Register> Src2Regs,
3607                                         LLT NarrowTy) {
3608   MachineIRBuilder &B = MIRBuilder;
3609   unsigned SrcParts = Src1Regs.size();
3610   unsigned DstParts = DstRegs.size();
3611 
3612   unsigned DstIdx = 0; // Low bits of the result.
3613   Register FactorSum =
3614       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
3615   DstRegs[DstIdx] = FactorSum;
3616 
3617   unsigned CarrySumPrevDstIdx;
3618   SmallVector<Register, 4> Factors;
3619 
3620   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
3621     // Collect low parts of muls for DstIdx.
3622     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
3623          i <= std::min(DstIdx, SrcParts - 1); ++i) {
3624       MachineInstrBuilder Mul =
3625           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
3626       Factors.push_back(Mul.getReg(0));
3627     }
3628     // Collect high parts of muls from previous DstIdx.
3629     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
3630          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
3631       MachineInstrBuilder Umulh =
3632           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
3633       Factors.push_back(Umulh.getReg(0));
3634     }
3635     // Add CarrySum from additions calculated for previous DstIdx.
3636     if (DstIdx != 1) {
3637       Factors.push_back(CarrySumPrevDstIdx);
3638     }
3639 
3640     Register CarrySum;
3641     // Add all factors and accumulate all carries into CarrySum.
3642     if (DstIdx != DstParts - 1) {
3643       MachineInstrBuilder Uaddo =
3644           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
3645       FactorSum = Uaddo.getReg(0);
3646       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
3647       for (unsigned i = 2; i < Factors.size(); ++i) {
3648         MachineInstrBuilder Uaddo =
3649             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
3650         FactorSum = Uaddo.getReg(0);
3651         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
3652         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
3653       }
3654     } else {
3655       // Since value for the next index is not calculated, neither is CarrySum.
3656       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
3657       for (unsigned i = 2; i < Factors.size(); ++i)
3658         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
3659     }
3660 
3661     CarrySumPrevDstIdx = CarrySum;
3662     DstRegs[DstIdx] = FactorSum;
3663     Factors.clear();
3664   }
3665 }
3666 
3667 LegalizerHelper::LegalizeResult
3668 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
3669   Register DstReg = MI.getOperand(0).getReg();
3670   Register Src1 = MI.getOperand(1).getReg();
3671   Register Src2 = MI.getOperand(2).getReg();
3672 
3673   LLT Ty = MRI.getType(DstReg);
3674   if (Ty.isVector())
3675     return UnableToLegalize;
3676 
3677   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
3678   unsigned DstSize = Ty.getSizeInBits();
3679   unsigned NarrowSize = NarrowTy.getSizeInBits();
3680   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
3681     return UnableToLegalize;
3682 
3683   unsigned NumDstParts = DstSize / NarrowSize;
3684   unsigned NumSrcParts = SrcSize / NarrowSize;
3685   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
3686   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
3687 
3688   SmallVector<Register, 2> Src1Parts, Src2Parts;
3689   SmallVector<Register, 2> DstTmpRegs(DstTmpParts);
3690   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
3691   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
3692   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
3693 
3694   // Take only high half of registers if this is high mul.
3695   ArrayRef<Register> DstRegs(
3696       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
3697   MIRBuilder.buildMerge(DstReg, DstRegs);
3698   MI.eraseFromParent();
3699   return Legalized;
3700 }
3701 
3702 LegalizerHelper::LegalizeResult
3703 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
3704                                      LLT NarrowTy) {
3705   if (TypeIdx != 1)
3706     return UnableToLegalize;
3707 
3708   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3709 
3710   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
3711   // FIXME: add support for when SizeOp1 isn't an exact multiple of
3712   // NarrowSize.
3713   if (SizeOp1 % NarrowSize != 0)
3714     return UnableToLegalize;
3715   int NumParts = SizeOp1 / NarrowSize;
3716 
3717   SmallVector<Register, 2> SrcRegs, DstRegs;
3718   SmallVector<uint64_t, 2> Indexes;
3719   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3720 
3721   Register OpReg = MI.getOperand(0).getReg();
3722   uint64_t OpStart = MI.getOperand(2).getImm();
3723   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3724   for (int i = 0; i < NumParts; ++i) {
3725     unsigned SrcStart = i * NarrowSize;
3726 
3727     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
3728       // No part of the extract uses this subregister, ignore it.
3729       continue;
3730     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3731       // The entire subregister is extracted, forward the value.
3732       DstRegs.push_back(SrcRegs[i]);
3733       continue;
3734     }
3735 
3736     // OpSegStart is where this destination segment would start in OpReg if it
3737     // extended infinitely in both directions.
3738     int64_t ExtractOffset;
3739     uint64_t SegSize;
3740     if (OpStart < SrcStart) {
3741       ExtractOffset = 0;
3742       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
3743     } else {
3744       ExtractOffset = OpStart - SrcStart;
3745       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
3746     }
3747 
3748     Register SegReg = SrcRegs[i];
3749     if (ExtractOffset != 0 || SegSize != NarrowSize) {
3750       // A genuine extract is needed.
3751       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3752       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
3753     }
3754 
3755     DstRegs.push_back(SegReg);
3756   }
3757 
3758   Register DstReg = MI.getOperand(0).getReg();
3759   if(MRI.getType(DstReg).isVector())
3760     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3761   else
3762     MIRBuilder.buildMerge(DstReg, DstRegs);
3763   MI.eraseFromParent();
3764   return Legalized;
3765 }
3766 
3767 LegalizerHelper::LegalizeResult
3768 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
3769                                     LLT NarrowTy) {
3770   // FIXME: Don't know how to handle secondary types yet.
3771   if (TypeIdx != 0)
3772     return UnableToLegalize;
3773 
3774   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
3775   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3776 
3777   // FIXME: add support for when SizeOp0 isn't an exact multiple of
3778   // NarrowSize.
3779   if (SizeOp0 % NarrowSize != 0)
3780     return UnableToLegalize;
3781 
3782   int NumParts = SizeOp0 / NarrowSize;
3783 
3784   SmallVector<Register, 2> SrcRegs, DstRegs;
3785   SmallVector<uint64_t, 2> Indexes;
3786   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3787 
3788   Register OpReg = MI.getOperand(2).getReg();
3789   uint64_t OpStart = MI.getOperand(3).getImm();
3790   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3791   for (int i = 0; i < NumParts; ++i) {
3792     unsigned DstStart = i * NarrowSize;
3793 
3794     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
3795       // No part of the insert affects this subregister, forward the original.
3796       DstRegs.push_back(SrcRegs[i]);
3797       continue;
3798     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3799       // The entire subregister is defined by this insert, forward the new
3800       // value.
3801       DstRegs.push_back(OpReg);
3802       continue;
3803     }
3804 
3805     // OpSegStart is where this destination segment would start in OpReg if it
3806     // extended infinitely in both directions.
3807     int64_t ExtractOffset, InsertOffset;
3808     uint64_t SegSize;
3809     if (OpStart < DstStart) {
3810       InsertOffset = 0;
3811       ExtractOffset = DstStart - OpStart;
3812       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
3813     } else {
3814       InsertOffset = OpStart - DstStart;
3815       ExtractOffset = 0;
3816       SegSize =
3817         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
3818     }
3819 
3820     Register SegReg = OpReg;
3821     if (ExtractOffset != 0 || SegSize != OpSize) {
3822       // A genuine extract is needed.
3823       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3824       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
3825     }
3826 
3827     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
3828     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
3829     DstRegs.push_back(DstReg);
3830   }
3831 
3832   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
3833   Register DstReg = MI.getOperand(0).getReg();
3834   if(MRI.getType(DstReg).isVector())
3835     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3836   else
3837     MIRBuilder.buildMerge(DstReg, DstRegs);
3838   MI.eraseFromParent();
3839   return Legalized;
3840 }
3841 
3842 LegalizerHelper::LegalizeResult
3843 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
3844                                    LLT NarrowTy) {
3845   Register DstReg = MI.getOperand(0).getReg();
3846   LLT DstTy = MRI.getType(DstReg);
3847 
3848   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
3849 
3850   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3851   SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
3852   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3853   LLT LeftoverTy;
3854   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
3855                     Src0Regs, Src0LeftoverRegs))
3856     return UnableToLegalize;
3857 
3858   LLT Unused;
3859   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
3860                     Src1Regs, Src1LeftoverRegs))
3861     llvm_unreachable("inconsistent extractParts result");
3862 
3863   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3864     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
3865                                         {Src0Regs[I], Src1Regs[I]});
3866     DstRegs.push_back(Inst.getReg(0));
3867   }
3868 
3869   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3870     auto Inst = MIRBuilder.buildInstr(
3871       MI.getOpcode(),
3872       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
3873     DstLeftoverRegs.push_back(Inst.getReg(0));
3874   }
3875 
3876   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3877               LeftoverTy, DstLeftoverRegs);
3878 
3879   MI.eraseFromParent();
3880   return Legalized;
3881 }
3882 
3883 LegalizerHelper::LegalizeResult
3884 LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx,
3885                                  LLT NarrowTy) {
3886   if (TypeIdx != 0)
3887     return UnableToLegalize;
3888 
3889   Register DstReg = MI.getOperand(0).getReg();
3890   Register SrcReg = MI.getOperand(1).getReg();
3891 
3892   LLT DstTy = MRI.getType(DstReg);
3893   if (DstTy.isVector())
3894     return UnableToLegalize;
3895 
3896   SmallVector<Register, 8> Parts;
3897   LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg);
3898   LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, MI.getOpcode());
3899   buildWidenedRemergeToDst(DstReg, LCMTy, Parts);
3900 
3901   MI.eraseFromParent();
3902   return Legalized;
3903 }
3904 
3905 LegalizerHelper::LegalizeResult
3906 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
3907                                     LLT NarrowTy) {
3908   if (TypeIdx != 0)
3909     return UnableToLegalize;
3910 
3911   Register CondReg = MI.getOperand(1).getReg();
3912   LLT CondTy = MRI.getType(CondReg);
3913   if (CondTy.isVector()) // TODO: Handle vselect
3914     return UnableToLegalize;
3915 
3916   Register DstReg = MI.getOperand(0).getReg();
3917   LLT DstTy = MRI.getType(DstReg);
3918 
3919   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3920   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3921   SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
3922   LLT LeftoverTy;
3923   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
3924                     Src1Regs, Src1LeftoverRegs))
3925     return UnableToLegalize;
3926 
3927   LLT Unused;
3928   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
3929                     Src2Regs, Src2LeftoverRegs))
3930     llvm_unreachable("inconsistent extractParts result");
3931 
3932   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3933     auto Select = MIRBuilder.buildSelect(NarrowTy,
3934                                          CondReg, Src1Regs[I], Src2Regs[I]);
3935     DstRegs.push_back(Select.getReg(0));
3936   }
3937 
3938   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3939     auto Select = MIRBuilder.buildSelect(
3940       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
3941     DstLeftoverRegs.push_back(Select.getReg(0));
3942   }
3943 
3944   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3945               LeftoverTy, DstLeftoverRegs);
3946 
3947   MI.eraseFromParent();
3948   return Legalized;
3949 }
3950 
3951 LegalizerHelper::LegalizeResult
3952 LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx,
3953                                   LLT NarrowTy) {
3954   if (TypeIdx != 1)
3955     return UnableToLegalize;
3956 
3957   Register DstReg = MI.getOperand(0).getReg();
3958   Register SrcReg = MI.getOperand(1).getReg();
3959   LLT DstTy = MRI.getType(DstReg);
3960   LLT SrcTy = MRI.getType(SrcReg);
3961   unsigned NarrowSize = NarrowTy.getSizeInBits();
3962 
3963   if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
3964     const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF;
3965 
3966     MachineIRBuilder &B = MIRBuilder;
3967     auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg);
3968     // ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi)
3969     auto C_0 = B.buildConstant(NarrowTy, 0);
3970     auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3971                                 UnmergeSrc.getReg(1), C_0);
3972     auto LoCTLZ = IsUndef ?
3973       B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)) :
3974       B.buildCTLZ(DstTy, UnmergeSrc.getReg(0));
3975     auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize);
3976     auto HiIsZeroCTLZ = B.buildAdd(DstTy, LoCTLZ, C_NarrowSize);
3977     auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1));
3978     B.buildSelect(DstReg, HiIsZero, HiIsZeroCTLZ, HiCTLZ);
3979 
3980     MI.eraseFromParent();
3981     return Legalized;
3982   }
3983 
3984   return UnableToLegalize;
3985 }
3986 
3987 LegalizerHelper::LegalizeResult
3988 LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx,
3989                                   LLT NarrowTy) {
3990   if (TypeIdx != 1)
3991     return UnableToLegalize;
3992 
3993   Register DstReg = MI.getOperand(0).getReg();
3994   Register SrcReg = MI.getOperand(1).getReg();
3995   LLT DstTy = MRI.getType(DstReg);
3996   LLT SrcTy = MRI.getType(SrcReg);
3997   unsigned NarrowSize = NarrowTy.getSizeInBits();
3998 
3999   if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
4000     const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF;
4001 
4002     MachineIRBuilder &B = MIRBuilder;
4003     auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg);
4004     // cttz(Hi:Lo) -> Lo == 0 ? (cttz(Hi) + NarrowSize) : cttz(Lo)
4005     auto C_0 = B.buildConstant(NarrowTy, 0);
4006     auto LoIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
4007                                 UnmergeSrc.getReg(0), C_0);
4008     auto HiCTTZ = IsUndef ?
4009       B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)) :
4010       B.buildCTTZ(DstTy, UnmergeSrc.getReg(1));
4011     auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize);
4012     auto LoIsZeroCTTZ = B.buildAdd(DstTy, HiCTTZ, C_NarrowSize);
4013     auto LoCTTZ = B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0));
4014     B.buildSelect(DstReg, LoIsZero, LoIsZeroCTTZ, LoCTTZ);
4015 
4016     MI.eraseFromParent();
4017     return Legalized;
4018   }
4019 
4020   return UnableToLegalize;
4021 }
4022 
4023 LegalizerHelper::LegalizeResult
4024 LegalizerHelper::narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx,
4025                                    LLT NarrowTy) {
4026   if (TypeIdx != 1)
4027     return UnableToLegalize;
4028 
4029   Register DstReg = MI.getOperand(0).getReg();
4030   LLT DstTy = MRI.getType(DstReg);
4031   LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
4032   unsigned NarrowSize = NarrowTy.getSizeInBits();
4033 
4034   if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) {
4035     auto UnmergeSrc = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1));
4036 
4037     auto LoCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(0));
4038     auto HiCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(1));
4039     MIRBuilder.buildAdd(DstReg, HiCTPOP, LoCTPOP);
4040 
4041     MI.eraseFromParent();
4042     return Legalized;
4043   }
4044 
4045   return UnableToLegalize;
4046 }
4047 
4048 LegalizerHelper::LegalizeResult
4049 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4050   unsigned Opc = MI.getOpcode();
4051   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
4052   auto isSupported = [this](const LegalityQuery &Q) {
4053     auto QAction = LI.getAction(Q).Action;
4054     return QAction == Legal || QAction == Libcall || QAction == Custom;
4055   };
4056   switch (Opc) {
4057   default:
4058     return UnableToLegalize;
4059   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
4060     // This trivially expands to CTLZ.
4061     Observer.changingInstr(MI);
4062     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
4063     Observer.changedInstr(MI);
4064     return Legalized;
4065   }
4066   case TargetOpcode::G_CTLZ: {
4067     Register DstReg = MI.getOperand(0).getReg();
4068     Register SrcReg = MI.getOperand(1).getReg();
4069     LLT DstTy = MRI.getType(DstReg);
4070     LLT SrcTy = MRI.getType(SrcReg);
4071     unsigned Len = SrcTy.getSizeInBits();
4072 
4073     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) {
4074       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
4075       auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg);
4076       auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0);
4077       auto ICmp = MIRBuilder.buildICmp(
4078           CmpInst::ICMP_EQ, SrcTy.changeElementSize(1), SrcReg, ZeroSrc);
4079       auto LenConst = MIRBuilder.buildConstant(DstTy, Len);
4080       MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CtlzZU);
4081       MI.eraseFromParent();
4082       return Legalized;
4083     }
4084     // for now, we do this:
4085     // NewLen = NextPowerOf2(Len);
4086     // x = x | (x >> 1);
4087     // x = x | (x >> 2);
4088     // ...
4089     // x = x | (x >>16);
4090     // x = x | (x >>32); // for 64-bit input
4091     // Upto NewLen/2
4092     // return Len - popcount(x);
4093     //
4094     // Ref: "Hacker's Delight" by Henry Warren
4095     Register Op = SrcReg;
4096     unsigned NewLen = PowerOf2Ceil(Len);
4097     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
4098       auto MIBShiftAmt = MIRBuilder.buildConstant(SrcTy, 1ULL << i);
4099       auto MIBOp = MIRBuilder.buildOr(
4100           SrcTy, Op, MIRBuilder.buildLShr(SrcTy, Op, MIBShiftAmt));
4101       Op = MIBOp.getReg(0);
4102     }
4103     auto MIBPop = MIRBuilder.buildCTPOP(DstTy, Op);
4104     MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(DstTy, Len),
4105                         MIBPop);
4106     MI.eraseFromParent();
4107     return Legalized;
4108   }
4109   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
4110     // This trivially expands to CTTZ.
4111     Observer.changingInstr(MI);
4112     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
4113     Observer.changedInstr(MI);
4114     return Legalized;
4115   }
4116   case TargetOpcode::G_CTTZ: {
4117     Register DstReg = MI.getOperand(0).getReg();
4118     Register SrcReg = MI.getOperand(1).getReg();
4119     LLT DstTy = MRI.getType(DstReg);
4120     LLT SrcTy = MRI.getType(SrcReg);
4121 
4122     unsigned Len = SrcTy.getSizeInBits();
4123     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) {
4124       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
4125       // zero.
4126       auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg);
4127       auto Zero = MIRBuilder.buildConstant(SrcTy, 0);
4128       auto ICmp = MIRBuilder.buildICmp(
4129           CmpInst::ICMP_EQ, DstTy.changeElementSize(1), SrcReg, Zero);
4130       auto LenConst = MIRBuilder.buildConstant(DstTy, Len);
4131       MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CttzZU);
4132       MI.eraseFromParent();
4133       return Legalized;
4134     }
4135     // for now, we use: { return popcount(~x & (x - 1)); }
4136     // unless the target has ctlz but not ctpop, in which case we use:
4137     // { return 32 - nlz(~x & (x-1)); }
4138     // Ref: "Hacker's Delight" by Henry Warren
4139     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
4140     auto MIBNot = MIRBuilder.buildXor(Ty, SrcReg, MIBCstNeg1);
4141     auto MIBTmp = MIRBuilder.buildAnd(
4142         Ty, MIBNot, MIRBuilder.buildAdd(Ty, SrcReg, MIBCstNeg1));
4143     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
4144         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
4145       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
4146       MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen,
4147                           MIRBuilder.buildCTLZ(Ty, MIBTmp));
4148       MI.eraseFromParent();
4149       return Legalized;
4150     }
4151     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
4152     MI.getOperand(1).setReg(MIBTmp.getReg(0));
4153     return Legalized;
4154   }
4155   case TargetOpcode::G_CTPOP: {
4156     unsigned Size = Ty.getSizeInBits();
4157     MachineIRBuilder &B = MIRBuilder;
4158 
4159     // Count set bits in blocks of 2 bits. Default approach would be
4160     // B2Count = { val & 0x55555555 } + { (val >> 1) & 0x55555555 }
4161     // We use following formula instead:
4162     // B2Count = val - { (val >> 1) & 0x55555555 }
4163     // since it gives same result in blocks of 2 with one instruction less.
4164     auto C_1 = B.buildConstant(Ty, 1);
4165     auto B2Set1LoTo1Hi = B.buildLShr(Ty, MI.getOperand(1).getReg(), C_1);
4166     APInt B2Mask1HiTo0 = APInt::getSplat(Size, APInt(8, 0x55));
4167     auto C_B2Mask1HiTo0 = B.buildConstant(Ty, B2Mask1HiTo0);
4168     auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0);
4169     auto B2Count = B.buildSub(Ty, MI.getOperand(1).getReg(), B2Count1Hi);
4170 
4171     // In order to get count in blocks of 4 add values from adjacent block of 2.
4172     // B4Count = { B2Count & 0x33333333 } + { (B2Count >> 2) & 0x33333333 }
4173     auto C_2 = B.buildConstant(Ty, 2);
4174     auto B4Set2LoTo2Hi = B.buildLShr(Ty, B2Count, C_2);
4175     APInt B4Mask2HiTo0 = APInt::getSplat(Size, APInt(8, 0x33));
4176     auto C_B4Mask2HiTo0 = B.buildConstant(Ty, B4Mask2HiTo0);
4177     auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0);
4178     auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0);
4179     auto B4Count = B.buildAdd(Ty, B4HiB2Count, B4LoB2Count);
4180 
4181     // For count in blocks of 8 bits we don't have to mask high 4 bits before
4182     // addition since count value sits in range {0,...,8} and 4 bits are enough
4183     // to hold such binary values. After addition high 4 bits still hold count
4184     // of set bits in high 4 bit block, set them to zero and get 8 bit result.
4185     // B8Count = { B4Count + (B4Count >> 4) } & 0x0F0F0F0F
4186     auto C_4 = B.buildConstant(Ty, 4);
4187     auto B8HiB4Count = B.buildLShr(Ty, B4Count, C_4);
4188     auto B8CountDirty4Hi = B.buildAdd(Ty, B8HiB4Count, B4Count);
4189     APInt B8Mask4HiTo0 = APInt::getSplat(Size, APInt(8, 0x0F));
4190     auto C_B8Mask4HiTo0 = B.buildConstant(Ty, B8Mask4HiTo0);
4191     auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0);
4192 
4193     assert(Size<=128 && "Scalar size is too large for CTPOP lower algorithm");
4194     // 8 bits can hold CTPOP result of 128 bit int or smaller. Mul with this
4195     // bitmask will set 8 msb in ResTmp to sum of all B8Counts in 8 bit blocks.
4196     auto MulMask = B.buildConstant(Ty, APInt::getSplat(Size, APInt(8, 0x01)));
4197     auto ResTmp = B.buildMul(Ty, B8Count, MulMask);
4198 
4199     // Shift count result from 8 high bits to low bits.
4200     auto C_SizeM8 = B.buildConstant(Ty, Size - 8);
4201     B.buildLShr(MI.getOperand(0).getReg(), ResTmp, C_SizeM8);
4202 
4203     MI.eraseFromParent();
4204     return Legalized;
4205   }
4206   }
4207 }
4208 
4209 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
4210 // representation.
4211 LegalizerHelper::LegalizeResult
4212 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
4213   Register Dst = MI.getOperand(0).getReg();
4214   Register Src = MI.getOperand(1).getReg();
4215   const LLT S64 = LLT::scalar(64);
4216   const LLT S32 = LLT::scalar(32);
4217   const LLT S1 = LLT::scalar(1);
4218 
4219   assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
4220 
4221   // unsigned cul2f(ulong u) {
4222   //   uint lz = clz(u);
4223   //   uint e = (u != 0) ? 127U + 63U - lz : 0;
4224   //   u = (u << lz) & 0x7fffffffffffffffUL;
4225   //   ulong t = u & 0xffffffffffUL;
4226   //   uint v = (e << 23) | (uint)(u >> 40);
4227   //   uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
4228   //   return as_float(v + r);
4229   // }
4230 
4231   auto Zero32 = MIRBuilder.buildConstant(S32, 0);
4232   auto Zero64 = MIRBuilder.buildConstant(S64, 0);
4233 
4234   auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
4235 
4236   auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
4237   auto Sub = MIRBuilder.buildSub(S32, K, LZ);
4238 
4239   auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
4240   auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
4241 
4242   auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
4243   auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
4244 
4245   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
4246 
4247   auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
4248   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
4249 
4250   auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
4251   auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
4252   auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
4253 
4254   auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
4255   auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
4256   auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
4257   auto One = MIRBuilder.buildConstant(S32, 1);
4258 
4259   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
4260   auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
4261   auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
4262   MIRBuilder.buildAdd(Dst, V, R);
4263 
4264   return Legalized;
4265 }
4266 
4267 LegalizerHelper::LegalizeResult
4268 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4269   Register Dst = MI.getOperand(0).getReg();
4270   Register Src = MI.getOperand(1).getReg();
4271   LLT DstTy = MRI.getType(Dst);
4272   LLT SrcTy = MRI.getType(Src);
4273 
4274   if (SrcTy == LLT::scalar(1)) {
4275     auto True = MIRBuilder.buildFConstant(DstTy, 1.0);
4276     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
4277     MIRBuilder.buildSelect(Dst, Src, True, False);
4278     MI.eraseFromParent();
4279     return Legalized;
4280   }
4281 
4282   if (SrcTy != LLT::scalar(64))
4283     return UnableToLegalize;
4284 
4285   if (DstTy == LLT::scalar(32)) {
4286     // TODO: SelectionDAG has several alternative expansions to port which may
4287     // be more reasonble depending on the available instructions. If a target
4288     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
4289     // intermediate type, this is probably worse.
4290     return lowerU64ToF32BitOps(MI);
4291   }
4292 
4293   return UnableToLegalize;
4294 }
4295 
4296 LegalizerHelper::LegalizeResult
4297 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4298   Register Dst = MI.getOperand(0).getReg();
4299   Register Src = MI.getOperand(1).getReg();
4300   LLT DstTy = MRI.getType(Dst);
4301   LLT SrcTy = MRI.getType(Src);
4302 
4303   const LLT S64 = LLT::scalar(64);
4304   const LLT S32 = LLT::scalar(32);
4305   const LLT S1 = LLT::scalar(1);
4306 
4307   if (SrcTy == S1) {
4308     auto True = MIRBuilder.buildFConstant(DstTy, -1.0);
4309     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
4310     MIRBuilder.buildSelect(Dst, Src, True, False);
4311     MI.eraseFromParent();
4312     return Legalized;
4313   }
4314 
4315   if (SrcTy != S64)
4316     return UnableToLegalize;
4317 
4318   if (DstTy == S32) {
4319     // signed cl2f(long l) {
4320     //   long s = l >> 63;
4321     //   float r = cul2f((l + s) ^ s);
4322     //   return s ? -r : r;
4323     // }
4324     Register L = Src;
4325     auto SignBit = MIRBuilder.buildConstant(S64, 63);
4326     auto S = MIRBuilder.buildAShr(S64, L, SignBit);
4327 
4328     auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
4329     auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
4330     auto R = MIRBuilder.buildUITOFP(S32, Xor);
4331 
4332     auto RNeg = MIRBuilder.buildFNeg(S32, R);
4333     auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
4334                                             MIRBuilder.buildConstant(S64, 0));
4335     MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
4336     return Legalized;
4337   }
4338 
4339   return UnableToLegalize;
4340 }
4341 
4342 LegalizerHelper::LegalizeResult
4343 LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4344   Register Dst = MI.getOperand(0).getReg();
4345   Register Src = MI.getOperand(1).getReg();
4346   LLT DstTy = MRI.getType(Dst);
4347   LLT SrcTy = MRI.getType(Src);
4348   const LLT S64 = LLT::scalar(64);
4349   const LLT S32 = LLT::scalar(32);
4350 
4351   if (SrcTy != S64 && SrcTy != S32)
4352     return UnableToLegalize;
4353   if (DstTy != S32 && DstTy != S64)
4354     return UnableToLegalize;
4355 
4356   // FPTOSI gives same result as FPTOUI for positive signed integers.
4357   // FPTOUI needs to deal with fp values that convert to unsigned integers
4358   // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp.
4359 
4360   APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits());
4361   APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle()
4362                                                 : APFloat::IEEEdouble(),
4363                     APInt::getNullValue(SrcTy.getSizeInBits()));
4364   TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven);
4365 
4366   MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src);
4367 
4368   MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP);
4369   // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on
4370   // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1.
4371   MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold);
4372   MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub);
4373   MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt);
4374   MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit);
4375 
4376   const LLT S1 = LLT::scalar(1);
4377 
4378   MachineInstrBuilder FCMP =
4379       MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold);
4380   MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res);
4381 
4382   MI.eraseFromParent();
4383   return Legalized;
4384 }
4385 
4386 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) {
4387   Register Dst = MI.getOperand(0).getReg();
4388   Register Src = MI.getOperand(1).getReg();
4389   LLT DstTy = MRI.getType(Dst);
4390   LLT SrcTy = MRI.getType(Src);
4391   const LLT S64 = LLT::scalar(64);
4392   const LLT S32 = LLT::scalar(32);
4393 
4394   // FIXME: Only f32 to i64 conversions are supported.
4395   if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64)
4396     return UnableToLegalize;
4397 
4398   // Expand f32 -> i64 conversion
4399   // This algorithm comes from compiler-rt's implementation of fixsfdi:
4400   // https://github.com/llvm/llvm-project/blob/master/compiler-rt/lib/builtins/fixsfdi.c
4401 
4402   unsigned SrcEltBits = SrcTy.getScalarSizeInBits();
4403 
4404   auto ExponentMask = MIRBuilder.buildConstant(SrcTy, 0x7F800000);
4405   auto ExponentLoBit = MIRBuilder.buildConstant(SrcTy, 23);
4406 
4407   auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask);
4408   auto ExponentBits = MIRBuilder.buildLShr(SrcTy, AndExpMask, ExponentLoBit);
4409 
4410   auto SignMask = MIRBuilder.buildConstant(SrcTy,
4411                                            APInt::getSignMask(SrcEltBits));
4412   auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask);
4413   auto SignLowBit = MIRBuilder.buildConstant(SrcTy, SrcEltBits - 1);
4414   auto Sign = MIRBuilder.buildAShr(SrcTy, AndSignMask, SignLowBit);
4415   Sign = MIRBuilder.buildSExt(DstTy, Sign);
4416 
4417   auto MantissaMask = MIRBuilder.buildConstant(SrcTy, 0x007FFFFF);
4418   auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask);
4419   auto K = MIRBuilder.buildConstant(SrcTy, 0x00800000);
4420 
4421   auto R = MIRBuilder.buildOr(SrcTy, AndMantissaMask, K);
4422   R = MIRBuilder.buildZExt(DstTy, R);
4423 
4424   auto Bias = MIRBuilder.buildConstant(SrcTy, 127);
4425   auto Exponent = MIRBuilder.buildSub(SrcTy, ExponentBits, Bias);
4426   auto SubExponent = MIRBuilder.buildSub(SrcTy, Exponent, ExponentLoBit);
4427   auto ExponentSub = MIRBuilder.buildSub(SrcTy, ExponentLoBit, Exponent);
4428 
4429   auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent);
4430   auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub);
4431 
4432   const LLT S1 = LLT::scalar(1);
4433   auto CmpGt = MIRBuilder.buildICmp(CmpInst::ICMP_SGT,
4434                                     S1, Exponent, ExponentLoBit);
4435 
4436   R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl);
4437 
4438   auto XorSign = MIRBuilder.buildXor(DstTy, R, Sign);
4439   auto Ret = MIRBuilder.buildSub(DstTy, XorSign, Sign);
4440 
4441   auto ZeroSrcTy = MIRBuilder.buildConstant(SrcTy, 0);
4442 
4443   auto ExponentLt0 = MIRBuilder.buildICmp(CmpInst::ICMP_SLT,
4444                                           S1, Exponent, ZeroSrcTy);
4445 
4446   auto ZeroDstTy = MIRBuilder.buildConstant(DstTy, 0);
4447   MIRBuilder.buildSelect(Dst, ExponentLt0, ZeroDstTy, Ret);
4448 
4449   MI.eraseFromParent();
4450   return Legalized;
4451 }
4452 
4453 // f64 -> f16 conversion using round-to-nearest-even rounding mode.
4454 LegalizerHelper::LegalizeResult
4455 LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) {
4456   Register Dst = MI.getOperand(0).getReg();
4457   Register Src = MI.getOperand(1).getReg();
4458 
4459   if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly.
4460     return UnableToLegalize;
4461 
4462   const unsigned ExpMask = 0x7ff;
4463   const unsigned ExpBiasf64 = 1023;
4464   const unsigned ExpBiasf16 = 15;
4465   const LLT S32 = LLT::scalar(32);
4466   const LLT S1 = LLT::scalar(1);
4467 
4468   auto Unmerge = MIRBuilder.buildUnmerge(S32, Src);
4469   Register U = Unmerge.getReg(0);
4470   Register UH = Unmerge.getReg(1);
4471 
4472   auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20));
4473 
4474   // Subtract the fp64 exponent bias (1023) to get the real exponent and
4475   // add the f16 bias (15) to get the biased exponent for the f16 format.
4476   E = MIRBuilder.buildAdd(
4477     S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16));
4478   E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask));
4479 
4480   auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8));
4481   M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe));
4482 
4483   auto MaskedSig = MIRBuilder.buildAnd(S32, UH,
4484                                        MIRBuilder.buildConstant(S32, 0x1ff));
4485   MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U);
4486 
4487   auto Zero = MIRBuilder.buildConstant(S32, 0);
4488   auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero);
4489   auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0);
4490   M = MIRBuilder.buildOr(S32, M, Lo40Set);
4491 
4492   // (M != 0 ? 0x0200 : 0) | 0x7c00;
4493   auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200);
4494   auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero);
4495   auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero);
4496 
4497   auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00);
4498   auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00);
4499 
4500   // N = M | (E << 12);
4501   auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12));
4502   auto N = MIRBuilder.buildOr(S32, M, EShl12);
4503 
4504   // B = clamp(1-E, 0, 13);
4505   auto One = MIRBuilder.buildConstant(S32, 1);
4506   auto OneSubExp = MIRBuilder.buildSub(S32, One, E);
4507   auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero);
4508   B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13));
4509 
4510   auto SigSetHigh = MIRBuilder.buildOr(S32, M,
4511                                        MIRBuilder.buildConstant(S32, 0x1000));
4512 
4513   auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B);
4514   auto D0 = MIRBuilder.buildShl(S32, D, B);
4515 
4516   auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1,
4517                                              D0, SigSetHigh);
4518   auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh);
4519   D = MIRBuilder.buildOr(S32, D, D1);
4520 
4521   auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One);
4522   auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N);
4523 
4524   auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7));
4525   V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2));
4526 
4527   auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3,
4528                                        MIRBuilder.buildConstant(S32, 3));
4529   auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3);
4530 
4531   auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3,
4532                                        MIRBuilder.buildConstant(S32, 5));
4533   auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5);
4534 
4535   V1 = MIRBuilder.buildOr(S32, V0, V1);
4536   V = MIRBuilder.buildAdd(S32, V, V1);
4537 
4538   auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT,  S1,
4539                                        E, MIRBuilder.buildConstant(S32, 30));
4540   V = MIRBuilder.buildSelect(S32, CmpEGt30,
4541                              MIRBuilder.buildConstant(S32, 0x7c00), V);
4542 
4543   auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1,
4544                                          E, MIRBuilder.buildConstant(S32, 1039));
4545   V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V);
4546 
4547   // Extract the sign bit.
4548   auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16));
4549   Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000));
4550 
4551   // Insert the sign bit
4552   V = MIRBuilder.buildOr(S32, Sign, V);
4553 
4554   MIRBuilder.buildTrunc(Dst, V);
4555   MI.eraseFromParent();
4556   return Legalized;
4557 }
4558 
4559 LegalizerHelper::LegalizeResult
4560 LegalizerHelper::lowerFPTRUNC(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4561   Register Dst = MI.getOperand(0).getReg();
4562   Register Src = MI.getOperand(1).getReg();
4563 
4564   LLT DstTy = MRI.getType(Dst);
4565   LLT SrcTy = MRI.getType(Src);
4566   const LLT S64 = LLT::scalar(64);
4567   const LLT S16 = LLT::scalar(16);
4568 
4569   if (DstTy.getScalarType() == S16 && SrcTy.getScalarType() == S64)
4570     return lowerFPTRUNC_F64_TO_F16(MI);
4571 
4572   return UnableToLegalize;
4573 }
4574 
4575 static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
4576   switch (Opc) {
4577   case TargetOpcode::G_SMIN:
4578     return CmpInst::ICMP_SLT;
4579   case TargetOpcode::G_SMAX:
4580     return CmpInst::ICMP_SGT;
4581   case TargetOpcode::G_UMIN:
4582     return CmpInst::ICMP_ULT;
4583   case TargetOpcode::G_UMAX:
4584     return CmpInst::ICMP_UGT;
4585   default:
4586     llvm_unreachable("not in integer min/max");
4587   }
4588 }
4589 
4590 LegalizerHelper::LegalizeResult
4591 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4592   Register Dst = MI.getOperand(0).getReg();
4593   Register Src0 = MI.getOperand(1).getReg();
4594   Register Src1 = MI.getOperand(2).getReg();
4595 
4596   const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
4597   LLT CmpType = MRI.getType(Dst).changeElementSize(1);
4598 
4599   auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
4600   MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
4601 
4602   MI.eraseFromParent();
4603   return Legalized;
4604 }
4605 
4606 LegalizerHelper::LegalizeResult
4607 LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4608   Register Dst = MI.getOperand(0).getReg();
4609   Register Src0 = MI.getOperand(1).getReg();
4610   Register Src1 = MI.getOperand(2).getReg();
4611 
4612   const LLT Src0Ty = MRI.getType(Src0);
4613   const LLT Src1Ty = MRI.getType(Src1);
4614 
4615   const int Src0Size = Src0Ty.getScalarSizeInBits();
4616   const int Src1Size = Src1Ty.getScalarSizeInBits();
4617 
4618   auto SignBitMask = MIRBuilder.buildConstant(
4619     Src0Ty, APInt::getSignMask(Src0Size));
4620 
4621   auto NotSignBitMask = MIRBuilder.buildConstant(
4622     Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
4623 
4624   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
4625   MachineInstr *Or;
4626 
4627   if (Src0Ty == Src1Ty) {
4628     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
4629     Or = MIRBuilder.buildOr(Dst, And0, And1);
4630   } else if (Src0Size > Src1Size) {
4631     auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
4632     auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
4633     auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
4634     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
4635     Or = MIRBuilder.buildOr(Dst, And0, And1);
4636   } else {
4637     auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
4638     auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
4639     auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
4640     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
4641     Or = MIRBuilder.buildOr(Dst, And0, And1);
4642   }
4643 
4644   // Be careful about setting nsz/nnan/ninf on every instruction, since the
4645   // constants are a nan and -0.0, but the final result should preserve
4646   // everything.
4647   if (unsigned Flags = MI.getFlags())
4648     Or->setFlags(Flags);
4649 
4650   MI.eraseFromParent();
4651   return Legalized;
4652 }
4653 
4654 LegalizerHelper::LegalizeResult
4655 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
4656   unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ?
4657     TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE;
4658 
4659   Register Dst = MI.getOperand(0).getReg();
4660   Register Src0 = MI.getOperand(1).getReg();
4661   Register Src1 = MI.getOperand(2).getReg();
4662   LLT Ty = MRI.getType(Dst);
4663 
4664   if (!MI.getFlag(MachineInstr::FmNoNans)) {
4665     // Insert canonicalizes if it's possible we need to quiet to get correct
4666     // sNaN behavior.
4667 
4668     // Note this must be done here, and not as an optimization combine in the
4669     // absence of a dedicate quiet-snan instruction as we're using an
4670     // omni-purpose G_FCANONICALIZE.
4671     if (!isKnownNeverSNaN(Src0, MRI))
4672       Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0);
4673 
4674     if (!isKnownNeverSNaN(Src1, MRI))
4675       Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0);
4676   }
4677 
4678   // If there are no nans, it's safe to simply replace this with the non-IEEE
4679   // version.
4680   MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags());
4681   MI.eraseFromParent();
4682   return Legalized;
4683 }
4684 
4685 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) {
4686   // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c
4687   Register DstReg = MI.getOperand(0).getReg();
4688   LLT Ty = MRI.getType(DstReg);
4689   unsigned Flags = MI.getFlags();
4690 
4691   auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2),
4692                                   Flags);
4693   MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags);
4694   MI.eraseFromParent();
4695   return Legalized;
4696 }
4697 
4698 LegalizerHelper::LegalizeResult
4699 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) {
4700   Register DstReg = MI.getOperand(0).getReg();
4701   Register SrcReg = MI.getOperand(1).getReg();
4702   unsigned Flags = MI.getFlags();
4703   LLT Ty = MRI.getType(DstReg);
4704   const LLT CondTy = Ty.changeElementSize(1);
4705 
4706   // result = trunc(src);
4707   // if (src < 0.0 && src != result)
4708   //   result += -1.0.
4709 
4710   auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
4711   auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags);
4712 
4713   auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy,
4714                                   SrcReg, Zero, Flags);
4715   auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy,
4716                                       SrcReg, Trunc, Flags);
4717   auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc);
4718   auto AddVal = MIRBuilder.buildSITOFP(Ty, And);
4719 
4720   MIRBuilder.buildFAdd(DstReg, Trunc, AddVal);
4721   MI.eraseFromParent();
4722   return Legalized;
4723 }
4724 
4725 LegalizerHelper::LegalizeResult
4726 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
4727   const unsigned NumDst = MI.getNumOperands() - 1;
4728   const Register SrcReg = MI.getOperand(NumDst).getReg();
4729   LLT SrcTy = MRI.getType(SrcReg);
4730 
4731   Register Dst0Reg = MI.getOperand(0).getReg();
4732   LLT DstTy = MRI.getType(Dst0Reg);
4733 
4734 
4735   // Expand scalarizing unmerge as bitcast to integer and shift.
4736   if (!DstTy.isVector() && SrcTy.isVector() &&
4737       SrcTy.getElementType() == DstTy) {
4738     LLT IntTy = LLT::scalar(SrcTy.getSizeInBits());
4739     Register Cast = MIRBuilder.buildBitcast(IntTy, SrcReg).getReg(0);
4740 
4741     MIRBuilder.buildTrunc(Dst0Reg, Cast);
4742 
4743     const unsigned DstSize = DstTy.getSizeInBits();
4744     unsigned Offset = DstSize;
4745     for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
4746       auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
4747       auto Shift = MIRBuilder.buildLShr(IntTy, Cast, ShiftAmt);
4748       MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
4749     }
4750 
4751     MI.eraseFromParent();
4752     return Legalized;
4753   }
4754 
4755   return UnableToLegalize;
4756 }
4757 
4758 LegalizerHelper::LegalizeResult
4759 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
4760   Register DstReg = MI.getOperand(0).getReg();
4761   Register Src0Reg = MI.getOperand(1).getReg();
4762   Register Src1Reg = MI.getOperand(2).getReg();
4763   LLT Src0Ty = MRI.getType(Src0Reg);
4764   LLT DstTy = MRI.getType(DstReg);
4765   LLT IdxTy = LLT::scalar(32);
4766 
4767   ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
4768 
4769   if (DstTy.isScalar()) {
4770     if (Src0Ty.isVector())
4771       return UnableToLegalize;
4772 
4773     // This is just a SELECT.
4774     assert(Mask.size() == 1 && "Expected a single mask element");
4775     Register Val;
4776     if (Mask[0] < 0 || Mask[0] > 1)
4777       Val = MIRBuilder.buildUndef(DstTy).getReg(0);
4778     else
4779       Val = Mask[0] == 0 ? Src0Reg : Src1Reg;
4780     MIRBuilder.buildCopy(DstReg, Val);
4781     MI.eraseFromParent();
4782     return Legalized;
4783   }
4784 
4785   Register Undef;
4786   SmallVector<Register, 32> BuildVec;
4787   LLT EltTy = DstTy.getElementType();
4788 
4789   for (int Idx : Mask) {
4790     if (Idx < 0) {
4791       if (!Undef.isValid())
4792         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);
4793       BuildVec.push_back(Undef);
4794       continue;
4795     }
4796 
4797     if (Src0Ty.isScalar()) {
4798       BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
4799     } else {
4800       int NumElts = Src0Ty.getNumElements();
4801       Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
4802       int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
4803       auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
4804       auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
4805       BuildVec.push_back(Extract.getReg(0));
4806     }
4807   }
4808 
4809   MIRBuilder.buildBuildVector(DstReg, BuildVec);
4810   MI.eraseFromParent();
4811   return Legalized;
4812 }
4813 
4814 LegalizerHelper::LegalizeResult
4815 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) {
4816   Register Dst = MI.getOperand(0).getReg();
4817   Register AllocSize = MI.getOperand(1).getReg();
4818   unsigned Align = MI.getOperand(2).getImm();
4819 
4820   const auto &MF = *MI.getMF();
4821   const auto &TLI = *MF.getSubtarget().getTargetLowering();
4822 
4823   LLT PtrTy = MRI.getType(Dst);
4824   LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
4825 
4826   Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
4827   auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg);
4828   SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp);
4829 
4830   // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't
4831   // have to generate an extra instruction to negate the alloc and then use
4832   // G_PTR_ADD to add the negative offset.
4833   auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize);
4834   if (Align) {
4835     APInt AlignMask(IntPtrTy.getSizeInBits(), Align, true);
4836     AlignMask.negate();
4837     auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask);
4838     Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst);
4839   }
4840 
4841   SPTmp = MIRBuilder.buildCast(PtrTy, Alloc);
4842   MIRBuilder.buildCopy(SPReg, SPTmp);
4843   MIRBuilder.buildCopy(Dst, SPTmp);
4844 
4845   MI.eraseFromParent();
4846   return Legalized;
4847 }
4848 
4849 LegalizerHelper::LegalizeResult
4850 LegalizerHelper::lowerExtract(MachineInstr &MI) {
4851   Register Dst = MI.getOperand(0).getReg();
4852   Register Src = MI.getOperand(1).getReg();
4853   unsigned Offset = MI.getOperand(2).getImm();
4854 
4855   LLT DstTy = MRI.getType(Dst);
4856   LLT SrcTy = MRI.getType(Src);
4857 
4858   if (DstTy.isScalar() &&
4859       (SrcTy.isScalar() ||
4860        (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
4861     LLT SrcIntTy = SrcTy;
4862     if (!SrcTy.isScalar()) {
4863       SrcIntTy = LLT::scalar(SrcTy.getSizeInBits());
4864       Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0);
4865     }
4866 
4867     if (Offset == 0)
4868       MIRBuilder.buildTrunc(Dst, Src);
4869     else {
4870       auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset);
4871       auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt);
4872       MIRBuilder.buildTrunc(Dst, Shr);
4873     }
4874 
4875     MI.eraseFromParent();
4876     return Legalized;
4877   }
4878 
4879   return UnableToLegalize;
4880 }
4881 
4882 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
4883   Register Dst = MI.getOperand(0).getReg();
4884   Register Src = MI.getOperand(1).getReg();
4885   Register InsertSrc = MI.getOperand(2).getReg();
4886   uint64_t Offset = MI.getOperand(3).getImm();
4887 
4888   LLT DstTy = MRI.getType(Src);
4889   LLT InsertTy = MRI.getType(InsertSrc);
4890 
4891   if (InsertTy.isScalar() &&
4892       (DstTy.isScalar() ||
4893        (DstTy.isVector() && DstTy.getElementType() == InsertTy))) {
4894     LLT IntDstTy = DstTy;
4895     if (!DstTy.isScalar()) {
4896       IntDstTy = LLT::scalar(DstTy.getSizeInBits());
4897       Src = MIRBuilder.buildBitcast(IntDstTy, Src).getReg(0);
4898     }
4899 
4900     Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0);
4901     if (Offset != 0) {
4902       auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset);
4903       ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0);
4904     }
4905 
4906     APInt MaskVal = APInt::getBitsSetWithWrap(DstTy.getSizeInBits(),
4907                                               Offset + InsertTy.getSizeInBits(),
4908                                               Offset);
4909 
4910     auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal);
4911     auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);
4912     auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc);
4913 
4914     MIRBuilder.buildBitcast(Dst, Or);
4915     MI.eraseFromParent();
4916     return Legalized;
4917   }
4918 
4919   return UnableToLegalize;
4920 }
4921 
4922 LegalizerHelper::LegalizeResult
4923 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {
4924   Register Dst0 = MI.getOperand(0).getReg();
4925   Register Dst1 = MI.getOperand(1).getReg();
4926   Register LHS = MI.getOperand(2).getReg();
4927   Register RHS = MI.getOperand(3).getReg();
4928   const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO;
4929 
4930   LLT Ty = MRI.getType(Dst0);
4931   LLT BoolTy = MRI.getType(Dst1);
4932 
4933   if (IsAdd)
4934     MIRBuilder.buildAdd(Dst0, LHS, RHS);
4935   else
4936     MIRBuilder.buildSub(Dst0, LHS, RHS);
4937 
4938   // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
4939 
4940   auto Zero = MIRBuilder.buildConstant(Ty, 0);
4941 
4942   // For an addition, the result should be less than one of the operands (LHS)
4943   // if and only if the other operand (RHS) is negative, otherwise there will
4944   // be overflow.
4945   // For a subtraction, the result should be less than one of the operands
4946   // (LHS) if and only if the other operand (RHS) is (non-zero) positive,
4947   // otherwise there will be overflow.
4948   auto ResultLowerThanLHS =
4949       MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS);
4950   auto ConditionRHS = MIRBuilder.buildICmp(
4951       IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero);
4952 
4953   MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS);
4954   MI.eraseFromParent();
4955   return Legalized;
4956 }
4957 
4958 LegalizerHelper::LegalizeResult
4959 LegalizerHelper::lowerBswap(MachineInstr &MI) {
4960   Register Dst = MI.getOperand(0).getReg();
4961   Register Src = MI.getOperand(1).getReg();
4962   const LLT Ty = MRI.getType(Src);
4963   unsigned SizeInBytes = Ty.getSizeInBytes();
4964   unsigned BaseShiftAmt = (SizeInBytes - 1) * 8;
4965 
4966   // Swap most and least significant byte, set remaining bytes in Res to zero.
4967   auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt);
4968   auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt);
4969   auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
4970   auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft);
4971 
4972   // Set i-th high/low byte in Res to i-th low/high byte from Src.
4973   for (unsigned i = 1; i < SizeInBytes / 2; ++i) {
4974     // AND with Mask leaves byte i unchanged and sets remaining bytes to 0.
4975     APInt APMask(SizeInBytes * 8, 0xFF << (i * 8));
4976     auto Mask = MIRBuilder.buildConstant(Ty, APMask);
4977     auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i);
4978     // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt.
4979     auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask);
4980     auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt);
4981     Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft);
4982     // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask.
4983     auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
4984     auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask);
4985     Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight);
4986   }
4987   Res.getInstr()->getOperand(0).setReg(Dst);
4988 
4989   MI.eraseFromParent();
4990   return Legalized;
4991 }
4992 
4993 //{ (Src & Mask) >> N } | { (Src << N) & Mask }
4994 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B,
4995                                  MachineInstrBuilder Src, APInt Mask) {
4996   const LLT Ty = Dst.getLLTTy(*B.getMRI());
4997   MachineInstrBuilder C_N = B.buildConstant(Ty, N);
4998   MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask);
4999   auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N);
5000   auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0);
5001   return B.buildOr(Dst, LHS, RHS);
5002 }
5003 
5004 LegalizerHelper::LegalizeResult
5005 LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
5006   Register Dst = MI.getOperand(0).getReg();
5007   Register Src = MI.getOperand(1).getReg();
5008   const LLT Ty = MRI.getType(Src);
5009   unsigned Size = Ty.getSizeInBits();
5010 
5011   MachineInstrBuilder BSWAP =
5012       MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src});
5013 
5014   // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654
5015   //    [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4]
5016   // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0]
5017   MachineInstrBuilder Swap4 =
5018       SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0)));
5019 
5020   // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76
5021   //    [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2]
5022   // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC]
5023   MachineInstrBuilder Swap2 =
5024       SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC)));
5025 
5026   // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7
5027   //    [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1]
5028   // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA]
5029   SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA)));
5030 
5031   MI.eraseFromParent();
5032   return Legalized;
5033 }
5034 
5035 LegalizerHelper::LegalizeResult
5036 LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) {
5037   MachineFunction &MF = MIRBuilder.getMF();
5038   const TargetSubtargetInfo &STI = MF.getSubtarget();
5039   const TargetLowering *TLI = STI.getTargetLowering();
5040 
5041   bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER;
5042   int NameOpIdx = IsRead ? 1 : 0;
5043   int ValRegIndex = IsRead ? 0 : 1;
5044 
5045   Register ValReg = MI.getOperand(ValRegIndex).getReg();
5046   const LLT Ty = MRI.getType(ValReg);
5047   const MDString *RegStr = cast<MDString>(
5048     cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0));
5049 
5050   Register PhysReg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
5051   if (!PhysReg.isValid())
5052     return UnableToLegalize;
5053 
5054   if (IsRead)
5055     MIRBuilder.buildCopy(ValReg, PhysReg);
5056   else
5057     MIRBuilder.buildCopy(PhysReg, ValReg);
5058 
5059   MI.eraseFromParent();
5060   return Legalized;
5061 }
5062