1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file This file implements the LegalizerHelper class to legalize 10 /// individual instructions and the LegalizeMachineIR wrapper pass for the 11 /// primary legalization. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 16 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 19 #include "llvm/CodeGen/GlobalISel/LostDebugLocObserver.h" 20 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" 21 #include "llvm/CodeGen/GlobalISel/Utils.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/TargetFrameLowering.h" 24 #include "llvm/CodeGen/TargetInstrInfo.h" 25 #include "llvm/CodeGen/TargetLowering.h" 26 #include "llvm/CodeGen/TargetOpcodes.h" 27 #include "llvm/CodeGen/TargetSubtargetInfo.h" 28 #include "llvm/IR/Instructions.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/MathExtras.h" 31 #include "llvm/Support/raw_ostream.h" 32 33 #define DEBUG_TYPE "legalizer" 34 35 using namespace llvm; 36 using namespace LegalizeActions; 37 using namespace MIPatternMatch; 38 39 /// Try to break down \p OrigTy into \p NarrowTy sized pieces. 40 /// 41 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy, 42 /// with any leftover piece as type \p LeftoverTy 43 /// 44 /// Returns -1 in the first element of the pair if the breakdown is not 45 /// satisfiable. 46 static std::pair<int, int> 47 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) { 48 assert(!LeftoverTy.isValid() && "this is an out argument"); 49 50 unsigned Size = OrigTy.getSizeInBits(); 51 unsigned NarrowSize = NarrowTy.getSizeInBits(); 52 unsigned NumParts = Size / NarrowSize; 53 unsigned LeftoverSize = Size - NumParts * NarrowSize; 54 assert(Size > NarrowSize); 55 56 if (LeftoverSize == 0) 57 return {NumParts, 0}; 58 59 if (NarrowTy.isVector()) { 60 unsigned EltSize = OrigTy.getScalarSizeInBits(); 61 if (LeftoverSize % EltSize != 0) 62 return {-1, -1}; 63 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); 64 } else { 65 LeftoverTy = LLT::scalar(LeftoverSize); 66 } 67 68 int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits(); 69 return std::make_pair(NumParts, NumLeftover); 70 } 71 72 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) { 73 74 if (!Ty.isScalar()) 75 return nullptr; 76 77 switch (Ty.getSizeInBits()) { 78 case 16: 79 return Type::getHalfTy(Ctx); 80 case 32: 81 return Type::getFloatTy(Ctx); 82 case 64: 83 return Type::getDoubleTy(Ctx); 84 case 80: 85 return Type::getX86_FP80Ty(Ctx); 86 case 128: 87 return Type::getFP128Ty(Ctx); 88 default: 89 return nullptr; 90 } 91 } 92 93 LegalizerHelper::LegalizerHelper(MachineFunction &MF, 94 GISelChangeObserver &Observer, 95 MachineIRBuilder &Builder) 96 : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()), 97 LI(*MF.getSubtarget().getLegalizerInfo()), 98 TLI(*MF.getSubtarget().getTargetLowering()) { } 99 100 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI, 101 GISelChangeObserver &Observer, 102 MachineIRBuilder &B) 103 : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI), 104 TLI(*MF.getSubtarget().getTargetLowering()) { } 105 106 LegalizerHelper::LegalizeResult 107 LegalizerHelper::legalizeInstrStep(MachineInstr &MI, 108 LostDebugLocObserver &LocObserver) { 109 LLVM_DEBUG(dbgs() << "Legalizing: " << MI); 110 111 MIRBuilder.setInstrAndDebugLoc(MI); 112 113 if (MI.getOpcode() == TargetOpcode::G_INTRINSIC || 114 MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS) 115 return LI.legalizeIntrinsic(*this, MI) ? Legalized : UnableToLegalize; 116 auto Step = LI.getAction(MI, MRI); 117 switch (Step.Action) { 118 case Legal: 119 LLVM_DEBUG(dbgs() << ".. Already legal\n"); 120 return AlreadyLegal; 121 case Libcall: 122 LLVM_DEBUG(dbgs() << ".. Convert to libcall\n"); 123 return libcall(MI, LocObserver); 124 case NarrowScalar: 125 LLVM_DEBUG(dbgs() << ".. Narrow scalar\n"); 126 return narrowScalar(MI, Step.TypeIdx, Step.NewType); 127 case WidenScalar: 128 LLVM_DEBUG(dbgs() << ".. Widen scalar\n"); 129 return widenScalar(MI, Step.TypeIdx, Step.NewType); 130 case Bitcast: 131 LLVM_DEBUG(dbgs() << ".. Bitcast type\n"); 132 return bitcast(MI, Step.TypeIdx, Step.NewType); 133 case Lower: 134 LLVM_DEBUG(dbgs() << ".. Lower\n"); 135 return lower(MI, Step.TypeIdx, Step.NewType); 136 case FewerElements: 137 LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n"); 138 return fewerElementsVector(MI, Step.TypeIdx, Step.NewType); 139 case MoreElements: 140 LLVM_DEBUG(dbgs() << ".. Increase number of elements\n"); 141 return moreElementsVector(MI, Step.TypeIdx, Step.NewType); 142 case Custom: 143 LLVM_DEBUG(dbgs() << ".. Custom legalization\n"); 144 return LI.legalizeCustom(*this, MI) ? Legalized : UnableToLegalize; 145 default: 146 LLVM_DEBUG(dbgs() << ".. Unable to legalize\n"); 147 return UnableToLegalize; 148 } 149 } 150 151 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts, 152 SmallVectorImpl<Register> &VRegs) { 153 for (int i = 0; i < NumParts; ++i) 154 VRegs.push_back(MRI.createGenericVirtualRegister(Ty)); 155 MIRBuilder.buildUnmerge(VRegs, Reg); 156 } 157 158 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, 159 LLT MainTy, LLT &LeftoverTy, 160 SmallVectorImpl<Register> &VRegs, 161 SmallVectorImpl<Register> &LeftoverRegs) { 162 assert(!LeftoverTy.isValid() && "this is an out argument"); 163 164 unsigned RegSize = RegTy.getSizeInBits(); 165 unsigned MainSize = MainTy.getSizeInBits(); 166 unsigned NumParts = RegSize / MainSize; 167 unsigned LeftoverSize = RegSize - NumParts * MainSize; 168 169 // Use an unmerge when possible. 170 if (LeftoverSize == 0) { 171 for (unsigned I = 0; I < NumParts; ++I) 172 VRegs.push_back(MRI.createGenericVirtualRegister(MainTy)); 173 MIRBuilder.buildUnmerge(VRegs, Reg); 174 return true; 175 } 176 177 if (MainTy.isVector()) { 178 unsigned EltSize = MainTy.getScalarSizeInBits(); 179 if (LeftoverSize % EltSize != 0) 180 return false; 181 LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize); 182 } else { 183 LeftoverTy = LLT::scalar(LeftoverSize); 184 } 185 186 // For irregular sizes, extract the individual parts. 187 for (unsigned I = 0; I != NumParts; ++I) { 188 Register NewReg = MRI.createGenericVirtualRegister(MainTy); 189 VRegs.push_back(NewReg); 190 MIRBuilder.buildExtract(NewReg, Reg, MainSize * I); 191 } 192 193 for (unsigned Offset = MainSize * NumParts; Offset < RegSize; 194 Offset += LeftoverSize) { 195 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy); 196 LeftoverRegs.push_back(NewReg); 197 MIRBuilder.buildExtract(NewReg, Reg, Offset); 198 } 199 200 return true; 201 } 202 203 void LegalizerHelper::insertParts(Register DstReg, 204 LLT ResultTy, LLT PartTy, 205 ArrayRef<Register> PartRegs, 206 LLT LeftoverTy, 207 ArrayRef<Register> LeftoverRegs) { 208 if (!LeftoverTy.isValid()) { 209 assert(LeftoverRegs.empty()); 210 211 if (!ResultTy.isVector()) { 212 MIRBuilder.buildMerge(DstReg, PartRegs); 213 return; 214 } 215 216 if (PartTy.isVector()) 217 MIRBuilder.buildConcatVectors(DstReg, PartRegs); 218 else 219 MIRBuilder.buildBuildVector(DstReg, PartRegs); 220 return; 221 } 222 223 SmallVector<Register> GCDRegs; 224 LLT GCDTy; 225 for (Register PartReg : PartRegs) 226 GCDTy = extractGCDType(GCDRegs, ResultTy, LeftoverTy, PartReg); 227 228 for (Register PartReg : LeftoverRegs) 229 extractGCDType(GCDRegs, ResultTy, LeftoverTy, PartReg); 230 231 LLT ResultLCMTy = buildLCMMergePieces(ResultTy, LeftoverTy, GCDTy, GCDRegs); 232 buildWidenedRemergeToDst(DstReg, ResultLCMTy, GCDRegs); 233 } 234 235 /// Append the result registers of G_UNMERGE_VALUES \p MI to \p Regs. 236 static void getUnmergeResults(SmallVectorImpl<Register> &Regs, 237 const MachineInstr &MI) { 238 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES); 239 240 const int StartIdx = Regs.size(); 241 const int NumResults = MI.getNumOperands() - 1; 242 Regs.resize(Regs.size() + NumResults); 243 for (int I = 0; I != NumResults; ++I) 244 Regs[StartIdx + I] = MI.getOperand(I).getReg(); 245 } 246 247 void LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, 248 LLT GCDTy, Register SrcReg) { 249 LLT SrcTy = MRI.getType(SrcReg); 250 if (SrcTy == GCDTy) { 251 // If the source already evenly divides the result type, we don't need to do 252 // anything. 253 Parts.push_back(SrcReg); 254 } else { 255 // Need to split into common type sized pieces. 256 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 257 getUnmergeResults(Parts, *Unmerge); 258 } 259 } 260 261 LLT LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy, 262 LLT NarrowTy, Register SrcReg) { 263 LLT SrcTy = MRI.getType(SrcReg); 264 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 265 extractGCDType(Parts, GCDTy, SrcReg); 266 return GCDTy; 267 } 268 269 LLT LegalizerHelper::buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy, 270 SmallVectorImpl<Register> &VRegs, 271 unsigned PadStrategy) { 272 LLT LCMTy = getLCMType(DstTy, NarrowTy); 273 274 int NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 275 int NumSubParts = NarrowTy.getSizeInBits() / GCDTy.getSizeInBits(); 276 int NumOrigSrc = VRegs.size(); 277 278 Register PadReg; 279 280 // Get a value we can use to pad the source value if the sources won't evenly 281 // cover the result type. 282 if (NumOrigSrc < NumParts * NumSubParts) { 283 if (PadStrategy == TargetOpcode::G_ZEXT) 284 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); 285 else if (PadStrategy == TargetOpcode::G_ANYEXT) 286 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 287 else { 288 assert(PadStrategy == TargetOpcode::G_SEXT); 289 290 // Shift the sign bit of the low register through the high register. 291 auto ShiftAmt = 292 MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1); 293 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0); 294 } 295 } 296 297 // Registers for the final merge to be produced. 298 SmallVector<Register, 4> Remerge(NumParts); 299 300 // Registers needed for intermediate merges, which will be merged into a 301 // source for Remerge. 302 SmallVector<Register, 4> SubMerge(NumSubParts); 303 304 // Once we've fully read off the end of the original source bits, we can reuse 305 // the same high bits for remaining padding elements. 306 Register AllPadReg; 307 308 // Build merges to the LCM type to cover the original result type. 309 for (int I = 0; I != NumParts; ++I) { 310 bool AllMergePartsArePadding = true; 311 312 // Build the requested merges to the requested type. 313 for (int J = 0; J != NumSubParts; ++J) { 314 int Idx = I * NumSubParts + J; 315 if (Idx >= NumOrigSrc) { 316 SubMerge[J] = PadReg; 317 continue; 318 } 319 320 SubMerge[J] = VRegs[Idx]; 321 322 // There are meaningful bits here we can't reuse later. 323 AllMergePartsArePadding = false; 324 } 325 326 // If we've filled up a complete piece with padding bits, we can directly 327 // emit the natural sized constant if applicable, rather than a merge of 328 // smaller constants. 329 if (AllMergePartsArePadding && !AllPadReg) { 330 if (PadStrategy == TargetOpcode::G_ANYEXT) 331 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); 332 else if (PadStrategy == TargetOpcode::G_ZEXT) 333 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); 334 335 // If this is a sign extension, we can't materialize a trivial constant 336 // with the right type and have to produce a merge. 337 } 338 339 if (AllPadReg) { 340 // Avoid creating additional instructions if we're just adding additional 341 // copies of padding bits. 342 Remerge[I] = AllPadReg; 343 continue; 344 } 345 346 if (NumSubParts == 1) 347 Remerge[I] = SubMerge[0]; 348 else 349 Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0); 350 351 // In the sign extend padding case, re-use the first all-signbit merge. 352 if (AllMergePartsArePadding && !AllPadReg) 353 AllPadReg = Remerge[I]; 354 } 355 356 VRegs = std::move(Remerge); 357 return LCMTy; 358 } 359 360 void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy, 361 ArrayRef<Register> RemergeRegs) { 362 LLT DstTy = MRI.getType(DstReg); 363 364 // Create the merge to the widened source, and extract the relevant bits into 365 // the result. 366 367 if (DstTy == LCMTy) { 368 MIRBuilder.buildMerge(DstReg, RemergeRegs); 369 return; 370 } 371 372 auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs); 373 if (DstTy.isScalar() && LCMTy.isScalar()) { 374 MIRBuilder.buildTrunc(DstReg, Remerge); 375 return; 376 } 377 378 if (LCMTy.isVector()) { 379 unsigned NumDefs = LCMTy.getSizeInBits() / DstTy.getSizeInBits(); 380 SmallVector<Register, 8> UnmergeDefs(NumDefs); 381 UnmergeDefs[0] = DstReg; 382 for (unsigned I = 1; I != NumDefs; ++I) 383 UnmergeDefs[I] = MRI.createGenericVirtualRegister(DstTy); 384 385 MIRBuilder.buildUnmerge(UnmergeDefs, 386 MIRBuilder.buildMerge(LCMTy, RemergeRegs)); 387 return; 388 } 389 390 llvm_unreachable("unhandled case"); 391 } 392 393 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) { 394 #define RTLIBCASE_INT(LibcallPrefix) \ 395 do { \ 396 switch (Size) { \ 397 case 32: \ 398 return RTLIB::LibcallPrefix##32; \ 399 case 64: \ 400 return RTLIB::LibcallPrefix##64; \ 401 case 128: \ 402 return RTLIB::LibcallPrefix##128; \ 403 default: \ 404 llvm_unreachable("unexpected size"); \ 405 } \ 406 } while (0) 407 408 #define RTLIBCASE(LibcallPrefix) \ 409 do { \ 410 switch (Size) { \ 411 case 32: \ 412 return RTLIB::LibcallPrefix##32; \ 413 case 64: \ 414 return RTLIB::LibcallPrefix##64; \ 415 case 80: \ 416 return RTLIB::LibcallPrefix##80; \ 417 case 128: \ 418 return RTLIB::LibcallPrefix##128; \ 419 default: \ 420 llvm_unreachable("unexpected size"); \ 421 } \ 422 } while (0) 423 424 switch (Opcode) { 425 case TargetOpcode::G_SDIV: 426 RTLIBCASE_INT(SDIV_I); 427 case TargetOpcode::G_UDIV: 428 RTLIBCASE_INT(UDIV_I); 429 case TargetOpcode::G_SREM: 430 RTLIBCASE_INT(SREM_I); 431 case TargetOpcode::G_UREM: 432 RTLIBCASE_INT(UREM_I); 433 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 434 RTLIBCASE_INT(CTLZ_I); 435 case TargetOpcode::G_FADD: 436 RTLIBCASE(ADD_F); 437 case TargetOpcode::G_FSUB: 438 RTLIBCASE(SUB_F); 439 case TargetOpcode::G_FMUL: 440 RTLIBCASE(MUL_F); 441 case TargetOpcode::G_FDIV: 442 RTLIBCASE(DIV_F); 443 case TargetOpcode::G_FEXP: 444 RTLIBCASE(EXP_F); 445 case TargetOpcode::G_FEXP2: 446 RTLIBCASE(EXP2_F); 447 case TargetOpcode::G_FREM: 448 RTLIBCASE(REM_F); 449 case TargetOpcode::G_FPOW: 450 RTLIBCASE(POW_F); 451 case TargetOpcode::G_FMA: 452 RTLIBCASE(FMA_F); 453 case TargetOpcode::G_FSIN: 454 RTLIBCASE(SIN_F); 455 case TargetOpcode::G_FCOS: 456 RTLIBCASE(COS_F); 457 case TargetOpcode::G_FLOG10: 458 RTLIBCASE(LOG10_F); 459 case TargetOpcode::G_FLOG: 460 RTLIBCASE(LOG_F); 461 case TargetOpcode::G_FLOG2: 462 RTLIBCASE(LOG2_F); 463 case TargetOpcode::G_FCEIL: 464 RTLIBCASE(CEIL_F); 465 case TargetOpcode::G_FFLOOR: 466 RTLIBCASE(FLOOR_F); 467 case TargetOpcode::G_FMINNUM: 468 RTLIBCASE(FMIN_F); 469 case TargetOpcode::G_FMAXNUM: 470 RTLIBCASE(FMAX_F); 471 case TargetOpcode::G_FSQRT: 472 RTLIBCASE(SQRT_F); 473 case TargetOpcode::G_FRINT: 474 RTLIBCASE(RINT_F); 475 case TargetOpcode::G_FNEARBYINT: 476 RTLIBCASE(NEARBYINT_F); 477 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 478 RTLIBCASE(ROUNDEVEN_F); 479 } 480 llvm_unreachable("Unknown libcall function"); 481 } 482 483 /// True if an instruction is in tail position in its caller. Intended for 484 /// legalizing libcalls as tail calls when possible. 485 static bool isLibCallInTailPosition(const TargetInstrInfo &TII, 486 MachineInstr &MI) { 487 MachineBasicBlock &MBB = *MI.getParent(); 488 const Function &F = MBB.getParent()->getFunction(); 489 490 // Conservatively require the attributes of the call to match those of 491 // the return. Ignore NoAlias and NonNull because they don't affect the 492 // call sequence. 493 AttributeList CallerAttrs = F.getAttributes(); 494 if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex) 495 .removeAttribute(Attribute::NoAlias) 496 .removeAttribute(Attribute::NonNull) 497 .hasAttributes()) 498 return false; 499 500 // It's not safe to eliminate the sign / zero extension of the return value. 501 if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) || 502 CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 503 return false; 504 505 // Only tail call if the following instruction is a standard return. 506 auto Next = next_nodbg(MI.getIterator(), MBB.instr_end()); 507 if (Next == MBB.instr_end() || TII.isTailCall(*Next) || !Next->isReturn()) 508 return false; 509 510 return true; 511 } 512 513 LegalizerHelper::LegalizeResult 514 llvm::createLibcall(MachineIRBuilder &MIRBuilder, const char *Name, 515 const CallLowering::ArgInfo &Result, 516 ArrayRef<CallLowering::ArgInfo> Args, 517 const CallingConv::ID CC) { 518 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 519 520 CallLowering::CallLoweringInfo Info; 521 Info.CallConv = CC; 522 Info.Callee = MachineOperand::CreateES(Name); 523 Info.OrigRet = Result; 524 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 525 if (!CLI.lowerCall(MIRBuilder, Info)) 526 return LegalizerHelper::UnableToLegalize; 527 528 return LegalizerHelper::Legalized; 529 } 530 531 LegalizerHelper::LegalizeResult 532 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall, 533 const CallLowering::ArgInfo &Result, 534 ArrayRef<CallLowering::ArgInfo> Args) { 535 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 536 const char *Name = TLI.getLibcallName(Libcall); 537 const CallingConv::ID CC = TLI.getLibcallCallingConv(Libcall); 538 return createLibcall(MIRBuilder, Name, Result, Args, CC); 539 } 540 541 // Useful for libcalls where all operands have the same type. 542 static LegalizerHelper::LegalizeResult 543 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size, 544 Type *OpType) { 545 auto Libcall = getRTLibDesc(MI.getOpcode(), Size); 546 547 SmallVector<CallLowering::ArgInfo, 3> Args; 548 for (unsigned i = 1; i < MI.getNumOperands(); i++) 549 Args.push_back({MI.getOperand(i).getReg(), OpType}); 550 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType}, 551 Args); 552 } 553 554 LegalizerHelper::LegalizeResult 555 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 556 MachineInstr &MI, LostDebugLocObserver &LocObserver) { 557 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 558 559 SmallVector<CallLowering::ArgInfo, 3> Args; 560 // Add all the args, except for the last which is an imm denoting 'tail'. 561 for (unsigned i = 0; i < MI.getNumOperands() - 1; ++i) { 562 Register Reg = MI.getOperand(i).getReg(); 563 564 // Need derive an IR type for call lowering. 565 LLT OpLLT = MRI.getType(Reg); 566 Type *OpTy = nullptr; 567 if (OpLLT.isPointer()) 568 OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace()); 569 else 570 OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits()); 571 Args.push_back({Reg, OpTy}); 572 } 573 574 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 575 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 576 RTLIB::Libcall RTLibcall; 577 unsigned Opc = MI.getOpcode(); 578 switch (Opc) { 579 case TargetOpcode::G_BZERO: 580 RTLibcall = RTLIB::BZERO; 581 break; 582 case TargetOpcode::G_MEMCPY: 583 RTLibcall = RTLIB::MEMCPY; 584 break; 585 case TargetOpcode::G_MEMMOVE: 586 RTLibcall = RTLIB::MEMMOVE; 587 break; 588 case TargetOpcode::G_MEMSET: 589 RTLibcall = RTLIB::MEMSET; 590 break; 591 default: 592 return LegalizerHelper::UnableToLegalize; 593 } 594 const char *Name = TLI.getLibcallName(RTLibcall); 595 596 // Unsupported libcall on the target. 597 if (!Name) { 598 LLVM_DEBUG(dbgs() << ".. .. Could not find libcall name for " 599 << MIRBuilder.getTII().getName(Opc) << "\n"); 600 return LegalizerHelper::UnableToLegalize; 601 } 602 603 CallLowering::CallLoweringInfo Info; 604 Info.CallConv = TLI.getLibcallCallingConv(RTLibcall); 605 Info.Callee = MachineOperand::CreateES(Name); 606 Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx)); 607 Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() && 608 isLibCallInTailPosition(MIRBuilder.getTII(), MI); 609 610 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 611 if (!CLI.lowerCall(MIRBuilder, Info)) 612 return LegalizerHelper::UnableToLegalize; 613 614 615 if (Info.LoweredTailCall) { 616 assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?"); 617 618 // Check debug locations before removing the return. 619 LocObserver.checkpoint(true); 620 621 // We must have a return following the call (or debug insts) to get past 622 // isLibCallInTailPosition. 623 do { 624 MachineInstr *Next = MI.getNextNode(); 625 assert(Next && (Next->isReturn() || Next->isDebugInstr()) && 626 "Expected instr following MI to be return or debug inst?"); 627 // We lowered a tail call, so the call is now the return from the block. 628 // Delete the old return. 629 Next->eraseFromParent(); 630 } while (MI.getNextNode()); 631 632 // We expect to lose the debug location from the return. 633 LocObserver.checkpoint(false); 634 } 635 636 return LegalizerHelper::Legalized; 637 } 638 639 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType, 640 Type *FromType) { 641 auto ToMVT = MVT::getVT(ToType); 642 auto FromMVT = MVT::getVT(FromType); 643 644 switch (Opcode) { 645 case TargetOpcode::G_FPEXT: 646 return RTLIB::getFPEXT(FromMVT, ToMVT); 647 case TargetOpcode::G_FPTRUNC: 648 return RTLIB::getFPROUND(FromMVT, ToMVT); 649 case TargetOpcode::G_FPTOSI: 650 return RTLIB::getFPTOSINT(FromMVT, ToMVT); 651 case TargetOpcode::G_FPTOUI: 652 return RTLIB::getFPTOUINT(FromMVT, ToMVT); 653 case TargetOpcode::G_SITOFP: 654 return RTLIB::getSINTTOFP(FromMVT, ToMVT); 655 case TargetOpcode::G_UITOFP: 656 return RTLIB::getUINTTOFP(FromMVT, ToMVT); 657 } 658 llvm_unreachable("Unsupported libcall function"); 659 } 660 661 static LegalizerHelper::LegalizeResult 662 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType, 663 Type *FromType) { 664 RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType); 665 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType}, 666 {{MI.getOperand(1).getReg(), FromType}}); 667 } 668 669 LegalizerHelper::LegalizeResult 670 LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) { 671 LLT LLTy = MRI.getType(MI.getOperand(0).getReg()); 672 unsigned Size = LLTy.getSizeInBits(); 673 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 674 675 switch (MI.getOpcode()) { 676 default: 677 return UnableToLegalize; 678 case TargetOpcode::G_SDIV: 679 case TargetOpcode::G_UDIV: 680 case TargetOpcode::G_SREM: 681 case TargetOpcode::G_UREM: 682 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 683 Type *HLTy = IntegerType::get(Ctx, Size); 684 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 685 if (Status != Legalized) 686 return Status; 687 break; 688 } 689 case TargetOpcode::G_FADD: 690 case TargetOpcode::G_FSUB: 691 case TargetOpcode::G_FMUL: 692 case TargetOpcode::G_FDIV: 693 case TargetOpcode::G_FMA: 694 case TargetOpcode::G_FPOW: 695 case TargetOpcode::G_FREM: 696 case TargetOpcode::G_FCOS: 697 case TargetOpcode::G_FSIN: 698 case TargetOpcode::G_FLOG10: 699 case TargetOpcode::G_FLOG: 700 case TargetOpcode::G_FLOG2: 701 case TargetOpcode::G_FEXP: 702 case TargetOpcode::G_FEXP2: 703 case TargetOpcode::G_FCEIL: 704 case TargetOpcode::G_FFLOOR: 705 case TargetOpcode::G_FMINNUM: 706 case TargetOpcode::G_FMAXNUM: 707 case TargetOpcode::G_FSQRT: 708 case TargetOpcode::G_FRINT: 709 case TargetOpcode::G_FNEARBYINT: 710 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 711 Type *HLTy = getFloatTypeForLLT(Ctx, LLTy); 712 if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) { 713 LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n"); 714 return UnableToLegalize; 715 } 716 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 717 if (Status != Legalized) 718 return Status; 719 break; 720 } 721 case TargetOpcode::G_FPEXT: 722 case TargetOpcode::G_FPTRUNC: { 723 Type *FromTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(1).getReg())); 724 Type *ToTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(0).getReg())); 725 if (!FromTy || !ToTy) 726 return UnableToLegalize; 727 LegalizeResult Status = conversionLibcall(MI, MIRBuilder, ToTy, FromTy ); 728 if (Status != Legalized) 729 return Status; 730 break; 731 } 732 case TargetOpcode::G_FPTOSI: 733 case TargetOpcode::G_FPTOUI: { 734 // FIXME: Support other types 735 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 736 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 737 if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64)) 738 return UnableToLegalize; 739 LegalizeResult Status = conversionLibcall( 740 MI, MIRBuilder, 741 ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx), 742 FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx)); 743 if (Status != Legalized) 744 return Status; 745 break; 746 } 747 case TargetOpcode::G_SITOFP: 748 case TargetOpcode::G_UITOFP: { 749 // FIXME: Support other types 750 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 751 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 752 if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64)) 753 return UnableToLegalize; 754 LegalizeResult Status = conversionLibcall( 755 MI, MIRBuilder, 756 ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx), 757 FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx)); 758 if (Status != Legalized) 759 return Status; 760 break; 761 } 762 case TargetOpcode::G_BZERO: 763 case TargetOpcode::G_MEMCPY: 764 case TargetOpcode::G_MEMMOVE: 765 case TargetOpcode::G_MEMSET: { 766 LegalizeResult Result = 767 createMemLibcall(MIRBuilder, *MIRBuilder.getMRI(), MI, LocObserver); 768 if (Result != Legalized) 769 return Result; 770 MI.eraseFromParent(); 771 return Result; 772 } 773 } 774 775 MI.eraseFromParent(); 776 return Legalized; 777 } 778 779 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, 780 unsigned TypeIdx, 781 LLT NarrowTy) { 782 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 783 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 784 785 switch (MI.getOpcode()) { 786 default: 787 return UnableToLegalize; 788 case TargetOpcode::G_IMPLICIT_DEF: { 789 Register DstReg = MI.getOperand(0).getReg(); 790 LLT DstTy = MRI.getType(DstReg); 791 792 // If SizeOp0 is not an exact multiple of NarrowSize, emit 793 // G_ANYEXT(G_IMPLICIT_DEF). Cast result to vector if needed. 794 // FIXME: Although this would also be legal for the general case, it causes 795 // a lot of regressions in the emitted code (superfluous COPYs, artifact 796 // combines not being hit). This seems to be a problem related to the 797 // artifact combiner. 798 if (SizeOp0 % NarrowSize != 0) { 799 LLT ImplicitTy = NarrowTy; 800 if (DstTy.isVector()) 801 ImplicitTy = LLT::vector(DstTy.getNumElements(), ImplicitTy); 802 803 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); 804 MIRBuilder.buildAnyExt(DstReg, ImplicitReg); 805 806 MI.eraseFromParent(); 807 return Legalized; 808 } 809 810 int NumParts = SizeOp0 / NarrowSize; 811 812 SmallVector<Register, 2> DstRegs; 813 for (int i = 0; i < NumParts; ++i) 814 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); 815 816 if (DstTy.isVector()) 817 MIRBuilder.buildBuildVector(DstReg, DstRegs); 818 else 819 MIRBuilder.buildMerge(DstReg, DstRegs); 820 MI.eraseFromParent(); 821 return Legalized; 822 } 823 case TargetOpcode::G_CONSTANT: { 824 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 825 const APInt &Val = MI.getOperand(1).getCImm()->getValue(); 826 unsigned TotalSize = Ty.getSizeInBits(); 827 unsigned NarrowSize = NarrowTy.getSizeInBits(); 828 int NumParts = TotalSize / NarrowSize; 829 830 SmallVector<Register, 4> PartRegs; 831 for (int I = 0; I != NumParts; ++I) { 832 unsigned Offset = I * NarrowSize; 833 auto K = MIRBuilder.buildConstant(NarrowTy, 834 Val.lshr(Offset).trunc(NarrowSize)); 835 PartRegs.push_back(K.getReg(0)); 836 } 837 838 LLT LeftoverTy; 839 unsigned LeftoverBits = TotalSize - NumParts * NarrowSize; 840 SmallVector<Register, 1> LeftoverRegs; 841 if (LeftoverBits != 0) { 842 LeftoverTy = LLT::scalar(LeftoverBits); 843 auto K = MIRBuilder.buildConstant( 844 LeftoverTy, 845 Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits)); 846 LeftoverRegs.push_back(K.getReg(0)); 847 } 848 849 insertParts(MI.getOperand(0).getReg(), 850 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs); 851 852 MI.eraseFromParent(); 853 return Legalized; 854 } 855 case TargetOpcode::G_SEXT: 856 case TargetOpcode::G_ZEXT: 857 case TargetOpcode::G_ANYEXT: 858 return narrowScalarExt(MI, TypeIdx, NarrowTy); 859 case TargetOpcode::G_TRUNC: { 860 if (TypeIdx != 1) 861 return UnableToLegalize; 862 863 uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 864 if (NarrowTy.getSizeInBits() * 2 != SizeOp1) { 865 LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n"); 866 return UnableToLegalize; 867 } 868 869 auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 870 MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0)); 871 MI.eraseFromParent(); 872 return Legalized; 873 } 874 875 case TargetOpcode::G_FREEZE: 876 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 877 case TargetOpcode::G_ADD: 878 case TargetOpcode::G_SUB: 879 case TargetOpcode::G_SADDO: 880 case TargetOpcode::G_SSUBO: 881 case TargetOpcode::G_SADDE: 882 case TargetOpcode::G_SSUBE: 883 case TargetOpcode::G_UADDO: 884 case TargetOpcode::G_USUBO: 885 case TargetOpcode::G_UADDE: 886 case TargetOpcode::G_USUBE: 887 return narrowScalarAddSub(MI, TypeIdx, NarrowTy); 888 case TargetOpcode::G_MUL: 889 case TargetOpcode::G_UMULH: 890 return narrowScalarMul(MI, NarrowTy); 891 case TargetOpcode::G_EXTRACT: 892 return narrowScalarExtract(MI, TypeIdx, NarrowTy); 893 case TargetOpcode::G_INSERT: 894 return narrowScalarInsert(MI, TypeIdx, NarrowTy); 895 case TargetOpcode::G_LOAD: { 896 auto &MMO = **MI.memoperands_begin(); 897 Register DstReg = MI.getOperand(0).getReg(); 898 LLT DstTy = MRI.getType(DstReg); 899 if (DstTy.isVector()) 900 return UnableToLegalize; 901 902 if (8 * MMO.getSize() != DstTy.getSizeInBits()) { 903 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 904 MIRBuilder.buildLoad(TmpReg, MI.getOperand(1), MMO); 905 MIRBuilder.buildAnyExt(DstReg, TmpReg); 906 MI.eraseFromParent(); 907 return Legalized; 908 } 909 910 return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy); 911 } 912 case TargetOpcode::G_ZEXTLOAD: 913 case TargetOpcode::G_SEXTLOAD: { 914 bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD; 915 Register DstReg = MI.getOperand(0).getReg(); 916 Register PtrReg = MI.getOperand(1).getReg(); 917 918 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 919 auto &MMO = **MI.memoperands_begin(); 920 unsigned MemSize = MMO.getSizeInBits(); 921 922 if (MemSize == NarrowSize) { 923 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); 924 } else if (MemSize < NarrowSize) { 925 MIRBuilder.buildLoadInstr(MI.getOpcode(), TmpReg, PtrReg, MMO); 926 } else if (MemSize > NarrowSize) { 927 // FIXME: Need to split the load. 928 return UnableToLegalize; 929 } 930 931 if (ZExt) 932 MIRBuilder.buildZExt(DstReg, TmpReg); 933 else 934 MIRBuilder.buildSExt(DstReg, TmpReg); 935 936 MI.eraseFromParent(); 937 return Legalized; 938 } 939 case TargetOpcode::G_STORE: { 940 const auto &MMO = **MI.memoperands_begin(); 941 942 Register SrcReg = MI.getOperand(0).getReg(); 943 LLT SrcTy = MRI.getType(SrcReg); 944 if (SrcTy.isVector()) 945 return UnableToLegalize; 946 947 int NumParts = SizeOp0 / NarrowSize; 948 unsigned HandledSize = NumParts * NarrowTy.getSizeInBits(); 949 unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize; 950 if (SrcTy.isVector() && LeftoverBits != 0) 951 return UnableToLegalize; 952 953 if (8 * MMO.getSize() != SrcTy.getSizeInBits()) { 954 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 955 auto &MMO = **MI.memoperands_begin(); 956 MIRBuilder.buildTrunc(TmpReg, SrcReg); 957 MIRBuilder.buildStore(TmpReg, MI.getOperand(1), MMO); 958 MI.eraseFromParent(); 959 return Legalized; 960 } 961 962 return reduceLoadStoreWidth(MI, 0, NarrowTy); 963 } 964 case TargetOpcode::G_SELECT: 965 return narrowScalarSelect(MI, TypeIdx, NarrowTy); 966 case TargetOpcode::G_AND: 967 case TargetOpcode::G_OR: 968 case TargetOpcode::G_XOR: { 969 // Legalize bitwise operation: 970 // A = BinOp<Ty> B, C 971 // into: 972 // B1, ..., BN = G_UNMERGE_VALUES B 973 // C1, ..., CN = G_UNMERGE_VALUES C 974 // A1 = BinOp<Ty/N> B1, C2 975 // ... 976 // AN = BinOp<Ty/N> BN, CN 977 // A = G_MERGE_VALUES A1, ..., AN 978 return narrowScalarBasic(MI, TypeIdx, NarrowTy); 979 } 980 case TargetOpcode::G_SHL: 981 case TargetOpcode::G_LSHR: 982 case TargetOpcode::G_ASHR: 983 return narrowScalarShift(MI, TypeIdx, NarrowTy); 984 case TargetOpcode::G_CTLZ: 985 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 986 case TargetOpcode::G_CTTZ: 987 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 988 case TargetOpcode::G_CTPOP: 989 if (TypeIdx == 1) 990 switch (MI.getOpcode()) { 991 case TargetOpcode::G_CTLZ: 992 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 993 return narrowScalarCTLZ(MI, TypeIdx, NarrowTy); 994 case TargetOpcode::G_CTTZ: 995 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 996 return narrowScalarCTTZ(MI, TypeIdx, NarrowTy); 997 case TargetOpcode::G_CTPOP: 998 return narrowScalarCTPOP(MI, TypeIdx, NarrowTy); 999 default: 1000 return UnableToLegalize; 1001 } 1002 1003 Observer.changingInstr(MI); 1004 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1005 Observer.changedInstr(MI); 1006 return Legalized; 1007 case TargetOpcode::G_INTTOPTR: 1008 if (TypeIdx != 1) 1009 return UnableToLegalize; 1010 1011 Observer.changingInstr(MI); 1012 narrowScalarSrc(MI, NarrowTy, 1); 1013 Observer.changedInstr(MI); 1014 return Legalized; 1015 case TargetOpcode::G_PTRTOINT: 1016 if (TypeIdx != 0) 1017 return UnableToLegalize; 1018 1019 Observer.changingInstr(MI); 1020 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1021 Observer.changedInstr(MI); 1022 return Legalized; 1023 case TargetOpcode::G_PHI: { 1024 // FIXME: add support for when SizeOp0 isn't an exact multiple of 1025 // NarrowSize. 1026 if (SizeOp0 % NarrowSize != 0) 1027 return UnableToLegalize; 1028 1029 unsigned NumParts = SizeOp0 / NarrowSize; 1030 SmallVector<Register, 2> DstRegs(NumParts); 1031 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2); 1032 Observer.changingInstr(MI); 1033 for (unsigned i = 1; i < MI.getNumOperands(); i += 2) { 1034 MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB(); 1035 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 1036 extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts, 1037 SrcRegs[i / 2]); 1038 } 1039 MachineBasicBlock &MBB = *MI.getParent(); 1040 MIRBuilder.setInsertPt(MBB, MI); 1041 for (unsigned i = 0; i < NumParts; ++i) { 1042 DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy); 1043 MachineInstrBuilder MIB = 1044 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); 1045 for (unsigned j = 1; j < MI.getNumOperands(); j += 2) 1046 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); 1047 } 1048 MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI()); 1049 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1050 Observer.changedInstr(MI); 1051 MI.eraseFromParent(); 1052 return Legalized; 1053 } 1054 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 1055 case TargetOpcode::G_INSERT_VECTOR_ELT: { 1056 if (TypeIdx != 2) 1057 return UnableToLegalize; 1058 1059 int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3; 1060 Observer.changingInstr(MI); 1061 narrowScalarSrc(MI, NarrowTy, OpIdx); 1062 Observer.changedInstr(MI); 1063 return Legalized; 1064 } 1065 case TargetOpcode::G_ICMP: { 1066 uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 1067 if (NarrowSize * 2 != SrcSize) 1068 return UnableToLegalize; 1069 1070 Observer.changingInstr(MI); 1071 Register LHSL = MRI.createGenericVirtualRegister(NarrowTy); 1072 Register LHSH = MRI.createGenericVirtualRegister(NarrowTy); 1073 MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2)); 1074 1075 Register RHSL = MRI.createGenericVirtualRegister(NarrowTy); 1076 Register RHSH = MRI.createGenericVirtualRegister(NarrowTy); 1077 MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3)); 1078 1079 CmpInst::Predicate Pred = 1080 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 1081 LLT ResTy = MRI.getType(MI.getOperand(0).getReg()); 1082 1083 if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) { 1084 MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL); 1085 MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH); 1086 MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH); 1087 MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0); 1088 MIRBuilder.buildICmp(Pred, MI.getOperand(0), Or, Zero); 1089 } else { 1090 MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH); 1091 MachineInstrBuilder CmpHEQ = 1092 MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH); 1093 MachineInstrBuilder CmpLU = MIRBuilder.buildICmp( 1094 ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL); 1095 MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH); 1096 } 1097 Observer.changedInstr(MI); 1098 MI.eraseFromParent(); 1099 return Legalized; 1100 } 1101 case TargetOpcode::G_SEXT_INREG: { 1102 if (TypeIdx != 0) 1103 return UnableToLegalize; 1104 1105 int64_t SizeInBits = MI.getOperand(2).getImm(); 1106 1107 // So long as the new type has more bits than the bits we're extending we 1108 // don't need to break it apart. 1109 if (NarrowTy.getScalarSizeInBits() >= SizeInBits) { 1110 Observer.changingInstr(MI); 1111 // We don't lose any non-extension bits by truncating the src and 1112 // sign-extending the dst. 1113 MachineOperand &MO1 = MI.getOperand(1); 1114 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1); 1115 MO1.setReg(TruncMIB.getReg(0)); 1116 1117 MachineOperand &MO2 = MI.getOperand(0); 1118 Register DstExt = MRI.createGenericVirtualRegister(NarrowTy); 1119 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1120 MIRBuilder.buildSExt(MO2, DstExt); 1121 MO2.setReg(DstExt); 1122 Observer.changedInstr(MI); 1123 return Legalized; 1124 } 1125 1126 // Break it apart. Components below the extension point are unmodified. The 1127 // component containing the extension point becomes a narrower SEXT_INREG. 1128 // Components above it are ashr'd from the component containing the 1129 // extension point. 1130 if (SizeOp0 % NarrowSize != 0) 1131 return UnableToLegalize; 1132 int NumParts = SizeOp0 / NarrowSize; 1133 1134 // List the registers where the destination will be scattered. 1135 SmallVector<Register, 2> DstRegs; 1136 // List the registers where the source will be split. 1137 SmallVector<Register, 2> SrcRegs; 1138 1139 // Create all the temporary registers. 1140 for (int i = 0; i < NumParts; ++i) { 1141 Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy); 1142 1143 SrcRegs.push_back(SrcReg); 1144 } 1145 1146 // Explode the big arguments into smaller chunks. 1147 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1)); 1148 1149 Register AshrCstReg = 1150 MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1) 1151 .getReg(0); 1152 Register FullExtensionReg = 0; 1153 Register PartialExtensionReg = 0; 1154 1155 // Do the operation on each small part. 1156 for (int i = 0; i < NumParts; ++i) { 1157 if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits) 1158 DstRegs.push_back(SrcRegs[i]); 1159 else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) { 1160 assert(PartialExtensionReg && 1161 "Expected to visit partial extension before full"); 1162 if (FullExtensionReg) { 1163 DstRegs.push_back(FullExtensionReg); 1164 continue; 1165 } 1166 DstRegs.push_back( 1167 MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg) 1168 .getReg(0)); 1169 FullExtensionReg = DstRegs.back(); 1170 } else { 1171 DstRegs.push_back( 1172 MIRBuilder 1173 .buildInstr( 1174 TargetOpcode::G_SEXT_INREG, {NarrowTy}, 1175 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) 1176 .getReg(0)); 1177 PartialExtensionReg = DstRegs.back(); 1178 } 1179 } 1180 1181 // Gather the destination registers into the final destination. 1182 Register DstReg = MI.getOperand(0).getReg(); 1183 MIRBuilder.buildMerge(DstReg, DstRegs); 1184 MI.eraseFromParent(); 1185 return Legalized; 1186 } 1187 case TargetOpcode::G_BSWAP: 1188 case TargetOpcode::G_BITREVERSE: { 1189 if (SizeOp0 % NarrowSize != 0) 1190 return UnableToLegalize; 1191 1192 Observer.changingInstr(MI); 1193 SmallVector<Register, 2> SrcRegs, DstRegs; 1194 unsigned NumParts = SizeOp0 / NarrowSize; 1195 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 1196 1197 for (unsigned i = 0; i < NumParts; ++i) { 1198 auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 1199 {SrcRegs[NumParts - 1 - i]}); 1200 DstRegs.push_back(DstPart.getReg(0)); 1201 } 1202 1203 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1204 1205 Observer.changedInstr(MI); 1206 MI.eraseFromParent(); 1207 return Legalized; 1208 } 1209 case TargetOpcode::G_PTR_ADD: 1210 case TargetOpcode::G_PTRMASK: { 1211 if (TypeIdx != 1) 1212 return UnableToLegalize; 1213 Observer.changingInstr(MI); 1214 narrowScalarSrc(MI, NarrowTy, 2); 1215 Observer.changedInstr(MI); 1216 return Legalized; 1217 } 1218 case TargetOpcode::G_FPTOUI: 1219 case TargetOpcode::G_FPTOSI: 1220 return narrowScalarFPTOI(MI, TypeIdx, NarrowTy); 1221 case TargetOpcode::G_FPEXT: 1222 if (TypeIdx != 0) 1223 return UnableToLegalize; 1224 Observer.changingInstr(MI); 1225 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_FPEXT); 1226 Observer.changedInstr(MI); 1227 return Legalized; 1228 } 1229 } 1230 1231 Register LegalizerHelper::coerceToScalar(Register Val) { 1232 LLT Ty = MRI.getType(Val); 1233 if (Ty.isScalar()) 1234 return Val; 1235 1236 const DataLayout &DL = MIRBuilder.getDataLayout(); 1237 LLT NewTy = LLT::scalar(Ty.getSizeInBits()); 1238 if (Ty.isPointer()) { 1239 if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace())) 1240 return Register(); 1241 return MIRBuilder.buildPtrToInt(NewTy, Val).getReg(0); 1242 } 1243 1244 Register NewVal = Val; 1245 1246 assert(Ty.isVector()); 1247 LLT EltTy = Ty.getElementType(); 1248 if (EltTy.isPointer()) 1249 NewVal = MIRBuilder.buildPtrToInt(NewTy, NewVal).getReg(0); 1250 return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0); 1251 } 1252 1253 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy, 1254 unsigned OpIdx, unsigned ExtOpcode) { 1255 MachineOperand &MO = MI.getOperand(OpIdx); 1256 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO}); 1257 MO.setReg(ExtB.getReg(0)); 1258 } 1259 1260 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, 1261 unsigned OpIdx) { 1262 MachineOperand &MO = MI.getOperand(OpIdx); 1263 auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO); 1264 MO.setReg(ExtB.getReg(0)); 1265 } 1266 1267 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy, 1268 unsigned OpIdx, unsigned TruncOpcode) { 1269 MachineOperand &MO = MI.getOperand(OpIdx); 1270 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1271 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1272 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); 1273 MO.setReg(DstExt); 1274 } 1275 1276 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy, 1277 unsigned OpIdx, unsigned ExtOpcode) { 1278 MachineOperand &MO = MI.getOperand(OpIdx); 1279 Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy); 1280 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1281 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); 1282 MO.setReg(DstTrunc); 1283 } 1284 1285 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy, 1286 unsigned OpIdx) { 1287 MachineOperand &MO = MI.getOperand(OpIdx); 1288 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1289 MO.setReg(widenWithUnmerge(WideTy, MO.getReg())); 1290 } 1291 1292 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, 1293 unsigned OpIdx) { 1294 MachineOperand &MO = MI.getOperand(OpIdx); 1295 1296 LLT OldTy = MRI.getType(MO.getReg()); 1297 unsigned OldElts = OldTy.getNumElements(); 1298 unsigned NewElts = MoreTy.getNumElements(); 1299 1300 unsigned NumParts = NewElts / OldElts; 1301 1302 // Use concat_vectors if the result is a multiple of the number of elements. 1303 if (NumParts * OldElts == NewElts) { 1304 SmallVector<Register, 8> Parts; 1305 Parts.push_back(MO.getReg()); 1306 1307 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); 1308 for (unsigned I = 1; I != NumParts; ++I) 1309 Parts.push_back(ImpDef); 1310 1311 auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts); 1312 MO.setReg(Concat.getReg(0)); 1313 return; 1314 } 1315 1316 Register MoreReg = MRI.createGenericVirtualRegister(MoreTy); 1317 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); 1318 MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0); 1319 MO.setReg(MoreReg); 1320 } 1321 1322 void LegalizerHelper::bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1323 MachineOperand &Op = MI.getOperand(OpIdx); 1324 Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0)); 1325 } 1326 1327 void LegalizerHelper::bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1328 MachineOperand &MO = MI.getOperand(OpIdx); 1329 Register CastDst = MRI.createGenericVirtualRegister(CastTy); 1330 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1331 MIRBuilder.buildBitcast(MO, CastDst); 1332 MO.setReg(CastDst); 1333 } 1334 1335 LegalizerHelper::LegalizeResult 1336 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, 1337 LLT WideTy) { 1338 if (TypeIdx != 1) 1339 return UnableToLegalize; 1340 1341 Register DstReg = MI.getOperand(0).getReg(); 1342 LLT DstTy = MRI.getType(DstReg); 1343 if (DstTy.isVector()) 1344 return UnableToLegalize; 1345 1346 Register Src1 = MI.getOperand(1).getReg(); 1347 LLT SrcTy = MRI.getType(Src1); 1348 const int DstSize = DstTy.getSizeInBits(); 1349 const int SrcSize = SrcTy.getSizeInBits(); 1350 const int WideSize = WideTy.getSizeInBits(); 1351 const int NumMerge = (DstSize + WideSize - 1) / WideSize; 1352 1353 unsigned NumOps = MI.getNumOperands(); 1354 unsigned NumSrc = MI.getNumOperands() - 1; 1355 unsigned PartSize = DstTy.getSizeInBits() / NumSrc; 1356 1357 if (WideSize >= DstSize) { 1358 // Directly pack the bits in the target type. 1359 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); 1360 1361 for (unsigned I = 2; I != NumOps; ++I) { 1362 const unsigned Offset = (I - 1) * PartSize; 1363 1364 Register SrcReg = MI.getOperand(I).getReg(); 1365 assert(MRI.getType(SrcReg) == LLT::scalar(PartSize)); 1366 1367 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 1368 1369 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 1370 MRI.createGenericVirtualRegister(WideTy); 1371 1372 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 1373 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 1374 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 1375 ResultReg = NextResult; 1376 } 1377 1378 if (WideSize > DstSize) 1379 MIRBuilder.buildTrunc(DstReg, ResultReg); 1380 else if (DstTy.isPointer()) 1381 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 1382 1383 MI.eraseFromParent(); 1384 return Legalized; 1385 } 1386 1387 // Unmerge the original values to the GCD type, and recombine to the next 1388 // multiple greater than the original type. 1389 // 1390 // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6 1391 // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0 1392 // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1 1393 // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2 1394 // %10:_(s6) = G_MERGE_VALUES %4, %5, %6 1395 // %11:_(s6) = G_MERGE_VALUES %7, %8, %9 1396 // %12:_(s12) = G_MERGE_VALUES %10, %11 1397 // 1398 // Padding with undef if necessary: 1399 // 1400 // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6 1401 // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0 1402 // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1 1403 // %7:_(s2) = G_IMPLICIT_DEF 1404 // %8:_(s6) = G_MERGE_VALUES %3, %4, %5 1405 // %9:_(s6) = G_MERGE_VALUES %6, %7, %7 1406 // %10:_(s12) = G_MERGE_VALUES %8, %9 1407 1408 const int GCD = greatestCommonDivisor(SrcSize, WideSize); 1409 LLT GCDTy = LLT::scalar(GCD); 1410 1411 SmallVector<Register, 8> Parts; 1412 SmallVector<Register, 8> NewMergeRegs; 1413 SmallVector<Register, 8> Unmerges; 1414 LLT WideDstTy = LLT::scalar(NumMerge * WideSize); 1415 1416 // Decompose the original operands if they don't evenly divide. 1417 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) { 1418 Register SrcReg = MI.getOperand(I).getReg(); 1419 if (GCD == SrcSize) { 1420 Unmerges.push_back(SrcReg); 1421 } else { 1422 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 1423 for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J) 1424 Unmerges.push_back(Unmerge.getReg(J)); 1425 } 1426 } 1427 1428 // Pad with undef to the next size that is a multiple of the requested size. 1429 if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) { 1430 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 1431 for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I) 1432 Unmerges.push_back(UndefReg); 1433 } 1434 1435 const int PartsPerGCD = WideSize / GCD; 1436 1437 // Build merges of each piece. 1438 ArrayRef<Register> Slicer(Unmerges); 1439 for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) { 1440 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD)); 1441 NewMergeRegs.push_back(Merge.getReg(0)); 1442 } 1443 1444 // A truncate may be necessary if the requested type doesn't evenly divide the 1445 // original result type. 1446 if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) { 1447 MIRBuilder.buildMerge(DstReg, NewMergeRegs); 1448 } else { 1449 auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs); 1450 MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0)); 1451 } 1452 1453 MI.eraseFromParent(); 1454 return Legalized; 1455 } 1456 1457 Register LegalizerHelper::widenWithUnmerge(LLT WideTy, Register OrigReg) { 1458 Register WideReg = MRI.createGenericVirtualRegister(WideTy); 1459 LLT OrigTy = MRI.getType(OrigReg); 1460 LLT LCMTy = getLCMType(WideTy, OrigTy); 1461 1462 const int NumMergeParts = LCMTy.getSizeInBits() / WideTy.getSizeInBits(); 1463 const int NumUnmergeParts = LCMTy.getSizeInBits() / OrigTy.getSizeInBits(); 1464 1465 Register UnmergeSrc = WideReg; 1466 1467 // Create a merge to the LCM type, padding with undef 1468 // %0:_(<3 x s32>) = G_FOO => <4 x s32> 1469 // => 1470 // %1:_(<4 x s32>) = G_FOO 1471 // %2:_(<4 x s32>) = G_IMPLICIT_DEF 1472 // %3:_(<12 x s32>) = G_CONCAT_VECTORS %1, %2, %2 1473 // %0:_(<3 x s32>), %4:_, %5:_, %6:_ = G_UNMERGE_VALUES %3 1474 if (NumMergeParts > 1) { 1475 Register Undef = MIRBuilder.buildUndef(WideTy).getReg(0); 1476 SmallVector<Register, 8> MergeParts(NumMergeParts, Undef); 1477 MergeParts[0] = WideReg; 1478 UnmergeSrc = MIRBuilder.buildMerge(LCMTy, MergeParts).getReg(0); 1479 } 1480 1481 // Unmerge to the original register and pad with dead defs. 1482 SmallVector<Register, 8> UnmergeResults(NumUnmergeParts); 1483 UnmergeResults[0] = OrigReg; 1484 for (int I = 1; I != NumUnmergeParts; ++I) 1485 UnmergeResults[I] = MRI.createGenericVirtualRegister(OrigTy); 1486 1487 MIRBuilder.buildUnmerge(UnmergeResults, UnmergeSrc); 1488 return WideReg; 1489 } 1490 1491 LegalizerHelper::LegalizeResult 1492 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, 1493 LLT WideTy) { 1494 if (TypeIdx != 0) 1495 return UnableToLegalize; 1496 1497 int NumDst = MI.getNumOperands() - 1; 1498 Register SrcReg = MI.getOperand(NumDst).getReg(); 1499 LLT SrcTy = MRI.getType(SrcReg); 1500 if (SrcTy.isVector()) 1501 return UnableToLegalize; 1502 1503 Register Dst0Reg = MI.getOperand(0).getReg(); 1504 LLT DstTy = MRI.getType(Dst0Reg); 1505 if (!DstTy.isScalar()) 1506 return UnableToLegalize; 1507 1508 if (WideTy.getSizeInBits() >= SrcTy.getSizeInBits()) { 1509 if (SrcTy.isPointer()) { 1510 const DataLayout &DL = MIRBuilder.getDataLayout(); 1511 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) { 1512 LLVM_DEBUG( 1513 dbgs() << "Not casting non-integral address space integer\n"); 1514 return UnableToLegalize; 1515 } 1516 1517 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 1518 SrcReg = MIRBuilder.buildPtrToInt(SrcTy, SrcReg).getReg(0); 1519 } 1520 1521 // Widen SrcTy to WideTy. This does not affect the result, but since the 1522 // user requested this size, it is probably better handled than SrcTy and 1523 // should reduce the total number of legalization artifacts 1524 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1525 SrcTy = WideTy; 1526 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); 1527 } 1528 1529 // Theres no unmerge type to target. Directly extract the bits from the 1530 // source type 1531 unsigned DstSize = DstTy.getSizeInBits(); 1532 1533 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 1534 for (int I = 1; I != NumDst; ++I) { 1535 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I); 1536 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); 1537 MIRBuilder.buildTrunc(MI.getOperand(I), Shr); 1538 } 1539 1540 MI.eraseFromParent(); 1541 return Legalized; 1542 } 1543 1544 // Extend the source to a wider type. 1545 LLT LCMTy = getLCMType(SrcTy, WideTy); 1546 1547 Register WideSrc = SrcReg; 1548 if (LCMTy.getSizeInBits() != SrcTy.getSizeInBits()) { 1549 // TODO: If this is an integral address space, cast to integer and anyext. 1550 if (SrcTy.isPointer()) { 1551 LLVM_DEBUG(dbgs() << "Widening pointer source types not implemented\n"); 1552 return UnableToLegalize; 1553 } 1554 1555 WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0); 1556 } 1557 1558 auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc); 1559 1560 // Create a sequence of unmerges and merges to the original results. Since we 1561 // may have widened the source, we will need to pad the results with dead defs 1562 // to cover the source register. 1563 // e.g. widen s48 to s64: 1564 // %1:_(s48), %2:_(s48) = G_UNMERGE_VALUES %0:_(s96) 1565 // 1566 // => 1567 // %4:_(s192) = G_ANYEXT %0:_(s96) 1568 // %5:_(s64), %6, %7 = G_UNMERGE_VALUES %4 ; Requested unmerge 1569 // ; unpack to GCD type, with extra dead defs 1570 // %8:_(s16), %9, %10, %11 = G_UNMERGE_VALUES %5:_(s64) 1571 // %12:_(s16), %13, dead %14, dead %15 = G_UNMERGE_VALUES %6:_(s64) 1572 // dead %16:_(s16), dead %17, dead %18, dead %18 = G_UNMERGE_VALUES %7:_(s64) 1573 // %1:_(s48) = G_MERGE_VALUES %8:_(s16), %9, %10 ; Remerge to destination 1574 // %2:_(s48) = G_MERGE_VALUES %11:_(s16), %12, %13 ; Remerge to destination 1575 const LLT GCDTy = getGCDType(WideTy, DstTy); 1576 const int NumUnmerge = Unmerge->getNumOperands() - 1; 1577 const int PartsPerRemerge = DstTy.getSizeInBits() / GCDTy.getSizeInBits(); 1578 1579 // Directly unmerge to the destination without going through a GCD type 1580 // if possible 1581 if (PartsPerRemerge == 1) { 1582 const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits(); 1583 1584 for (int I = 0; I != NumUnmerge; ++I) { 1585 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 1586 1587 for (int J = 0; J != PartsPerUnmerge; ++J) { 1588 int Idx = I * PartsPerUnmerge + J; 1589 if (Idx < NumDst) 1590 MIB.addDef(MI.getOperand(Idx).getReg()); 1591 else { 1592 // Create dead def for excess components. 1593 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 1594 } 1595 } 1596 1597 MIB.addUse(Unmerge.getReg(I)); 1598 } 1599 } else { 1600 SmallVector<Register, 16> Parts; 1601 for (int J = 0; J != NumUnmerge; ++J) 1602 extractGCDType(Parts, GCDTy, Unmerge.getReg(J)); 1603 1604 SmallVector<Register, 8> RemergeParts; 1605 for (int I = 0; I != NumDst; ++I) { 1606 for (int J = 0; J < PartsPerRemerge; ++J) { 1607 const int Idx = I * PartsPerRemerge + J; 1608 RemergeParts.emplace_back(Parts[Idx]); 1609 } 1610 1611 MIRBuilder.buildMerge(MI.getOperand(I).getReg(), RemergeParts); 1612 RemergeParts.clear(); 1613 } 1614 } 1615 1616 MI.eraseFromParent(); 1617 return Legalized; 1618 } 1619 1620 LegalizerHelper::LegalizeResult 1621 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, 1622 LLT WideTy) { 1623 Register DstReg = MI.getOperand(0).getReg(); 1624 Register SrcReg = MI.getOperand(1).getReg(); 1625 LLT SrcTy = MRI.getType(SrcReg); 1626 1627 LLT DstTy = MRI.getType(DstReg); 1628 unsigned Offset = MI.getOperand(2).getImm(); 1629 1630 if (TypeIdx == 0) { 1631 if (SrcTy.isVector() || DstTy.isVector()) 1632 return UnableToLegalize; 1633 1634 SrcOp Src(SrcReg); 1635 if (SrcTy.isPointer()) { 1636 // Extracts from pointers can be handled only if they are really just 1637 // simple integers. 1638 const DataLayout &DL = MIRBuilder.getDataLayout(); 1639 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) 1640 return UnableToLegalize; 1641 1642 LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits()); 1643 Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src); 1644 SrcTy = SrcAsIntTy; 1645 } 1646 1647 if (DstTy.isPointer()) 1648 return UnableToLegalize; 1649 1650 if (Offset == 0) { 1651 // Avoid a shift in the degenerate case. 1652 MIRBuilder.buildTrunc(DstReg, 1653 MIRBuilder.buildAnyExtOrTrunc(WideTy, Src)); 1654 MI.eraseFromParent(); 1655 return Legalized; 1656 } 1657 1658 // Do a shift in the source type. 1659 LLT ShiftTy = SrcTy; 1660 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1661 Src = MIRBuilder.buildAnyExt(WideTy, Src); 1662 ShiftTy = WideTy; 1663 } 1664 1665 auto LShr = MIRBuilder.buildLShr( 1666 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); 1667 MIRBuilder.buildTrunc(DstReg, LShr); 1668 MI.eraseFromParent(); 1669 return Legalized; 1670 } 1671 1672 if (SrcTy.isScalar()) { 1673 Observer.changingInstr(MI); 1674 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1675 Observer.changedInstr(MI); 1676 return Legalized; 1677 } 1678 1679 if (!SrcTy.isVector()) 1680 return UnableToLegalize; 1681 1682 if (DstTy != SrcTy.getElementType()) 1683 return UnableToLegalize; 1684 1685 if (Offset % SrcTy.getScalarSizeInBits() != 0) 1686 return UnableToLegalize; 1687 1688 Observer.changingInstr(MI); 1689 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1690 1691 MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) * 1692 Offset); 1693 widenScalarDst(MI, WideTy.getScalarType(), 0); 1694 Observer.changedInstr(MI); 1695 return Legalized; 1696 } 1697 1698 LegalizerHelper::LegalizeResult 1699 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, 1700 LLT WideTy) { 1701 if (TypeIdx != 0 || WideTy.isVector()) 1702 return UnableToLegalize; 1703 Observer.changingInstr(MI); 1704 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1705 widenScalarDst(MI, WideTy); 1706 Observer.changedInstr(MI); 1707 return Legalized; 1708 } 1709 1710 LegalizerHelper::LegalizeResult 1711 LegalizerHelper::widenScalarAddSubOverflow(MachineInstr &MI, unsigned TypeIdx, 1712 LLT WideTy) { 1713 if (TypeIdx == 1) 1714 return UnableToLegalize; // TODO 1715 1716 unsigned Opcode; 1717 unsigned ExtOpcode; 1718 Optional<Register> CarryIn = None; 1719 switch (MI.getOpcode()) { 1720 default: 1721 llvm_unreachable("Unexpected opcode!"); 1722 case TargetOpcode::G_SADDO: 1723 Opcode = TargetOpcode::G_ADD; 1724 ExtOpcode = TargetOpcode::G_SEXT; 1725 break; 1726 case TargetOpcode::G_SSUBO: 1727 Opcode = TargetOpcode::G_SUB; 1728 ExtOpcode = TargetOpcode::G_SEXT; 1729 break; 1730 case TargetOpcode::G_UADDO: 1731 Opcode = TargetOpcode::G_ADD; 1732 ExtOpcode = TargetOpcode::G_ZEXT; 1733 break; 1734 case TargetOpcode::G_USUBO: 1735 Opcode = TargetOpcode::G_SUB; 1736 ExtOpcode = TargetOpcode::G_ZEXT; 1737 break; 1738 case TargetOpcode::G_SADDE: 1739 Opcode = TargetOpcode::G_UADDE; 1740 ExtOpcode = TargetOpcode::G_SEXT; 1741 CarryIn = MI.getOperand(4).getReg(); 1742 break; 1743 case TargetOpcode::G_SSUBE: 1744 Opcode = TargetOpcode::G_USUBE; 1745 ExtOpcode = TargetOpcode::G_SEXT; 1746 CarryIn = MI.getOperand(4).getReg(); 1747 break; 1748 case TargetOpcode::G_UADDE: 1749 Opcode = TargetOpcode::G_UADDE; 1750 ExtOpcode = TargetOpcode::G_ZEXT; 1751 CarryIn = MI.getOperand(4).getReg(); 1752 break; 1753 case TargetOpcode::G_USUBE: 1754 Opcode = TargetOpcode::G_USUBE; 1755 ExtOpcode = TargetOpcode::G_ZEXT; 1756 CarryIn = MI.getOperand(4).getReg(); 1757 break; 1758 } 1759 1760 auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)}); 1761 auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)}); 1762 // Do the arithmetic in the larger type. 1763 Register NewOp; 1764 if (CarryIn) { 1765 LLT CarryOutTy = MRI.getType(MI.getOperand(1).getReg()); 1766 NewOp = MIRBuilder 1767 .buildInstr(Opcode, {WideTy, CarryOutTy}, 1768 {LHSExt, RHSExt, *CarryIn}) 1769 .getReg(0); 1770 } else { 1771 NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt}).getReg(0); 1772 } 1773 LLT OrigTy = MRI.getType(MI.getOperand(0).getReg()); 1774 auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp); 1775 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); 1776 // There is no overflow if the ExtOp is the same as NewOp. 1777 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); 1778 // Now trunc the NewOp to the original result. 1779 MIRBuilder.buildTrunc(MI.getOperand(0), NewOp); 1780 MI.eraseFromParent(); 1781 return Legalized; 1782 } 1783 1784 LegalizerHelper::LegalizeResult 1785 LegalizerHelper::widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx, 1786 LLT WideTy) { 1787 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SADDSAT || 1788 MI.getOpcode() == TargetOpcode::G_SSUBSAT || 1789 MI.getOpcode() == TargetOpcode::G_SSHLSAT; 1790 bool IsShift = MI.getOpcode() == TargetOpcode::G_SSHLSAT || 1791 MI.getOpcode() == TargetOpcode::G_USHLSAT; 1792 // We can convert this to: 1793 // 1. Any extend iN to iM 1794 // 2. SHL by M-N 1795 // 3. [US][ADD|SUB|SHL]SAT 1796 // 4. L/ASHR by M-N 1797 // 1798 // It may be more efficient to lower this to a min and a max operation in 1799 // the higher precision arithmetic if the promoted operation isn't legal, 1800 // but this decision is up to the target's lowering request. 1801 Register DstReg = MI.getOperand(0).getReg(); 1802 1803 unsigned NewBits = WideTy.getScalarSizeInBits(); 1804 unsigned SHLAmount = NewBits - MRI.getType(DstReg).getScalarSizeInBits(); 1805 1806 // Shifts must zero-extend the RHS to preserve the unsigned quantity, and 1807 // must not left shift the RHS to preserve the shift amount. 1808 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1)); 1809 auto RHS = IsShift ? MIRBuilder.buildZExt(WideTy, MI.getOperand(2)) 1810 : MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2)); 1811 auto ShiftK = MIRBuilder.buildConstant(WideTy, SHLAmount); 1812 auto ShiftL = MIRBuilder.buildShl(WideTy, LHS, ShiftK); 1813 auto ShiftR = IsShift ? RHS : MIRBuilder.buildShl(WideTy, RHS, ShiftK); 1814 1815 auto WideInst = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, 1816 {ShiftL, ShiftR}, MI.getFlags()); 1817 1818 // Use a shift that will preserve the number of sign bits when the trunc is 1819 // folded away. 1820 auto Result = IsSigned ? MIRBuilder.buildAShr(WideTy, WideInst, ShiftK) 1821 : MIRBuilder.buildLShr(WideTy, WideInst, ShiftK); 1822 1823 MIRBuilder.buildTrunc(DstReg, Result); 1824 MI.eraseFromParent(); 1825 return Legalized; 1826 } 1827 1828 LegalizerHelper::LegalizeResult 1829 LegalizerHelper::widenScalarMulo(MachineInstr &MI, unsigned TypeIdx, 1830 LLT WideTy) { 1831 if (TypeIdx == 1) 1832 return UnableToLegalize; 1833 1834 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULO; 1835 Register Result = MI.getOperand(0).getReg(); 1836 Register OriginalOverflow = MI.getOperand(1).getReg(); 1837 Register LHS = MI.getOperand(2).getReg(); 1838 Register RHS = MI.getOperand(3).getReg(); 1839 LLT SrcTy = MRI.getType(LHS); 1840 LLT OverflowTy = MRI.getType(OriginalOverflow); 1841 unsigned SrcBitWidth = SrcTy.getScalarSizeInBits(); 1842 1843 // To determine if the result overflowed in the larger type, we extend the 1844 // input to the larger type, do the multiply (checking if it overflows), 1845 // then also check the high bits of the result to see if overflow happened 1846 // there. 1847 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 1848 auto LeftOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {LHS}); 1849 auto RightOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {RHS}); 1850 1851 auto Mulo = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy, OverflowTy}, 1852 {LeftOperand, RightOperand}); 1853 auto Mul = Mulo->getOperand(0); 1854 MIRBuilder.buildTrunc(Result, Mul); 1855 1856 MachineInstrBuilder ExtResult; 1857 // Overflow occurred if it occurred in the larger type, or if the high part 1858 // of the result does not zero/sign-extend the low part. Check this second 1859 // possibility first. 1860 if (IsSigned) { 1861 // For signed, overflow occurred when the high part does not sign-extend 1862 // the low part. 1863 ExtResult = MIRBuilder.buildSExtInReg(WideTy, Mul, SrcBitWidth); 1864 } else { 1865 // Unsigned overflow occurred when the high part does not zero-extend the 1866 // low part. 1867 ExtResult = MIRBuilder.buildZExtInReg(WideTy, Mul, SrcBitWidth); 1868 } 1869 1870 // Multiplication cannot overflow if the WideTy is >= 2 * original width, 1871 // so we don't need to check the overflow result of larger type Mulo. 1872 if (WideTy.getScalarSizeInBits() < 2 * SrcBitWidth) { 1873 auto Overflow = 1874 MIRBuilder.buildICmp(CmpInst::ICMP_NE, OverflowTy, Mul, ExtResult); 1875 // Finally check if the multiplication in the larger type itself overflowed. 1876 MIRBuilder.buildOr(OriginalOverflow, Mulo->getOperand(1), Overflow); 1877 } else { 1878 MIRBuilder.buildICmp(CmpInst::ICMP_NE, OriginalOverflow, Mul, ExtResult); 1879 } 1880 MI.eraseFromParent(); 1881 return Legalized; 1882 } 1883 1884 LegalizerHelper::LegalizeResult 1885 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { 1886 switch (MI.getOpcode()) { 1887 default: 1888 return UnableToLegalize; 1889 case TargetOpcode::G_EXTRACT: 1890 return widenScalarExtract(MI, TypeIdx, WideTy); 1891 case TargetOpcode::G_INSERT: 1892 return widenScalarInsert(MI, TypeIdx, WideTy); 1893 case TargetOpcode::G_MERGE_VALUES: 1894 return widenScalarMergeValues(MI, TypeIdx, WideTy); 1895 case TargetOpcode::G_UNMERGE_VALUES: 1896 return widenScalarUnmergeValues(MI, TypeIdx, WideTy); 1897 case TargetOpcode::G_SADDO: 1898 case TargetOpcode::G_SSUBO: 1899 case TargetOpcode::G_UADDO: 1900 case TargetOpcode::G_USUBO: 1901 case TargetOpcode::G_SADDE: 1902 case TargetOpcode::G_SSUBE: 1903 case TargetOpcode::G_UADDE: 1904 case TargetOpcode::G_USUBE: 1905 return widenScalarAddSubOverflow(MI, TypeIdx, WideTy); 1906 case TargetOpcode::G_UMULO: 1907 case TargetOpcode::G_SMULO: 1908 return widenScalarMulo(MI, TypeIdx, WideTy); 1909 case TargetOpcode::G_SADDSAT: 1910 case TargetOpcode::G_SSUBSAT: 1911 case TargetOpcode::G_SSHLSAT: 1912 case TargetOpcode::G_UADDSAT: 1913 case TargetOpcode::G_USUBSAT: 1914 case TargetOpcode::G_USHLSAT: 1915 return widenScalarAddSubShlSat(MI, TypeIdx, WideTy); 1916 case TargetOpcode::G_CTTZ: 1917 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 1918 case TargetOpcode::G_CTLZ: 1919 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 1920 case TargetOpcode::G_CTPOP: { 1921 if (TypeIdx == 0) { 1922 Observer.changingInstr(MI); 1923 widenScalarDst(MI, WideTy, 0); 1924 Observer.changedInstr(MI); 1925 return Legalized; 1926 } 1927 1928 Register SrcReg = MI.getOperand(1).getReg(); 1929 1930 // First ZEXT the input. 1931 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg); 1932 LLT CurTy = MRI.getType(SrcReg); 1933 if (MI.getOpcode() == TargetOpcode::G_CTTZ) { 1934 // The count is the same in the larger type except if the original 1935 // value was zero. This can be handled by setting the bit just off 1936 // the top of the original type. 1937 auto TopBit = 1938 APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits()); 1939 MIBSrc = MIRBuilder.buildOr( 1940 WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit)); 1941 } 1942 1943 // Perform the operation at the larger size. 1944 auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc}); 1945 // This is already the correct result for CTPOP and CTTZs 1946 if (MI.getOpcode() == TargetOpcode::G_CTLZ || 1947 MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) { 1948 // The correct result is NewOp - (Difference in widety and current ty). 1949 unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits(); 1950 MIBNewOp = MIRBuilder.buildSub( 1951 WideTy, MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)); 1952 } 1953 1954 MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp); 1955 MI.eraseFromParent(); 1956 return Legalized; 1957 } 1958 case TargetOpcode::G_BSWAP: { 1959 Observer.changingInstr(MI); 1960 Register DstReg = MI.getOperand(0).getReg(); 1961 1962 Register ShrReg = MRI.createGenericVirtualRegister(WideTy); 1963 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1964 Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy); 1965 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1966 1967 MI.getOperand(0).setReg(DstExt); 1968 1969 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1970 1971 LLT Ty = MRI.getType(DstReg); 1972 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 1973 MIRBuilder.buildConstant(ShiftAmtReg, DiffBits); 1974 MIRBuilder.buildLShr(ShrReg, DstExt, ShiftAmtReg); 1975 1976 MIRBuilder.buildTrunc(DstReg, ShrReg); 1977 Observer.changedInstr(MI); 1978 return Legalized; 1979 } 1980 case TargetOpcode::G_BITREVERSE: { 1981 Observer.changingInstr(MI); 1982 1983 Register DstReg = MI.getOperand(0).getReg(); 1984 LLT Ty = MRI.getType(DstReg); 1985 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 1986 1987 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1988 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1989 MI.getOperand(0).setReg(DstExt); 1990 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1991 1992 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); 1993 auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt); 1994 MIRBuilder.buildTrunc(DstReg, Shift); 1995 Observer.changedInstr(MI); 1996 return Legalized; 1997 } 1998 case TargetOpcode::G_FREEZE: 1999 Observer.changingInstr(MI); 2000 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2001 widenScalarDst(MI, WideTy); 2002 Observer.changedInstr(MI); 2003 return Legalized; 2004 2005 case TargetOpcode::G_ABS: 2006 Observer.changingInstr(MI); 2007 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2008 widenScalarDst(MI, WideTy); 2009 Observer.changedInstr(MI); 2010 return Legalized; 2011 2012 case TargetOpcode::G_ADD: 2013 case TargetOpcode::G_AND: 2014 case TargetOpcode::G_MUL: 2015 case TargetOpcode::G_OR: 2016 case TargetOpcode::G_XOR: 2017 case TargetOpcode::G_SUB: 2018 // Perform operation at larger width (any extension is fines here, high bits 2019 // don't affect the result) and then truncate the result back to the 2020 // original type. 2021 Observer.changingInstr(MI); 2022 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2023 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2024 widenScalarDst(MI, WideTy); 2025 Observer.changedInstr(MI); 2026 return Legalized; 2027 2028 case TargetOpcode::G_SHL: 2029 Observer.changingInstr(MI); 2030 2031 if (TypeIdx == 0) { 2032 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2033 widenScalarDst(MI, WideTy); 2034 } else { 2035 assert(TypeIdx == 1); 2036 // The "number of bits to shift" operand must preserve its value as an 2037 // unsigned integer: 2038 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2039 } 2040 2041 Observer.changedInstr(MI); 2042 return Legalized; 2043 2044 case TargetOpcode::G_SDIV: 2045 case TargetOpcode::G_SREM: 2046 case TargetOpcode::G_SMIN: 2047 case TargetOpcode::G_SMAX: 2048 Observer.changingInstr(MI); 2049 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2050 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2051 widenScalarDst(MI, WideTy); 2052 Observer.changedInstr(MI); 2053 return Legalized; 2054 2055 case TargetOpcode::G_SDIVREM: 2056 Observer.changingInstr(MI); 2057 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2058 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT); 2059 widenScalarDst(MI, WideTy); 2060 widenScalarDst(MI, WideTy, 1); 2061 Observer.changedInstr(MI); 2062 return Legalized; 2063 2064 case TargetOpcode::G_ASHR: 2065 case TargetOpcode::G_LSHR: 2066 Observer.changingInstr(MI); 2067 2068 if (TypeIdx == 0) { 2069 unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ? 2070 TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 2071 2072 widenScalarSrc(MI, WideTy, 1, CvtOp); 2073 widenScalarDst(MI, WideTy); 2074 } else { 2075 assert(TypeIdx == 1); 2076 // The "number of bits to shift" operand must preserve its value as an 2077 // unsigned integer: 2078 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2079 } 2080 2081 Observer.changedInstr(MI); 2082 return Legalized; 2083 case TargetOpcode::G_UDIV: 2084 case TargetOpcode::G_UREM: 2085 case TargetOpcode::G_UMIN: 2086 case TargetOpcode::G_UMAX: 2087 Observer.changingInstr(MI); 2088 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2089 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2090 widenScalarDst(MI, WideTy); 2091 Observer.changedInstr(MI); 2092 return Legalized; 2093 2094 case TargetOpcode::G_UDIVREM: 2095 Observer.changingInstr(MI); 2096 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2097 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ZEXT); 2098 widenScalarDst(MI, WideTy); 2099 widenScalarDst(MI, WideTy, 1); 2100 Observer.changedInstr(MI); 2101 return Legalized; 2102 2103 case TargetOpcode::G_SELECT: 2104 Observer.changingInstr(MI); 2105 if (TypeIdx == 0) { 2106 // Perform operation at larger width (any extension is fine here, high 2107 // bits don't affect the result) and then truncate the result back to the 2108 // original type. 2109 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2110 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT); 2111 widenScalarDst(MI, WideTy); 2112 } else { 2113 bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector(); 2114 // Explicit extension is required here since high bits affect the result. 2115 widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false)); 2116 } 2117 Observer.changedInstr(MI); 2118 return Legalized; 2119 2120 case TargetOpcode::G_FPTOSI: 2121 case TargetOpcode::G_FPTOUI: 2122 Observer.changingInstr(MI); 2123 2124 if (TypeIdx == 0) 2125 widenScalarDst(MI, WideTy); 2126 else 2127 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2128 2129 Observer.changedInstr(MI); 2130 return Legalized; 2131 case TargetOpcode::G_SITOFP: 2132 Observer.changingInstr(MI); 2133 2134 if (TypeIdx == 0) 2135 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2136 else 2137 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2138 2139 Observer.changedInstr(MI); 2140 return Legalized; 2141 case TargetOpcode::G_UITOFP: 2142 Observer.changingInstr(MI); 2143 2144 if (TypeIdx == 0) 2145 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2146 else 2147 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2148 2149 Observer.changedInstr(MI); 2150 return Legalized; 2151 case TargetOpcode::G_LOAD: 2152 case TargetOpcode::G_SEXTLOAD: 2153 case TargetOpcode::G_ZEXTLOAD: 2154 Observer.changingInstr(MI); 2155 widenScalarDst(MI, WideTy); 2156 Observer.changedInstr(MI); 2157 return Legalized; 2158 2159 case TargetOpcode::G_STORE: { 2160 if (TypeIdx != 0) 2161 return UnableToLegalize; 2162 2163 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 2164 if (!Ty.isScalar()) 2165 return UnableToLegalize; 2166 2167 Observer.changingInstr(MI); 2168 2169 unsigned ExtType = Ty.getScalarSizeInBits() == 1 ? 2170 TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT; 2171 widenScalarSrc(MI, WideTy, 0, ExtType); 2172 2173 Observer.changedInstr(MI); 2174 return Legalized; 2175 } 2176 case TargetOpcode::G_CONSTANT: { 2177 MachineOperand &SrcMO = MI.getOperand(1); 2178 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2179 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( 2180 MRI.getType(MI.getOperand(0).getReg())); 2181 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || 2182 ExtOpc == TargetOpcode::G_ANYEXT) && 2183 "Illegal Extend"); 2184 const APInt &SrcVal = SrcMO.getCImm()->getValue(); 2185 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) 2186 ? SrcVal.sext(WideTy.getSizeInBits()) 2187 : SrcVal.zext(WideTy.getSizeInBits()); 2188 Observer.changingInstr(MI); 2189 SrcMO.setCImm(ConstantInt::get(Ctx, Val)); 2190 2191 widenScalarDst(MI, WideTy); 2192 Observer.changedInstr(MI); 2193 return Legalized; 2194 } 2195 case TargetOpcode::G_FCONSTANT: { 2196 MachineOperand &SrcMO = MI.getOperand(1); 2197 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2198 APFloat Val = SrcMO.getFPImm()->getValueAPF(); 2199 bool LosesInfo; 2200 switch (WideTy.getSizeInBits()) { 2201 case 32: 2202 Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, 2203 &LosesInfo); 2204 break; 2205 case 64: 2206 Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 2207 &LosesInfo); 2208 break; 2209 default: 2210 return UnableToLegalize; 2211 } 2212 2213 assert(!LosesInfo && "extend should always be lossless"); 2214 2215 Observer.changingInstr(MI); 2216 SrcMO.setFPImm(ConstantFP::get(Ctx, Val)); 2217 2218 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2219 Observer.changedInstr(MI); 2220 return Legalized; 2221 } 2222 case TargetOpcode::G_IMPLICIT_DEF: { 2223 Observer.changingInstr(MI); 2224 widenScalarDst(MI, WideTy); 2225 Observer.changedInstr(MI); 2226 return Legalized; 2227 } 2228 case TargetOpcode::G_BRCOND: 2229 Observer.changingInstr(MI); 2230 widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false)); 2231 Observer.changedInstr(MI); 2232 return Legalized; 2233 2234 case TargetOpcode::G_FCMP: 2235 Observer.changingInstr(MI); 2236 if (TypeIdx == 0) 2237 widenScalarDst(MI, WideTy); 2238 else { 2239 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT); 2240 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT); 2241 } 2242 Observer.changedInstr(MI); 2243 return Legalized; 2244 2245 case TargetOpcode::G_ICMP: 2246 Observer.changingInstr(MI); 2247 if (TypeIdx == 0) 2248 widenScalarDst(MI, WideTy); 2249 else { 2250 unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>( 2251 MI.getOperand(1).getPredicate())) 2252 ? TargetOpcode::G_SEXT 2253 : TargetOpcode::G_ZEXT; 2254 widenScalarSrc(MI, WideTy, 2, ExtOpcode); 2255 widenScalarSrc(MI, WideTy, 3, ExtOpcode); 2256 } 2257 Observer.changedInstr(MI); 2258 return Legalized; 2259 2260 case TargetOpcode::G_PTR_ADD: 2261 assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD"); 2262 Observer.changingInstr(MI); 2263 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2264 Observer.changedInstr(MI); 2265 return Legalized; 2266 2267 case TargetOpcode::G_PHI: { 2268 assert(TypeIdx == 0 && "Expecting only Idx 0"); 2269 2270 Observer.changingInstr(MI); 2271 for (unsigned I = 1; I < MI.getNumOperands(); I += 2) { 2272 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 2273 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 2274 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT); 2275 } 2276 2277 MachineBasicBlock &MBB = *MI.getParent(); 2278 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 2279 widenScalarDst(MI, WideTy); 2280 Observer.changedInstr(MI); 2281 return Legalized; 2282 } 2283 case TargetOpcode::G_EXTRACT_VECTOR_ELT: { 2284 if (TypeIdx == 0) { 2285 Register VecReg = MI.getOperand(1).getReg(); 2286 LLT VecTy = MRI.getType(VecReg); 2287 Observer.changingInstr(MI); 2288 2289 widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(), 2290 WideTy.getSizeInBits()), 2291 1, TargetOpcode::G_SEXT); 2292 2293 widenScalarDst(MI, WideTy, 0); 2294 Observer.changedInstr(MI); 2295 return Legalized; 2296 } 2297 2298 if (TypeIdx != 2) 2299 return UnableToLegalize; 2300 Observer.changingInstr(MI); 2301 // TODO: Probably should be zext 2302 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2303 Observer.changedInstr(MI); 2304 return Legalized; 2305 } 2306 case TargetOpcode::G_INSERT_VECTOR_ELT: { 2307 if (TypeIdx == 1) { 2308 Observer.changingInstr(MI); 2309 2310 Register VecReg = MI.getOperand(1).getReg(); 2311 LLT VecTy = MRI.getType(VecReg); 2312 LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy); 2313 2314 widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT); 2315 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2316 widenScalarDst(MI, WideVecTy, 0); 2317 Observer.changedInstr(MI); 2318 return Legalized; 2319 } 2320 2321 if (TypeIdx == 2) { 2322 Observer.changingInstr(MI); 2323 // TODO: Probably should be zext 2324 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT); 2325 Observer.changedInstr(MI); 2326 return Legalized; 2327 } 2328 2329 return UnableToLegalize; 2330 } 2331 case TargetOpcode::G_FADD: 2332 case TargetOpcode::G_FMUL: 2333 case TargetOpcode::G_FSUB: 2334 case TargetOpcode::G_FMA: 2335 case TargetOpcode::G_FMAD: 2336 case TargetOpcode::G_FNEG: 2337 case TargetOpcode::G_FABS: 2338 case TargetOpcode::G_FCANONICALIZE: 2339 case TargetOpcode::G_FMINNUM: 2340 case TargetOpcode::G_FMAXNUM: 2341 case TargetOpcode::G_FMINNUM_IEEE: 2342 case TargetOpcode::G_FMAXNUM_IEEE: 2343 case TargetOpcode::G_FMINIMUM: 2344 case TargetOpcode::G_FMAXIMUM: 2345 case TargetOpcode::G_FDIV: 2346 case TargetOpcode::G_FREM: 2347 case TargetOpcode::G_FCEIL: 2348 case TargetOpcode::G_FFLOOR: 2349 case TargetOpcode::G_FCOS: 2350 case TargetOpcode::G_FSIN: 2351 case TargetOpcode::G_FLOG10: 2352 case TargetOpcode::G_FLOG: 2353 case TargetOpcode::G_FLOG2: 2354 case TargetOpcode::G_FRINT: 2355 case TargetOpcode::G_FNEARBYINT: 2356 case TargetOpcode::G_FSQRT: 2357 case TargetOpcode::G_FEXP: 2358 case TargetOpcode::G_FEXP2: 2359 case TargetOpcode::G_FPOW: 2360 case TargetOpcode::G_INTRINSIC_TRUNC: 2361 case TargetOpcode::G_INTRINSIC_ROUND: 2362 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 2363 assert(TypeIdx == 0); 2364 Observer.changingInstr(MI); 2365 2366 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 2367 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT); 2368 2369 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2370 Observer.changedInstr(MI); 2371 return Legalized; 2372 case TargetOpcode::G_FPOWI: { 2373 if (TypeIdx != 0) 2374 return UnableToLegalize; 2375 Observer.changingInstr(MI); 2376 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2377 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2378 Observer.changedInstr(MI); 2379 return Legalized; 2380 } 2381 case TargetOpcode::G_INTTOPTR: 2382 if (TypeIdx != 1) 2383 return UnableToLegalize; 2384 2385 Observer.changingInstr(MI); 2386 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2387 Observer.changedInstr(MI); 2388 return Legalized; 2389 case TargetOpcode::G_PTRTOINT: 2390 if (TypeIdx != 0) 2391 return UnableToLegalize; 2392 2393 Observer.changingInstr(MI); 2394 widenScalarDst(MI, WideTy, 0); 2395 Observer.changedInstr(MI); 2396 return Legalized; 2397 case TargetOpcode::G_BUILD_VECTOR: { 2398 Observer.changingInstr(MI); 2399 2400 const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType(); 2401 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) 2402 widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT); 2403 2404 // Avoid changing the result vector type if the source element type was 2405 // requested. 2406 if (TypeIdx == 1) { 2407 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); 2408 } else { 2409 widenScalarDst(MI, WideTy, 0); 2410 } 2411 2412 Observer.changedInstr(MI); 2413 return Legalized; 2414 } 2415 case TargetOpcode::G_SEXT_INREG: 2416 if (TypeIdx != 0) 2417 return UnableToLegalize; 2418 2419 Observer.changingInstr(MI); 2420 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2421 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC); 2422 Observer.changedInstr(MI); 2423 return Legalized; 2424 case TargetOpcode::G_PTRMASK: { 2425 if (TypeIdx != 1) 2426 return UnableToLegalize; 2427 Observer.changingInstr(MI); 2428 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2429 Observer.changedInstr(MI); 2430 return Legalized; 2431 } 2432 } 2433 } 2434 2435 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces, 2436 MachineIRBuilder &B, Register Src, LLT Ty) { 2437 auto Unmerge = B.buildUnmerge(Ty, Src); 2438 for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I) 2439 Pieces.push_back(Unmerge.getReg(I)); 2440 } 2441 2442 LegalizerHelper::LegalizeResult 2443 LegalizerHelper::lowerBitcast(MachineInstr &MI) { 2444 Register Dst = MI.getOperand(0).getReg(); 2445 Register Src = MI.getOperand(1).getReg(); 2446 LLT DstTy = MRI.getType(Dst); 2447 LLT SrcTy = MRI.getType(Src); 2448 2449 if (SrcTy.isVector()) { 2450 LLT SrcEltTy = SrcTy.getElementType(); 2451 SmallVector<Register, 8> SrcRegs; 2452 2453 if (DstTy.isVector()) { 2454 int NumDstElt = DstTy.getNumElements(); 2455 int NumSrcElt = SrcTy.getNumElements(); 2456 2457 LLT DstEltTy = DstTy.getElementType(); 2458 LLT DstCastTy = DstEltTy; // Intermediate bitcast result type 2459 LLT SrcPartTy = SrcEltTy; // Original unmerge result type. 2460 2461 // If there's an element size mismatch, insert intermediate casts to match 2462 // the result element type. 2463 if (NumSrcElt < NumDstElt) { // Source element type is larger. 2464 // %1:_(<4 x s8>) = G_BITCAST %0:_(<2 x s16>) 2465 // 2466 // => 2467 // 2468 // %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0 2469 // %3:_(<2 x s8>) = G_BITCAST %2 2470 // %4:_(<2 x s8>) = G_BITCAST %3 2471 // %1:_(<4 x s16>) = G_CONCAT_VECTORS %3, %4 2472 DstCastTy = LLT::vector(NumDstElt / NumSrcElt, DstEltTy); 2473 SrcPartTy = SrcEltTy; 2474 } else if (NumSrcElt > NumDstElt) { // Source element type is smaller. 2475 // 2476 // %1:_(<2 x s16>) = G_BITCAST %0:_(<4 x s8>) 2477 // 2478 // => 2479 // 2480 // %2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %0 2481 // %3:_(s16) = G_BITCAST %2 2482 // %4:_(s16) = G_BITCAST %3 2483 // %1:_(<2 x s16>) = G_BUILD_VECTOR %3, %4 2484 SrcPartTy = LLT::vector(NumSrcElt / NumDstElt, SrcEltTy); 2485 DstCastTy = DstEltTy; 2486 } 2487 2488 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcPartTy); 2489 for (Register &SrcReg : SrcRegs) 2490 SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); 2491 } else 2492 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcEltTy); 2493 2494 MIRBuilder.buildMerge(Dst, SrcRegs); 2495 MI.eraseFromParent(); 2496 return Legalized; 2497 } 2498 2499 if (DstTy.isVector()) { 2500 SmallVector<Register, 8> SrcRegs; 2501 getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType()); 2502 MIRBuilder.buildMerge(Dst, SrcRegs); 2503 MI.eraseFromParent(); 2504 return Legalized; 2505 } 2506 2507 return UnableToLegalize; 2508 } 2509 2510 /// Figure out the bit offset into a register when coercing a vector index for 2511 /// the wide element type. This is only for the case when promoting vector to 2512 /// one with larger elements. 2513 // 2514 /// 2515 /// %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2516 /// %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2517 static Register getBitcastWiderVectorElementOffset(MachineIRBuilder &B, 2518 Register Idx, 2519 unsigned NewEltSize, 2520 unsigned OldEltSize) { 2521 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2522 LLT IdxTy = B.getMRI()->getType(Idx); 2523 2524 // Now figure out the amount we need to shift to get the target bits. 2525 auto OffsetMask = B.buildConstant( 2526 IdxTy, ~(APInt::getAllOnesValue(IdxTy.getSizeInBits()) << Log2EltRatio)); 2527 auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask); 2528 return B.buildShl(IdxTy, OffsetIdx, 2529 B.buildConstant(IdxTy, Log2_32(OldEltSize))).getReg(0); 2530 } 2531 2532 /// Perform a G_EXTRACT_VECTOR_ELT in a different sized vector element. If this 2533 /// is casting to a vector with a smaller element size, perform multiple element 2534 /// extracts and merge the results. If this is coercing to a vector with larger 2535 /// elements, index the bitcasted vector and extract the target element with bit 2536 /// operations. This is intended to force the indexing in the native register 2537 /// size for architectures that can dynamically index the register file. 2538 LegalizerHelper::LegalizeResult 2539 LegalizerHelper::bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx, 2540 LLT CastTy) { 2541 if (TypeIdx != 1) 2542 return UnableToLegalize; 2543 2544 Register Dst = MI.getOperand(0).getReg(); 2545 Register SrcVec = MI.getOperand(1).getReg(); 2546 Register Idx = MI.getOperand(2).getReg(); 2547 LLT SrcVecTy = MRI.getType(SrcVec); 2548 LLT IdxTy = MRI.getType(Idx); 2549 2550 LLT SrcEltTy = SrcVecTy.getElementType(); 2551 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2552 unsigned OldNumElts = SrcVecTy.getNumElements(); 2553 2554 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2555 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2556 2557 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2558 const unsigned OldEltSize = SrcEltTy.getSizeInBits(); 2559 if (NewNumElts > OldNumElts) { 2560 // Decreasing the vector element size 2561 // 2562 // e.g. i64 = extract_vector_elt x:v2i64, y:i32 2563 // => 2564 // v4i32:castx = bitcast x:v2i64 2565 // 2566 // i64 = bitcast 2567 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))), 2568 // (i32 (extract_vector_elt castx, (2 * y + 1))) 2569 // 2570 if (NewNumElts % OldNumElts != 0) 2571 return UnableToLegalize; 2572 2573 // Type of the intermediate result vector. 2574 const unsigned NewEltsPerOldElt = NewNumElts / OldNumElts; 2575 LLT MidTy = LLT::scalarOrVector(NewEltsPerOldElt, NewEltTy); 2576 2577 auto NewEltsPerOldEltK = MIRBuilder.buildConstant(IdxTy, NewEltsPerOldElt); 2578 2579 SmallVector<Register, 8> NewOps(NewEltsPerOldElt); 2580 auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, Idx, NewEltsPerOldEltK); 2581 2582 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) { 2583 auto IdxOffset = MIRBuilder.buildConstant(IdxTy, I); 2584 auto TmpIdx = MIRBuilder.buildAdd(IdxTy, NewBaseIdx, IdxOffset); 2585 auto Elt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, TmpIdx); 2586 NewOps[I] = Elt.getReg(0); 2587 } 2588 2589 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); 2590 MIRBuilder.buildBitcast(Dst, NewVec); 2591 MI.eraseFromParent(); 2592 return Legalized; 2593 } 2594 2595 if (NewNumElts < OldNumElts) { 2596 if (NewEltSize % OldEltSize != 0) 2597 return UnableToLegalize; 2598 2599 // This only depends on powers of 2 because we use bit tricks to figure out 2600 // the bit offset we need to shift to get the target element. A general 2601 // expansion could emit division/multiply. 2602 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2603 return UnableToLegalize; 2604 2605 // Increasing the vector element size. 2606 // %elt:_(small_elt) = G_EXTRACT_VECTOR_ELT %vec:_(<N x small_elt>), %idx 2607 // 2608 // => 2609 // 2610 // %cast = G_BITCAST %vec 2611 // %scaled_idx = G_LSHR %idx, Log2(DstEltSize / SrcEltSize) 2612 // %wide_elt = G_EXTRACT_VECTOR_ELT %cast, %scaled_idx 2613 // %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2614 // %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2615 // %elt_bits = G_LSHR %wide_elt, %offset_bits 2616 // %elt = G_TRUNC %elt_bits 2617 2618 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2619 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2620 2621 // Divide to get the index in the wider element type. 2622 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2623 2624 Register WideElt = CastVec; 2625 if (CastTy.isVector()) { 2626 WideElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2627 ScaledIdx).getReg(0); 2628 } 2629 2630 // Compute the bit offset into the register of the target element. 2631 Register OffsetBits = getBitcastWiderVectorElementOffset( 2632 MIRBuilder, Idx, NewEltSize, OldEltSize); 2633 2634 // Shift the wide element to get the target element. 2635 auto ExtractedBits = MIRBuilder.buildLShr(NewEltTy, WideElt, OffsetBits); 2636 MIRBuilder.buildTrunc(Dst, ExtractedBits); 2637 MI.eraseFromParent(); 2638 return Legalized; 2639 } 2640 2641 return UnableToLegalize; 2642 } 2643 2644 /// Emit code to insert \p InsertReg into \p TargetRet at \p OffsetBits in \p 2645 /// TargetReg, while preserving other bits in \p TargetReg. 2646 /// 2647 /// (InsertReg << Offset) | (TargetReg & ~(-1 >> InsertReg.size()) << Offset) 2648 static Register buildBitFieldInsert(MachineIRBuilder &B, 2649 Register TargetReg, Register InsertReg, 2650 Register OffsetBits) { 2651 LLT TargetTy = B.getMRI()->getType(TargetReg); 2652 LLT InsertTy = B.getMRI()->getType(InsertReg); 2653 auto ZextVal = B.buildZExt(TargetTy, InsertReg); 2654 auto ShiftedInsertVal = B.buildShl(TargetTy, ZextVal, OffsetBits); 2655 2656 // Produce a bitmask of the value to insert 2657 auto EltMask = B.buildConstant( 2658 TargetTy, APInt::getLowBitsSet(TargetTy.getSizeInBits(), 2659 InsertTy.getSizeInBits())); 2660 // Shift it into position 2661 auto ShiftedMask = B.buildShl(TargetTy, EltMask, OffsetBits); 2662 auto InvShiftedMask = B.buildNot(TargetTy, ShiftedMask); 2663 2664 // Clear out the bits in the wide element 2665 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); 2666 2667 // The value to insert has all zeros already, so stick it into the masked 2668 // wide element. 2669 return B.buildOr(TargetTy, MaskedOldElt, ShiftedInsertVal).getReg(0); 2670 } 2671 2672 /// Perform a G_INSERT_VECTOR_ELT in a different sized vector element. If this 2673 /// is increasing the element size, perform the indexing in the target element 2674 /// type, and use bit operations to insert at the element position. This is 2675 /// intended for architectures that can dynamically index the register file and 2676 /// want to force indexing in the native register size. 2677 LegalizerHelper::LegalizeResult 2678 LegalizerHelper::bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, 2679 LLT CastTy) { 2680 if (TypeIdx != 0) 2681 return UnableToLegalize; 2682 2683 Register Dst = MI.getOperand(0).getReg(); 2684 Register SrcVec = MI.getOperand(1).getReg(); 2685 Register Val = MI.getOperand(2).getReg(); 2686 Register Idx = MI.getOperand(3).getReg(); 2687 2688 LLT VecTy = MRI.getType(Dst); 2689 LLT IdxTy = MRI.getType(Idx); 2690 2691 LLT VecEltTy = VecTy.getElementType(); 2692 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2693 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2694 const unsigned OldEltSize = VecEltTy.getSizeInBits(); 2695 2696 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2697 unsigned OldNumElts = VecTy.getNumElements(); 2698 2699 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2700 if (NewNumElts < OldNumElts) { 2701 if (NewEltSize % OldEltSize != 0) 2702 return UnableToLegalize; 2703 2704 // This only depends on powers of 2 because we use bit tricks to figure out 2705 // the bit offset we need to shift to get the target element. A general 2706 // expansion could emit division/multiply. 2707 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2708 return UnableToLegalize; 2709 2710 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2711 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2712 2713 // Divide to get the index in the wider element type. 2714 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2715 2716 Register ExtractedElt = CastVec; 2717 if (CastTy.isVector()) { 2718 ExtractedElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2719 ScaledIdx).getReg(0); 2720 } 2721 2722 // Compute the bit offset into the register of the target element. 2723 Register OffsetBits = getBitcastWiderVectorElementOffset( 2724 MIRBuilder, Idx, NewEltSize, OldEltSize); 2725 2726 Register InsertedElt = buildBitFieldInsert(MIRBuilder, ExtractedElt, 2727 Val, OffsetBits); 2728 if (CastTy.isVector()) { 2729 InsertedElt = MIRBuilder.buildInsertVectorElement( 2730 CastTy, CastVec, InsertedElt, ScaledIdx).getReg(0); 2731 } 2732 2733 MIRBuilder.buildBitcast(Dst, InsertedElt); 2734 MI.eraseFromParent(); 2735 return Legalized; 2736 } 2737 2738 return UnableToLegalize; 2739 } 2740 2741 LegalizerHelper::LegalizeResult 2742 LegalizerHelper::lowerLoad(MachineInstr &MI) { 2743 // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT 2744 Register DstReg = MI.getOperand(0).getReg(); 2745 Register PtrReg = MI.getOperand(1).getReg(); 2746 LLT DstTy = MRI.getType(DstReg); 2747 auto &MMO = **MI.memoperands_begin(); 2748 2749 if (DstTy.getSizeInBits() == MMO.getSizeInBits()) { 2750 if (MI.getOpcode() == TargetOpcode::G_LOAD) { 2751 // This load needs splitting into power of 2 sized loads. 2752 if (DstTy.isVector()) 2753 return UnableToLegalize; 2754 if (isPowerOf2_32(DstTy.getSizeInBits())) 2755 return UnableToLegalize; // Don't know what we're being asked to do. 2756 2757 // Our strategy here is to generate anyextending loads for the smaller 2758 // types up to next power-2 result type, and then combine the two larger 2759 // result values together, before truncating back down to the non-pow-2 2760 // type. 2761 // E.g. v1 = i24 load => 2762 // v2 = i32 zextload (2 byte) 2763 // v3 = i32 load (1 byte) 2764 // v4 = i32 shl v3, 16 2765 // v5 = i32 or v4, v2 2766 // v1 = i24 trunc v5 2767 // By doing this we generate the correct truncate which should get 2768 // combined away as an artifact with a matching extend. 2769 uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits()); 2770 uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize; 2771 2772 MachineFunction &MF = MIRBuilder.getMF(); 2773 MachineMemOperand *LargeMMO = 2774 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2775 MachineMemOperand *SmallMMO = MF.getMachineMemOperand( 2776 &MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2777 2778 LLT PtrTy = MRI.getType(PtrReg); 2779 unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits()); 2780 LLT AnyExtTy = LLT::scalar(AnyExtSize); 2781 auto LargeLoad = MIRBuilder.buildLoadInstr( 2782 TargetOpcode::G_ZEXTLOAD, AnyExtTy, PtrReg, *LargeMMO); 2783 2784 auto OffsetCst = MIRBuilder.buildConstant( 2785 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2786 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2787 auto SmallPtr = 2788 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); 2789 auto SmallLoad = MIRBuilder.buildLoad(AnyExtTy, SmallPtr, 2790 *SmallMMO); 2791 2792 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize); 2793 auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt); 2794 auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad); 2795 MIRBuilder.buildTrunc(DstReg, {Or}); 2796 MI.eraseFromParent(); 2797 return Legalized; 2798 } 2799 2800 MIRBuilder.buildLoad(DstReg, PtrReg, MMO); 2801 MI.eraseFromParent(); 2802 return Legalized; 2803 } 2804 2805 return UnableToLegalize; 2806 } 2807 2808 LegalizerHelper::LegalizeResult 2809 LegalizerHelper::lowerStore(MachineInstr &MI) { 2810 // Lower a non-power of 2 store into multiple pow-2 stores. 2811 // E.g. split an i24 store into an i16 store + i8 store. 2812 // We do this by first extending the stored value to the next largest power 2813 // of 2 type, and then using truncating stores to store the components. 2814 // By doing this, likewise with G_LOAD, generate an extend that can be 2815 // artifact-combined away instead of leaving behind extracts. 2816 Register SrcReg = MI.getOperand(0).getReg(); 2817 Register PtrReg = MI.getOperand(1).getReg(); 2818 LLT SrcTy = MRI.getType(SrcReg); 2819 MachineMemOperand &MMO = **MI.memoperands_begin(); 2820 if (SrcTy.getSizeInBits() != MMO.getSizeInBits()) 2821 return UnableToLegalize; 2822 if (SrcTy.isVector()) 2823 return UnableToLegalize; 2824 if (isPowerOf2_32(SrcTy.getSizeInBits())) 2825 return UnableToLegalize; // Don't know what we're being asked to do. 2826 2827 // Extend to the next pow-2. 2828 const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits())); 2829 auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg); 2830 2831 // Obtain the smaller value by shifting away the larger value. 2832 uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits()); 2833 uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize; 2834 auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize); 2835 auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt); 2836 2837 // Generate the PtrAdd and truncating stores. 2838 LLT PtrTy = MRI.getType(PtrReg); 2839 auto OffsetCst = MIRBuilder.buildConstant( 2840 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2841 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2842 auto SmallPtr = 2843 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); 2844 2845 MachineFunction &MF = MIRBuilder.getMF(); 2846 MachineMemOperand *LargeMMO = 2847 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2848 MachineMemOperand *SmallMMO = 2849 MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2850 MIRBuilder.buildStore(ExtVal, PtrReg, *LargeMMO); 2851 MIRBuilder.buildStore(SmallVal, SmallPtr, *SmallMMO); 2852 MI.eraseFromParent(); 2853 return Legalized; 2854 } 2855 2856 LegalizerHelper::LegalizeResult 2857 LegalizerHelper::bitcast(MachineInstr &MI, unsigned TypeIdx, LLT CastTy) { 2858 switch (MI.getOpcode()) { 2859 case TargetOpcode::G_LOAD: { 2860 if (TypeIdx != 0) 2861 return UnableToLegalize; 2862 2863 Observer.changingInstr(MI); 2864 bitcastDst(MI, CastTy, 0); 2865 Observer.changedInstr(MI); 2866 return Legalized; 2867 } 2868 case TargetOpcode::G_STORE: { 2869 if (TypeIdx != 0) 2870 return UnableToLegalize; 2871 2872 Observer.changingInstr(MI); 2873 bitcastSrc(MI, CastTy, 0); 2874 Observer.changedInstr(MI); 2875 return Legalized; 2876 } 2877 case TargetOpcode::G_SELECT: { 2878 if (TypeIdx != 0) 2879 return UnableToLegalize; 2880 2881 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) { 2882 LLVM_DEBUG( 2883 dbgs() << "bitcast action not implemented for vector select\n"); 2884 return UnableToLegalize; 2885 } 2886 2887 Observer.changingInstr(MI); 2888 bitcastSrc(MI, CastTy, 2); 2889 bitcastSrc(MI, CastTy, 3); 2890 bitcastDst(MI, CastTy, 0); 2891 Observer.changedInstr(MI); 2892 return Legalized; 2893 } 2894 case TargetOpcode::G_AND: 2895 case TargetOpcode::G_OR: 2896 case TargetOpcode::G_XOR: { 2897 Observer.changingInstr(MI); 2898 bitcastSrc(MI, CastTy, 1); 2899 bitcastSrc(MI, CastTy, 2); 2900 bitcastDst(MI, CastTy, 0); 2901 Observer.changedInstr(MI); 2902 return Legalized; 2903 } 2904 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 2905 return bitcastExtractVectorElt(MI, TypeIdx, CastTy); 2906 case TargetOpcode::G_INSERT_VECTOR_ELT: 2907 return bitcastInsertVectorElt(MI, TypeIdx, CastTy); 2908 default: 2909 return UnableToLegalize; 2910 } 2911 } 2912 2913 // Legalize an instruction by changing the opcode in place. 2914 void LegalizerHelper::changeOpcode(MachineInstr &MI, unsigned NewOpcode) { 2915 Observer.changingInstr(MI); 2916 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); 2917 Observer.changedInstr(MI); 2918 } 2919 2920 LegalizerHelper::LegalizeResult 2921 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) { 2922 using namespace TargetOpcode; 2923 2924 switch(MI.getOpcode()) { 2925 default: 2926 return UnableToLegalize; 2927 case TargetOpcode::G_BITCAST: 2928 return lowerBitcast(MI); 2929 case TargetOpcode::G_SREM: 2930 case TargetOpcode::G_UREM: { 2931 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 2932 auto Quot = 2933 MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {Ty}, 2934 {MI.getOperand(1), MI.getOperand(2)}); 2935 2936 auto Prod = MIRBuilder.buildMul(Ty, Quot, MI.getOperand(2)); 2937 MIRBuilder.buildSub(MI.getOperand(0), MI.getOperand(1), Prod); 2938 MI.eraseFromParent(); 2939 return Legalized; 2940 } 2941 case TargetOpcode::G_SADDO: 2942 case TargetOpcode::G_SSUBO: 2943 return lowerSADDO_SSUBO(MI); 2944 case TargetOpcode::G_UMULH: 2945 case TargetOpcode::G_SMULH: 2946 return lowerSMULH_UMULH(MI); 2947 case TargetOpcode::G_SMULO: 2948 case TargetOpcode::G_UMULO: { 2949 // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the 2950 // result. 2951 Register Res = MI.getOperand(0).getReg(); 2952 Register Overflow = MI.getOperand(1).getReg(); 2953 Register LHS = MI.getOperand(2).getReg(); 2954 Register RHS = MI.getOperand(3).getReg(); 2955 LLT Ty = MRI.getType(Res); 2956 2957 unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO 2958 ? TargetOpcode::G_SMULH 2959 : TargetOpcode::G_UMULH; 2960 2961 Observer.changingInstr(MI); 2962 const auto &TII = MIRBuilder.getTII(); 2963 MI.setDesc(TII.get(TargetOpcode::G_MUL)); 2964 MI.RemoveOperand(1); 2965 Observer.changedInstr(MI); 2966 2967 auto HiPart = MIRBuilder.buildInstr(Opcode, {Ty}, {LHS, RHS}); 2968 auto Zero = MIRBuilder.buildConstant(Ty, 0); 2969 2970 // Move insert point forward so we can use the Res register if needed. 2971 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 2972 2973 // For *signed* multiply, overflow is detected by checking: 2974 // (hi != (lo >> bitwidth-1)) 2975 if (Opcode == TargetOpcode::G_SMULH) { 2976 auto ShiftAmt = MIRBuilder.buildConstant(Ty, Ty.getSizeInBits() - 1); 2977 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); 2978 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted); 2979 } else { 2980 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero); 2981 } 2982 return Legalized; 2983 } 2984 case TargetOpcode::G_FNEG: { 2985 Register Res = MI.getOperand(0).getReg(); 2986 LLT Ty = MRI.getType(Res); 2987 2988 // TODO: Handle vector types once we are able to 2989 // represent them. 2990 if (Ty.isVector()) 2991 return UnableToLegalize; 2992 auto SignMask = 2993 MIRBuilder.buildConstant(Ty, APInt::getSignMask(Ty.getSizeInBits())); 2994 Register SubByReg = MI.getOperand(1).getReg(); 2995 MIRBuilder.buildXor(Res, SubByReg, SignMask); 2996 MI.eraseFromParent(); 2997 return Legalized; 2998 } 2999 case TargetOpcode::G_FSUB: { 3000 Register Res = MI.getOperand(0).getReg(); 3001 LLT Ty = MRI.getType(Res); 3002 3003 // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)). 3004 // First, check if G_FNEG is marked as Lower. If so, we may 3005 // end up with an infinite loop as G_FSUB is used to legalize G_FNEG. 3006 if (LI.getAction({G_FNEG, {Ty}}).Action == Lower) 3007 return UnableToLegalize; 3008 Register LHS = MI.getOperand(1).getReg(); 3009 Register RHS = MI.getOperand(2).getReg(); 3010 Register Neg = MRI.createGenericVirtualRegister(Ty); 3011 MIRBuilder.buildFNeg(Neg, RHS); 3012 MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags()); 3013 MI.eraseFromParent(); 3014 return Legalized; 3015 } 3016 case TargetOpcode::G_FMAD: 3017 return lowerFMad(MI); 3018 case TargetOpcode::G_FFLOOR: 3019 return lowerFFloor(MI); 3020 case TargetOpcode::G_INTRINSIC_ROUND: 3021 return lowerIntrinsicRound(MI); 3022 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 3023 // Since round even is the assumed rounding mode for unconstrained FP 3024 // operations, rint and roundeven are the same operation. 3025 changeOpcode(MI, TargetOpcode::G_FRINT); 3026 return Legalized; 3027 } 3028 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: { 3029 Register OldValRes = MI.getOperand(0).getReg(); 3030 Register SuccessRes = MI.getOperand(1).getReg(); 3031 Register Addr = MI.getOperand(2).getReg(); 3032 Register CmpVal = MI.getOperand(3).getReg(); 3033 Register NewVal = MI.getOperand(4).getReg(); 3034 MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal, 3035 **MI.memoperands_begin()); 3036 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal); 3037 MI.eraseFromParent(); 3038 return Legalized; 3039 } 3040 case TargetOpcode::G_LOAD: 3041 case TargetOpcode::G_SEXTLOAD: 3042 case TargetOpcode::G_ZEXTLOAD: 3043 return lowerLoad(MI); 3044 case TargetOpcode::G_STORE: 3045 return lowerStore(MI); 3046 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 3047 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 3048 case TargetOpcode::G_CTLZ: 3049 case TargetOpcode::G_CTTZ: 3050 case TargetOpcode::G_CTPOP: 3051 return lowerBitCount(MI); 3052 case G_UADDO: { 3053 Register Res = MI.getOperand(0).getReg(); 3054 Register CarryOut = MI.getOperand(1).getReg(); 3055 Register LHS = MI.getOperand(2).getReg(); 3056 Register RHS = MI.getOperand(3).getReg(); 3057 3058 MIRBuilder.buildAdd(Res, LHS, RHS); 3059 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS); 3060 3061 MI.eraseFromParent(); 3062 return Legalized; 3063 } 3064 case G_UADDE: { 3065 Register Res = MI.getOperand(0).getReg(); 3066 Register CarryOut = MI.getOperand(1).getReg(); 3067 Register LHS = MI.getOperand(2).getReg(); 3068 Register RHS = MI.getOperand(3).getReg(); 3069 Register CarryIn = MI.getOperand(4).getReg(); 3070 LLT Ty = MRI.getType(Res); 3071 3072 auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS); 3073 auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); 3074 MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn); 3075 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS); 3076 3077 MI.eraseFromParent(); 3078 return Legalized; 3079 } 3080 case G_USUBO: { 3081 Register Res = MI.getOperand(0).getReg(); 3082 Register BorrowOut = MI.getOperand(1).getReg(); 3083 Register LHS = MI.getOperand(2).getReg(); 3084 Register RHS = MI.getOperand(3).getReg(); 3085 3086 MIRBuilder.buildSub(Res, LHS, RHS); 3087 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS); 3088 3089 MI.eraseFromParent(); 3090 return Legalized; 3091 } 3092 case G_USUBE: { 3093 Register Res = MI.getOperand(0).getReg(); 3094 Register BorrowOut = MI.getOperand(1).getReg(); 3095 Register LHS = MI.getOperand(2).getReg(); 3096 Register RHS = MI.getOperand(3).getReg(); 3097 Register BorrowIn = MI.getOperand(4).getReg(); 3098 const LLT CondTy = MRI.getType(BorrowOut); 3099 const LLT Ty = MRI.getType(Res); 3100 3101 auto TmpRes = MIRBuilder.buildSub(Ty, LHS, RHS); 3102 auto ZExtBorrowIn = MIRBuilder.buildZExt(Ty, BorrowIn); 3103 MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn); 3104 3105 auto LHS_EQ_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, LHS, RHS); 3106 auto LHS_ULT_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, LHS, RHS); 3107 MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS); 3108 3109 MI.eraseFromParent(); 3110 return Legalized; 3111 } 3112 case G_UITOFP: 3113 return lowerUITOFP(MI); 3114 case G_SITOFP: 3115 return lowerSITOFP(MI); 3116 case G_FPTOUI: 3117 return lowerFPTOUI(MI); 3118 case G_FPTOSI: 3119 return lowerFPTOSI(MI); 3120 case G_FPTRUNC: 3121 return lowerFPTRUNC(MI); 3122 case G_FPOWI: 3123 return lowerFPOWI(MI); 3124 case G_SMIN: 3125 case G_SMAX: 3126 case G_UMIN: 3127 case G_UMAX: 3128 return lowerMinMax(MI); 3129 case G_FCOPYSIGN: 3130 return lowerFCopySign(MI); 3131 case G_FMINNUM: 3132 case G_FMAXNUM: 3133 return lowerFMinNumMaxNum(MI); 3134 case G_MERGE_VALUES: 3135 return lowerMergeValues(MI); 3136 case G_UNMERGE_VALUES: 3137 return lowerUnmergeValues(MI); 3138 case TargetOpcode::G_SEXT_INREG: { 3139 assert(MI.getOperand(2).isImm() && "Expected immediate"); 3140 int64_t SizeInBits = MI.getOperand(2).getImm(); 3141 3142 Register DstReg = MI.getOperand(0).getReg(); 3143 Register SrcReg = MI.getOperand(1).getReg(); 3144 LLT DstTy = MRI.getType(DstReg); 3145 Register TmpRes = MRI.createGenericVirtualRegister(DstTy); 3146 3147 auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits); 3148 MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0)); 3149 MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0)); 3150 MI.eraseFromParent(); 3151 return Legalized; 3152 } 3153 case G_EXTRACT_VECTOR_ELT: 3154 case G_INSERT_VECTOR_ELT: 3155 return lowerExtractInsertVectorElt(MI); 3156 case G_SHUFFLE_VECTOR: 3157 return lowerShuffleVector(MI); 3158 case G_DYN_STACKALLOC: 3159 return lowerDynStackAlloc(MI); 3160 case G_EXTRACT: 3161 return lowerExtract(MI); 3162 case G_INSERT: 3163 return lowerInsert(MI); 3164 case G_BSWAP: 3165 return lowerBswap(MI); 3166 case G_BITREVERSE: 3167 return lowerBitreverse(MI); 3168 case G_READ_REGISTER: 3169 case G_WRITE_REGISTER: 3170 return lowerReadWriteRegister(MI); 3171 case G_UADDSAT: 3172 case G_USUBSAT: { 3173 // Try to make a reasonable guess about which lowering strategy to use. The 3174 // target can override this with custom lowering and calling the 3175 // implementation functions. 3176 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3177 if (LI.isLegalOrCustom({G_UMIN, Ty})) 3178 return lowerAddSubSatToMinMax(MI); 3179 return lowerAddSubSatToAddoSubo(MI); 3180 } 3181 case G_SADDSAT: 3182 case G_SSUBSAT: { 3183 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3184 3185 // FIXME: It would probably make more sense to see if G_SADDO is preferred, 3186 // since it's a shorter expansion. However, we would need to figure out the 3187 // preferred boolean type for the carry out for the query. 3188 if (LI.isLegalOrCustom({G_SMIN, Ty}) && LI.isLegalOrCustom({G_SMAX, Ty})) 3189 return lowerAddSubSatToMinMax(MI); 3190 return lowerAddSubSatToAddoSubo(MI); 3191 } 3192 case G_SSHLSAT: 3193 case G_USHLSAT: 3194 return lowerShlSat(MI); 3195 case G_ABS: 3196 return lowerAbsToAddXor(MI); 3197 case G_SELECT: 3198 return lowerSelect(MI); 3199 case G_SDIVREM: 3200 case G_UDIVREM: 3201 return lowerDIVREM(MI); 3202 case G_FSHL: 3203 case G_FSHR: 3204 return lowerFunnelShift(MI); 3205 case G_ROTL: 3206 case G_ROTR: 3207 return lowerRotate(MI); 3208 } 3209 } 3210 3211 Align LegalizerHelper::getStackTemporaryAlignment(LLT Ty, 3212 Align MinAlign) const { 3213 // FIXME: We're missing a way to go back from LLT to llvm::Type to query the 3214 // datalayout for the preferred alignment. Also there should be a target hook 3215 // for this to allow targets to reduce the alignment and ignore the 3216 // datalayout. e.g. AMDGPU should always use a 4-byte alignment, regardless of 3217 // the type. 3218 return std::max(Align(PowerOf2Ceil(Ty.getSizeInBytes())), MinAlign); 3219 } 3220 3221 MachineInstrBuilder 3222 LegalizerHelper::createStackTemporary(TypeSize Bytes, Align Alignment, 3223 MachinePointerInfo &PtrInfo) { 3224 MachineFunction &MF = MIRBuilder.getMF(); 3225 const DataLayout &DL = MIRBuilder.getDataLayout(); 3226 int FrameIdx = MF.getFrameInfo().CreateStackObject(Bytes, Alignment, false); 3227 3228 unsigned AddrSpace = DL.getAllocaAddrSpace(); 3229 LLT FramePtrTy = LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace)); 3230 3231 PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIdx); 3232 return MIRBuilder.buildFrameIndex(FramePtrTy, FrameIdx); 3233 } 3234 3235 static Register clampDynamicVectorIndex(MachineIRBuilder &B, Register IdxReg, 3236 LLT VecTy) { 3237 int64_t IdxVal; 3238 if (mi_match(IdxReg, *B.getMRI(), m_ICst(IdxVal))) 3239 return IdxReg; 3240 3241 LLT IdxTy = B.getMRI()->getType(IdxReg); 3242 unsigned NElts = VecTy.getNumElements(); 3243 if (isPowerOf2_32(NElts)) { 3244 APInt Imm = APInt::getLowBitsSet(IdxTy.getSizeInBits(), Log2_32(NElts)); 3245 return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0); 3246 } 3247 3248 return B.buildUMin(IdxTy, IdxReg, B.buildConstant(IdxTy, NElts - 1)) 3249 .getReg(0); 3250 } 3251 3252 Register LegalizerHelper::getVectorElementPointer(Register VecPtr, LLT VecTy, 3253 Register Index) { 3254 LLT EltTy = VecTy.getElementType(); 3255 3256 // Calculate the element offset and add it to the pointer. 3257 unsigned EltSize = EltTy.getSizeInBits() / 8; // FIXME: should be ABI size. 3258 assert(EltSize * 8 == EltTy.getSizeInBits() && 3259 "Converting bits to bytes lost precision"); 3260 3261 Index = clampDynamicVectorIndex(MIRBuilder, Index, VecTy); 3262 3263 LLT IdxTy = MRI.getType(Index); 3264 auto Mul = MIRBuilder.buildMul(IdxTy, Index, 3265 MIRBuilder.buildConstant(IdxTy, EltSize)); 3266 3267 LLT PtrTy = MRI.getType(VecPtr); 3268 return MIRBuilder.buildPtrAdd(PtrTy, VecPtr, Mul).getReg(0); 3269 } 3270 3271 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef( 3272 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) { 3273 Register DstReg = MI.getOperand(0).getReg(); 3274 LLT DstTy = MRI.getType(DstReg); 3275 LLT LCMTy = getLCMType(DstTy, NarrowTy); 3276 3277 unsigned NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 3278 3279 auto NewUndef = MIRBuilder.buildUndef(NarrowTy); 3280 SmallVector<Register, 8> Parts(NumParts, NewUndef.getReg(0)); 3281 3282 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3283 MI.eraseFromParent(); 3284 return Legalized; 3285 } 3286 3287 // Handle splitting vector operations which need to have the same number of 3288 // elements in each type index, but each type index may have a different element 3289 // type. 3290 // 3291 // e.g. <4 x s64> = G_SHL <4 x s64>, <4 x s32> -> 3292 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3293 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3294 // 3295 // Also handles some irregular breakdown cases, e.g. 3296 // e.g. <3 x s64> = G_SHL <3 x s64>, <3 x s32> -> 3297 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3298 // s64 = G_SHL s64, s32 3299 LegalizerHelper::LegalizeResult 3300 LegalizerHelper::fewerElementsVectorMultiEltType( 3301 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) { 3302 if (TypeIdx != 0) 3303 return UnableToLegalize; 3304 3305 const LLT NarrowTy0 = NarrowTyArg; 3306 const unsigned NewNumElts = 3307 NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1; 3308 3309 const Register DstReg = MI.getOperand(0).getReg(); 3310 LLT DstTy = MRI.getType(DstReg); 3311 LLT LeftoverTy0; 3312 3313 // All of the operands need to have the same number of elements, so if we can 3314 // determine a type breakdown for the result type, we can for all of the 3315 // source types. 3316 int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first; 3317 if (NumParts < 0) 3318 return UnableToLegalize; 3319 3320 SmallVector<MachineInstrBuilder, 4> NewInsts; 3321 3322 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3323 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3324 3325 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) { 3326 Register SrcReg = MI.getOperand(I).getReg(); 3327 LLT SrcTyI = MRI.getType(SrcReg); 3328 LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType()); 3329 LLT LeftoverTyI; 3330 3331 // Split this operand into the requested typed registers, and any leftover 3332 // required to reproduce the original type. 3333 if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs, 3334 LeftoverRegs)) 3335 return UnableToLegalize; 3336 3337 if (I == 1) { 3338 // For the first operand, create an instruction for each part and setup 3339 // the result. 3340 for (Register PartReg : PartRegs) { 3341 Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3342 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3343 .addDef(PartDstReg) 3344 .addUse(PartReg)); 3345 DstRegs.push_back(PartDstReg); 3346 } 3347 3348 for (Register LeftoverReg : LeftoverRegs) { 3349 Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0); 3350 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3351 .addDef(PartDstReg) 3352 .addUse(LeftoverReg)); 3353 LeftoverDstRegs.push_back(PartDstReg); 3354 } 3355 } else { 3356 assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size()); 3357 3358 // Add the newly created operand splits to the existing instructions. The 3359 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3360 // pieces. 3361 unsigned InstCount = 0; 3362 for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J) 3363 NewInsts[InstCount++].addUse(PartRegs[J]); 3364 for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J) 3365 NewInsts[InstCount++].addUse(LeftoverRegs[J]); 3366 } 3367 3368 PartRegs.clear(); 3369 LeftoverRegs.clear(); 3370 } 3371 3372 // Insert the newly built operations and rebuild the result register. 3373 for (auto &MIB : NewInsts) 3374 MIRBuilder.insertInstr(MIB); 3375 3376 insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs); 3377 3378 MI.eraseFromParent(); 3379 return Legalized; 3380 } 3381 3382 LegalizerHelper::LegalizeResult 3383 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx, 3384 LLT NarrowTy) { 3385 if (TypeIdx != 0) 3386 return UnableToLegalize; 3387 3388 Register DstReg = MI.getOperand(0).getReg(); 3389 Register SrcReg = MI.getOperand(1).getReg(); 3390 LLT DstTy = MRI.getType(DstReg); 3391 LLT SrcTy = MRI.getType(SrcReg); 3392 3393 LLT NarrowTy0 = NarrowTy; 3394 LLT NarrowTy1; 3395 unsigned NumParts; 3396 3397 if (NarrowTy.isVector()) { 3398 // Uneven breakdown not handled. 3399 NumParts = DstTy.getNumElements() / NarrowTy.getNumElements(); 3400 if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements()) 3401 return UnableToLegalize; 3402 3403 NarrowTy1 = LLT::vector(NarrowTy.getNumElements(), SrcTy.getElementType()); 3404 } else { 3405 NumParts = DstTy.getNumElements(); 3406 NarrowTy1 = SrcTy.getElementType(); 3407 } 3408 3409 SmallVector<Register, 4> SrcRegs, DstRegs; 3410 extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs); 3411 3412 for (unsigned I = 0; I < NumParts; ++I) { 3413 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3414 MachineInstr *NewInst = 3415 MIRBuilder.buildInstr(MI.getOpcode(), {DstReg}, {SrcRegs[I]}); 3416 3417 NewInst->setFlags(MI.getFlags()); 3418 DstRegs.push_back(DstReg); 3419 } 3420 3421 if (NarrowTy.isVector()) 3422 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3423 else 3424 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3425 3426 MI.eraseFromParent(); 3427 return Legalized; 3428 } 3429 3430 LegalizerHelper::LegalizeResult 3431 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx, 3432 LLT NarrowTy) { 3433 Register DstReg = MI.getOperand(0).getReg(); 3434 Register Src0Reg = MI.getOperand(2).getReg(); 3435 LLT DstTy = MRI.getType(DstReg); 3436 LLT SrcTy = MRI.getType(Src0Reg); 3437 3438 unsigned NumParts; 3439 LLT NarrowTy0, NarrowTy1; 3440 3441 if (TypeIdx == 0) { 3442 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3443 unsigned OldElts = DstTy.getNumElements(); 3444 3445 NarrowTy0 = NarrowTy; 3446 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements(); 3447 NarrowTy1 = NarrowTy.isVector() ? 3448 LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) : 3449 SrcTy.getElementType(); 3450 3451 } else { 3452 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3453 unsigned OldElts = SrcTy.getNumElements(); 3454 3455 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : 3456 NarrowTy.getNumElements(); 3457 NarrowTy0 = LLT::vector(NarrowTy.getNumElements(), 3458 DstTy.getScalarSizeInBits()); 3459 NarrowTy1 = NarrowTy; 3460 } 3461 3462 // FIXME: Don't know how to handle the situation where the small vectors 3463 // aren't all the same size yet. 3464 if (NarrowTy1.isVector() && 3465 NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements()) 3466 return UnableToLegalize; 3467 3468 CmpInst::Predicate Pred 3469 = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 3470 3471 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 3472 extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs); 3473 extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs); 3474 3475 for (unsigned I = 0; I < NumParts; ++I) { 3476 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3477 DstRegs.push_back(DstReg); 3478 3479 if (MI.getOpcode() == TargetOpcode::G_ICMP) 3480 MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3481 else { 3482 MachineInstr *NewCmp 3483 = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3484 NewCmp->setFlags(MI.getFlags()); 3485 } 3486 } 3487 3488 if (NarrowTy1.isVector()) 3489 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3490 else 3491 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3492 3493 MI.eraseFromParent(); 3494 return Legalized; 3495 } 3496 3497 LegalizerHelper::LegalizeResult 3498 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, 3499 LLT NarrowTy) { 3500 Register DstReg = MI.getOperand(0).getReg(); 3501 Register CondReg = MI.getOperand(1).getReg(); 3502 3503 unsigned NumParts = 0; 3504 LLT NarrowTy0, NarrowTy1; 3505 3506 LLT DstTy = MRI.getType(DstReg); 3507 LLT CondTy = MRI.getType(CondReg); 3508 unsigned Size = DstTy.getSizeInBits(); 3509 3510 assert(TypeIdx == 0 || CondTy.isVector()); 3511 3512 if (TypeIdx == 0) { 3513 NarrowTy0 = NarrowTy; 3514 NarrowTy1 = CondTy; 3515 3516 unsigned NarrowSize = NarrowTy0.getSizeInBits(); 3517 // FIXME: Don't know how to handle the situation where the small vectors 3518 // aren't all the same size yet. 3519 if (Size % NarrowSize != 0) 3520 return UnableToLegalize; 3521 3522 NumParts = Size / NarrowSize; 3523 3524 // Need to break down the condition type 3525 if (CondTy.isVector()) { 3526 if (CondTy.getNumElements() == NumParts) 3527 NarrowTy1 = CondTy.getElementType(); 3528 else 3529 NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts, 3530 CondTy.getScalarSizeInBits()); 3531 } 3532 } else { 3533 NumParts = CondTy.getNumElements(); 3534 if (NarrowTy.isVector()) { 3535 // TODO: Handle uneven breakdown. 3536 if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements()) 3537 return UnableToLegalize; 3538 3539 return UnableToLegalize; 3540 } else { 3541 NarrowTy0 = DstTy.getElementType(); 3542 NarrowTy1 = NarrowTy; 3543 } 3544 } 3545 3546 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs; 3547 if (CondTy.isVector()) 3548 extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs); 3549 3550 extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs); 3551 extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs); 3552 3553 for (unsigned i = 0; i < NumParts; ++i) { 3554 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3555 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg, 3556 Src1Regs[i], Src2Regs[i]); 3557 DstRegs.push_back(DstReg); 3558 } 3559 3560 if (NarrowTy0.isVector()) 3561 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3562 else 3563 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3564 3565 MI.eraseFromParent(); 3566 return Legalized; 3567 } 3568 3569 LegalizerHelper::LegalizeResult 3570 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 3571 LLT NarrowTy) { 3572 const Register DstReg = MI.getOperand(0).getReg(); 3573 LLT PhiTy = MRI.getType(DstReg); 3574 LLT LeftoverTy; 3575 3576 // All of the operands need to have the same number of elements, so if we can 3577 // determine a type breakdown for the result type, we can for all of the 3578 // source types. 3579 int NumParts, NumLeftover; 3580 std::tie(NumParts, NumLeftover) 3581 = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy); 3582 if (NumParts < 0) 3583 return UnableToLegalize; 3584 3585 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3586 SmallVector<MachineInstrBuilder, 4> NewInsts; 3587 3588 const int TotalNumParts = NumParts + NumLeftover; 3589 3590 // Insert the new phis in the result block first. 3591 for (int I = 0; I != TotalNumParts; ++I) { 3592 LLT Ty = I < NumParts ? NarrowTy : LeftoverTy; 3593 Register PartDstReg = MRI.createGenericVirtualRegister(Ty); 3594 NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI) 3595 .addDef(PartDstReg)); 3596 if (I < NumParts) 3597 DstRegs.push_back(PartDstReg); 3598 else 3599 LeftoverDstRegs.push_back(PartDstReg); 3600 } 3601 3602 MachineBasicBlock *MBB = MI.getParent(); 3603 MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI()); 3604 insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs); 3605 3606 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3607 3608 // Insert code to extract the incoming values in each predecessor block. 3609 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 3610 PartRegs.clear(); 3611 LeftoverRegs.clear(); 3612 3613 Register SrcReg = MI.getOperand(I).getReg(); 3614 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 3615 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 3616 3617 LLT Unused; 3618 if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs, 3619 LeftoverRegs)) 3620 return UnableToLegalize; 3621 3622 // Add the newly created operand splits to the existing instructions. The 3623 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3624 // pieces. 3625 for (int J = 0; J != TotalNumParts; ++J) { 3626 MachineInstrBuilder MIB = NewInsts[J]; 3627 MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]); 3628 MIB.addMBB(&OpMBB); 3629 } 3630 } 3631 3632 MI.eraseFromParent(); 3633 return Legalized; 3634 } 3635 3636 LegalizerHelper::LegalizeResult 3637 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI, 3638 unsigned TypeIdx, 3639 LLT NarrowTy) { 3640 if (TypeIdx != 1) 3641 return UnableToLegalize; 3642 3643 const int NumDst = MI.getNumOperands() - 1; 3644 const Register SrcReg = MI.getOperand(NumDst).getReg(); 3645 LLT SrcTy = MRI.getType(SrcReg); 3646 3647 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 3648 3649 // TODO: Create sequence of extracts. 3650 if (DstTy == NarrowTy) 3651 return UnableToLegalize; 3652 3653 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3654 if (DstTy == GCDTy) { 3655 // This would just be a copy of the same unmerge. 3656 // TODO: Create extracts, pad with undef and create intermediate merges. 3657 return UnableToLegalize; 3658 } 3659 3660 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 3661 const int NumUnmerge = Unmerge->getNumOperands() - 1; 3662 const int PartsPerUnmerge = NumDst / NumUnmerge; 3663 3664 for (int I = 0; I != NumUnmerge; ++I) { 3665 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 3666 3667 for (int J = 0; J != PartsPerUnmerge; ++J) 3668 MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg()); 3669 MIB.addUse(Unmerge.getReg(I)); 3670 } 3671 3672 MI.eraseFromParent(); 3673 return Legalized; 3674 } 3675 3676 LegalizerHelper::LegalizeResult 3677 LegalizerHelper::fewerElementsVectorMulo(MachineInstr &MI, unsigned TypeIdx, 3678 LLT NarrowTy) { 3679 Register Result = MI.getOperand(0).getReg(); 3680 Register Overflow = MI.getOperand(1).getReg(); 3681 Register LHS = MI.getOperand(2).getReg(); 3682 Register RHS = MI.getOperand(3).getReg(); 3683 3684 LLT SrcTy = MRI.getType(LHS); 3685 if (!SrcTy.isVector()) 3686 return UnableToLegalize; 3687 3688 LLT ElementType = SrcTy.getElementType(); 3689 LLT OverflowElementTy = MRI.getType(Overflow).getElementType(); 3690 const int NumResult = SrcTy.getNumElements(); 3691 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3692 3693 // Unmerge the operands to smaller parts of GCD type. 3694 auto UnmergeLHS = MIRBuilder.buildUnmerge(GCDTy, LHS); 3695 auto UnmergeRHS = MIRBuilder.buildUnmerge(GCDTy, RHS); 3696 3697 const int NumOps = UnmergeLHS->getNumOperands() - 1; 3698 const int PartsPerUnmerge = NumResult / NumOps; 3699 LLT OverflowTy = LLT::scalarOrVector(PartsPerUnmerge, OverflowElementTy); 3700 LLT ResultTy = LLT::scalarOrVector(PartsPerUnmerge, ElementType); 3701 3702 // Perform the operation over unmerged parts. 3703 SmallVector<Register, 8> ResultParts; 3704 SmallVector<Register, 8> OverflowParts; 3705 for (int I = 0; I != NumOps; ++I) { 3706 Register Operand1 = UnmergeLHS->getOperand(I).getReg(); 3707 Register Operand2 = UnmergeRHS->getOperand(I).getReg(); 3708 auto PartMul = MIRBuilder.buildInstr(MI.getOpcode(), {ResultTy, OverflowTy}, 3709 {Operand1, Operand2}); 3710 ResultParts.push_back(PartMul->getOperand(0).getReg()); 3711 OverflowParts.push_back(PartMul->getOperand(1).getReg()); 3712 } 3713 3714 LLT ResultLCMTy = buildLCMMergePieces(SrcTy, NarrowTy, GCDTy, ResultParts); 3715 LLT OverflowLCMTy = 3716 LLT::scalarOrVector(ResultLCMTy.getNumElements(), OverflowElementTy); 3717 3718 // Recombine the pieces to the original result and overflow registers. 3719 buildWidenedRemergeToDst(Result, ResultLCMTy, ResultParts); 3720 buildWidenedRemergeToDst(Overflow, OverflowLCMTy, OverflowParts); 3721 MI.eraseFromParent(); 3722 return Legalized; 3723 } 3724 3725 // Handle FewerElementsVector a G_BUILD_VECTOR or G_CONCAT_VECTORS that produces 3726 // a vector 3727 // 3728 // Create a G_BUILD_VECTOR or G_CONCAT_VECTORS of NarrowTy pieces, padding with 3729 // undef as necessary. 3730 // 3731 // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2 3732 // -> <2 x s16> 3733 // 3734 // %4:_(s16) = G_IMPLICIT_DEF 3735 // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1 3736 // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4 3737 // %7:_(<2 x s16>) = G_IMPLICIT_DEF 3738 // %8:_(<6 x s16>) = G_CONCAT_VECTORS %5, %6, %7 3739 // %3:_(<3 x s16>), %8:_(<3 x s16>) = G_UNMERGE_VALUES %8 3740 LegalizerHelper::LegalizeResult 3741 LegalizerHelper::fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx, 3742 LLT NarrowTy) { 3743 Register DstReg = MI.getOperand(0).getReg(); 3744 LLT DstTy = MRI.getType(DstReg); 3745 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 3746 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 3747 3748 // Break into a common type 3749 SmallVector<Register, 16> Parts; 3750 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 3751 extractGCDType(Parts, GCDTy, MI.getOperand(I).getReg()); 3752 3753 // Build the requested new merge, padding with undef. 3754 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, 3755 TargetOpcode::G_ANYEXT); 3756 3757 // Pack into the original result register. 3758 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3759 3760 MI.eraseFromParent(); 3761 return Legalized; 3762 } 3763 3764 LegalizerHelper::LegalizeResult 3765 LegalizerHelper::fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI, 3766 unsigned TypeIdx, 3767 LLT NarrowVecTy) { 3768 Register DstReg = MI.getOperand(0).getReg(); 3769 Register SrcVec = MI.getOperand(1).getReg(); 3770 Register InsertVal; 3771 bool IsInsert = MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT; 3772 3773 assert((IsInsert ? TypeIdx == 0 : TypeIdx == 1) && "not a vector type index"); 3774 if (IsInsert) 3775 InsertVal = MI.getOperand(2).getReg(); 3776 3777 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 3778 3779 // TODO: Handle total scalarization case. 3780 if (!NarrowVecTy.isVector()) 3781 return UnableToLegalize; 3782 3783 LLT VecTy = MRI.getType(SrcVec); 3784 3785 // If the index is a constant, we can really break this down as you would 3786 // expect, and index into the target size pieces. 3787 int64_t IdxVal; 3788 auto MaybeCst = 3789 getConstantVRegValWithLookThrough(Idx, MRI, /*LookThroughInstrs*/ true, 3790 /*HandleFConstants*/ false); 3791 if (MaybeCst) { 3792 IdxVal = MaybeCst->Value.getSExtValue(); 3793 // Avoid out of bounds indexing the pieces. 3794 if (IdxVal >= VecTy.getNumElements()) { 3795 MIRBuilder.buildUndef(DstReg); 3796 MI.eraseFromParent(); 3797 return Legalized; 3798 } 3799 3800 SmallVector<Register, 8> VecParts; 3801 LLT GCDTy = extractGCDType(VecParts, VecTy, NarrowVecTy, SrcVec); 3802 3803 // Build a sequence of NarrowTy pieces in VecParts for this operand. 3804 LLT LCMTy = buildLCMMergePieces(VecTy, NarrowVecTy, GCDTy, VecParts, 3805 TargetOpcode::G_ANYEXT); 3806 3807 unsigned NewNumElts = NarrowVecTy.getNumElements(); 3808 3809 LLT IdxTy = MRI.getType(Idx); 3810 int64_t PartIdx = IdxVal / NewNumElts; 3811 auto NewIdx = 3812 MIRBuilder.buildConstant(IdxTy, IdxVal - NewNumElts * PartIdx); 3813 3814 if (IsInsert) { 3815 LLT PartTy = MRI.getType(VecParts[PartIdx]); 3816 3817 // Use the adjusted index to insert into one of the subvectors. 3818 auto InsertPart = MIRBuilder.buildInsertVectorElement( 3819 PartTy, VecParts[PartIdx], InsertVal, NewIdx); 3820 VecParts[PartIdx] = InsertPart.getReg(0); 3821 3822 // Recombine the inserted subvector with the others to reform the result 3823 // vector. 3824 buildWidenedRemergeToDst(DstReg, LCMTy, VecParts); 3825 } else { 3826 MIRBuilder.buildExtractVectorElement(DstReg, VecParts[PartIdx], NewIdx); 3827 } 3828 3829 MI.eraseFromParent(); 3830 return Legalized; 3831 } 3832 3833 // With a variable index, we can't perform the operation in a smaller type, so 3834 // we're forced to expand this. 3835 // 3836 // TODO: We could emit a chain of compare/select to figure out which piece to 3837 // index. 3838 return lowerExtractInsertVectorElt(MI); 3839 } 3840 3841 LegalizerHelper::LegalizeResult 3842 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx, 3843 LLT NarrowTy) { 3844 // FIXME: Don't know how to handle secondary types yet. 3845 if (TypeIdx != 0) 3846 return UnableToLegalize; 3847 3848 MachineMemOperand *MMO = *MI.memoperands_begin(); 3849 3850 // This implementation doesn't work for atomics. Give up instead of doing 3851 // something invalid. 3852 if (MMO->getOrdering() != AtomicOrdering::NotAtomic || 3853 MMO->getFailureOrdering() != AtomicOrdering::NotAtomic) 3854 return UnableToLegalize; 3855 3856 bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD; 3857 Register ValReg = MI.getOperand(0).getReg(); 3858 Register AddrReg = MI.getOperand(1).getReg(); 3859 LLT ValTy = MRI.getType(ValReg); 3860 3861 // FIXME: Do we need a distinct NarrowMemory legalize action? 3862 if (ValTy.getSizeInBits() != 8 * MMO->getSize()) { 3863 LLVM_DEBUG(dbgs() << "Can't narrow extload/truncstore\n"); 3864 return UnableToLegalize; 3865 } 3866 3867 int NumParts = -1; 3868 int NumLeftover = -1; 3869 LLT LeftoverTy; 3870 SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs; 3871 if (IsLoad) { 3872 std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy); 3873 } else { 3874 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, 3875 NarrowLeftoverRegs)) { 3876 NumParts = NarrowRegs.size(); 3877 NumLeftover = NarrowLeftoverRegs.size(); 3878 } 3879 } 3880 3881 if (NumParts == -1) 3882 return UnableToLegalize; 3883 3884 LLT PtrTy = MRI.getType(AddrReg); 3885 const LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits()); 3886 3887 unsigned TotalSize = ValTy.getSizeInBits(); 3888 3889 // Split the load/store into PartTy sized pieces starting at Offset. If this 3890 // is a load, return the new registers in ValRegs. For a store, each elements 3891 // of ValRegs should be PartTy. Returns the next offset that needs to be 3892 // handled. 3893 auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs, 3894 unsigned Offset) -> unsigned { 3895 MachineFunction &MF = MIRBuilder.getMF(); 3896 unsigned PartSize = PartTy.getSizeInBits(); 3897 for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize; 3898 Offset += PartSize, ++Idx) { 3899 unsigned ByteSize = PartSize / 8; 3900 unsigned ByteOffset = Offset / 8; 3901 Register NewAddrReg; 3902 3903 MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset); 3904 3905 MachineMemOperand *NewMMO = 3906 MF.getMachineMemOperand(MMO, ByteOffset, ByteSize); 3907 3908 if (IsLoad) { 3909 Register Dst = MRI.createGenericVirtualRegister(PartTy); 3910 ValRegs.push_back(Dst); 3911 MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO); 3912 } else { 3913 MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO); 3914 } 3915 } 3916 3917 return Offset; 3918 }; 3919 3920 unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0); 3921 3922 // Handle the rest of the register if this isn't an even type breakdown. 3923 if (LeftoverTy.isValid()) 3924 splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset); 3925 3926 if (IsLoad) { 3927 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, 3928 LeftoverTy, NarrowLeftoverRegs); 3929 } 3930 3931 MI.eraseFromParent(); 3932 return Legalized; 3933 } 3934 3935 LegalizerHelper::LegalizeResult 3936 LegalizerHelper::reduceOperationWidth(MachineInstr &MI, unsigned int TypeIdx, 3937 LLT NarrowTy) { 3938 assert(TypeIdx == 0 && "only one type index expected"); 3939 3940 const unsigned Opc = MI.getOpcode(); 3941 const int NumDefOps = MI.getNumExplicitDefs(); 3942 const int NumSrcOps = MI.getNumOperands() - NumDefOps; 3943 const unsigned Flags = MI.getFlags(); 3944 const unsigned NarrowSize = NarrowTy.getSizeInBits(); 3945 const LLT NarrowScalarTy = LLT::scalar(NarrowSize); 3946 3947 assert(MI.getNumOperands() <= 4 && "expected instruction with either 1 " 3948 "result and 1-3 sources or 2 results and " 3949 "1-2 sources"); 3950 3951 SmallVector<Register, 2> DstRegs; 3952 for (int I = 0; I < NumDefOps; ++I) 3953 DstRegs.push_back(MI.getOperand(I).getReg()); 3954 3955 // First of all check whether we are narrowing (changing the element type) 3956 // or reducing the vector elements 3957 const LLT DstTy = MRI.getType(DstRegs[0]); 3958 const bool IsNarrow = NarrowTy.getScalarType() != DstTy.getScalarType(); 3959 3960 SmallVector<Register, 8> ExtractedRegs[3]; 3961 SmallVector<Register, 8> Parts; 3962 3963 unsigned NarrowElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3964 3965 // Break down all the sources into NarrowTy pieces we can operate on. This may 3966 // involve creating merges to a wider type, padded with undef. 3967 for (int I = 0; I != NumSrcOps; ++I) { 3968 Register SrcReg = MI.getOperand(I + NumDefOps).getReg(); 3969 LLT SrcTy = MRI.getType(SrcReg); 3970 3971 // The type to narrow SrcReg to. For narrowing, this is a smaller scalar. 3972 // For fewerElements, this is a smaller vector with the same element type. 3973 LLT OpNarrowTy; 3974 if (IsNarrow) { 3975 OpNarrowTy = NarrowScalarTy; 3976 3977 // In case of narrowing, we need to cast vectors to scalars for this to 3978 // work properly 3979 // FIXME: Can we do without the bitcast here if we're narrowing? 3980 if (SrcTy.isVector()) { 3981 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 3982 SrcReg = MIRBuilder.buildBitcast(SrcTy, SrcReg).getReg(0); 3983 } 3984 } else { 3985 OpNarrowTy = LLT::scalarOrVector(NarrowElts, SrcTy.getScalarType()); 3986 } 3987 3988 LLT GCDTy = extractGCDType(ExtractedRegs[I], SrcTy, OpNarrowTy, SrcReg); 3989 3990 // Build a sequence of NarrowTy pieces in ExtractedRegs for this operand. 3991 buildLCMMergePieces(SrcTy, OpNarrowTy, GCDTy, ExtractedRegs[I], 3992 TargetOpcode::G_ANYEXT); 3993 } 3994 3995 SmallVector<Register, 8> ResultRegs[2]; 3996 3997 // Input operands for each sub-instruction. 3998 SmallVector<SrcOp, 4> InputRegs(NumSrcOps, Register()); 3999 4000 int NumParts = ExtractedRegs[0].size(); 4001 const unsigned DstSize = DstTy.getSizeInBits(); 4002 const LLT DstScalarTy = LLT::scalar(DstSize); 4003 4004 // Narrowing needs to use scalar types 4005 LLT DstLCMTy, NarrowDstTy; 4006 if (IsNarrow) { 4007 DstLCMTy = getLCMType(DstScalarTy, NarrowScalarTy); 4008 NarrowDstTy = NarrowScalarTy; 4009 } else { 4010 DstLCMTy = getLCMType(DstTy, NarrowTy); 4011 NarrowDstTy = NarrowTy; 4012 } 4013 4014 // We widened the source registers to satisfy merge/unmerge size 4015 // constraints. We'll have some extra fully undef parts. 4016 const int NumRealParts = (DstSize + NarrowSize - 1) / NarrowSize; 4017 4018 for (int I = 0; I != NumRealParts; ++I) { 4019 // Emit this instruction on each of the split pieces. 4020 for (int J = 0; J != NumSrcOps; ++J) 4021 InputRegs[J] = ExtractedRegs[J][I]; 4022 4023 MachineInstrBuilder Inst; 4024 if (NumDefOps == 1) 4025 Inst = MIRBuilder.buildInstr(Opc, {NarrowDstTy}, InputRegs, Flags); 4026 else 4027 Inst = MIRBuilder.buildInstr(Opc, {NarrowDstTy, NarrowDstTy}, InputRegs, 4028 Flags); 4029 4030 for (int J = 0; J != NumDefOps; ++J) 4031 ResultRegs[J].push_back(Inst.getReg(J)); 4032 } 4033 4034 // Fill out the widened result with undef instead of creating instructions 4035 // with undef inputs. 4036 int NumUndefParts = NumParts - NumRealParts; 4037 if (NumUndefParts != 0) { 4038 Register Undef = MIRBuilder.buildUndef(NarrowDstTy).getReg(0); 4039 for (int I = 0; I != NumDefOps; ++I) 4040 ResultRegs[I].append(NumUndefParts, Undef); 4041 } 4042 4043 // Extract the possibly padded result. Use a scratch register if we need to do 4044 // a final bitcast, otherwise use the original result register. 4045 Register MergeDstReg; 4046 for (int I = 0; I != NumDefOps; ++I) { 4047 if (IsNarrow && DstTy.isVector()) 4048 MergeDstReg = MRI.createGenericVirtualRegister(DstScalarTy); 4049 else 4050 MergeDstReg = DstRegs[I]; 4051 4052 buildWidenedRemergeToDst(MergeDstReg, DstLCMTy, ResultRegs[I]); 4053 4054 // Recast to vector if we narrowed a vector 4055 if (IsNarrow && DstTy.isVector()) 4056 MIRBuilder.buildBitcast(DstRegs[I], MergeDstReg); 4057 } 4058 4059 MI.eraseFromParent(); 4060 return Legalized; 4061 } 4062 4063 LegalizerHelper::LegalizeResult 4064 LegalizerHelper::fewerElementsVectorSextInReg(MachineInstr &MI, unsigned TypeIdx, 4065 LLT NarrowTy) { 4066 Register DstReg = MI.getOperand(0).getReg(); 4067 Register SrcReg = MI.getOperand(1).getReg(); 4068 int64_t Imm = MI.getOperand(2).getImm(); 4069 4070 LLT DstTy = MRI.getType(DstReg); 4071 4072 SmallVector<Register, 8> Parts; 4073 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 4074 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts); 4075 4076 for (Register &R : Parts) 4077 R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0); 4078 4079 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 4080 4081 MI.eraseFromParent(); 4082 return Legalized; 4083 } 4084 4085 LegalizerHelper::LegalizeResult 4086 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, 4087 LLT NarrowTy) { 4088 using namespace TargetOpcode; 4089 4090 switch (MI.getOpcode()) { 4091 case G_IMPLICIT_DEF: 4092 return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy); 4093 case G_TRUNC: 4094 case G_AND: 4095 case G_OR: 4096 case G_XOR: 4097 case G_ADD: 4098 case G_SUB: 4099 case G_MUL: 4100 case G_PTR_ADD: 4101 case G_SMULH: 4102 case G_UMULH: 4103 case G_FADD: 4104 case G_FMUL: 4105 case G_FSUB: 4106 case G_FNEG: 4107 case G_FABS: 4108 case G_FCANONICALIZE: 4109 case G_FDIV: 4110 case G_FREM: 4111 case G_FMA: 4112 case G_FMAD: 4113 case G_FPOW: 4114 case G_FEXP: 4115 case G_FEXP2: 4116 case G_FLOG: 4117 case G_FLOG2: 4118 case G_FLOG10: 4119 case G_FNEARBYINT: 4120 case G_FCEIL: 4121 case G_FFLOOR: 4122 case G_FRINT: 4123 case G_INTRINSIC_ROUND: 4124 case G_INTRINSIC_ROUNDEVEN: 4125 case G_INTRINSIC_TRUNC: 4126 case G_FCOS: 4127 case G_FSIN: 4128 case G_FSQRT: 4129 case G_BSWAP: 4130 case G_BITREVERSE: 4131 case G_SDIV: 4132 case G_UDIV: 4133 case G_SREM: 4134 case G_UREM: 4135 case G_SDIVREM: 4136 case G_UDIVREM: 4137 case G_SMIN: 4138 case G_SMAX: 4139 case G_UMIN: 4140 case G_UMAX: 4141 case G_ABS: 4142 case G_FMINNUM: 4143 case G_FMAXNUM: 4144 case G_FMINNUM_IEEE: 4145 case G_FMAXNUM_IEEE: 4146 case G_FMINIMUM: 4147 case G_FMAXIMUM: 4148 case G_FSHL: 4149 case G_FSHR: 4150 case G_FREEZE: 4151 case G_SADDSAT: 4152 case G_SSUBSAT: 4153 case G_UADDSAT: 4154 case G_USUBSAT: 4155 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 4156 case G_UMULO: 4157 case G_SMULO: 4158 return fewerElementsVectorMulo(MI, TypeIdx, NarrowTy); 4159 case G_SHL: 4160 case G_LSHR: 4161 case G_ASHR: 4162 case G_SSHLSAT: 4163 case G_USHLSAT: 4164 case G_CTLZ: 4165 case G_CTLZ_ZERO_UNDEF: 4166 case G_CTTZ: 4167 case G_CTTZ_ZERO_UNDEF: 4168 case G_CTPOP: 4169 case G_FCOPYSIGN: 4170 return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy); 4171 case G_ZEXT: 4172 case G_SEXT: 4173 case G_ANYEXT: 4174 case G_FPEXT: 4175 case G_FPTRUNC: 4176 case G_SITOFP: 4177 case G_UITOFP: 4178 case G_FPTOSI: 4179 case G_FPTOUI: 4180 case G_INTTOPTR: 4181 case G_PTRTOINT: 4182 case G_ADDRSPACE_CAST: 4183 return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy); 4184 case G_ICMP: 4185 case G_FCMP: 4186 return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy); 4187 case G_SELECT: 4188 return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy); 4189 case G_PHI: 4190 return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy); 4191 case G_UNMERGE_VALUES: 4192 return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy); 4193 case G_BUILD_VECTOR: 4194 assert(TypeIdx == 0 && "not a vector type index"); 4195 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4196 case G_CONCAT_VECTORS: 4197 if (TypeIdx != 1) // TODO: This probably does work as expected already. 4198 return UnableToLegalize; 4199 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4200 case G_EXTRACT_VECTOR_ELT: 4201 case G_INSERT_VECTOR_ELT: 4202 return fewerElementsVectorExtractInsertVectorElt(MI, TypeIdx, NarrowTy); 4203 case G_LOAD: 4204 case G_STORE: 4205 return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy); 4206 case G_SEXT_INREG: 4207 return fewerElementsVectorSextInReg(MI, TypeIdx, NarrowTy); 4208 GISEL_VECREDUCE_CASES_NONSEQ 4209 return fewerElementsVectorReductions(MI, TypeIdx, NarrowTy); 4210 case G_SHUFFLE_VECTOR: 4211 return fewerElementsVectorShuffle(MI, TypeIdx, NarrowTy); 4212 default: 4213 return UnableToLegalize; 4214 } 4215 } 4216 4217 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle( 4218 MachineInstr &MI, unsigned int TypeIdx, LLT NarrowTy) { 4219 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR); 4220 if (TypeIdx != 0) 4221 return UnableToLegalize; 4222 4223 Register DstReg = MI.getOperand(0).getReg(); 4224 Register Src1Reg = MI.getOperand(1).getReg(); 4225 Register Src2Reg = MI.getOperand(2).getReg(); 4226 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 4227 LLT DstTy = MRI.getType(DstReg); 4228 LLT Src1Ty = MRI.getType(Src1Reg); 4229 LLT Src2Ty = MRI.getType(Src2Reg); 4230 // The shuffle should be canonicalized by now. 4231 if (DstTy != Src1Ty) 4232 return UnableToLegalize; 4233 if (DstTy != Src2Ty) 4234 return UnableToLegalize; 4235 4236 if (!isPowerOf2_32(DstTy.getNumElements())) 4237 return UnableToLegalize; 4238 4239 // We only support splitting a shuffle into 2, so adjust NarrowTy accordingly. 4240 // Further legalization attempts will be needed to do split further. 4241 NarrowTy = DstTy.changeNumElements(DstTy.getNumElements() / 2); 4242 unsigned NewElts = NarrowTy.getNumElements(); 4243 4244 SmallVector<Register> SplitSrc1Regs, SplitSrc2Regs; 4245 extractParts(Src1Reg, NarrowTy, 2, SplitSrc1Regs); 4246 extractParts(Src2Reg, NarrowTy, 2, SplitSrc2Regs); 4247 Register Inputs[4] = {SplitSrc1Regs[0], SplitSrc1Regs[1], SplitSrc2Regs[0], 4248 SplitSrc2Regs[1]}; 4249 4250 Register Hi, Lo; 4251 4252 // If Lo or Hi uses elements from at most two of the four input vectors, then 4253 // express it as a vector shuffle of those two inputs. Otherwise extract the 4254 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 4255 SmallVector<int, 16> Ops; 4256 for (unsigned High = 0; High < 2; ++High) { 4257 Register &Output = High ? Hi : Lo; 4258 4259 // Build a shuffle mask for the output, discovering on the fly which 4260 // input vectors to use as shuffle operands (recorded in InputUsed). 4261 // If building a suitable shuffle vector proves too hard, then bail 4262 // out with useBuildVector set. 4263 unsigned InputUsed[2] = {-1U, -1U}; // Not yet discovered. 4264 unsigned FirstMaskIdx = High * NewElts; 4265 bool UseBuildVector = false; 4266 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 4267 // The mask element. This indexes into the input. 4268 int Idx = Mask[FirstMaskIdx + MaskOffset]; 4269 4270 // The input vector this mask element indexes into. 4271 unsigned Input = (unsigned)Idx / NewElts; 4272 4273 if (Input >= array_lengthof(Inputs)) { 4274 // The mask element does not index into any input vector. 4275 Ops.push_back(-1); 4276 continue; 4277 } 4278 4279 // Turn the index into an offset from the start of the input vector. 4280 Idx -= Input * NewElts; 4281 4282 // Find or create a shuffle vector operand to hold this input. 4283 unsigned OpNo; 4284 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 4285 if (InputUsed[OpNo] == Input) { 4286 // This input vector is already an operand. 4287 break; 4288 } else if (InputUsed[OpNo] == -1U) { 4289 // Create a new operand for this input vector. 4290 InputUsed[OpNo] = Input; 4291 break; 4292 } 4293 } 4294 4295 if (OpNo >= array_lengthof(InputUsed)) { 4296 // More than two input vectors used! Give up on trying to create a 4297 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 4298 UseBuildVector = true; 4299 break; 4300 } 4301 4302 // Add the mask index for the new shuffle vector. 4303 Ops.push_back(Idx + OpNo * NewElts); 4304 } 4305 4306 if (UseBuildVector) { 4307 LLT EltTy = NarrowTy.getElementType(); 4308 SmallVector<Register, 16> SVOps; 4309 4310 // Extract the input elements by hand. 4311 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 4312 // The mask element. This indexes into the input. 4313 int Idx = Mask[FirstMaskIdx + MaskOffset]; 4314 4315 // The input vector this mask element indexes into. 4316 unsigned Input = (unsigned)Idx / NewElts; 4317 4318 if (Input >= array_lengthof(Inputs)) { 4319 // The mask element is "undef" or indexes off the end of the input. 4320 SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0)); 4321 continue; 4322 } 4323 4324 // Turn the index into an offset from the start of the input vector. 4325 Idx -= Input * NewElts; 4326 4327 // Extract the vector element by hand. 4328 SVOps.push_back(MIRBuilder 4329 .buildExtractVectorElement( 4330 EltTy, Inputs[Input], 4331 MIRBuilder.buildConstant(LLT::scalar(32), Idx)) 4332 .getReg(0)); 4333 } 4334 4335 // Construct the Lo/Hi output using a G_BUILD_VECTOR. 4336 Output = MIRBuilder.buildBuildVector(NarrowTy, SVOps).getReg(0); 4337 } else if (InputUsed[0] == -1U) { 4338 // No input vectors were used! The result is undefined. 4339 Output = MIRBuilder.buildUndef(NarrowTy).getReg(0); 4340 } else { 4341 Register Op0 = Inputs[InputUsed[0]]; 4342 // If only one input was used, use an undefined vector for the other. 4343 Register Op1 = InputUsed[1] == -1U 4344 ? MIRBuilder.buildUndef(NarrowTy).getReg(0) 4345 : Inputs[InputUsed[1]]; 4346 // At least one input vector was used. Create a new shuffle vector. 4347 Output = MIRBuilder.buildShuffleVector(NarrowTy, Op0, Op1, Ops).getReg(0); 4348 } 4349 4350 Ops.clear(); 4351 } 4352 4353 MIRBuilder.buildConcatVectors(DstReg, {Lo, Hi}); 4354 MI.eraseFromParent(); 4355 return Legalized; 4356 } 4357 4358 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorReductions( 4359 MachineInstr &MI, unsigned int TypeIdx, LLT NarrowTy) { 4360 unsigned Opc = MI.getOpcode(); 4361 assert(Opc != TargetOpcode::G_VECREDUCE_SEQ_FADD && 4362 Opc != TargetOpcode::G_VECREDUCE_SEQ_FMUL && 4363 "Sequential reductions not expected"); 4364 4365 if (TypeIdx != 1) 4366 return UnableToLegalize; 4367 4368 // The semantics of the normal non-sequential reductions allow us to freely 4369 // re-associate the operation. 4370 Register SrcReg = MI.getOperand(1).getReg(); 4371 LLT SrcTy = MRI.getType(SrcReg); 4372 Register DstReg = MI.getOperand(0).getReg(); 4373 LLT DstTy = MRI.getType(DstReg); 4374 4375 if (SrcTy.getNumElements() % NarrowTy.getNumElements() != 0) 4376 return UnableToLegalize; 4377 4378 SmallVector<Register> SplitSrcs; 4379 const unsigned NumParts = SrcTy.getNumElements() / NarrowTy.getNumElements(); 4380 extractParts(SrcReg, NarrowTy, NumParts, SplitSrcs); 4381 SmallVector<Register> PartialReductions; 4382 for (unsigned Part = 0; Part < NumParts; ++Part) { 4383 PartialReductions.push_back( 4384 MIRBuilder.buildInstr(Opc, {DstTy}, {SplitSrcs[Part]}).getReg(0)); 4385 } 4386 4387 unsigned ScalarOpc; 4388 switch (Opc) { 4389 case TargetOpcode::G_VECREDUCE_FADD: 4390 ScalarOpc = TargetOpcode::G_FADD; 4391 break; 4392 case TargetOpcode::G_VECREDUCE_FMUL: 4393 ScalarOpc = TargetOpcode::G_FMUL; 4394 break; 4395 case TargetOpcode::G_VECREDUCE_FMAX: 4396 ScalarOpc = TargetOpcode::G_FMAXNUM; 4397 break; 4398 case TargetOpcode::G_VECREDUCE_FMIN: 4399 ScalarOpc = TargetOpcode::G_FMINNUM; 4400 break; 4401 case TargetOpcode::G_VECREDUCE_ADD: 4402 ScalarOpc = TargetOpcode::G_ADD; 4403 break; 4404 case TargetOpcode::G_VECREDUCE_MUL: 4405 ScalarOpc = TargetOpcode::G_MUL; 4406 break; 4407 case TargetOpcode::G_VECREDUCE_AND: 4408 ScalarOpc = TargetOpcode::G_AND; 4409 break; 4410 case TargetOpcode::G_VECREDUCE_OR: 4411 ScalarOpc = TargetOpcode::G_OR; 4412 break; 4413 case TargetOpcode::G_VECREDUCE_XOR: 4414 ScalarOpc = TargetOpcode::G_XOR; 4415 break; 4416 case TargetOpcode::G_VECREDUCE_SMAX: 4417 ScalarOpc = TargetOpcode::G_SMAX; 4418 break; 4419 case TargetOpcode::G_VECREDUCE_SMIN: 4420 ScalarOpc = TargetOpcode::G_SMIN; 4421 break; 4422 case TargetOpcode::G_VECREDUCE_UMAX: 4423 ScalarOpc = TargetOpcode::G_UMAX; 4424 break; 4425 case TargetOpcode::G_VECREDUCE_UMIN: 4426 ScalarOpc = TargetOpcode::G_UMIN; 4427 break; 4428 default: 4429 LLVM_DEBUG(dbgs() << "Can't legalize: unknown reduction kind.\n"); 4430 return UnableToLegalize; 4431 } 4432 4433 // If the types involved are powers of 2, we can generate intermediate vector 4434 // ops, before generating a final reduction operation. 4435 if (isPowerOf2_32(SrcTy.getNumElements()) && 4436 isPowerOf2_32(NarrowTy.getNumElements())) { 4437 return tryNarrowPow2Reduction(MI, SrcReg, SrcTy, NarrowTy, ScalarOpc); 4438 } 4439 4440 Register Acc = PartialReductions[0]; 4441 for (unsigned Part = 1; Part < NumParts; ++Part) { 4442 if (Part == NumParts - 1) { 4443 MIRBuilder.buildInstr(ScalarOpc, {DstReg}, 4444 {Acc, PartialReductions[Part]}); 4445 } else { 4446 Acc = MIRBuilder 4447 .buildInstr(ScalarOpc, {DstTy}, {Acc, PartialReductions[Part]}) 4448 .getReg(0); 4449 } 4450 } 4451 MI.eraseFromParent(); 4452 return Legalized; 4453 } 4454 4455 LegalizerHelper::LegalizeResult 4456 LegalizerHelper::tryNarrowPow2Reduction(MachineInstr &MI, Register SrcReg, 4457 LLT SrcTy, LLT NarrowTy, 4458 unsigned ScalarOpc) { 4459 SmallVector<Register> SplitSrcs; 4460 // Split the sources into NarrowTy size pieces. 4461 extractParts(SrcReg, NarrowTy, 4462 SrcTy.getNumElements() / NarrowTy.getNumElements(), SplitSrcs); 4463 // We're going to do a tree reduction using vector operations until we have 4464 // one NarrowTy size value left. 4465 while (SplitSrcs.size() > 1) { 4466 SmallVector<Register> PartialRdxs; 4467 for (unsigned Idx = 0; Idx < SplitSrcs.size()-1; Idx += 2) { 4468 Register LHS = SplitSrcs[Idx]; 4469 Register RHS = SplitSrcs[Idx + 1]; 4470 // Create the intermediate vector op. 4471 Register Res = 4472 MIRBuilder.buildInstr(ScalarOpc, {NarrowTy}, {LHS, RHS}).getReg(0); 4473 PartialRdxs.push_back(Res); 4474 } 4475 SplitSrcs = std::move(PartialRdxs); 4476 } 4477 // Finally generate the requested NarrowTy based reduction. 4478 Observer.changingInstr(MI); 4479 MI.getOperand(1).setReg(SplitSrcs[0]); 4480 Observer.changedInstr(MI); 4481 return Legalized; 4482 } 4483 4484 LegalizerHelper::LegalizeResult 4485 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt, 4486 const LLT HalfTy, const LLT AmtTy) { 4487 4488 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4489 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4490 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4491 4492 if (Amt.isNullValue()) { 4493 MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH}); 4494 MI.eraseFromParent(); 4495 return Legalized; 4496 } 4497 4498 LLT NVT = HalfTy; 4499 unsigned NVTBits = HalfTy.getSizeInBits(); 4500 unsigned VTBits = 2 * NVTBits; 4501 4502 SrcOp Lo(Register(0)), Hi(Register(0)); 4503 if (MI.getOpcode() == TargetOpcode::G_SHL) { 4504 if (Amt.ugt(VTBits)) { 4505 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4506 } else if (Amt.ugt(NVTBits)) { 4507 Lo = MIRBuilder.buildConstant(NVT, 0); 4508 Hi = MIRBuilder.buildShl(NVT, InL, 4509 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4510 } else if (Amt == NVTBits) { 4511 Lo = MIRBuilder.buildConstant(NVT, 0); 4512 Hi = InL; 4513 } else { 4514 Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt)); 4515 auto OrLHS = 4516 MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt)); 4517 auto OrRHS = MIRBuilder.buildLShr( 4518 NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4519 Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4520 } 4521 } else if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4522 if (Amt.ugt(VTBits)) { 4523 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4524 } else if (Amt.ugt(NVTBits)) { 4525 Lo = MIRBuilder.buildLShr(NVT, InH, 4526 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4527 Hi = MIRBuilder.buildConstant(NVT, 0); 4528 } else if (Amt == NVTBits) { 4529 Lo = InH; 4530 Hi = MIRBuilder.buildConstant(NVT, 0); 4531 } else { 4532 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4533 4534 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4535 auto OrRHS = MIRBuilder.buildShl( 4536 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4537 4538 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4539 Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst); 4540 } 4541 } else { 4542 if (Amt.ugt(VTBits)) { 4543 Hi = Lo = MIRBuilder.buildAShr( 4544 NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4545 } else if (Amt.ugt(NVTBits)) { 4546 Lo = MIRBuilder.buildAShr(NVT, InH, 4547 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4548 Hi = MIRBuilder.buildAShr(NVT, InH, 4549 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4550 } else if (Amt == NVTBits) { 4551 Lo = InH; 4552 Hi = MIRBuilder.buildAShr(NVT, InH, 4553 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4554 } else { 4555 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4556 4557 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4558 auto OrRHS = MIRBuilder.buildShl( 4559 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4560 4561 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4562 Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst); 4563 } 4564 } 4565 4566 MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi}); 4567 MI.eraseFromParent(); 4568 4569 return Legalized; 4570 } 4571 4572 // TODO: Optimize if constant shift amount. 4573 LegalizerHelper::LegalizeResult 4574 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, 4575 LLT RequestedTy) { 4576 if (TypeIdx == 1) { 4577 Observer.changingInstr(MI); 4578 narrowScalarSrc(MI, RequestedTy, 2); 4579 Observer.changedInstr(MI); 4580 return Legalized; 4581 } 4582 4583 Register DstReg = MI.getOperand(0).getReg(); 4584 LLT DstTy = MRI.getType(DstReg); 4585 if (DstTy.isVector()) 4586 return UnableToLegalize; 4587 4588 Register Amt = MI.getOperand(2).getReg(); 4589 LLT ShiftAmtTy = MRI.getType(Amt); 4590 const unsigned DstEltSize = DstTy.getScalarSizeInBits(); 4591 if (DstEltSize % 2 != 0) 4592 return UnableToLegalize; 4593 4594 // Ignore the input type. We can only go to exactly half the size of the 4595 // input. If that isn't small enough, the resulting pieces will be further 4596 // legalized. 4597 const unsigned NewBitSize = DstEltSize / 2; 4598 const LLT HalfTy = LLT::scalar(NewBitSize); 4599 const LLT CondTy = LLT::scalar(1); 4600 4601 if (const MachineInstr *KShiftAmt = 4602 getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) { 4603 return narrowScalarShiftByConstant( 4604 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy); 4605 } 4606 4607 // TODO: Expand with known bits. 4608 4609 // Handle the fully general expansion by an unknown amount. 4610 auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize); 4611 4612 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4613 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4614 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4615 4616 auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits); 4617 auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt); 4618 4619 auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0); 4620 auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits); 4621 auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero); 4622 4623 Register ResultRegs[2]; 4624 switch (MI.getOpcode()) { 4625 case TargetOpcode::G_SHL: { 4626 // Short: ShAmt < NewBitSize 4627 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); 4628 4629 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack); 4630 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt); 4631 auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4632 4633 // Long: ShAmt >= NewBitSize 4634 auto LoL = MIRBuilder.buildConstant(HalfTy, 0); // Lo part is zero. 4635 auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part. 4636 4637 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL); 4638 auto Hi = MIRBuilder.buildSelect( 4639 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL)); 4640 4641 ResultRegs[0] = Lo.getReg(0); 4642 ResultRegs[1] = Hi.getReg(0); 4643 break; 4644 } 4645 case TargetOpcode::G_LSHR: 4646 case TargetOpcode::G_ASHR: { 4647 // Short: ShAmt < NewBitSize 4648 auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt}); 4649 4650 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt); 4651 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack); 4652 auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4653 4654 // Long: ShAmt >= NewBitSize 4655 MachineInstrBuilder HiL; 4656 if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4657 HiL = MIRBuilder.buildConstant(HalfTy, 0); // Hi part is zero. 4658 } else { 4659 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1); 4660 HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt); // Sign of Hi part. 4661 } 4662 auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, 4663 {InH, AmtExcess}); // Lo from Hi part. 4664 4665 auto Lo = MIRBuilder.buildSelect( 4666 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL)); 4667 4668 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL); 4669 4670 ResultRegs[0] = Lo.getReg(0); 4671 ResultRegs[1] = Hi.getReg(0); 4672 break; 4673 } 4674 default: 4675 llvm_unreachable("not a shift"); 4676 } 4677 4678 MIRBuilder.buildMerge(DstReg, ResultRegs); 4679 MI.eraseFromParent(); 4680 return Legalized; 4681 } 4682 4683 LegalizerHelper::LegalizeResult 4684 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 4685 LLT MoreTy) { 4686 assert(TypeIdx == 0 && "Expecting only Idx 0"); 4687 4688 Observer.changingInstr(MI); 4689 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 4690 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 4691 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 4692 moreElementsVectorSrc(MI, MoreTy, I); 4693 } 4694 4695 MachineBasicBlock &MBB = *MI.getParent(); 4696 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 4697 moreElementsVectorDst(MI, MoreTy, 0); 4698 Observer.changedInstr(MI); 4699 return Legalized; 4700 } 4701 4702 LegalizerHelper::LegalizeResult 4703 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx, 4704 LLT MoreTy) { 4705 unsigned Opc = MI.getOpcode(); 4706 switch (Opc) { 4707 case TargetOpcode::G_IMPLICIT_DEF: 4708 case TargetOpcode::G_LOAD: { 4709 if (TypeIdx != 0) 4710 return UnableToLegalize; 4711 Observer.changingInstr(MI); 4712 moreElementsVectorDst(MI, MoreTy, 0); 4713 Observer.changedInstr(MI); 4714 return Legalized; 4715 } 4716 case TargetOpcode::G_STORE: 4717 if (TypeIdx != 0) 4718 return UnableToLegalize; 4719 Observer.changingInstr(MI); 4720 moreElementsVectorSrc(MI, MoreTy, 0); 4721 Observer.changedInstr(MI); 4722 return Legalized; 4723 case TargetOpcode::G_AND: 4724 case TargetOpcode::G_OR: 4725 case TargetOpcode::G_XOR: 4726 case TargetOpcode::G_SMIN: 4727 case TargetOpcode::G_SMAX: 4728 case TargetOpcode::G_UMIN: 4729 case TargetOpcode::G_UMAX: 4730 case TargetOpcode::G_FMINNUM: 4731 case TargetOpcode::G_FMAXNUM: 4732 case TargetOpcode::G_FMINNUM_IEEE: 4733 case TargetOpcode::G_FMAXNUM_IEEE: 4734 case TargetOpcode::G_FMINIMUM: 4735 case TargetOpcode::G_FMAXIMUM: { 4736 Observer.changingInstr(MI); 4737 moreElementsVectorSrc(MI, MoreTy, 1); 4738 moreElementsVectorSrc(MI, MoreTy, 2); 4739 moreElementsVectorDst(MI, MoreTy, 0); 4740 Observer.changedInstr(MI); 4741 return Legalized; 4742 } 4743 case TargetOpcode::G_EXTRACT: 4744 if (TypeIdx != 1) 4745 return UnableToLegalize; 4746 Observer.changingInstr(MI); 4747 moreElementsVectorSrc(MI, MoreTy, 1); 4748 Observer.changedInstr(MI); 4749 return Legalized; 4750 case TargetOpcode::G_INSERT: 4751 case TargetOpcode::G_FREEZE: 4752 if (TypeIdx != 0) 4753 return UnableToLegalize; 4754 Observer.changingInstr(MI); 4755 moreElementsVectorSrc(MI, MoreTy, 1); 4756 moreElementsVectorDst(MI, MoreTy, 0); 4757 Observer.changedInstr(MI); 4758 return Legalized; 4759 case TargetOpcode::G_SELECT: 4760 if (TypeIdx != 0) 4761 return UnableToLegalize; 4762 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) 4763 return UnableToLegalize; 4764 4765 Observer.changingInstr(MI); 4766 moreElementsVectorSrc(MI, MoreTy, 2); 4767 moreElementsVectorSrc(MI, MoreTy, 3); 4768 moreElementsVectorDst(MI, MoreTy, 0); 4769 Observer.changedInstr(MI); 4770 return Legalized; 4771 case TargetOpcode::G_UNMERGE_VALUES: { 4772 if (TypeIdx != 1) 4773 return UnableToLegalize; 4774 4775 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 4776 int NumDst = MI.getNumOperands() - 1; 4777 moreElementsVectorSrc(MI, MoreTy, NumDst); 4778 4779 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 4780 for (int I = 0; I != NumDst; ++I) 4781 MIB.addDef(MI.getOperand(I).getReg()); 4782 4783 int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits(); 4784 for (int I = NumDst; I != NewNumDst; ++I) 4785 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 4786 4787 MIB.addUse(MI.getOperand(NumDst).getReg()); 4788 MI.eraseFromParent(); 4789 return Legalized; 4790 } 4791 case TargetOpcode::G_PHI: 4792 return moreElementsVectorPhi(MI, TypeIdx, MoreTy); 4793 default: 4794 return UnableToLegalize; 4795 } 4796 } 4797 4798 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs, 4799 ArrayRef<Register> Src1Regs, 4800 ArrayRef<Register> Src2Regs, 4801 LLT NarrowTy) { 4802 MachineIRBuilder &B = MIRBuilder; 4803 unsigned SrcParts = Src1Regs.size(); 4804 unsigned DstParts = DstRegs.size(); 4805 4806 unsigned DstIdx = 0; // Low bits of the result. 4807 Register FactorSum = 4808 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); 4809 DstRegs[DstIdx] = FactorSum; 4810 4811 unsigned CarrySumPrevDstIdx; 4812 SmallVector<Register, 4> Factors; 4813 4814 for (DstIdx = 1; DstIdx < DstParts; DstIdx++) { 4815 // Collect low parts of muls for DstIdx. 4816 for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1; 4817 i <= std::min(DstIdx, SrcParts - 1); ++i) { 4818 MachineInstrBuilder Mul = 4819 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); 4820 Factors.push_back(Mul.getReg(0)); 4821 } 4822 // Collect high parts of muls from previous DstIdx. 4823 for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts; 4824 i <= std::min(DstIdx - 1, SrcParts - 1); ++i) { 4825 MachineInstrBuilder Umulh = 4826 B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]); 4827 Factors.push_back(Umulh.getReg(0)); 4828 } 4829 // Add CarrySum from additions calculated for previous DstIdx. 4830 if (DstIdx != 1) { 4831 Factors.push_back(CarrySumPrevDstIdx); 4832 } 4833 4834 Register CarrySum; 4835 // Add all factors and accumulate all carries into CarrySum. 4836 if (DstIdx != DstParts - 1) { 4837 MachineInstrBuilder Uaddo = 4838 B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]); 4839 FactorSum = Uaddo.getReg(0); 4840 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0); 4841 for (unsigned i = 2; i < Factors.size(); ++i) { 4842 MachineInstrBuilder Uaddo = 4843 B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]); 4844 FactorSum = Uaddo.getReg(0); 4845 MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1)); 4846 CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0); 4847 } 4848 } else { 4849 // Since value for the next index is not calculated, neither is CarrySum. 4850 FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0); 4851 for (unsigned i = 2; i < Factors.size(); ++i) 4852 FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0); 4853 } 4854 4855 CarrySumPrevDstIdx = CarrySum; 4856 DstRegs[DstIdx] = FactorSum; 4857 Factors.clear(); 4858 } 4859 } 4860 4861 LegalizerHelper::LegalizeResult 4862 LegalizerHelper::narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx, 4863 LLT NarrowTy) { 4864 if (TypeIdx != 0) 4865 return UnableToLegalize; 4866 4867 Register DstReg = MI.getOperand(0).getReg(); 4868 LLT DstType = MRI.getType(DstReg); 4869 // FIXME: add support for vector types 4870 if (DstType.isVector()) 4871 return UnableToLegalize; 4872 4873 unsigned Opcode = MI.getOpcode(); 4874 unsigned OpO, OpE, OpF; 4875 switch (Opcode) { 4876 case TargetOpcode::G_SADDO: 4877 case TargetOpcode::G_SADDE: 4878 case TargetOpcode::G_UADDO: 4879 case TargetOpcode::G_UADDE: 4880 case TargetOpcode::G_ADD: 4881 OpO = TargetOpcode::G_UADDO; 4882 OpE = TargetOpcode::G_UADDE; 4883 OpF = TargetOpcode::G_UADDE; 4884 if (Opcode == TargetOpcode::G_SADDO || Opcode == TargetOpcode::G_SADDE) 4885 OpF = TargetOpcode::G_SADDE; 4886 break; 4887 case TargetOpcode::G_SSUBO: 4888 case TargetOpcode::G_SSUBE: 4889 case TargetOpcode::G_USUBO: 4890 case TargetOpcode::G_USUBE: 4891 case TargetOpcode::G_SUB: 4892 OpO = TargetOpcode::G_USUBO; 4893 OpE = TargetOpcode::G_USUBE; 4894 OpF = TargetOpcode::G_USUBE; 4895 if (Opcode == TargetOpcode::G_SSUBO || Opcode == TargetOpcode::G_SSUBE) 4896 OpF = TargetOpcode::G_SSUBE; 4897 break; 4898 default: 4899 llvm_unreachable("Unexpected add/sub opcode!"); 4900 } 4901 4902 // 1 for a plain add/sub, 2 if this is an operation with a carry-out. 4903 unsigned NumDefs = MI.getNumExplicitDefs(); 4904 Register Src1 = MI.getOperand(NumDefs).getReg(); 4905 Register Src2 = MI.getOperand(NumDefs + 1).getReg(); 4906 Register CarryDst, CarryIn; 4907 if (NumDefs == 2) 4908 CarryDst = MI.getOperand(1).getReg(); 4909 if (MI.getNumOperands() == NumDefs + 3) 4910 CarryIn = MI.getOperand(NumDefs + 2).getReg(); 4911 4912 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); 4913 LLT LeftoverTy, DummyTy; 4914 SmallVector<Register, 2> Src1Regs, Src2Regs, Src1Left, Src2Left, DstRegs; 4915 extractParts(Src1, RegTy, NarrowTy, LeftoverTy, Src1Regs, Src1Left); 4916 extractParts(Src2, RegTy, NarrowTy, DummyTy, Src2Regs, Src2Left); 4917 4918 int NarrowParts = Src1Regs.size(); 4919 for (int I = 0, E = Src1Left.size(); I != E; ++I) { 4920 Src1Regs.push_back(Src1Left[I]); 4921 Src2Regs.push_back(Src2Left[I]); 4922 } 4923 DstRegs.reserve(Src1Regs.size()); 4924 4925 for (int i = 0, e = Src1Regs.size(); i != e; ++i) { 4926 Register DstReg = 4927 MRI.createGenericVirtualRegister(MRI.getType(Src1Regs[i])); 4928 Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); 4929 // Forward the final carry-out to the destination register 4930 if (i == e - 1 && CarryDst) 4931 CarryOut = CarryDst; 4932 4933 if (!CarryIn) { 4934 MIRBuilder.buildInstr(OpO, {DstReg, CarryOut}, 4935 {Src1Regs[i], Src2Regs[i]}); 4936 } else if (i == e - 1) { 4937 MIRBuilder.buildInstr(OpF, {DstReg, CarryOut}, 4938 {Src1Regs[i], Src2Regs[i], CarryIn}); 4939 } else { 4940 MIRBuilder.buildInstr(OpE, {DstReg, CarryOut}, 4941 {Src1Regs[i], Src2Regs[i], CarryIn}); 4942 } 4943 4944 DstRegs.push_back(DstReg); 4945 CarryIn = CarryOut; 4946 } 4947 insertParts(MI.getOperand(0).getReg(), RegTy, NarrowTy, 4948 makeArrayRef(DstRegs).take_front(NarrowParts), LeftoverTy, 4949 makeArrayRef(DstRegs).drop_front(NarrowParts)); 4950 4951 MI.eraseFromParent(); 4952 return Legalized; 4953 } 4954 4955 LegalizerHelper::LegalizeResult 4956 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) { 4957 Register DstReg = MI.getOperand(0).getReg(); 4958 Register Src1 = MI.getOperand(1).getReg(); 4959 Register Src2 = MI.getOperand(2).getReg(); 4960 4961 LLT Ty = MRI.getType(DstReg); 4962 if (Ty.isVector()) 4963 return UnableToLegalize; 4964 4965 unsigned SrcSize = MRI.getType(Src1).getSizeInBits(); 4966 unsigned DstSize = Ty.getSizeInBits(); 4967 unsigned NarrowSize = NarrowTy.getSizeInBits(); 4968 if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0) 4969 return UnableToLegalize; 4970 4971 unsigned NumDstParts = DstSize / NarrowSize; 4972 unsigned NumSrcParts = SrcSize / NarrowSize; 4973 bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH; 4974 unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1); 4975 4976 SmallVector<Register, 2> Src1Parts, Src2Parts; 4977 SmallVector<Register, 2> DstTmpRegs(DstTmpParts); 4978 extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts); 4979 extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts); 4980 multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy); 4981 4982 // Take only high half of registers if this is high mul. 4983 ArrayRef<Register> DstRegs( 4984 IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts); 4985 MIRBuilder.buildMerge(DstReg, DstRegs); 4986 MI.eraseFromParent(); 4987 return Legalized; 4988 } 4989 4990 LegalizerHelper::LegalizeResult 4991 LegalizerHelper::narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx, 4992 LLT NarrowTy) { 4993 if (TypeIdx != 0) 4994 return UnableToLegalize; 4995 4996 bool IsSigned = MI.getOpcode() == TargetOpcode::G_FPTOSI; 4997 4998 Register Src = MI.getOperand(1).getReg(); 4999 LLT SrcTy = MRI.getType(Src); 5000 5001 // If all finite floats fit into the narrowed integer type, we can just swap 5002 // out the result type. This is practically only useful for conversions from 5003 // half to at least 16-bits, so just handle the one case. 5004 if (SrcTy.getScalarType() != LLT::scalar(16) || 5005 NarrowTy.getScalarSizeInBits() < (IsSigned ? 17u : 16u)) 5006 return UnableToLegalize; 5007 5008 Observer.changingInstr(MI); 5009 narrowScalarDst(MI, NarrowTy, 0, 5010 IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT); 5011 Observer.changedInstr(MI); 5012 return Legalized; 5013 } 5014 5015 LegalizerHelper::LegalizeResult 5016 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, 5017 LLT NarrowTy) { 5018 if (TypeIdx != 1) 5019 return UnableToLegalize; 5020 5021 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 5022 5023 int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 5024 // FIXME: add support for when SizeOp1 isn't an exact multiple of 5025 // NarrowSize. 5026 if (SizeOp1 % NarrowSize != 0) 5027 return UnableToLegalize; 5028 int NumParts = SizeOp1 / NarrowSize; 5029 5030 SmallVector<Register, 2> SrcRegs, DstRegs; 5031 SmallVector<uint64_t, 2> Indexes; 5032 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 5033 5034 Register OpReg = MI.getOperand(0).getReg(); 5035 uint64_t OpStart = MI.getOperand(2).getImm(); 5036 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 5037 for (int i = 0; i < NumParts; ++i) { 5038 unsigned SrcStart = i * NarrowSize; 5039 5040 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) { 5041 // No part of the extract uses this subregister, ignore it. 5042 continue; 5043 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 5044 // The entire subregister is extracted, forward the value. 5045 DstRegs.push_back(SrcRegs[i]); 5046 continue; 5047 } 5048 5049 // OpSegStart is where this destination segment would start in OpReg if it 5050 // extended infinitely in both directions. 5051 int64_t ExtractOffset; 5052 uint64_t SegSize; 5053 if (OpStart < SrcStart) { 5054 ExtractOffset = 0; 5055 SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart); 5056 } else { 5057 ExtractOffset = OpStart - SrcStart; 5058 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize); 5059 } 5060 5061 Register SegReg = SrcRegs[i]; 5062 if (ExtractOffset != 0 || SegSize != NarrowSize) { 5063 // A genuine extract is needed. 5064 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 5065 MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset); 5066 } 5067 5068 DstRegs.push_back(SegReg); 5069 } 5070 5071 Register DstReg = MI.getOperand(0).getReg(); 5072 if (MRI.getType(DstReg).isVector()) 5073 MIRBuilder.buildBuildVector(DstReg, DstRegs); 5074 else if (DstRegs.size() > 1) 5075 MIRBuilder.buildMerge(DstReg, DstRegs); 5076 else 5077 MIRBuilder.buildCopy(DstReg, DstRegs[0]); 5078 MI.eraseFromParent(); 5079 return Legalized; 5080 } 5081 5082 LegalizerHelper::LegalizeResult 5083 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, 5084 LLT NarrowTy) { 5085 // FIXME: Don't know how to handle secondary types yet. 5086 if (TypeIdx != 0) 5087 return UnableToLegalize; 5088 5089 SmallVector<Register, 2> SrcRegs, LeftoverRegs, DstRegs; 5090 SmallVector<uint64_t, 2> Indexes; 5091 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); 5092 LLT LeftoverTy; 5093 extractParts(MI.getOperand(1).getReg(), RegTy, NarrowTy, LeftoverTy, SrcRegs, 5094 LeftoverRegs); 5095 5096 for (Register Reg : LeftoverRegs) 5097 SrcRegs.push_back(Reg); 5098 5099 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 5100 Register OpReg = MI.getOperand(2).getReg(); 5101 uint64_t OpStart = MI.getOperand(3).getImm(); 5102 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 5103 for (int I = 0, E = SrcRegs.size(); I != E; ++I) { 5104 unsigned DstStart = I * NarrowSize; 5105 5106 if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 5107 // The entire subregister is defined by this insert, forward the new 5108 // value. 5109 DstRegs.push_back(OpReg); 5110 continue; 5111 } 5112 5113 Register SrcReg = SrcRegs[I]; 5114 if (MRI.getType(SrcRegs[I]) == LeftoverTy) { 5115 // The leftover reg is smaller than NarrowTy, so we need to extend it. 5116 SrcReg = MRI.createGenericVirtualRegister(NarrowTy); 5117 MIRBuilder.buildAnyExt(SrcReg, SrcRegs[I]); 5118 } 5119 5120 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) { 5121 // No part of the insert affects this subregister, forward the original. 5122 DstRegs.push_back(SrcReg); 5123 continue; 5124 } 5125 5126 // OpSegStart is where this destination segment would start in OpReg if it 5127 // extended infinitely in both directions. 5128 int64_t ExtractOffset, InsertOffset; 5129 uint64_t SegSize; 5130 if (OpStart < DstStart) { 5131 InsertOffset = 0; 5132 ExtractOffset = DstStart - OpStart; 5133 SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart); 5134 } else { 5135 InsertOffset = OpStart - DstStart; 5136 ExtractOffset = 0; 5137 SegSize = 5138 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart); 5139 } 5140 5141 Register SegReg = OpReg; 5142 if (ExtractOffset != 0 || SegSize != OpSize) { 5143 // A genuine extract is needed. 5144 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 5145 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); 5146 } 5147 5148 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 5149 MIRBuilder.buildInsert(DstReg, SrcReg, SegReg, InsertOffset); 5150 DstRegs.push_back(DstReg); 5151 } 5152 5153 uint64_t WideSize = DstRegs.size() * NarrowSize; 5154 Register DstReg = MI.getOperand(0).getReg(); 5155 if (WideSize > RegTy.getSizeInBits()) { 5156 Register MergeReg = MRI.createGenericVirtualRegister(LLT::scalar(WideSize)); 5157 MIRBuilder.buildMerge(MergeReg, DstRegs); 5158 MIRBuilder.buildTrunc(DstReg, MergeReg); 5159 } else 5160 MIRBuilder.buildMerge(DstReg, DstRegs); 5161 5162 MI.eraseFromParent(); 5163 return Legalized; 5164 } 5165 5166 LegalizerHelper::LegalizeResult 5167 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, 5168 LLT NarrowTy) { 5169 Register DstReg = MI.getOperand(0).getReg(); 5170 LLT DstTy = MRI.getType(DstReg); 5171 5172 assert(MI.getNumOperands() == 3 && TypeIdx == 0); 5173 5174 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 5175 SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs; 5176 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 5177 LLT LeftoverTy; 5178 if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy, 5179 Src0Regs, Src0LeftoverRegs)) 5180 return UnableToLegalize; 5181 5182 LLT Unused; 5183 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused, 5184 Src1Regs, Src1LeftoverRegs)) 5185 llvm_unreachable("inconsistent extractParts result"); 5186 5187 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 5188 auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 5189 {Src0Regs[I], Src1Regs[I]}); 5190 DstRegs.push_back(Inst.getReg(0)); 5191 } 5192 5193 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 5194 auto Inst = MIRBuilder.buildInstr( 5195 MI.getOpcode(), 5196 {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]}); 5197 DstLeftoverRegs.push_back(Inst.getReg(0)); 5198 } 5199 5200 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 5201 LeftoverTy, DstLeftoverRegs); 5202 5203 MI.eraseFromParent(); 5204 return Legalized; 5205 } 5206 5207 LegalizerHelper::LegalizeResult 5208 LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, 5209 LLT NarrowTy) { 5210 if (TypeIdx != 0) 5211 return UnableToLegalize; 5212 5213 Register DstReg = MI.getOperand(0).getReg(); 5214 Register SrcReg = MI.getOperand(1).getReg(); 5215 5216 LLT DstTy = MRI.getType(DstReg); 5217 if (DstTy.isVector()) 5218 return UnableToLegalize; 5219 5220 SmallVector<Register, 8> Parts; 5221 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 5222 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, MI.getOpcode()); 5223 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 5224 5225 MI.eraseFromParent(); 5226 return Legalized; 5227 } 5228 5229 LegalizerHelper::LegalizeResult 5230 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, 5231 LLT NarrowTy) { 5232 if (TypeIdx != 0) 5233 return UnableToLegalize; 5234 5235 Register CondReg = MI.getOperand(1).getReg(); 5236 LLT CondTy = MRI.getType(CondReg); 5237 if (CondTy.isVector()) // TODO: Handle vselect 5238 return UnableToLegalize; 5239 5240 Register DstReg = MI.getOperand(0).getReg(); 5241 LLT DstTy = MRI.getType(DstReg); 5242 5243 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 5244 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 5245 SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs; 5246 LLT LeftoverTy; 5247 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy, 5248 Src1Regs, Src1LeftoverRegs)) 5249 return UnableToLegalize; 5250 5251 LLT Unused; 5252 if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused, 5253 Src2Regs, Src2LeftoverRegs)) 5254 llvm_unreachable("inconsistent extractParts result"); 5255 5256 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 5257 auto Select = MIRBuilder.buildSelect(NarrowTy, 5258 CondReg, Src1Regs[I], Src2Regs[I]); 5259 DstRegs.push_back(Select.getReg(0)); 5260 } 5261 5262 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 5263 auto Select = MIRBuilder.buildSelect( 5264 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); 5265 DstLeftoverRegs.push_back(Select.getReg(0)); 5266 } 5267 5268 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 5269 LeftoverTy, DstLeftoverRegs); 5270 5271 MI.eraseFromParent(); 5272 return Legalized; 5273 } 5274 5275 LegalizerHelper::LegalizeResult 5276 LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, 5277 LLT NarrowTy) { 5278 if (TypeIdx != 1) 5279 return UnableToLegalize; 5280 5281 Register DstReg = MI.getOperand(0).getReg(); 5282 Register SrcReg = MI.getOperand(1).getReg(); 5283 LLT DstTy = MRI.getType(DstReg); 5284 LLT SrcTy = MRI.getType(SrcReg); 5285 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5286 5287 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5288 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF; 5289 5290 MachineIRBuilder &B = MIRBuilder; 5291 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 5292 // ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi) 5293 auto C_0 = B.buildConstant(NarrowTy, 0); 5294 auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 5295 UnmergeSrc.getReg(1), C_0); 5296 auto LoCTLZ = IsUndef ? 5297 B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)) : 5298 B.buildCTLZ(DstTy, UnmergeSrc.getReg(0)); 5299 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 5300 auto HiIsZeroCTLZ = B.buildAdd(DstTy, LoCTLZ, C_NarrowSize); 5301 auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)); 5302 B.buildSelect(DstReg, HiIsZero, HiIsZeroCTLZ, HiCTLZ); 5303 5304 MI.eraseFromParent(); 5305 return Legalized; 5306 } 5307 5308 return UnableToLegalize; 5309 } 5310 5311 LegalizerHelper::LegalizeResult 5312 LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, 5313 LLT NarrowTy) { 5314 if (TypeIdx != 1) 5315 return UnableToLegalize; 5316 5317 Register DstReg = MI.getOperand(0).getReg(); 5318 Register SrcReg = MI.getOperand(1).getReg(); 5319 LLT DstTy = MRI.getType(DstReg); 5320 LLT SrcTy = MRI.getType(SrcReg); 5321 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5322 5323 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5324 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF; 5325 5326 MachineIRBuilder &B = MIRBuilder; 5327 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 5328 // cttz(Hi:Lo) -> Lo == 0 ? (cttz(Hi) + NarrowSize) : cttz(Lo) 5329 auto C_0 = B.buildConstant(NarrowTy, 0); 5330 auto LoIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 5331 UnmergeSrc.getReg(0), C_0); 5332 auto HiCTTZ = IsUndef ? 5333 B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)) : 5334 B.buildCTTZ(DstTy, UnmergeSrc.getReg(1)); 5335 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 5336 auto LoIsZeroCTTZ = B.buildAdd(DstTy, HiCTTZ, C_NarrowSize); 5337 auto LoCTTZ = B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)); 5338 B.buildSelect(DstReg, LoIsZero, LoIsZeroCTTZ, LoCTTZ); 5339 5340 MI.eraseFromParent(); 5341 return Legalized; 5342 } 5343 5344 return UnableToLegalize; 5345 } 5346 5347 LegalizerHelper::LegalizeResult 5348 LegalizerHelper::narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, 5349 LLT NarrowTy) { 5350 if (TypeIdx != 1) 5351 return UnableToLegalize; 5352 5353 Register DstReg = MI.getOperand(0).getReg(); 5354 LLT DstTy = MRI.getType(DstReg); 5355 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 5356 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5357 5358 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5359 auto UnmergeSrc = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 5360 5361 auto LoCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(0)); 5362 auto HiCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(1)); 5363 MIRBuilder.buildAdd(DstReg, HiCTPOP, LoCTPOP); 5364 5365 MI.eraseFromParent(); 5366 return Legalized; 5367 } 5368 5369 return UnableToLegalize; 5370 } 5371 5372 LegalizerHelper::LegalizeResult 5373 LegalizerHelper::lowerBitCount(MachineInstr &MI) { 5374 unsigned Opc = MI.getOpcode(); 5375 const auto &TII = MIRBuilder.getTII(); 5376 auto isSupported = [this](const LegalityQuery &Q) { 5377 auto QAction = LI.getAction(Q).Action; 5378 return QAction == Legal || QAction == Libcall || QAction == Custom; 5379 }; 5380 switch (Opc) { 5381 default: 5382 return UnableToLegalize; 5383 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 5384 // This trivially expands to CTLZ. 5385 Observer.changingInstr(MI); 5386 MI.setDesc(TII.get(TargetOpcode::G_CTLZ)); 5387 Observer.changedInstr(MI); 5388 return Legalized; 5389 } 5390 case TargetOpcode::G_CTLZ: { 5391 Register DstReg = MI.getOperand(0).getReg(); 5392 Register SrcReg = MI.getOperand(1).getReg(); 5393 LLT DstTy = MRI.getType(DstReg); 5394 LLT SrcTy = MRI.getType(SrcReg); 5395 unsigned Len = SrcTy.getSizeInBits(); 5396 5397 if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 5398 // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero. 5399 auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg); 5400 auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0); 5401 auto ICmp = MIRBuilder.buildICmp( 5402 CmpInst::ICMP_EQ, SrcTy.changeElementSize(1), SrcReg, ZeroSrc); 5403 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 5404 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CtlzZU); 5405 MI.eraseFromParent(); 5406 return Legalized; 5407 } 5408 // for now, we do this: 5409 // NewLen = NextPowerOf2(Len); 5410 // x = x | (x >> 1); 5411 // x = x | (x >> 2); 5412 // ... 5413 // x = x | (x >>16); 5414 // x = x | (x >>32); // for 64-bit input 5415 // Upto NewLen/2 5416 // return Len - popcount(x); 5417 // 5418 // Ref: "Hacker's Delight" by Henry Warren 5419 Register Op = SrcReg; 5420 unsigned NewLen = PowerOf2Ceil(Len); 5421 for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) { 5422 auto MIBShiftAmt = MIRBuilder.buildConstant(SrcTy, 1ULL << i); 5423 auto MIBOp = MIRBuilder.buildOr( 5424 SrcTy, Op, MIRBuilder.buildLShr(SrcTy, Op, MIBShiftAmt)); 5425 Op = MIBOp.getReg(0); 5426 } 5427 auto MIBPop = MIRBuilder.buildCTPOP(DstTy, Op); 5428 MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(DstTy, Len), 5429 MIBPop); 5430 MI.eraseFromParent(); 5431 return Legalized; 5432 } 5433 case TargetOpcode::G_CTTZ_ZERO_UNDEF: { 5434 // This trivially expands to CTTZ. 5435 Observer.changingInstr(MI); 5436 MI.setDesc(TII.get(TargetOpcode::G_CTTZ)); 5437 Observer.changedInstr(MI); 5438 return Legalized; 5439 } 5440 case TargetOpcode::G_CTTZ: { 5441 Register DstReg = MI.getOperand(0).getReg(); 5442 Register SrcReg = MI.getOperand(1).getReg(); 5443 LLT DstTy = MRI.getType(DstReg); 5444 LLT SrcTy = MRI.getType(SrcReg); 5445 5446 unsigned Len = SrcTy.getSizeInBits(); 5447 if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 5448 // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with 5449 // zero. 5450 auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg); 5451 auto Zero = MIRBuilder.buildConstant(SrcTy, 0); 5452 auto ICmp = MIRBuilder.buildICmp( 5453 CmpInst::ICMP_EQ, DstTy.changeElementSize(1), SrcReg, Zero); 5454 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 5455 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CttzZU); 5456 MI.eraseFromParent(); 5457 return Legalized; 5458 } 5459 // for now, we use: { return popcount(~x & (x - 1)); } 5460 // unless the target has ctlz but not ctpop, in which case we use: 5461 // { return 32 - nlz(~x & (x-1)); } 5462 // Ref: "Hacker's Delight" by Henry Warren 5463 auto MIBCstNeg1 = MIRBuilder.buildConstant(SrcTy, -1); 5464 auto MIBNot = MIRBuilder.buildXor(SrcTy, SrcReg, MIBCstNeg1); 5465 auto MIBTmp = MIRBuilder.buildAnd( 5466 SrcTy, MIBNot, MIRBuilder.buildAdd(SrcTy, SrcReg, MIBCstNeg1)); 5467 if (!isSupported({TargetOpcode::G_CTPOP, {SrcTy, SrcTy}}) && 5468 isSupported({TargetOpcode::G_CTLZ, {SrcTy, SrcTy}})) { 5469 auto MIBCstLen = MIRBuilder.buildConstant(SrcTy, Len); 5470 MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen, 5471 MIRBuilder.buildCTLZ(SrcTy, MIBTmp)); 5472 MI.eraseFromParent(); 5473 return Legalized; 5474 } 5475 MI.setDesc(TII.get(TargetOpcode::G_CTPOP)); 5476 MI.getOperand(1).setReg(MIBTmp.getReg(0)); 5477 return Legalized; 5478 } 5479 case TargetOpcode::G_CTPOP: { 5480 Register SrcReg = MI.getOperand(1).getReg(); 5481 LLT Ty = MRI.getType(SrcReg); 5482 unsigned Size = Ty.getSizeInBits(); 5483 MachineIRBuilder &B = MIRBuilder; 5484 5485 // Count set bits in blocks of 2 bits. Default approach would be 5486 // B2Count = { val & 0x55555555 } + { (val >> 1) & 0x55555555 } 5487 // We use following formula instead: 5488 // B2Count = val - { (val >> 1) & 0x55555555 } 5489 // since it gives same result in blocks of 2 with one instruction less. 5490 auto C_1 = B.buildConstant(Ty, 1); 5491 auto B2Set1LoTo1Hi = B.buildLShr(Ty, SrcReg, C_1); 5492 APInt B2Mask1HiTo0 = APInt::getSplat(Size, APInt(8, 0x55)); 5493 auto C_B2Mask1HiTo0 = B.buildConstant(Ty, B2Mask1HiTo0); 5494 auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0); 5495 auto B2Count = B.buildSub(Ty, SrcReg, B2Count1Hi); 5496 5497 // In order to get count in blocks of 4 add values from adjacent block of 2. 5498 // B4Count = { B2Count & 0x33333333 } + { (B2Count >> 2) & 0x33333333 } 5499 auto C_2 = B.buildConstant(Ty, 2); 5500 auto B4Set2LoTo2Hi = B.buildLShr(Ty, B2Count, C_2); 5501 APInt B4Mask2HiTo0 = APInt::getSplat(Size, APInt(8, 0x33)); 5502 auto C_B4Mask2HiTo0 = B.buildConstant(Ty, B4Mask2HiTo0); 5503 auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0); 5504 auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0); 5505 auto B4Count = B.buildAdd(Ty, B4HiB2Count, B4LoB2Count); 5506 5507 // For count in blocks of 8 bits we don't have to mask high 4 bits before 5508 // addition since count value sits in range {0,...,8} and 4 bits are enough 5509 // to hold such binary values. After addition high 4 bits still hold count 5510 // of set bits in high 4 bit block, set them to zero and get 8 bit result. 5511 // B8Count = { B4Count + (B4Count >> 4) } & 0x0F0F0F0F 5512 auto C_4 = B.buildConstant(Ty, 4); 5513 auto B8HiB4Count = B.buildLShr(Ty, B4Count, C_4); 5514 auto B8CountDirty4Hi = B.buildAdd(Ty, B8HiB4Count, B4Count); 5515 APInt B8Mask4HiTo0 = APInt::getSplat(Size, APInt(8, 0x0F)); 5516 auto C_B8Mask4HiTo0 = B.buildConstant(Ty, B8Mask4HiTo0); 5517 auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0); 5518 5519 assert(Size<=128 && "Scalar size is too large for CTPOP lower algorithm"); 5520 // 8 bits can hold CTPOP result of 128 bit int or smaller. Mul with this 5521 // bitmask will set 8 msb in ResTmp to sum of all B8Counts in 8 bit blocks. 5522 auto MulMask = B.buildConstant(Ty, APInt::getSplat(Size, APInt(8, 0x01))); 5523 auto ResTmp = B.buildMul(Ty, B8Count, MulMask); 5524 5525 // Shift count result from 8 high bits to low bits. 5526 auto C_SizeM8 = B.buildConstant(Ty, Size - 8); 5527 B.buildLShr(MI.getOperand(0).getReg(), ResTmp, C_SizeM8); 5528 5529 MI.eraseFromParent(); 5530 return Legalized; 5531 } 5532 } 5533 } 5534 5535 // Check that (every element of) Reg is undef or not an exact multiple of BW. 5536 static bool isNonZeroModBitWidthOrUndef(const MachineRegisterInfo &MRI, 5537 Register Reg, unsigned BW) { 5538 return matchUnaryPredicate( 5539 MRI, Reg, 5540 [=](const Constant *C) { 5541 // Null constant here means an undef. 5542 const ConstantInt *CI = dyn_cast_or_null<ConstantInt>(C); 5543 return !CI || CI->getValue().urem(BW) != 0; 5544 }, 5545 /*AllowUndefs*/ true); 5546 } 5547 5548 LegalizerHelper::LegalizeResult 5549 LegalizerHelper::lowerFunnelShiftWithInverse(MachineInstr &MI) { 5550 Register Dst = MI.getOperand(0).getReg(); 5551 Register X = MI.getOperand(1).getReg(); 5552 Register Y = MI.getOperand(2).getReg(); 5553 Register Z = MI.getOperand(3).getReg(); 5554 LLT Ty = MRI.getType(Dst); 5555 LLT ShTy = MRI.getType(Z); 5556 5557 unsigned BW = Ty.getScalarSizeInBits(); 5558 5559 if (!isPowerOf2_32(BW)) 5560 return UnableToLegalize; 5561 5562 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5563 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; 5564 5565 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { 5566 // fshl X, Y, Z -> fshr X, Y, -Z 5567 // fshr X, Y, Z -> fshl X, Y, -Z 5568 auto Zero = MIRBuilder.buildConstant(ShTy, 0); 5569 Z = MIRBuilder.buildSub(Ty, Zero, Z).getReg(0); 5570 } else { 5571 // fshl X, Y, Z -> fshr (srl X, 1), (fshr X, Y, 1), ~Z 5572 // fshr X, Y, Z -> fshl (fshl X, Y, 1), (shl Y, 1), ~Z 5573 auto One = MIRBuilder.buildConstant(ShTy, 1); 5574 if (IsFSHL) { 5575 Y = MIRBuilder.buildInstr(RevOpcode, {Ty}, {X, Y, One}).getReg(0); 5576 X = MIRBuilder.buildLShr(Ty, X, One).getReg(0); 5577 } else { 5578 X = MIRBuilder.buildInstr(RevOpcode, {Ty}, {X, Y, One}).getReg(0); 5579 Y = MIRBuilder.buildShl(Ty, Y, One).getReg(0); 5580 } 5581 5582 Z = MIRBuilder.buildNot(ShTy, Z).getReg(0); 5583 } 5584 5585 MIRBuilder.buildInstr(RevOpcode, {Dst}, {X, Y, Z}); 5586 MI.eraseFromParent(); 5587 return Legalized; 5588 } 5589 5590 LegalizerHelper::LegalizeResult 5591 LegalizerHelper::lowerFunnelShiftAsShifts(MachineInstr &MI) { 5592 Register Dst = MI.getOperand(0).getReg(); 5593 Register X = MI.getOperand(1).getReg(); 5594 Register Y = MI.getOperand(2).getReg(); 5595 Register Z = MI.getOperand(3).getReg(); 5596 LLT Ty = MRI.getType(Dst); 5597 LLT ShTy = MRI.getType(Z); 5598 5599 const unsigned BW = Ty.getScalarSizeInBits(); 5600 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5601 5602 Register ShX, ShY; 5603 Register ShAmt, InvShAmt; 5604 5605 // FIXME: Emit optimized urem by constant instead of letting it expand later. 5606 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { 5607 // fshl: X << C | Y >> (BW - C) 5608 // fshr: X << (BW - C) | Y >> C 5609 // where C = Z % BW is not zero 5610 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); 5611 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); 5612 InvShAmt = MIRBuilder.buildSub(ShTy, BitWidthC, ShAmt).getReg(0); 5613 ShX = MIRBuilder.buildShl(Ty, X, IsFSHL ? ShAmt : InvShAmt).getReg(0); 5614 ShY = MIRBuilder.buildLShr(Ty, Y, IsFSHL ? InvShAmt : ShAmt).getReg(0); 5615 } else { 5616 // fshl: X << (Z % BW) | Y >> 1 >> (BW - 1 - (Z % BW)) 5617 // fshr: X << 1 << (BW - 1 - (Z % BW)) | Y >> (Z % BW) 5618 auto Mask = MIRBuilder.buildConstant(ShTy, BW - 1); 5619 if (isPowerOf2_32(BW)) { 5620 // Z % BW -> Z & (BW - 1) 5621 ShAmt = MIRBuilder.buildAnd(ShTy, Z, Mask).getReg(0); 5622 // (BW - 1) - (Z % BW) -> ~Z & (BW - 1) 5623 auto NotZ = MIRBuilder.buildNot(ShTy, Z); 5624 InvShAmt = MIRBuilder.buildAnd(ShTy, NotZ, Mask).getReg(0); 5625 } else { 5626 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); 5627 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); 5628 InvShAmt = MIRBuilder.buildSub(ShTy, Mask, ShAmt).getReg(0); 5629 } 5630 5631 auto One = MIRBuilder.buildConstant(ShTy, 1); 5632 if (IsFSHL) { 5633 ShX = MIRBuilder.buildShl(Ty, X, ShAmt).getReg(0); 5634 auto ShY1 = MIRBuilder.buildLShr(Ty, Y, One); 5635 ShY = MIRBuilder.buildLShr(Ty, ShY1, InvShAmt).getReg(0); 5636 } else { 5637 auto ShX1 = MIRBuilder.buildShl(Ty, X, One); 5638 ShX = MIRBuilder.buildShl(Ty, ShX1, InvShAmt).getReg(0); 5639 ShY = MIRBuilder.buildLShr(Ty, Y, ShAmt).getReg(0); 5640 } 5641 } 5642 5643 MIRBuilder.buildOr(Dst, ShX, ShY); 5644 MI.eraseFromParent(); 5645 return Legalized; 5646 } 5647 5648 LegalizerHelper::LegalizeResult 5649 LegalizerHelper::lowerFunnelShift(MachineInstr &MI) { 5650 // These operations approximately do the following (while avoiding undefined 5651 // shifts by BW): 5652 // G_FSHL: (X << (Z % BW)) | (Y >> (BW - (Z % BW))) 5653 // G_FSHR: (X << (BW - (Z % BW))) | (Y >> (Z % BW)) 5654 Register Dst = MI.getOperand(0).getReg(); 5655 LLT Ty = MRI.getType(Dst); 5656 LLT ShTy = MRI.getType(MI.getOperand(3).getReg()); 5657 5658 bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5659 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; 5660 5661 // TODO: Use smarter heuristic that accounts for vector legalization. 5662 if (LI.getAction({RevOpcode, {Ty, ShTy}}).Action == Lower) 5663 return lowerFunnelShiftAsShifts(MI); 5664 5665 // This only works for powers of 2, fallback to shifts if it fails. 5666 LegalizerHelper::LegalizeResult Result = lowerFunnelShiftWithInverse(MI); 5667 if (Result == UnableToLegalize) 5668 return lowerFunnelShiftAsShifts(MI); 5669 return Result; 5670 } 5671 5672 LegalizerHelper::LegalizeResult 5673 LegalizerHelper::lowerRotateWithReverseRotate(MachineInstr &MI) { 5674 Register Dst = MI.getOperand(0).getReg(); 5675 Register Src = MI.getOperand(1).getReg(); 5676 Register Amt = MI.getOperand(2).getReg(); 5677 LLT AmtTy = MRI.getType(Amt); 5678 auto Zero = MIRBuilder.buildConstant(AmtTy, 0); 5679 bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL; 5680 unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL; 5681 auto Neg = MIRBuilder.buildSub(AmtTy, Zero, Amt); 5682 MIRBuilder.buildInstr(RevRot, {Dst}, {Src, Neg}); 5683 MI.eraseFromParent(); 5684 return Legalized; 5685 } 5686 5687 LegalizerHelper::LegalizeResult LegalizerHelper::lowerRotate(MachineInstr &MI) { 5688 Register Dst = MI.getOperand(0).getReg(); 5689 Register Src = MI.getOperand(1).getReg(); 5690 Register Amt = MI.getOperand(2).getReg(); 5691 LLT DstTy = MRI.getType(Dst); 5692 LLT SrcTy = MRI.getType(Dst); 5693 LLT AmtTy = MRI.getType(Amt); 5694 5695 unsigned EltSizeInBits = DstTy.getScalarSizeInBits(); 5696 bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL; 5697 5698 MIRBuilder.setInstrAndDebugLoc(MI); 5699 5700 // If a rotate in the other direction is supported, use it. 5701 unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL; 5702 if (LI.isLegalOrCustom({RevRot, {DstTy, SrcTy}}) && 5703 isPowerOf2_32(EltSizeInBits)) 5704 return lowerRotateWithReverseRotate(MI); 5705 5706 auto Zero = MIRBuilder.buildConstant(AmtTy, 0); 5707 unsigned ShOpc = IsLeft ? TargetOpcode::G_SHL : TargetOpcode::G_LSHR; 5708 unsigned RevShiftOpc = IsLeft ? TargetOpcode::G_LSHR : TargetOpcode::G_SHL; 5709 auto BitWidthMinusOneC = MIRBuilder.buildConstant(AmtTy, EltSizeInBits - 1); 5710 Register ShVal; 5711 Register RevShiftVal; 5712 if (isPowerOf2_32(EltSizeInBits)) { 5713 // (rotl x, c) -> x << (c & (w - 1)) | x >> (-c & (w - 1)) 5714 // (rotr x, c) -> x >> (c & (w - 1)) | x << (-c & (w - 1)) 5715 auto NegAmt = MIRBuilder.buildSub(AmtTy, Zero, Amt); 5716 auto ShAmt = MIRBuilder.buildAnd(AmtTy, Amt, BitWidthMinusOneC); 5717 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); 5718 auto RevAmt = MIRBuilder.buildAnd(AmtTy, NegAmt, BitWidthMinusOneC); 5719 RevShiftVal = 5720 MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Src, RevAmt}).getReg(0); 5721 } else { 5722 // (rotl x, c) -> x << (c % w) | x >> 1 >> (w - 1 - (c % w)) 5723 // (rotr x, c) -> x >> (c % w) | x << 1 << (w - 1 - (c % w)) 5724 auto BitWidthC = MIRBuilder.buildConstant(AmtTy, EltSizeInBits); 5725 auto ShAmt = MIRBuilder.buildURem(AmtTy, Amt, BitWidthC); 5726 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); 5727 auto RevAmt = MIRBuilder.buildSub(AmtTy, BitWidthMinusOneC, ShAmt); 5728 auto One = MIRBuilder.buildConstant(AmtTy, 1); 5729 auto Inner = MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Src, One}); 5730 RevShiftVal = 5731 MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Inner, RevAmt}).getReg(0); 5732 } 5733 MIRBuilder.buildOr(Dst, ShVal, RevShiftVal); 5734 MI.eraseFromParent(); 5735 return Legalized; 5736 } 5737 5738 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float 5739 // representation. 5740 LegalizerHelper::LegalizeResult 5741 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) { 5742 Register Dst = MI.getOperand(0).getReg(); 5743 Register Src = MI.getOperand(1).getReg(); 5744 const LLT S64 = LLT::scalar(64); 5745 const LLT S32 = LLT::scalar(32); 5746 const LLT S1 = LLT::scalar(1); 5747 5748 assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32); 5749 5750 // unsigned cul2f(ulong u) { 5751 // uint lz = clz(u); 5752 // uint e = (u != 0) ? 127U + 63U - lz : 0; 5753 // u = (u << lz) & 0x7fffffffffffffffUL; 5754 // ulong t = u & 0xffffffffffUL; 5755 // uint v = (e << 23) | (uint)(u >> 40); 5756 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U); 5757 // return as_float(v + r); 5758 // } 5759 5760 auto Zero32 = MIRBuilder.buildConstant(S32, 0); 5761 auto Zero64 = MIRBuilder.buildConstant(S64, 0); 5762 5763 auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src); 5764 5765 auto K = MIRBuilder.buildConstant(S32, 127U + 63U); 5766 auto Sub = MIRBuilder.buildSub(S32, K, LZ); 5767 5768 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64); 5769 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32); 5770 5771 auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1); 5772 auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ); 5773 5774 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0); 5775 5776 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); 5777 auto T = MIRBuilder.buildAnd(S64, U, Mask1); 5778 5779 auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40)); 5780 auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23)); 5781 auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl)); 5782 5783 auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL); 5784 auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C); 5785 auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C); 5786 auto One = MIRBuilder.buildConstant(S32, 1); 5787 5788 auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One); 5789 auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32); 5790 auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0); 5791 MIRBuilder.buildAdd(Dst, V, R); 5792 5793 MI.eraseFromParent(); 5794 return Legalized; 5795 } 5796 5797 LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) { 5798 Register Dst = MI.getOperand(0).getReg(); 5799 Register Src = MI.getOperand(1).getReg(); 5800 LLT DstTy = MRI.getType(Dst); 5801 LLT SrcTy = MRI.getType(Src); 5802 5803 if (SrcTy == LLT::scalar(1)) { 5804 auto True = MIRBuilder.buildFConstant(DstTy, 1.0); 5805 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5806 MIRBuilder.buildSelect(Dst, Src, True, False); 5807 MI.eraseFromParent(); 5808 return Legalized; 5809 } 5810 5811 if (SrcTy != LLT::scalar(64)) 5812 return UnableToLegalize; 5813 5814 if (DstTy == LLT::scalar(32)) { 5815 // TODO: SelectionDAG has several alternative expansions to port which may 5816 // be more reasonble depending on the available instructions. If a target 5817 // has sitofp, does not have CTLZ, or can efficiently use f64 as an 5818 // intermediate type, this is probably worse. 5819 return lowerU64ToF32BitOps(MI); 5820 } 5821 5822 return UnableToLegalize; 5823 } 5824 5825 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) { 5826 Register Dst = MI.getOperand(0).getReg(); 5827 Register Src = MI.getOperand(1).getReg(); 5828 LLT DstTy = MRI.getType(Dst); 5829 LLT SrcTy = MRI.getType(Src); 5830 5831 const LLT S64 = LLT::scalar(64); 5832 const LLT S32 = LLT::scalar(32); 5833 const LLT S1 = LLT::scalar(1); 5834 5835 if (SrcTy == S1) { 5836 auto True = MIRBuilder.buildFConstant(DstTy, -1.0); 5837 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5838 MIRBuilder.buildSelect(Dst, Src, True, False); 5839 MI.eraseFromParent(); 5840 return Legalized; 5841 } 5842 5843 if (SrcTy != S64) 5844 return UnableToLegalize; 5845 5846 if (DstTy == S32) { 5847 // signed cl2f(long l) { 5848 // long s = l >> 63; 5849 // float r = cul2f((l + s) ^ s); 5850 // return s ? -r : r; 5851 // } 5852 Register L = Src; 5853 auto SignBit = MIRBuilder.buildConstant(S64, 63); 5854 auto S = MIRBuilder.buildAShr(S64, L, SignBit); 5855 5856 auto LPlusS = MIRBuilder.buildAdd(S64, L, S); 5857 auto Xor = MIRBuilder.buildXor(S64, LPlusS, S); 5858 auto R = MIRBuilder.buildUITOFP(S32, Xor); 5859 5860 auto RNeg = MIRBuilder.buildFNeg(S32, R); 5861 auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S, 5862 MIRBuilder.buildConstant(S64, 0)); 5863 MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R); 5864 MI.eraseFromParent(); 5865 return Legalized; 5866 } 5867 5868 return UnableToLegalize; 5869 } 5870 5871 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) { 5872 Register Dst = MI.getOperand(0).getReg(); 5873 Register Src = MI.getOperand(1).getReg(); 5874 LLT DstTy = MRI.getType(Dst); 5875 LLT SrcTy = MRI.getType(Src); 5876 const LLT S64 = LLT::scalar(64); 5877 const LLT S32 = LLT::scalar(32); 5878 5879 if (SrcTy != S64 && SrcTy != S32) 5880 return UnableToLegalize; 5881 if (DstTy != S32 && DstTy != S64) 5882 return UnableToLegalize; 5883 5884 // FPTOSI gives same result as FPTOUI for positive signed integers. 5885 // FPTOUI needs to deal with fp values that convert to unsigned integers 5886 // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp. 5887 5888 APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits()); 5889 APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle() 5890 : APFloat::IEEEdouble(), 5891 APInt::getNullValue(SrcTy.getSizeInBits())); 5892 TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven); 5893 5894 MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src); 5895 5896 MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP); 5897 // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on 5898 // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1. 5899 MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold); 5900 MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub); 5901 MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt); 5902 MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit); 5903 5904 const LLT S1 = LLT::scalar(1); 5905 5906 MachineInstrBuilder FCMP = 5907 MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold); 5908 MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res); 5909 5910 MI.eraseFromParent(); 5911 return Legalized; 5912 } 5913 5914 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) { 5915 Register Dst = MI.getOperand(0).getReg(); 5916 Register Src = MI.getOperand(1).getReg(); 5917 LLT DstTy = MRI.getType(Dst); 5918 LLT SrcTy = MRI.getType(Src); 5919 const LLT S64 = LLT::scalar(64); 5920 const LLT S32 = LLT::scalar(32); 5921 5922 // FIXME: Only f32 to i64 conversions are supported. 5923 if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64) 5924 return UnableToLegalize; 5925 5926 // Expand f32 -> i64 conversion 5927 // This algorithm comes from compiler-rt's implementation of fixsfdi: 5928 // https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/fixsfdi.c 5929 5930 unsigned SrcEltBits = SrcTy.getScalarSizeInBits(); 5931 5932 auto ExponentMask = MIRBuilder.buildConstant(SrcTy, 0x7F800000); 5933 auto ExponentLoBit = MIRBuilder.buildConstant(SrcTy, 23); 5934 5935 auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask); 5936 auto ExponentBits = MIRBuilder.buildLShr(SrcTy, AndExpMask, ExponentLoBit); 5937 5938 auto SignMask = MIRBuilder.buildConstant(SrcTy, 5939 APInt::getSignMask(SrcEltBits)); 5940 auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask); 5941 auto SignLowBit = MIRBuilder.buildConstant(SrcTy, SrcEltBits - 1); 5942 auto Sign = MIRBuilder.buildAShr(SrcTy, AndSignMask, SignLowBit); 5943 Sign = MIRBuilder.buildSExt(DstTy, Sign); 5944 5945 auto MantissaMask = MIRBuilder.buildConstant(SrcTy, 0x007FFFFF); 5946 auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask); 5947 auto K = MIRBuilder.buildConstant(SrcTy, 0x00800000); 5948 5949 auto R = MIRBuilder.buildOr(SrcTy, AndMantissaMask, K); 5950 R = MIRBuilder.buildZExt(DstTy, R); 5951 5952 auto Bias = MIRBuilder.buildConstant(SrcTy, 127); 5953 auto Exponent = MIRBuilder.buildSub(SrcTy, ExponentBits, Bias); 5954 auto SubExponent = MIRBuilder.buildSub(SrcTy, Exponent, ExponentLoBit); 5955 auto ExponentSub = MIRBuilder.buildSub(SrcTy, ExponentLoBit, Exponent); 5956 5957 auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent); 5958 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); 5959 5960 const LLT S1 = LLT::scalar(1); 5961 auto CmpGt = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, 5962 S1, Exponent, ExponentLoBit); 5963 5964 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl); 5965 5966 auto XorSign = MIRBuilder.buildXor(DstTy, R, Sign); 5967 auto Ret = MIRBuilder.buildSub(DstTy, XorSign, Sign); 5968 5969 auto ZeroSrcTy = MIRBuilder.buildConstant(SrcTy, 0); 5970 5971 auto ExponentLt0 = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, 5972 S1, Exponent, ZeroSrcTy); 5973 5974 auto ZeroDstTy = MIRBuilder.buildConstant(DstTy, 0); 5975 MIRBuilder.buildSelect(Dst, ExponentLt0, ZeroDstTy, Ret); 5976 5977 MI.eraseFromParent(); 5978 return Legalized; 5979 } 5980 5981 // f64 -> f16 conversion using round-to-nearest-even rounding mode. 5982 LegalizerHelper::LegalizeResult 5983 LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) { 5984 Register Dst = MI.getOperand(0).getReg(); 5985 Register Src = MI.getOperand(1).getReg(); 5986 5987 if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly. 5988 return UnableToLegalize; 5989 5990 const unsigned ExpMask = 0x7ff; 5991 const unsigned ExpBiasf64 = 1023; 5992 const unsigned ExpBiasf16 = 15; 5993 const LLT S32 = LLT::scalar(32); 5994 const LLT S1 = LLT::scalar(1); 5995 5996 auto Unmerge = MIRBuilder.buildUnmerge(S32, Src); 5997 Register U = Unmerge.getReg(0); 5998 Register UH = Unmerge.getReg(1); 5999 6000 auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20)); 6001 E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask)); 6002 6003 // Subtract the fp64 exponent bias (1023) to get the real exponent and 6004 // add the f16 bias (15) to get the biased exponent for the f16 format. 6005 E = MIRBuilder.buildAdd( 6006 S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16)); 6007 6008 auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8)); 6009 M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe)); 6010 6011 auto MaskedSig = MIRBuilder.buildAnd(S32, UH, 6012 MIRBuilder.buildConstant(S32, 0x1ff)); 6013 MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U); 6014 6015 auto Zero = MIRBuilder.buildConstant(S32, 0); 6016 auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero); 6017 auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0); 6018 M = MIRBuilder.buildOr(S32, M, Lo40Set); 6019 6020 // (M != 0 ? 0x0200 : 0) | 0x7c00; 6021 auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200); 6022 auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero); 6023 auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero); 6024 6025 auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00); 6026 auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00); 6027 6028 // N = M | (E << 12); 6029 auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12)); 6030 auto N = MIRBuilder.buildOr(S32, M, EShl12); 6031 6032 // B = clamp(1-E, 0, 13); 6033 auto One = MIRBuilder.buildConstant(S32, 1); 6034 auto OneSubExp = MIRBuilder.buildSub(S32, One, E); 6035 auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero); 6036 B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13)); 6037 6038 auto SigSetHigh = MIRBuilder.buildOr(S32, M, 6039 MIRBuilder.buildConstant(S32, 0x1000)); 6040 6041 auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B); 6042 auto D0 = MIRBuilder.buildShl(S32, D, B); 6043 6044 auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, 6045 D0, SigSetHigh); 6046 auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh); 6047 D = MIRBuilder.buildOr(S32, D, D1); 6048 6049 auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One); 6050 auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N); 6051 6052 auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7)); 6053 V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2)); 6054 6055 auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3, 6056 MIRBuilder.buildConstant(S32, 3)); 6057 auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3); 6058 6059 auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3, 6060 MIRBuilder.buildConstant(S32, 5)); 6061 auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5); 6062 6063 V1 = MIRBuilder.buildOr(S32, V0, V1); 6064 V = MIRBuilder.buildAdd(S32, V, V1); 6065 6066 auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, 6067 E, MIRBuilder.buildConstant(S32, 30)); 6068 V = MIRBuilder.buildSelect(S32, CmpEGt30, 6069 MIRBuilder.buildConstant(S32, 0x7c00), V); 6070 6071 auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, 6072 E, MIRBuilder.buildConstant(S32, 1039)); 6073 V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V); 6074 6075 // Extract the sign bit. 6076 auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16)); 6077 Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000)); 6078 6079 // Insert the sign bit 6080 V = MIRBuilder.buildOr(S32, Sign, V); 6081 6082 MIRBuilder.buildTrunc(Dst, V); 6083 MI.eraseFromParent(); 6084 return Legalized; 6085 } 6086 6087 LegalizerHelper::LegalizeResult 6088 LegalizerHelper::lowerFPTRUNC(MachineInstr &MI) { 6089 Register Dst = MI.getOperand(0).getReg(); 6090 Register Src = MI.getOperand(1).getReg(); 6091 6092 LLT DstTy = MRI.getType(Dst); 6093 LLT SrcTy = MRI.getType(Src); 6094 const LLT S64 = LLT::scalar(64); 6095 const LLT S16 = LLT::scalar(16); 6096 6097 if (DstTy.getScalarType() == S16 && SrcTy.getScalarType() == S64) 6098 return lowerFPTRUNC_F64_TO_F16(MI); 6099 6100 return UnableToLegalize; 6101 } 6102 6103 // TODO: If RHS is a constant SelectionDAGBuilder expands this into a 6104 // multiplication tree. 6105 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPOWI(MachineInstr &MI) { 6106 Register Dst = MI.getOperand(0).getReg(); 6107 Register Src0 = MI.getOperand(1).getReg(); 6108 Register Src1 = MI.getOperand(2).getReg(); 6109 LLT Ty = MRI.getType(Dst); 6110 6111 auto CvtSrc1 = MIRBuilder.buildSITOFP(Ty, Src1); 6112 MIRBuilder.buildFPow(Dst, Src0, CvtSrc1, MI.getFlags()); 6113 MI.eraseFromParent(); 6114 return Legalized; 6115 } 6116 6117 static CmpInst::Predicate minMaxToCompare(unsigned Opc) { 6118 switch (Opc) { 6119 case TargetOpcode::G_SMIN: 6120 return CmpInst::ICMP_SLT; 6121 case TargetOpcode::G_SMAX: 6122 return CmpInst::ICMP_SGT; 6123 case TargetOpcode::G_UMIN: 6124 return CmpInst::ICMP_ULT; 6125 case TargetOpcode::G_UMAX: 6126 return CmpInst::ICMP_UGT; 6127 default: 6128 llvm_unreachable("not in integer min/max"); 6129 } 6130 } 6131 6132 LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) { 6133 Register Dst = MI.getOperand(0).getReg(); 6134 Register Src0 = MI.getOperand(1).getReg(); 6135 Register Src1 = MI.getOperand(2).getReg(); 6136 6137 const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode()); 6138 LLT CmpType = MRI.getType(Dst).changeElementSize(1); 6139 6140 auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1); 6141 MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1); 6142 6143 MI.eraseFromParent(); 6144 return Legalized; 6145 } 6146 6147 LegalizerHelper::LegalizeResult 6148 LegalizerHelper::lowerFCopySign(MachineInstr &MI) { 6149 Register Dst = MI.getOperand(0).getReg(); 6150 Register Src0 = MI.getOperand(1).getReg(); 6151 Register Src1 = MI.getOperand(2).getReg(); 6152 6153 const LLT Src0Ty = MRI.getType(Src0); 6154 const LLT Src1Ty = MRI.getType(Src1); 6155 6156 const int Src0Size = Src0Ty.getScalarSizeInBits(); 6157 const int Src1Size = Src1Ty.getScalarSizeInBits(); 6158 6159 auto SignBitMask = MIRBuilder.buildConstant( 6160 Src0Ty, APInt::getSignMask(Src0Size)); 6161 6162 auto NotSignBitMask = MIRBuilder.buildConstant( 6163 Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1)); 6164 6165 Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask).getReg(0); 6166 Register And1; 6167 if (Src0Ty == Src1Ty) { 6168 And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask).getReg(0); 6169 } else if (Src0Size > Src1Size) { 6170 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size); 6171 auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1); 6172 auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt); 6173 And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0); 6174 } else { 6175 auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size); 6176 auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt); 6177 auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift); 6178 And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask).getReg(0); 6179 } 6180 6181 // Be careful about setting nsz/nnan/ninf on every instruction, since the 6182 // constants are a nan and -0.0, but the final result should preserve 6183 // everything. 6184 unsigned Flags = MI.getFlags(); 6185 MIRBuilder.buildOr(Dst, And0, And1, Flags); 6186 6187 MI.eraseFromParent(); 6188 return Legalized; 6189 } 6190 6191 LegalizerHelper::LegalizeResult 6192 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) { 6193 unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ? 6194 TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE; 6195 6196 Register Dst = MI.getOperand(0).getReg(); 6197 Register Src0 = MI.getOperand(1).getReg(); 6198 Register Src1 = MI.getOperand(2).getReg(); 6199 LLT Ty = MRI.getType(Dst); 6200 6201 if (!MI.getFlag(MachineInstr::FmNoNans)) { 6202 // Insert canonicalizes if it's possible we need to quiet to get correct 6203 // sNaN behavior. 6204 6205 // Note this must be done here, and not as an optimization combine in the 6206 // absence of a dedicate quiet-snan instruction as we're using an 6207 // omni-purpose G_FCANONICALIZE. 6208 if (!isKnownNeverSNaN(Src0, MRI)) 6209 Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0); 6210 6211 if (!isKnownNeverSNaN(Src1, MRI)) 6212 Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0); 6213 } 6214 6215 // If there are no nans, it's safe to simply replace this with the non-IEEE 6216 // version. 6217 MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags()); 6218 MI.eraseFromParent(); 6219 return Legalized; 6220 } 6221 6222 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) { 6223 // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c 6224 Register DstReg = MI.getOperand(0).getReg(); 6225 LLT Ty = MRI.getType(DstReg); 6226 unsigned Flags = MI.getFlags(); 6227 6228 auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2), 6229 Flags); 6230 MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags); 6231 MI.eraseFromParent(); 6232 return Legalized; 6233 } 6234 6235 LegalizerHelper::LegalizeResult 6236 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) { 6237 Register DstReg = MI.getOperand(0).getReg(); 6238 Register X = MI.getOperand(1).getReg(); 6239 const unsigned Flags = MI.getFlags(); 6240 const LLT Ty = MRI.getType(DstReg); 6241 const LLT CondTy = Ty.changeElementSize(1); 6242 6243 // round(x) => 6244 // t = trunc(x); 6245 // d = fabs(x - t); 6246 // o = copysign(1.0f, x); 6247 // return t + (d >= 0.5 ? o : 0.0); 6248 6249 auto T = MIRBuilder.buildIntrinsicTrunc(Ty, X, Flags); 6250 6251 auto Diff = MIRBuilder.buildFSub(Ty, X, T, Flags); 6252 auto AbsDiff = MIRBuilder.buildFAbs(Ty, Diff, Flags); 6253 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 6254 auto One = MIRBuilder.buildFConstant(Ty, 1.0); 6255 auto Half = MIRBuilder.buildFConstant(Ty, 0.5); 6256 auto SignOne = MIRBuilder.buildFCopysign(Ty, One, X); 6257 6258 auto Cmp = MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half, 6259 Flags); 6260 auto Sel = MIRBuilder.buildSelect(Ty, Cmp, SignOne, Zero, Flags); 6261 6262 MIRBuilder.buildFAdd(DstReg, T, Sel, Flags); 6263 6264 MI.eraseFromParent(); 6265 return Legalized; 6266 } 6267 6268 LegalizerHelper::LegalizeResult 6269 LegalizerHelper::lowerFFloor(MachineInstr &MI) { 6270 Register DstReg = MI.getOperand(0).getReg(); 6271 Register SrcReg = MI.getOperand(1).getReg(); 6272 unsigned Flags = MI.getFlags(); 6273 LLT Ty = MRI.getType(DstReg); 6274 const LLT CondTy = Ty.changeElementSize(1); 6275 6276 // result = trunc(src); 6277 // if (src < 0.0 && src != result) 6278 // result += -1.0. 6279 6280 auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags); 6281 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 6282 6283 auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy, 6284 SrcReg, Zero, Flags); 6285 auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy, 6286 SrcReg, Trunc, Flags); 6287 auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc); 6288 auto AddVal = MIRBuilder.buildSITOFP(Ty, And); 6289 6290 MIRBuilder.buildFAdd(DstReg, Trunc, AddVal, Flags); 6291 MI.eraseFromParent(); 6292 return Legalized; 6293 } 6294 6295 LegalizerHelper::LegalizeResult 6296 LegalizerHelper::lowerMergeValues(MachineInstr &MI) { 6297 const unsigned NumOps = MI.getNumOperands(); 6298 Register DstReg = MI.getOperand(0).getReg(); 6299 Register Src0Reg = MI.getOperand(1).getReg(); 6300 LLT DstTy = MRI.getType(DstReg); 6301 LLT SrcTy = MRI.getType(Src0Reg); 6302 unsigned PartSize = SrcTy.getSizeInBits(); 6303 6304 LLT WideTy = LLT::scalar(DstTy.getSizeInBits()); 6305 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); 6306 6307 for (unsigned I = 2; I != NumOps; ++I) { 6308 const unsigned Offset = (I - 1) * PartSize; 6309 6310 Register SrcReg = MI.getOperand(I).getReg(); 6311 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 6312 6313 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 6314 MRI.createGenericVirtualRegister(WideTy); 6315 6316 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 6317 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 6318 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 6319 ResultReg = NextResult; 6320 } 6321 6322 if (DstTy.isPointer()) { 6323 if (MIRBuilder.getDataLayout().isNonIntegralAddressSpace( 6324 DstTy.getAddressSpace())) { 6325 LLVM_DEBUG(dbgs() << "Not casting nonintegral address space\n"); 6326 return UnableToLegalize; 6327 } 6328 6329 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 6330 } 6331 6332 MI.eraseFromParent(); 6333 return Legalized; 6334 } 6335 6336 LegalizerHelper::LegalizeResult 6337 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) { 6338 const unsigned NumDst = MI.getNumOperands() - 1; 6339 Register SrcReg = MI.getOperand(NumDst).getReg(); 6340 Register Dst0Reg = MI.getOperand(0).getReg(); 6341 LLT DstTy = MRI.getType(Dst0Reg); 6342 if (DstTy.isPointer()) 6343 return UnableToLegalize; // TODO 6344 6345 SrcReg = coerceToScalar(SrcReg); 6346 if (!SrcReg) 6347 return UnableToLegalize; 6348 6349 // Expand scalarizing unmerge as bitcast to integer and shift. 6350 LLT IntTy = MRI.getType(SrcReg); 6351 6352 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 6353 6354 const unsigned DstSize = DstTy.getSizeInBits(); 6355 unsigned Offset = DstSize; 6356 for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) { 6357 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset); 6358 auto Shift = MIRBuilder.buildLShr(IntTy, SrcReg, ShiftAmt); 6359 MIRBuilder.buildTrunc(MI.getOperand(I), Shift); 6360 } 6361 6362 MI.eraseFromParent(); 6363 return Legalized; 6364 } 6365 6366 /// Lower a vector extract or insert by writing the vector to a stack temporary 6367 /// and reloading the element or vector. 6368 /// 6369 /// %dst = G_EXTRACT_VECTOR_ELT %vec, %idx 6370 /// => 6371 /// %stack_temp = G_FRAME_INDEX 6372 /// G_STORE %vec, %stack_temp 6373 /// %idx = clamp(%idx, %vec.getNumElements()) 6374 /// %element_ptr = G_PTR_ADD %stack_temp, %idx 6375 /// %dst = G_LOAD %element_ptr 6376 LegalizerHelper::LegalizeResult 6377 LegalizerHelper::lowerExtractInsertVectorElt(MachineInstr &MI) { 6378 Register DstReg = MI.getOperand(0).getReg(); 6379 Register SrcVec = MI.getOperand(1).getReg(); 6380 Register InsertVal; 6381 if (MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT) 6382 InsertVal = MI.getOperand(2).getReg(); 6383 6384 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 6385 6386 LLT VecTy = MRI.getType(SrcVec); 6387 LLT EltTy = VecTy.getElementType(); 6388 if (!EltTy.isByteSized()) { // Not implemented. 6389 LLVM_DEBUG(dbgs() << "Can't handle non-byte element vectors yet\n"); 6390 return UnableToLegalize; 6391 } 6392 6393 unsigned EltBytes = EltTy.getSizeInBytes(); 6394 Align VecAlign = getStackTemporaryAlignment(VecTy); 6395 Align EltAlign; 6396 6397 MachinePointerInfo PtrInfo; 6398 auto StackTemp = createStackTemporary(TypeSize::Fixed(VecTy.getSizeInBytes()), 6399 VecAlign, PtrInfo); 6400 MIRBuilder.buildStore(SrcVec, StackTemp, PtrInfo, VecAlign); 6401 6402 // Get the pointer to the element, and be sure not to hit undefined behavior 6403 // if the index is out of bounds. 6404 Register EltPtr = getVectorElementPointer(StackTemp.getReg(0), VecTy, Idx); 6405 6406 int64_t IdxVal; 6407 if (mi_match(Idx, MRI, m_ICst(IdxVal))) { 6408 int64_t Offset = IdxVal * EltBytes; 6409 PtrInfo = PtrInfo.getWithOffset(Offset); 6410 EltAlign = commonAlignment(VecAlign, Offset); 6411 } else { 6412 // We lose information with a variable offset. 6413 EltAlign = getStackTemporaryAlignment(EltTy); 6414 PtrInfo = MachinePointerInfo(MRI.getType(EltPtr).getAddressSpace()); 6415 } 6416 6417 if (InsertVal) { 6418 // Write the inserted element 6419 MIRBuilder.buildStore(InsertVal, EltPtr, PtrInfo, EltAlign); 6420 6421 // Reload the whole vector. 6422 MIRBuilder.buildLoad(DstReg, StackTemp, PtrInfo, VecAlign); 6423 } else { 6424 MIRBuilder.buildLoad(DstReg, EltPtr, PtrInfo, EltAlign); 6425 } 6426 6427 MI.eraseFromParent(); 6428 return Legalized; 6429 } 6430 6431 LegalizerHelper::LegalizeResult 6432 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) { 6433 Register DstReg = MI.getOperand(0).getReg(); 6434 Register Src0Reg = MI.getOperand(1).getReg(); 6435 Register Src1Reg = MI.getOperand(2).getReg(); 6436 LLT Src0Ty = MRI.getType(Src0Reg); 6437 LLT DstTy = MRI.getType(DstReg); 6438 LLT IdxTy = LLT::scalar(32); 6439 6440 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 6441 6442 if (DstTy.isScalar()) { 6443 if (Src0Ty.isVector()) 6444 return UnableToLegalize; 6445 6446 // This is just a SELECT. 6447 assert(Mask.size() == 1 && "Expected a single mask element"); 6448 Register Val; 6449 if (Mask[0] < 0 || Mask[0] > 1) 6450 Val = MIRBuilder.buildUndef(DstTy).getReg(0); 6451 else 6452 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; 6453 MIRBuilder.buildCopy(DstReg, Val); 6454 MI.eraseFromParent(); 6455 return Legalized; 6456 } 6457 6458 Register Undef; 6459 SmallVector<Register, 32> BuildVec; 6460 LLT EltTy = DstTy.getElementType(); 6461 6462 for (int Idx : Mask) { 6463 if (Idx < 0) { 6464 if (!Undef.isValid()) 6465 Undef = MIRBuilder.buildUndef(EltTy).getReg(0); 6466 BuildVec.push_back(Undef); 6467 continue; 6468 } 6469 6470 if (Src0Ty.isScalar()) { 6471 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); 6472 } else { 6473 int NumElts = Src0Ty.getNumElements(); 6474 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; 6475 int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts; 6476 auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx); 6477 auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK); 6478 BuildVec.push_back(Extract.getReg(0)); 6479 } 6480 } 6481 6482 MIRBuilder.buildBuildVector(DstReg, BuildVec); 6483 MI.eraseFromParent(); 6484 return Legalized; 6485 } 6486 6487 LegalizerHelper::LegalizeResult 6488 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) { 6489 const auto &MF = *MI.getMF(); 6490 const auto &TFI = *MF.getSubtarget().getFrameLowering(); 6491 if (TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp) 6492 return UnableToLegalize; 6493 6494 Register Dst = MI.getOperand(0).getReg(); 6495 Register AllocSize = MI.getOperand(1).getReg(); 6496 Align Alignment = assumeAligned(MI.getOperand(2).getImm()); 6497 6498 LLT PtrTy = MRI.getType(Dst); 6499 LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits()); 6500 6501 Register SPReg = TLI.getStackPointerRegisterToSaveRestore(); 6502 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); 6503 SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp); 6504 6505 // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't 6506 // have to generate an extra instruction to negate the alloc and then use 6507 // G_PTR_ADD to add the negative offset. 6508 auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize); 6509 if (Alignment > Align(1)) { 6510 APInt AlignMask(IntPtrTy.getSizeInBits(), Alignment.value(), true); 6511 AlignMask.negate(); 6512 auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask); 6513 Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst); 6514 } 6515 6516 SPTmp = MIRBuilder.buildCast(PtrTy, Alloc); 6517 MIRBuilder.buildCopy(SPReg, SPTmp); 6518 MIRBuilder.buildCopy(Dst, SPTmp); 6519 6520 MI.eraseFromParent(); 6521 return Legalized; 6522 } 6523 6524 LegalizerHelper::LegalizeResult 6525 LegalizerHelper::lowerExtract(MachineInstr &MI) { 6526 Register Dst = MI.getOperand(0).getReg(); 6527 Register Src = MI.getOperand(1).getReg(); 6528 unsigned Offset = MI.getOperand(2).getImm(); 6529 6530 LLT DstTy = MRI.getType(Dst); 6531 LLT SrcTy = MRI.getType(Src); 6532 6533 if (DstTy.isScalar() && 6534 (SrcTy.isScalar() || 6535 (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) { 6536 LLT SrcIntTy = SrcTy; 6537 if (!SrcTy.isScalar()) { 6538 SrcIntTy = LLT::scalar(SrcTy.getSizeInBits()); 6539 Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0); 6540 } 6541 6542 if (Offset == 0) 6543 MIRBuilder.buildTrunc(Dst, Src); 6544 else { 6545 auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset); 6546 auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt); 6547 MIRBuilder.buildTrunc(Dst, Shr); 6548 } 6549 6550 MI.eraseFromParent(); 6551 return Legalized; 6552 } 6553 6554 return UnableToLegalize; 6555 } 6556 6557 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) { 6558 Register Dst = MI.getOperand(0).getReg(); 6559 Register Src = MI.getOperand(1).getReg(); 6560 Register InsertSrc = MI.getOperand(2).getReg(); 6561 uint64_t Offset = MI.getOperand(3).getImm(); 6562 6563 LLT DstTy = MRI.getType(Src); 6564 LLT InsertTy = MRI.getType(InsertSrc); 6565 6566 if (InsertTy.isVector() || 6567 (DstTy.isVector() && DstTy.getElementType() != InsertTy)) 6568 return UnableToLegalize; 6569 6570 const DataLayout &DL = MIRBuilder.getDataLayout(); 6571 if ((DstTy.isPointer() && 6572 DL.isNonIntegralAddressSpace(DstTy.getAddressSpace())) || 6573 (InsertTy.isPointer() && 6574 DL.isNonIntegralAddressSpace(InsertTy.getAddressSpace()))) { 6575 LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n"); 6576 return UnableToLegalize; 6577 } 6578 6579 LLT IntDstTy = DstTy; 6580 6581 if (!DstTy.isScalar()) { 6582 IntDstTy = LLT::scalar(DstTy.getSizeInBits()); 6583 Src = MIRBuilder.buildCast(IntDstTy, Src).getReg(0); 6584 } 6585 6586 if (!InsertTy.isScalar()) { 6587 const LLT IntInsertTy = LLT::scalar(InsertTy.getSizeInBits()); 6588 InsertSrc = MIRBuilder.buildPtrToInt(IntInsertTy, InsertSrc).getReg(0); 6589 } 6590 6591 Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0); 6592 if (Offset != 0) { 6593 auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset); 6594 ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0); 6595 } 6596 6597 APInt MaskVal = APInt::getBitsSetWithWrap( 6598 DstTy.getSizeInBits(), Offset + InsertTy.getSizeInBits(), Offset); 6599 6600 auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal); 6601 auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask); 6602 auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc); 6603 6604 MIRBuilder.buildCast(Dst, Or); 6605 MI.eraseFromParent(); 6606 return Legalized; 6607 } 6608 6609 LegalizerHelper::LegalizeResult 6610 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) { 6611 Register Dst0 = MI.getOperand(0).getReg(); 6612 Register Dst1 = MI.getOperand(1).getReg(); 6613 Register LHS = MI.getOperand(2).getReg(); 6614 Register RHS = MI.getOperand(3).getReg(); 6615 const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO; 6616 6617 LLT Ty = MRI.getType(Dst0); 6618 LLT BoolTy = MRI.getType(Dst1); 6619 6620 if (IsAdd) 6621 MIRBuilder.buildAdd(Dst0, LHS, RHS); 6622 else 6623 MIRBuilder.buildSub(Dst0, LHS, RHS); 6624 6625 // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow. 6626 6627 auto Zero = MIRBuilder.buildConstant(Ty, 0); 6628 6629 // For an addition, the result should be less than one of the operands (LHS) 6630 // if and only if the other operand (RHS) is negative, otherwise there will 6631 // be overflow. 6632 // For a subtraction, the result should be less than one of the operands 6633 // (LHS) if and only if the other operand (RHS) is (non-zero) positive, 6634 // otherwise there will be overflow. 6635 auto ResultLowerThanLHS = 6636 MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS); 6637 auto ConditionRHS = MIRBuilder.buildICmp( 6638 IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero); 6639 6640 MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS); 6641 MI.eraseFromParent(); 6642 return Legalized; 6643 } 6644 6645 LegalizerHelper::LegalizeResult 6646 LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI) { 6647 Register Res = MI.getOperand(0).getReg(); 6648 Register LHS = MI.getOperand(1).getReg(); 6649 Register RHS = MI.getOperand(2).getReg(); 6650 LLT Ty = MRI.getType(Res); 6651 bool IsSigned; 6652 bool IsAdd; 6653 unsigned BaseOp; 6654 switch (MI.getOpcode()) { 6655 default: 6656 llvm_unreachable("unexpected addsat/subsat opcode"); 6657 case TargetOpcode::G_UADDSAT: 6658 IsSigned = false; 6659 IsAdd = true; 6660 BaseOp = TargetOpcode::G_ADD; 6661 break; 6662 case TargetOpcode::G_SADDSAT: 6663 IsSigned = true; 6664 IsAdd = true; 6665 BaseOp = TargetOpcode::G_ADD; 6666 break; 6667 case TargetOpcode::G_USUBSAT: 6668 IsSigned = false; 6669 IsAdd = false; 6670 BaseOp = TargetOpcode::G_SUB; 6671 break; 6672 case TargetOpcode::G_SSUBSAT: 6673 IsSigned = true; 6674 IsAdd = false; 6675 BaseOp = TargetOpcode::G_SUB; 6676 break; 6677 } 6678 6679 if (IsSigned) { 6680 // sadd.sat(a, b) -> 6681 // hi = 0x7fffffff - smax(a, 0) 6682 // lo = 0x80000000 - smin(a, 0) 6683 // a + smin(smax(lo, b), hi) 6684 // ssub.sat(a, b) -> 6685 // lo = smax(a, -1) - 0x7fffffff 6686 // hi = smin(a, -1) - 0x80000000 6687 // a - smin(smax(lo, b), hi) 6688 // TODO: AMDGPU can use a "median of 3" instruction here: 6689 // a +/- med3(lo, b, hi) 6690 uint64_t NumBits = Ty.getScalarSizeInBits(); 6691 auto MaxVal = 6692 MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(NumBits)); 6693 auto MinVal = 6694 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6695 MachineInstrBuilder Hi, Lo; 6696 if (IsAdd) { 6697 auto Zero = MIRBuilder.buildConstant(Ty, 0); 6698 Hi = MIRBuilder.buildSub(Ty, MaxVal, MIRBuilder.buildSMax(Ty, LHS, Zero)); 6699 Lo = MIRBuilder.buildSub(Ty, MinVal, MIRBuilder.buildSMin(Ty, LHS, Zero)); 6700 } else { 6701 auto NegOne = MIRBuilder.buildConstant(Ty, -1); 6702 Lo = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMax(Ty, LHS, NegOne), 6703 MaxVal); 6704 Hi = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMin(Ty, LHS, NegOne), 6705 MinVal); 6706 } 6707 auto RHSClamped = 6708 MIRBuilder.buildSMin(Ty, MIRBuilder.buildSMax(Ty, Lo, RHS), Hi); 6709 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped}); 6710 } else { 6711 // uadd.sat(a, b) -> a + umin(~a, b) 6712 // usub.sat(a, b) -> a - umin(a, b) 6713 Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS; 6714 auto Min = MIRBuilder.buildUMin(Ty, Not, RHS); 6715 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min}); 6716 } 6717 6718 MI.eraseFromParent(); 6719 return Legalized; 6720 } 6721 6722 LegalizerHelper::LegalizeResult 6723 LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) { 6724 Register Res = MI.getOperand(0).getReg(); 6725 Register LHS = MI.getOperand(1).getReg(); 6726 Register RHS = MI.getOperand(2).getReg(); 6727 LLT Ty = MRI.getType(Res); 6728 LLT BoolTy = Ty.changeElementSize(1); 6729 bool IsSigned; 6730 bool IsAdd; 6731 unsigned OverflowOp; 6732 switch (MI.getOpcode()) { 6733 default: 6734 llvm_unreachable("unexpected addsat/subsat opcode"); 6735 case TargetOpcode::G_UADDSAT: 6736 IsSigned = false; 6737 IsAdd = true; 6738 OverflowOp = TargetOpcode::G_UADDO; 6739 break; 6740 case TargetOpcode::G_SADDSAT: 6741 IsSigned = true; 6742 IsAdd = true; 6743 OverflowOp = TargetOpcode::G_SADDO; 6744 break; 6745 case TargetOpcode::G_USUBSAT: 6746 IsSigned = false; 6747 IsAdd = false; 6748 OverflowOp = TargetOpcode::G_USUBO; 6749 break; 6750 case TargetOpcode::G_SSUBSAT: 6751 IsSigned = true; 6752 IsAdd = false; 6753 OverflowOp = TargetOpcode::G_SSUBO; 6754 break; 6755 } 6756 6757 auto OverflowRes = 6758 MIRBuilder.buildInstr(OverflowOp, {Ty, BoolTy}, {LHS, RHS}); 6759 Register Tmp = OverflowRes.getReg(0); 6760 Register Ov = OverflowRes.getReg(1); 6761 MachineInstrBuilder Clamp; 6762 if (IsSigned) { 6763 // sadd.sat(a, b) -> 6764 // {tmp, ov} = saddo(a, b) 6765 // ov ? (tmp >>s 31) + 0x80000000 : r 6766 // ssub.sat(a, b) -> 6767 // {tmp, ov} = ssubo(a, b) 6768 // ov ? (tmp >>s 31) + 0x80000000 : r 6769 uint64_t NumBits = Ty.getScalarSizeInBits(); 6770 auto ShiftAmount = MIRBuilder.buildConstant(Ty, NumBits - 1); 6771 auto Sign = MIRBuilder.buildAShr(Ty, Tmp, ShiftAmount); 6772 auto MinVal = 6773 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6774 Clamp = MIRBuilder.buildAdd(Ty, Sign, MinVal); 6775 } else { 6776 // uadd.sat(a, b) -> 6777 // {tmp, ov} = uaddo(a, b) 6778 // ov ? 0xffffffff : tmp 6779 // usub.sat(a, b) -> 6780 // {tmp, ov} = usubo(a, b) 6781 // ov ? 0 : tmp 6782 Clamp = MIRBuilder.buildConstant(Ty, IsAdd ? -1 : 0); 6783 } 6784 MIRBuilder.buildSelect(Res, Ov, Clamp, Tmp); 6785 6786 MI.eraseFromParent(); 6787 return Legalized; 6788 } 6789 6790 LegalizerHelper::LegalizeResult 6791 LegalizerHelper::lowerShlSat(MachineInstr &MI) { 6792 assert((MI.getOpcode() == TargetOpcode::G_SSHLSAT || 6793 MI.getOpcode() == TargetOpcode::G_USHLSAT) && 6794 "Expected shlsat opcode!"); 6795 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SSHLSAT; 6796 Register Res = MI.getOperand(0).getReg(); 6797 Register LHS = MI.getOperand(1).getReg(); 6798 Register RHS = MI.getOperand(2).getReg(); 6799 LLT Ty = MRI.getType(Res); 6800 LLT BoolTy = Ty.changeElementSize(1); 6801 6802 unsigned BW = Ty.getScalarSizeInBits(); 6803 auto Result = MIRBuilder.buildShl(Ty, LHS, RHS); 6804 auto Orig = IsSigned ? MIRBuilder.buildAShr(Ty, Result, RHS) 6805 : MIRBuilder.buildLShr(Ty, Result, RHS); 6806 6807 MachineInstrBuilder SatVal; 6808 if (IsSigned) { 6809 auto SatMin = MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(BW)); 6810 auto SatMax = MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(BW)); 6811 auto Cmp = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, LHS, 6812 MIRBuilder.buildConstant(Ty, 0)); 6813 SatVal = MIRBuilder.buildSelect(Ty, Cmp, SatMin, SatMax); 6814 } else { 6815 SatVal = MIRBuilder.buildConstant(Ty, APInt::getMaxValue(BW)); 6816 } 6817 auto Ov = MIRBuilder.buildICmp(CmpInst::ICMP_NE, BoolTy, LHS, Orig); 6818 MIRBuilder.buildSelect(Res, Ov, SatVal, Result); 6819 6820 MI.eraseFromParent(); 6821 return Legalized; 6822 } 6823 6824 LegalizerHelper::LegalizeResult 6825 LegalizerHelper::lowerBswap(MachineInstr &MI) { 6826 Register Dst = MI.getOperand(0).getReg(); 6827 Register Src = MI.getOperand(1).getReg(); 6828 const LLT Ty = MRI.getType(Src); 6829 unsigned SizeInBytes = (Ty.getScalarSizeInBits() + 7) / 8; 6830 unsigned BaseShiftAmt = (SizeInBytes - 1) * 8; 6831 6832 // Swap most and least significant byte, set remaining bytes in Res to zero. 6833 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt); 6834 auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt); 6835 auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 6836 auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft); 6837 6838 // Set i-th high/low byte in Res to i-th low/high byte from Src. 6839 for (unsigned i = 1; i < SizeInBytes / 2; ++i) { 6840 // AND with Mask leaves byte i unchanged and sets remaining bytes to 0. 6841 APInt APMask(SizeInBytes * 8, 0xFF << (i * 8)); 6842 auto Mask = MIRBuilder.buildConstant(Ty, APMask); 6843 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i); 6844 // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt. 6845 auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask); 6846 auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt); 6847 Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft); 6848 // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask. 6849 auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 6850 auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask); 6851 Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight); 6852 } 6853 Res.getInstr()->getOperand(0).setReg(Dst); 6854 6855 MI.eraseFromParent(); 6856 return Legalized; 6857 } 6858 6859 //{ (Src & Mask) >> N } | { (Src << N) & Mask } 6860 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B, 6861 MachineInstrBuilder Src, APInt Mask) { 6862 const LLT Ty = Dst.getLLTTy(*B.getMRI()); 6863 MachineInstrBuilder C_N = B.buildConstant(Ty, N); 6864 MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask); 6865 auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N); 6866 auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0); 6867 return B.buildOr(Dst, LHS, RHS); 6868 } 6869 6870 LegalizerHelper::LegalizeResult 6871 LegalizerHelper::lowerBitreverse(MachineInstr &MI) { 6872 Register Dst = MI.getOperand(0).getReg(); 6873 Register Src = MI.getOperand(1).getReg(); 6874 const LLT Ty = MRI.getType(Src); 6875 unsigned Size = Ty.getSizeInBits(); 6876 6877 MachineInstrBuilder BSWAP = 6878 MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src}); 6879 6880 // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654 6881 // [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4] 6882 // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0] 6883 MachineInstrBuilder Swap4 = 6884 SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0))); 6885 6886 // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76 6887 // [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2] 6888 // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC] 6889 MachineInstrBuilder Swap2 = 6890 SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC))); 6891 6892 // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7 6893 // [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1] 6894 // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA] 6895 SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA))); 6896 6897 MI.eraseFromParent(); 6898 return Legalized; 6899 } 6900 6901 LegalizerHelper::LegalizeResult 6902 LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) { 6903 MachineFunction &MF = MIRBuilder.getMF(); 6904 6905 bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER; 6906 int NameOpIdx = IsRead ? 1 : 0; 6907 int ValRegIndex = IsRead ? 0 : 1; 6908 6909 Register ValReg = MI.getOperand(ValRegIndex).getReg(); 6910 const LLT Ty = MRI.getType(ValReg); 6911 const MDString *RegStr = cast<MDString>( 6912 cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0)); 6913 6914 Register PhysReg = TLI.getRegisterByName(RegStr->getString().data(), Ty, MF); 6915 if (!PhysReg.isValid()) 6916 return UnableToLegalize; 6917 6918 if (IsRead) 6919 MIRBuilder.buildCopy(ValReg, PhysReg); 6920 else 6921 MIRBuilder.buildCopy(PhysReg, ValReg); 6922 6923 MI.eraseFromParent(); 6924 return Legalized; 6925 } 6926 6927 LegalizerHelper::LegalizeResult 6928 LegalizerHelper::lowerSMULH_UMULH(MachineInstr &MI) { 6929 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULH; 6930 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 6931 Register Result = MI.getOperand(0).getReg(); 6932 LLT OrigTy = MRI.getType(Result); 6933 auto SizeInBits = OrigTy.getScalarSizeInBits(); 6934 LLT WideTy = OrigTy.changeElementSize(SizeInBits * 2); 6935 6936 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)}); 6937 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)}); 6938 auto Mul = MIRBuilder.buildMul(WideTy, LHS, RHS); 6939 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; 6940 6941 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, SizeInBits); 6942 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); 6943 MIRBuilder.buildTrunc(Result, Shifted); 6944 6945 MI.eraseFromParent(); 6946 return Legalized; 6947 } 6948 6949 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) { 6950 // Implement vector G_SELECT in terms of XOR, AND, OR. 6951 Register DstReg = MI.getOperand(0).getReg(); 6952 Register MaskReg = MI.getOperand(1).getReg(); 6953 Register Op1Reg = MI.getOperand(2).getReg(); 6954 Register Op2Reg = MI.getOperand(3).getReg(); 6955 LLT DstTy = MRI.getType(DstReg); 6956 LLT MaskTy = MRI.getType(MaskReg); 6957 LLT Op1Ty = MRI.getType(Op1Reg); 6958 if (!DstTy.isVector()) 6959 return UnableToLegalize; 6960 6961 // Vector selects can have a scalar predicate. If so, splat into a vector and 6962 // finish for later legalization attempts to try again. 6963 if (MaskTy.isScalar()) { 6964 Register MaskElt = MaskReg; 6965 if (MaskTy.getSizeInBits() < DstTy.getScalarSizeInBits()) 6966 MaskElt = MIRBuilder.buildSExt(DstTy.getElementType(), MaskElt).getReg(0); 6967 // Generate a vector splat idiom to be pattern matched later. 6968 auto ShufSplat = MIRBuilder.buildShuffleSplat(DstTy, MaskElt); 6969 Observer.changingInstr(MI); 6970 MI.getOperand(1).setReg(ShufSplat.getReg(0)); 6971 Observer.changedInstr(MI); 6972 return Legalized; 6973 } 6974 6975 if (MaskTy.getSizeInBits() != Op1Ty.getSizeInBits()) { 6976 return UnableToLegalize; 6977 } 6978 6979 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); 6980 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); 6981 auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask); 6982 MIRBuilder.buildOr(DstReg, NewOp1, NewOp2); 6983 MI.eraseFromParent(); 6984 return Legalized; 6985 } 6986 6987 LegalizerHelper::LegalizeResult LegalizerHelper::lowerDIVREM(MachineInstr &MI) { 6988 // Split DIVREM into individual instructions. 6989 unsigned Opcode = MI.getOpcode(); 6990 6991 MIRBuilder.buildInstr( 6992 Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SDIV 6993 : TargetOpcode::G_UDIV, 6994 {MI.getOperand(0).getReg()}, {MI.getOperand(2), MI.getOperand(3)}); 6995 MIRBuilder.buildInstr( 6996 Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SREM 6997 : TargetOpcode::G_UREM, 6998 {MI.getOperand(1).getReg()}, {MI.getOperand(2), MI.getOperand(3)}); 6999 MI.eraseFromParent(); 7000 return Legalized; 7001 } 7002 7003 LegalizerHelper::LegalizeResult 7004 LegalizerHelper::lowerAbsToAddXor(MachineInstr &MI) { 7005 // Expand %res = G_ABS %a into: 7006 // %v1 = G_ASHR %a, scalar_size-1 7007 // %v2 = G_ADD %a, %v1 7008 // %res = G_XOR %v2, %v1 7009 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 7010 Register OpReg = MI.getOperand(1).getReg(); 7011 auto ShiftAmt = 7012 MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - 1); 7013 auto Shift = MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt); 7014 auto Add = MIRBuilder.buildAdd(DstTy, OpReg, Shift); 7015 MIRBuilder.buildXor(MI.getOperand(0).getReg(), Add, Shift); 7016 MI.eraseFromParent(); 7017 return Legalized; 7018 } 7019 7020 LegalizerHelper::LegalizeResult 7021 LegalizerHelper::lowerAbsToMaxNeg(MachineInstr &MI) { 7022 // Expand %res = G_ABS %a into: 7023 // %v1 = G_CONSTANT 0 7024 // %v2 = G_SUB %v1, %a 7025 // %res = G_SMAX %a, %v2 7026 Register SrcReg = MI.getOperand(1).getReg(); 7027 LLT Ty = MRI.getType(SrcReg); 7028 auto Zero = MIRBuilder.buildConstant(Ty, 0).getReg(0); 7029 auto Sub = MIRBuilder.buildSub(Ty, Zero, SrcReg).getReg(0); 7030 MIRBuilder.buildSMax(MI.getOperand(0), SrcReg, Sub); 7031 MI.eraseFromParent(); 7032 return Legalized; 7033 } 7034