1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetFrameLowering.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetLowering.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 
28 #define DEBUG_TYPE "legalizer"
29 
30 using namespace llvm;
31 using namespace LegalizeActions;
32 
33 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
34 ///
35 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
36 /// with any leftover piece as type \p LeftoverTy
37 ///
38 /// Returns -1 in the first element of the pair if the breakdown is not
39 /// satisfiable.
40 static std::pair<int, int>
41 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
42   assert(!LeftoverTy.isValid() && "this is an out argument");
43 
44   unsigned Size = OrigTy.getSizeInBits();
45   unsigned NarrowSize = NarrowTy.getSizeInBits();
46   unsigned NumParts = Size / NarrowSize;
47   unsigned LeftoverSize = Size - NumParts * NarrowSize;
48   assert(Size > NarrowSize);
49 
50   if (LeftoverSize == 0)
51     return {NumParts, 0};
52 
53   if (NarrowTy.isVector()) {
54     unsigned EltSize = OrigTy.getScalarSizeInBits();
55     if (LeftoverSize % EltSize != 0)
56       return {-1, -1};
57     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
58   } else {
59     LeftoverTy = LLT::scalar(LeftoverSize);
60   }
61 
62   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
63   return std::make_pair(NumParts, NumLeftover);
64 }
65 
66 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
67                                  GISelChangeObserver &Observer,
68                                  MachineIRBuilder &Builder)
69     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
70       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
71   MIRBuilder.setMF(MF);
72   MIRBuilder.setChangeObserver(Observer);
73 }
74 
75 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
76                                  GISelChangeObserver &Observer,
77                                  MachineIRBuilder &B)
78     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
79   MIRBuilder.setMF(MF);
80   MIRBuilder.setChangeObserver(Observer);
81 }
82 LegalizerHelper::LegalizeResult
83 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
84   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
85 
86   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
87       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
88     return LI.legalizeIntrinsic(MI, MRI, MIRBuilder) ? Legalized
89                                                      : UnableToLegalize;
90   auto Step = LI.getAction(MI, MRI);
91   switch (Step.Action) {
92   case Legal:
93     LLVM_DEBUG(dbgs() << ".. Already legal\n");
94     return AlreadyLegal;
95   case Libcall:
96     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
97     return libcall(MI);
98   case NarrowScalar:
99     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
100     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
101   case WidenScalar:
102     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
103     return widenScalar(MI, Step.TypeIdx, Step.NewType);
104   case Lower:
105     LLVM_DEBUG(dbgs() << ".. Lower\n");
106     return lower(MI, Step.TypeIdx, Step.NewType);
107   case FewerElements:
108     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
109     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
110   case MoreElements:
111     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
112     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
113   case Custom:
114     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
115     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
116                                                             : UnableToLegalize;
117   default:
118     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
119     return UnableToLegalize;
120   }
121 }
122 
123 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
124                                    SmallVectorImpl<Register> &VRegs) {
125   for (int i = 0; i < NumParts; ++i)
126     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
127   MIRBuilder.buildUnmerge(VRegs, Reg);
128 }
129 
130 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
131                                    LLT MainTy, LLT &LeftoverTy,
132                                    SmallVectorImpl<Register> &VRegs,
133                                    SmallVectorImpl<Register> &LeftoverRegs) {
134   assert(!LeftoverTy.isValid() && "this is an out argument");
135 
136   unsigned RegSize = RegTy.getSizeInBits();
137   unsigned MainSize = MainTy.getSizeInBits();
138   unsigned NumParts = RegSize / MainSize;
139   unsigned LeftoverSize = RegSize - NumParts * MainSize;
140 
141   // Use an unmerge when possible.
142   if (LeftoverSize == 0) {
143     for (unsigned I = 0; I < NumParts; ++I)
144       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
145     MIRBuilder.buildUnmerge(VRegs, Reg);
146     return true;
147   }
148 
149   if (MainTy.isVector()) {
150     unsigned EltSize = MainTy.getScalarSizeInBits();
151     if (LeftoverSize % EltSize != 0)
152       return false;
153     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
154   } else {
155     LeftoverTy = LLT::scalar(LeftoverSize);
156   }
157 
158   // For irregular sizes, extract the individual parts.
159   for (unsigned I = 0; I != NumParts; ++I) {
160     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
161     VRegs.push_back(NewReg);
162     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
163   }
164 
165   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
166        Offset += LeftoverSize) {
167     Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
168     LeftoverRegs.push_back(NewReg);
169     MIRBuilder.buildExtract(NewReg, Reg, Offset);
170   }
171 
172   return true;
173 }
174 
175 static LLT getGCDType(LLT OrigTy, LLT TargetTy) {
176   if (OrigTy.isVector() && TargetTy.isVector()) {
177     assert(OrigTy.getElementType() == TargetTy.getElementType());
178     int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
179                                     TargetTy.getNumElements());
180     return LLT::scalarOrVector(GCD, OrigTy.getElementType());
181   }
182 
183   if (OrigTy.isVector() && !TargetTy.isVector()) {
184     assert(OrigTy.getElementType() == TargetTy);
185     return TargetTy;
186   }
187 
188   assert(!OrigTy.isVector() && !TargetTy.isVector());
189 
190   int GCD = greatestCommonDivisor(OrigTy.getSizeInBits(),
191                                   TargetTy.getSizeInBits());
192   return LLT::scalar(GCD);
193 }
194 
195 void LegalizerHelper::insertParts(Register DstReg,
196                                   LLT ResultTy, LLT PartTy,
197                                   ArrayRef<Register> PartRegs,
198                                   LLT LeftoverTy,
199                                   ArrayRef<Register> LeftoverRegs) {
200   if (!LeftoverTy.isValid()) {
201     assert(LeftoverRegs.empty());
202 
203     if (!ResultTy.isVector()) {
204       MIRBuilder.buildMerge(DstReg, PartRegs);
205       return;
206     }
207 
208     if (PartTy.isVector())
209       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
210     else
211       MIRBuilder.buildBuildVector(DstReg, PartRegs);
212     return;
213   }
214 
215   unsigned PartSize = PartTy.getSizeInBits();
216   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
217 
218   Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
219   MIRBuilder.buildUndef(CurResultReg);
220 
221   unsigned Offset = 0;
222   for (Register PartReg : PartRegs) {
223     Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
224     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
225     CurResultReg = NewResultReg;
226     Offset += PartSize;
227   }
228 
229   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
230     // Use the original output register for the final insert to avoid a copy.
231     Register NewResultReg = (I + 1 == E) ?
232       DstReg : MRI.createGenericVirtualRegister(ResultTy);
233 
234     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
235     CurResultReg = NewResultReg;
236     Offset += LeftoverPartSize;
237   }
238 }
239 
240 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
241   switch (Opcode) {
242   case TargetOpcode::G_SDIV:
243     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
244     switch (Size) {
245     case 32:
246       return RTLIB::SDIV_I32;
247     case 64:
248       return RTLIB::SDIV_I64;
249     case 128:
250       return RTLIB::SDIV_I128;
251     default:
252       llvm_unreachable("unexpected size");
253     }
254   case TargetOpcode::G_UDIV:
255     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
256     switch (Size) {
257     case 32:
258       return RTLIB::UDIV_I32;
259     case 64:
260       return RTLIB::UDIV_I64;
261     case 128:
262       return RTLIB::UDIV_I128;
263     default:
264       llvm_unreachable("unexpected size");
265     }
266   case TargetOpcode::G_SREM:
267     assert((Size == 32 || Size == 64) && "Unsupported size");
268     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
269   case TargetOpcode::G_UREM:
270     assert((Size == 32 || Size == 64) && "Unsupported size");
271     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
272   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
273     assert(Size == 32 && "Unsupported size");
274     return RTLIB::CTLZ_I32;
275   case TargetOpcode::G_FADD:
276     assert((Size == 32 || Size == 64) && "Unsupported size");
277     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
278   case TargetOpcode::G_FSUB:
279     assert((Size == 32 || Size == 64) && "Unsupported size");
280     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
281   case TargetOpcode::G_FMUL:
282     assert((Size == 32 || Size == 64) && "Unsupported size");
283     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
284   case TargetOpcode::G_FDIV:
285     assert((Size == 32 || Size == 64) && "Unsupported size");
286     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
287   case TargetOpcode::G_FEXP:
288     assert((Size == 32 || Size == 64) && "Unsupported size");
289     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
290   case TargetOpcode::G_FEXP2:
291     assert((Size == 32 || Size == 64) && "Unsupported size");
292     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
293   case TargetOpcode::G_FREM:
294     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
295   case TargetOpcode::G_FPOW:
296     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
297   case TargetOpcode::G_FMA:
298     assert((Size == 32 || Size == 64) && "Unsupported size");
299     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
300   case TargetOpcode::G_FSIN:
301     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
302     return Size == 128 ? RTLIB::SIN_F128
303                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
304   case TargetOpcode::G_FCOS:
305     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
306     return Size == 128 ? RTLIB::COS_F128
307                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
308   case TargetOpcode::G_FLOG10:
309     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
310     return Size == 128 ? RTLIB::LOG10_F128
311                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
312   case TargetOpcode::G_FLOG:
313     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
314     return Size == 128 ? RTLIB::LOG_F128
315                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
316   case TargetOpcode::G_FLOG2:
317     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
318     return Size == 128 ? RTLIB::LOG2_F128
319                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
320   case TargetOpcode::G_FCEIL:
321     assert((Size == 32 || Size == 64) && "Unsupported size");
322     return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
323   case TargetOpcode::G_FFLOOR:
324     assert((Size == 32 || Size == 64) && "Unsupported size");
325     return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
326   }
327   llvm_unreachable("Unknown libcall function");
328 }
329 
330 /// True if an instruction is in tail position in its caller. Intended for
331 /// legalizing libcalls as tail calls when possible.
332 static bool isLibCallInTailPosition(MachineInstr &MI) {
333   const Function &F = MI.getParent()->getParent()->getFunction();
334 
335   // Conservatively require the attributes of the call to match those of
336   // the return. Ignore NoAlias and NonNull because they don't affect the
337   // call sequence.
338   AttributeList CallerAttrs = F.getAttributes();
339   if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
340           .removeAttribute(Attribute::NoAlias)
341           .removeAttribute(Attribute::NonNull)
342           .hasAttributes())
343     return false;
344 
345   // It's not safe to eliminate the sign / zero extension of the return value.
346   if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
347       CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
348     return false;
349 
350   // Only tail call if the following instruction is a standard return.
351   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
352   MachineInstr *Next = MI.getNextNode();
353   if (!Next || TII.isTailCall(*Next) || !Next->isReturn())
354     return false;
355 
356   return true;
357 }
358 
359 LegalizerHelper::LegalizeResult
360 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
361                     const CallLowering::ArgInfo &Result,
362                     ArrayRef<CallLowering::ArgInfo> Args) {
363   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
364   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
365   const char *Name = TLI.getLibcallName(Libcall);
366 
367   CallLowering::CallLoweringInfo Info;
368   Info.CallConv = TLI.getLibcallCallingConv(Libcall);
369   Info.Callee = MachineOperand::CreateES(Name);
370   Info.OrigRet = Result;
371   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
372   if (!CLI.lowerCall(MIRBuilder, Info))
373     return LegalizerHelper::UnableToLegalize;
374 
375   return LegalizerHelper::Legalized;
376 }
377 
378 // Useful for libcalls where all operands have the same type.
379 static LegalizerHelper::LegalizeResult
380 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
381               Type *OpType) {
382   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
383 
384   SmallVector<CallLowering::ArgInfo, 3> Args;
385   for (unsigned i = 1; i < MI.getNumOperands(); i++)
386     Args.push_back({MI.getOperand(i).getReg(), OpType});
387   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
388                        Args);
389 }
390 
391 LegalizerHelper::LegalizeResult
392 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
393                        MachineInstr &MI) {
394   assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
395   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
396 
397   SmallVector<CallLowering::ArgInfo, 3> Args;
398   // Add all the args, except for the last which is an imm denoting 'tail'.
399   for (unsigned i = 1; i < MI.getNumOperands() - 1; i++) {
400     Register Reg = MI.getOperand(i).getReg();
401 
402     // Need derive an IR type for call lowering.
403     LLT OpLLT = MRI.getType(Reg);
404     Type *OpTy = nullptr;
405     if (OpLLT.isPointer())
406       OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace());
407     else
408       OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits());
409     Args.push_back({Reg, OpTy});
410   }
411 
412   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
413   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
414   Intrinsic::ID ID = MI.getOperand(0).getIntrinsicID();
415   RTLIB::Libcall RTLibcall;
416   switch (ID) {
417   case Intrinsic::memcpy:
418     RTLibcall = RTLIB::MEMCPY;
419     break;
420   case Intrinsic::memset:
421     RTLibcall = RTLIB::MEMSET;
422     break;
423   case Intrinsic::memmove:
424     RTLibcall = RTLIB::MEMMOVE;
425     break;
426   default:
427     return LegalizerHelper::UnableToLegalize;
428   }
429   const char *Name = TLI.getLibcallName(RTLibcall);
430 
431   MIRBuilder.setInstr(MI);
432 
433   CallLowering::CallLoweringInfo Info;
434   Info.CallConv = TLI.getLibcallCallingConv(RTLibcall);
435   Info.Callee = MachineOperand::CreateES(Name);
436   Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx));
437   Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() == 1 &&
438                     isLibCallInTailPosition(MI);
439 
440   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
441   if (!CLI.lowerCall(MIRBuilder, Info))
442     return LegalizerHelper::UnableToLegalize;
443 
444   if (Info.LoweredTailCall) {
445     assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?");
446     // We must have a return following the call to get past
447     // isLibCallInTailPosition.
448     assert(MI.getNextNode() && MI.getNextNode()->isReturn() &&
449            "Expected instr following MI to be a return?");
450 
451     // We lowered a tail call, so the call is now the return from the block.
452     // Delete the old return.
453     MI.getNextNode()->eraseFromParent();
454   }
455 
456   return LegalizerHelper::Legalized;
457 }
458 
459 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
460                                        Type *FromType) {
461   auto ToMVT = MVT::getVT(ToType);
462   auto FromMVT = MVT::getVT(FromType);
463 
464   switch (Opcode) {
465   case TargetOpcode::G_FPEXT:
466     return RTLIB::getFPEXT(FromMVT, ToMVT);
467   case TargetOpcode::G_FPTRUNC:
468     return RTLIB::getFPROUND(FromMVT, ToMVT);
469   case TargetOpcode::G_FPTOSI:
470     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
471   case TargetOpcode::G_FPTOUI:
472     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
473   case TargetOpcode::G_SITOFP:
474     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
475   case TargetOpcode::G_UITOFP:
476     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
477   }
478   llvm_unreachable("Unsupported libcall function");
479 }
480 
481 static LegalizerHelper::LegalizeResult
482 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
483                   Type *FromType) {
484   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
485   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
486                        {{MI.getOperand(1).getReg(), FromType}});
487 }
488 
489 LegalizerHelper::LegalizeResult
490 LegalizerHelper::libcall(MachineInstr &MI) {
491   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
492   unsigned Size = LLTy.getSizeInBits();
493   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
494 
495   MIRBuilder.setInstr(MI);
496 
497   switch (MI.getOpcode()) {
498   default:
499     return UnableToLegalize;
500   case TargetOpcode::G_SDIV:
501   case TargetOpcode::G_UDIV:
502   case TargetOpcode::G_SREM:
503   case TargetOpcode::G_UREM:
504   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
505     Type *HLTy = IntegerType::get(Ctx, Size);
506     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
507     if (Status != Legalized)
508       return Status;
509     break;
510   }
511   case TargetOpcode::G_FADD:
512   case TargetOpcode::G_FSUB:
513   case TargetOpcode::G_FMUL:
514   case TargetOpcode::G_FDIV:
515   case TargetOpcode::G_FMA:
516   case TargetOpcode::G_FPOW:
517   case TargetOpcode::G_FREM:
518   case TargetOpcode::G_FCOS:
519   case TargetOpcode::G_FSIN:
520   case TargetOpcode::G_FLOG10:
521   case TargetOpcode::G_FLOG:
522   case TargetOpcode::G_FLOG2:
523   case TargetOpcode::G_FEXP:
524   case TargetOpcode::G_FEXP2:
525   case TargetOpcode::G_FCEIL:
526   case TargetOpcode::G_FFLOOR: {
527     if (Size > 64) {
528       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
529       return UnableToLegalize;
530     }
531     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
532     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
533     if (Status != Legalized)
534       return Status;
535     break;
536   }
537   case TargetOpcode::G_FPEXT: {
538     // FIXME: Support other floating point types (half, fp128 etc)
539     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
540     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
541     if (ToSize != 64 || FromSize != 32)
542       return UnableToLegalize;
543     LegalizeResult Status = conversionLibcall(
544         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
545     if (Status != Legalized)
546       return Status;
547     break;
548   }
549   case TargetOpcode::G_FPTRUNC: {
550     // FIXME: Support other floating point types (half, fp128 etc)
551     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
552     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
553     if (ToSize != 32 || FromSize != 64)
554       return UnableToLegalize;
555     LegalizeResult Status = conversionLibcall(
556         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
557     if (Status != Legalized)
558       return Status;
559     break;
560   }
561   case TargetOpcode::G_FPTOSI:
562   case TargetOpcode::G_FPTOUI: {
563     // FIXME: Support other types
564     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
565     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
566     if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
567       return UnableToLegalize;
568     LegalizeResult Status = conversionLibcall(
569         MI, MIRBuilder,
570         ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
571         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
572     if (Status != Legalized)
573       return Status;
574     break;
575   }
576   case TargetOpcode::G_SITOFP:
577   case TargetOpcode::G_UITOFP: {
578     // FIXME: Support other types
579     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
580     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
581     if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
582       return UnableToLegalize;
583     LegalizeResult Status = conversionLibcall(
584         MI, MIRBuilder,
585         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
586         FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
587     if (Status != Legalized)
588       return Status;
589     break;
590   }
591   }
592 
593   MI.eraseFromParent();
594   return Legalized;
595 }
596 
597 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
598                                                               unsigned TypeIdx,
599                                                               LLT NarrowTy) {
600   MIRBuilder.setInstr(MI);
601 
602   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
603   uint64_t NarrowSize = NarrowTy.getSizeInBits();
604 
605   switch (MI.getOpcode()) {
606   default:
607     return UnableToLegalize;
608   case TargetOpcode::G_IMPLICIT_DEF: {
609     // FIXME: add support for when SizeOp0 isn't an exact multiple of
610     // NarrowSize.
611     if (SizeOp0 % NarrowSize != 0)
612       return UnableToLegalize;
613     int NumParts = SizeOp0 / NarrowSize;
614 
615     SmallVector<Register, 2> DstRegs;
616     for (int i = 0; i < NumParts; ++i)
617       DstRegs.push_back(
618           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
619 
620     Register DstReg = MI.getOperand(0).getReg();
621     if(MRI.getType(DstReg).isVector())
622       MIRBuilder.buildBuildVector(DstReg, DstRegs);
623     else
624       MIRBuilder.buildMerge(DstReg, DstRegs);
625     MI.eraseFromParent();
626     return Legalized;
627   }
628   case TargetOpcode::G_CONSTANT: {
629     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
630     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
631     unsigned TotalSize = Ty.getSizeInBits();
632     unsigned NarrowSize = NarrowTy.getSizeInBits();
633     int NumParts = TotalSize / NarrowSize;
634 
635     SmallVector<Register, 4> PartRegs;
636     for (int I = 0; I != NumParts; ++I) {
637       unsigned Offset = I * NarrowSize;
638       auto K = MIRBuilder.buildConstant(NarrowTy,
639                                         Val.lshr(Offset).trunc(NarrowSize));
640       PartRegs.push_back(K.getReg(0));
641     }
642 
643     LLT LeftoverTy;
644     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
645     SmallVector<Register, 1> LeftoverRegs;
646     if (LeftoverBits != 0) {
647       LeftoverTy = LLT::scalar(LeftoverBits);
648       auto K = MIRBuilder.buildConstant(
649         LeftoverTy,
650         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
651       LeftoverRegs.push_back(K.getReg(0));
652     }
653 
654     insertParts(MI.getOperand(0).getReg(),
655                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
656 
657     MI.eraseFromParent();
658     return Legalized;
659   }
660   case TargetOpcode::G_SEXT:
661   case TargetOpcode::G_ZEXT:
662   case TargetOpcode::G_ANYEXT: {
663     if (TypeIdx != 0)
664       return UnableToLegalize;
665 
666     Register SrcReg = MI.getOperand(1).getReg();
667     LLT SrcTy = MRI.getType(SrcReg);
668     uint64_t SizeOp1 = SrcTy.getSizeInBits();
669     if (SizeOp0 % SizeOp1 != 0)
670       return UnableToLegalize;
671 
672     Register PadReg;
673     if (MI.getOpcode() == TargetOpcode::G_ZEXT)
674       PadReg = MIRBuilder.buildConstant(SrcTy, 0).getReg(0);
675     else if (MI.getOpcode() == TargetOpcode::G_ANYEXT)
676       PadReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
677     else {
678       // Shift the sign bit of the low register through the high register.
679       auto ShiftAmt =
680         MIRBuilder.buildConstant(LLT::scalar(64), SrcTy.getSizeInBits() - 1);
681       PadReg = MIRBuilder.buildAShr(SrcTy, SrcReg, ShiftAmt).getReg(0);
682     }
683 
684     // Generate a merge where the bottom bits are taken from the source, and
685     // zero/impdef/sign bit everything else.
686     unsigned NumParts = SizeOp0 / SizeOp1;
687     SmallVector<Register, 4> Srcs = {SrcReg};
688     for (unsigned Part = 1; Part < NumParts; ++Part)
689       Srcs.push_back(PadReg);
690     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs);
691     MI.eraseFromParent();
692     return Legalized;
693   }
694   case TargetOpcode::G_TRUNC: {
695     if (TypeIdx != 1)
696       return UnableToLegalize;
697 
698     uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
699     if (NarrowTy.getSizeInBits() * 2 != SizeOp1) {
700       LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n");
701       return UnableToLegalize;
702     }
703 
704     auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg());
705     MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0));
706     MI.eraseFromParent();
707     return Legalized;
708   }
709 
710   case TargetOpcode::G_ADD: {
711     // FIXME: add support for when SizeOp0 isn't an exact multiple of
712     // NarrowSize.
713     if (SizeOp0 % NarrowSize != 0)
714       return UnableToLegalize;
715     // Expand in terms of carry-setting/consuming G_ADDE instructions.
716     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
717 
718     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
719     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
720     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
721 
722     Register CarryIn;
723     for (int i = 0; i < NumParts; ++i) {
724       Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
725       Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
726 
727       if (i == 0)
728         MIRBuilder.buildUAddo(DstReg, CarryOut, Src1Regs[i], Src2Regs[i]);
729       else {
730         MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
731                               Src2Regs[i], CarryIn);
732       }
733 
734       DstRegs.push_back(DstReg);
735       CarryIn = CarryOut;
736     }
737     Register DstReg = MI.getOperand(0).getReg();
738     if(MRI.getType(DstReg).isVector())
739       MIRBuilder.buildBuildVector(DstReg, DstRegs);
740     else
741       MIRBuilder.buildMerge(DstReg, DstRegs);
742     MI.eraseFromParent();
743     return Legalized;
744   }
745   case TargetOpcode::G_SUB: {
746     // FIXME: add support for when SizeOp0 isn't an exact multiple of
747     // NarrowSize.
748     if (SizeOp0 % NarrowSize != 0)
749       return UnableToLegalize;
750 
751     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
752 
753     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
754     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
755     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
756 
757     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
758     Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
759     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
760                           {Src1Regs[0], Src2Regs[0]});
761     DstRegs.push_back(DstReg);
762     Register BorrowIn = BorrowOut;
763     for (int i = 1; i < NumParts; ++i) {
764       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
765       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
766 
767       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
768                             {Src1Regs[i], Src2Regs[i], BorrowIn});
769 
770       DstRegs.push_back(DstReg);
771       BorrowIn = BorrowOut;
772     }
773     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
774     MI.eraseFromParent();
775     return Legalized;
776   }
777   case TargetOpcode::G_MUL:
778   case TargetOpcode::G_UMULH:
779     return narrowScalarMul(MI, NarrowTy);
780   case TargetOpcode::G_EXTRACT:
781     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
782   case TargetOpcode::G_INSERT:
783     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
784   case TargetOpcode::G_LOAD: {
785     const auto &MMO = **MI.memoperands_begin();
786     Register DstReg = MI.getOperand(0).getReg();
787     LLT DstTy = MRI.getType(DstReg);
788     if (DstTy.isVector())
789       return UnableToLegalize;
790 
791     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
792       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
793       auto &MMO = **MI.memoperands_begin();
794       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
795       MIRBuilder.buildAnyExt(DstReg, TmpReg);
796       MI.eraseFromParent();
797       return Legalized;
798     }
799 
800     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
801   }
802   case TargetOpcode::G_ZEXTLOAD:
803   case TargetOpcode::G_SEXTLOAD: {
804     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
805     Register DstReg = MI.getOperand(0).getReg();
806     Register PtrReg = MI.getOperand(1).getReg();
807 
808     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
809     auto &MMO = **MI.memoperands_begin();
810     if (MMO.getSizeInBits() == NarrowSize) {
811       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
812     } else {
813       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
814         : TargetOpcode::G_SEXTLOAD;
815       MIRBuilder.buildInstr(ExtLoad)
816         .addDef(TmpReg)
817         .addUse(PtrReg)
818         .addMemOperand(&MMO);
819     }
820 
821     if (ZExt)
822       MIRBuilder.buildZExt(DstReg, TmpReg);
823     else
824       MIRBuilder.buildSExt(DstReg, TmpReg);
825 
826     MI.eraseFromParent();
827     return Legalized;
828   }
829   case TargetOpcode::G_STORE: {
830     const auto &MMO = **MI.memoperands_begin();
831 
832     Register SrcReg = MI.getOperand(0).getReg();
833     LLT SrcTy = MRI.getType(SrcReg);
834     if (SrcTy.isVector())
835       return UnableToLegalize;
836 
837     int NumParts = SizeOp0 / NarrowSize;
838     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
839     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
840     if (SrcTy.isVector() && LeftoverBits != 0)
841       return UnableToLegalize;
842 
843     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
844       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
845       auto &MMO = **MI.memoperands_begin();
846       MIRBuilder.buildTrunc(TmpReg, SrcReg);
847       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
848       MI.eraseFromParent();
849       return Legalized;
850     }
851 
852     return reduceLoadStoreWidth(MI, 0, NarrowTy);
853   }
854   case TargetOpcode::G_SELECT:
855     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
856   case TargetOpcode::G_AND:
857   case TargetOpcode::G_OR:
858   case TargetOpcode::G_XOR: {
859     // Legalize bitwise operation:
860     // A = BinOp<Ty> B, C
861     // into:
862     // B1, ..., BN = G_UNMERGE_VALUES B
863     // C1, ..., CN = G_UNMERGE_VALUES C
864     // A1 = BinOp<Ty/N> B1, C2
865     // ...
866     // AN = BinOp<Ty/N> BN, CN
867     // A = G_MERGE_VALUES A1, ..., AN
868     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
869   }
870   case TargetOpcode::G_SHL:
871   case TargetOpcode::G_LSHR:
872   case TargetOpcode::G_ASHR:
873     return narrowScalarShift(MI, TypeIdx, NarrowTy);
874   case TargetOpcode::G_CTLZ:
875   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
876   case TargetOpcode::G_CTTZ:
877   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
878   case TargetOpcode::G_CTPOP:
879     if (TypeIdx != 0)
880       return UnableToLegalize; // TODO
881 
882     Observer.changingInstr(MI);
883     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
884     Observer.changedInstr(MI);
885     return Legalized;
886   case TargetOpcode::G_INTTOPTR:
887     if (TypeIdx != 1)
888       return UnableToLegalize;
889 
890     Observer.changingInstr(MI);
891     narrowScalarSrc(MI, NarrowTy, 1);
892     Observer.changedInstr(MI);
893     return Legalized;
894   case TargetOpcode::G_PTRTOINT:
895     if (TypeIdx != 0)
896       return UnableToLegalize;
897 
898     Observer.changingInstr(MI);
899     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
900     Observer.changedInstr(MI);
901     return Legalized;
902   case TargetOpcode::G_PHI: {
903     unsigned NumParts = SizeOp0 / NarrowSize;
904     SmallVector<Register, 2> DstRegs;
905     SmallVector<SmallVector<Register, 2>, 2> SrcRegs;
906     DstRegs.resize(NumParts);
907     SrcRegs.resize(MI.getNumOperands() / 2);
908     Observer.changingInstr(MI);
909     for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
910       MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
911       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
912       extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
913                    SrcRegs[i / 2]);
914     }
915     MachineBasicBlock &MBB = *MI.getParent();
916     MIRBuilder.setInsertPt(MBB, MI);
917     for (unsigned i = 0; i < NumParts; ++i) {
918       DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
919       MachineInstrBuilder MIB =
920           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
921       for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
922         MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
923     }
924     MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
925     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
926     Observer.changedInstr(MI);
927     MI.eraseFromParent();
928     return Legalized;
929   }
930   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
931   case TargetOpcode::G_INSERT_VECTOR_ELT: {
932     if (TypeIdx != 2)
933       return UnableToLegalize;
934 
935     int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
936     Observer.changingInstr(MI);
937     narrowScalarSrc(MI, NarrowTy, OpIdx);
938     Observer.changedInstr(MI);
939     return Legalized;
940   }
941   case TargetOpcode::G_ICMP: {
942     uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
943     if (NarrowSize * 2 != SrcSize)
944       return UnableToLegalize;
945 
946     Observer.changingInstr(MI);
947     Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
948     Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
949     MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg());
950 
951     Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
952     Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
953     MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg());
954 
955     CmpInst::Predicate Pred =
956         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
957     LLT ResTy = MRI.getType(MI.getOperand(0).getReg());
958 
959     if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) {
960       MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
961       MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
962       MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
963       MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
964       MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero);
965     } else {
966       MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
967       MachineInstrBuilder CmpHEQ =
968           MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
969       MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
970           ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
971       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH);
972     }
973     Observer.changedInstr(MI);
974     MI.eraseFromParent();
975     return Legalized;
976   }
977   case TargetOpcode::G_SEXT_INREG: {
978     if (TypeIdx != 0)
979       return UnableToLegalize;
980 
981     if (!MI.getOperand(2).isImm())
982       return UnableToLegalize;
983     int64_t SizeInBits = MI.getOperand(2).getImm();
984 
985     // So long as the new type has more bits than the bits we're extending we
986     // don't need to break it apart.
987     if (NarrowTy.getScalarSizeInBits() >= SizeInBits) {
988       Observer.changingInstr(MI);
989       // We don't lose any non-extension bits by truncating the src and
990       // sign-extending the dst.
991       MachineOperand &MO1 = MI.getOperand(1);
992       auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1.getReg());
993       MO1.setReg(TruncMIB->getOperand(0).getReg());
994 
995       MachineOperand &MO2 = MI.getOperand(0);
996       Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
997       MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
998       MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt});
999       MO2.setReg(DstExt);
1000       Observer.changedInstr(MI);
1001       return Legalized;
1002     }
1003 
1004     // Break it apart. Components below the extension point are unmodified. The
1005     // component containing the extension point becomes a narrower SEXT_INREG.
1006     // Components above it are ashr'd from the component containing the
1007     // extension point.
1008     if (SizeOp0 % NarrowSize != 0)
1009       return UnableToLegalize;
1010     int NumParts = SizeOp0 / NarrowSize;
1011 
1012     // List the registers where the destination will be scattered.
1013     SmallVector<Register, 2> DstRegs;
1014     // List the registers where the source will be split.
1015     SmallVector<Register, 2> SrcRegs;
1016 
1017     // Create all the temporary registers.
1018     for (int i = 0; i < NumParts; ++i) {
1019       Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy);
1020 
1021       SrcRegs.push_back(SrcReg);
1022     }
1023 
1024     // Explode the big arguments into smaller chunks.
1025     MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg());
1026 
1027     Register AshrCstReg =
1028         MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
1029             ->getOperand(0)
1030             .getReg();
1031     Register FullExtensionReg = 0;
1032     Register PartialExtensionReg = 0;
1033 
1034     // Do the operation on each small part.
1035     for (int i = 0; i < NumParts; ++i) {
1036       if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits)
1037         DstRegs.push_back(SrcRegs[i]);
1038       else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) {
1039         assert(PartialExtensionReg &&
1040                "Expected to visit partial extension before full");
1041         if (FullExtensionReg) {
1042           DstRegs.push_back(FullExtensionReg);
1043           continue;
1044         }
1045         DstRegs.push_back(MIRBuilder
1046                               .buildInstr(TargetOpcode::G_ASHR, {NarrowTy},
1047                                           {PartialExtensionReg, AshrCstReg})
1048                               ->getOperand(0)
1049                               .getReg());
1050         FullExtensionReg = DstRegs.back();
1051       } else {
1052         DstRegs.push_back(
1053             MIRBuilder
1054                 .buildInstr(
1055                     TargetOpcode::G_SEXT_INREG, {NarrowTy},
1056                     {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
1057                 ->getOperand(0)
1058                 .getReg());
1059         PartialExtensionReg = DstRegs.back();
1060       }
1061     }
1062 
1063     // Gather the destination registers into the final destination.
1064     Register DstReg = MI.getOperand(0).getReg();
1065     MIRBuilder.buildMerge(DstReg, DstRegs);
1066     MI.eraseFromParent();
1067     return Legalized;
1068   }
1069   case TargetOpcode::G_BSWAP:
1070   case TargetOpcode::G_BITREVERSE: {
1071     if (SizeOp0 % NarrowSize != 0)
1072       return UnableToLegalize;
1073 
1074     Observer.changingInstr(MI);
1075     SmallVector<Register, 2> SrcRegs, DstRegs;
1076     unsigned NumParts = SizeOp0 / NarrowSize;
1077     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
1078 
1079     for (unsigned i = 0; i < NumParts; ++i) {
1080       auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
1081                                            {SrcRegs[NumParts - 1 - i]});
1082       DstRegs.push_back(DstPart.getReg(0));
1083     }
1084 
1085     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
1086 
1087     Observer.changedInstr(MI);
1088     MI.eraseFromParent();
1089     return Legalized;
1090   }
1091   }
1092 }
1093 
1094 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
1095                                      unsigned OpIdx, unsigned ExtOpcode) {
1096   MachineOperand &MO = MI.getOperand(OpIdx);
1097   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
1098   MO.setReg(ExtB->getOperand(0).getReg());
1099 }
1100 
1101 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
1102                                       unsigned OpIdx) {
1103   MachineOperand &MO = MI.getOperand(OpIdx);
1104   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
1105                                     {MO.getReg()});
1106   MO.setReg(ExtB->getOperand(0).getReg());
1107 }
1108 
1109 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
1110                                      unsigned OpIdx, unsigned TruncOpcode) {
1111   MachineOperand &MO = MI.getOperand(OpIdx);
1112   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1113   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1114   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
1115   MO.setReg(DstExt);
1116 }
1117 
1118 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
1119                                       unsigned OpIdx, unsigned ExtOpcode) {
1120   MachineOperand &MO = MI.getOperand(OpIdx);
1121   Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
1122   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1123   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
1124   MO.setReg(DstTrunc);
1125 }
1126 
1127 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
1128                                             unsigned OpIdx) {
1129   MachineOperand &MO = MI.getOperand(OpIdx);
1130   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1131   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1132   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
1133   MO.setReg(DstExt);
1134 }
1135 
1136 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
1137                                             unsigned OpIdx) {
1138   MachineOperand &MO = MI.getOperand(OpIdx);
1139 
1140   LLT OldTy = MRI.getType(MO.getReg());
1141   unsigned OldElts = OldTy.getNumElements();
1142   unsigned NewElts = MoreTy.getNumElements();
1143 
1144   unsigned NumParts = NewElts / OldElts;
1145 
1146   // Use concat_vectors if the result is a multiple of the number of elements.
1147   if (NumParts * OldElts == NewElts) {
1148     SmallVector<Register, 8> Parts;
1149     Parts.push_back(MO.getReg());
1150 
1151     Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
1152     for (unsigned I = 1; I != NumParts; ++I)
1153       Parts.push_back(ImpDef);
1154 
1155     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
1156     MO.setReg(Concat.getReg(0));
1157     return;
1158   }
1159 
1160   Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
1161   Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
1162   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
1163   MO.setReg(MoreReg);
1164 }
1165 
1166 LegalizerHelper::LegalizeResult
1167 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
1168                                         LLT WideTy) {
1169   if (TypeIdx != 1)
1170     return UnableToLegalize;
1171 
1172   Register DstReg = MI.getOperand(0).getReg();
1173   LLT DstTy = MRI.getType(DstReg);
1174   if (DstTy.isVector())
1175     return UnableToLegalize;
1176 
1177   Register Src1 = MI.getOperand(1).getReg();
1178   LLT SrcTy = MRI.getType(Src1);
1179   const int DstSize = DstTy.getSizeInBits();
1180   const int SrcSize = SrcTy.getSizeInBits();
1181   const int WideSize = WideTy.getSizeInBits();
1182   const int NumMerge = (DstSize + WideSize - 1) / WideSize;
1183 
1184   unsigned NumOps = MI.getNumOperands();
1185   unsigned NumSrc = MI.getNumOperands() - 1;
1186   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
1187 
1188   if (WideSize >= DstSize) {
1189     // Directly pack the bits in the target type.
1190     Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1191 
1192     for (unsigned I = 2; I != NumOps; ++I) {
1193       const unsigned Offset = (I - 1) * PartSize;
1194 
1195       Register SrcReg = MI.getOperand(I).getReg();
1196       assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
1197 
1198       auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
1199 
1200       Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
1201         MRI.createGenericVirtualRegister(WideTy);
1202 
1203       auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
1204       auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
1205       MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1206       ResultReg = NextResult;
1207     }
1208 
1209     if (WideSize > DstSize)
1210       MIRBuilder.buildTrunc(DstReg, ResultReg);
1211     else if (DstTy.isPointer())
1212       MIRBuilder.buildIntToPtr(DstReg, ResultReg);
1213 
1214     MI.eraseFromParent();
1215     return Legalized;
1216   }
1217 
1218   // Unmerge the original values to the GCD type, and recombine to the next
1219   // multiple greater than the original type.
1220   //
1221   // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6
1222   // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0
1223   // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1
1224   // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2
1225   // %10:_(s6) = G_MERGE_VALUES %4, %5, %6
1226   // %11:_(s6) = G_MERGE_VALUES %7, %8, %9
1227   // %12:_(s12) = G_MERGE_VALUES %10, %11
1228   //
1229   // Padding with undef if necessary:
1230   //
1231   // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6
1232   // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0
1233   // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1
1234   // %7:_(s2) = G_IMPLICIT_DEF
1235   // %8:_(s6) = G_MERGE_VALUES %3, %4, %5
1236   // %9:_(s6) = G_MERGE_VALUES %6, %7, %7
1237   // %10:_(s12) = G_MERGE_VALUES %8, %9
1238 
1239   const int GCD = greatestCommonDivisor(SrcSize, WideSize);
1240   LLT GCDTy = LLT::scalar(GCD);
1241 
1242   SmallVector<Register, 8> Parts;
1243   SmallVector<Register, 8> NewMergeRegs;
1244   SmallVector<Register, 8> Unmerges;
1245   LLT WideDstTy = LLT::scalar(NumMerge * WideSize);
1246 
1247   // Decompose the original operands if they don't evenly divide.
1248   for (int I = 1, E = MI.getNumOperands(); I != E; ++I) {
1249     Register SrcReg = MI.getOperand(I).getReg();
1250     if (GCD == SrcSize) {
1251       Unmerges.push_back(SrcReg);
1252     } else {
1253       auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
1254       for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J)
1255         Unmerges.push_back(Unmerge.getReg(J));
1256     }
1257   }
1258 
1259   // Pad with undef to the next size that is a multiple of the requested size.
1260   if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) {
1261     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1262     for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I)
1263       Unmerges.push_back(UndefReg);
1264   }
1265 
1266   const int PartsPerGCD = WideSize / GCD;
1267 
1268   // Build merges of each piece.
1269   ArrayRef<Register> Slicer(Unmerges);
1270   for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) {
1271     auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
1272     NewMergeRegs.push_back(Merge.getReg(0));
1273   }
1274 
1275   // A truncate may be necessary if the requested type doesn't evenly divide the
1276   // original result type.
1277   if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
1278     MIRBuilder.buildMerge(DstReg, NewMergeRegs);
1279   } else {
1280     auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
1281     MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
1282   }
1283 
1284   MI.eraseFromParent();
1285   return Legalized;
1286 }
1287 
1288 LegalizerHelper::LegalizeResult
1289 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
1290                                           LLT WideTy) {
1291   if (TypeIdx != 0)
1292     return UnableToLegalize;
1293 
1294   unsigned NumDst = MI.getNumOperands() - 1;
1295   Register SrcReg = MI.getOperand(NumDst).getReg();
1296   LLT SrcTy = MRI.getType(SrcReg);
1297   if (!SrcTy.isScalar())
1298     return UnableToLegalize;
1299 
1300   Register Dst0Reg = MI.getOperand(0).getReg();
1301   LLT DstTy = MRI.getType(Dst0Reg);
1302   if (!DstTy.isScalar())
1303     return UnableToLegalize;
1304 
1305   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
1306   LLT NewSrcTy = LLT::scalar(NewSrcSize);
1307   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
1308 
1309   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
1310 
1311   for (unsigned I = 1; I != NumDst; ++I) {
1312     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
1313     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
1314     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
1315   }
1316 
1317   Observer.changingInstr(MI);
1318 
1319   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
1320   for (unsigned I = 0; I != NumDst; ++I)
1321     widenScalarDst(MI, WideTy, I);
1322 
1323   Observer.changedInstr(MI);
1324 
1325   return Legalized;
1326 }
1327 
1328 LegalizerHelper::LegalizeResult
1329 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
1330                                     LLT WideTy) {
1331   Register DstReg = MI.getOperand(0).getReg();
1332   Register SrcReg = MI.getOperand(1).getReg();
1333   LLT SrcTy = MRI.getType(SrcReg);
1334 
1335   LLT DstTy = MRI.getType(DstReg);
1336   unsigned Offset = MI.getOperand(2).getImm();
1337 
1338   if (TypeIdx == 0) {
1339     if (SrcTy.isVector() || DstTy.isVector())
1340       return UnableToLegalize;
1341 
1342     SrcOp Src(SrcReg);
1343     if (SrcTy.isPointer()) {
1344       // Extracts from pointers can be handled only if they are really just
1345       // simple integers.
1346       const DataLayout &DL = MIRBuilder.getDataLayout();
1347       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
1348         return UnableToLegalize;
1349 
1350       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
1351       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
1352       SrcTy = SrcAsIntTy;
1353     }
1354 
1355     if (DstTy.isPointer())
1356       return UnableToLegalize;
1357 
1358     if (Offset == 0) {
1359       // Avoid a shift in the degenerate case.
1360       MIRBuilder.buildTrunc(DstReg,
1361                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
1362       MI.eraseFromParent();
1363       return Legalized;
1364     }
1365 
1366     // Do a shift in the source type.
1367     LLT ShiftTy = SrcTy;
1368     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1369       Src = MIRBuilder.buildAnyExt(WideTy, Src);
1370       ShiftTy = WideTy;
1371     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
1372       return UnableToLegalize;
1373 
1374     auto LShr = MIRBuilder.buildLShr(
1375       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
1376     MIRBuilder.buildTrunc(DstReg, LShr);
1377     MI.eraseFromParent();
1378     return Legalized;
1379   }
1380 
1381   if (SrcTy.isScalar()) {
1382     Observer.changingInstr(MI);
1383     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1384     Observer.changedInstr(MI);
1385     return Legalized;
1386   }
1387 
1388   if (!SrcTy.isVector())
1389     return UnableToLegalize;
1390 
1391   if (DstTy != SrcTy.getElementType())
1392     return UnableToLegalize;
1393 
1394   if (Offset % SrcTy.getScalarSizeInBits() != 0)
1395     return UnableToLegalize;
1396 
1397   Observer.changingInstr(MI);
1398   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1399 
1400   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
1401                           Offset);
1402   widenScalarDst(MI, WideTy.getScalarType(), 0);
1403   Observer.changedInstr(MI);
1404   return Legalized;
1405 }
1406 
1407 LegalizerHelper::LegalizeResult
1408 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
1409                                    LLT WideTy) {
1410   if (TypeIdx != 0)
1411     return UnableToLegalize;
1412   Observer.changingInstr(MI);
1413   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1414   widenScalarDst(MI, WideTy);
1415   Observer.changedInstr(MI);
1416   return Legalized;
1417 }
1418 
1419 LegalizerHelper::LegalizeResult
1420 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
1421   MIRBuilder.setInstr(MI);
1422 
1423   switch (MI.getOpcode()) {
1424   default:
1425     return UnableToLegalize;
1426   case TargetOpcode::G_EXTRACT:
1427     return widenScalarExtract(MI, TypeIdx, WideTy);
1428   case TargetOpcode::G_INSERT:
1429     return widenScalarInsert(MI, TypeIdx, WideTy);
1430   case TargetOpcode::G_MERGE_VALUES:
1431     return widenScalarMergeValues(MI, TypeIdx, WideTy);
1432   case TargetOpcode::G_UNMERGE_VALUES:
1433     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
1434   case TargetOpcode::G_UADDO:
1435   case TargetOpcode::G_USUBO: {
1436     if (TypeIdx == 1)
1437       return UnableToLegalize; // TODO
1438     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1439                                          {MI.getOperand(2).getReg()});
1440     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1441                                          {MI.getOperand(3).getReg()});
1442     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1443                           ? TargetOpcode::G_ADD
1444                           : TargetOpcode::G_SUB;
1445     // Do the arithmetic in the larger type.
1446     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1447     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1448     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
1449     auto AndOp = MIRBuilder.buildInstr(
1450         TargetOpcode::G_AND, {WideTy},
1451         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
1452     // There is no overflow if the AndOp is the same as NewOp.
1453     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
1454                          AndOp);
1455     // Now trunc the NewOp to the original result.
1456     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
1457     MI.eraseFromParent();
1458     return Legalized;
1459   }
1460   case TargetOpcode::G_CTTZ:
1461   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1462   case TargetOpcode::G_CTLZ:
1463   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1464   case TargetOpcode::G_CTPOP: {
1465     if (TypeIdx == 0) {
1466       Observer.changingInstr(MI);
1467       widenScalarDst(MI, WideTy, 0);
1468       Observer.changedInstr(MI);
1469       return Legalized;
1470     }
1471 
1472     Register SrcReg = MI.getOperand(1).getReg();
1473 
1474     // First ZEXT the input.
1475     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1476     LLT CurTy = MRI.getType(SrcReg);
1477     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1478       // The count is the same in the larger type except if the original
1479       // value was zero.  This can be handled by setting the bit just off
1480       // the top of the original type.
1481       auto TopBit =
1482           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1483       MIBSrc = MIRBuilder.buildOr(
1484         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1485     }
1486 
1487     // Perform the operation at the larger size.
1488     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1489     // This is already the correct result for CTPOP and CTTZs
1490     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1491         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1492       // The correct result is NewOp - (Difference in widety and current ty).
1493       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1494       MIBNewOp = MIRBuilder.buildInstr(
1495           TargetOpcode::G_SUB, {WideTy},
1496           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1497     }
1498 
1499     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1500     MI.eraseFromParent();
1501     return Legalized;
1502   }
1503   case TargetOpcode::G_BSWAP: {
1504     Observer.changingInstr(MI);
1505     Register DstReg = MI.getOperand(0).getReg();
1506 
1507     Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1508     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1509     Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1510     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1511 
1512     MI.getOperand(0).setReg(DstExt);
1513 
1514     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1515 
1516     LLT Ty = MRI.getType(DstReg);
1517     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1518     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1519     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1520       .addDef(ShrReg)
1521       .addUse(DstExt)
1522       .addUse(ShiftAmtReg);
1523 
1524     MIRBuilder.buildTrunc(DstReg, ShrReg);
1525     Observer.changedInstr(MI);
1526     return Legalized;
1527   }
1528   case TargetOpcode::G_BITREVERSE: {
1529     Observer.changingInstr(MI);
1530 
1531     Register DstReg = MI.getOperand(0).getReg();
1532     LLT Ty = MRI.getType(DstReg);
1533     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1534 
1535     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1536     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1537     MI.getOperand(0).setReg(DstExt);
1538     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1539 
1540     auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
1541     auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt);
1542     MIRBuilder.buildTrunc(DstReg, Shift);
1543     Observer.changedInstr(MI);
1544     return Legalized;
1545   }
1546   case TargetOpcode::G_ADD:
1547   case TargetOpcode::G_AND:
1548   case TargetOpcode::G_MUL:
1549   case TargetOpcode::G_OR:
1550   case TargetOpcode::G_XOR:
1551   case TargetOpcode::G_SUB:
1552     // Perform operation at larger width (any extension is fines here, high bits
1553     // don't affect the result) and then truncate the result back to the
1554     // original type.
1555     Observer.changingInstr(MI);
1556     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1557     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1558     widenScalarDst(MI, WideTy);
1559     Observer.changedInstr(MI);
1560     return Legalized;
1561 
1562   case TargetOpcode::G_SHL:
1563     Observer.changingInstr(MI);
1564 
1565     if (TypeIdx == 0) {
1566       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1567       widenScalarDst(MI, WideTy);
1568     } else {
1569       assert(TypeIdx == 1);
1570       // The "number of bits to shift" operand must preserve its value as an
1571       // unsigned integer:
1572       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1573     }
1574 
1575     Observer.changedInstr(MI);
1576     return Legalized;
1577 
1578   case TargetOpcode::G_SDIV:
1579   case TargetOpcode::G_SREM:
1580   case TargetOpcode::G_SMIN:
1581   case TargetOpcode::G_SMAX:
1582     Observer.changingInstr(MI);
1583     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1584     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1585     widenScalarDst(MI, WideTy);
1586     Observer.changedInstr(MI);
1587     return Legalized;
1588 
1589   case TargetOpcode::G_ASHR:
1590   case TargetOpcode::G_LSHR:
1591     Observer.changingInstr(MI);
1592 
1593     if (TypeIdx == 0) {
1594       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1595         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1596 
1597       widenScalarSrc(MI, WideTy, 1, CvtOp);
1598       widenScalarDst(MI, WideTy);
1599     } else {
1600       assert(TypeIdx == 1);
1601       // The "number of bits to shift" operand must preserve its value as an
1602       // unsigned integer:
1603       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1604     }
1605 
1606     Observer.changedInstr(MI);
1607     return Legalized;
1608   case TargetOpcode::G_UDIV:
1609   case TargetOpcode::G_UREM:
1610   case TargetOpcode::G_UMIN:
1611   case TargetOpcode::G_UMAX:
1612     Observer.changingInstr(MI);
1613     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1614     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1615     widenScalarDst(MI, WideTy);
1616     Observer.changedInstr(MI);
1617     return Legalized;
1618 
1619   case TargetOpcode::G_SELECT:
1620     Observer.changingInstr(MI);
1621     if (TypeIdx == 0) {
1622       // Perform operation at larger width (any extension is fine here, high
1623       // bits don't affect the result) and then truncate the result back to the
1624       // original type.
1625       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1626       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1627       widenScalarDst(MI, WideTy);
1628     } else {
1629       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1630       // Explicit extension is required here since high bits affect the result.
1631       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1632     }
1633     Observer.changedInstr(MI);
1634     return Legalized;
1635 
1636   case TargetOpcode::G_FPTOSI:
1637   case TargetOpcode::G_FPTOUI:
1638     Observer.changingInstr(MI);
1639 
1640     if (TypeIdx == 0)
1641       widenScalarDst(MI, WideTy);
1642     else
1643       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT);
1644 
1645     Observer.changedInstr(MI);
1646     return Legalized;
1647   case TargetOpcode::G_SITOFP:
1648     if (TypeIdx != 1)
1649       return UnableToLegalize;
1650     Observer.changingInstr(MI);
1651     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1652     Observer.changedInstr(MI);
1653     return Legalized;
1654 
1655   case TargetOpcode::G_UITOFP:
1656     if (TypeIdx != 1)
1657       return UnableToLegalize;
1658     Observer.changingInstr(MI);
1659     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1660     Observer.changedInstr(MI);
1661     return Legalized;
1662 
1663   case TargetOpcode::G_LOAD:
1664   case TargetOpcode::G_SEXTLOAD:
1665   case TargetOpcode::G_ZEXTLOAD:
1666     Observer.changingInstr(MI);
1667     widenScalarDst(MI, WideTy);
1668     Observer.changedInstr(MI);
1669     return Legalized;
1670 
1671   case TargetOpcode::G_STORE: {
1672     if (TypeIdx != 0)
1673       return UnableToLegalize;
1674 
1675     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1676     if (!isPowerOf2_32(Ty.getSizeInBits()))
1677       return UnableToLegalize;
1678 
1679     Observer.changingInstr(MI);
1680 
1681     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1682       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1683     widenScalarSrc(MI, WideTy, 0, ExtType);
1684 
1685     Observer.changedInstr(MI);
1686     return Legalized;
1687   }
1688   case TargetOpcode::G_CONSTANT: {
1689     MachineOperand &SrcMO = MI.getOperand(1);
1690     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1691     unsigned ExtOpc = LI.getExtOpcodeForWideningConstant(
1692         MRI.getType(MI.getOperand(0).getReg()));
1693     assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT ||
1694             ExtOpc == TargetOpcode::G_ANYEXT) &&
1695            "Illegal Extend");
1696     const APInt &SrcVal = SrcMO.getCImm()->getValue();
1697     const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT)
1698                            ? SrcVal.sext(WideTy.getSizeInBits())
1699                            : SrcVal.zext(WideTy.getSizeInBits());
1700     Observer.changingInstr(MI);
1701     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1702 
1703     widenScalarDst(MI, WideTy);
1704     Observer.changedInstr(MI);
1705     return Legalized;
1706   }
1707   case TargetOpcode::G_FCONSTANT: {
1708     MachineOperand &SrcMO = MI.getOperand(1);
1709     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1710     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1711     bool LosesInfo;
1712     switch (WideTy.getSizeInBits()) {
1713     case 32:
1714       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1715                   &LosesInfo);
1716       break;
1717     case 64:
1718       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1719                   &LosesInfo);
1720       break;
1721     default:
1722       return UnableToLegalize;
1723     }
1724 
1725     assert(!LosesInfo && "extend should always be lossless");
1726 
1727     Observer.changingInstr(MI);
1728     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1729 
1730     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1731     Observer.changedInstr(MI);
1732     return Legalized;
1733   }
1734   case TargetOpcode::G_IMPLICIT_DEF: {
1735     Observer.changingInstr(MI);
1736     widenScalarDst(MI, WideTy);
1737     Observer.changedInstr(MI);
1738     return Legalized;
1739   }
1740   case TargetOpcode::G_BRCOND:
1741     Observer.changingInstr(MI);
1742     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1743     Observer.changedInstr(MI);
1744     return Legalized;
1745 
1746   case TargetOpcode::G_FCMP:
1747     Observer.changingInstr(MI);
1748     if (TypeIdx == 0)
1749       widenScalarDst(MI, WideTy);
1750     else {
1751       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1752       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1753     }
1754     Observer.changedInstr(MI);
1755     return Legalized;
1756 
1757   case TargetOpcode::G_ICMP:
1758     Observer.changingInstr(MI);
1759     if (TypeIdx == 0)
1760       widenScalarDst(MI, WideTy);
1761     else {
1762       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1763                                MI.getOperand(1).getPredicate()))
1764                                ? TargetOpcode::G_SEXT
1765                                : TargetOpcode::G_ZEXT;
1766       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1767       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1768     }
1769     Observer.changedInstr(MI);
1770     return Legalized;
1771 
1772   case TargetOpcode::G_PTR_ADD:
1773     assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD");
1774     Observer.changingInstr(MI);
1775     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1776     Observer.changedInstr(MI);
1777     return Legalized;
1778 
1779   case TargetOpcode::G_PHI: {
1780     assert(TypeIdx == 0 && "Expecting only Idx 0");
1781 
1782     Observer.changingInstr(MI);
1783     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1784       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1785       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1786       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1787     }
1788 
1789     MachineBasicBlock &MBB = *MI.getParent();
1790     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1791     widenScalarDst(MI, WideTy);
1792     Observer.changedInstr(MI);
1793     return Legalized;
1794   }
1795   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1796     if (TypeIdx == 0) {
1797       Register VecReg = MI.getOperand(1).getReg();
1798       LLT VecTy = MRI.getType(VecReg);
1799       Observer.changingInstr(MI);
1800 
1801       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1802                                      WideTy.getSizeInBits()),
1803                      1, TargetOpcode::G_SEXT);
1804 
1805       widenScalarDst(MI, WideTy, 0);
1806       Observer.changedInstr(MI);
1807       return Legalized;
1808     }
1809 
1810     if (TypeIdx != 2)
1811       return UnableToLegalize;
1812     Observer.changingInstr(MI);
1813     // TODO: Probably should be zext
1814     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1815     Observer.changedInstr(MI);
1816     return Legalized;
1817   }
1818   case TargetOpcode::G_INSERT_VECTOR_ELT: {
1819     if (TypeIdx == 1) {
1820       Observer.changingInstr(MI);
1821 
1822       Register VecReg = MI.getOperand(1).getReg();
1823       LLT VecTy = MRI.getType(VecReg);
1824       LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy);
1825 
1826       widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT);
1827       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1828       widenScalarDst(MI, WideVecTy, 0);
1829       Observer.changedInstr(MI);
1830       return Legalized;
1831     }
1832 
1833     if (TypeIdx == 2) {
1834       Observer.changingInstr(MI);
1835       // TODO: Probably should be zext
1836       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT);
1837       Observer.changedInstr(MI);
1838     }
1839 
1840     return Legalized;
1841   }
1842   case TargetOpcode::G_FADD:
1843   case TargetOpcode::G_FMUL:
1844   case TargetOpcode::G_FSUB:
1845   case TargetOpcode::G_FMA:
1846   case TargetOpcode::G_FMAD:
1847   case TargetOpcode::G_FNEG:
1848   case TargetOpcode::G_FABS:
1849   case TargetOpcode::G_FCANONICALIZE:
1850   case TargetOpcode::G_FMINNUM:
1851   case TargetOpcode::G_FMAXNUM:
1852   case TargetOpcode::G_FMINNUM_IEEE:
1853   case TargetOpcode::G_FMAXNUM_IEEE:
1854   case TargetOpcode::G_FMINIMUM:
1855   case TargetOpcode::G_FMAXIMUM:
1856   case TargetOpcode::G_FDIV:
1857   case TargetOpcode::G_FREM:
1858   case TargetOpcode::G_FCEIL:
1859   case TargetOpcode::G_FFLOOR:
1860   case TargetOpcode::G_FCOS:
1861   case TargetOpcode::G_FSIN:
1862   case TargetOpcode::G_FLOG10:
1863   case TargetOpcode::G_FLOG:
1864   case TargetOpcode::G_FLOG2:
1865   case TargetOpcode::G_FRINT:
1866   case TargetOpcode::G_FNEARBYINT:
1867   case TargetOpcode::G_FSQRT:
1868   case TargetOpcode::G_FEXP:
1869   case TargetOpcode::G_FEXP2:
1870   case TargetOpcode::G_FPOW:
1871   case TargetOpcode::G_INTRINSIC_TRUNC:
1872   case TargetOpcode::G_INTRINSIC_ROUND:
1873     assert(TypeIdx == 0);
1874     Observer.changingInstr(MI);
1875 
1876     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1877       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1878 
1879     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1880     Observer.changedInstr(MI);
1881     return Legalized;
1882   case TargetOpcode::G_INTTOPTR:
1883     if (TypeIdx != 1)
1884       return UnableToLegalize;
1885 
1886     Observer.changingInstr(MI);
1887     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1888     Observer.changedInstr(MI);
1889     return Legalized;
1890   case TargetOpcode::G_PTRTOINT:
1891     if (TypeIdx != 0)
1892       return UnableToLegalize;
1893 
1894     Observer.changingInstr(MI);
1895     widenScalarDst(MI, WideTy, 0);
1896     Observer.changedInstr(MI);
1897     return Legalized;
1898   case TargetOpcode::G_BUILD_VECTOR: {
1899     Observer.changingInstr(MI);
1900 
1901     const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
1902     for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
1903       widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT);
1904 
1905     // Avoid changing the result vector type if the source element type was
1906     // requested.
1907     if (TypeIdx == 1) {
1908       auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
1909       MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
1910     } else {
1911       widenScalarDst(MI, WideTy, 0);
1912     }
1913 
1914     Observer.changedInstr(MI);
1915     return Legalized;
1916   }
1917   case TargetOpcode::G_SEXT_INREG:
1918     if (TypeIdx != 0)
1919       return UnableToLegalize;
1920 
1921     Observer.changingInstr(MI);
1922     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1923     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC);
1924     Observer.changedInstr(MI);
1925     return Legalized;
1926   }
1927 }
1928 
1929 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces,
1930                              MachineIRBuilder &B, Register Src, LLT Ty) {
1931   auto Unmerge = B.buildUnmerge(Ty, Src);
1932   for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
1933     Pieces.push_back(Unmerge.getReg(I));
1934 }
1935 
1936 LegalizerHelper::LegalizeResult
1937 LegalizerHelper::lowerBitcast(MachineInstr &MI) {
1938   Register Dst = MI.getOperand(0).getReg();
1939   Register Src = MI.getOperand(1).getReg();
1940   LLT DstTy = MRI.getType(Dst);
1941   LLT SrcTy = MRI.getType(Src);
1942 
1943   if (SrcTy.isVector() && !DstTy.isVector()) {
1944     SmallVector<Register, 8> SrcRegs;
1945     getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcTy.getElementType());
1946     MIRBuilder.buildMerge(Dst, SrcRegs);
1947     MI.eraseFromParent();
1948     return Legalized;
1949   }
1950 
1951   if (DstTy.isVector() && !SrcTy.isVector()) {
1952     SmallVector<Register, 8> SrcRegs;
1953     getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType());
1954     MIRBuilder.buildMerge(Dst, SrcRegs);
1955     MI.eraseFromParent();
1956     return Legalized;
1957   }
1958 
1959   return UnableToLegalize;
1960 }
1961 
1962 LegalizerHelper::LegalizeResult
1963 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1964   using namespace TargetOpcode;
1965   MIRBuilder.setInstr(MI);
1966 
1967   switch(MI.getOpcode()) {
1968   default:
1969     return UnableToLegalize;
1970   case TargetOpcode::G_BITCAST:
1971     return lowerBitcast(MI);
1972   case TargetOpcode::G_SREM:
1973   case TargetOpcode::G_UREM: {
1974     Register QuotReg = MRI.createGenericVirtualRegister(Ty);
1975     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1976         .addDef(QuotReg)
1977         .addUse(MI.getOperand(1).getReg())
1978         .addUse(MI.getOperand(2).getReg());
1979 
1980     Register ProdReg = MRI.createGenericVirtualRegister(Ty);
1981     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1982     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1983                         ProdReg);
1984     MI.eraseFromParent();
1985     return Legalized;
1986   }
1987   case TargetOpcode::G_SADDO:
1988   case TargetOpcode::G_SSUBO:
1989     return lowerSADDO_SSUBO(MI);
1990   case TargetOpcode::G_SMULO:
1991   case TargetOpcode::G_UMULO: {
1992     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
1993     // result.
1994     Register Res = MI.getOperand(0).getReg();
1995     Register Overflow = MI.getOperand(1).getReg();
1996     Register LHS = MI.getOperand(2).getReg();
1997     Register RHS = MI.getOperand(3).getReg();
1998 
1999     MIRBuilder.buildMul(Res, LHS, RHS);
2000 
2001     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
2002                           ? TargetOpcode::G_SMULH
2003                           : TargetOpcode::G_UMULH;
2004 
2005     Register HiPart = MRI.createGenericVirtualRegister(Ty);
2006     MIRBuilder.buildInstr(Opcode)
2007       .addDef(HiPart)
2008       .addUse(LHS)
2009       .addUse(RHS);
2010 
2011     Register Zero = MRI.createGenericVirtualRegister(Ty);
2012     MIRBuilder.buildConstant(Zero, 0);
2013 
2014     // For *signed* multiply, overflow is detected by checking:
2015     // (hi != (lo >> bitwidth-1))
2016     if (Opcode == TargetOpcode::G_SMULH) {
2017       Register Shifted = MRI.createGenericVirtualRegister(Ty);
2018       Register ShiftAmt = MRI.createGenericVirtualRegister(Ty);
2019       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
2020       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
2021         .addDef(Shifted)
2022         .addUse(Res)
2023         .addUse(ShiftAmt);
2024       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
2025     } else {
2026       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
2027     }
2028     MI.eraseFromParent();
2029     return Legalized;
2030   }
2031   case TargetOpcode::G_FNEG: {
2032     // TODO: Handle vector types once we are able to
2033     // represent them.
2034     if (Ty.isVector())
2035       return UnableToLegalize;
2036     Register Res = MI.getOperand(0).getReg();
2037     Type *ZeroTy;
2038     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
2039     switch (Ty.getSizeInBits()) {
2040     case 16:
2041       ZeroTy = Type::getHalfTy(Ctx);
2042       break;
2043     case 32:
2044       ZeroTy = Type::getFloatTy(Ctx);
2045       break;
2046     case 64:
2047       ZeroTy = Type::getDoubleTy(Ctx);
2048       break;
2049     case 128:
2050       ZeroTy = Type::getFP128Ty(Ctx);
2051       break;
2052     default:
2053       llvm_unreachable("unexpected floating-point type");
2054     }
2055     ConstantFP &ZeroForNegation =
2056         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
2057     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
2058     Register SubByReg = MI.getOperand(1).getReg();
2059     Register ZeroReg = Zero->getOperand(0).getReg();
2060     MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
2061                           MI.getFlags());
2062     MI.eraseFromParent();
2063     return Legalized;
2064   }
2065   case TargetOpcode::G_FSUB: {
2066     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
2067     // First, check if G_FNEG is marked as Lower. If so, we may
2068     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
2069     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
2070       return UnableToLegalize;
2071     Register Res = MI.getOperand(0).getReg();
2072     Register LHS = MI.getOperand(1).getReg();
2073     Register RHS = MI.getOperand(2).getReg();
2074     Register Neg = MRI.createGenericVirtualRegister(Ty);
2075     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
2076     MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
2077     MI.eraseFromParent();
2078     return Legalized;
2079   }
2080   case TargetOpcode::G_FMAD:
2081     return lowerFMad(MI);
2082   case TargetOpcode::G_INTRINSIC_ROUND:
2083     return lowerIntrinsicRound(MI);
2084   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
2085     Register OldValRes = MI.getOperand(0).getReg();
2086     Register SuccessRes = MI.getOperand(1).getReg();
2087     Register Addr = MI.getOperand(2).getReg();
2088     Register CmpVal = MI.getOperand(3).getReg();
2089     Register NewVal = MI.getOperand(4).getReg();
2090     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
2091                                   **MI.memoperands_begin());
2092     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
2093     MI.eraseFromParent();
2094     return Legalized;
2095   }
2096   case TargetOpcode::G_LOAD:
2097   case TargetOpcode::G_SEXTLOAD:
2098   case TargetOpcode::G_ZEXTLOAD: {
2099     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
2100     Register DstReg = MI.getOperand(0).getReg();
2101     Register PtrReg = MI.getOperand(1).getReg();
2102     LLT DstTy = MRI.getType(DstReg);
2103     auto &MMO = **MI.memoperands_begin();
2104 
2105     if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
2106       if (MI.getOpcode() == TargetOpcode::G_LOAD) {
2107         // This load needs splitting into power of 2 sized loads.
2108         if (DstTy.isVector())
2109           return UnableToLegalize;
2110         if (isPowerOf2_32(DstTy.getSizeInBits()))
2111           return UnableToLegalize; // Don't know what we're being asked to do.
2112 
2113         // Our strategy here is to generate anyextending loads for the smaller
2114         // types up to next power-2 result type, and then combine the two larger
2115         // result values together, before truncating back down to the non-pow-2
2116         // type.
2117         // E.g. v1 = i24 load =>
2118         // v2 = i32 load (2 byte)
2119         // v3 = i32 load (1 byte)
2120         // v4 = i32 shl v3, 16
2121         // v5 = i32 or v4, v2
2122         // v1 = i24 trunc v5
2123         // By doing this we generate the correct truncate which should get
2124         // combined away as an artifact with a matching extend.
2125         uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits());
2126         uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize;
2127 
2128         MachineFunction &MF = MIRBuilder.getMF();
2129         MachineMemOperand *LargeMMO =
2130             MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2131         MachineMemOperand *SmallMMO = MF.getMachineMemOperand(
2132             &MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2133 
2134         LLT PtrTy = MRI.getType(PtrReg);
2135         unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits());
2136         LLT AnyExtTy = LLT::scalar(AnyExtSize);
2137         Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2138         Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2139         auto LargeLoad =
2140             MIRBuilder.buildLoad(LargeLdReg, PtrReg, *LargeMMO);
2141 
2142         auto OffsetCst =
2143             MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2144         Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2145         auto SmallPtr =
2146             MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2147         auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
2148                                               *SmallMMO);
2149 
2150         auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
2151         auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt);
2152         auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
2153         MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)});
2154         MI.eraseFromParent();
2155         return Legalized;
2156       }
2157       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
2158       MI.eraseFromParent();
2159       return Legalized;
2160     }
2161 
2162     if (DstTy.isScalar()) {
2163       Register TmpReg =
2164           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
2165       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
2166       switch (MI.getOpcode()) {
2167       default:
2168         llvm_unreachable("Unexpected opcode");
2169       case TargetOpcode::G_LOAD:
2170         MIRBuilder.buildExtOrTrunc(TargetOpcode::G_ANYEXT, DstReg, TmpReg);
2171         break;
2172       case TargetOpcode::G_SEXTLOAD:
2173         MIRBuilder.buildSExt(DstReg, TmpReg);
2174         break;
2175       case TargetOpcode::G_ZEXTLOAD:
2176         MIRBuilder.buildZExt(DstReg, TmpReg);
2177         break;
2178       }
2179       MI.eraseFromParent();
2180       return Legalized;
2181     }
2182 
2183     return UnableToLegalize;
2184   }
2185   case TargetOpcode::G_STORE: {
2186     // Lower a non-power of 2 store into multiple pow-2 stores.
2187     // E.g. split an i24 store into an i16 store + i8 store.
2188     // We do this by first extending the stored value to the next largest power
2189     // of 2 type, and then using truncating stores to store the components.
2190     // By doing this, likewise with G_LOAD, generate an extend that can be
2191     // artifact-combined away instead of leaving behind extracts.
2192     Register SrcReg = MI.getOperand(0).getReg();
2193     Register PtrReg = MI.getOperand(1).getReg();
2194     LLT SrcTy = MRI.getType(SrcReg);
2195     MachineMemOperand &MMO = **MI.memoperands_begin();
2196     if (SrcTy.getSizeInBits() != MMO.getSizeInBits())
2197       return UnableToLegalize;
2198     if (SrcTy.isVector())
2199       return UnableToLegalize;
2200     if (isPowerOf2_32(SrcTy.getSizeInBits()))
2201       return UnableToLegalize; // Don't know what we're being asked to do.
2202 
2203     // Extend to the next pow-2.
2204     const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits()));
2205     auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg);
2206 
2207     // Obtain the smaller value by shifting away the larger value.
2208     uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits());
2209     uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize;
2210     auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize);
2211     auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt);
2212 
2213     // Generate the PtrAdd and truncating stores.
2214     LLT PtrTy = MRI.getType(PtrReg);
2215     auto OffsetCst =
2216         MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2217     Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2218     auto SmallPtr =
2219         MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2220 
2221     MachineFunction &MF = MIRBuilder.getMF();
2222     MachineMemOperand *LargeMMO =
2223         MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2224     MachineMemOperand *SmallMMO =
2225         MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2226     MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO);
2227     MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO);
2228     MI.eraseFromParent();
2229     return Legalized;
2230   }
2231   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
2232   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
2233   case TargetOpcode::G_CTLZ:
2234   case TargetOpcode::G_CTTZ:
2235   case TargetOpcode::G_CTPOP:
2236     return lowerBitCount(MI, TypeIdx, Ty);
2237   case G_UADDO: {
2238     Register Res = MI.getOperand(0).getReg();
2239     Register CarryOut = MI.getOperand(1).getReg();
2240     Register LHS = MI.getOperand(2).getReg();
2241     Register RHS = MI.getOperand(3).getReg();
2242 
2243     MIRBuilder.buildAdd(Res, LHS, RHS);
2244     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
2245 
2246     MI.eraseFromParent();
2247     return Legalized;
2248   }
2249   case G_UADDE: {
2250     Register Res = MI.getOperand(0).getReg();
2251     Register CarryOut = MI.getOperand(1).getReg();
2252     Register LHS = MI.getOperand(2).getReg();
2253     Register RHS = MI.getOperand(3).getReg();
2254     Register CarryIn = MI.getOperand(4).getReg();
2255 
2256     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2257     Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
2258 
2259     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
2260     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
2261     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
2262     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
2263 
2264     MI.eraseFromParent();
2265     return Legalized;
2266   }
2267   case G_USUBO: {
2268     Register Res = MI.getOperand(0).getReg();
2269     Register BorrowOut = MI.getOperand(1).getReg();
2270     Register LHS = MI.getOperand(2).getReg();
2271     Register RHS = MI.getOperand(3).getReg();
2272 
2273     MIRBuilder.buildSub(Res, LHS, RHS);
2274     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
2275 
2276     MI.eraseFromParent();
2277     return Legalized;
2278   }
2279   case G_USUBE: {
2280     Register Res = MI.getOperand(0).getReg();
2281     Register BorrowOut = MI.getOperand(1).getReg();
2282     Register LHS = MI.getOperand(2).getReg();
2283     Register RHS = MI.getOperand(3).getReg();
2284     Register BorrowIn = MI.getOperand(4).getReg();
2285 
2286     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2287     Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
2288     Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2289     Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2290 
2291     MIRBuilder.buildSub(TmpRes, LHS, RHS);
2292     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
2293     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
2294     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
2295     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
2296     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
2297 
2298     MI.eraseFromParent();
2299     return Legalized;
2300   }
2301   case G_UITOFP:
2302     return lowerUITOFP(MI, TypeIdx, Ty);
2303   case G_SITOFP:
2304     return lowerSITOFP(MI, TypeIdx, Ty);
2305   case G_FPTOUI:
2306     return lowerFPTOUI(MI, TypeIdx, Ty);
2307   case G_SMIN:
2308   case G_SMAX:
2309   case G_UMIN:
2310   case G_UMAX:
2311     return lowerMinMax(MI, TypeIdx, Ty);
2312   case G_FCOPYSIGN:
2313     return lowerFCopySign(MI, TypeIdx, Ty);
2314   case G_FMINNUM:
2315   case G_FMAXNUM:
2316     return lowerFMinNumMaxNum(MI);
2317   case G_UNMERGE_VALUES:
2318     return lowerUnmergeValues(MI);
2319   case TargetOpcode::G_SEXT_INREG: {
2320     assert(MI.getOperand(2).isImm() && "Expected immediate");
2321     int64_t SizeInBits = MI.getOperand(2).getImm();
2322 
2323     Register DstReg = MI.getOperand(0).getReg();
2324     Register SrcReg = MI.getOperand(1).getReg();
2325     LLT DstTy = MRI.getType(DstReg);
2326     Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
2327 
2328     auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
2329     MIRBuilder.buildInstr(TargetOpcode::G_SHL, {TmpRes}, {SrcReg, MIBSz->getOperand(0).getReg()});
2330     MIRBuilder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {TmpRes, MIBSz->getOperand(0).getReg()});
2331     MI.eraseFromParent();
2332     return Legalized;
2333   }
2334   case G_SHUFFLE_VECTOR:
2335     return lowerShuffleVector(MI);
2336   case G_DYN_STACKALLOC:
2337     return lowerDynStackAlloc(MI);
2338   case G_EXTRACT:
2339     return lowerExtract(MI);
2340   case G_INSERT:
2341     return lowerInsert(MI);
2342   case G_BSWAP:
2343     return lowerBswap(MI);
2344   case G_BITREVERSE:
2345     return lowerBitreverse(MI);
2346   case G_READ_REGISTER:
2347     return lowerReadRegister(MI);
2348   }
2349 }
2350 
2351 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
2352     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
2353   SmallVector<Register, 2> DstRegs;
2354 
2355   unsigned NarrowSize = NarrowTy.getSizeInBits();
2356   Register DstReg = MI.getOperand(0).getReg();
2357   unsigned Size = MRI.getType(DstReg).getSizeInBits();
2358   int NumParts = Size / NarrowSize;
2359   // FIXME: Don't know how to handle the situation where the small vectors
2360   // aren't all the same size yet.
2361   if (Size % NarrowSize != 0)
2362     return UnableToLegalize;
2363 
2364   for (int i = 0; i < NumParts; ++i) {
2365     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
2366     MIRBuilder.buildUndef(TmpReg);
2367     DstRegs.push_back(TmpReg);
2368   }
2369 
2370   if (NarrowTy.isVector())
2371     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2372   else
2373     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2374 
2375   MI.eraseFromParent();
2376   return Legalized;
2377 }
2378 
2379 LegalizerHelper::LegalizeResult
2380 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
2381                                           LLT NarrowTy) {
2382   const unsigned Opc = MI.getOpcode();
2383   const unsigned NumOps = MI.getNumOperands() - 1;
2384   const unsigned NarrowSize = NarrowTy.getSizeInBits();
2385   const Register DstReg = MI.getOperand(0).getReg();
2386   const unsigned Flags = MI.getFlags();
2387   const LLT DstTy = MRI.getType(DstReg);
2388   const unsigned Size = DstTy.getSizeInBits();
2389   const int NumParts = Size / NarrowSize;
2390   const LLT EltTy = DstTy.getElementType();
2391   const unsigned EltSize = EltTy.getSizeInBits();
2392   const unsigned BitsForNumParts = NarrowSize * NumParts;
2393 
2394   // Check if we have any leftovers. If we do, then only handle the case where
2395   // the leftover is one element.
2396   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
2397     return UnableToLegalize;
2398 
2399   if (BitsForNumParts != Size) {
2400     Register AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
2401     MIRBuilder.buildUndef(AccumDstReg);
2402 
2403     // Handle the pieces which evenly divide into the requested type with
2404     // extract/op/insert sequence.
2405     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
2406       SmallVector<SrcOp, 4> SrcOps;
2407       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2408         Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
2409         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
2410         SrcOps.push_back(PartOpReg);
2411       }
2412 
2413       Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
2414       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2415 
2416       Register PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
2417       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
2418       AccumDstReg = PartInsertReg;
2419     }
2420 
2421     // Handle the remaining element sized leftover piece.
2422     SmallVector<SrcOp, 4> SrcOps;
2423     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2424       Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
2425       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
2426                               BitsForNumParts);
2427       SrcOps.push_back(PartOpReg);
2428     }
2429 
2430     Register PartDstReg = MRI.createGenericVirtualRegister(EltTy);
2431     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2432     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
2433     MI.eraseFromParent();
2434 
2435     return Legalized;
2436   }
2437 
2438   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2439 
2440   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
2441 
2442   if (NumOps >= 2)
2443     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
2444 
2445   if (NumOps >= 3)
2446     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
2447 
2448   for (int i = 0; i < NumParts; ++i) {
2449     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2450 
2451     if (NumOps == 1)
2452       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
2453     else if (NumOps == 2) {
2454       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
2455     } else if (NumOps == 3) {
2456       MIRBuilder.buildInstr(Opc, {DstReg},
2457                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
2458     }
2459 
2460     DstRegs.push_back(DstReg);
2461   }
2462 
2463   if (NarrowTy.isVector())
2464     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2465   else
2466     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2467 
2468   MI.eraseFromParent();
2469   return Legalized;
2470 }
2471 
2472 // Handle splitting vector operations which need to have the same number of
2473 // elements in each type index, but each type index may have a different element
2474 // type.
2475 //
2476 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
2477 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2478 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2479 //
2480 // Also handles some irregular breakdown cases, e.g.
2481 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
2482 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2483 //             s64 = G_SHL s64, s32
2484 LegalizerHelper::LegalizeResult
2485 LegalizerHelper::fewerElementsVectorMultiEltType(
2486   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
2487   if (TypeIdx != 0)
2488     return UnableToLegalize;
2489 
2490   const LLT NarrowTy0 = NarrowTyArg;
2491   const unsigned NewNumElts =
2492       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
2493 
2494   const Register DstReg = MI.getOperand(0).getReg();
2495   LLT DstTy = MRI.getType(DstReg);
2496   LLT LeftoverTy0;
2497 
2498   // All of the operands need to have the same number of elements, so if we can
2499   // determine a type breakdown for the result type, we can for all of the
2500   // source types.
2501   int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first;
2502   if (NumParts < 0)
2503     return UnableToLegalize;
2504 
2505   SmallVector<MachineInstrBuilder, 4> NewInsts;
2506 
2507   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2508   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2509 
2510   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2511     LLT LeftoverTy;
2512     Register SrcReg = MI.getOperand(I).getReg();
2513     LLT SrcTyI = MRI.getType(SrcReg);
2514     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
2515     LLT LeftoverTyI;
2516 
2517     // Split this operand into the requested typed registers, and any leftover
2518     // required to reproduce the original type.
2519     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
2520                       LeftoverRegs))
2521       return UnableToLegalize;
2522 
2523     if (I == 1) {
2524       // For the first operand, create an instruction for each part and setup
2525       // the result.
2526       for (Register PartReg : PartRegs) {
2527         Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2528         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2529                                .addDef(PartDstReg)
2530                                .addUse(PartReg));
2531         DstRegs.push_back(PartDstReg);
2532       }
2533 
2534       for (Register LeftoverReg : LeftoverRegs) {
2535         Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
2536         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2537                                .addDef(PartDstReg)
2538                                .addUse(LeftoverReg));
2539         LeftoverDstRegs.push_back(PartDstReg);
2540       }
2541     } else {
2542       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
2543 
2544       // Add the newly created operand splits to the existing instructions. The
2545       // odd-sized pieces are ordered after the requested NarrowTyArg sized
2546       // pieces.
2547       unsigned InstCount = 0;
2548       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
2549         NewInsts[InstCount++].addUse(PartRegs[J]);
2550       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
2551         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
2552     }
2553 
2554     PartRegs.clear();
2555     LeftoverRegs.clear();
2556   }
2557 
2558   // Insert the newly built operations and rebuild the result register.
2559   for (auto &MIB : NewInsts)
2560     MIRBuilder.insertInstr(MIB);
2561 
2562   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
2563 
2564   MI.eraseFromParent();
2565   return Legalized;
2566 }
2567 
2568 LegalizerHelper::LegalizeResult
2569 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
2570                                           LLT NarrowTy) {
2571   if (TypeIdx != 0)
2572     return UnableToLegalize;
2573 
2574   Register DstReg = MI.getOperand(0).getReg();
2575   Register SrcReg = MI.getOperand(1).getReg();
2576   LLT DstTy = MRI.getType(DstReg);
2577   LLT SrcTy = MRI.getType(SrcReg);
2578 
2579   LLT NarrowTy0 = NarrowTy;
2580   LLT NarrowTy1;
2581   unsigned NumParts;
2582 
2583   if (NarrowTy.isVector()) {
2584     // Uneven breakdown not handled.
2585     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
2586     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
2587       return UnableToLegalize;
2588 
2589     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
2590   } else {
2591     NumParts = DstTy.getNumElements();
2592     NarrowTy1 = SrcTy.getElementType();
2593   }
2594 
2595   SmallVector<Register, 4> SrcRegs, DstRegs;
2596   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
2597 
2598   for (unsigned I = 0; I < NumParts; ++I) {
2599     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2600     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
2601       .addDef(DstReg)
2602       .addUse(SrcRegs[I]);
2603 
2604     NewInst->setFlags(MI.getFlags());
2605     DstRegs.push_back(DstReg);
2606   }
2607 
2608   if (NarrowTy.isVector())
2609     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2610   else
2611     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2612 
2613   MI.eraseFromParent();
2614   return Legalized;
2615 }
2616 
2617 LegalizerHelper::LegalizeResult
2618 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
2619                                         LLT NarrowTy) {
2620   Register DstReg = MI.getOperand(0).getReg();
2621   Register Src0Reg = MI.getOperand(2).getReg();
2622   LLT DstTy = MRI.getType(DstReg);
2623   LLT SrcTy = MRI.getType(Src0Reg);
2624 
2625   unsigned NumParts;
2626   LLT NarrowTy0, NarrowTy1;
2627 
2628   if (TypeIdx == 0) {
2629     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2630     unsigned OldElts = DstTy.getNumElements();
2631 
2632     NarrowTy0 = NarrowTy;
2633     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
2634     NarrowTy1 = NarrowTy.isVector() ?
2635       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
2636       SrcTy.getElementType();
2637 
2638   } else {
2639     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2640     unsigned OldElts = SrcTy.getNumElements();
2641 
2642     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
2643       NarrowTy.getNumElements();
2644     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
2645                             DstTy.getScalarSizeInBits());
2646     NarrowTy1 = NarrowTy;
2647   }
2648 
2649   // FIXME: Don't know how to handle the situation where the small vectors
2650   // aren't all the same size yet.
2651   if (NarrowTy1.isVector() &&
2652       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
2653     return UnableToLegalize;
2654 
2655   CmpInst::Predicate Pred
2656     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
2657 
2658   SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
2659   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
2660   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
2661 
2662   for (unsigned I = 0; I < NumParts; ++I) {
2663     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2664     DstRegs.push_back(DstReg);
2665 
2666     if (MI.getOpcode() == TargetOpcode::G_ICMP)
2667       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2668     else {
2669       MachineInstr *NewCmp
2670         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2671       NewCmp->setFlags(MI.getFlags());
2672     }
2673   }
2674 
2675   if (NarrowTy1.isVector())
2676     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2677   else
2678     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2679 
2680   MI.eraseFromParent();
2681   return Legalized;
2682 }
2683 
2684 LegalizerHelper::LegalizeResult
2685 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
2686                                            LLT NarrowTy) {
2687   Register DstReg = MI.getOperand(0).getReg();
2688   Register CondReg = MI.getOperand(1).getReg();
2689 
2690   unsigned NumParts = 0;
2691   LLT NarrowTy0, NarrowTy1;
2692 
2693   LLT DstTy = MRI.getType(DstReg);
2694   LLT CondTy = MRI.getType(CondReg);
2695   unsigned Size = DstTy.getSizeInBits();
2696 
2697   assert(TypeIdx == 0 || CondTy.isVector());
2698 
2699   if (TypeIdx == 0) {
2700     NarrowTy0 = NarrowTy;
2701     NarrowTy1 = CondTy;
2702 
2703     unsigned NarrowSize = NarrowTy0.getSizeInBits();
2704     // FIXME: Don't know how to handle the situation where the small vectors
2705     // aren't all the same size yet.
2706     if (Size % NarrowSize != 0)
2707       return UnableToLegalize;
2708 
2709     NumParts = Size / NarrowSize;
2710 
2711     // Need to break down the condition type
2712     if (CondTy.isVector()) {
2713       if (CondTy.getNumElements() == NumParts)
2714         NarrowTy1 = CondTy.getElementType();
2715       else
2716         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
2717                                 CondTy.getScalarSizeInBits());
2718     }
2719   } else {
2720     NumParts = CondTy.getNumElements();
2721     if (NarrowTy.isVector()) {
2722       // TODO: Handle uneven breakdown.
2723       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
2724         return UnableToLegalize;
2725 
2726       return UnableToLegalize;
2727     } else {
2728       NarrowTy0 = DstTy.getElementType();
2729       NarrowTy1 = NarrowTy;
2730     }
2731   }
2732 
2733   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2734   if (CondTy.isVector())
2735     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2736 
2737   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2738   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2739 
2740   for (unsigned i = 0; i < NumParts; ++i) {
2741     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2742     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
2743                            Src1Regs[i], Src2Regs[i]);
2744     DstRegs.push_back(DstReg);
2745   }
2746 
2747   if (NarrowTy0.isVector())
2748     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2749   else
2750     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2751 
2752   MI.eraseFromParent();
2753   return Legalized;
2754 }
2755 
2756 LegalizerHelper::LegalizeResult
2757 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2758                                         LLT NarrowTy) {
2759   const Register DstReg = MI.getOperand(0).getReg();
2760   LLT PhiTy = MRI.getType(DstReg);
2761   LLT LeftoverTy;
2762 
2763   // All of the operands need to have the same number of elements, so if we can
2764   // determine a type breakdown for the result type, we can for all of the
2765   // source types.
2766   int NumParts, NumLeftover;
2767   std::tie(NumParts, NumLeftover)
2768     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2769   if (NumParts < 0)
2770     return UnableToLegalize;
2771 
2772   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2773   SmallVector<MachineInstrBuilder, 4> NewInsts;
2774 
2775   const int TotalNumParts = NumParts + NumLeftover;
2776 
2777   // Insert the new phis in the result block first.
2778   for (int I = 0; I != TotalNumParts; ++I) {
2779     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2780     Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
2781     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2782                        .addDef(PartDstReg));
2783     if (I < NumParts)
2784       DstRegs.push_back(PartDstReg);
2785     else
2786       LeftoverDstRegs.push_back(PartDstReg);
2787   }
2788 
2789   MachineBasicBlock *MBB = MI.getParent();
2790   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2791   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2792 
2793   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2794 
2795   // Insert code to extract the incoming values in each predecessor block.
2796   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2797     PartRegs.clear();
2798     LeftoverRegs.clear();
2799 
2800     Register SrcReg = MI.getOperand(I).getReg();
2801     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2802     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2803 
2804     LLT Unused;
2805     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2806                       LeftoverRegs))
2807       return UnableToLegalize;
2808 
2809     // Add the newly created operand splits to the existing instructions. The
2810     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2811     // pieces.
2812     for (int J = 0; J != TotalNumParts; ++J) {
2813       MachineInstrBuilder MIB = NewInsts[J];
2814       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2815       MIB.addMBB(&OpMBB);
2816     }
2817   }
2818 
2819   MI.eraseFromParent();
2820   return Legalized;
2821 }
2822 
2823 LegalizerHelper::LegalizeResult
2824 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
2825                                                   unsigned TypeIdx,
2826                                                   LLT NarrowTy) {
2827   if (TypeIdx != 1)
2828     return UnableToLegalize;
2829 
2830   const int NumDst = MI.getNumOperands() - 1;
2831   const Register SrcReg = MI.getOperand(NumDst).getReg();
2832   LLT SrcTy = MRI.getType(SrcReg);
2833 
2834   LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2835 
2836   // TODO: Create sequence of extracts.
2837   if (DstTy == NarrowTy)
2838     return UnableToLegalize;
2839 
2840   LLT GCDTy = getGCDType(SrcTy, NarrowTy);
2841   if (DstTy == GCDTy) {
2842     // This would just be a copy of the same unmerge.
2843     // TODO: Create extracts, pad with undef and create intermediate merges.
2844     return UnableToLegalize;
2845   }
2846 
2847   auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
2848   const int NumUnmerge = Unmerge->getNumOperands() - 1;
2849   const int PartsPerUnmerge = NumDst / NumUnmerge;
2850 
2851   for (int I = 0; I != NumUnmerge; ++I) {
2852     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
2853 
2854     for (int J = 0; J != PartsPerUnmerge; ++J)
2855       MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg());
2856     MIB.addUse(Unmerge.getReg(I));
2857   }
2858 
2859   MI.eraseFromParent();
2860   return Legalized;
2861 }
2862 
2863 LegalizerHelper::LegalizeResult
2864 LegalizerHelper::fewerElementsVectorBuildVector(MachineInstr &MI,
2865                                                 unsigned TypeIdx,
2866                                                 LLT NarrowTy) {
2867   assert(TypeIdx == 0 && "not a vector type index");
2868   Register DstReg = MI.getOperand(0).getReg();
2869   LLT DstTy = MRI.getType(DstReg);
2870   LLT SrcTy = DstTy.getElementType();
2871 
2872   int DstNumElts = DstTy.getNumElements();
2873   int NarrowNumElts = NarrowTy.getNumElements();
2874   int NumConcat = (DstNumElts + NarrowNumElts - 1) / NarrowNumElts;
2875   LLT WidenedDstTy = LLT::vector(NarrowNumElts * NumConcat, SrcTy);
2876 
2877   SmallVector<Register, 8> ConcatOps;
2878   SmallVector<Register, 8> SubBuildVector;
2879 
2880   Register UndefReg;
2881   if (WidenedDstTy != DstTy)
2882     UndefReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
2883 
2884   // Create a G_CONCAT_VECTORS of NarrowTy pieces, padding with undef as
2885   // necessary.
2886   //
2887   // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2
2888   //   -> <2 x s16>
2889   //
2890   // %4:_(s16) = G_IMPLICIT_DEF
2891   // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1
2892   // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4
2893   // %7:_(<4 x s16>) = G_CONCAT_VECTORS %5, %6
2894   // %3:_(<3 x s16>) = G_EXTRACT %7, 0
2895   for (int I = 0; I != NumConcat; ++I) {
2896     for (int J = 0; J != NarrowNumElts; ++J) {
2897       int SrcIdx = NarrowNumElts * I + J;
2898 
2899       if (SrcIdx < DstNumElts) {
2900         Register SrcReg = MI.getOperand(SrcIdx + 1).getReg();
2901         SubBuildVector.push_back(SrcReg);
2902       } else
2903         SubBuildVector.push_back(UndefReg);
2904     }
2905 
2906     auto BuildVec = MIRBuilder.buildBuildVector(NarrowTy, SubBuildVector);
2907     ConcatOps.push_back(BuildVec.getReg(0));
2908     SubBuildVector.clear();
2909   }
2910 
2911   if (DstTy == WidenedDstTy)
2912     MIRBuilder.buildConcatVectors(DstReg, ConcatOps);
2913   else {
2914     auto Concat = MIRBuilder.buildConcatVectors(WidenedDstTy, ConcatOps);
2915     MIRBuilder.buildExtract(DstReg, Concat, 0);
2916   }
2917 
2918   MI.eraseFromParent();
2919   return Legalized;
2920 }
2921 
2922 LegalizerHelper::LegalizeResult
2923 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2924                                       LLT NarrowTy) {
2925   // FIXME: Don't know how to handle secondary types yet.
2926   if (TypeIdx != 0)
2927     return UnableToLegalize;
2928 
2929   MachineMemOperand *MMO = *MI.memoperands_begin();
2930 
2931   // This implementation doesn't work for atomics. Give up instead of doing
2932   // something invalid.
2933   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2934       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2935     return UnableToLegalize;
2936 
2937   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2938   Register ValReg = MI.getOperand(0).getReg();
2939   Register AddrReg = MI.getOperand(1).getReg();
2940   LLT ValTy = MRI.getType(ValReg);
2941 
2942   int NumParts = -1;
2943   int NumLeftover = -1;
2944   LLT LeftoverTy;
2945   SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
2946   if (IsLoad) {
2947     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2948   } else {
2949     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2950                      NarrowLeftoverRegs)) {
2951       NumParts = NarrowRegs.size();
2952       NumLeftover = NarrowLeftoverRegs.size();
2953     }
2954   }
2955 
2956   if (NumParts == -1)
2957     return UnableToLegalize;
2958 
2959   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2960 
2961   unsigned TotalSize = ValTy.getSizeInBits();
2962 
2963   // Split the load/store into PartTy sized pieces starting at Offset. If this
2964   // is a load, return the new registers in ValRegs. For a store, each elements
2965   // of ValRegs should be PartTy. Returns the next offset that needs to be
2966   // handled.
2967   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
2968                              unsigned Offset) -> unsigned {
2969     MachineFunction &MF = MIRBuilder.getMF();
2970     unsigned PartSize = PartTy.getSizeInBits();
2971     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2972          Offset += PartSize, ++Idx) {
2973       unsigned ByteSize = PartSize / 8;
2974       unsigned ByteOffset = Offset / 8;
2975       Register NewAddrReg;
2976 
2977       MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2978 
2979       MachineMemOperand *NewMMO =
2980         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2981 
2982       if (IsLoad) {
2983         Register Dst = MRI.createGenericVirtualRegister(PartTy);
2984         ValRegs.push_back(Dst);
2985         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
2986       } else {
2987         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
2988       }
2989     }
2990 
2991     return Offset;
2992   };
2993 
2994   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
2995 
2996   // Handle the rest of the register if this isn't an even type breakdown.
2997   if (LeftoverTy.isValid())
2998     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
2999 
3000   if (IsLoad) {
3001     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
3002                 LeftoverTy, NarrowLeftoverRegs);
3003   }
3004 
3005   MI.eraseFromParent();
3006   return Legalized;
3007 }
3008 
3009 LegalizerHelper::LegalizeResult
3010 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
3011                                      LLT NarrowTy) {
3012   using namespace TargetOpcode;
3013 
3014   MIRBuilder.setInstr(MI);
3015   switch (MI.getOpcode()) {
3016   case G_IMPLICIT_DEF:
3017     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
3018   case G_AND:
3019   case G_OR:
3020   case G_XOR:
3021   case G_ADD:
3022   case G_SUB:
3023   case G_MUL:
3024   case G_SMULH:
3025   case G_UMULH:
3026   case G_FADD:
3027   case G_FMUL:
3028   case G_FSUB:
3029   case G_FNEG:
3030   case G_FABS:
3031   case G_FCANONICALIZE:
3032   case G_FDIV:
3033   case G_FREM:
3034   case G_FMA:
3035   case G_FMAD:
3036   case G_FPOW:
3037   case G_FEXP:
3038   case G_FEXP2:
3039   case G_FLOG:
3040   case G_FLOG2:
3041   case G_FLOG10:
3042   case G_FNEARBYINT:
3043   case G_FCEIL:
3044   case G_FFLOOR:
3045   case G_FRINT:
3046   case G_INTRINSIC_ROUND:
3047   case G_INTRINSIC_TRUNC:
3048   case G_FCOS:
3049   case G_FSIN:
3050   case G_FSQRT:
3051   case G_BSWAP:
3052   case G_BITREVERSE:
3053   case G_SDIV:
3054   case G_UDIV:
3055   case G_SREM:
3056   case G_UREM:
3057   case G_SMIN:
3058   case G_SMAX:
3059   case G_UMIN:
3060   case G_UMAX:
3061   case G_FMINNUM:
3062   case G_FMAXNUM:
3063   case G_FMINNUM_IEEE:
3064   case G_FMAXNUM_IEEE:
3065   case G_FMINIMUM:
3066   case G_FMAXIMUM:
3067     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
3068   case G_SHL:
3069   case G_LSHR:
3070   case G_ASHR:
3071   case G_CTLZ:
3072   case G_CTLZ_ZERO_UNDEF:
3073   case G_CTTZ:
3074   case G_CTTZ_ZERO_UNDEF:
3075   case G_CTPOP:
3076   case G_FCOPYSIGN:
3077     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
3078   case G_ZEXT:
3079   case G_SEXT:
3080   case G_ANYEXT:
3081   case G_FPEXT:
3082   case G_FPTRUNC:
3083   case G_SITOFP:
3084   case G_UITOFP:
3085   case G_FPTOSI:
3086   case G_FPTOUI:
3087   case G_INTTOPTR:
3088   case G_PTRTOINT:
3089   case G_ADDRSPACE_CAST:
3090     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
3091   case G_ICMP:
3092   case G_FCMP:
3093     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
3094   case G_SELECT:
3095     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
3096   case G_PHI:
3097     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
3098   case G_UNMERGE_VALUES:
3099     return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy);
3100   case G_BUILD_VECTOR:
3101     return fewerElementsVectorBuildVector(MI, TypeIdx, NarrowTy);
3102   case G_LOAD:
3103   case G_STORE:
3104     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
3105   default:
3106     return UnableToLegalize;
3107   }
3108 }
3109 
3110 LegalizerHelper::LegalizeResult
3111 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
3112                                              const LLT HalfTy, const LLT AmtTy) {
3113 
3114   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3115   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3116   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3117 
3118   if (Amt.isNullValue()) {
3119     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
3120     MI.eraseFromParent();
3121     return Legalized;
3122   }
3123 
3124   LLT NVT = HalfTy;
3125   unsigned NVTBits = HalfTy.getSizeInBits();
3126   unsigned VTBits = 2 * NVTBits;
3127 
3128   SrcOp Lo(Register(0)), Hi(Register(0));
3129   if (MI.getOpcode() == TargetOpcode::G_SHL) {
3130     if (Amt.ugt(VTBits)) {
3131       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3132     } else if (Amt.ugt(NVTBits)) {
3133       Lo = MIRBuilder.buildConstant(NVT, 0);
3134       Hi = MIRBuilder.buildShl(NVT, InL,
3135                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3136     } else if (Amt == NVTBits) {
3137       Lo = MIRBuilder.buildConstant(NVT, 0);
3138       Hi = InL;
3139     } else {
3140       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
3141       auto OrLHS =
3142           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
3143       auto OrRHS = MIRBuilder.buildLShr(
3144           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3145       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3146     }
3147   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3148     if (Amt.ugt(VTBits)) {
3149       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3150     } else if (Amt.ugt(NVTBits)) {
3151       Lo = MIRBuilder.buildLShr(NVT, InH,
3152                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3153       Hi = MIRBuilder.buildConstant(NVT, 0);
3154     } else if (Amt == NVTBits) {
3155       Lo = InH;
3156       Hi = MIRBuilder.buildConstant(NVT, 0);
3157     } else {
3158       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3159 
3160       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3161       auto OrRHS = MIRBuilder.buildShl(
3162           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3163 
3164       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3165       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
3166     }
3167   } else {
3168     if (Amt.ugt(VTBits)) {
3169       Hi = Lo = MIRBuilder.buildAShr(
3170           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3171     } else if (Amt.ugt(NVTBits)) {
3172       Lo = MIRBuilder.buildAShr(NVT, InH,
3173                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3174       Hi = MIRBuilder.buildAShr(NVT, InH,
3175                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3176     } else if (Amt == NVTBits) {
3177       Lo = InH;
3178       Hi = MIRBuilder.buildAShr(NVT, InH,
3179                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3180     } else {
3181       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3182 
3183       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3184       auto OrRHS = MIRBuilder.buildShl(
3185           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3186 
3187       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3188       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
3189     }
3190   }
3191 
3192   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
3193   MI.eraseFromParent();
3194 
3195   return Legalized;
3196 }
3197 
3198 // TODO: Optimize if constant shift amount.
3199 LegalizerHelper::LegalizeResult
3200 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
3201                                    LLT RequestedTy) {
3202   if (TypeIdx == 1) {
3203     Observer.changingInstr(MI);
3204     narrowScalarSrc(MI, RequestedTy, 2);
3205     Observer.changedInstr(MI);
3206     return Legalized;
3207   }
3208 
3209   Register DstReg = MI.getOperand(0).getReg();
3210   LLT DstTy = MRI.getType(DstReg);
3211   if (DstTy.isVector())
3212     return UnableToLegalize;
3213 
3214   Register Amt = MI.getOperand(2).getReg();
3215   LLT ShiftAmtTy = MRI.getType(Amt);
3216   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
3217   if (DstEltSize % 2 != 0)
3218     return UnableToLegalize;
3219 
3220   // Ignore the input type. We can only go to exactly half the size of the
3221   // input. If that isn't small enough, the resulting pieces will be further
3222   // legalized.
3223   const unsigned NewBitSize = DstEltSize / 2;
3224   const LLT HalfTy = LLT::scalar(NewBitSize);
3225   const LLT CondTy = LLT::scalar(1);
3226 
3227   if (const MachineInstr *KShiftAmt =
3228           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
3229     return narrowScalarShiftByConstant(
3230         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
3231   }
3232 
3233   // TODO: Expand with known bits.
3234 
3235   // Handle the fully general expansion by an unknown amount.
3236   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
3237 
3238   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3239   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3240   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3241 
3242   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
3243   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
3244 
3245   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
3246   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
3247   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
3248 
3249   Register ResultRegs[2];
3250   switch (MI.getOpcode()) {
3251   case TargetOpcode::G_SHL: {
3252     // Short: ShAmt < NewBitSize
3253     auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt);
3254 
3255     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
3256     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt);
3257     auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3258 
3259     // Long: ShAmt >= NewBitSize
3260     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
3261     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
3262 
3263     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
3264     auto Hi = MIRBuilder.buildSelect(
3265         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
3266 
3267     ResultRegs[0] = Lo.getReg(0);
3268     ResultRegs[1] = Hi.getReg(0);
3269     break;
3270   }
3271   case TargetOpcode::G_LSHR:
3272   case TargetOpcode::G_ASHR: {
3273     // Short: ShAmt < NewBitSize
3274     auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt});
3275 
3276     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt);
3277     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
3278     auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3279 
3280     // Long: ShAmt >= NewBitSize
3281     MachineInstrBuilder HiL;
3282     if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3283       HiL = MIRBuilder.buildConstant(HalfTy, 0);            // Hi part is zero.
3284     } else {
3285       auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1);
3286       HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt);    // Sign of Hi part.
3287     }
3288     auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy},
3289                                      {InH, AmtExcess});     // Lo from Hi part.
3290 
3291     auto Lo = MIRBuilder.buildSelect(
3292         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
3293 
3294     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
3295 
3296     ResultRegs[0] = Lo.getReg(0);
3297     ResultRegs[1] = Hi.getReg(0);
3298     break;
3299   }
3300   default:
3301     llvm_unreachable("not a shift");
3302   }
3303 
3304   MIRBuilder.buildMerge(DstReg, ResultRegs);
3305   MI.eraseFromParent();
3306   return Legalized;
3307 }
3308 
3309 LegalizerHelper::LegalizeResult
3310 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
3311                                        LLT MoreTy) {
3312   assert(TypeIdx == 0 && "Expecting only Idx 0");
3313 
3314   Observer.changingInstr(MI);
3315   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
3316     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
3317     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
3318     moreElementsVectorSrc(MI, MoreTy, I);
3319   }
3320 
3321   MachineBasicBlock &MBB = *MI.getParent();
3322   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
3323   moreElementsVectorDst(MI, MoreTy, 0);
3324   Observer.changedInstr(MI);
3325   return Legalized;
3326 }
3327 
3328 LegalizerHelper::LegalizeResult
3329 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
3330                                     LLT MoreTy) {
3331   MIRBuilder.setInstr(MI);
3332   unsigned Opc = MI.getOpcode();
3333   switch (Opc) {
3334   case TargetOpcode::G_IMPLICIT_DEF:
3335   case TargetOpcode::G_LOAD: {
3336     if (TypeIdx != 0)
3337       return UnableToLegalize;
3338     Observer.changingInstr(MI);
3339     moreElementsVectorDst(MI, MoreTy, 0);
3340     Observer.changedInstr(MI);
3341     return Legalized;
3342   }
3343   case TargetOpcode::G_STORE:
3344     if (TypeIdx != 0)
3345       return UnableToLegalize;
3346     Observer.changingInstr(MI);
3347     moreElementsVectorSrc(MI, MoreTy, 0);
3348     Observer.changedInstr(MI);
3349     return Legalized;
3350   case TargetOpcode::G_AND:
3351   case TargetOpcode::G_OR:
3352   case TargetOpcode::G_XOR:
3353   case TargetOpcode::G_SMIN:
3354   case TargetOpcode::G_SMAX:
3355   case TargetOpcode::G_UMIN:
3356   case TargetOpcode::G_UMAX:
3357   case TargetOpcode::G_FMINNUM:
3358   case TargetOpcode::G_FMAXNUM:
3359   case TargetOpcode::G_FMINNUM_IEEE:
3360   case TargetOpcode::G_FMAXNUM_IEEE:
3361   case TargetOpcode::G_FMINIMUM:
3362   case TargetOpcode::G_FMAXIMUM: {
3363     Observer.changingInstr(MI);
3364     moreElementsVectorSrc(MI, MoreTy, 1);
3365     moreElementsVectorSrc(MI, MoreTy, 2);
3366     moreElementsVectorDst(MI, MoreTy, 0);
3367     Observer.changedInstr(MI);
3368     return Legalized;
3369   }
3370   case TargetOpcode::G_EXTRACT:
3371     if (TypeIdx != 1)
3372       return UnableToLegalize;
3373     Observer.changingInstr(MI);
3374     moreElementsVectorSrc(MI, MoreTy, 1);
3375     Observer.changedInstr(MI);
3376     return Legalized;
3377   case TargetOpcode::G_INSERT:
3378     if (TypeIdx != 0)
3379       return UnableToLegalize;
3380     Observer.changingInstr(MI);
3381     moreElementsVectorSrc(MI, MoreTy, 1);
3382     moreElementsVectorDst(MI, MoreTy, 0);
3383     Observer.changedInstr(MI);
3384     return Legalized;
3385   case TargetOpcode::G_SELECT:
3386     if (TypeIdx != 0)
3387       return UnableToLegalize;
3388     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
3389       return UnableToLegalize;
3390 
3391     Observer.changingInstr(MI);
3392     moreElementsVectorSrc(MI, MoreTy, 2);
3393     moreElementsVectorSrc(MI, MoreTy, 3);
3394     moreElementsVectorDst(MI, MoreTy, 0);
3395     Observer.changedInstr(MI);
3396     return Legalized;
3397   case TargetOpcode::G_UNMERGE_VALUES: {
3398     if (TypeIdx != 1)
3399       return UnableToLegalize;
3400 
3401     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
3402     int NumDst = MI.getNumOperands() - 1;
3403     moreElementsVectorSrc(MI, MoreTy, NumDst);
3404 
3405     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
3406     for (int I = 0; I != NumDst; ++I)
3407       MIB.addDef(MI.getOperand(I).getReg());
3408 
3409     int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits();
3410     for (int I = NumDst; I != NewNumDst; ++I)
3411       MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
3412 
3413     MIB.addUse(MI.getOperand(NumDst).getReg());
3414     MI.eraseFromParent();
3415     return Legalized;
3416   }
3417   case TargetOpcode::G_PHI:
3418     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
3419   default:
3420     return UnableToLegalize;
3421   }
3422 }
3423 
3424 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
3425                                         ArrayRef<Register> Src1Regs,
3426                                         ArrayRef<Register> Src2Regs,
3427                                         LLT NarrowTy) {
3428   MachineIRBuilder &B = MIRBuilder;
3429   unsigned SrcParts = Src1Regs.size();
3430   unsigned DstParts = DstRegs.size();
3431 
3432   unsigned DstIdx = 0; // Low bits of the result.
3433   Register FactorSum =
3434       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
3435   DstRegs[DstIdx] = FactorSum;
3436 
3437   unsigned CarrySumPrevDstIdx;
3438   SmallVector<Register, 4> Factors;
3439 
3440   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
3441     // Collect low parts of muls for DstIdx.
3442     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
3443          i <= std::min(DstIdx, SrcParts - 1); ++i) {
3444       MachineInstrBuilder Mul =
3445           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
3446       Factors.push_back(Mul.getReg(0));
3447     }
3448     // Collect high parts of muls from previous DstIdx.
3449     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
3450          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
3451       MachineInstrBuilder Umulh =
3452           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
3453       Factors.push_back(Umulh.getReg(0));
3454     }
3455     // Add CarrySum from additions calculated for previous DstIdx.
3456     if (DstIdx != 1) {
3457       Factors.push_back(CarrySumPrevDstIdx);
3458     }
3459 
3460     Register CarrySum;
3461     // Add all factors and accumulate all carries into CarrySum.
3462     if (DstIdx != DstParts - 1) {
3463       MachineInstrBuilder Uaddo =
3464           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
3465       FactorSum = Uaddo.getReg(0);
3466       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
3467       for (unsigned i = 2; i < Factors.size(); ++i) {
3468         MachineInstrBuilder Uaddo =
3469             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
3470         FactorSum = Uaddo.getReg(0);
3471         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
3472         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
3473       }
3474     } else {
3475       // Since value for the next index is not calculated, neither is CarrySum.
3476       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
3477       for (unsigned i = 2; i < Factors.size(); ++i)
3478         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
3479     }
3480 
3481     CarrySumPrevDstIdx = CarrySum;
3482     DstRegs[DstIdx] = FactorSum;
3483     Factors.clear();
3484   }
3485 }
3486 
3487 LegalizerHelper::LegalizeResult
3488 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
3489   Register DstReg = MI.getOperand(0).getReg();
3490   Register Src1 = MI.getOperand(1).getReg();
3491   Register Src2 = MI.getOperand(2).getReg();
3492 
3493   LLT Ty = MRI.getType(DstReg);
3494   if (Ty.isVector())
3495     return UnableToLegalize;
3496 
3497   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
3498   unsigned DstSize = Ty.getSizeInBits();
3499   unsigned NarrowSize = NarrowTy.getSizeInBits();
3500   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
3501     return UnableToLegalize;
3502 
3503   unsigned NumDstParts = DstSize / NarrowSize;
3504   unsigned NumSrcParts = SrcSize / NarrowSize;
3505   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
3506   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
3507 
3508   SmallVector<Register, 2> Src1Parts, Src2Parts, DstTmpRegs;
3509   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
3510   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
3511   DstTmpRegs.resize(DstTmpParts);
3512   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
3513 
3514   // Take only high half of registers if this is high mul.
3515   ArrayRef<Register> DstRegs(
3516       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
3517   MIRBuilder.buildMerge(DstReg, DstRegs);
3518   MI.eraseFromParent();
3519   return Legalized;
3520 }
3521 
3522 LegalizerHelper::LegalizeResult
3523 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
3524                                      LLT NarrowTy) {
3525   if (TypeIdx != 1)
3526     return UnableToLegalize;
3527 
3528   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3529 
3530   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
3531   // FIXME: add support for when SizeOp1 isn't an exact multiple of
3532   // NarrowSize.
3533   if (SizeOp1 % NarrowSize != 0)
3534     return UnableToLegalize;
3535   int NumParts = SizeOp1 / NarrowSize;
3536 
3537   SmallVector<Register, 2> SrcRegs, DstRegs;
3538   SmallVector<uint64_t, 2> Indexes;
3539   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3540 
3541   Register OpReg = MI.getOperand(0).getReg();
3542   uint64_t OpStart = MI.getOperand(2).getImm();
3543   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3544   for (int i = 0; i < NumParts; ++i) {
3545     unsigned SrcStart = i * NarrowSize;
3546 
3547     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
3548       // No part of the extract uses this subregister, ignore it.
3549       continue;
3550     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3551       // The entire subregister is extracted, forward the value.
3552       DstRegs.push_back(SrcRegs[i]);
3553       continue;
3554     }
3555 
3556     // OpSegStart is where this destination segment would start in OpReg if it
3557     // extended infinitely in both directions.
3558     int64_t ExtractOffset;
3559     uint64_t SegSize;
3560     if (OpStart < SrcStart) {
3561       ExtractOffset = 0;
3562       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
3563     } else {
3564       ExtractOffset = OpStart - SrcStart;
3565       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
3566     }
3567 
3568     Register SegReg = SrcRegs[i];
3569     if (ExtractOffset != 0 || SegSize != NarrowSize) {
3570       // A genuine extract is needed.
3571       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3572       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
3573     }
3574 
3575     DstRegs.push_back(SegReg);
3576   }
3577 
3578   Register DstReg = MI.getOperand(0).getReg();
3579   if(MRI.getType(DstReg).isVector())
3580     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3581   else
3582     MIRBuilder.buildMerge(DstReg, DstRegs);
3583   MI.eraseFromParent();
3584   return Legalized;
3585 }
3586 
3587 LegalizerHelper::LegalizeResult
3588 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
3589                                     LLT NarrowTy) {
3590   // FIXME: Don't know how to handle secondary types yet.
3591   if (TypeIdx != 0)
3592     return UnableToLegalize;
3593 
3594   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
3595   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3596 
3597   // FIXME: add support for when SizeOp0 isn't an exact multiple of
3598   // NarrowSize.
3599   if (SizeOp0 % NarrowSize != 0)
3600     return UnableToLegalize;
3601 
3602   int NumParts = SizeOp0 / NarrowSize;
3603 
3604   SmallVector<Register, 2> SrcRegs, DstRegs;
3605   SmallVector<uint64_t, 2> Indexes;
3606   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3607 
3608   Register OpReg = MI.getOperand(2).getReg();
3609   uint64_t OpStart = MI.getOperand(3).getImm();
3610   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3611   for (int i = 0; i < NumParts; ++i) {
3612     unsigned DstStart = i * NarrowSize;
3613 
3614     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
3615       // No part of the insert affects this subregister, forward the original.
3616       DstRegs.push_back(SrcRegs[i]);
3617       continue;
3618     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3619       // The entire subregister is defined by this insert, forward the new
3620       // value.
3621       DstRegs.push_back(OpReg);
3622       continue;
3623     }
3624 
3625     // OpSegStart is where this destination segment would start in OpReg if it
3626     // extended infinitely in both directions.
3627     int64_t ExtractOffset, InsertOffset;
3628     uint64_t SegSize;
3629     if (OpStart < DstStart) {
3630       InsertOffset = 0;
3631       ExtractOffset = DstStart - OpStart;
3632       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
3633     } else {
3634       InsertOffset = OpStart - DstStart;
3635       ExtractOffset = 0;
3636       SegSize =
3637         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
3638     }
3639 
3640     Register SegReg = OpReg;
3641     if (ExtractOffset != 0 || SegSize != OpSize) {
3642       // A genuine extract is needed.
3643       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3644       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
3645     }
3646 
3647     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
3648     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
3649     DstRegs.push_back(DstReg);
3650   }
3651 
3652   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
3653   Register DstReg = MI.getOperand(0).getReg();
3654   if(MRI.getType(DstReg).isVector())
3655     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3656   else
3657     MIRBuilder.buildMerge(DstReg, DstRegs);
3658   MI.eraseFromParent();
3659   return Legalized;
3660 }
3661 
3662 LegalizerHelper::LegalizeResult
3663 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
3664                                    LLT NarrowTy) {
3665   Register DstReg = MI.getOperand(0).getReg();
3666   LLT DstTy = MRI.getType(DstReg);
3667 
3668   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
3669 
3670   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3671   SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
3672   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3673   LLT LeftoverTy;
3674   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
3675                     Src0Regs, Src0LeftoverRegs))
3676     return UnableToLegalize;
3677 
3678   LLT Unused;
3679   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
3680                     Src1Regs, Src1LeftoverRegs))
3681     llvm_unreachable("inconsistent extractParts result");
3682 
3683   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3684     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
3685                                         {Src0Regs[I], Src1Regs[I]});
3686     DstRegs.push_back(Inst->getOperand(0).getReg());
3687   }
3688 
3689   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3690     auto Inst = MIRBuilder.buildInstr(
3691       MI.getOpcode(),
3692       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
3693     DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
3694   }
3695 
3696   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3697               LeftoverTy, DstLeftoverRegs);
3698 
3699   MI.eraseFromParent();
3700   return Legalized;
3701 }
3702 
3703 LegalizerHelper::LegalizeResult
3704 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
3705                                     LLT NarrowTy) {
3706   if (TypeIdx != 0)
3707     return UnableToLegalize;
3708 
3709   Register CondReg = MI.getOperand(1).getReg();
3710   LLT CondTy = MRI.getType(CondReg);
3711   if (CondTy.isVector()) // TODO: Handle vselect
3712     return UnableToLegalize;
3713 
3714   Register DstReg = MI.getOperand(0).getReg();
3715   LLT DstTy = MRI.getType(DstReg);
3716 
3717   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3718   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3719   SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
3720   LLT LeftoverTy;
3721   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
3722                     Src1Regs, Src1LeftoverRegs))
3723     return UnableToLegalize;
3724 
3725   LLT Unused;
3726   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
3727                     Src2Regs, Src2LeftoverRegs))
3728     llvm_unreachable("inconsistent extractParts result");
3729 
3730   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3731     auto Select = MIRBuilder.buildSelect(NarrowTy,
3732                                          CondReg, Src1Regs[I], Src2Regs[I]);
3733     DstRegs.push_back(Select->getOperand(0).getReg());
3734   }
3735 
3736   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3737     auto Select = MIRBuilder.buildSelect(
3738       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
3739     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
3740   }
3741 
3742   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3743               LeftoverTy, DstLeftoverRegs);
3744 
3745   MI.eraseFromParent();
3746   return Legalized;
3747 }
3748 
3749 LegalizerHelper::LegalizeResult
3750 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3751   unsigned Opc = MI.getOpcode();
3752   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
3753   auto isSupported = [this](const LegalityQuery &Q) {
3754     auto QAction = LI.getAction(Q).Action;
3755     return QAction == Legal || QAction == Libcall || QAction == Custom;
3756   };
3757   switch (Opc) {
3758   default:
3759     return UnableToLegalize;
3760   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
3761     // This trivially expands to CTLZ.
3762     Observer.changingInstr(MI);
3763     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
3764     Observer.changedInstr(MI);
3765     return Legalized;
3766   }
3767   case TargetOpcode::G_CTLZ: {
3768     Register SrcReg = MI.getOperand(1).getReg();
3769     unsigned Len = Ty.getSizeInBits();
3770     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
3771       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
3772       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
3773                                              {Ty}, {SrcReg});
3774       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3775       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3776       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3777                                           SrcReg, MIBZero);
3778       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3779                              MIBCtlzZU);
3780       MI.eraseFromParent();
3781       return Legalized;
3782     }
3783     // for now, we do this:
3784     // NewLen = NextPowerOf2(Len);
3785     // x = x | (x >> 1);
3786     // x = x | (x >> 2);
3787     // ...
3788     // x = x | (x >>16);
3789     // x = x | (x >>32); // for 64-bit input
3790     // Upto NewLen/2
3791     // return Len - popcount(x);
3792     //
3793     // Ref: "Hacker's Delight" by Henry Warren
3794     Register Op = SrcReg;
3795     unsigned NewLen = PowerOf2Ceil(Len);
3796     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
3797       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
3798       auto MIBOp = MIRBuilder.buildInstr(
3799           TargetOpcode::G_OR, {Ty},
3800           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
3801                                      {Op, MIBShiftAmt})});
3802       Op = MIBOp->getOperand(0).getReg();
3803     }
3804     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
3805     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3806                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
3807     MI.eraseFromParent();
3808     return Legalized;
3809   }
3810   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
3811     // This trivially expands to CTTZ.
3812     Observer.changingInstr(MI);
3813     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
3814     Observer.changedInstr(MI);
3815     return Legalized;
3816   }
3817   case TargetOpcode::G_CTTZ: {
3818     Register SrcReg = MI.getOperand(1).getReg();
3819     unsigned Len = Ty.getSizeInBits();
3820     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
3821       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
3822       // zero.
3823       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
3824                                              {Ty}, {SrcReg});
3825       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3826       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3827       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3828                                           SrcReg, MIBZero);
3829       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3830                              MIBCttzZU);
3831       MI.eraseFromParent();
3832       return Legalized;
3833     }
3834     // for now, we use: { return popcount(~x & (x - 1)); }
3835     // unless the target has ctlz but not ctpop, in which case we use:
3836     // { return 32 - nlz(~x & (x-1)); }
3837     // Ref: "Hacker's Delight" by Henry Warren
3838     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
3839     auto MIBNot =
3840         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
3841     auto MIBTmp = MIRBuilder.buildInstr(
3842         TargetOpcode::G_AND, {Ty},
3843         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
3844                                        {SrcReg, MIBCstNeg1})});
3845     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
3846         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
3847       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
3848       MIRBuilder.buildInstr(
3849           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3850           {MIBCstLen,
3851            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
3852       MI.eraseFromParent();
3853       return Legalized;
3854     }
3855     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
3856     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3857     return Legalized;
3858   }
3859   }
3860 }
3861 
3862 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
3863 // representation.
3864 LegalizerHelper::LegalizeResult
3865 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
3866   Register Dst = MI.getOperand(0).getReg();
3867   Register Src = MI.getOperand(1).getReg();
3868   const LLT S64 = LLT::scalar(64);
3869   const LLT S32 = LLT::scalar(32);
3870   const LLT S1 = LLT::scalar(1);
3871 
3872   assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
3873 
3874   // unsigned cul2f(ulong u) {
3875   //   uint lz = clz(u);
3876   //   uint e = (u != 0) ? 127U + 63U - lz : 0;
3877   //   u = (u << lz) & 0x7fffffffffffffffUL;
3878   //   ulong t = u & 0xffffffffffUL;
3879   //   uint v = (e << 23) | (uint)(u >> 40);
3880   //   uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
3881   //   return as_float(v + r);
3882   // }
3883 
3884   auto Zero32 = MIRBuilder.buildConstant(S32, 0);
3885   auto Zero64 = MIRBuilder.buildConstant(S64, 0);
3886 
3887   auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
3888 
3889   auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
3890   auto Sub = MIRBuilder.buildSub(S32, K, LZ);
3891 
3892   auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
3893   auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
3894 
3895   auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
3896   auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
3897 
3898   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
3899 
3900   auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
3901   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
3902 
3903   auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
3904   auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
3905   auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
3906 
3907   auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
3908   auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
3909   auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
3910   auto One = MIRBuilder.buildConstant(S32, 1);
3911 
3912   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
3913   auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
3914   auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
3915   MIRBuilder.buildAdd(Dst, V, R);
3916 
3917   return Legalized;
3918 }
3919 
3920 LegalizerHelper::LegalizeResult
3921 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3922   Register Dst = MI.getOperand(0).getReg();
3923   Register Src = MI.getOperand(1).getReg();
3924   LLT DstTy = MRI.getType(Dst);
3925   LLT SrcTy = MRI.getType(Src);
3926 
3927   if (SrcTy == LLT::scalar(1)) {
3928     auto True = MIRBuilder.buildFConstant(DstTy, 1.0);
3929     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
3930     MIRBuilder.buildSelect(Dst, Src, True, False);
3931     MI.eraseFromParent();
3932     return Legalized;
3933   }
3934 
3935   if (SrcTy != LLT::scalar(64))
3936     return UnableToLegalize;
3937 
3938   if (DstTy == LLT::scalar(32)) {
3939     // TODO: SelectionDAG has several alternative expansions to port which may
3940     // be more reasonble depending on the available instructions. If a target
3941     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
3942     // intermediate type, this is probably worse.
3943     return lowerU64ToF32BitOps(MI);
3944   }
3945 
3946   return UnableToLegalize;
3947 }
3948 
3949 LegalizerHelper::LegalizeResult
3950 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3951   Register Dst = MI.getOperand(0).getReg();
3952   Register Src = MI.getOperand(1).getReg();
3953   LLT DstTy = MRI.getType(Dst);
3954   LLT SrcTy = MRI.getType(Src);
3955 
3956   const LLT S64 = LLT::scalar(64);
3957   const LLT S32 = LLT::scalar(32);
3958   const LLT S1 = LLT::scalar(1);
3959 
3960   if (SrcTy == S1) {
3961     auto True = MIRBuilder.buildFConstant(DstTy, -1.0);
3962     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
3963     MIRBuilder.buildSelect(Dst, Src, True, False);
3964     MI.eraseFromParent();
3965     return Legalized;
3966   }
3967 
3968   if (SrcTy != S64)
3969     return UnableToLegalize;
3970 
3971   if (DstTy == S32) {
3972     // signed cl2f(long l) {
3973     //   long s = l >> 63;
3974     //   float r = cul2f((l + s) ^ s);
3975     //   return s ? -r : r;
3976     // }
3977     Register L = Src;
3978     auto SignBit = MIRBuilder.buildConstant(S64, 63);
3979     auto S = MIRBuilder.buildAShr(S64, L, SignBit);
3980 
3981     auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
3982     auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
3983     auto R = MIRBuilder.buildUITOFP(S32, Xor);
3984 
3985     auto RNeg = MIRBuilder.buildFNeg(S32, R);
3986     auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
3987                                             MIRBuilder.buildConstant(S64, 0));
3988     MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
3989     return Legalized;
3990   }
3991 
3992   return UnableToLegalize;
3993 }
3994 
3995 LegalizerHelper::LegalizeResult
3996 LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3997   Register Dst = MI.getOperand(0).getReg();
3998   Register Src = MI.getOperand(1).getReg();
3999   LLT DstTy = MRI.getType(Dst);
4000   LLT SrcTy = MRI.getType(Src);
4001   const LLT S64 = LLT::scalar(64);
4002   const LLT S32 = LLT::scalar(32);
4003 
4004   if (SrcTy != S64 && SrcTy != S32)
4005     return UnableToLegalize;
4006   if (DstTy != S32 && DstTy != S64)
4007     return UnableToLegalize;
4008 
4009   // FPTOSI gives same result as FPTOUI for positive signed integers.
4010   // FPTOUI needs to deal with fp values that convert to unsigned integers
4011   // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp.
4012 
4013   APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits());
4014   APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle()
4015                                                 : APFloat::IEEEdouble(),
4016                     APInt::getNullValue(SrcTy.getSizeInBits()));
4017   TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven);
4018 
4019   MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src);
4020 
4021   MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP);
4022   // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on
4023   // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1.
4024   MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold);
4025   MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub);
4026   MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt);
4027   MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit);
4028 
4029   const LLT S1 = LLT::scalar(1);
4030 
4031   MachineInstrBuilder FCMP =
4032       MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold);
4033   MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res);
4034 
4035   MI.eraseFromParent();
4036   return Legalized;
4037 }
4038 
4039 static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
4040   switch (Opc) {
4041   case TargetOpcode::G_SMIN:
4042     return CmpInst::ICMP_SLT;
4043   case TargetOpcode::G_SMAX:
4044     return CmpInst::ICMP_SGT;
4045   case TargetOpcode::G_UMIN:
4046     return CmpInst::ICMP_ULT;
4047   case TargetOpcode::G_UMAX:
4048     return CmpInst::ICMP_UGT;
4049   default:
4050     llvm_unreachable("not in integer min/max");
4051   }
4052 }
4053 
4054 LegalizerHelper::LegalizeResult
4055 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4056   Register Dst = MI.getOperand(0).getReg();
4057   Register Src0 = MI.getOperand(1).getReg();
4058   Register Src1 = MI.getOperand(2).getReg();
4059 
4060   const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
4061   LLT CmpType = MRI.getType(Dst).changeElementSize(1);
4062 
4063   auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
4064   MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
4065 
4066   MI.eraseFromParent();
4067   return Legalized;
4068 }
4069 
4070 LegalizerHelper::LegalizeResult
4071 LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4072   Register Dst = MI.getOperand(0).getReg();
4073   Register Src0 = MI.getOperand(1).getReg();
4074   Register Src1 = MI.getOperand(2).getReg();
4075 
4076   const LLT Src0Ty = MRI.getType(Src0);
4077   const LLT Src1Ty = MRI.getType(Src1);
4078 
4079   const int Src0Size = Src0Ty.getScalarSizeInBits();
4080   const int Src1Size = Src1Ty.getScalarSizeInBits();
4081 
4082   auto SignBitMask = MIRBuilder.buildConstant(
4083     Src0Ty, APInt::getSignMask(Src0Size));
4084 
4085   auto NotSignBitMask = MIRBuilder.buildConstant(
4086     Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
4087 
4088   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
4089   MachineInstr *Or;
4090 
4091   if (Src0Ty == Src1Ty) {
4092     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
4093     Or = MIRBuilder.buildOr(Dst, And0, And1);
4094   } else if (Src0Size > Src1Size) {
4095     auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
4096     auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
4097     auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
4098     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
4099     Or = MIRBuilder.buildOr(Dst, And0, And1);
4100   } else {
4101     auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
4102     auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
4103     auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
4104     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
4105     Or = MIRBuilder.buildOr(Dst, And0, And1);
4106   }
4107 
4108   // Be careful about setting nsz/nnan/ninf on every instruction, since the
4109   // constants are a nan and -0.0, but the final result should preserve
4110   // everything.
4111   if (unsigned Flags = MI.getFlags())
4112     Or->setFlags(Flags);
4113 
4114   MI.eraseFromParent();
4115   return Legalized;
4116 }
4117 
4118 LegalizerHelper::LegalizeResult
4119 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
4120   unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ?
4121     TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE;
4122 
4123   Register Dst = MI.getOperand(0).getReg();
4124   Register Src0 = MI.getOperand(1).getReg();
4125   Register Src1 = MI.getOperand(2).getReg();
4126   LLT Ty = MRI.getType(Dst);
4127 
4128   if (!MI.getFlag(MachineInstr::FmNoNans)) {
4129     // Insert canonicalizes if it's possible we need to quiet to get correct
4130     // sNaN behavior.
4131 
4132     // Note this must be done here, and not as an optimization combine in the
4133     // absence of a dedicate quiet-snan instruction as we're using an
4134     // omni-purpose G_FCANONICALIZE.
4135     if (!isKnownNeverSNaN(Src0, MRI))
4136       Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0);
4137 
4138     if (!isKnownNeverSNaN(Src1, MRI))
4139       Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0);
4140   }
4141 
4142   // If there are no nans, it's safe to simply replace this with the non-IEEE
4143   // version.
4144   MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags());
4145   MI.eraseFromParent();
4146   return Legalized;
4147 }
4148 
4149 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) {
4150   // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c
4151   Register DstReg = MI.getOperand(0).getReg();
4152   LLT Ty = MRI.getType(DstReg);
4153   unsigned Flags = MI.getFlags();
4154 
4155   auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2),
4156                                   Flags);
4157   MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags);
4158   MI.eraseFromParent();
4159   return Legalized;
4160 }
4161 
4162 LegalizerHelper::LegalizeResult
4163 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) {
4164   Register DstReg = MI.getOperand(0).getReg();
4165   Register SrcReg = MI.getOperand(1).getReg();
4166   unsigned Flags = MI.getFlags();
4167   LLT Ty = MRI.getType(DstReg);
4168   const LLT CondTy = Ty.changeElementSize(1);
4169 
4170   // result = trunc(src);
4171   // if (src < 0.0 && src != result)
4172   //   result += -1.0.
4173 
4174   auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
4175   auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags);
4176 
4177   auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy,
4178                                   SrcReg, Zero, Flags);
4179   auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy,
4180                                       SrcReg, Trunc, Flags);
4181   auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc);
4182   auto AddVal = MIRBuilder.buildSITOFP(Ty, And);
4183 
4184   MIRBuilder.buildFAdd(DstReg, Trunc, AddVal);
4185   MI.eraseFromParent();
4186   return Legalized;
4187 }
4188 
4189 LegalizerHelper::LegalizeResult
4190 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
4191   const unsigned NumDst = MI.getNumOperands() - 1;
4192   const Register SrcReg = MI.getOperand(NumDst).getReg();
4193   LLT SrcTy = MRI.getType(SrcReg);
4194 
4195   Register Dst0Reg = MI.getOperand(0).getReg();
4196   LLT DstTy = MRI.getType(Dst0Reg);
4197 
4198 
4199   // Expand scalarizing unmerge as bitcast to integer and shift.
4200   if (!DstTy.isVector() && SrcTy.isVector() &&
4201       SrcTy.getElementType() == DstTy) {
4202     LLT IntTy = LLT::scalar(SrcTy.getSizeInBits());
4203     Register Cast = MIRBuilder.buildBitcast(IntTy, SrcReg).getReg(0);
4204 
4205     MIRBuilder.buildTrunc(Dst0Reg, Cast);
4206 
4207     const unsigned DstSize = DstTy.getSizeInBits();
4208     unsigned Offset = DstSize;
4209     for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
4210       auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
4211       auto Shift = MIRBuilder.buildLShr(IntTy, Cast, ShiftAmt);
4212       MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
4213     }
4214 
4215     MI.eraseFromParent();
4216     return Legalized;
4217   }
4218 
4219   return UnableToLegalize;
4220 }
4221 
4222 LegalizerHelper::LegalizeResult
4223 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
4224   Register DstReg = MI.getOperand(0).getReg();
4225   Register Src0Reg = MI.getOperand(1).getReg();
4226   Register Src1Reg = MI.getOperand(2).getReg();
4227   LLT Src0Ty = MRI.getType(Src0Reg);
4228   LLT DstTy = MRI.getType(DstReg);
4229   LLT IdxTy = LLT::scalar(32);
4230 
4231   ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
4232 
4233   if (DstTy.isScalar()) {
4234     if (Src0Ty.isVector())
4235       return UnableToLegalize;
4236 
4237     // This is just a SELECT.
4238     assert(Mask.size() == 1 && "Expected a single mask element");
4239     Register Val;
4240     if (Mask[0] < 0 || Mask[0] > 1)
4241       Val = MIRBuilder.buildUndef(DstTy).getReg(0);
4242     else
4243       Val = Mask[0] == 0 ? Src0Reg : Src1Reg;
4244     MIRBuilder.buildCopy(DstReg, Val);
4245     MI.eraseFromParent();
4246     return Legalized;
4247   }
4248 
4249   Register Undef;
4250   SmallVector<Register, 32> BuildVec;
4251   LLT EltTy = DstTy.getElementType();
4252 
4253   for (int Idx : Mask) {
4254     if (Idx < 0) {
4255       if (!Undef.isValid())
4256         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);
4257       BuildVec.push_back(Undef);
4258       continue;
4259     }
4260 
4261     if (Src0Ty.isScalar()) {
4262       BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
4263     } else {
4264       int NumElts = Src0Ty.getNumElements();
4265       Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
4266       int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
4267       auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
4268       auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
4269       BuildVec.push_back(Extract.getReg(0));
4270     }
4271   }
4272 
4273   MIRBuilder.buildBuildVector(DstReg, BuildVec);
4274   MI.eraseFromParent();
4275   return Legalized;
4276 }
4277 
4278 LegalizerHelper::LegalizeResult
4279 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) {
4280   Register Dst = MI.getOperand(0).getReg();
4281   Register AllocSize = MI.getOperand(1).getReg();
4282   unsigned Align = MI.getOperand(2).getImm();
4283 
4284   const auto &MF = *MI.getMF();
4285   const auto &TLI = *MF.getSubtarget().getTargetLowering();
4286 
4287   LLT PtrTy = MRI.getType(Dst);
4288   LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
4289 
4290   Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
4291   auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg);
4292   SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp);
4293 
4294   // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't
4295   // have to generate an extra instruction to negate the alloc and then use
4296   // G_PTR_ADD to add the negative offset.
4297   auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize);
4298   if (Align) {
4299     APInt AlignMask(IntPtrTy.getSizeInBits(), Align, true);
4300     AlignMask.negate();
4301     auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask);
4302     Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst);
4303   }
4304 
4305   SPTmp = MIRBuilder.buildCast(PtrTy, Alloc);
4306   MIRBuilder.buildCopy(SPReg, SPTmp);
4307   MIRBuilder.buildCopy(Dst, SPTmp);
4308 
4309   MI.eraseFromParent();
4310   return Legalized;
4311 }
4312 
4313 LegalizerHelper::LegalizeResult
4314 LegalizerHelper::lowerExtract(MachineInstr &MI) {
4315   Register Dst = MI.getOperand(0).getReg();
4316   Register Src = MI.getOperand(1).getReg();
4317   unsigned Offset = MI.getOperand(2).getImm();
4318 
4319   LLT DstTy = MRI.getType(Dst);
4320   LLT SrcTy = MRI.getType(Src);
4321 
4322   if (DstTy.isScalar() &&
4323       (SrcTy.isScalar() ||
4324        (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
4325     LLT SrcIntTy = SrcTy;
4326     if (!SrcTy.isScalar()) {
4327       SrcIntTy = LLT::scalar(SrcTy.getSizeInBits());
4328       Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0);
4329     }
4330 
4331     if (Offset == 0)
4332       MIRBuilder.buildTrunc(Dst, Src);
4333     else {
4334       auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset);
4335       auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt);
4336       MIRBuilder.buildTrunc(Dst, Shr);
4337     }
4338 
4339     MI.eraseFromParent();
4340     return Legalized;
4341   }
4342 
4343   return UnableToLegalize;
4344 }
4345 
4346 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
4347   Register Dst = MI.getOperand(0).getReg();
4348   Register Src = MI.getOperand(1).getReg();
4349   Register InsertSrc = MI.getOperand(2).getReg();
4350   uint64_t Offset = MI.getOperand(3).getImm();
4351 
4352   LLT DstTy = MRI.getType(Src);
4353   LLT InsertTy = MRI.getType(InsertSrc);
4354 
4355   if (InsertTy.isScalar() &&
4356       (DstTy.isScalar() ||
4357        (DstTy.isVector() && DstTy.getElementType() == InsertTy))) {
4358     LLT IntDstTy = DstTy;
4359     if (!DstTy.isScalar()) {
4360       IntDstTy = LLT::scalar(DstTy.getSizeInBits());
4361       Src = MIRBuilder.buildBitcast(IntDstTy, Src).getReg(0);
4362     }
4363 
4364     Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0);
4365     if (Offset != 0) {
4366       auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset);
4367       ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0);
4368     }
4369 
4370     APInt MaskVal = ~APInt::getBitsSet(DstTy.getSizeInBits(), Offset,
4371                                        InsertTy.getSizeInBits());
4372 
4373     auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal);
4374     auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);
4375     auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc);
4376 
4377     MIRBuilder.buildBitcast(Dst, Or);
4378     MI.eraseFromParent();
4379     return Legalized;
4380   }
4381 
4382   return UnableToLegalize;
4383 }
4384 
4385 LegalizerHelper::LegalizeResult
4386 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {
4387   Register Dst0 = MI.getOperand(0).getReg();
4388   Register Dst1 = MI.getOperand(1).getReg();
4389   Register LHS = MI.getOperand(2).getReg();
4390   Register RHS = MI.getOperand(3).getReg();
4391   const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO;
4392 
4393   LLT Ty = MRI.getType(Dst0);
4394   LLT BoolTy = MRI.getType(Dst1);
4395 
4396   if (IsAdd)
4397     MIRBuilder.buildAdd(Dst0, LHS, RHS);
4398   else
4399     MIRBuilder.buildSub(Dst0, LHS, RHS);
4400 
4401   // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
4402 
4403   auto Zero = MIRBuilder.buildConstant(Ty, 0);
4404 
4405   // For an addition, the result should be less than one of the operands (LHS)
4406   // if and only if the other operand (RHS) is negative, otherwise there will
4407   // be overflow.
4408   // For a subtraction, the result should be less than one of the operands
4409   // (LHS) if and only if the other operand (RHS) is (non-zero) positive,
4410   // otherwise there will be overflow.
4411   auto ResultLowerThanLHS =
4412       MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS);
4413   auto ConditionRHS = MIRBuilder.buildICmp(
4414       IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero);
4415 
4416   MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS);
4417   MI.eraseFromParent();
4418   return Legalized;
4419 }
4420 
4421 LegalizerHelper::LegalizeResult
4422 LegalizerHelper::lowerBswap(MachineInstr &MI) {
4423   Register Dst = MI.getOperand(0).getReg();
4424   Register Src = MI.getOperand(1).getReg();
4425   const LLT Ty = MRI.getType(Src);
4426   unsigned SizeInBytes = Ty.getSizeInBytes();
4427   unsigned BaseShiftAmt = (SizeInBytes - 1) * 8;
4428 
4429   // Swap most and least significant byte, set remaining bytes in Res to zero.
4430   auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt);
4431   auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt);
4432   auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
4433   auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft);
4434 
4435   // Set i-th high/low byte in Res to i-th low/high byte from Src.
4436   for (unsigned i = 1; i < SizeInBytes / 2; ++i) {
4437     // AND with Mask leaves byte i unchanged and sets remaining bytes to 0.
4438     APInt APMask(SizeInBytes * 8, 0xFF << (i * 8));
4439     auto Mask = MIRBuilder.buildConstant(Ty, APMask);
4440     auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i);
4441     // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt.
4442     auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask);
4443     auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt);
4444     Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft);
4445     // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask.
4446     auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
4447     auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask);
4448     Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight);
4449   }
4450   Res.getInstr()->getOperand(0).setReg(Dst);
4451 
4452   MI.eraseFromParent();
4453   return Legalized;
4454 }
4455 
4456 //{ (Src & Mask) >> N } | { (Src << N) & Mask }
4457 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B,
4458                                  MachineInstrBuilder Src, APInt Mask) {
4459   const LLT Ty = Dst.getLLTTy(*B.getMRI());
4460   MachineInstrBuilder C_N = B.buildConstant(Ty, N);
4461   MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask);
4462   auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N);
4463   auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0);
4464   return B.buildOr(Dst, LHS, RHS);
4465 }
4466 
4467 LegalizerHelper::LegalizeResult
4468 LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
4469   Register Dst = MI.getOperand(0).getReg();
4470   Register Src = MI.getOperand(1).getReg();
4471   const LLT Ty = MRI.getType(Src);
4472   unsigned Size = Ty.getSizeInBits();
4473 
4474   MachineInstrBuilder BSWAP =
4475       MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src});
4476 
4477   // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654
4478   //    [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4]
4479   // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0]
4480   MachineInstrBuilder Swap4 =
4481       SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0)));
4482 
4483   // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76
4484   //    [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2]
4485   // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC]
4486   MachineInstrBuilder Swap2 =
4487       SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC)));
4488 
4489   // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7
4490   //    [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1]
4491   // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA]
4492   SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA)));
4493 
4494   MI.eraseFromParent();
4495   return Legalized;
4496 }
4497 
4498 LegalizerHelper::LegalizeResult
4499 LegalizerHelper::lowerReadRegister(MachineInstr &MI) {
4500   Register Dst = MI.getOperand(0).getReg();
4501   const LLT Ty = MRI.getType(Dst);
4502   const MDString *RegStr = cast<MDString>(
4503     cast<MDNode>(MI.getOperand(1).getMetadata())->getOperand(0));
4504 
4505   MachineFunction &MF = MIRBuilder.getMF();
4506   const TargetSubtargetInfo &STI = MF.getSubtarget();
4507   const TargetLowering *TLI = STI.getTargetLowering();
4508   Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
4509   if (!Reg.isValid())
4510     return UnableToLegalize;
4511 
4512   MIRBuilder.buildCopy(Dst, Reg);
4513   MI.eraseFromParent();
4514   return Legalized;
4515 }
4516