1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file implements the LegalizerHelper class to legalize
11 /// individual instructions and the LegalizeMachineIR wrapper pass for the
12 /// primary legalization.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
17 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
18 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
19 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetLowering.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 
28 #define DEBUG_TYPE "legalizer"
29 
30 using namespace llvm;
31 using namespace LegalizeActions;
32 
33 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
34                                  GISelChangeObserver &Observer)
35     : MRI(MF.getRegInfo()), LI(*MF.getSubtarget().getLegalizerInfo()),
36       Observer(Observer) {
37   MIRBuilder.setMF(MF);
38   MIRBuilder.setChangeObserver(Observer);
39 }
40 
41 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
42                                  GISelChangeObserver &Observer)
43     : MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
44   MIRBuilder.setMF(MF);
45   MIRBuilder.setChangeObserver(Observer);
46 }
47 LegalizerHelper::LegalizeResult
48 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
49   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
50 
51   auto Step = LI.getAction(MI, MRI);
52   switch (Step.Action) {
53   case Legal:
54     LLVM_DEBUG(dbgs() << ".. Already legal\n");
55     return AlreadyLegal;
56   case Libcall:
57     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
58     return libcall(MI);
59   case NarrowScalar:
60     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
61     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
62   case WidenScalar:
63     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
64     return widenScalar(MI, Step.TypeIdx, Step.NewType);
65   case Lower:
66     LLVM_DEBUG(dbgs() << ".. Lower\n");
67     return lower(MI, Step.TypeIdx, Step.NewType);
68   case FewerElements:
69     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
70     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
71   case Custom:
72     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
73     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
74                                                             : UnableToLegalize;
75   default:
76     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
77     return UnableToLegalize;
78   }
79 }
80 
81 void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
82                                    SmallVectorImpl<unsigned> &VRegs) {
83   for (int i = 0; i < NumParts; ++i)
84     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
85   MIRBuilder.buildUnmerge(VRegs, Reg);
86 }
87 
88 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
89   switch (Opcode) {
90   case TargetOpcode::G_SDIV:
91     assert((Size == 32 || Size == 64) && "Unsupported size");
92     return Size == 64 ? RTLIB::SDIV_I64 : RTLIB::SDIV_I32;
93   case TargetOpcode::G_UDIV:
94     assert((Size == 32 || Size == 64) && "Unsupported size");
95     return Size == 64 ? RTLIB::UDIV_I64 : RTLIB::UDIV_I32;
96   case TargetOpcode::G_SREM:
97     assert((Size == 32 || Size == 64) && "Unsupported size");
98     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
99   case TargetOpcode::G_UREM:
100     assert((Size == 32 || Size == 64) && "Unsupported size");
101     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
102   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
103     assert(Size == 32 && "Unsupported size");
104     return RTLIB::CTLZ_I32;
105   case TargetOpcode::G_FADD:
106     assert((Size == 32 || Size == 64) && "Unsupported size");
107     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
108   case TargetOpcode::G_FSUB:
109     assert((Size == 32 || Size == 64) && "Unsupported size");
110     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
111   case TargetOpcode::G_FMUL:
112     assert((Size == 32 || Size == 64) && "Unsupported size");
113     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
114   case TargetOpcode::G_FDIV:
115     assert((Size == 32 || Size == 64) && "Unsupported size");
116     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
117   case TargetOpcode::G_FREM:
118     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
119   case TargetOpcode::G_FPOW:
120     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
121   case TargetOpcode::G_FMA:
122     assert((Size == 32 || Size == 64) && "Unsupported size");
123     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
124   }
125   llvm_unreachable("Unknown libcall function");
126 }
127 
128 LegalizerHelper::LegalizeResult
129 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
130                     const CallLowering::ArgInfo &Result,
131                     ArrayRef<CallLowering::ArgInfo> Args) {
132   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
133   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
134   const char *Name = TLI.getLibcallName(Libcall);
135 
136   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
137   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
138                      MachineOperand::CreateES(Name), Result, Args))
139     return LegalizerHelper::UnableToLegalize;
140 
141   return LegalizerHelper::Legalized;
142 }
143 
144 // Useful for libcalls where all operands have the same type.
145 static LegalizerHelper::LegalizeResult
146 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
147               Type *OpType) {
148   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
149 
150   SmallVector<CallLowering::ArgInfo, 3> Args;
151   for (unsigned i = 1; i < MI.getNumOperands(); i++)
152     Args.push_back({MI.getOperand(i).getReg(), OpType});
153   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
154                        Args);
155 }
156 
157 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
158                                        Type *FromType) {
159   auto ToMVT = MVT::getVT(ToType);
160   auto FromMVT = MVT::getVT(FromType);
161 
162   switch (Opcode) {
163   case TargetOpcode::G_FPEXT:
164     return RTLIB::getFPEXT(FromMVT, ToMVT);
165   case TargetOpcode::G_FPTRUNC:
166     return RTLIB::getFPROUND(FromMVT, ToMVT);
167   case TargetOpcode::G_FPTOSI:
168     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
169   case TargetOpcode::G_FPTOUI:
170     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
171   case TargetOpcode::G_SITOFP:
172     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
173   case TargetOpcode::G_UITOFP:
174     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
175   }
176   llvm_unreachable("Unsupported libcall function");
177 }
178 
179 static LegalizerHelper::LegalizeResult
180 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
181                   Type *FromType) {
182   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
183   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
184                        {{MI.getOperand(1).getReg(), FromType}});
185 }
186 
187 LegalizerHelper::LegalizeResult
188 LegalizerHelper::libcall(MachineInstr &MI) {
189   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
190   unsigned Size = LLTy.getSizeInBits();
191   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
192 
193   MIRBuilder.setInstr(MI);
194 
195   switch (MI.getOpcode()) {
196   default:
197     return UnableToLegalize;
198   case TargetOpcode::G_SDIV:
199   case TargetOpcode::G_UDIV:
200   case TargetOpcode::G_SREM:
201   case TargetOpcode::G_UREM:
202   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
203     Type *HLTy = IntegerType::get(Ctx, Size);
204     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
205     if (Status != Legalized)
206       return Status;
207     break;
208   }
209   case TargetOpcode::G_FADD:
210   case TargetOpcode::G_FSUB:
211   case TargetOpcode::G_FMUL:
212   case TargetOpcode::G_FDIV:
213   case TargetOpcode::G_FMA:
214   case TargetOpcode::G_FPOW:
215   case TargetOpcode::G_FREM: {
216     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
217     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
218     if (Status != Legalized)
219       return Status;
220     break;
221   }
222   case TargetOpcode::G_FPEXT: {
223     // FIXME: Support other floating point types (half, fp128 etc)
224     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
225     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
226     if (ToSize != 64 || FromSize != 32)
227       return UnableToLegalize;
228     LegalizeResult Status = conversionLibcall(
229         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
230     if (Status != Legalized)
231       return Status;
232     break;
233   }
234   case TargetOpcode::G_FPTRUNC: {
235     // FIXME: Support other floating point types (half, fp128 etc)
236     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
237     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
238     if (ToSize != 32 || FromSize != 64)
239       return UnableToLegalize;
240     LegalizeResult Status = conversionLibcall(
241         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
242     if (Status != Legalized)
243       return Status;
244     break;
245   }
246   case TargetOpcode::G_FPTOSI:
247   case TargetOpcode::G_FPTOUI: {
248     // FIXME: Support other types
249     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
250     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
251     if (ToSize != 32 || (FromSize != 32 && FromSize != 64))
252       return UnableToLegalize;
253     LegalizeResult Status = conversionLibcall(
254         MI, MIRBuilder, Type::getInt32Ty(Ctx),
255         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
256     if (Status != Legalized)
257       return Status;
258     break;
259   }
260   case TargetOpcode::G_SITOFP:
261   case TargetOpcode::G_UITOFP: {
262     // FIXME: Support other types
263     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
264     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
265     if (FromSize != 32 || (ToSize != 32 && ToSize != 64))
266       return UnableToLegalize;
267     LegalizeResult Status = conversionLibcall(
268         MI, MIRBuilder,
269         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
270         Type::getInt32Ty(Ctx));
271     if (Status != Legalized)
272       return Status;
273     break;
274   }
275   }
276 
277   MI.eraseFromParent();
278   return Legalized;
279 }
280 
281 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
282                                                               unsigned TypeIdx,
283                                                               LLT NarrowTy) {
284   // FIXME: Don't know how to handle secondary types yet.
285   if (TypeIdx != 0 && MI.getOpcode() != TargetOpcode::G_EXTRACT)
286     return UnableToLegalize;
287 
288   MIRBuilder.setInstr(MI);
289 
290   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
291   uint64_t NarrowSize = NarrowTy.getSizeInBits();
292 
293   switch (MI.getOpcode()) {
294   default:
295     return UnableToLegalize;
296   case TargetOpcode::G_IMPLICIT_DEF: {
297     // FIXME: add support for when SizeOp0 isn't an exact multiple of
298     // NarrowSize.
299     if (SizeOp0 % NarrowSize != 0)
300       return UnableToLegalize;
301     int NumParts = SizeOp0 / NarrowSize;
302 
303     SmallVector<unsigned, 2> DstRegs;
304     for (int i = 0; i < NumParts; ++i)
305       DstRegs.push_back(
306           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
307 
308     unsigned DstReg = MI.getOperand(0).getReg();
309     if(MRI.getType(DstReg).isVector())
310       MIRBuilder.buildBuildVector(DstReg, DstRegs);
311     else
312       MIRBuilder.buildMerge(DstReg, DstRegs);
313     MI.eraseFromParent();
314     return Legalized;
315   }
316   case TargetOpcode::G_ADD: {
317     // FIXME: add support for when SizeOp0 isn't an exact multiple of
318     // NarrowSize.
319     if (SizeOp0 % NarrowSize != 0)
320       return UnableToLegalize;
321     // Expand in terms of carry-setting/consuming G_ADDE instructions.
322     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
323 
324     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
325     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
326     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
327 
328     unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
329     MIRBuilder.buildConstant(CarryIn, 0);
330 
331     for (int i = 0; i < NumParts; ++i) {
332       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
333       unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
334 
335       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
336                             Src2Regs[i], CarryIn);
337 
338       DstRegs.push_back(DstReg);
339       CarryIn = CarryOut;
340     }
341     unsigned DstReg = MI.getOperand(0).getReg();
342     if(MRI.getType(DstReg).isVector())
343       MIRBuilder.buildBuildVector(DstReg, DstRegs);
344     else
345       MIRBuilder.buildMerge(DstReg, DstRegs);
346     MI.eraseFromParent();
347     return Legalized;
348   }
349   case TargetOpcode::G_EXTRACT: {
350     if (TypeIdx != 1)
351       return UnableToLegalize;
352 
353     int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
354     // FIXME: add support for when SizeOp1 isn't an exact multiple of
355     // NarrowSize.
356     if (SizeOp1 % NarrowSize != 0)
357       return UnableToLegalize;
358     int NumParts = SizeOp1 / NarrowSize;
359 
360     SmallVector<unsigned, 2> SrcRegs, DstRegs;
361     SmallVector<uint64_t, 2> Indexes;
362     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
363 
364     unsigned OpReg = MI.getOperand(0).getReg();
365     uint64_t OpStart = MI.getOperand(2).getImm();
366     uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
367     for (int i = 0; i < NumParts; ++i) {
368       unsigned SrcStart = i * NarrowSize;
369 
370       if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
371         // No part of the extract uses this subregister, ignore it.
372         continue;
373       } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
374         // The entire subregister is extracted, forward the value.
375         DstRegs.push_back(SrcRegs[i]);
376         continue;
377       }
378 
379       // OpSegStart is where this destination segment would start in OpReg if it
380       // extended infinitely in both directions.
381       int64_t ExtractOffset;
382       uint64_t SegSize;
383       if (OpStart < SrcStart) {
384         ExtractOffset = 0;
385         SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
386       } else {
387         ExtractOffset = OpStart - SrcStart;
388         SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
389       }
390 
391       unsigned SegReg = SrcRegs[i];
392       if (ExtractOffset != 0 || SegSize != NarrowSize) {
393         // A genuine extract is needed.
394         SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
395         MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
396       }
397 
398       DstRegs.push_back(SegReg);
399     }
400 
401     unsigned DstReg = MI.getOperand(0).getReg();
402     if(MRI.getType(DstReg).isVector())
403       MIRBuilder.buildBuildVector(DstReg, DstRegs);
404     else
405       MIRBuilder.buildMerge(DstReg, DstRegs);
406     MI.eraseFromParent();
407     return Legalized;
408   }
409   case TargetOpcode::G_INSERT: {
410     // FIXME: add support for when SizeOp0 isn't an exact multiple of
411     // NarrowSize.
412     if (SizeOp0 % NarrowSize != 0)
413       return UnableToLegalize;
414 
415     int NumParts = SizeOp0 / NarrowSize;
416 
417     SmallVector<unsigned, 2> SrcRegs, DstRegs;
418     SmallVector<uint64_t, 2> Indexes;
419     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
420 
421     unsigned OpReg = MI.getOperand(2).getReg();
422     uint64_t OpStart = MI.getOperand(3).getImm();
423     uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
424     for (int i = 0; i < NumParts; ++i) {
425       unsigned DstStart = i * NarrowSize;
426 
427       if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
428         // No part of the insert affects this subregister, forward the original.
429         DstRegs.push_back(SrcRegs[i]);
430         continue;
431       } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
432         // The entire subregister is defined by this insert, forward the new
433         // value.
434         DstRegs.push_back(OpReg);
435         continue;
436       }
437 
438       // OpSegStart is where this destination segment would start in OpReg if it
439       // extended infinitely in both directions.
440       int64_t ExtractOffset, InsertOffset;
441       uint64_t SegSize;
442       if (OpStart < DstStart) {
443         InsertOffset = 0;
444         ExtractOffset = DstStart - OpStart;
445         SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
446       } else {
447         InsertOffset = OpStart - DstStart;
448         ExtractOffset = 0;
449         SegSize =
450             std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
451       }
452 
453       unsigned SegReg = OpReg;
454       if (ExtractOffset != 0 || SegSize != OpSize) {
455         // A genuine extract is needed.
456         SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
457         MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
458       }
459 
460       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
461       MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
462       DstRegs.push_back(DstReg);
463     }
464 
465     assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
466     unsigned DstReg = MI.getOperand(0).getReg();
467     if(MRI.getType(DstReg).isVector())
468       MIRBuilder.buildBuildVector(DstReg, DstRegs);
469     else
470       MIRBuilder.buildMerge(DstReg, DstRegs);
471     MI.eraseFromParent();
472     return Legalized;
473   }
474   case TargetOpcode::G_LOAD: {
475     // FIXME: add support for when SizeOp0 isn't an exact multiple of
476     // NarrowSize.
477     if (SizeOp0 % NarrowSize != 0)
478       return UnableToLegalize;
479 
480     const auto &MMO = **MI.memoperands_begin();
481     // This implementation doesn't work for atomics. Give up instead of doing
482     // something invalid.
483     if (MMO.getOrdering() != AtomicOrdering::NotAtomic ||
484         MMO.getFailureOrdering() != AtomicOrdering::NotAtomic)
485       return UnableToLegalize;
486 
487     int NumParts = SizeOp0 / NarrowSize;
488     LLT OffsetTy = LLT::scalar(
489         MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
490 
491     SmallVector<unsigned, 2> DstRegs;
492     for (int i = 0; i < NumParts; ++i) {
493       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
494       unsigned SrcReg = 0;
495       unsigned Adjustment = i * NarrowSize / 8;
496       unsigned Alignment = MinAlign(MMO.getAlignment(), Adjustment);
497 
498       MachineMemOperand *SplitMMO = MIRBuilder.getMF().getMachineMemOperand(
499           MMO.getPointerInfo().getWithOffset(Adjustment), MMO.getFlags(),
500           NarrowSize / 8, Alignment, MMO.getAAInfo(), MMO.getRanges(),
501           MMO.getSyncScopeID(), MMO.getOrdering(), MMO.getFailureOrdering());
502 
503       MIRBuilder.materializeGEP(SrcReg, MI.getOperand(1).getReg(), OffsetTy,
504                                 Adjustment);
505 
506       MIRBuilder.buildLoad(DstReg, SrcReg, *SplitMMO);
507 
508       DstRegs.push_back(DstReg);
509     }
510     unsigned DstReg = MI.getOperand(0).getReg();
511     if(MRI.getType(DstReg).isVector())
512       MIRBuilder.buildBuildVector(DstReg, DstRegs);
513     else
514       MIRBuilder.buildMerge(DstReg, DstRegs);
515     MI.eraseFromParent();
516     return Legalized;
517   }
518   case TargetOpcode::G_STORE: {
519     // FIXME: add support for when SizeOp0 isn't an exact multiple of
520     // NarrowSize.
521     if (SizeOp0 % NarrowSize != 0)
522       return UnableToLegalize;
523 
524     const auto &MMO = **MI.memoperands_begin();
525     // This implementation doesn't work for atomics. Give up instead of doing
526     // something invalid.
527     if (MMO.getOrdering() != AtomicOrdering::NotAtomic ||
528         MMO.getFailureOrdering() != AtomicOrdering::NotAtomic)
529       return UnableToLegalize;
530 
531     int NumParts = SizeOp0 / NarrowSize;
532     LLT OffsetTy = LLT::scalar(
533         MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
534 
535     SmallVector<unsigned, 2> SrcRegs;
536     extractParts(MI.getOperand(0).getReg(), NarrowTy, NumParts, SrcRegs);
537 
538     for (int i = 0; i < NumParts; ++i) {
539       unsigned DstReg = 0;
540       unsigned Adjustment = i * NarrowSize / 8;
541       unsigned Alignment = MinAlign(MMO.getAlignment(), Adjustment);
542 
543       MachineMemOperand *SplitMMO = MIRBuilder.getMF().getMachineMemOperand(
544           MMO.getPointerInfo().getWithOffset(Adjustment), MMO.getFlags(),
545           NarrowSize / 8, Alignment, MMO.getAAInfo(), MMO.getRanges(),
546           MMO.getSyncScopeID(), MMO.getOrdering(), MMO.getFailureOrdering());
547 
548       MIRBuilder.materializeGEP(DstReg, MI.getOperand(1).getReg(), OffsetTy,
549                                 Adjustment);
550 
551       MIRBuilder.buildStore(SrcRegs[i], DstReg, *SplitMMO);
552     }
553     MI.eraseFromParent();
554     return Legalized;
555   }
556   case TargetOpcode::G_CONSTANT: {
557     // FIXME: add support for when SizeOp0 isn't an exact multiple of
558     // NarrowSize.
559     if (SizeOp0 % NarrowSize != 0)
560       return UnableToLegalize;
561     int NumParts = SizeOp0 / NarrowSize;
562     const APInt &Cst = MI.getOperand(1).getCImm()->getValue();
563     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
564 
565     SmallVector<unsigned, 2> DstRegs;
566     for (int i = 0; i < NumParts; ++i) {
567       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
568       ConstantInt *CI =
569           ConstantInt::get(Ctx, Cst.lshr(NarrowSize * i).trunc(NarrowSize));
570       MIRBuilder.buildConstant(DstReg, *CI);
571       DstRegs.push_back(DstReg);
572     }
573     unsigned DstReg = MI.getOperand(0).getReg();
574     if(MRI.getType(DstReg).isVector())
575       MIRBuilder.buildBuildVector(DstReg, DstRegs);
576     else
577       MIRBuilder.buildMerge(DstReg, DstRegs);
578     MI.eraseFromParent();
579     return Legalized;
580   }
581   case TargetOpcode::G_AND:
582   case TargetOpcode::G_OR:
583   case TargetOpcode::G_XOR: {
584     // Legalize bitwise operation:
585     // A = BinOp<Ty> B, C
586     // into:
587     // B1, ..., BN = G_UNMERGE_VALUES B
588     // C1, ..., CN = G_UNMERGE_VALUES C
589     // A1 = BinOp<Ty/N> B1, C2
590     // ...
591     // AN = BinOp<Ty/N> BN, CN
592     // A = G_MERGE_VALUES A1, ..., AN
593 
594     // FIXME: add support for when SizeOp0 isn't an exact multiple of
595     // NarrowSize.
596     if (SizeOp0 % NarrowSize != 0)
597       return UnableToLegalize;
598     int NumParts = SizeOp0 / NarrowSize;
599 
600     // List the registers where the destination will be scattered.
601     SmallVector<unsigned, 2> DstRegs;
602     // List the registers where the first argument will be split.
603     SmallVector<unsigned, 2> SrcsReg1;
604     // List the registers where the second argument will be split.
605     SmallVector<unsigned, 2> SrcsReg2;
606     // Create all the temporary registers.
607     for (int i = 0; i < NumParts; ++i) {
608       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
609       unsigned SrcReg1 = MRI.createGenericVirtualRegister(NarrowTy);
610       unsigned SrcReg2 = MRI.createGenericVirtualRegister(NarrowTy);
611 
612       DstRegs.push_back(DstReg);
613       SrcsReg1.push_back(SrcReg1);
614       SrcsReg2.push_back(SrcReg2);
615     }
616     // Explode the big arguments into smaller chunks.
617     MIRBuilder.buildUnmerge(SrcsReg1, MI.getOperand(1).getReg());
618     MIRBuilder.buildUnmerge(SrcsReg2, MI.getOperand(2).getReg());
619 
620     // Do the operation on each small part.
621     for (int i = 0; i < NumParts; ++i)
622       MIRBuilder.buildInstr(MI.getOpcode(), {DstRegs[i]},
623                             {SrcsReg1[i], SrcsReg2[i]});
624 
625     // Gather the destination registers into the final destination.
626     unsigned DstReg = MI.getOperand(0).getReg();
627     if(MRI.getType(DstReg).isVector())
628       MIRBuilder.buildBuildVector(DstReg, DstRegs);
629     else
630       MIRBuilder.buildMerge(DstReg, DstRegs);
631     MI.eraseFromParent();
632     return Legalized;
633   }
634   }
635 }
636 
637 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
638                                      unsigned OpIdx, unsigned ExtOpcode) {
639   MachineOperand &MO = MI.getOperand(OpIdx);
640   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
641   MO.setReg(ExtB->getOperand(0).getReg());
642 }
643 
644 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
645                                      unsigned OpIdx, unsigned TruncOpcode) {
646   MachineOperand &MO = MI.getOperand(OpIdx);
647   unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
648   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
649   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
650   MO.setReg(DstExt);
651 }
652 
653 LegalizerHelper::LegalizeResult
654 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
655   MIRBuilder.setInstr(MI);
656 
657   switch (MI.getOpcode()) {
658   default:
659     return UnableToLegalize;
660   case TargetOpcode::G_UADDO:
661   case TargetOpcode::G_USUBO: {
662     if (TypeIdx == 1)
663       return UnableToLegalize; // TODO
664     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
665                                          {MI.getOperand(2).getReg()});
666     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
667                                          {MI.getOperand(3).getReg()});
668     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
669                           ? TargetOpcode::G_ADD
670                           : TargetOpcode::G_SUB;
671     // Do the arithmetic in the larger type.
672     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
673     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
674     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
675     auto AndOp = MIRBuilder.buildInstr(
676         TargetOpcode::G_AND, {WideTy},
677         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
678     // There is no overflow if the AndOp is the same as NewOp.
679     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
680                          AndOp);
681     // Now trunc the NewOp to the original result.
682     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
683     MI.eraseFromParent();
684     return Legalized;
685   }
686   case TargetOpcode::G_CTTZ:
687   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
688   case TargetOpcode::G_CTLZ:
689   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
690   case TargetOpcode::G_CTPOP: {
691     // First ZEXT the input.
692     auto MIBSrc = MIRBuilder.buildZExt(WideTy, MI.getOperand(1).getReg());
693     LLT CurTy = MRI.getType(MI.getOperand(0).getReg());
694     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
695       // The count is the same in the larger type except if the original
696       // value was zero.  This can be handled by setting the bit just off
697       // the top of the original type.
698       auto TopBit =
699           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
700       MIBSrc = MIRBuilder.buildInstr(
701           TargetOpcode::G_OR, {WideTy},
702           {MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit.getSExtValue())});
703     }
704     // Perform the operation at the larger size.
705     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
706     // This is already the correct result for CTPOP and CTTZs
707     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
708         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
709       // The correct result is NewOp - (Difference in widety and current ty).
710       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
711       MIBNewOp = MIRBuilder.buildInstr(
712           TargetOpcode::G_SUB, {WideTy},
713           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
714     }
715     auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
716     // Make the original instruction a trunc now, and update its source.
717     Observer.changingInstr(MI);
718     MI.setDesc(TII.get(TargetOpcode::G_TRUNC));
719     MI.getOperand(1).setReg(MIBNewOp->getOperand(0).getReg());
720     Observer.changedInstr(MI);
721     return Legalized;
722   }
723 
724   case TargetOpcode::G_ADD:
725   case TargetOpcode::G_AND:
726   case TargetOpcode::G_MUL:
727   case TargetOpcode::G_OR:
728   case TargetOpcode::G_XOR:
729   case TargetOpcode::G_SUB:
730     // Perform operation at larger width (any extension is fine here, high bits
731     // don't affect the result) and then truncate the result back to the
732     // original type.
733     Observer.changingInstr(MI);
734     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
735     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
736     widenScalarDst(MI, WideTy);
737     Observer.changedInstr(MI);
738     return Legalized;
739 
740   case TargetOpcode::G_SHL:
741     Observer.changingInstr(MI);
742     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
743     // The "number of bits to shift" operand must preserve its value as an
744     // unsigned integer:
745     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
746     widenScalarDst(MI, WideTy);
747     Observer.changedInstr(MI);
748     return Legalized;
749 
750   case TargetOpcode::G_SDIV:
751   case TargetOpcode::G_SREM:
752     Observer.changingInstr(MI);
753     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
754     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
755     widenScalarDst(MI, WideTy);
756     Observer.changedInstr(MI);
757     return Legalized;
758 
759   case TargetOpcode::G_ASHR:
760     Observer.changingInstr(MI);
761     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
762     // The "number of bits to shift" operand must preserve its value as an
763     // unsigned integer:
764     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
765     widenScalarDst(MI, WideTy);
766     Observer.changedInstr(MI);
767     return Legalized;
768 
769   case TargetOpcode::G_UDIV:
770   case TargetOpcode::G_UREM:
771   case TargetOpcode::G_LSHR:
772     Observer.changingInstr(MI);
773     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
774     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
775     widenScalarDst(MI, WideTy);
776     Observer.changedInstr(MI);
777     return Legalized;
778 
779   case TargetOpcode::G_SELECT:
780     Observer.changingInstr(MI);
781     if (TypeIdx == 0) {
782       // Perform operation at larger width (any extension is fine here, high
783       // bits don't affect the result) and then truncate the result back to the
784       // original type.
785       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
786       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
787       widenScalarDst(MI, WideTy);
788     } else {
789       // Explicit extension is required here since high bits affect the result.
790       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
791     }
792     Observer.changedInstr(MI);
793     return Legalized;
794 
795   case TargetOpcode::G_FPTOSI:
796   case TargetOpcode::G_FPTOUI:
797     if (TypeIdx != 0)
798       return UnableToLegalize;
799     Observer.changingInstr(MI);
800     widenScalarDst(MI, WideTy);
801     Observer.changedInstr(MI);
802     return Legalized;
803 
804   case TargetOpcode::G_SITOFP:
805     if (TypeIdx != 1)
806       return UnableToLegalize;
807     Observer.changingInstr(MI);
808     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
809     Observer.changedInstr(MI);
810     return Legalized;
811 
812   case TargetOpcode::G_UITOFP:
813     if (TypeIdx != 1)
814       return UnableToLegalize;
815     Observer.changingInstr(MI);
816     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
817     Observer.changedInstr(MI);
818     return Legalized;
819 
820   case TargetOpcode::G_INSERT:
821     if (TypeIdx != 0)
822       return UnableToLegalize;
823     Observer.changingInstr(MI);
824     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
825     widenScalarDst(MI, WideTy);
826     Observer.changedInstr(MI);
827     return Legalized;
828 
829   case TargetOpcode::G_LOAD:
830     // For some types like i24, we might try to widen to i32. To properly handle
831     // this we should be using a dedicated extending load, until then avoid
832     // trying to legalize.
833     if (alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) !=
834         WideTy.getSizeInBits())
835       return UnableToLegalize;
836     LLVM_FALLTHROUGH;
837   case TargetOpcode::G_SEXTLOAD:
838   case TargetOpcode::G_ZEXTLOAD:
839     Observer.changingInstr(MI);
840     widenScalarDst(MI, WideTy);
841     Observer.changedInstr(MI);
842     return Legalized;
843 
844   case TargetOpcode::G_STORE: {
845     if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(1) ||
846         WideTy != LLT::scalar(8))
847       return UnableToLegalize;
848 
849     Observer.changingInstr(MI);
850     widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ZEXT);
851     Observer.changedInstr(MI);
852     return Legalized;
853   }
854   case TargetOpcode::G_CONSTANT: {
855     MachineOperand &SrcMO = MI.getOperand(1);
856     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
857     const APInt &Val = SrcMO.getCImm()->getValue().sext(WideTy.getSizeInBits());
858     Observer.changingInstr(MI);
859     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
860 
861     widenScalarDst(MI, WideTy);
862     Observer.changedInstr(MI);
863     return Legalized;
864   }
865   case TargetOpcode::G_FCONSTANT: {
866     MachineOperand &SrcMO = MI.getOperand(1);
867     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
868     APFloat Val = SrcMO.getFPImm()->getValueAPF();
869     bool LosesInfo;
870     switch (WideTy.getSizeInBits()) {
871     case 32:
872       Val.convert(APFloat::IEEEsingle(), APFloat::rmTowardZero, &LosesInfo);
873       break;
874     case 64:
875       Val.convert(APFloat::IEEEdouble(), APFloat::rmTowardZero, &LosesInfo);
876       break;
877     default:
878       llvm_unreachable("Unhandled fp widen type");
879     }
880     Observer.changingInstr(MI);
881     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
882 
883     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
884     Observer.changedInstr(MI);
885     return Legalized;
886   }
887   case TargetOpcode::G_BRCOND:
888     Observer.changingInstr(MI);
889     widenScalarSrc(MI, WideTy, 0, TargetOpcode::G_ANYEXT);
890     Observer.changedInstr(MI);
891     return Legalized;
892 
893   case TargetOpcode::G_FCMP:
894     Observer.changingInstr(MI);
895     if (TypeIdx == 0)
896       widenScalarDst(MI, WideTy);
897     else {
898       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
899       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
900     }
901     Observer.changedInstr(MI);
902     return Legalized;
903 
904   case TargetOpcode::G_ICMP:
905     Observer.changingInstr(MI);
906     if (TypeIdx == 0)
907       widenScalarDst(MI, WideTy);
908     else {
909       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
910                                MI.getOperand(1).getPredicate()))
911                                ? TargetOpcode::G_SEXT
912                                : TargetOpcode::G_ZEXT;
913       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
914       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
915     }
916     Observer.changedInstr(MI);
917     return Legalized;
918 
919   case TargetOpcode::G_GEP:
920     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
921     Observer.changingInstr(MI);
922     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
923     Observer.changedInstr(MI);
924     return Legalized;
925 
926   case TargetOpcode::G_PHI: {
927     assert(TypeIdx == 0 && "Expecting only Idx 0");
928 
929     Observer.changingInstr(MI);
930     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
931       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
932       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
933       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
934     }
935 
936     MachineBasicBlock &MBB = *MI.getParent();
937     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
938     widenScalarDst(MI, WideTy);
939     Observer.changedInstr(MI);
940     return Legalized;
941   }
942   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
943     if (TypeIdx != 2)
944       return UnableToLegalize;
945     Observer.changingInstr(MI);
946     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
947     Observer.changedInstr(MI);
948     return Legalized;
949 
950   case TargetOpcode::G_FCEIL:
951     if (TypeIdx != 0)
952       return UnableToLegalize;
953     Observer.changingInstr(MI);
954     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT);
955     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
956     Observer.changedInstr(MI);
957     return Legalized;
958   }
959 }
960 
961 LegalizerHelper::LegalizeResult
962 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
963   using namespace TargetOpcode;
964   MIRBuilder.setInstr(MI);
965 
966   switch(MI.getOpcode()) {
967   default:
968     return UnableToLegalize;
969   case TargetOpcode::G_SREM:
970   case TargetOpcode::G_UREM: {
971     unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
972     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
973         .addDef(QuotReg)
974         .addUse(MI.getOperand(1).getReg())
975         .addUse(MI.getOperand(2).getReg());
976 
977     unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
978     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
979     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
980                         ProdReg);
981     MI.eraseFromParent();
982     return Legalized;
983   }
984   case TargetOpcode::G_SMULO:
985   case TargetOpcode::G_UMULO: {
986     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
987     // result.
988     unsigned Res = MI.getOperand(0).getReg();
989     unsigned Overflow = MI.getOperand(1).getReg();
990     unsigned LHS = MI.getOperand(2).getReg();
991     unsigned RHS = MI.getOperand(3).getReg();
992 
993     MIRBuilder.buildMul(Res, LHS, RHS);
994 
995     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
996                           ? TargetOpcode::G_SMULH
997                           : TargetOpcode::G_UMULH;
998 
999     unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
1000     MIRBuilder.buildInstr(Opcode)
1001       .addDef(HiPart)
1002       .addUse(LHS)
1003       .addUse(RHS);
1004 
1005     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
1006     MIRBuilder.buildConstant(Zero, 0);
1007 
1008     // For *signed* multiply, overflow is detected by checking:
1009     // (hi != (lo >> bitwidth-1))
1010     if (Opcode == TargetOpcode::G_SMULH) {
1011       unsigned Shifted = MRI.createGenericVirtualRegister(Ty);
1012       unsigned ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1013       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
1014       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
1015         .addDef(Shifted)
1016         .addUse(Res)
1017         .addUse(ShiftAmt);
1018       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
1019     } else {
1020       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
1021     }
1022     MI.eraseFromParent();
1023     return Legalized;
1024   }
1025   case TargetOpcode::G_FNEG: {
1026     // TODO: Handle vector types once we are able to
1027     // represent them.
1028     if (Ty.isVector())
1029       return UnableToLegalize;
1030     unsigned Res = MI.getOperand(0).getReg();
1031     Type *ZeroTy;
1032     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1033     switch (Ty.getSizeInBits()) {
1034     case 16:
1035       ZeroTy = Type::getHalfTy(Ctx);
1036       break;
1037     case 32:
1038       ZeroTy = Type::getFloatTy(Ctx);
1039       break;
1040     case 64:
1041       ZeroTy = Type::getDoubleTy(Ctx);
1042       break;
1043     case 128:
1044       ZeroTy = Type::getFP128Ty(Ctx);
1045       break;
1046     default:
1047       llvm_unreachable("unexpected floating-point type");
1048     }
1049     ConstantFP &ZeroForNegation =
1050         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
1051     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
1052     MIRBuilder.buildInstr(TargetOpcode::G_FSUB)
1053         .addDef(Res)
1054         .addUse(Zero->getOperand(0).getReg())
1055         .addUse(MI.getOperand(1).getReg());
1056     MI.eraseFromParent();
1057     return Legalized;
1058   }
1059   case TargetOpcode::G_FSUB: {
1060     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
1061     // First, check if G_FNEG is marked as Lower. If so, we may
1062     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
1063     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
1064       return UnableToLegalize;
1065     unsigned Res = MI.getOperand(0).getReg();
1066     unsigned LHS = MI.getOperand(1).getReg();
1067     unsigned RHS = MI.getOperand(2).getReg();
1068     unsigned Neg = MRI.createGenericVirtualRegister(Ty);
1069     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
1070     MIRBuilder.buildInstr(TargetOpcode::G_FADD)
1071         .addDef(Res)
1072         .addUse(LHS)
1073         .addUse(Neg);
1074     MI.eraseFromParent();
1075     return Legalized;
1076   }
1077   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
1078     unsigned OldValRes = MI.getOperand(0).getReg();
1079     unsigned SuccessRes = MI.getOperand(1).getReg();
1080     unsigned Addr = MI.getOperand(2).getReg();
1081     unsigned CmpVal = MI.getOperand(3).getReg();
1082     unsigned NewVal = MI.getOperand(4).getReg();
1083     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
1084                                   **MI.memoperands_begin());
1085     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
1086     MI.eraseFromParent();
1087     return Legalized;
1088   }
1089   case TargetOpcode::G_LOAD:
1090   case TargetOpcode::G_SEXTLOAD:
1091   case TargetOpcode::G_ZEXTLOAD: {
1092     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
1093     unsigned DstReg = MI.getOperand(0).getReg();
1094     unsigned PtrReg = MI.getOperand(1).getReg();
1095     LLT DstTy = MRI.getType(DstReg);
1096     auto &MMO = **MI.memoperands_begin();
1097 
1098     if (DstTy.getSizeInBits() == MMO.getSize() /* in bytes */ * 8) {
1099       // In the case of G_LOAD, this was a non-extending load already and we're
1100       // about to lower to the same instruction.
1101       if (MI.getOpcode() == TargetOpcode::G_LOAD)
1102           return UnableToLegalize;
1103       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
1104       MI.eraseFromParent();
1105       return Legalized;
1106     }
1107 
1108     if (DstTy.isScalar()) {
1109       unsigned TmpReg = MRI.createGenericVirtualRegister(
1110           LLT::scalar(MMO.getSize() /* in bytes */ * 8));
1111       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
1112       switch (MI.getOpcode()) {
1113       default:
1114         llvm_unreachable("Unexpected opcode");
1115       case TargetOpcode::G_LOAD:
1116         MIRBuilder.buildAnyExt(DstReg, TmpReg);
1117         break;
1118       case TargetOpcode::G_SEXTLOAD:
1119         MIRBuilder.buildSExt(DstReg, TmpReg);
1120         break;
1121       case TargetOpcode::G_ZEXTLOAD:
1122         MIRBuilder.buildZExt(DstReg, TmpReg);
1123         break;
1124       }
1125       MI.eraseFromParent();
1126       return Legalized;
1127     }
1128 
1129     return UnableToLegalize;
1130   }
1131   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1132   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1133   case TargetOpcode::G_CTLZ:
1134   case TargetOpcode::G_CTTZ:
1135   case TargetOpcode::G_CTPOP:
1136     return lowerBitCount(MI, TypeIdx, Ty);
1137   case G_UADDE: {
1138     unsigned Res = MI.getOperand(0).getReg();
1139     unsigned CarryOut = MI.getOperand(1).getReg();
1140     unsigned LHS = MI.getOperand(2).getReg();
1141     unsigned RHS = MI.getOperand(3).getReg();
1142     unsigned CarryIn = MI.getOperand(4).getReg();
1143 
1144     unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
1145     unsigned ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
1146 
1147     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
1148     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
1149     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
1150     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
1151 
1152     MI.eraseFromParent();
1153     return Legalized;
1154   }
1155   }
1156 }
1157 
1158 LegalizerHelper::LegalizeResult
1159 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
1160                                      LLT NarrowTy) {
1161   // FIXME: Don't know how to handle secondary types yet.
1162   if (TypeIdx != 0)
1163     return UnableToLegalize;
1164 
1165   MIRBuilder.setInstr(MI);
1166   switch (MI.getOpcode()) {
1167   default:
1168     return UnableToLegalize;
1169   case TargetOpcode::G_ADD: {
1170     unsigned NarrowSize = NarrowTy.getSizeInBits();
1171     unsigned DstReg = MI.getOperand(0).getReg();
1172     unsigned Size = MRI.getType(DstReg).getSizeInBits();
1173     int NumParts = Size / NarrowSize;
1174     // FIXME: Don't know how to handle the situation where the small vectors
1175     // aren't all the same size yet.
1176     if (Size % NarrowSize != 0)
1177       return UnableToLegalize;
1178 
1179     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
1180     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
1181     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
1182 
1183     for (int i = 0; i < NumParts; ++i) {
1184       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
1185       MIRBuilder.buildAdd(DstReg, Src1Regs[i], Src2Regs[i]);
1186       DstRegs.push_back(DstReg);
1187     }
1188 
1189     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1190     MI.eraseFromParent();
1191     return Legalized;
1192   }
1193   case TargetOpcode::G_LOAD:
1194   case TargetOpcode::G_STORE: {
1195     bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
1196     unsigned ValReg = MI.getOperand(0).getReg();
1197     unsigned AddrReg = MI.getOperand(1).getReg();
1198     unsigned NarrowSize = NarrowTy.getSizeInBits();
1199     unsigned Size = MRI.getType(ValReg).getSizeInBits();
1200     unsigned NumParts = Size / NarrowSize;
1201 
1202     SmallVector<unsigned, 8> NarrowRegs;
1203     if (!IsLoad)
1204       extractParts(ValReg, NarrowTy, NumParts, NarrowRegs);
1205 
1206     const LLT OffsetTy =
1207         LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
1208     MachineFunction &MF = *MI.getMF();
1209     MachineMemOperand *MMO = *MI.memoperands_begin();
1210     for (unsigned Idx = 0; Idx < NumParts; ++Idx) {
1211       unsigned Adjustment = Idx * NarrowTy.getSizeInBits() / 8;
1212       unsigned Alignment = MinAlign(MMO->getAlignment(), Adjustment);
1213       unsigned NewAddrReg = 0;
1214       MIRBuilder.materializeGEP(NewAddrReg, AddrReg, OffsetTy, Adjustment);
1215       MachineMemOperand &NewMMO = *MF.getMachineMemOperand(
1216           MMO->getPointerInfo().getWithOffset(Adjustment), MMO->getFlags(),
1217           NarrowTy.getSizeInBits() / 8, Alignment);
1218       if (IsLoad) {
1219         unsigned Dst = MRI.createGenericVirtualRegister(NarrowTy);
1220         NarrowRegs.push_back(Dst);
1221         MIRBuilder.buildLoad(Dst, NewAddrReg, NewMMO);
1222       } else {
1223         MIRBuilder.buildStore(NarrowRegs[Idx], NewAddrReg, NewMMO);
1224       }
1225     }
1226     if (IsLoad) {
1227       if (NarrowTy.isVector())
1228         MIRBuilder.buildConcatVectors(ValReg, NarrowRegs);
1229       else
1230         MIRBuilder.buildBuildVector(ValReg, NarrowRegs);
1231     }
1232     MI.eraseFromParent();
1233     return Legalized;
1234   }
1235   }
1236 }
1237 
1238 LegalizerHelper::LegalizeResult
1239 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1240   unsigned Opc = MI.getOpcode();
1241   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
1242   auto isSupported = [this](const LegalityQuery &Q) {
1243     auto QAction = LI.getAction(Q).Action;
1244     return QAction == Legal || QAction == Libcall || QAction == Custom;
1245   };
1246   switch (Opc) {
1247   default:
1248     return UnableToLegalize;
1249   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
1250     // This trivially expands to CTLZ.
1251     Observer.changingInstr(MI);
1252     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
1253     Observer.changedInstr(MI);
1254     return Legalized;
1255   }
1256   case TargetOpcode::G_CTLZ: {
1257     unsigned SrcReg = MI.getOperand(1).getReg();
1258     unsigned Len = Ty.getSizeInBits();
1259     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty}})) {
1260       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
1261       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
1262                                              {Ty}, {SrcReg});
1263       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
1264       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
1265       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
1266                                           SrcReg, MIBZero);
1267       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
1268                              MIBCtlzZU);
1269       MI.eraseFromParent();
1270       return Legalized;
1271     }
1272     // for now, we do this:
1273     // NewLen = NextPowerOf2(Len);
1274     // x = x | (x >> 1);
1275     // x = x | (x >> 2);
1276     // ...
1277     // x = x | (x >>16);
1278     // x = x | (x >>32); // for 64-bit input
1279     // Upto NewLen/2
1280     // return Len - popcount(x);
1281     //
1282     // Ref: "Hacker's Delight" by Henry Warren
1283     unsigned Op = SrcReg;
1284     unsigned NewLen = PowerOf2Ceil(Len);
1285     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
1286       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
1287       auto MIBOp = MIRBuilder.buildInstr(
1288           TargetOpcode::G_OR, {Ty},
1289           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
1290                                      {Op, MIBShiftAmt})});
1291       Op = MIBOp->getOperand(0).getReg();
1292     }
1293     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
1294     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
1295                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
1296     MI.eraseFromParent();
1297     return Legalized;
1298   }
1299   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
1300     // This trivially expands to CTTZ.
1301     Observer.changingInstr(MI);
1302     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
1303     Observer.changedInstr(MI);
1304     return Legalized;
1305   }
1306   case TargetOpcode::G_CTTZ: {
1307     unsigned SrcReg = MI.getOperand(1).getReg();
1308     unsigned Len = Ty.getSizeInBits();
1309     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty}})) {
1310       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
1311       // zero.
1312       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
1313                                              {Ty}, {SrcReg});
1314       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
1315       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
1316       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
1317                                           SrcReg, MIBZero);
1318       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
1319                              MIBCttzZU);
1320       MI.eraseFromParent();
1321       return Legalized;
1322     }
1323     // for now, we use: { return popcount(~x & (x - 1)); }
1324     // unless the target has ctlz but not ctpop, in which case we use:
1325     // { return 32 - nlz(~x & (x-1)); }
1326     // Ref: "Hacker's Delight" by Henry Warren
1327     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
1328     auto MIBNot =
1329         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
1330     auto MIBTmp = MIRBuilder.buildInstr(
1331         TargetOpcode::G_AND, {Ty},
1332         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
1333                                        {SrcReg, MIBCstNeg1})});
1334     if (!isSupported({TargetOpcode::G_CTPOP, {Ty}}) &&
1335         isSupported({TargetOpcode::G_CTLZ, {Ty}})) {
1336       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
1337       MIRBuilder.buildInstr(
1338           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
1339           {MIBCstLen,
1340            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
1341       MI.eraseFromParent();
1342       return Legalized;
1343     }
1344     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
1345     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
1346     return Legalized;
1347   }
1348   }
1349 }
1350