1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #include "llvm/CodeGen/TargetLowering.h"
22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/raw_ostream.h"
26 
27 #define DEBUG_TYPE "legalizer"
28 
29 using namespace llvm;
30 using namespace LegalizeActions;
31 
32 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
33 ///
34 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
35 /// with any leftover piece as type \p LeftoverTy
36 ///
37 /// Returns -1 in the first element of the pair if the breakdown is not
38 /// satisfiable.
39 static std::pair<int, int>
40 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
41   assert(!LeftoverTy.isValid() && "this is an out argument");
42 
43   unsigned Size = OrigTy.getSizeInBits();
44   unsigned NarrowSize = NarrowTy.getSizeInBits();
45   unsigned NumParts = Size / NarrowSize;
46   unsigned LeftoverSize = Size - NumParts * NarrowSize;
47   assert(Size > NarrowSize);
48 
49   if (LeftoverSize == 0)
50     return {NumParts, 0};
51 
52   if (NarrowTy.isVector()) {
53     unsigned EltSize = OrigTy.getScalarSizeInBits();
54     if (LeftoverSize % EltSize != 0)
55       return {-1, -1};
56     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
57   } else {
58     LeftoverTy = LLT::scalar(LeftoverSize);
59   }
60 
61   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
62   return std::make_pair(NumParts, NumLeftover);
63 }
64 
65 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
66                                  GISelChangeObserver &Observer,
67                                  MachineIRBuilder &Builder)
68     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
69       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
70   MIRBuilder.setMF(MF);
71   MIRBuilder.setChangeObserver(Observer);
72 }
73 
74 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
75                                  GISelChangeObserver &Observer,
76                                  MachineIRBuilder &B)
77     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
78   MIRBuilder.setMF(MF);
79   MIRBuilder.setChangeObserver(Observer);
80 }
81 LegalizerHelper::LegalizeResult
82 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
83   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
84 
85   auto Step = LI.getAction(MI, MRI);
86   switch (Step.Action) {
87   case Legal:
88     LLVM_DEBUG(dbgs() << ".. Already legal\n");
89     return AlreadyLegal;
90   case Libcall:
91     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
92     return libcall(MI);
93   case NarrowScalar:
94     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
95     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
96   case WidenScalar:
97     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
98     return widenScalar(MI, Step.TypeIdx, Step.NewType);
99   case Lower:
100     LLVM_DEBUG(dbgs() << ".. Lower\n");
101     return lower(MI, Step.TypeIdx, Step.NewType);
102   case FewerElements:
103     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
104     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
105   case MoreElements:
106     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
107     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
108   case Custom:
109     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
110     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
111                                                             : UnableToLegalize;
112   default:
113     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
114     return UnableToLegalize;
115   }
116 }
117 
118 void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
119                                    SmallVectorImpl<unsigned> &VRegs) {
120   for (int i = 0; i < NumParts; ++i)
121     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
122   MIRBuilder.buildUnmerge(VRegs, Reg);
123 }
124 
125 bool LegalizerHelper::extractParts(unsigned Reg, LLT RegTy,
126                                    LLT MainTy, LLT &LeftoverTy,
127                                    SmallVectorImpl<unsigned> &VRegs,
128                                    SmallVectorImpl<unsigned> &LeftoverRegs) {
129   assert(!LeftoverTy.isValid() && "this is an out argument");
130 
131   unsigned RegSize = RegTy.getSizeInBits();
132   unsigned MainSize = MainTy.getSizeInBits();
133   unsigned NumParts = RegSize / MainSize;
134   unsigned LeftoverSize = RegSize - NumParts * MainSize;
135 
136   // Use an unmerge when possible.
137   if (LeftoverSize == 0) {
138     for (unsigned I = 0; I < NumParts; ++I)
139       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
140     MIRBuilder.buildUnmerge(VRegs, Reg);
141     return true;
142   }
143 
144   if (MainTy.isVector()) {
145     unsigned EltSize = MainTy.getScalarSizeInBits();
146     if (LeftoverSize % EltSize != 0)
147       return false;
148     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
149   } else {
150     LeftoverTy = LLT::scalar(LeftoverSize);
151   }
152 
153   // For irregular sizes, extract the individual parts.
154   for (unsigned I = 0; I != NumParts; ++I) {
155     unsigned NewReg = MRI.createGenericVirtualRegister(MainTy);
156     VRegs.push_back(NewReg);
157     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
158   }
159 
160   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
161        Offset += LeftoverSize) {
162     unsigned NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
163     LeftoverRegs.push_back(NewReg);
164     MIRBuilder.buildExtract(NewReg, Reg, Offset);
165   }
166 
167   return true;
168 }
169 
170 void LegalizerHelper::insertParts(unsigned DstReg,
171                                   LLT ResultTy, LLT PartTy,
172                                   ArrayRef<unsigned> PartRegs,
173                                   LLT LeftoverTy,
174                                   ArrayRef<unsigned> LeftoverRegs) {
175   if (!LeftoverTy.isValid()) {
176     assert(LeftoverRegs.empty());
177 
178     if (!ResultTy.isVector()) {
179       MIRBuilder.buildMerge(DstReg, PartRegs);
180       return;
181     }
182 
183     if (PartTy.isVector())
184       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
185     else
186       MIRBuilder.buildBuildVector(DstReg, PartRegs);
187     return;
188   }
189 
190   unsigned PartSize = PartTy.getSizeInBits();
191   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
192 
193   unsigned CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
194   MIRBuilder.buildUndef(CurResultReg);
195 
196   unsigned Offset = 0;
197   for (unsigned PartReg : PartRegs) {
198     unsigned NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
199     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
200     CurResultReg = NewResultReg;
201     Offset += PartSize;
202   }
203 
204   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
205     // Use the original output register for the final insert to avoid a copy.
206     unsigned NewResultReg = (I + 1 == E) ?
207       DstReg : MRI.createGenericVirtualRegister(ResultTy);
208 
209     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
210     CurResultReg = NewResultReg;
211     Offset += LeftoverPartSize;
212   }
213 }
214 
215 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
216   switch (Opcode) {
217   case TargetOpcode::G_SDIV:
218     assert((Size == 32 || Size == 64) && "Unsupported size");
219     return Size == 64 ? RTLIB::SDIV_I64 : RTLIB::SDIV_I32;
220   case TargetOpcode::G_UDIV:
221     assert((Size == 32 || Size == 64) && "Unsupported size");
222     return Size == 64 ? RTLIB::UDIV_I64 : RTLIB::UDIV_I32;
223   case TargetOpcode::G_SREM:
224     assert((Size == 32 || Size == 64) && "Unsupported size");
225     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
226   case TargetOpcode::G_UREM:
227     assert((Size == 32 || Size == 64) && "Unsupported size");
228     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
229   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
230     assert(Size == 32 && "Unsupported size");
231     return RTLIB::CTLZ_I32;
232   case TargetOpcode::G_FADD:
233     assert((Size == 32 || Size == 64) && "Unsupported size");
234     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
235   case TargetOpcode::G_FSUB:
236     assert((Size == 32 || Size == 64) && "Unsupported size");
237     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
238   case TargetOpcode::G_FMUL:
239     assert((Size == 32 || Size == 64) && "Unsupported size");
240     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
241   case TargetOpcode::G_FDIV:
242     assert((Size == 32 || Size == 64) && "Unsupported size");
243     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
244   case TargetOpcode::G_FEXP:
245     assert((Size == 32 || Size == 64) && "Unsupported size");
246     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
247   case TargetOpcode::G_FEXP2:
248     assert((Size == 32 || Size == 64) && "Unsupported size");
249     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
250   case TargetOpcode::G_FREM:
251     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
252   case TargetOpcode::G_FPOW:
253     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
254   case TargetOpcode::G_FMA:
255     assert((Size == 32 || Size == 64) && "Unsupported size");
256     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
257   case TargetOpcode::G_FSIN:
258     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
259     return Size == 128 ? RTLIB::SIN_F128
260                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
261   case TargetOpcode::G_FCOS:
262     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
263     return Size == 128 ? RTLIB::COS_F128
264                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
265   case TargetOpcode::G_FLOG10:
266     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
267     return Size == 128 ? RTLIB::LOG10_F128
268                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
269   case TargetOpcode::G_FLOG:
270     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
271     return Size == 128 ? RTLIB::LOG_F128
272                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
273   case TargetOpcode::G_FLOG2:
274     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
275     return Size == 128 ? RTLIB::LOG2_F128
276                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
277   }
278   llvm_unreachable("Unknown libcall function");
279 }
280 
281 LegalizerHelper::LegalizeResult
282 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
283                     const CallLowering::ArgInfo &Result,
284                     ArrayRef<CallLowering::ArgInfo> Args) {
285   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
286   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
287   const char *Name = TLI.getLibcallName(Libcall);
288 
289   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
290   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
291                      MachineOperand::CreateES(Name), Result, Args))
292     return LegalizerHelper::UnableToLegalize;
293 
294   return LegalizerHelper::Legalized;
295 }
296 
297 // Useful for libcalls where all operands have the same type.
298 static LegalizerHelper::LegalizeResult
299 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
300               Type *OpType) {
301   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
302 
303   SmallVector<CallLowering::ArgInfo, 3> Args;
304   for (unsigned i = 1; i < MI.getNumOperands(); i++)
305     Args.push_back({MI.getOperand(i).getReg(), OpType});
306   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
307                        Args);
308 }
309 
310 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
311                                        Type *FromType) {
312   auto ToMVT = MVT::getVT(ToType);
313   auto FromMVT = MVT::getVT(FromType);
314 
315   switch (Opcode) {
316   case TargetOpcode::G_FPEXT:
317     return RTLIB::getFPEXT(FromMVT, ToMVT);
318   case TargetOpcode::G_FPTRUNC:
319     return RTLIB::getFPROUND(FromMVT, ToMVT);
320   case TargetOpcode::G_FPTOSI:
321     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
322   case TargetOpcode::G_FPTOUI:
323     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
324   case TargetOpcode::G_SITOFP:
325     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
326   case TargetOpcode::G_UITOFP:
327     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
328   }
329   llvm_unreachable("Unsupported libcall function");
330 }
331 
332 static LegalizerHelper::LegalizeResult
333 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
334                   Type *FromType) {
335   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
336   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
337                        {{MI.getOperand(1).getReg(), FromType}});
338 }
339 
340 LegalizerHelper::LegalizeResult
341 LegalizerHelper::libcall(MachineInstr &MI) {
342   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
343   unsigned Size = LLTy.getSizeInBits();
344   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
345 
346   MIRBuilder.setInstr(MI);
347 
348   switch (MI.getOpcode()) {
349   default:
350     return UnableToLegalize;
351   case TargetOpcode::G_SDIV:
352   case TargetOpcode::G_UDIV:
353   case TargetOpcode::G_SREM:
354   case TargetOpcode::G_UREM:
355   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
356     Type *HLTy = IntegerType::get(Ctx, Size);
357     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
358     if (Status != Legalized)
359       return Status;
360     break;
361   }
362   case TargetOpcode::G_FADD:
363   case TargetOpcode::G_FSUB:
364   case TargetOpcode::G_FMUL:
365   case TargetOpcode::G_FDIV:
366   case TargetOpcode::G_FMA:
367   case TargetOpcode::G_FPOW:
368   case TargetOpcode::G_FREM:
369   case TargetOpcode::G_FCOS:
370   case TargetOpcode::G_FSIN:
371   case TargetOpcode::G_FLOG10:
372   case TargetOpcode::G_FLOG:
373   case TargetOpcode::G_FLOG2:
374   case TargetOpcode::G_FEXP:
375   case TargetOpcode::G_FEXP2: {
376     if (Size > 64) {
377       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
378       return UnableToLegalize;
379     }
380     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
381     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
382     if (Status != Legalized)
383       return Status;
384     break;
385   }
386   case TargetOpcode::G_FPEXT: {
387     // FIXME: Support other floating point types (half, fp128 etc)
388     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
389     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
390     if (ToSize != 64 || FromSize != 32)
391       return UnableToLegalize;
392     LegalizeResult Status = conversionLibcall(
393         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
394     if (Status != Legalized)
395       return Status;
396     break;
397   }
398   case TargetOpcode::G_FPTRUNC: {
399     // FIXME: Support other floating point types (half, fp128 etc)
400     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
401     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
402     if (ToSize != 32 || FromSize != 64)
403       return UnableToLegalize;
404     LegalizeResult Status = conversionLibcall(
405         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
406     if (Status != Legalized)
407       return Status;
408     break;
409   }
410   case TargetOpcode::G_FPTOSI:
411   case TargetOpcode::G_FPTOUI: {
412     // FIXME: Support other types
413     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
414     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
415     if (ToSize != 32 || (FromSize != 32 && FromSize != 64))
416       return UnableToLegalize;
417     LegalizeResult Status = conversionLibcall(
418         MI, MIRBuilder, Type::getInt32Ty(Ctx),
419         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
420     if (Status != Legalized)
421       return Status;
422     break;
423   }
424   case TargetOpcode::G_SITOFP:
425   case TargetOpcode::G_UITOFP: {
426     // FIXME: Support other types
427     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
428     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
429     if (FromSize != 32 || (ToSize != 32 && ToSize != 64))
430       return UnableToLegalize;
431     LegalizeResult Status = conversionLibcall(
432         MI, MIRBuilder,
433         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
434         Type::getInt32Ty(Ctx));
435     if (Status != Legalized)
436       return Status;
437     break;
438   }
439   }
440 
441   MI.eraseFromParent();
442   return Legalized;
443 }
444 
445 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
446                                                               unsigned TypeIdx,
447                                                               LLT NarrowTy) {
448   MIRBuilder.setInstr(MI);
449 
450   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
451   uint64_t NarrowSize = NarrowTy.getSizeInBits();
452 
453   switch (MI.getOpcode()) {
454   default:
455     return UnableToLegalize;
456   case TargetOpcode::G_IMPLICIT_DEF: {
457     // FIXME: add support for when SizeOp0 isn't an exact multiple of
458     // NarrowSize.
459     if (SizeOp0 % NarrowSize != 0)
460       return UnableToLegalize;
461     int NumParts = SizeOp0 / NarrowSize;
462 
463     SmallVector<unsigned, 2> DstRegs;
464     for (int i = 0; i < NumParts; ++i)
465       DstRegs.push_back(
466           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
467 
468     unsigned DstReg = MI.getOperand(0).getReg();
469     if(MRI.getType(DstReg).isVector())
470       MIRBuilder.buildBuildVector(DstReg, DstRegs);
471     else
472       MIRBuilder.buildMerge(DstReg, DstRegs);
473     MI.eraseFromParent();
474     return Legalized;
475   }
476   case TargetOpcode::G_CONSTANT: {
477     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
478     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
479     unsigned TotalSize = Ty.getSizeInBits();
480     unsigned NarrowSize = NarrowTy.getSizeInBits();
481     int NumParts = TotalSize / NarrowSize;
482 
483     SmallVector<unsigned, 4> PartRegs;
484     for (int I = 0; I != NumParts; ++I) {
485       unsigned Offset = I * NarrowSize;
486       auto K = MIRBuilder.buildConstant(NarrowTy,
487                                         Val.lshr(Offset).trunc(NarrowSize));
488       PartRegs.push_back(K.getReg(0));
489     }
490 
491     LLT LeftoverTy;
492     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
493     SmallVector<unsigned, 1> LeftoverRegs;
494     if (LeftoverBits != 0) {
495       LeftoverTy = LLT::scalar(LeftoverBits);
496       auto K = MIRBuilder.buildConstant(
497         LeftoverTy,
498         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
499       LeftoverRegs.push_back(K.getReg(0));
500     }
501 
502     insertParts(MI.getOperand(0).getReg(),
503                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
504 
505     MI.eraseFromParent();
506     return Legalized;
507   }
508   case TargetOpcode::G_ADD: {
509     // FIXME: add support for when SizeOp0 isn't an exact multiple of
510     // NarrowSize.
511     if (SizeOp0 % NarrowSize != 0)
512       return UnableToLegalize;
513     // Expand in terms of carry-setting/consuming G_ADDE instructions.
514     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
515 
516     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
517     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
518     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
519 
520     unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
521     MIRBuilder.buildConstant(CarryIn, 0);
522 
523     for (int i = 0; i < NumParts; ++i) {
524       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
525       unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
526 
527       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
528                             Src2Regs[i], CarryIn);
529 
530       DstRegs.push_back(DstReg);
531       CarryIn = CarryOut;
532     }
533     unsigned DstReg = MI.getOperand(0).getReg();
534     if(MRI.getType(DstReg).isVector())
535       MIRBuilder.buildBuildVector(DstReg, DstRegs);
536     else
537       MIRBuilder.buildMerge(DstReg, DstRegs);
538     MI.eraseFromParent();
539     return Legalized;
540   }
541   case TargetOpcode::G_SUB: {
542     // FIXME: add support for when SizeOp0 isn't an exact multiple of
543     // NarrowSize.
544     if (SizeOp0 % NarrowSize != 0)
545       return UnableToLegalize;
546 
547     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
548 
549     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
550     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
551     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
552 
553     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
554     unsigned BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
555     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
556                           {Src1Regs[0], Src2Regs[0]});
557     DstRegs.push_back(DstReg);
558     unsigned BorrowIn = BorrowOut;
559     for (int i = 1; i < NumParts; ++i) {
560       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
561       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
562 
563       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
564                             {Src1Regs[i], Src2Regs[i], BorrowIn});
565 
566       DstRegs.push_back(DstReg);
567       BorrowIn = BorrowOut;
568     }
569     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
570     MI.eraseFromParent();
571     return Legalized;
572   }
573   case TargetOpcode::G_MUL:
574   case TargetOpcode::G_UMULH:
575     return narrowScalarMul(MI, NarrowTy);
576   case TargetOpcode::G_EXTRACT:
577     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
578   case TargetOpcode::G_INSERT:
579     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
580   case TargetOpcode::G_LOAD: {
581     const auto &MMO = **MI.memoperands_begin();
582     unsigned DstReg = MI.getOperand(0).getReg();
583     LLT DstTy = MRI.getType(DstReg);
584     if (DstTy.isVector())
585       return UnableToLegalize;
586 
587     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
588       unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
589       auto &MMO = **MI.memoperands_begin();
590       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
591       MIRBuilder.buildAnyExt(DstReg, TmpReg);
592       MI.eraseFromParent();
593       return Legalized;
594     }
595 
596     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
597   }
598   case TargetOpcode::G_ZEXTLOAD:
599   case TargetOpcode::G_SEXTLOAD: {
600     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
601     unsigned DstReg = MI.getOperand(0).getReg();
602     unsigned PtrReg = MI.getOperand(1).getReg();
603 
604     unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
605     auto &MMO = **MI.memoperands_begin();
606     if (MMO.getSize() * 8 == NarrowSize) {
607       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
608     } else {
609       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
610         : TargetOpcode::G_SEXTLOAD;
611       MIRBuilder.buildInstr(ExtLoad)
612         .addDef(TmpReg)
613         .addUse(PtrReg)
614         .addMemOperand(&MMO);
615     }
616 
617     if (ZExt)
618       MIRBuilder.buildZExt(DstReg, TmpReg);
619     else
620       MIRBuilder.buildSExt(DstReg, TmpReg);
621 
622     MI.eraseFromParent();
623     return Legalized;
624   }
625   case TargetOpcode::G_STORE: {
626     const auto &MMO = **MI.memoperands_begin();
627 
628     unsigned SrcReg = MI.getOperand(0).getReg();
629     LLT SrcTy = MRI.getType(SrcReg);
630     if (SrcTy.isVector())
631       return UnableToLegalize;
632 
633     int NumParts = SizeOp0 / NarrowSize;
634     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
635     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
636     if (SrcTy.isVector() && LeftoverBits != 0)
637       return UnableToLegalize;
638 
639     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
640       unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
641       auto &MMO = **MI.memoperands_begin();
642       MIRBuilder.buildTrunc(TmpReg, SrcReg);
643       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
644       MI.eraseFromParent();
645       return Legalized;
646     }
647 
648     return reduceLoadStoreWidth(MI, 0, NarrowTy);
649   }
650   case TargetOpcode::G_SELECT:
651     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
652   case TargetOpcode::G_AND:
653   case TargetOpcode::G_OR:
654   case TargetOpcode::G_XOR: {
655     // Legalize bitwise operation:
656     // A = BinOp<Ty> B, C
657     // into:
658     // B1, ..., BN = G_UNMERGE_VALUES B
659     // C1, ..., CN = G_UNMERGE_VALUES C
660     // A1 = BinOp<Ty/N> B1, C2
661     // ...
662     // AN = BinOp<Ty/N> BN, CN
663     // A = G_MERGE_VALUES A1, ..., AN
664     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
665   }
666   case TargetOpcode::G_SHL:
667   case TargetOpcode::G_LSHR:
668   case TargetOpcode::G_ASHR:
669     return narrowScalarShift(MI, TypeIdx, NarrowTy);
670   case TargetOpcode::G_CTLZ:
671   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
672   case TargetOpcode::G_CTTZ:
673   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
674   case TargetOpcode::G_CTPOP:
675     if (TypeIdx != 0)
676       return UnableToLegalize; // TODO
677 
678     Observer.changingInstr(MI);
679     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
680     Observer.changedInstr(MI);
681     return Legalized;
682   case TargetOpcode::G_INTTOPTR:
683     if (TypeIdx != 1)
684       return UnableToLegalize;
685 
686     Observer.changingInstr(MI);
687     narrowScalarSrc(MI, NarrowTy, 1);
688     Observer.changedInstr(MI);
689     return Legalized;
690   case TargetOpcode::G_PTRTOINT:
691     if (TypeIdx != 0)
692       return UnableToLegalize;
693 
694     Observer.changingInstr(MI);
695     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
696     Observer.changedInstr(MI);
697     return Legalized;
698   }
699 }
700 
701 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
702                                      unsigned OpIdx, unsigned ExtOpcode) {
703   MachineOperand &MO = MI.getOperand(OpIdx);
704   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
705   MO.setReg(ExtB->getOperand(0).getReg());
706 }
707 
708 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
709                                       unsigned OpIdx) {
710   MachineOperand &MO = MI.getOperand(OpIdx);
711   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
712                                     {MO.getReg()});
713   MO.setReg(ExtB->getOperand(0).getReg());
714 }
715 
716 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
717                                      unsigned OpIdx, unsigned TruncOpcode) {
718   MachineOperand &MO = MI.getOperand(OpIdx);
719   unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
720   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
721   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
722   MO.setReg(DstExt);
723 }
724 
725 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
726                                       unsigned OpIdx, unsigned ExtOpcode) {
727   MachineOperand &MO = MI.getOperand(OpIdx);
728   unsigned DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
729   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
730   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
731   MO.setReg(DstTrunc);
732 }
733 
734 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
735                                             unsigned OpIdx) {
736   MachineOperand &MO = MI.getOperand(OpIdx);
737   unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
738   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
739   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
740   MO.setReg(DstExt);
741 }
742 
743 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
744                                             unsigned OpIdx) {
745   MachineOperand &MO = MI.getOperand(OpIdx);
746 
747   LLT OldTy = MRI.getType(MO.getReg());
748   unsigned OldElts = OldTy.getNumElements();
749   unsigned NewElts = MoreTy.getNumElements();
750 
751   unsigned NumParts = NewElts / OldElts;
752 
753   // Use concat_vectors if the result is a multiple of the number of elements.
754   if (NumParts * OldElts == NewElts) {
755     SmallVector<unsigned, 8> Parts;
756     Parts.push_back(MO.getReg());
757 
758     unsigned ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
759     for (unsigned I = 1; I != NumParts; ++I)
760       Parts.push_back(ImpDef);
761 
762     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
763     MO.setReg(Concat.getReg(0));
764     return;
765   }
766 
767   unsigned MoreReg = MRI.createGenericVirtualRegister(MoreTy);
768   unsigned ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
769   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
770   MO.setReg(MoreReg);
771 }
772 
773 LegalizerHelper::LegalizeResult
774 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
775                                         LLT WideTy) {
776   if (TypeIdx != 1)
777     return UnableToLegalize;
778 
779   unsigned DstReg = MI.getOperand(0).getReg();
780   LLT DstTy = MRI.getType(DstReg);
781   if (!DstTy.isScalar())
782     return UnableToLegalize;
783 
784   unsigned NumOps = MI.getNumOperands();
785   unsigned NumSrc = MI.getNumOperands() - 1;
786   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
787 
788   unsigned Src1 = MI.getOperand(1).getReg();
789   unsigned ResultReg = MIRBuilder.buildZExt(DstTy, Src1)->getOperand(0).getReg();
790 
791   for (unsigned I = 2; I != NumOps; ++I) {
792     const unsigned Offset = (I - 1) * PartSize;
793 
794     unsigned SrcReg = MI.getOperand(I).getReg();
795     assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
796 
797     auto ZextInput = MIRBuilder.buildZExt(DstTy, SrcReg);
798 
799     unsigned NextResult = I + 1 == NumOps ? DstReg :
800       MRI.createGenericVirtualRegister(DstTy);
801 
802     auto ShiftAmt = MIRBuilder.buildConstant(DstTy, Offset);
803     auto Shl = MIRBuilder.buildShl(DstTy, ZextInput, ShiftAmt);
804     MIRBuilder.buildOr(NextResult, ResultReg, Shl);
805     ResultReg = NextResult;
806   }
807 
808   MI.eraseFromParent();
809   return Legalized;
810 }
811 
812 LegalizerHelper::LegalizeResult
813 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
814                                           LLT WideTy) {
815   if (TypeIdx != 0)
816     return UnableToLegalize;
817 
818   unsigned NumDst = MI.getNumOperands() - 1;
819   unsigned SrcReg = MI.getOperand(NumDst).getReg();
820   LLT SrcTy = MRI.getType(SrcReg);
821   if (!SrcTy.isScalar())
822     return UnableToLegalize;
823 
824   unsigned Dst0Reg = MI.getOperand(0).getReg();
825   LLT DstTy = MRI.getType(Dst0Reg);
826   if (!DstTy.isScalar())
827     return UnableToLegalize;
828 
829   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
830   LLT NewSrcTy = LLT::scalar(NewSrcSize);
831   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
832 
833   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
834 
835   for (unsigned I = 1; I != NumDst; ++I) {
836     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
837     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
838     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
839   }
840 
841   Observer.changingInstr(MI);
842 
843   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
844   for (unsigned I = 0; I != NumDst; ++I)
845     widenScalarDst(MI, WideTy, I);
846 
847   Observer.changedInstr(MI);
848 
849   return Legalized;
850 }
851 
852 LegalizerHelper::LegalizeResult
853 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
854                                     LLT WideTy) {
855   unsigned DstReg = MI.getOperand(0).getReg();
856   unsigned SrcReg = MI.getOperand(1).getReg();
857   LLT SrcTy = MRI.getType(SrcReg);
858 
859   LLT DstTy = MRI.getType(DstReg);
860   unsigned Offset = MI.getOperand(2).getImm();
861 
862   if (TypeIdx == 0) {
863     if (SrcTy.isVector() || DstTy.isVector())
864       return UnableToLegalize;
865 
866     SrcOp Src(SrcReg);
867     if (SrcTy.isPointer()) {
868       // Extracts from pointers can be handled only if they are really just
869       // simple integers.
870       const DataLayout &DL = MIRBuilder.getDataLayout();
871       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
872         return UnableToLegalize;
873 
874       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
875       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
876       SrcTy = SrcAsIntTy;
877     }
878 
879     if (DstTy.isPointer())
880       return UnableToLegalize;
881 
882     if (Offset == 0) {
883       // Avoid a shift in the degenerate case.
884       MIRBuilder.buildTrunc(DstReg,
885                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
886       MI.eraseFromParent();
887       return Legalized;
888     }
889 
890     // Do a shift in the source type.
891     LLT ShiftTy = SrcTy;
892     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
893       Src = MIRBuilder.buildAnyExt(WideTy, Src);
894       ShiftTy = WideTy;
895     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
896       return UnableToLegalize;
897 
898     auto LShr = MIRBuilder.buildLShr(
899       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
900     MIRBuilder.buildTrunc(DstReg, LShr);
901     MI.eraseFromParent();
902     return Legalized;
903   }
904 
905   if (!SrcTy.isVector())
906     return UnableToLegalize;
907 
908   if (DstTy != SrcTy.getElementType())
909     return UnableToLegalize;
910 
911   if (Offset % SrcTy.getScalarSizeInBits() != 0)
912     return UnableToLegalize;
913 
914   Observer.changingInstr(MI);
915   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
916 
917   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
918                           Offset);
919   widenScalarDst(MI, WideTy.getScalarType(), 0);
920   Observer.changedInstr(MI);
921   return Legalized;
922 }
923 
924 LegalizerHelper::LegalizeResult
925 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
926                                    LLT WideTy) {
927   if (TypeIdx != 0)
928     return UnableToLegalize;
929   Observer.changingInstr(MI);
930   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
931   widenScalarDst(MI, WideTy);
932   Observer.changedInstr(MI);
933   return Legalized;
934 }
935 
936 LegalizerHelper::LegalizeResult
937 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
938   MIRBuilder.setInstr(MI);
939 
940   switch (MI.getOpcode()) {
941   default:
942     return UnableToLegalize;
943   case TargetOpcode::G_EXTRACT:
944     return widenScalarExtract(MI, TypeIdx, WideTy);
945   case TargetOpcode::G_INSERT:
946     return widenScalarInsert(MI, TypeIdx, WideTy);
947   case TargetOpcode::G_MERGE_VALUES:
948     return widenScalarMergeValues(MI, TypeIdx, WideTy);
949   case TargetOpcode::G_UNMERGE_VALUES:
950     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
951   case TargetOpcode::G_UADDO:
952   case TargetOpcode::G_USUBO: {
953     if (TypeIdx == 1)
954       return UnableToLegalize; // TODO
955     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
956                                          {MI.getOperand(2).getReg()});
957     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
958                                          {MI.getOperand(3).getReg()});
959     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
960                           ? TargetOpcode::G_ADD
961                           : TargetOpcode::G_SUB;
962     // Do the arithmetic in the larger type.
963     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
964     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
965     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
966     auto AndOp = MIRBuilder.buildInstr(
967         TargetOpcode::G_AND, {WideTy},
968         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
969     // There is no overflow if the AndOp is the same as NewOp.
970     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
971                          AndOp);
972     // Now trunc the NewOp to the original result.
973     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
974     MI.eraseFromParent();
975     return Legalized;
976   }
977   case TargetOpcode::G_CTTZ:
978   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
979   case TargetOpcode::G_CTLZ:
980   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
981   case TargetOpcode::G_CTPOP: {
982     if (TypeIdx == 0) {
983       Observer.changingInstr(MI);
984       widenScalarDst(MI, WideTy, 0);
985       Observer.changedInstr(MI);
986       return Legalized;
987     }
988 
989     unsigned SrcReg = MI.getOperand(1).getReg();
990 
991     // First ZEXT the input.
992     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
993     LLT CurTy = MRI.getType(SrcReg);
994     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
995       // The count is the same in the larger type except if the original
996       // value was zero.  This can be handled by setting the bit just off
997       // the top of the original type.
998       auto TopBit =
999           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1000       MIBSrc = MIRBuilder.buildOr(
1001         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1002     }
1003 
1004     // Perform the operation at the larger size.
1005     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1006     // This is already the correct result for CTPOP and CTTZs
1007     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1008         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1009       // The correct result is NewOp - (Difference in widety and current ty).
1010       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1011       MIBNewOp = MIRBuilder.buildInstr(
1012           TargetOpcode::G_SUB, {WideTy},
1013           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1014     }
1015 
1016     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1017     MI.eraseFromParent();
1018     return Legalized;
1019   }
1020   case TargetOpcode::G_BSWAP: {
1021     Observer.changingInstr(MI);
1022     unsigned DstReg = MI.getOperand(0).getReg();
1023 
1024     unsigned ShrReg = MRI.createGenericVirtualRegister(WideTy);
1025     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
1026     unsigned ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1027     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1028 
1029     MI.getOperand(0).setReg(DstExt);
1030 
1031     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1032 
1033     LLT Ty = MRI.getType(DstReg);
1034     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1035     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1036     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1037       .addDef(ShrReg)
1038       .addUse(DstExt)
1039       .addUse(ShiftAmtReg);
1040 
1041     MIRBuilder.buildTrunc(DstReg, ShrReg);
1042     Observer.changedInstr(MI);
1043     return Legalized;
1044   }
1045   case TargetOpcode::G_ADD:
1046   case TargetOpcode::G_AND:
1047   case TargetOpcode::G_MUL:
1048   case TargetOpcode::G_OR:
1049   case TargetOpcode::G_XOR:
1050   case TargetOpcode::G_SUB:
1051     // Perform operation at larger width (any extension is fines here, high bits
1052     // don't affect the result) and then truncate the result back to the
1053     // original type.
1054     Observer.changingInstr(MI);
1055     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1056     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1057     widenScalarDst(MI, WideTy);
1058     Observer.changedInstr(MI);
1059     return Legalized;
1060 
1061   case TargetOpcode::G_SHL:
1062       Observer.changingInstr(MI);
1063 
1064     if (TypeIdx == 0) {
1065       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1066       widenScalarDst(MI, WideTy);
1067     } else {
1068       assert(TypeIdx == 1);
1069       // The "number of bits to shift" operand must preserve its value as an
1070       // unsigned integer:
1071       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1072     }
1073 
1074     Observer.changedInstr(MI);
1075     return Legalized;
1076 
1077   case TargetOpcode::G_SDIV:
1078   case TargetOpcode::G_SREM:
1079     Observer.changingInstr(MI);
1080     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1081     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1082     widenScalarDst(MI, WideTy);
1083     Observer.changedInstr(MI);
1084     return Legalized;
1085 
1086   case TargetOpcode::G_ASHR:
1087   case TargetOpcode::G_LSHR:
1088     Observer.changingInstr(MI);
1089 
1090     if (TypeIdx == 0) {
1091       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1092         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1093 
1094       widenScalarSrc(MI, WideTy, 1, CvtOp);
1095       widenScalarDst(MI, WideTy);
1096     } else {
1097       assert(TypeIdx == 1);
1098       // The "number of bits to shift" operand must preserve its value as an
1099       // unsigned integer:
1100       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1101     }
1102 
1103     Observer.changedInstr(MI);
1104     return Legalized;
1105   case TargetOpcode::G_UDIV:
1106   case TargetOpcode::G_UREM:
1107     Observer.changingInstr(MI);
1108     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1109     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1110     widenScalarDst(MI, WideTy);
1111     Observer.changedInstr(MI);
1112     return Legalized;
1113 
1114   case TargetOpcode::G_SELECT:
1115     Observer.changingInstr(MI);
1116     if (TypeIdx == 0) {
1117       // Perform operation at larger width (any extension is fine here, high
1118       // bits don't affect the result) and then truncate the result back to the
1119       // original type.
1120       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1121       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1122       widenScalarDst(MI, WideTy);
1123     } else {
1124       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1125       // Explicit extension is required here since high bits affect the result.
1126       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1127     }
1128     Observer.changedInstr(MI);
1129     return Legalized;
1130 
1131   case TargetOpcode::G_FPTOSI:
1132   case TargetOpcode::G_FPTOUI:
1133     if (TypeIdx != 0)
1134       return UnableToLegalize;
1135     Observer.changingInstr(MI);
1136     widenScalarDst(MI, WideTy);
1137     Observer.changedInstr(MI);
1138     return Legalized;
1139 
1140   case TargetOpcode::G_SITOFP:
1141     if (TypeIdx != 1)
1142       return UnableToLegalize;
1143     Observer.changingInstr(MI);
1144     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1145     Observer.changedInstr(MI);
1146     return Legalized;
1147 
1148   case TargetOpcode::G_UITOFP:
1149     if (TypeIdx != 1)
1150       return UnableToLegalize;
1151     Observer.changingInstr(MI);
1152     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1153     Observer.changedInstr(MI);
1154     return Legalized;
1155 
1156   case TargetOpcode::G_LOAD:
1157   case TargetOpcode::G_SEXTLOAD:
1158   case TargetOpcode::G_ZEXTLOAD:
1159     Observer.changingInstr(MI);
1160     widenScalarDst(MI, WideTy);
1161     Observer.changedInstr(MI);
1162     return Legalized;
1163 
1164   case TargetOpcode::G_STORE: {
1165     if (TypeIdx != 0)
1166       return UnableToLegalize;
1167 
1168     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1169     if (!isPowerOf2_32(Ty.getSizeInBits()))
1170       return UnableToLegalize;
1171 
1172     Observer.changingInstr(MI);
1173 
1174     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1175       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1176     widenScalarSrc(MI, WideTy, 0, ExtType);
1177 
1178     Observer.changedInstr(MI);
1179     return Legalized;
1180   }
1181   case TargetOpcode::G_CONSTANT: {
1182     MachineOperand &SrcMO = MI.getOperand(1);
1183     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1184     const APInt &Val = SrcMO.getCImm()->getValue().sext(WideTy.getSizeInBits());
1185     Observer.changingInstr(MI);
1186     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1187 
1188     widenScalarDst(MI, WideTy);
1189     Observer.changedInstr(MI);
1190     return Legalized;
1191   }
1192   case TargetOpcode::G_FCONSTANT: {
1193     MachineOperand &SrcMO = MI.getOperand(1);
1194     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1195     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1196     bool LosesInfo;
1197     switch (WideTy.getSizeInBits()) {
1198     case 32:
1199       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1200                   &LosesInfo);
1201       break;
1202     case 64:
1203       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1204                   &LosesInfo);
1205       break;
1206     default:
1207       return UnableToLegalize;
1208     }
1209 
1210     assert(!LosesInfo && "extend should always be lossless");
1211 
1212     Observer.changingInstr(MI);
1213     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1214 
1215     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1216     Observer.changedInstr(MI);
1217     return Legalized;
1218   }
1219   case TargetOpcode::G_IMPLICIT_DEF: {
1220     Observer.changingInstr(MI);
1221     widenScalarDst(MI, WideTy);
1222     Observer.changedInstr(MI);
1223     return Legalized;
1224   }
1225   case TargetOpcode::G_BRCOND:
1226     Observer.changingInstr(MI);
1227     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1228     Observer.changedInstr(MI);
1229     return Legalized;
1230 
1231   case TargetOpcode::G_FCMP:
1232     Observer.changingInstr(MI);
1233     if (TypeIdx == 0)
1234       widenScalarDst(MI, WideTy);
1235     else {
1236       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1237       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1238     }
1239     Observer.changedInstr(MI);
1240     return Legalized;
1241 
1242   case TargetOpcode::G_ICMP:
1243     Observer.changingInstr(MI);
1244     if (TypeIdx == 0)
1245       widenScalarDst(MI, WideTy);
1246     else {
1247       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1248                                MI.getOperand(1).getPredicate()))
1249                                ? TargetOpcode::G_SEXT
1250                                : TargetOpcode::G_ZEXT;
1251       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1252       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1253     }
1254     Observer.changedInstr(MI);
1255     return Legalized;
1256 
1257   case TargetOpcode::G_GEP:
1258     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
1259     Observer.changingInstr(MI);
1260     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1261     Observer.changedInstr(MI);
1262     return Legalized;
1263 
1264   case TargetOpcode::G_PHI: {
1265     assert(TypeIdx == 0 && "Expecting only Idx 0");
1266 
1267     Observer.changingInstr(MI);
1268     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1269       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1270       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1271       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1272     }
1273 
1274     MachineBasicBlock &MBB = *MI.getParent();
1275     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1276     widenScalarDst(MI, WideTy);
1277     Observer.changedInstr(MI);
1278     return Legalized;
1279   }
1280   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1281     if (TypeIdx == 0) {
1282       unsigned VecReg = MI.getOperand(1).getReg();
1283       LLT VecTy = MRI.getType(VecReg);
1284       Observer.changingInstr(MI);
1285 
1286       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1287                                      WideTy.getSizeInBits()),
1288                      1, TargetOpcode::G_SEXT);
1289 
1290       widenScalarDst(MI, WideTy, 0);
1291       Observer.changedInstr(MI);
1292       return Legalized;
1293     }
1294 
1295     if (TypeIdx != 2)
1296       return UnableToLegalize;
1297     Observer.changingInstr(MI);
1298     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1299     Observer.changedInstr(MI);
1300     return Legalized;
1301   }
1302   case TargetOpcode::G_FADD:
1303   case TargetOpcode::G_FMUL:
1304   case TargetOpcode::G_FSUB:
1305   case TargetOpcode::G_FMA:
1306   case TargetOpcode::G_FNEG:
1307   case TargetOpcode::G_FABS:
1308   case TargetOpcode::G_FCANONICALIZE:
1309   case TargetOpcode::G_FDIV:
1310   case TargetOpcode::G_FREM:
1311   case TargetOpcode::G_FCEIL:
1312   case TargetOpcode::G_FFLOOR:
1313   case TargetOpcode::G_FCOS:
1314   case TargetOpcode::G_FSIN:
1315   case TargetOpcode::G_FLOG10:
1316   case TargetOpcode::G_FLOG:
1317   case TargetOpcode::G_FLOG2:
1318   case TargetOpcode::G_FSQRT:
1319   case TargetOpcode::G_FEXP:
1320   case TargetOpcode::G_FEXP2:
1321     assert(TypeIdx == 0);
1322     Observer.changingInstr(MI);
1323 
1324     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1325       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1326 
1327     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1328     Observer.changedInstr(MI);
1329     return Legalized;
1330   case TargetOpcode::G_INTTOPTR:
1331     if (TypeIdx != 1)
1332       return UnableToLegalize;
1333 
1334     Observer.changingInstr(MI);
1335     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1336     Observer.changedInstr(MI);
1337     return Legalized;
1338   case TargetOpcode::G_PTRTOINT:
1339     if (TypeIdx != 0)
1340       return UnableToLegalize;
1341 
1342     Observer.changingInstr(MI);
1343     widenScalarDst(MI, WideTy, 0);
1344     Observer.changedInstr(MI);
1345     return Legalized;
1346   }
1347 }
1348 
1349 LegalizerHelper::LegalizeResult
1350 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1351   using namespace TargetOpcode;
1352   MIRBuilder.setInstr(MI);
1353 
1354   switch(MI.getOpcode()) {
1355   default:
1356     return UnableToLegalize;
1357   case TargetOpcode::G_SREM:
1358   case TargetOpcode::G_UREM: {
1359     unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
1360     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1361         .addDef(QuotReg)
1362         .addUse(MI.getOperand(1).getReg())
1363         .addUse(MI.getOperand(2).getReg());
1364 
1365     unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
1366     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1367     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1368                         ProdReg);
1369     MI.eraseFromParent();
1370     return Legalized;
1371   }
1372   case TargetOpcode::G_SMULO:
1373   case TargetOpcode::G_UMULO: {
1374     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
1375     // result.
1376     unsigned Res = MI.getOperand(0).getReg();
1377     unsigned Overflow = MI.getOperand(1).getReg();
1378     unsigned LHS = MI.getOperand(2).getReg();
1379     unsigned RHS = MI.getOperand(3).getReg();
1380 
1381     MIRBuilder.buildMul(Res, LHS, RHS);
1382 
1383     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
1384                           ? TargetOpcode::G_SMULH
1385                           : TargetOpcode::G_UMULH;
1386 
1387     unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
1388     MIRBuilder.buildInstr(Opcode)
1389       .addDef(HiPart)
1390       .addUse(LHS)
1391       .addUse(RHS);
1392 
1393     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
1394     MIRBuilder.buildConstant(Zero, 0);
1395 
1396     // For *signed* multiply, overflow is detected by checking:
1397     // (hi != (lo >> bitwidth-1))
1398     if (Opcode == TargetOpcode::G_SMULH) {
1399       unsigned Shifted = MRI.createGenericVirtualRegister(Ty);
1400       unsigned ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1401       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
1402       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
1403         .addDef(Shifted)
1404         .addUse(Res)
1405         .addUse(ShiftAmt);
1406       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
1407     } else {
1408       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
1409     }
1410     MI.eraseFromParent();
1411     return Legalized;
1412   }
1413   case TargetOpcode::G_FNEG: {
1414     // TODO: Handle vector types once we are able to
1415     // represent them.
1416     if (Ty.isVector())
1417       return UnableToLegalize;
1418     unsigned Res = MI.getOperand(0).getReg();
1419     Type *ZeroTy;
1420     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1421     switch (Ty.getSizeInBits()) {
1422     case 16:
1423       ZeroTy = Type::getHalfTy(Ctx);
1424       break;
1425     case 32:
1426       ZeroTy = Type::getFloatTy(Ctx);
1427       break;
1428     case 64:
1429       ZeroTy = Type::getDoubleTy(Ctx);
1430       break;
1431     case 128:
1432       ZeroTy = Type::getFP128Ty(Ctx);
1433       break;
1434     default:
1435       llvm_unreachable("unexpected floating-point type");
1436     }
1437     ConstantFP &ZeroForNegation =
1438         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
1439     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
1440     MIRBuilder.buildInstr(TargetOpcode::G_FSUB)
1441         .addDef(Res)
1442         .addUse(Zero->getOperand(0).getReg())
1443         .addUse(MI.getOperand(1).getReg());
1444     MI.eraseFromParent();
1445     return Legalized;
1446   }
1447   case TargetOpcode::G_FSUB: {
1448     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
1449     // First, check if G_FNEG is marked as Lower. If so, we may
1450     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
1451     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
1452       return UnableToLegalize;
1453     unsigned Res = MI.getOperand(0).getReg();
1454     unsigned LHS = MI.getOperand(1).getReg();
1455     unsigned RHS = MI.getOperand(2).getReg();
1456     unsigned Neg = MRI.createGenericVirtualRegister(Ty);
1457     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
1458     MIRBuilder.buildInstr(TargetOpcode::G_FADD)
1459         .addDef(Res)
1460         .addUse(LHS)
1461         .addUse(Neg);
1462     MI.eraseFromParent();
1463     return Legalized;
1464   }
1465   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
1466     unsigned OldValRes = MI.getOperand(0).getReg();
1467     unsigned SuccessRes = MI.getOperand(1).getReg();
1468     unsigned Addr = MI.getOperand(2).getReg();
1469     unsigned CmpVal = MI.getOperand(3).getReg();
1470     unsigned NewVal = MI.getOperand(4).getReg();
1471     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
1472                                   **MI.memoperands_begin());
1473     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
1474     MI.eraseFromParent();
1475     return Legalized;
1476   }
1477   case TargetOpcode::G_LOAD:
1478   case TargetOpcode::G_SEXTLOAD:
1479   case TargetOpcode::G_ZEXTLOAD: {
1480     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
1481     unsigned DstReg = MI.getOperand(0).getReg();
1482     unsigned PtrReg = MI.getOperand(1).getReg();
1483     LLT DstTy = MRI.getType(DstReg);
1484     auto &MMO = **MI.memoperands_begin();
1485 
1486     if (DstTy.getSizeInBits() == MMO.getSize() /* in bytes */ * 8) {
1487       // In the case of G_LOAD, this was a non-extending load already and we're
1488       // about to lower to the same instruction.
1489       if (MI.getOpcode() == TargetOpcode::G_LOAD)
1490           return UnableToLegalize;
1491       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
1492       MI.eraseFromParent();
1493       return Legalized;
1494     }
1495 
1496     if (DstTy.isScalar()) {
1497       unsigned TmpReg = MRI.createGenericVirtualRegister(
1498           LLT::scalar(MMO.getSize() /* in bytes */ * 8));
1499       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
1500       switch (MI.getOpcode()) {
1501       default:
1502         llvm_unreachable("Unexpected opcode");
1503       case TargetOpcode::G_LOAD:
1504         MIRBuilder.buildAnyExt(DstReg, TmpReg);
1505         break;
1506       case TargetOpcode::G_SEXTLOAD:
1507         MIRBuilder.buildSExt(DstReg, TmpReg);
1508         break;
1509       case TargetOpcode::G_ZEXTLOAD:
1510         MIRBuilder.buildZExt(DstReg, TmpReg);
1511         break;
1512       }
1513       MI.eraseFromParent();
1514       return Legalized;
1515     }
1516 
1517     return UnableToLegalize;
1518   }
1519   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1520   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1521   case TargetOpcode::G_CTLZ:
1522   case TargetOpcode::G_CTTZ:
1523   case TargetOpcode::G_CTPOP:
1524     return lowerBitCount(MI, TypeIdx, Ty);
1525   case G_UADDO: {
1526     unsigned Res = MI.getOperand(0).getReg();
1527     unsigned CarryOut = MI.getOperand(1).getReg();
1528     unsigned LHS = MI.getOperand(2).getReg();
1529     unsigned RHS = MI.getOperand(3).getReg();
1530 
1531     MIRBuilder.buildAdd(Res, LHS, RHS);
1532     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
1533 
1534     MI.eraseFromParent();
1535     return Legalized;
1536   }
1537   case G_UADDE: {
1538     unsigned Res = MI.getOperand(0).getReg();
1539     unsigned CarryOut = MI.getOperand(1).getReg();
1540     unsigned LHS = MI.getOperand(2).getReg();
1541     unsigned RHS = MI.getOperand(3).getReg();
1542     unsigned CarryIn = MI.getOperand(4).getReg();
1543 
1544     unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
1545     unsigned ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
1546 
1547     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
1548     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
1549     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
1550     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
1551 
1552     MI.eraseFromParent();
1553     return Legalized;
1554   }
1555   case G_USUBO: {
1556     unsigned Res = MI.getOperand(0).getReg();
1557     unsigned BorrowOut = MI.getOperand(1).getReg();
1558     unsigned LHS = MI.getOperand(2).getReg();
1559     unsigned RHS = MI.getOperand(3).getReg();
1560 
1561     MIRBuilder.buildSub(Res, LHS, RHS);
1562     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
1563 
1564     MI.eraseFromParent();
1565     return Legalized;
1566   }
1567   case G_USUBE: {
1568     unsigned Res = MI.getOperand(0).getReg();
1569     unsigned BorrowOut = MI.getOperand(1).getReg();
1570     unsigned LHS = MI.getOperand(2).getReg();
1571     unsigned RHS = MI.getOperand(3).getReg();
1572     unsigned BorrowIn = MI.getOperand(4).getReg();
1573 
1574     unsigned TmpRes = MRI.createGenericVirtualRegister(Ty);
1575     unsigned ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
1576     unsigned LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1577     unsigned LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1578 
1579     MIRBuilder.buildSub(TmpRes, LHS, RHS);
1580     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
1581     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
1582     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
1583     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
1584     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
1585 
1586     MI.eraseFromParent();
1587     return Legalized;
1588   }
1589   }
1590 }
1591 
1592 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
1593     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
1594   SmallVector<unsigned, 2> DstRegs;
1595 
1596   unsigned NarrowSize = NarrowTy.getSizeInBits();
1597   unsigned DstReg = MI.getOperand(0).getReg();
1598   unsigned Size = MRI.getType(DstReg).getSizeInBits();
1599   int NumParts = Size / NarrowSize;
1600   // FIXME: Don't know how to handle the situation where the small vectors
1601   // aren't all the same size yet.
1602   if (Size % NarrowSize != 0)
1603     return UnableToLegalize;
1604 
1605   for (int i = 0; i < NumParts; ++i) {
1606     unsigned TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
1607     MIRBuilder.buildUndef(TmpReg);
1608     DstRegs.push_back(TmpReg);
1609   }
1610 
1611   if (NarrowTy.isVector())
1612     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1613   else
1614     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1615 
1616   MI.eraseFromParent();
1617   return Legalized;
1618 }
1619 
1620 LegalizerHelper::LegalizeResult
1621 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
1622                                           LLT NarrowTy) {
1623   const unsigned Opc = MI.getOpcode();
1624   const unsigned NumOps = MI.getNumOperands() - 1;
1625   const unsigned NarrowSize = NarrowTy.getSizeInBits();
1626   const unsigned DstReg = MI.getOperand(0).getReg();
1627   const unsigned Flags = MI.getFlags();
1628   const LLT DstTy = MRI.getType(DstReg);
1629   const unsigned Size = DstTy.getSizeInBits();
1630   const int NumParts = Size / NarrowSize;
1631   const LLT EltTy = DstTy.getElementType();
1632   const unsigned EltSize = EltTy.getSizeInBits();
1633   const unsigned BitsForNumParts = NarrowSize * NumParts;
1634 
1635   // Check if we have any leftovers. If we do, then only handle the case where
1636   // the leftover is one element.
1637   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
1638     return UnableToLegalize;
1639 
1640   if (BitsForNumParts != Size) {
1641     unsigned AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
1642     MIRBuilder.buildUndef(AccumDstReg);
1643 
1644     // Handle the pieces which evenly divide into the requested type with
1645     // extract/op/insert sequence.
1646     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
1647       SmallVector<SrcOp, 4> SrcOps;
1648       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1649         unsigned PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
1650         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
1651         SrcOps.push_back(PartOpReg);
1652       }
1653 
1654       unsigned PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
1655       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1656 
1657       unsigned PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
1658       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
1659       AccumDstReg = PartInsertReg;
1660     }
1661 
1662     // Handle the remaining element sized leftover piece.
1663     SmallVector<SrcOp, 4> SrcOps;
1664     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1665       unsigned PartOpReg = MRI.createGenericVirtualRegister(EltTy);
1666       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
1667                               BitsForNumParts);
1668       SrcOps.push_back(PartOpReg);
1669     }
1670 
1671     unsigned PartDstReg = MRI.createGenericVirtualRegister(EltTy);
1672     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1673     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
1674     MI.eraseFromParent();
1675 
1676     return Legalized;
1677   }
1678 
1679   SmallVector<unsigned, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
1680 
1681   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
1682 
1683   if (NumOps >= 2)
1684     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
1685 
1686   if (NumOps >= 3)
1687     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
1688 
1689   for (int i = 0; i < NumParts; ++i) {
1690     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
1691 
1692     if (NumOps == 1)
1693       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
1694     else if (NumOps == 2) {
1695       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
1696     } else if (NumOps == 3) {
1697       MIRBuilder.buildInstr(Opc, {DstReg},
1698                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
1699     }
1700 
1701     DstRegs.push_back(DstReg);
1702   }
1703 
1704   if (NarrowTy.isVector())
1705     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1706   else
1707     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1708 
1709   MI.eraseFromParent();
1710   return Legalized;
1711 }
1712 
1713 // Handle splitting vector operations which need to have the same number of
1714 // elements in each type index, but each type index may have a different element
1715 // type.
1716 //
1717 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
1718 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1719 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1720 //
1721 // Also handles some irregular breakdown cases, e.g.
1722 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
1723 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1724 //             s64 = G_SHL s64, s32
1725 LegalizerHelper::LegalizeResult
1726 LegalizerHelper::fewerElementsVectorMultiEltType(
1727   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
1728   if (TypeIdx != 0)
1729     return UnableToLegalize;
1730 
1731   const LLT NarrowTy0 = NarrowTyArg;
1732   const unsigned NewNumElts =
1733       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
1734 
1735   const unsigned DstReg = MI.getOperand(0).getReg();
1736   LLT DstTy = MRI.getType(DstReg);
1737   LLT LeftoverTy0;
1738 
1739   int NumParts, NumLeftover;
1740   // All of the operands need to have the same number of elements, so if we can
1741   // determine a type breakdown for the result type, we can for all of the
1742   // source types.
1743   std::tie(NumParts, NumLeftover)
1744     = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0);
1745   if (NumParts < 0)
1746     return UnableToLegalize;
1747 
1748   SmallVector<MachineInstrBuilder, 4> NewInsts;
1749 
1750   SmallVector<unsigned, 4> DstRegs, LeftoverDstRegs;
1751   SmallVector<unsigned, 4> PartRegs, LeftoverRegs;
1752 
1753   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1754     LLT LeftoverTy;
1755     unsigned SrcReg = MI.getOperand(I).getReg();
1756     LLT SrcTyI = MRI.getType(SrcReg);
1757     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
1758     LLT LeftoverTyI;
1759 
1760     // Split this operand into the requested typed registers, and any leftover
1761     // required to reproduce the original type.
1762     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
1763                       LeftoverRegs))
1764       return UnableToLegalize;
1765 
1766     if (I == 1) {
1767       // For the first operand, create an instruction for each part and setup
1768       // the result.
1769       for (unsigned PartReg : PartRegs) {
1770         unsigned PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1771         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
1772                                .addDef(PartDstReg)
1773                                .addUse(PartReg));
1774         DstRegs.push_back(PartDstReg);
1775       }
1776 
1777       for (unsigned LeftoverReg : LeftoverRegs) {
1778         unsigned PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
1779         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
1780                                .addDef(PartDstReg)
1781                                .addUse(LeftoverReg));
1782         LeftoverDstRegs.push_back(PartDstReg);
1783       }
1784     } else {
1785       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
1786 
1787       // Add the newly created operand splits to the existing instructions. The
1788       // odd-sized pieces are ordered after the requested NarrowTyArg sized
1789       // pieces.
1790       unsigned InstCount = 0;
1791       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
1792         NewInsts[InstCount++].addUse(PartRegs[J]);
1793       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
1794         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
1795     }
1796 
1797     PartRegs.clear();
1798     LeftoverRegs.clear();
1799   }
1800 
1801   // Insert the newly built operations and rebuild the result register.
1802   for (auto &MIB : NewInsts)
1803     MIRBuilder.insertInstr(MIB);
1804 
1805   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
1806 
1807   MI.eraseFromParent();
1808   return Legalized;
1809 }
1810 
1811 LegalizerHelper::LegalizeResult
1812 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
1813                                           LLT NarrowTy) {
1814   if (TypeIdx != 0)
1815     return UnableToLegalize;
1816 
1817   unsigned DstReg = MI.getOperand(0).getReg();
1818   unsigned SrcReg = MI.getOperand(1).getReg();
1819   LLT DstTy = MRI.getType(DstReg);
1820   LLT SrcTy = MRI.getType(SrcReg);
1821 
1822   LLT NarrowTy0 = NarrowTy;
1823   LLT NarrowTy1;
1824   unsigned NumParts;
1825 
1826   if (NarrowTy.isVector()) {
1827     // Uneven breakdown not handled.
1828     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
1829     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
1830       return UnableToLegalize;
1831 
1832     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
1833   } else {
1834     NumParts = DstTy.getNumElements();
1835     NarrowTy1 = SrcTy.getElementType();
1836   }
1837 
1838   SmallVector<unsigned, 4> SrcRegs, DstRegs;
1839   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
1840 
1841   for (unsigned I = 0; I < NumParts; ++I) {
1842     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1843     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
1844       .addDef(DstReg)
1845       .addUse(SrcRegs[I]);
1846 
1847     NewInst->setFlags(MI.getFlags());
1848     DstRegs.push_back(DstReg);
1849   }
1850 
1851   if (NarrowTy.isVector())
1852     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1853   else
1854     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1855 
1856   MI.eraseFromParent();
1857   return Legalized;
1858 }
1859 
1860 LegalizerHelper::LegalizeResult
1861 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
1862                                         LLT NarrowTy) {
1863   unsigned DstReg = MI.getOperand(0).getReg();
1864   unsigned Src0Reg = MI.getOperand(2).getReg();
1865   LLT DstTy = MRI.getType(DstReg);
1866   LLT SrcTy = MRI.getType(Src0Reg);
1867 
1868   unsigned NumParts;
1869   LLT NarrowTy0, NarrowTy1;
1870 
1871   if (TypeIdx == 0) {
1872     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
1873     unsigned OldElts = DstTy.getNumElements();
1874 
1875     NarrowTy0 = NarrowTy;
1876     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
1877     NarrowTy1 = NarrowTy.isVector() ?
1878       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
1879       SrcTy.getElementType();
1880 
1881   } else {
1882     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
1883     unsigned OldElts = SrcTy.getNumElements();
1884 
1885     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
1886       NarrowTy.getNumElements();
1887     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
1888                             DstTy.getScalarSizeInBits());
1889     NarrowTy1 = NarrowTy;
1890   }
1891 
1892   // FIXME: Don't know how to handle the situation where the small vectors
1893   // aren't all the same size yet.
1894   if (NarrowTy1.isVector() &&
1895       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
1896     return UnableToLegalize;
1897 
1898   CmpInst::Predicate Pred
1899     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
1900 
1901   SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
1902   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
1903   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
1904 
1905   for (unsigned I = 0; I < NumParts; ++I) {
1906     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1907     DstRegs.push_back(DstReg);
1908 
1909     if (MI.getOpcode() == TargetOpcode::G_ICMP)
1910       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
1911     else {
1912       MachineInstr *NewCmp
1913         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
1914       NewCmp->setFlags(MI.getFlags());
1915     }
1916   }
1917 
1918   if (NarrowTy1.isVector())
1919     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1920   else
1921     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1922 
1923   MI.eraseFromParent();
1924   return Legalized;
1925 }
1926 
1927 LegalizerHelper::LegalizeResult
1928 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
1929                                            LLT NarrowTy) {
1930   unsigned DstReg = MI.getOperand(0).getReg();
1931   unsigned CondReg = MI.getOperand(1).getReg();
1932 
1933   unsigned NumParts = 0;
1934   LLT NarrowTy0, NarrowTy1;
1935 
1936   LLT DstTy = MRI.getType(DstReg);
1937   LLT CondTy = MRI.getType(CondReg);
1938   unsigned Size = DstTy.getSizeInBits();
1939 
1940   assert(TypeIdx == 0 || CondTy.isVector());
1941 
1942   if (TypeIdx == 0) {
1943     NarrowTy0 = NarrowTy;
1944     NarrowTy1 = CondTy;
1945 
1946     unsigned NarrowSize = NarrowTy0.getSizeInBits();
1947     // FIXME: Don't know how to handle the situation where the small vectors
1948     // aren't all the same size yet.
1949     if (Size % NarrowSize != 0)
1950       return UnableToLegalize;
1951 
1952     NumParts = Size / NarrowSize;
1953 
1954     // Need to break down the condition type
1955     if (CondTy.isVector()) {
1956       if (CondTy.getNumElements() == NumParts)
1957         NarrowTy1 = CondTy.getElementType();
1958       else
1959         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
1960                                 CondTy.getScalarSizeInBits());
1961     }
1962   } else {
1963     NumParts = CondTy.getNumElements();
1964     if (NarrowTy.isVector()) {
1965       // TODO: Handle uneven breakdown.
1966       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
1967         return UnableToLegalize;
1968 
1969       return UnableToLegalize;
1970     } else {
1971       NarrowTy0 = DstTy.getElementType();
1972       NarrowTy1 = NarrowTy;
1973     }
1974   }
1975 
1976   SmallVector<unsigned, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
1977   if (CondTy.isVector())
1978     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
1979 
1980   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
1981   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
1982 
1983   for (unsigned i = 0; i < NumParts; ++i) {
1984     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1985     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
1986                            Src1Regs[i], Src2Regs[i]);
1987     DstRegs.push_back(DstReg);
1988   }
1989 
1990   if (NarrowTy0.isVector())
1991     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1992   else
1993     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1994 
1995   MI.eraseFromParent();
1996   return Legalized;
1997 }
1998 
1999 LegalizerHelper::LegalizeResult
2000 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2001                                         LLT NarrowTy) {
2002   const unsigned DstReg = MI.getOperand(0).getReg();
2003   LLT PhiTy = MRI.getType(DstReg);
2004   LLT LeftoverTy;
2005 
2006   // All of the operands need to have the same number of elements, so if we can
2007   // determine a type breakdown for the result type, we can for all of the
2008   // source types.
2009   int NumParts, NumLeftover;
2010   std::tie(NumParts, NumLeftover)
2011     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2012   if (NumParts < 0)
2013     return UnableToLegalize;
2014 
2015   SmallVector<unsigned, 4> DstRegs, LeftoverDstRegs;
2016   SmallVector<MachineInstrBuilder, 4> NewInsts;
2017 
2018   const int TotalNumParts = NumParts + NumLeftover;
2019 
2020   // Insert the new phis in the result block first.
2021   for (int I = 0; I != TotalNumParts; ++I) {
2022     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2023     unsigned PartDstReg = MRI.createGenericVirtualRegister(Ty);
2024     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2025                        .addDef(PartDstReg));
2026     if (I < NumParts)
2027       DstRegs.push_back(PartDstReg);
2028     else
2029       LeftoverDstRegs.push_back(PartDstReg);
2030   }
2031 
2032   MachineBasicBlock *MBB = MI.getParent();
2033   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2034   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2035 
2036   SmallVector<unsigned, 4> PartRegs, LeftoverRegs;
2037 
2038   // Insert code to extract the incoming values in each predecessor block.
2039   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2040     PartRegs.clear();
2041     LeftoverRegs.clear();
2042 
2043     unsigned SrcReg = MI.getOperand(I).getReg();
2044     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2045     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2046 
2047     LLT Unused;
2048     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2049                       LeftoverRegs))
2050       return UnableToLegalize;
2051 
2052     // Add the newly created operand splits to the existing instructions. The
2053     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2054     // pieces.
2055     for (int J = 0; J != TotalNumParts; ++J) {
2056       MachineInstrBuilder MIB = NewInsts[J];
2057       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2058       MIB.addMBB(&OpMBB);
2059     }
2060   }
2061 
2062   MI.eraseFromParent();
2063   return Legalized;
2064 }
2065 
2066 LegalizerHelper::LegalizeResult
2067 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2068                                       LLT NarrowTy) {
2069   // FIXME: Don't know how to handle secondary types yet.
2070   if (TypeIdx != 0)
2071     return UnableToLegalize;
2072 
2073   MachineMemOperand *MMO = *MI.memoperands_begin();
2074 
2075   // This implementation doesn't work for atomics. Give up instead of doing
2076   // something invalid.
2077   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2078       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2079     return UnableToLegalize;
2080 
2081   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2082   unsigned ValReg = MI.getOperand(0).getReg();
2083   unsigned AddrReg = MI.getOperand(1).getReg();
2084   LLT ValTy = MRI.getType(ValReg);
2085 
2086   int NumParts = -1;
2087   int NumLeftover = -1;
2088   LLT LeftoverTy;
2089   SmallVector<unsigned, 8> NarrowRegs, NarrowLeftoverRegs;
2090   if (IsLoad) {
2091     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2092   } else {
2093     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2094                      NarrowLeftoverRegs)) {
2095       NumParts = NarrowRegs.size();
2096       NumLeftover = NarrowLeftoverRegs.size();
2097     }
2098   }
2099 
2100   if (NumParts == -1)
2101     return UnableToLegalize;
2102 
2103   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2104 
2105   unsigned TotalSize = ValTy.getSizeInBits();
2106 
2107   // Split the load/store into PartTy sized pieces starting at Offset. If this
2108   // is a load, return the new registers in ValRegs. For a store, each elements
2109   // of ValRegs should be PartTy. Returns the next offset that needs to be
2110   // handled.
2111   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<unsigned> &ValRegs,
2112                              unsigned Offset) -> unsigned {
2113     MachineFunction &MF = MIRBuilder.getMF();
2114     unsigned PartSize = PartTy.getSizeInBits();
2115     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2116          Offset += PartSize, ++Idx) {
2117       unsigned ByteSize = PartSize / 8;
2118       unsigned ByteOffset = Offset / 8;
2119       unsigned NewAddrReg = 0;
2120 
2121       MIRBuilder.materializeGEP(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2122 
2123       MachineMemOperand *NewMMO =
2124         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2125 
2126       if (IsLoad) {
2127         unsigned Dst = MRI.createGenericVirtualRegister(PartTy);
2128         ValRegs.push_back(Dst);
2129         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
2130       } else {
2131         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
2132       }
2133     }
2134 
2135     return Offset;
2136   };
2137 
2138   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
2139 
2140   // Handle the rest of the register if this isn't an even type breakdown.
2141   if (LeftoverTy.isValid())
2142     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
2143 
2144   if (IsLoad) {
2145     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
2146                 LeftoverTy, NarrowLeftoverRegs);
2147   }
2148 
2149   MI.eraseFromParent();
2150   return Legalized;
2151 }
2152 
2153 LegalizerHelper::LegalizeResult
2154 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
2155                                      LLT NarrowTy) {
2156   using namespace TargetOpcode;
2157 
2158   MIRBuilder.setInstr(MI);
2159   switch (MI.getOpcode()) {
2160   case G_IMPLICIT_DEF:
2161     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
2162   case G_AND:
2163   case G_OR:
2164   case G_XOR:
2165   case G_ADD:
2166   case G_SUB:
2167   case G_MUL:
2168   case G_SMULH:
2169   case G_UMULH:
2170   case G_FADD:
2171   case G_FMUL:
2172   case G_FSUB:
2173   case G_FNEG:
2174   case G_FABS:
2175   case G_FCANONICALIZE:
2176   case G_FDIV:
2177   case G_FREM:
2178   case G_FMA:
2179   case G_FPOW:
2180   case G_FEXP:
2181   case G_FEXP2:
2182   case G_FLOG:
2183   case G_FLOG2:
2184   case G_FLOG10:
2185   case G_FCEIL:
2186   case G_FFLOOR:
2187   case G_INTRINSIC_ROUND:
2188   case G_INTRINSIC_TRUNC:
2189   case G_FCOS:
2190   case G_FSIN:
2191   case G_FSQRT:
2192   case G_BSWAP:
2193     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
2194   case G_SHL:
2195   case G_LSHR:
2196   case G_ASHR:
2197   case G_CTLZ:
2198   case G_CTLZ_ZERO_UNDEF:
2199   case G_CTTZ:
2200   case G_CTTZ_ZERO_UNDEF:
2201   case G_CTPOP:
2202     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
2203   case G_ZEXT:
2204   case G_SEXT:
2205   case G_ANYEXT:
2206   case G_FPEXT:
2207   case G_FPTRUNC:
2208   case G_SITOFP:
2209   case G_UITOFP:
2210   case G_FPTOSI:
2211   case G_FPTOUI:
2212   case G_INTTOPTR:
2213   case G_PTRTOINT:
2214   case G_ADDRSPACE_CAST:
2215     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
2216   case G_ICMP:
2217   case G_FCMP:
2218     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
2219   case G_SELECT:
2220     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
2221   case G_PHI:
2222     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
2223   case G_LOAD:
2224   case G_STORE:
2225     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
2226   default:
2227     return UnableToLegalize;
2228   }
2229 }
2230 
2231 LegalizerHelper::LegalizeResult
2232 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
2233                                              const LLT HalfTy, const LLT AmtTy) {
2234 
2235   unsigned InL = MRI.createGenericVirtualRegister(HalfTy);
2236   unsigned InH = MRI.createGenericVirtualRegister(HalfTy);
2237   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2238 
2239   if (Amt.isNullValue()) {
2240     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
2241     MI.eraseFromParent();
2242     return Legalized;
2243   }
2244 
2245   LLT NVT = HalfTy;
2246   unsigned NVTBits = HalfTy.getSizeInBits();
2247   unsigned VTBits = 2 * NVTBits;
2248 
2249   SrcOp Lo(0), Hi(0);
2250   if (MI.getOpcode() == TargetOpcode::G_SHL) {
2251     if (Amt.ugt(VTBits)) {
2252       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2253     } else if (Amt.ugt(NVTBits)) {
2254       Lo = MIRBuilder.buildConstant(NVT, 0);
2255       Hi = MIRBuilder.buildShl(NVT, InL,
2256                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2257     } else if (Amt == NVTBits) {
2258       Lo = MIRBuilder.buildConstant(NVT, 0);
2259       Hi = InL;
2260     } else {
2261       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
2262       auto OrLHS =
2263           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
2264       auto OrRHS = MIRBuilder.buildLShr(
2265           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2266       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2267     }
2268   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
2269     if (Amt.ugt(VTBits)) {
2270       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2271     } else if (Amt.ugt(NVTBits)) {
2272       Lo = MIRBuilder.buildLShr(NVT, InH,
2273                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2274       Hi = MIRBuilder.buildConstant(NVT, 0);
2275     } else if (Amt == NVTBits) {
2276       Lo = InH;
2277       Hi = MIRBuilder.buildConstant(NVT, 0);
2278     } else {
2279       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2280 
2281       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2282       auto OrRHS = MIRBuilder.buildShl(
2283           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2284 
2285       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2286       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
2287     }
2288   } else {
2289     if (Amt.ugt(VTBits)) {
2290       Hi = Lo = MIRBuilder.buildAShr(
2291           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2292     } else if (Amt.ugt(NVTBits)) {
2293       Lo = MIRBuilder.buildAShr(NVT, InH,
2294                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2295       Hi = MIRBuilder.buildAShr(NVT, InH,
2296                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2297     } else if (Amt == NVTBits) {
2298       Lo = InH;
2299       Hi = MIRBuilder.buildAShr(NVT, InH,
2300                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2301     } else {
2302       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2303 
2304       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2305       auto OrRHS = MIRBuilder.buildShl(
2306           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2307 
2308       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2309       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
2310     }
2311   }
2312 
2313   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
2314   MI.eraseFromParent();
2315 
2316   return Legalized;
2317 }
2318 
2319 // TODO: Optimize if constant shift amount.
2320 LegalizerHelper::LegalizeResult
2321 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
2322                                    LLT RequestedTy) {
2323   if (TypeIdx == 1) {
2324     Observer.changingInstr(MI);
2325     narrowScalarSrc(MI, RequestedTy, 2);
2326     Observer.changedInstr(MI);
2327     return Legalized;
2328   }
2329 
2330   unsigned DstReg = MI.getOperand(0).getReg();
2331   LLT DstTy = MRI.getType(DstReg);
2332   if (DstTy.isVector())
2333     return UnableToLegalize;
2334 
2335   unsigned Amt = MI.getOperand(2).getReg();
2336   LLT ShiftAmtTy = MRI.getType(Amt);
2337   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
2338   if (DstEltSize % 2 != 0)
2339     return UnableToLegalize;
2340 
2341   // Ignore the input type. We can only go to exactly half the size of the
2342   // input. If that isn't small enough, the resulting pieces will be further
2343   // legalized.
2344   const unsigned NewBitSize = DstEltSize / 2;
2345   const LLT HalfTy = LLT::scalar(NewBitSize);
2346   const LLT CondTy = LLT::scalar(1);
2347 
2348   if (const MachineInstr *KShiftAmt =
2349           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
2350     return narrowScalarShiftByConstant(
2351         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
2352   }
2353 
2354   // TODO: Expand with known bits.
2355 
2356   // Handle the fully general expansion by an unknown amount.
2357   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
2358 
2359   unsigned InL = MRI.createGenericVirtualRegister(HalfTy);
2360   unsigned InH = MRI.createGenericVirtualRegister(HalfTy);
2361   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2362 
2363   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
2364   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
2365 
2366   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
2367   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
2368   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
2369 
2370   unsigned ResultRegs[2];
2371   switch (MI.getOpcode()) {
2372   case TargetOpcode::G_SHL: {
2373     // Short: ShAmt < NewBitSize
2374     auto LoS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2375 
2376     auto OrLHS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2377     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
2378     auto HiS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2379 
2380     // Long: ShAmt >= NewBitSize
2381     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
2382     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
2383 
2384     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
2385     auto Hi = MIRBuilder.buildSelect(
2386         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
2387 
2388     ResultRegs[0] = Lo.getReg(0);
2389     ResultRegs[1] = Hi.getReg(0);
2390     break;
2391   }
2392   case TargetOpcode::G_LSHR: {
2393     // Short: ShAmt < NewBitSize
2394     auto HiS = MIRBuilder.buildLShr(HalfTy, InH, Amt);
2395 
2396     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2397     auto OrRHS = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
2398     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2399 
2400     // Long: ShAmt >= NewBitSize
2401     auto HiL = MIRBuilder.buildConstant(HalfTy, 0);          // Hi part is zero.
2402     auto LoL = MIRBuilder.buildLShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2403 
2404     auto Lo = MIRBuilder.buildSelect(
2405         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2406     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2407 
2408     ResultRegs[0] = Lo.getReg(0);
2409     ResultRegs[1] = Hi.getReg(0);
2410     break;
2411   }
2412   case TargetOpcode::G_ASHR: {
2413     // Short: ShAmt < NewBitSize
2414     auto HiS = MIRBuilder.buildAShr(HalfTy, InH, Amt);
2415 
2416     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2417     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InH, AmtLack);
2418     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2419 
2420     // Long: ShAmt >= NewBitSize
2421 
2422     // Sign of Hi part.
2423     auto HiL = MIRBuilder.buildAShr(
2424         HalfTy, InH, MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1));
2425 
2426     auto LoL = MIRBuilder.buildAShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2427 
2428     auto Lo = MIRBuilder.buildSelect(
2429         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2430 
2431     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2432 
2433     ResultRegs[0] = Lo.getReg(0);
2434     ResultRegs[1] = Hi.getReg(0);
2435     break;
2436   }
2437   default:
2438     llvm_unreachable("not a shift");
2439   }
2440 
2441   MIRBuilder.buildMerge(DstReg, ResultRegs);
2442   MI.eraseFromParent();
2443   return Legalized;
2444 }
2445 
2446 LegalizerHelper::LegalizeResult
2447 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2448                                        LLT MoreTy) {
2449   assert(TypeIdx == 0 && "Expecting only Idx 0");
2450 
2451   Observer.changingInstr(MI);
2452   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2453     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2454     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2455     moreElementsVectorSrc(MI, MoreTy, I);
2456   }
2457 
2458   MachineBasicBlock &MBB = *MI.getParent();
2459   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
2460   moreElementsVectorDst(MI, MoreTy, 0);
2461   Observer.changedInstr(MI);
2462   return Legalized;
2463 }
2464 
2465 LegalizerHelper::LegalizeResult
2466 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
2467                                     LLT MoreTy) {
2468   MIRBuilder.setInstr(MI);
2469   unsigned Opc = MI.getOpcode();
2470   switch (Opc) {
2471   case TargetOpcode::G_IMPLICIT_DEF: {
2472     Observer.changingInstr(MI);
2473     moreElementsVectorDst(MI, MoreTy, 0);
2474     Observer.changedInstr(MI);
2475     return Legalized;
2476   }
2477   case TargetOpcode::G_AND:
2478   case TargetOpcode::G_OR:
2479   case TargetOpcode::G_XOR: {
2480     Observer.changingInstr(MI);
2481     moreElementsVectorSrc(MI, MoreTy, 1);
2482     moreElementsVectorSrc(MI, MoreTy, 2);
2483     moreElementsVectorDst(MI, MoreTy, 0);
2484     Observer.changedInstr(MI);
2485     return Legalized;
2486   }
2487   case TargetOpcode::G_EXTRACT:
2488     if (TypeIdx != 1)
2489       return UnableToLegalize;
2490     Observer.changingInstr(MI);
2491     moreElementsVectorSrc(MI, MoreTy, 1);
2492     Observer.changedInstr(MI);
2493     return Legalized;
2494   case TargetOpcode::G_INSERT:
2495     if (TypeIdx != 0)
2496       return UnableToLegalize;
2497     Observer.changingInstr(MI);
2498     moreElementsVectorSrc(MI, MoreTy, 1);
2499     moreElementsVectorDst(MI, MoreTy, 0);
2500     Observer.changedInstr(MI);
2501     return Legalized;
2502   case TargetOpcode::G_SELECT:
2503     if (TypeIdx != 0)
2504       return UnableToLegalize;
2505     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
2506       return UnableToLegalize;
2507 
2508     Observer.changingInstr(MI);
2509     moreElementsVectorSrc(MI, MoreTy, 2);
2510     moreElementsVectorSrc(MI, MoreTy, 3);
2511     moreElementsVectorDst(MI, MoreTy, 0);
2512     Observer.changedInstr(MI);
2513     return Legalized;
2514   case TargetOpcode::G_PHI:
2515     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
2516   default:
2517     return UnableToLegalize;
2518   }
2519 }
2520 
2521 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<unsigned> &DstRegs,
2522                                         ArrayRef<unsigned> Src1Regs,
2523                                         ArrayRef<unsigned> Src2Regs,
2524                                         LLT NarrowTy) {
2525   MachineIRBuilder &B = MIRBuilder;
2526   unsigned SrcParts = Src1Regs.size();
2527   unsigned DstParts = DstRegs.size();
2528 
2529   unsigned DstIdx = 0; // Low bits of the result.
2530   unsigned FactorSum =
2531       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
2532   DstRegs[DstIdx] = FactorSum;
2533 
2534   unsigned CarrySumPrevDstIdx;
2535   SmallVector<unsigned, 4> Factors;
2536 
2537   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
2538     // Collect low parts of muls for DstIdx.
2539     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
2540          i <= std::min(DstIdx, SrcParts - 1); ++i) {
2541       MachineInstrBuilder Mul =
2542           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
2543       Factors.push_back(Mul.getReg(0));
2544     }
2545     // Collect high parts of muls from previous DstIdx.
2546     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
2547          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
2548       MachineInstrBuilder Umulh =
2549           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
2550       Factors.push_back(Umulh.getReg(0));
2551     }
2552     // Add CarrySum from additons calculated for previous DstIdx.
2553     if (DstIdx != 1) {
2554       Factors.push_back(CarrySumPrevDstIdx);
2555     }
2556 
2557     unsigned CarrySum = 0;
2558     // Add all factors and accumulate all carries into CarrySum.
2559     if (DstIdx != DstParts - 1) {
2560       MachineInstrBuilder Uaddo =
2561           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
2562       FactorSum = Uaddo.getReg(0);
2563       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
2564       for (unsigned i = 2; i < Factors.size(); ++i) {
2565         MachineInstrBuilder Uaddo =
2566             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
2567         FactorSum = Uaddo.getReg(0);
2568         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
2569         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
2570       }
2571     } else {
2572       // Since value for the next index is not calculated, neither is CarrySum.
2573       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
2574       for (unsigned i = 2; i < Factors.size(); ++i)
2575         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
2576     }
2577 
2578     CarrySumPrevDstIdx = CarrySum;
2579     DstRegs[DstIdx] = FactorSum;
2580     Factors.clear();
2581   }
2582 }
2583 
2584 LegalizerHelper::LegalizeResult
2585 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
2586   unsigned DstReg = MI.getOperand(0).getReg();
2587   unsigned Src1 = MI.getOperand(1).getReg();
2588   unsigned Src2 = MI.getOperand(2).getReg();
2589 
2590   LLT Ty = MRI.getType(DstReg);
2591   if (Ty.isVector())
2592     return UnableToLegalize;
2593 
2594   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
2595   unsigned DstSize = Ty.getSizeInBits();
2596   unsigned NarrowSize = NarrowTy.getSizeInBits();
2597   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
2598     return UnableToLegalize;
2599 
2600   unsigned NumDstParts = DstSize / NarrowSize;
2601   unsigned NumSrcParts = SrcSize / NarrowSize;
2602   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
2603   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
2604 
2605   SmallVector<unsigned, 2> Src1Parts, Src2Parts, DstTmpRegs;
2606   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
2607   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
2608   DstTmpRegs.resize(DstTmpParts);
2609   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
2610 
2611   // Take only high half of registers if this is high mul.
2612   ArrayRef<unsigned> DstRegs(
2613       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
2614   MIRBuilder.buildMerge(DstReg, DstRegs);
2615   MI.eraseFromParent();
2616   return Legalized;
2617 }
2618 
2619 LegalizerHelper::LegalizeResult
2620 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
2621                                      LLT NarrowTy) {
2622   if (TypeIdx != 1)
2623     return UnableToLegalize;
2624 
2625   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2626 
2627   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2628   // FIXME: add support for when SizeOp1 isn't an exact multiple of
2629   // NarrowSize.
2630   if (SizeOp1 % NarrowSize != 0)
2631     return UnableToLegalize;
2632   int NumParts = SizeOp1 / NarrowSize;
2633 
2634   SmallVector<unsigned, 2> SrcRegs, DstRegs;
2635   SmallVector<uint64_t, 2> Indexes;
2636   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
2637 
2638   unsigned OpReg = MI.getOperand(0).getReg();
2639   uint64_t OpStart = MI.getOperand(2).getImm();
2640   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
2641   for (int i = 0; i < NumParts; ++i) {
2642     unsigned SrcStart = i * NarrowSize;
2643 
2644     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
2645       // No part of the extract uses this subregister, ignore it.
2646       continue;
2647     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
2648       // The entire subregister is extracted, forward the value.
2649       DstRegs.push_back(SrcRegs[i]);
2650       continue;
2651     }
2652 
2653     // OpSegStart is where this destination segment would start in OpReg if it
2654     // extended infinitely in both directions.
2655     int64_t ExtractOffset;
2656     uint64_t SegSize;
2657     if (OpStart < SrcStart) {
2658       ExtractOffset = 0;
2659       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
2660     } else {
2661       ExtractOffset = OpStart - SrcStart;
2662       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
2663     }
2664 
2665     unsigned SegReg = SrcRegs[i];
2666     if (ExtractOffset != 0 || SegSize != NarrowSize) {
2667       // A genuine extract is needed.
2668       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
2669       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
2670     }
2671 
2672     DstRegs.push_back(SegReg);
2673   }
2674 
2675   unsigned DstReg = MI.getOperand(0).getReg();
2676   if(MRI.getType(DstReg).isVector())
2677     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2678   else
2679     MIRBuilder.buildMerge(DstReg, DstRegs);
2680   MI.eraseFromParent();
2681   return Legalized;
2682 }
2683 
2684 LegalizerHelper::LegalizeResult
2685 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
2686                                     LLT NarrowTy) {
2687   // FIXME: Don't know how to handle secondary types yet.
2688   if (TypeIdx != 0)
2689     return UnableToLegalize;
2690 
2691   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2692   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2693 
2694   // FIXME: add support for when SizeOp0 isn't an exact multiple of
2695   // NarrowSize.
2696   if (SizeOp0 % NarrowSize != 0)
2697     return UnableToLegalize;
2698 
2699   int NumParts = SizeOp0 / NarrowSize;
2700 
2701   SmallVector<unsigned, 2> SrcRegs, DstRegs;
2702   SmallVector<uint64_t, 2> Indexes;
2703   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
2704 
2705   unsigned OpReg = MI.getOperand(2).getReg();
2706   uint64_t OpStart = MI.getOperand(3).getImm();
2707   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
2708   for (int i = 0; i < NumParts; ++i) {
2709     unsigned DstStart = i * NarrowSize;
2710 
2711     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
2712       // No part of the insert affects this subregister, forward the original.
2713       DstRegs.push_back(SrcRegs[i]);
2714       continue;
2715     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
2716       // The entire subregister is defined by this insert, forward the new
2717       // value.
2718       DstRegs.push_back(OpReg);
2719       continue;
2720     }
2721 
2722     // OpSegStart is where this destination segment would start in OpReg if it
2723     // extended infinitely in both directions.
2724     int64_t ExtractOffset, InsertOffset;
2725     uint64_t SegSize;
2726     if (OpStart < DstStart) {
2727       InsertOffset = 0;
2728       ExtractOffset = DstStart - OpStart;
2729       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
2730     } else {
2731       InsertOffset = OpStart - DstStart;
2732       ExtractOffset = 0;
2733       SegSize =
2734         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
2735     }
2736 
2737     unsigned SegReg = OpReg;
2738     if (ExtractOffset != 0 || SegSize != OpSize) {
2739       // A genuine extract is needed.
2740       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
2741       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
2742     }
2743 
2744     unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2745     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
2746     DstRegs.push_back(DstReg);
2747   }
2748 
2749   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
2750   unsigned DstReg = MI.getOperand(0).getReg();
2751   if(MRI.getType(DstReg).isVector())
2752     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2753   else
2754     MIRBuilder.buildMerge(DstReg, DstRegs);
2755   MI.eraseFromParent();
2756   return Legalized;
2757 }
2758 
2759 LegalizerHelper::LegalizeResult
2760 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
2761                                    LLT NarrowTy) {
2762   unsigned DstReg = MI.getOperand(0).getReg();
2763   LLT DstTy = MRI.getType(DstReg);
2764 
2765   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
2766 
2767   SmallVector<unsigned, 4> DstRegs, DstLeftoverRegs;
2768   SmallVector<unsigned, 4> Src0Regs, Src0LeftoverRegs;
2769   SmallVector<unsigned, 4> Src1Regs, Src1LeftoverRegs;
2770   LLT LeftoverTy;
2771   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
2772                     Src0Regs, Src0LeftoverRegs))
2773     return UnableToLegalize;
2774 
2775   LLT Unused;
2776   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
2777                     Src1Regs, Src1LeftoverRegs))
2778     llvm_unreachable("inconsistent extractParts result");
2779 
2780   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
2781     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
2782                                         {Src0Regs[I], Src1Regs[I]});
2783     DstRegs.push_back(Inst->getOperand(0).getReg());
2784   }
2785 
2786   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
2787     auto Inst = MIRBuilder.buildInstr(
2788       MI.getOpcode(),
2789       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
2790     DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
2791   }
2792 
2793   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
2794               LeftoverTy, DstLeftoverRegs);
2795 
2796   MI.eraseFromParent();
2797   return Legalized;
2798 }
2799 
2800 LegalizerHelper::LegalizeResult
2801 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
2802                                     LLT NarrowTy) {
2803   if (TypeIdx != 0)
2804     return UnableToLegalize;
2805 
2806   unsigned CondReg = MI.getOperand(1).getReg();
2807   LLT CondTy = MRI.getType(CondReg);
2808   if (CondTy.isVector()) // TODO: Handle vselect
2809     return UnableToLegalize;
2810 
2811   unsigned DstReg = MI.getOperand(0).getReg();
2812   LLT DstTy = MRI.getType(DstReg);
2813 
2814   SmallVector<unsigned, 4> DstRegs, DstLeftoverRegs;
2815   SmallVector<unsigned, 4> Src1Regs, Src1LeftoverRegs;
2816   SmallVector<unsigned, 4> Src2Regs, Src2LeftoverRegs;
2817   LLT LeftoverTy;
2818   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
2819                     Src1Regs, Src1LeftoverRegs))
2820     return UnableToLegalize;
2821 
2822   LLT Unused;
2823   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
2824                     Src2Regs, Src2LeftoverRegs))
2825     llvm_unreachable("inconsistent extractParts result");
2826 
2827   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
2828     auto Select = MIRBuilder.buildSelect(NarrowTy,
2829                                          CondReg, Src1Regs[I], Src2Regs[I]);
2830     DstRegs.push_back(Select->getOperand(0).getReg());
2831   }
2832 
2833   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
2834     auto Select = MIRBuilder.buildSelect(
2835       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
2836     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
2837   }
2838 
2839   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
2840               LeftoverTy, DstLeftoverRegs);
2841 
2842   MI.eraseFromParent();
2843   return Legalized;
2844 }
2845 
2846 LegalizerHelper::LegalizeResult
2847 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
2848   unsigned Opc = MI.getOpcode();
2849   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
2850   auto isSupported = [this](const LegalityQuery &Q) {
2851     auto QAction = LI.getAction(Q).Action;
2852     return QAction == Legal || QAction == Libcall || QAction == Custom;
2853   };
2854   switch (Opc) {
2855   default:
2856     return UnableToLegalize;
2857   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
2858     // This trivially expands to CTLZ.
2859     Observer.changingInstr(MI);
2860     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
2861     Observer.changedInstr(MI);
2862     return Legalized;
2863   }
2864   case TargetOpcode::G_CTLZ: {
2865     unsigned SrcReg = MI.getOperand(1).getReg();
2866     unsigned Len = Ty.getSizeInBits();
2867     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
2868       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
2869       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
2870                                              {Ty}, {SrcReg});
2871       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
2872       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
2873       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
2874                                           SrcReg, MIBZero);
2875       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
2876                              MIBCtlzZU);
2877       MI.eraseFromParent();
2878       return Legalized;
2879     }
2880     // for now, we do this:
2881     // NewLen = NextPowerOf2(Len);
2882     // x = x | (x >> 1);
2883     // x = x | (x >> 2);
2884     // ...
2885     // x = x | (x >>16);
2886     // x = x | (x >>32); // for 64-bit input
2887     // Upto NewLen/2
2888     // return Len - popcount(x);
2889     //
2890     // Ref: "Hacker's Delight" by Henry Warren
2891     unsigned Op = SrcReg;
2892     unsigned NewLen = PowerOf2Ceil(Len);
2893     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
2894       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
2895       auto MIBOp = MIRBuilder.buildInstr(
2896           TargetOpcode::G_OR, {Ty},
2897           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
2898                                      {Op, MIBShiftAmt})});
2899       Op = MIBOp->getOperand(0).getReg();
2900     }
2901     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
2902     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
2903                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
2904     MI.eraseFromParent();
2905     return Legalized;
2906   }
2907   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
2908     // This trivially expands to CTTZ.
2909     Observer.changingInstr(MI);
2910     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
2911     Observer.changedInstr(MI);
2912     return Legalized;
2913   }
2914   case TargetOpcode::G_CTTZ: {
2915     unsigned SrcReg = MI.getOperand(1).getReg();
2916     unsigned Len = Ty.getSizeInBits();
2917     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
2918       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
2919       // zero.
2920       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
2921                                              {Ty}, {SrcReg});
2922       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
2923       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
2924       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
2925                                           SrcReg, MIBZero);
2926       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
2927                              MIBCttzZU);
2928       MI.eraseFromParent();
2929       return Legalized;
2930     }
2931     // for now, we use: { return popcount(~x & (x - 1)); }
2932     // unless the target has ctlz but not ctpop, in which case we use:
2933     // { return 32 - nlz(~x & (x-1)); }
2934     // Ref: "Hacker's Delight" by Henry Warren
2935     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
2936     auto MIBNot =
2937         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
2938     auto MIBTmp = MIRBuilder.buildInstr(
2939         TargetOpcode::G_AND, {Ty},
2940         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
2941                                        {SrcReg, MIBCstNeg1})});
2942     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
2943         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
2944       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
2945       MIRBuilder.buildInstr(
2946           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
2947           {MIBCstLen,
2948            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
2949       MI.eraseFromParent();
2950       return Legalized;
2951     }
2952     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
2953     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
2954     return Legalized;
2955   }
2956   }
2957 }
2958