1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file This file implements the LegalizerHelper class to legalize 10 /// individual instructions and the LegalizeMachineIR wrapper pass for the 11 /// primary legalization. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 16 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 19 #include "llvm/CodeGen/GlobalISel/LostDebugLocObserver.h" 20 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" 21 #include "llvm/CodeGen/GlobalISel/Utils.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/TargetFrameLowering.h" 24 #include "llvm/CodeGen/TargetInstrInfo.h" 25 #include "llvm/CodeGen/TargetLowering.h" 26 #include "llvm/CodeGen/TargetOpcodes.h" 27 #include "llvm/CodeGen/TargetSubtargetInfo.h" 28 #include "llvm/IR/Instructions.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/MathExtras.h" 31 #include "llvm/Support/raw_ostream.h" 32 33 #define DEBUG_TYPE "legalizer" 34 35 using namespace llvm; 36 using namespace LegalizeActions; 37 using namespace MIPatternMatch; 38 39 /// Try to break down \p OrigTy into \p NarrowTy sized pieces. 40 /// 41 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy, 42 /// with any leftover piece as type \p LeftoverTy 43 /// 44 /// Returns -1 in the first element of the pair if the breakdown is not 45 /// satisfiable. 46 static std::pair<int, int> 47 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) { 48 assert(!LeftoverTy.isValid() && "this is an out argument"); 49 50 unsigned Size = OrigTy.getSizeInBits(); 51 unsigned NarrowSize = NarrowTy.getSizeInBits(); 52 unsigned NumParts = Size / NarrowSize; 53 unsigned LeftoverSize = Size - NumParts * NarrowSize; 54 assert(Size > NarrowSize); 55 56 if (LeftoverSize == 0) 57 return {NumParts, 0}; 58 59 if (NarrowTy.isVector()) { 60 unsigned EltSize = OrigTy.getScalarSizeInBits(); 61 if (LeftoverSize % EltSize != 0) 62 return {-1, -1}; 63 LeftoverTy = LLT::scalarOrVector( 64 ElementCount::getFixed(LeftoverSize / EltSize), EltSize); 65 } else { 66 LeftoverTy = LLT::scalar(LeftoverSize); 67 } 68 69 int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits(); 70 return std::make_pair(NumParts, NumLeftover); 71 } 72 73 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) { 74 75 if (!Ty.isScalar()) 76 return nullptr; 77 78 switch (Ty.getSizeInBits()) { 79 case 16: 80 return Type::getHalfTy(Ctx); 81 case 32: 82 return Type::getFloatTy(Ctx); 83 case 64: 84 return Type::getDoubleTy(Ctx); 85 case 80: 86 return Type::getX86_FP80Ty(Ctx); 87 case 128: 88 return Type::getFP128Ty(Ctx); 89 default: 90 return nullptr; 91 } 92 } 93 94 LegalizerHelper::LegalizerHelper(MachineFunction &MF, 95 GISelChangeObserver &Observer, 96 MachineIRBuilder &Builder) 97 : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()), 98 LI(*MF.getSubtarget().getLegalizerInfo()), 99 TLI(*MF.getSubtarget().getTargetLowering()) { } 100 101 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI, 102 GISelChangeObserver &Observer, 103 MachineIRBuilder &B) 104 : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI), 105 TLI(*MF.getSubtarget().getTargetLowering()) { } 106 107 LegalizerHelper::LegalizeResult 108 LegalizerHelper::legalizeInstrStep(MachineInstr &MI, 109 LostDebugLocObserver &LocObserver) { 110 LLVM_DEBUG(dbgs() << "Legalizing: " << MI); 111 112 MIRBuilder.setInstrAndDebugLoc(MI); 113 114 if (MI.getOpcode() == TargetOpcode::G_INTRINSIC || 115 MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS) 116 return LI.legalizeIntrinsic(*this, MI) ? Legalized : UnableToLegalize; 117 auto Step = LI.getAction(MI, MRI); 118 switch (Step.Action) { 119 case Legal: 120 LLVM_DEBUG(dbgs() << ".. Already legal\n"); 121 return AlreadyLegal; 122 case Libcall: 123 LLVM_DEBUG(dbgs() << ".. Convert to libcall\n"); 124 return libcall(MI, LocObserver); 125 case NarrowScalar: 126 LLVM_DEBUG(dbgs() << ".. Narrow scalar\n"); 127 return narrowScalar(MI, Step.TypeIdx, Step.NewType); 128 case WidenScalar: 129 LLVM_DEBUG(dbgs() << ".. Widen scalar\n"); 130 return widenScalar(MI, Step.TypeIdx, Step.NewType); 131 case Bitcast: 132 LLVM_DEBUG(dbgs() << ".. Bitcast type\n"); 133 return bitcast(MI, Step.TypeIdx, Step.NewType); 134 case Lower: 135 LLVM_DEBUG(dbgs() << ".. Lower\n"); 136 return lower(MI, Step.TypeIdx, Step.NewType); 137 case FewerElements: 138 LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n"); 139 return fewerElementsVector(MI, Step.TypeIdx, Step.NewType); 140 case MoreElements: 141 LLVM_DEBUG(dbgs() << ".. Increase number of elements\n"); 142 return moreElementsVector(MI, Step.TypeIdx, Step.NewType); 143 case Custom: 144 LLVM_DEBUG(dbgs() << ".. Custom legalization\n"); 145 return LI.legalizeCustom(*this, MI) ? Legalized : UnableToLegalize; 146 default: 147 LLVM_DEBUG(dbgs() << ".. Unable to legalize\n"); 148 return UnableToLegalize; 149 } 150 } 151 152 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts, 153 SmallVectorImpl<Register> &VRegs) { 154 for (int i = 0; i < NumParts; ++i) 155 VRegs.push_back(MRI.createGenericVirtualRegister(Ty)); 156 MIRBuilder.buildUnmerge(VRegs, Reg); 157 } 158 159 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, 160 LLT MainTy, LLT &LeftoverTy, 161 SmallVectorImpl<Register> &VRegs, 162 SmallVectorImpl<Register> &LeftoverRegs) { 163 assert(!LeftoverTy.isValid() && "this is an out argument"); 164 165 unsigned RegSize = RegTy.getSizeInBits(); 166 unsigned MainSize = MainTy.getSizeInBits(); 167 unsigned NumParts = RegSize / MainSize; 168 unsigned LeftoverSize = RegSize - NumParts * MainSize; 169 170 // Use an unmerge when possible. 171 if (LeftoverSize == 0) { 172 for (unsigned I = 0; I < NumParts; ++I) 173 VRegs.push_back(MRI.createGenericVirtualRegister(MainTy)); 174 MIRBuilder.buildUnmerge(VRegs, Reg); 175 return true; 176 } 177 178 if (MainTy.isVector()) { 179 unsigned EltSize = MainTy.getScalarSizeInBits(); 180 if (LeftoverSize % EltSize != 0) 181 return false; 182 LeftoverTy = LLT::scalarOrVector( 183 ElementCount::getFixed(LeftoverSize / EltSize), EltSize); 184 } else { 185 LeftoverTy = LLT::scalar(LeftoverSize); 186 } 187 188 // For irregular sizes, extract the individual parts. 189 for (unsigned I = 0; I != NumParts; ++I) { 190 Register NewReg = MRI.createGenericVirtualRegister(MainTy); 191 VRegs.push_back(NewReg); 192 MIRBuilder.buildExtract(NewReg, Reg, MainSize * I); 193 } 194 195 for (unsigned Offset = MainSize * NumParts; Offset < RegSize; 196 Offset += LeftoverSize) { 197 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy); 198 LeftoverRegs.push_back(NewReg); 199 MIRBuilder.buildExtract(NewReg, Reg, Offset); 200 } 201 202 return true; 203 } 204 205 void LegalizerHelper::insertParts(Register DstReg, 206 LLT ResultTy, LLT PartTy, 207 ArrayRef<Register> PartRegs, 208 LLT LeftoverTy, 209 ArrayRef<Register> LeftoverRegs) { 210 if (!LeftoverTy.isValid()) { 211 assert(LeftoverRegs.empty()); 212 213 if (!ResultTy.isVector()) { 214 MIRBuilder.buildMerge(DstReg, PartRegs); 215 return; 216 } 217 218 if (PartTy.isVector()) 219 MIRBuilder.buildConcatVectors(DstReg, PartRegs); 220 else 221 MIRBuilder.buildBuildVector(DstReg, PartRegs); 222 return; 223 } 224 225 SmallVector<Register> GCDRegs; 226 LLT GCDTy = getGCDType(getGCDType(ResultTy, LeftoverTy), PartTy); 227 for (auto PartReg : concat<const Register>(PartRegs, LeftoverRegs)) 228 extractGCDType(GCDRegs, GCDTy, PartReg); 229 LLT ResultLCMTy = buildLCMMergePieces(ResultTy, LeftoverTy, GCDTy, GCDRegs); 230 buildWidenedRemergeToDst(DstReg, ResultLCMTy, GCDRegs); 231 } 232 233 /// Append the result registers of G_UNMERGE_VALUES \p MI to \p Regs. 234 static void getUnmergeResults(SmallVectorImpl<Register> &Regs, 235 const MachineInstr &MI) { 236 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES); 237 238 const int StartIdx = Regs.size(); 239 const int NumResults = MI.getNumOperands() - 1; 240 Regs.resize(Regs.size() + NumResults); 241 for (int I = 0; I != NumResults; ++I) 242 Regs[StartIdx + I] = MI.getOperand(I).getReg(); 243 } 244 245 void LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, 246 LLT GCDTy, Register SrcReg) { 247 LLT SrcTy = MRI.getType(SrcReg); 248 if (SrcTy == GCDTy) { 249 // If the source already evenly divides the result type, we don't need to do 250 // anything. 251 Parts.push_back(SrcReg); 252 } else { 253 // Need to split into common type sized pieces. 254 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 255 getUnmergeResults(Parts, *Unmerge); 256 } 257 } 258 259 LLT LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy, 260 LLT NarrowTy, Register SrcReg) { 261 LLT SrcTy = MRI.getType(SrcReg); 262 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 263 extractGCDType(Parts, GCDTy, SrcReg); 264 return GCDTy; 265 } 266 267 LLT LegalizerHelper::buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy, 268 SmallVectorImpl<Register> &VRegs, 269 unsigned PadStrategy) { 270 LLT LCMTy = getLCMType(DstTy, NarrowTy); 271 272 int NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 273 int NumSubParts = NarrowTy.getSizeInBits() / GCDTy.getSizeInBits(); 274 int NumOrigSrc = VRegs.size(); 275 276 Register PadReg; 277 278 // Get a value we can use to pad the source value if the sources won't evenly 279 // cover the result type. 280 if (NumOrigSrc < NumParts * NumSubParts) { 281 if (PadStrategy == TargetOpcode::G_ZEXT) 282 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); 283 else if (PadStrategy == TargetOpcode::G_ANYEXT) 284 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 285 else { 286 assert(PadStrategy == TargetOpcode::G_SEXT); 287 288 // Shift the sign bit of the low register through the high register. 289 auto ShiftAmt = 290 MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1); 291 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0); 292 } 293 } 294 295 // Registers for the final merge to be produced. 296 SmallVector<Register, 4> Remerge(NumParts); 297 298 // Registers needed for intermediate merges, which will be merged into a 299 // source for Remerge. 300 SmallVector<Register, 4> SubMerge(NumSubParts); 301 302 // Once we've fully read off the end of the original source bits, we can reuse 303 // the same high bits for remaining padding elements. 304 Register AllPadReg; 305 306 // Build merges to the LCM type to cover the original result type. 307 for (int I = 0; I != NumParts; ++I) { 308 bool AllMergePartsArePadding = true; 309 310 // Build the requested merges to the requested type. 311 for (int J = 0; J != NumSubParts; ++J) { 312 int Idx = I * NumSubParts + J; 313 if (Idx >= NumOrigSrc) { 314 SubMerge[J] = PadReg; 315 continue; 316 } 317 318 SubMerge[J] = VRegs[Idx]; 319 320 // There are meaningful bits here we can't reuse later. 321 AllMergePartsArePadding = false; 322 } 323 324 // If we've filled up a complete piece with padding bits, we can directly 325 // emit the natural sized constant if applicable, rather than a merge of 326 // smaller constants. 327 if (AllMergePartsArePadding && !AllPadReg) { 328 if (PadStrategy == TargetOpcode::G_ANYEXT) 329 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); 330 else if (PadStrategy == TargetOpcode::G_ZEXT) 331 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); 332 333 // If this is a sign extension, we can't materialize a trivial constant 334 // with the right type and have to produce a merge. 335 } 336 337 if (AllPadReg) { 338 // Avoid creating additional instructions if we're just adding additional 339 // copies of padding bits. 340 Remerge[I] = AllPadReg; 341 continue; 342 } 343 344 if (NumSubParts == 1) 345 Remerge[I] = SubMerge[0]; 346 else 347 Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0); 348 349 // In the sign extend padding case, re-use the first all-signbit merge. 350 if (AllMergePartsArePadding && !AllPadReg) 351 AllPadReg = Remerge[I]; 352 } 353 354 VRegs = std::move(Remerge); 355 return LCMTy; 356 } 357 358 void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy, 359 ArrayRef<Register> RemergeRegs) { 360 LLT DstTy = MRI.getType(DstReg); 361 362 // Create the merge to the widened source, and extract the relevant bits into 363 // the result. 364 365 if (DstTy == LCMTy) { 366 MIRBuilder.buildMerge(DstReg, RemergeRegs); 367 return; 368 } 369 370 auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs); 371 if (DstTy.isScalar() && LCMTy.isScalar()) { 372 MIRBuilder.buildTrunc(DstReg, Remerge); 373 return; 374 } 375 376 if (LCMTy.isVector()) { 377 unsigned NumDefs = LCMTy.getSizeInBits() / DstTy.getSizeInBits(); 378 SmallVector<Register, 8> UnmergeDefs(NumDefs); 379 UnmergeDefs[0] = DstReg; 380 for (unsigned I = 1; I != NumDefs; ++I) 381 UnmergeDefs[I] = MRI.createGenericVirtualRegister(DstTy); 382 383 MIRBuilder.buildUnmerge(UnmergeDefs, 384 MIRBuilder.buildMerge(LCMTy, RemergeRegs)); 385 return; 386 } 387 388 llvm_unreachable("unhandled case"); 389 } 390 391 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) { 392 #define RTLIBCASE_INT(LibcallPrefix) \ 393 do { \ 394 switch (Size) { \ 395 case 32: \ 396 return RTLIB::LibcallPrefix##32; \ 397 case 64: \ 398 return RTLIB::LibcallPrefix##64; \ 399 case 128: \ 400 return RTLIB::LibcallPrefix##128; \ 401 default: \ 402 llvm_unreachable("unexpected size"); \ 403 } \ 404 } while (0) 405 406 #define RTLIBCASE(LibcallPrefix) \ 407 do { \ 408 switch (Size) { \ 409 case 32: \ 410 return RTLIB::LibcallPrefix##32; \ 411 case 64: \ 412 return RTLIB::LibcallPrefix##64; \ 413 case 80: \ 414 return RTLIB::LibcallPrefix##80; \ 415 case 128: \ 416 return RTLIB::LibcallPrefix##128; \ 417 default: \ 418 llvm_unreachable("unexpected size"); \ 419 } \ 420 } while (0) 421 422 switch (Opcode) { 423 case TargetOpcode::G_SDIV: 424 RTLIBCASE_INT(SDIV_I); 425 case TargetOpcode::G_UDIV: 426 RTLIBCASE_INT(UDIV_I); 427 case TargetOpcode::G_SREM: 428 RTLIBCASE_INT(SREM_I); 429 case TargetOpcode::G_UREM: 430 RTLIBCASE_INT(UREM_I); 431 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 432 RTLIBCASE_INT(CTLZ_I); 433 case TargetOpcode::G_FADD: 434 RTLIBCASE(ADD_F); 435 case TargetOpcode::G_FSUB: 436 RTLIBCASE(SUB_F); 437 case TargetOpcode::G_FMUL: 438 RTLIBCASE(MUL_F); 439 case TargetOpcode::G_FDIV: 440 RTLIBCASE(DIV_F); 441 case TargetOpcode::G_FEXP: 442 RTLIBCASE(EXP_F); 443 case TargetOpcode::G_FEXP2: 444 RTLIBCASE(EXP2_F); 445 case TargetOpcode::G_FREM: 446 RTLIBCASE(REM_F); 447 case TargetOpcode::G_FPOW: 448 RTLIBCASE(POW_F); 449 case TargetOpcode::G_FMA: 450 RTLIBCASE(FMA_F); 451 case TargetOpcode::G_FSIN: 452 RTLIBCASE(SIN_F); 453 case TargetOpcode::G_FCOS: 454 RTLIBCASE(COS_F); 455 case TargetOpcode::G_FLOG10: 456 RTLIBCASE(LOG10_F); 457 case TargetOpcode::G_FLOG: 458 RTLIBCASE(LOG_F); 459 case TargetOpcode::G_FLOG2: 460 RTLIBCASE(LOG2_F); 461 case TargetOpcode::G_FCEIL: 462 RTLIBCASE(CEIL_F); 463 case TargetOpcode::G_FFLOOR: 464 RTLIBCASE(FLOOR_F); 465 case TargetOpcode::G_FMINNUM: 466 RTLIBCASE(FMIN_F); 467 case TargetOpcode::G_FMAXNUM: 468 RTLIBCASE(FMAX_F); 469 case TargetOpcode::G_FSQRT: 470 RTLIBCASE(SQRT_F); 471 case TargetOpcode::G_FRINT: 472 RTLIBCASE(RINT_F); 473 case TargetOpcode::G_FNEARBYINT: 474 RTLIBCASE(NEARBYINT_F); 475 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 476 RTLIBCASE(ROUNDEVEN_F); 477 } 478 llvm_unreachable("Unknown libcall function"); 479 } 480 481 /// True if an instruction is in tail position in its caller. Intended for 482 /// legalizing libcalls as tail calls when possible. 483 static bool isLibCallInTailPosition(const TargetInstrInfo &TII, 484 MachineInstr &MI) { 485 MachineBasicBlock &MBB = *MI.getParent(); 486 const Function &F = MBB.getParent()->getFunction(); 487 488 // Conservatively require the attributes of the call to match those of 489 // the return. Ignore NoAlias and NonNull because they don't affect the 490 // call sequence. 491 AttributeList CallerAttrs = F.getAttributes(); 492 if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex) 493 .removeAttribute(Attribute::NoAlias) 494 .removeAttribute(Attribute::NonNull) 495 .hasAttributes()) 496 return false; 497 498 // It's not safe to eliminate the sign / zero extension of the return value. 499 if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) || 500 CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 501 return false; 502 503 // Only tail call if the following instruction is a standard return. 504 auto Next = next_nodbg(MI.getIterator(), MBB.instr_end()); 505 if (Next == MBB.instr_end() || TII.isTailCall(*Next) || !Next->isReturn()) 506 return false; 507 508 return true; 509 } 510 511 LegalizerHelper::LegalizeResult 512 llvm::createLibcall(MachineIRBuilder &MIRBuilder, const char *Name, 513 const CallLowering::ArgInfo &Result, 514 ArrayRef<CallLowering::ArgInfo> Args, 515 const CallingConv::ID CC) { 516 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 517 518 CallLowering::CallLoweringInfo Info; 519 Info.CallConv = CC; 520 Info.Callee = MachineOperand::CreateES(Name); 521 Info.OrigRet = Result; 522 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 523 if (!CLI.lowerCall(MIRBuilder, Info)) 524 return LegalizerHelper::UnableToLegalize; 525 526 return LegalizerHelper::Legalized; 527 } 528 529 LegalizerHelper::LegalizeResult 530 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall, 531 const CallLowering::ArgInfo &Result, 532 ArrayRef<CallLowering::ArgInfo> Args) { 533 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 534 const char *Name = TLI.getLibcallName(Libcall); 535 const CallingConv::ID CC = TLI.getLibcallCallingConv(Libcall); 536 return createLibcall(MIRBuilder, Name, Result, Args, CC); 537 } 538 539 // Useful for libcalls where all operands have the same type. 540 static LegalizerHelper::LegalizeResult 541 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size, 542 Type *OpType) { 543 auto Libcall = getRTLibDesc(MI.getOpcode(), Size); 544 545 // FIXME: What does the original arg index mean here? 546 SmallVector<CallLowering::ArgInfo, 3> Args; 547 for (unsigned i = 1; i < MI.getNumOperands(); i++) 548 Args.push_back({MI.getOperand(i).getReg(), OpType, 0}); 549 return createLibcall(MIRBuilder, Libcall, 550 {MI.getOperand(0).getReg(), OpType, 0}, Args); 551 } 552 553 LegalizerHelper::LegalizeResult 554 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 555 MachineInstr &MI, LostDebugLocObserver &LocObserver) { 556 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 557 558 SmallVector<CallLowering::ArgInfo, 3> Args; 559 // Add all the args, except for the last which is an imm denoting 'tail'. 560 for (unsigned i = 0; i < MI.getNumOperands() - 1; ++i) { 561 Register Reg = MI.getOperand(i).getReg(); 562 563 // Need derive an IR type for call lowering. 564 LLT OpLLT = MRI.getType(Reg); 565 Type *OpTy = nullptr; 566 if (OpLLT.isPointer()) 567 OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace()); 568 else 569 OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits()); 570 Args.push_back({Reg, OpTy, 0}); 571 } 572 573 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 574 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 575 RTLIB::Libcall RTLibcall; 576 unsigned Opc = MI.getOpcode(); 577 switch (Opc) { 578 case TargetOpcode::G_BZERO: 579 RTLibcall = RTLIB::BZERO; 580 break; 581 case TargetOpcode::G_MEMCPY: 582 RTLibcall = RTLIB::MEMCPY; 583 break; 584 case TargetOpcode::G_MEMMOVE: 585 RTLibcall = RTLIB::MEMMOVE; 586 break; 587 case TargetOpcode::G_MEMSET: 588 RTLibcall = RTLIB::MEMSET; 589 break; 590 default: 591 return LegalizerHelper::UnableToLegalize; 592 } 593 const char *Name = TLI.getLibcallName(RTLibcall); 594 595 // Unsupported libcall on the target. 596 if (!Name) { 597 LLVM_DEBUG(dbgs() << ".. .. Could not find libcall name for " 598 << MIRBuilder.getTII().getName(Opc) << "\n"); 599 return LegalizerHelper::UnableToLegalize; 600 } 601 602 CallLowering::CallLoweringInfo Info; 603 Info.CallConv = TLI.getLibcallCallingConv(RTLibcall); 604 Info.Callee = MachineOperand::CreateES(Name); 605 Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx), 0); 606 Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() && 607 isLibCallInTailPosition(MIRBuilder.getTII(), MI); 608 609 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 610 if (!CLI.lowerCall(MIRBuilder, Info)) 611 return LegalizerHelper::UnableToLegalize; 612 613 614 if (Info.LoweredTailCall) { 615 assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?"); 616 617 // Check debug locations before removing the return. 618 LocObserver.checkpoint(true); 619 620 // We must have a return following the call (or debug insts) to get past 621 // isLibCallInTailPosition. 622 do { 623 MachineInstr *Next = MI.getNextNode(); 624 assert(Next && (Next->isReturn() || Next->isDebugInstr()) && 625 "Expected instr following MI to be return or debug inst?"); 626 // We lowered a tail call, so the call is now the return from the block. 627 // Delete the old return. 628 Next->eraseFromParent(); 629 } while (MI.getNextNode()); 630 631 // We expect to lose the debug location from the return. 632 LocObserver.checkpoint(false); 633 } 634 635 return LegalizerHelper::Legalized; 636 } 637 638 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType, 639 Type *FromType) { 640 auto ToMVT = MVT::getVT(ToType); 641 auto FromMVT = MVT::getVT(FromType); 642 643 switch (Opcode) { 644 case TargetOpcode::G_FPEXT: 645 return RTLIB::getFPEXT(FromMVT, ToMVT); 646 case TargetOpcode::G_FPTRUNC: 647 return RTLIB::getFPROUND(FromMVT, ToMVT); 648 case TargetOpcode::G_FPTOSI: 649 return RTLIB::getFPTOSINT(FromMVT, ToMVT); 650 case TargetOpcode::G_FPTOUI: 651 return RTLIB::getFPTOUINT(FromMVT, ToMVT); 652 case TargetOpcode::G_SITOFP: 653 return RTLIB::getSINTTOFP(FromMVT, ToMVT); 654 case TargetOpcode::G_UITOFP: 655 return RTLIB::getUINTTOFP(FromMVT, ToMVT); 656 } 657 llvm_unreachable("Unsupported libcall function"); 658 } 659 660 static LegalizerHelper::LegalizeResult 661 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType, 662 Type *FromType) { 663 RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType); 664 return createLibcall(MIRBuilder, Libcall, 665 {MI.getOperand(0).getReg(), ToType, 0}, 666 {{MI.getOperand(1).getReg(), FromType, 0}}); 667 } 668 669 LegalizerHelper::LegalizeResult 670 LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) { 671 LLT LLTy = MRI.getType(MI.getOperand(0).getReg()); 672 unsigned Size = LLTy.getSizeInBits(); 673 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 674 675 switch (MI.getOpcode()) { 676 default: 677 return UnableToLegalize; 678 case TargetOpcode::G_SDIV: 679 case TargetOpcode::G_UDIV: 680 case TargetOpcode::G_SREM: 681 case TargetOpcode::G_UREM: 682 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 683 Type *HLTy = IntegerType::get(Ctx, Size); 684 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 685 if (Status != Legalized) 686 return Status; 687 break; 688 } 689 case TargetOpcode::G_FADD: 690 case TargetOpcode::G_FSUB: 691 case TargetOpcode::G_FMUL: 692 case TargetOpcode::G_FDIV: 693 case TargetOpcode::G_FMA: 694 case TargetOpcode::G_FPOW: 695 case TargetOpcode::G_FREM: 696 case TargetOpcode::G_FCOS: 697 case TargetOpcode::G_FSIN: 698 case TargetOpcode::G_FLOG10: 699 case TargetOpcode::G_FLOG: 700 case TargetOpcode::G_FLOG2: 701 case TargetOpcode::G_FEXP: 702 case TargetOpcode::G_FEXP2: 703 case TargetOpcode::G_FCEIL: 704 case TargetOpcode::G_FFLOOR: 705 case TargetOpcode::G_FMINNUM: 706 case TargetOpcode::G_FMAXNUM: 707 case TargetOpcode::G_FSQRT: 708 case TargetOpcode::G_FRINT: 709 case TargetOpcode::G_FNEARBYINT: 710 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 711 Type *HLTy = getFloatTypeForLLT(Ctx, LLTy); 712 if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) { 713 LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n"); 714 return UnableToLegalize; 715 } 716 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 717 if (Status != Legalized) 718 return Status; 719 break; 720 } 721 case TargetOpcode::G_FPEXT: 722 case TargetOpcode::G_FPTRUNC: { 723 Type *FromTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(1).getReg())); 724 Type *ToTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(0).getReg())); 725 if (!FromTy || !ToTy) 726 return UnableToLegalize; 727 LegalizeResult Status = conversionLibcall(MI, MIRBuilder, ToTy, FromTy ); 728 if (Status != Legalized) 729 return Status; 730 break; 731 } 732 case TargetOpcode::G_FPTOSI: 733 case TargetOpcode::G_FPTOUI: { 734 // FIXME: Support other types 735 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 736 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 737 if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64)) 738 return UnableToLegalize; 739 LegalizeResult Status = conversionLibcall( 740 MI, MIRBuilder, 741 ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx), 742 FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx)); 743 if (Status != Legalized) 744 return Status; 745 break; 746 } 747 case TargetOpcode::G_SITOFP: 748 case TargetOpcode::G_UITOFP: { 749 // FIXME: Support other types 750 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 751 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 752 if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64)) 753 return UnableToLegalize; 754 LegalizeResult Status = conversionLibcall( 755 MI, MIRBuilder, 756 ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx), 757 FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx)); 758 if (Status != Legalized) 759 return Status; 760 break; 761 } 762 case TargetOpcode::G_BZERO: 763 case TargetOpcode::G_MEMCPY: 764 case TargetOpcode::G_MEMMOVE: 765 case TargetOpcode::G_MEMSET: { 766 LegalizeResult Result = 767 createMemLibcall(MIRBuilder, *MIRBuilder.getMRI(), MI, LocObserver); 768 if (Result != Legalized) 769 return Result; 770 MI.eraseFromParent(); 771 return Result; 772 } 773 } 774 775 MI.eraseFromParent(); 776 return Legalized; 777 } 778 779 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, 780 unsigned TypeIdx, 781 LLT NarrowTy) { 782 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 783 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 784 785 switch (MI.getOpcode()) { 786 default: 787 return UnableToLegalize; 788 case TargetOpcode::G_IMPLICIT_DEF: { 789 Register DstReg = MI.getOperand(0).getReg(); 790 LLT DstTy = MRI.getType(DstReg); 791 792 // If SizeOp0 is not an exact multiple of NarrowSize, emit 793 // G_ANYEXT(G_IMPLICIT_DEF). Cast result to vector if needed. 794 // FIXME: Although this would also be legal for the general case, it causes 795 // a lot of regressions in the emitted code (superfluous COPYs, artifact 796 // combines not being hit). This seems to be a problem related to the 797 // artifact combiner. 798 if (SizeOp0 % NarrowSize != 0) { 799 LLT ImplicitTy = NarrowTy; 800 if (DstTy.isVector()) 801 ImplicitTy = LLT::vector(DstTy.getElementCount(), ImplicitTy); 802 803 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); 804 MIRBuilder.buildAnyExt(DstReg, ImplicitReg); 805 806 MI.eraseFromParent(); 807 return Legalized; 808 } 809 810 int NumParts = SizeOp0 / NarrowSize; 811 812 SmallVector<Register, 2> DstRegs; 813 for (int i = 0; i < NumParts; ++i) 814 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); 815 816 if (DstTy.isVector()) 817 MIRBuilder.buildBuildVector(DstReg, DstRegs); 818 else 819 MIRBuilder.buildMerge(DstReg, DstRegs); 820 MI.eraseFromParent(); 821 return Legalized; 822 } 823 case TargetOpcode::G_CONSTANT: { 824 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 825 const APInt &Val = MI.getOperand(1).getCImm()->getValue(); 826 unsigned TotalSize = Ty.getSizeInBits(); 827 unsigned NarrowSize = NarrowTy.getSizeInBits(); 828 int NumParts = TotalSize / NarrowSize; 829 830 SmallVector<Register, 4> PartRegs; 831 for (int I = 0; I != NumParts; ++I) { 832 unsigned Offset = I * NarrowSize; 833 auto K = MIRBuilder.buildConstant(NarrowTy, 834 Val.lshr(Offset).trunc(NarrowSize)); 835 PartRegs.push_back(K.getReg(0)); 836 } 837 838 LLT LeftoverTy; 839 unsigned LeftoverBits = TotalSize - NumParts * NarrowSize; 840 SmallVector<Register, 1> LeftoverRegs; 841 if (LeftoverBits != 0) { 842 LeftoverTy = LLT::scalar(LeftoverBits); 843 auto K = MIRBuilder.buildConstant( 844 LeftoverTy, 845 Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits)); 846 LeftoverRegs.push_back(K.getReg(0)); 847 } 848 849 insertParts(MI.getOperand(0).getReg(), 850 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs); 851 852 MI.eraseFromParent(); 853 return Legalized; 854 } 855 case TargetOpcode::G_SEXT: 856 case TargetOpcode::G_ZEXT: 857 case TargetOpcode::G_ANYEXT: 858 return narrowScalarExt(MI, TypeIdx, NarrowTy); 859 case TargetOpcode::G_TRUNC: { 860 if (TypeIdx != 1) 861 return UnableToLegalize; 862 863 uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 864 if (NarrowTy.getSizeInBits() * 2 != SizeOp1) { 865 LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n"); 866 return UnableToLegalize; 867 } 868 869 auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 870 MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0)); 871 MI.eraseFromParent(); 872 return Legalized; 873 } 874 875 case TargetOpcode::G_FREEZE: 876 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 877 case TargetOpcode::G_ADD: 878 case TargetOpcode::G_SUB: 879 case TargetOpcode::G_SADDO: 880 case TargetOpcode::G_SSUBO: 881 case TargetOpcode::G_SADDE: 882 case TargetOpcode::G_SSUBE: 883 case TargetOpcode::G_UADDO: 884 case TargetOpcode::G_USUBO: 885 case TargetOpcode::G_UADDE: 886 case TargetOpcode::G_USUBE: 887 return narrowScalarAddSub(MI, TypeIdx, NarrowTy); 888 case TargetOpcode::G_MUL: 889 case TargetOpcode::G_UMULH: 890 return narrowScalarMul(MI, NarrowTy); 891 case TargetOpcode::G_EXTRACT: 892 return narrowScalarExtract(MI, TypeIdx, NarrowTy); 893 case TargetOpcode::G_INSERT: 894 return narrowScalarInsert(MI, TypeIdx, NarrowTy); 895 case TargetOpcode::G_LOAD: { 896 auto &MMO = **MI.memoperands_begin(); 897 Register DstReg = MI.getOperand(0).getReg(); 898 LLT DstTy = MRI.getType(DstReg); 899 if (DstTy.isVector()) 900 return UnableToLegalize; 901 902 if (8 * MMO.getSize() != DstTy.getSizeInBits()) { 903 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 904 MIRBuilder.buildLoad(TmpReg, MI.getOperand(1), MMO); 905 MIRBuilder.buildAnyExt(DstReg, TmpReg); 906 MI.eraseFromParent(); 907 return Legalized; 908 } 909 910 return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy); 911 } 912 case TargetOpcode::G_ZEXTLOAD: 913 case TargetOpcode::G_SEXTLOAD: { 914 bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD; 915 Register DstReg = MI.getOperand(0).getReg(); 916 Register PtrReg = MI.getOperand(1).getReg(); 917 918 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 919 auto &MMO = **MI.memoperands_begin(); 920 unsigned MemSize = MMO.getSizeInBits(); 921 922 if (MemSize == NarrowSize) { 923 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); 924 } else if (MemSize < NarrowSize) { 925 MIRBuilder.buildLoadInstr(MI.getOpcode(), TmpReg, PtrReg, MMO); 926 } else if (MemSize > NarrowSize) { 927 // FIXME: Need to split the load. 928 return UnableToLegalize; 929 } 930 931 if (ZExt) 932 MIRBuilder.buildZExt(DstReg, TmpReg); 933 else 934 MIRBuilder.buildSExt(DstReg, TmpReg); 935 936 MI.eraseFromParent(); 937 return Legalized; 938 } 939 case TargetOpcode::G_STORE: { 940 const auto &MMO = **MI.memoperands_begin(); 941 942 Register SrcReg = MI.getOperand(0).getReg(); 943 LLT SrcTy = MRI.getType(SrcReg); 944 if (SrcTy.isVector()) 945 return UnableToLegalize; 946 947 int NumParts = SizeOp0 / NarrowSize; 948 unsigned HandledSize = NumParts * NarrowTy.getSizeInBits(); 949 unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize; 950 if (SrcTy.isVector() && LeftoverBits != 0) 951 return UnableToLegalize; 952 953 if (8 * MMO.getSize() != SrcTy.getSizeInBits()) { 954 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 955 auto &MMO = **MI.memoperands_begin(); 956 MIRBuilder.buildTrunc(TmpReg, SrcReg); 957 MIRBuilder.buildStore(TmpReg, MI.getOperand(1), MMO); 958 MI.eraseFromParent(); 959 return Legalized; 960 } 961 962 return reduceLoadStoreWidth(MI, 0, NarrowTy); 963 } 964 case TargetOpcode::G_SELECT: 965 return narrowScalarSelect(MI, TypeIdx, NarrowTy); 966 case TargetOpcode::G_AND: 967 case TargetOpcode::G_OR: 968 case TargetOpcode::G_XOR: { 969 // Legalize bitwise operation: 970 // A = BinOp<Ty> B, C 971 // into: 972 // B1, ..., BN = G_UNMERGE_VALUES B 973 // C1, ..., CN = G_UNMERGE_VALUES C 974 // A1 = BinOp<Ty/N> B1, C2 975 // ... 976 // AN = BinOp<Ty/N> BN, CN 977 // A = G_MERGE_VALUES A1, ..., AN 978 return narrowScalarBasic(MI, TypeIdx, NarrowTy); 979 } 980 case TargetOpcode::G_SHL: 981 case TargetOpcode::G_LSHR: 982 case TargetOpcode::G_ASHR: 983 return narrowScalarShift(MI, TypeIdx, NarrowTy); 984 case TargetOpcode::G_CTLZ: 985 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 986 case TargetOpcode::G_CTTZ: 987 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 988 case TargetOpcode::G_CTPOP: 989 if (TypeIdx == 1) 990 switch (MI.getOpcode()) { 991 case TargetOpcode::G_CTLZ: 992 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 993 return narrowScalarCTLZ(MI, TypeIdx, NarrowTy); 994 case TargetOpcode::G_CTTZ: 995 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 996 return narrowScalarCTTZ(MI, TypeIdx, NarrowTy); 997 case TargetOpcode::G_CTPOP: 998 return narrowScalarCTPOP(MI, TypeIdx, NarrowTy); 999 default: 1000 return UnableToLegalize; 1001 } 1002 1003 Observer.changingInstr(MI); 1004 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1005 Observer.changedInstr(MI); 1006 return Legalized; 1007 case TargetOpcode::G_INTTOPTR: 1008 if (TypeIdx != 1) 1009 return UnableToLegalize; 1010 1011 Observer.changingInstr(MI); 1012 narrowScalarSrc(MI, NarrowTy, 1); 1013 Observer.changedInstr(MI); 1014 return Legalized; 1015 case TargetOpcode::G_PTRTOINT: 1016 if (TypeIdx != 0) 1017 return UnableToLegalize; 1018 1019 Observer.changingInstr(MI); 1020 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1021 Observer.changedInstr(MI); 1022 return Legalized; 1023 case TargetOpcode::G_PHI: { 1024 // FIXME: add support for when SizeOp0 isn't an exact multiple of 1025 // NarrowSize. 1026 if (SizeOp0 % NarrowSize != 0) 1027 return UnableToLegalize; 1028 1029 unsigned NumParts = SizeOp0 / NarrowSize; 1030 SmallVector<Register, 2> DstRegs(NumParts); 1031 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2); 1032 Observer.changingInstr(MI); 1033 for (unsigned i = 1; i < MI.getNumOperands(); i += 2) { 1034 MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB(); 1035 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 1036 extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts, 1037 SrcRegs[i / 2]); 1038 } 1039 MachineBasicBlock &MBB = *MI.getParent(); 1040 MIRBuilder.setInsertPt(MBB, MI); 1041 for (unsigned i = 0; i < NumParts; ++i) { 1042 DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy); 1043 MachineInstrBuilder MIB = 1044 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); 1045 for (unsigned j = 1; j < MI.getNumOperands(); j += 2) 1046 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); 1047 } 1048 MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI()); 1049 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1050 Observer.changedInstr(MI); 1051 MI.eraseFromParent(); 1052 return Legalized; 1053 } 1054 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 1055 case TargetOpcode::G_INSERT_VECTOR_ELT: { 1056 if (TypeIdx != 2) 1057 return UnableToLegalize; 1058 1059 int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3; 1060 Observer.changingInstr(MI); 1061 narrowScalarSrc(MI, NarrowTy, OpIdx); 1062 Observer.changedInstr(MI); 1063 return Legalized; 1064 } 1065 case TargetOpcode::G_ICMP: { 1066 uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); 1067 if (NarrowSize * 2 != SrcSize) 1068 return UnableToLegalize; 1069 1070 Observer.changingInstr(MI); 1071 Register LHSL = MRI.createGenericVirtualRegister(NarrowTy); 1072 Register LHSH = MRI.createGenericVirtualRegister(NarrowTy); 1073 MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2)); 1074 1075 Register RHSL = MRI.createGenericVirtualRegister(NarrowTy); 1076 Register RHSH = MRI.createGenericVirtualRegister(NarrowTy); 1077 MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3)); 1078 1079 CmpInst::Predicate Pred = 1080 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 1081 LLT ResTy = MRI.getType(MI.getOperand(0).getReg()); 1082 1083 if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) { 1084 MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL); 1085 MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH); 1086 MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH); 1087 MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0); 1088 MIRBuilder.buildICmp(Pred, MI.getOperand(0), Or, Zero); 1089 } else { 1090 MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH); 1091 MachineInstrBuilder CmpHEQ = 1092 MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH); 1093 MachineInstrBuilder CmpLU = MIRBuilder.buildICmp( 1094 ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL); 1095 MIRBuilder.buildSelect(MI.getOperand(0), CmpHEQ, CmpLU, CmpH); 1096 } 1097 Observer.changedInstr(MI); 1098 MI.eraseFromParent(); 1099 return Legalized; 1100 } 1101 case TargetOpcode::G_SEXT_INREG: { 1102 if (TypeIdx != 0) 1103 return UnableToLegalize; 1104 1105 int64_t SizeInBits = MI.getOperand(2).getImm(); 1106 1107 // So long as the new type has more bits than the bits we're extending we 1108 // don't need to break it apart. 1109 if (NarrowTy.getScalarSizeInBits() >= SizeInBits) { 1110 Observer.changingInstr(MI); 1111 // We don't lose any non-extension bits by truncating the src and 1112 // sign-extending the dst. 1113 MachineOperand &MO1 = MI.getOperand(1); 1114 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1); 1115 MO1.setReg(TruncMIB.getReg(0)); 1116 1117 MachineOperand &MO2 = MI.getOperand(0); 1118 Register DstExt = MRI.createGenericVirtualRegister(NarrowTy); 1119 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1120 MIRBuilder.buildSExt(MO2, DstExt); 1121 MO2.setReg(DstExt); 1122 Observer.changedInstr(MI); 1123 return Legalized; 1124 } 1125 1126 // Break it apart. Components below the extension point are unmodified. The 1127 // component containing the extension point becomes a narrower SEXT_INREG. 1128 // Components above it are ashr'd from the component containing the 1129 // extension point. 1130 if (SizeOp0 % NarrowSize != 0) 1131 return UnableToLegalize; 1132 int NumParts = SizeOp0 / NarrowSize; 1133 1134 // List the registers where the destination will be scattered. 1135 SmallVector<Register, 2> DstRegs; 1136 // List the registers where the source will be split. 1137 SmallVector<Register, 2> SrcRegs; 1138 1139 // Create all the temporary registers. 1140 for (int i = 0; i < NumParts; ++i) { 1141 Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy); 1142 1143 SrcRegs.push_back(SrcReg); 1144 } 1145 1146 // Explode the big arguments into smaller chunks. 1147 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1)); 1148 1149 Register AshrCstReg = 1150 MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1) 1151 .getReg(0); 1152 Register FullExtensionReg = 0; 1153 Register PartialExtensionReg = 0; 1154 1155 // Do the operation on each small part. 1156 for (int i = 0; i < NumParts; ++i) { 1157 if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits) 1158 DstRegs.push_back(SrcRegs[i]); 1159 else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) { 1160 assert(PartialExtensionReg && 1161 "Expected to visit partial extension before full"); 1162 if (FullExtensionReg) { 1163 DstRegs.push_back(FullExtensionReg); 1164 continue; 1165 } 1166 DstRegs.push_back( 1167 MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg) 1168 .getReg(0)); 1169 FullExtensionReg = DstRegs.back(); 1170 } else { 1171 DstRegs.push_back( 1172 MIRBuilder 1173 .buildInstr( 1174 TargetOpcode::G_SEXT_INREG, {NarrowTy}, 1175 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) 1176 .getReg(0)); 1177 PartialExtensionReg = DstRegs.back(); 1178 } 1179 } 1180 1181 // Gather the destination registers into the final destination. 1182 Register DstReg = MI.getOperand(0).getReg(); 1183 MIRBuilder.buildMerge(DstReg, DstRegs); 1184 MI.eraseFromParent(); 1185 return Legalized; 1186 } 1187 case TargetOpcode::G_BSWAP: 1188 case TargetOpcode::G_BITREVERSE: { 1189 if (SizeOp0 % NarrowSize != 0) 1190 return UnableToLegalize; 1191 1192 Observer.changingInstr(MI); 1193 SmallVector<Register, 2> SrcRegs, DstRegs; 1194 unsigned NumParts = SizeOp0 / NarrowSize; 1195 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 1196 1197 for (unsigned i = 0; i < NumParts; ++i) { 1198 auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 1199 {SrcRegs[NumParts - 1 - i]}); 1200 DstRegs.push_back(DstPart.getReg(0)); 1201 } 1202 1203 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1204 1205 Observer.changedInstr(MI); 1206 MI.eraseFromParent(); 1207 return Legalized; 1208 } 1209 case TargetOpcode::G_PTR_ADD: 1210 case TargetOpcode::G_PTRMASK: { 1211 if (TypeIdx != 1) 1212 return UnableToLegalize; 1213 Observer.changingInstr(MI); 1214 narrowScalarSrc(MI, NarrowTy, 2); 1215 Observer.changedInstr(MI); 1216 return Legalized; 1217 } 1218 case TargetOpcode::G_FPTOUI: 1219 case TargetOpcode::G_FPTOSI: 1220 return narrowScalarFPTOI(MI, TypeIdx, NarrowTy); 1221 case TargetOpcode::G_FPEXT: 1222 if (TypeIdx != 0) 1223 return UnableToLegalize; 1224 Observer.changingInstr(MI); 1225 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_FPEXT); 1226 Observer.changedInstr(MI); 1227 return Legalized; 1228 } 1229 } 1230 1231 Register LegalizerHelper::coerceToScalar(Register Val) { 1232 LLT Ty = MRI.getType(Val); 1233 if (Ty.isScalar()) 1234 return Val; 1235 1236 const DataLayout &DL = MIRBuilder.getDataLayout(); 1237 LLT NewTy = LLT::scalar(Ty.getSizeInBits()); 1238 if (Ty.isPointer()) { 1239 if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace())) 1240 return Register(); 1241 return MIRBuilder.buildPtrToInt(NewTy, Val).getReg(0); 1242 } 1243 1244 Register NewVal = Val; 1245 1246 assert(Ty.isVector()); 1247 LLT EltTy = Ty.getElementType(); 1248 if (EltTy.isPointer()) 1249 NewVal = MIRBuilder.buildPtrToInt(NewTy, NewVal).getReg(0); 1250 return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0); 1251 } 1252 1253 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy, 1254 unsigned OpIdx, unsigned ExtOpcode) { 1255 MachineOperand &MO = MI.getOperand(OpIdx); 1256 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO}); 1257 MO.setReg(ExtB.getReg(0)); 1258 } 1259 1260 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, 1261 unsigned OpIdx) { 1262 MachineOperand &MO = MI.getOperand(OpIdx); 1263 auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO); 1264 MO.setReg(ExtB.getReg(0)); 1265 } 1266 1267 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy, 1268 unsigned OpIdx, unsigned TruncOpcode) { 1269 MachineOperand &MO = MI.getOperand(OpIdx); 1270 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1271 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1272 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); 1273 MO.setReg(DstExt); 1274 } 1275 1276 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy, 1277 unsigned OpIdx, unsigned ExtOpcode) { 1278 MachineOperand &MO = MI.getOperand(OpIdx); 1279 Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy); 1280 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1281 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); 1282 MO.setReg(DstTrunc); 1283 } 1284 1285 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy, 1286 unsigned OpIdx) { 1287 MachineOperand &MO = MI.getOperand(OpIdx); 1288 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1289 MO.setReg(widenWithUnmerge(WideTy, MO.getReg())); 1290 } 1291 1292 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, 1293 unsigned OpIdx) { 1294 MachineOperand &MO = MI.getOperand(OpIdx); 1295 1296 LLT OldTy = MRI.getType(MO.getReg()); 1297 unsigned OldElts = OldTy.getNumElements(); 1298 unsigned NewElts = MoreTy.getNumElements(); 1299 1300 unsigned NumParts = NewElts / OldElts; 1301 1302 // Use concat_vectors if the result is a multiple of the number of elements. 1303 if (NumParts * OldElts == NewElts) { 1304 SmallVector<Register, 8> Parts; 1305 Parts.push_back(MO.getReg()); 1306 1307 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); 1308 for (unsigned I = 1; I != NumParts; ++I) 1309 Parts.push_back(ImpDef); 1310 1311 auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts); 1312 MO.setReg(Concat.getReg(0)); 1313 return; 1314 } 1315 1316 Register MoreReg = MRI.createGenericVirtualRegister(MoreTy); 1317 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); 1318 MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0); 1319 MO.setReg(MoreReg); 1320 } 1321 1322 void LegalizerHelper::bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1323 MachineOperand &Op = MI.getOperand(OpIdx); 1324 Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0)); 1325 } 1326 1327 void LegalizerHelper::bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1328 MachineOperand &MO = MI.getOperand(OpIdx); 1329 Register CastDst = MRI.createGenericVirtualRegister(CastTy); 1330 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1331 MIRBuilder.buildBitcast(MO, CastDst); 1332 MO.setReg(CastDst); 1333 } 1334 1335 LegalizerHelper::LegalizeResult 1336 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, 1337 LLT WideTy) { 1338 if (TypeIdx != 1) 1339 return UnableToLegalize; 1340 1341 Register DstReg = MI.getOperand(0).getReg(); 1342 LLT DstTy = MRI.getType(DstReg); 1343 if (DstTy.isVector()) 1344 return UnableToLegalize; 1345 1346 Register Src1 = MI.getOperand(1).getReg(); 1347 LLT SrcTy = MRI.getType(Src1); 1348 const int DstSize = DstTy.getSizeInBits(); 1349 const int SrcSize = SrcTy.getSizeInBits(); 1350 const int WideSize = WideTy.getSizeInBits(); 1351 const int NumMerge = (DstSize + WideSize - 1) / WideSize; 1352 1353 unsigned NumOps = MI.getNumOperands(); 1354 unsigned NumSrc = MI.getNumOperands() - 1; 1355 unsigned PartSize = DstTy.getSizeInBits() / NumSrc; 1356 1357 if (WideSize >= DstSize) { 1358 // Directly pack the bits in the target type. 1359 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); 1360 1361 for (unsigned I = 2; I != NumOps; ++I) { 1362 const unsigned Offset = (I - 1) * PartSize; 1363 1364 Register SrcReg = MI.getOperand(I).getReg(); 1365 assert(MRI.getType(SrcReg) == LLT::scalar(PartSize)); 1366 1367 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 1368 1369 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 1370 MRI.createGenericVirtualRegister(WideTy); 1371 1372 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 1373 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 1374 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 1375 ResultReg = NextResult; 1376 } 1377 1378 if (WideSize > DstSize) 1379 MIRBuilder.buildTrunc(DstReg, ResultReg); 1380 else if (DstTy.isPointer()) 1381 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 1382 1383 MI.eraseFromParent(); 1384 return Legalized; 1385 } 1386 1387 // Unmerge the original values to the GCD type, and recombine to the next 1388 // multiple greater than the original type. 1389 // 1390 // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6 1391 // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0 1392 // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1 1393 // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2 1394 // %10:_(s6) = G_MERGE_VALUES %4, %5, %6 1395 // %11:_(s6) = G_MERGE_VALUES %7, %8, %9 1396 // %12:_(s12) = G_MERGE_VALUES %10, %11 1397 // 1398 // Padding with undef if necessary: 1399 // 1400 // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6 1401 // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0 1402 // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1 1403 // %7:_(s2) = G_IMPLICIT_DEF 1404 // %8:_(s6) = G_MERGE_VALUES %3, %4, %5 1405 // %9:_(s6) = G_MERGE_VALUES %6, %7, %7 1406 // %10:_(s12) = G_MERGE_VALUES %8, %9 1407 1408 const int GCD = greatestCommonDivisor(SrcSize, WideSize); 1409 LLT GCDTy = LLT::scalar(GCD); 1410 1411 SmallVector<Register, 8> Parts; 1412 SmallVector<Register, 8> NewMergeRegs; 1413 SmallVector<Register, 8> Unmerges; 1414 LLT WideDstTy = LLT::scalar(NumMerge * WideSize); 1415 1416 // Decompose the original operands if they don't evenly divide. 1417 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) { 1418 Register SrcReg = MI.getOperand(I).getReg(); 1419 if (GCD == SrcSize) { 1420 Unmerges.push_back(SrcReg); 1421 } else { 1422 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 1423 for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J) 1424 Unmerges.push_back(Unmerge.getReg(J)); 1425 } 1426 } 1427 1428 // Pad with undef to the next size that is a multiple of the requested size. 1429 if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) { 1430 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 1431 for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I) 1432 Unmerges.push_back(UndefReg); 1433 } 1434 1435 const int PartsPerGCD = WideSize / GCD; 1436 1437 // Build merges of each piece. 1438 ArrayRef<Register> Slicer(Unmerges); 1439 for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) { 1440 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD)); 1441 NewMergeRegs.push_back(Merge.getReg(0)); 1442 } 1443 1444 // A truncate may be necessary if the requested type doesn't evenly divide the 1445 // original result type. 1446 if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) { 1447 MIRBuilder.buildMerge(DstReg, NewMergeRegs); 1448 } else { 1449 auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs); 1450 MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0)); 1451 } 1452 1453 MI.eraseFromParent(); 1454 return Legalized; 1455 } 1456 1457 Register LegalizerHelper::widenWithUnmerge(LLT WideTy, Register OrigReg) { 1458 Register WideReg = MRI.createGenericVirtualRegister(WideTy); 1459 LLT OrigTy = MRI.getType(OrigReg); 1460 LLT LCMTy = getLCMType(WideTy, OrigTy); 1461 1462 const int NumMergeParts = LCMTy.getSizeInBits() / WideTy.getSizeInBits(); 1463 const int NumUnmergeParts = LCMTy.getSizeInBits() / OrigTy.getSizeInBits(); 1464 1465 Register UnmergeSrc = WideReg; 1466 1467 // Create a merge to the LCM type, padding with undef 1468 // %0:_(<3 x s32>) = G_FOO => <4 x s32> 1469 // => 1470 // %1:_(<4 x s32>) = G_FOO 1471 // %2:_(<4 x s32>) = G_IMPLICIT_DEF 1472 // %3:_(<12 x s32>) = G_CONCAT_VECTORS %1, %2, %2 1473 // %0:_(<3 x s32>), %4:_, %5:_, %6:_ = G_UNMERGE_VALUES %3 1474 if (NumMergeParts > 1) { 1475 Register Undef = MIRBuilder.buildUndef(WideTy).getReg(0); 1476 SmallVector<Register, 8> MergeParts(NumMergeParts, Undef); 1477 MergeParts[0] = WideReg; 1478 UnmergeSrc = MIRBuilder.buildMerge(LCMTy, MergeParts).getReg(0); 1479 } 1480 1481 // Unmerge to the original register and pad with dead defs. 1482 SmallVector<Register, 8> UnmergeResults(NumUnmergeParts); 1483 UnmergeResults[0] = OrigReg; 1484 for (int I = 1; I != NumUnmergeParts; ++I) 1485 UnmergeResults[I] = MRI.createGenericVirtualRegister(OrigTy); 1486 1487 MIRBuilder.buildUnmerge(UnmergeResults, UnmergeSrc); 1488 return WideReg; 1489 } 1490 1491 LegalizerHelper::LegalizeResult 1492 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, 1493 LLT WideTy) { 1494 if (TypeIdx != 0) 1495 return UnableToLegalize; 1496 1497 int NumDst = MI.getNumOperands() - 1; 1498 Register SrcReg = MI.getOperand(NumDst).getReg(); 1499 LLT SrcTy = MRI.getType(SrcReg); 1500 if (SrcTy.isVector()) 1501 return UnableToLegalize; 1502 1503 Register Dst0Reg = MI.getOperand(0).getReg(); 1504 LLT DstTy = MRI.getType(Dst0Reg); 1505 if (!DstTy.isScalar()) 1506 return UnableToLegalize; 1507 1508 if (WideTy.getSizeInBits() >= SrcTy.getSizeInBits()) { 1509 if (SrcTy.isPointer()) { 1510 const DataLayout &DL = MIRBuilder.getDataLayout(); 1511 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) { 1512 LLVM_DEBUG( 1513 dbgs() << "Not casting non-integral address space integer\n"); 1514 return UnableToLegalize; 1515 } 1516 1517 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 1518 SrcReg = MIRBuilder.buildPtrToInt(SrcTy, SrcReg).getReg(0); 1519 } 1520 1521 // Widen SrcTy to WideTy. This does not affect the result, but since the 1522 // user requested this size, it is probably better handled than SrcTy and 1523 // should reduce the total number of legalization artifacts 1524 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1525 SrcTy = WideTy; 1526 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); 1527 } 1528 1529 // Theres no unmerge type to target. Directly extract the bits from the 1530 // source type 1531 unsigned DstSize = DstTy.getSizeInBits(); 1532 1533 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 1534 for (int I = 1; I != NumDst; ++I) { 1535 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I); 1536 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); 1537 MIRBuilder.buildTrunc(MI.getOperand(I), Shr); 1538 } 1539 1540 MI.eraseFromParent(); 1541 return Legalized; 1542 } 1543 1544 // Extend the source to a wider type. 1545 LLT LCMTy = getLCMType(SrcTy, WideTy); 1546 1547 Register WideSrc = SrcReg; 1548 if (LCMTy.getSizeInBits() != SrcTy.getSizeInBits()) { 1549 // TODO: If this is an integral address space, cast to integer and anyext. 1550 if (SrcTy.isPointer()) { 1551 LLVM_DEBUG(dbgs() << "Widening pointer source types not implemented\n"); 1552 return UnableToLegalize; 1553 } 1554 1555 WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0); 1556 } 1557 1558 auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc); 1559 1560 // Create a sequence of unmerges and merges to the original results. Since we 1561 // may have widened the source, we will need to pad the results with dead defs 1562 // to cover the source register. 1563 // e.g. widen s48 to s64: 1564 // %1:_(s48), %2:_(s48) = G_UNMERGE_VALUES %0:_(s96) 1565 // 1566 // => 1567 // %4:_(s192) = G_ANYEXT %0:_(s96) 1568 // %5:_(s64), %6, %7 = G_UNMERGE_VALUES %4 ; Requested unmerge 1569 // ; unpack to GCD type, with extra dead defs 1570 // %8:_(s16), %9, %10, %11 = G_UNMERGE_VALUES %5:_(s64) 1571 // %12:_(s16), %13, dead %14, dead %15 = G_UNMERGE_VALUES %6:_(s64) 1572 // dead %16:_(s16), dead %17, dead %18, dead %18 = G_UNMERGE_VALUES %7:_(s64) 1573 // %1:_(s48) = G_MERGE_VALUES %8:_(s16), %9, %10 ; Remerge to destination 1574 // %2:_(s48) = G_MERGE_VALUES %11:_(s16), %12, %13 ; Remerge to destination 1575 const LLT GCDTy = getGCDType(WideTy, DstTy); 1576 const int NumUnmerge = Unmerge->getNumOperands() - 1; 1577 const int PartsPerRemerge = DstTy.getSizeInBits() / GCDTy.getSizeInBits(); 1578 1579 // Directly unmerge to the destination without going through a GCD type 1580 // if possible 1581 if (PartsPerRemerge == 1) { 1582 const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits(); 1583 1584 for (int I = 0; I != NumUnmerge; ++I) { 1585 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 1586 1587 for (int J = 0; J != PartsPerUnmerge; ++J) { 1588 int Idx = I * PartsPerUnmerge + J; 1589 if (Idx < NumDst) 1590 MIB.addDef(MI.getOperand(Idx).getReg()); 1591 else { 1592 // Create dead def for excess components. 1593 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 1594 } 1595 } 1596 1597 MIB.addUse(Unmerge.getReg(I)); 1598 } 1599 } else { 1600 SmallVector<Register, 16> Parts; 1601 for (int J = 0; J != NumUnmerge; ++J) 1602 extractGCDType(Parts, GCDTy, Unmerge.getReg(J)); 1603 1604 SmallVector<Register, 8> RemergeParts; 1605 for (int I = 0; I != NumDst; ++I) { 1606 for (int J = 0; J < PartsPerRemerge; ++J) { 1607 const int Idx = I * PartsPerRemerge + J; 1608 RemergeParts.emplace_back(Parts[Idx]); 1609 } 1610 1611 MIRBuilder.buildMerge(MI.getOperand(I).getReg(), RemergeParts); 1612 RemergeParts.clear(); 1613 } 1614 } 1615 1616 MI.eraseFromParent(); 1617 return Legalized; 1618 } 1619 1620 LegalizerHelper::LegalizeResult 1621 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, 1622 LLT WideTy) { 1623 Register DstReg = MI.getOperand(0).getReg(); 1624 Register SrcReg = MI.getOperand(1).getReg(); 1625 LLT SrcTy = MRI.getType(SrcReg); 1626 1627 LLT DstTy = MRI.getType(DstReg); 1628 unsigned Offset = MI.getOperand(2).getImm(); 1629 1630 if (TypeIdx == 0) { 1631 if (SrcTy.isVector() || DstTy.isVector()) 1632 return UnableToLegalize; 1633 1634 SrcOp Src(SrcReg); 1635 if (SrcTy.isPointer()) { 1636 // Extracts from pointers can be handled only if they are really just 1637 // simple integers. 1638 const DataLayout &DL = MIRBuilder.getDataLayout(); 1639 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) 1640 return UnableToLegalize; 1641 1642 LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits()); 1643 Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src); 1644 SrcTy = SrcAsIntTy; 1645 } 1646 1647 if (DstTy.isPointer()) 1648 return UnableToLegalize; 1649 1650 if (Offset == 0) { 1651 // Avoid a shift in the degenerate case. 1652 MIRBuilder.buildTrunc(DstReg, 1653 MIRBuilder.buildAnyExtOrTrunc(WideTy, Src)); 1654 MI.eraseFromParent(); 1655 return Legalized; 1656 } 1657 1658 // Do a shift in the source type. 1659 LLT ShiftTy = SrcTy; 1660 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1661 Src = MIRBuilder.buildAnyExt(WideTy, Src); 1662 ShiftTy = WideTy; 1663 } 1664 1665 auto LShr = MIRBuilder.buildLShr( 1666 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); 1667 MIRBuilder.buildTrunc(DstReg, LShr); 1668 MI.eraseFromParent(); 1669 return Legalized; 1670 } 1671 1672 if (SrcTy.isScalar()) { 1673 Observer.changingInstr(MI); 1674 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1675 Observer.changedInstr(MI); 1676 return Legalized; 1677 } 1678 1679 if (!SrcTy.isVector()) 1680 return UnableToLegalize; 1681 1682 if (DstTy != SrcTy.getElementType()) 1683 return UnableToLegalize; 1684 1685 if (Offset % SrcTy.getScalarSizeInBits() != 0) 1686 return UnableToLegalize; 1687 1688 Observer.changingInstr(MI); 1689 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1690 1691 MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) * 1692 Offset); 1693 widenScalarDst(MI, WideTy.getScalarType(), 0); 1694 Observer.changedInstr(MI); 1695 return Legalized; 1696 } 1697 1698 LegalizerHelper::LegalizeResult 1699 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, 1700 LLT WideTy) { 1701 if (TypeIdx != 0 || WideTy.isVector()) 1702 return UnableToLegalize; 1703 Observer.changingInstr(MI); 1704 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1705 widenScalarDst(MI, WideTy); 1706 Observer.changedInstr(MI); 1707 return Legalized; 1708 } 1709 1710 LegalizerHelper::LegalizeResult 1711 LegalizerHelper::widenScalarAddSubOverflow(MachineInstr &MI, unsigned TypeIdx, 1712 LLT WideTy) { 1713 if (TypeIdx == 1) 1714 return UnableToLegalize; // TODO 1715 1716 unsigned Opcode; 1717 unsigned ExtOpcode; 1718 Optional<Register> CarryIn = None; 1719 switch (MI.getOpcode()) { 1720 default: 1721 llvm_unreachable("Unexpected opcode!"); 1722 case TargetOpcode::G_SADDO: 1723 Opcode = TargetOpcode::G_ADD; 1724 ExtOpcode = TargetOpcode::G_SEXT; 1725 break; 1726 case TargetOpcode::G_SSUBO: 1727 Opcode = TargetOpcode::G_SUB; 1728 ExtOpcode = TargetOpcode::G_SEXT; 1729 break; 1730 case TargetOpcode::G_UADDO: 1731 Opcode = TargetOpcode::G_ADD; 1732 ExtOpcode = TargetOpcode::G_ZEXT; 1733 break; 1734 case TargetOpcode::G_USUBO: 1735 Opcode = TargetOpcode::G_SUB; 1736 ExtOpcode = TargetOpcode::G_ZEXT; 1737 break; 1738 case TargetOpcode::G_SADDE: 1739 Opcode = TargetOpcode::G_UADDE; 1740 ExtOpcode = TargetOpcode::G_SEXT; 1741 CarryIn = MI.getOperand(4).getReg(); 1742 break; 1743 case TargetOpcode::G_SSUBE: 1744 Opcode = TargetOpcode::G_USUBE; 1745 ExtOpcode = TargetOpcode::G_SEXT; 1746 CarryIn = MI.getOperand(4).getReg(); 1747 break; 1748 case TargetOpcode::G_UADDE: 1749 Opcode = TargetOpcode::G_UADDE; 1750 ExtOpcode = TargetOpcode::G_ZEXT; 1751 CarryIn = MI.getOperand(4).getReg(); 1752 break; 1753 case TargetOpcode::G_USUBE: 1754 Opcode = TargetOpcode::G_USUBE; 1755 ExtOpcode = TargetOpcode::G_ZEXT; 1756 CarryIn = MI.getOperand(4).getReg(); 1757 break; 1758 } 1759 1760 auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)}); 1761 auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)}); 1762 // Do the arithmetic in the larger type. 1763 Register NewOp; 1764 if (CarryIn) { 1765 LLT CarryOutTy = MRI.getType(MI.getOperand(1).getReg()); 1766 NewOp = MIRBuilder 1767 .buildInstr(Opcode, {WideTy, CarryOutTy}, 1768 {LHSExt, RHSExt, *CarryIn}) 1769 .getReg(0); 1770 } else { 1771 NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt}).getReg(0); 1772 } 1773 LLT OrigTy = MRI.getType(MI.getOperand(0).getReg()); 1774 auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp); 1775 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); 1776 // There is no overflow if the ExtOp is the same as NewOp. 1777 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); 1778 // Now trunc the NewOp to the original result. 1779 MIRBuilder.buildTrunc(MI.getOperand(0), NewOp); 1780 MI.eraseFromParent(); 1781 return Legalized; 1782 } 1783 1784 LegalizerHelper::LegalizeResult 1785 LegalizerHelper::widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx, 1786 LLT WideTy) { 1787 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SADDSAT || 1788 MI.getOpcode() == TargetOpcode::G_SSUBSAT || 1789 MI.getOpcode() == TargetOpcode::G_SSHLSAT; 1790 bool IsShift = MI.getOpcode() == TargetOpcode::G_SSHLSAT || 1791 MI.getOpcode() == TargetOpcode::G_USHLSAT; 1792 // We can convert this to: 1793 // 1. Any extend iN to iM 1794 // 2. SHL by M-N 1795 // 3. [US][ADD|SUB|SHL]SAT 1796 // 4. L/ASHR by M-N 1797 // 1798 // It may be more efficient to lower this to a min and a max operation in 1799 // the higher precision arithmetic if the promoted operation isn't legal, 1800 // but this decision is up to the target's lowering request. 1801 Register DstReg = MI.getOperand(0).getReg(); 1802 1803 unsigned NewBits = WideTy.getScalarSizeInBits(); 1804 unsigned SHLAmount = NewBits - MRI.getType(DstReg).getScalarSizeInBits(); 1805 1806 // Shifts must zero-extend the RHS to preserve the unsigned quantity, and 1807 // must not left shift the RHS to preserve the shift amount. 1808 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1)); 1809 auto RHS = IsShift ? MIRBuilder.buildZExt(WideTy, MI.getOperand(2)) 1810 : MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2)); 1811 auto ShiftK = MIRBuilder.buildConstant(WideTy, SHLAmount); 1812 auto ShiftL = MIRBuilder.buildShl(WideTy, LHS, ShiftK); 1813 auto ShiftR = IsShift ? RHS : MIRBuilder.buildShl(WideTy, RHS, ShiftK); 1814 1815 auto WideInst = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, 1816 {ShiftL, ShiftR}, MI.getFlags()); 1817 1818 // Use a shift that will preserve the number of sign bits when the trunc is 1819 // folded away. 1820 auto Result = IsSigned ? MIRBuilder.buildAShr(WideTy, WideInst, ShiftK) 1821 : MIRBuilder.buildLShr(WideTy, WideInst, ShiftK); 1822 1823 MIRBuilder.buildTrunc(DstReg, Result); 1824 MI.eraseFromParent(); 1825 return Legalized; 1826 } 1827 1828 LegalizerHelper::LegalizeResult 1829 LegalizerHelper::widenScalarMulo(MachineInstr &MI, unsigned TypeIdx, 1830 LLT WideTy) { 1831 if (TypeIdx == 1) 1832 return UnableToLegalize; 1833 1834 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULO; 1835 Register Result = MI.getOperand(0).getReg(); 1836 Register OriginalOverflow = MI.getOperand(1).getReg(); 1837 Register LHS = MI.getOperand(2).getReg(); 1838 Register RHS = MI.getOperand(3).getReg(); 1839 LLT SrcTy = MRI.getType(LHS); 1840 LLT OverflowTy = MRI.getType(OriginalOverflow); 1841 unsigned SrcBitWidth = SrcTy.getScalarSizeInBits(); 1842 1843 // To determine if the result overflowed in the larger type, we extend the 1844 // input to the larger type, do the multiply (checking if it overflows), 1845 // then also check the high bits of the result to see if overflow happened 1846 // there. 1847 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 1848 auto LeftOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {LHS}); 1849 auto RightOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {RHS}); 1850 1851 auto Mulo = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy, OverflowTy}, 1852 {LeftOperand, RightOperand}); 1853 auto Mul = Mulo->getOperand(0); 1854 MIRBuilder.buildTrunc(Result, Mul); 1855 1856 MachineInstrBuilder ExtResult; 1857 // Overflow occurred if it occurred in the larger type, or if the high part 1858 // of the result does not zero/sign-extend the low part. Check this second 1859 // possibility first. 1860 if (IsSigned) { 1861 // For signed, overflow occurred when the high part does not sign-extend 1862 // the low part. 1863 ExtResult = MIRBuilder.buildSExtInReg(WideTy, Mul, SrcBitWidth); 1864 } else { 1865 // Unsigned overflow occurred when the high part does not zero-extend the 1866 // low part. 1867 ExtResult = MIRBuilder.buildZExtInReg(WideTy, Mul, SrcBitWidth); 1868 } 1869 1870 // Multiplication cannot overflow if the WideTy is >= 2 * original width, 1871 // so we don't need to check the overflow result of larger type Mulo. 1872 if (WideTy.getScalarSizeInBits() < 2 * SrcBitWidth) { 1873 auto Overflow = 1874 MIRBuilder.buildICmp(CmpInst::ICMP_NE, OverflowTy, Mul, ExtResult); 1875 // Finally check if the multiplication in the larger type itself overflowed. 1876 MIRBuilder.buildOr(OriginalOverflow, Mulo->getOperand(1), Overflow); 1877 } else { 1878 MIRBuilder.buildICmp(CmpInst::ICMP_NE, OriginalOverflow, Mul, ExtResult); 1879 } 1880 MI.eraseFromParent(); 1881 return Legalized; 1882 } 1883 1884 LegalizerHelper::LegalizeResult 1885 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { 1886 switch (MI.getOpcode()) { 1887 default: 1888 return UnableToLegalize; 1889 case TargetOpcode::G_EXTRACT: 1890 return widenScalarExtract(MI, TypeIdx, WideTy); 1891 case TargetOpcode::G_INSERT: 1892 return widenScalarInsert(MI, TypeIdx, WideTy); 1893 case TargetOpcode::G_MERGE_VALUES: 1894 return widenScalarMergeValues(MI, TypeIdx, WideTy); 1895 case TargetOpcode::G_UNMERGE_VALUES: 1896 return widenScalarUnmergeValues(MI, TypeIdx, WideTy); 1897 case TargetOpcode::G_SADDO: 1898 case TargetOpcode::G_SSUBO: 1899 case TargetOpcode::G_UADDO: 1900 case TargetOpcode::G_USUBO: 1901 case TargetOpcode::G_SADDE: 1902 case TargetOpcode::G_SSUBE: 1903 case TargetOpcode::G_UADDE: 1904 case TargetOpcode::G_USUBE: 1905 return widenScalarAddSubOverflow(MI, TypeIdx, WideTy); 1906 case TargetOpcode::G_UMULO: 1907 case TargetOpcode::G_SMULO: 1908 return widenScalarMulo(MI, TypeIdx, WideTy); 1909 case TargetOpcode::G_SADDSAT: 1910 case TargetOpcode::G_SSUBSAT: 1911 case TargetOpcode::G_SSHLSAT: 1912 case TargetOpcode::G_UADDSAT: 1913 case TargetOpcode::G_USUBSAT: 1914 case TargetOpcode::G_USHLSAT: 1915 return widenScalarAddSubShlSat(MI, TypeIdx, WideTy); 1916 case TargetOpcode::G_CTTZ: 1917 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 1918 case TargetOpcode::G_CTLZ: 1919 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 1920 case TargetOpcode::G_CTPOP: { 1921 if (TypeIdx == 0) { 1922 Observer.changingInstr(MI); 1923 widenScalarDst(MI, WideTy, 0); 1924 Observer.changedInstr(MI); 1925 return Legalized; 1926 } 1927 1928 Register SrcReg = MI.getOperand(1).getReg(); 1929 1930 // First ZEXT the input. 1931 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg); 1932 LLT CurTy = MRI.getType(SrcReg); 1933 if (MI.getOpcode() == TargetOpcode::G_CTTZ) { 1934 // The count is the same in the larger type except if the original 1935 // value was zero. This can be handled by setting the bit just off 1936 // the top of the original type. 1937 auto TopBit = 1938 APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits()); 1939 MIBSrc = MIRBuilder.buildOr( 1940 WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit)); 1941 } 1942 1943 // Perform the operation at the larger size. 1944 auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc}); 1945 // This is already the correct result for CTPOP and CTTZs 1946 if (MI.getOpcode() == TargetOpcode::G_CTLZ || 1947 MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) { 1948 // The correct result is NewOp - (Difference in widety and current ty). 1949 unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits(); 1950 MIBNewOp = MIRBuilder.buildSub( 1951 WideTy, MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)); 1952 } 1953 1954 MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp); 1955 MI.eraseFromParent(); 1956 return Legalized; 1957 } 1958 case TargetOpcode::G_BSWAP: { 1959 Observer.changingInstr(MI); 1960 Register DstReg = MI.getOperand(0).getReg(); 1961 1962 Register ShrReg = MRI.createGenericVirtualRegister(WideTy); 1963 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1964 Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy); 1965 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1966 1967 MI.getOperand(0).setReg(DstExt); 1968 1969 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1970 1971 LLT Ty = MRI.getType(DstReg); 1972 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 1973 MIRBuilder.buildConstant(ShiftAmtReg, DiffBits); 1974 MIRBuilder.buildLShr(ShrReg, DstExt, ShiftAmtReg); 1975 1976 MIRBuilder.buildTrunc(DstReg, ShrReg); 1977 Observer.changedInstr(MI); 1978 return Legalized; 1979 } 1980 case TargetOpcode::G_BITREVERSE: { 1981 Observer.changingInstr(MI); 1982 1983 Register DstReg = MI.getOperand(0).getReg(); 1984 LLT Ty = MRI.getType(DstReg); 1985 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 1986 1987 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1988 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1989 MI.getOperand(0).setReg(DstExt); 1990 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1991 1992 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); 1993 auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt); 1994 MIRBuilder.buildTrunc(DstReg, Shift); 1995 Observer.changedInstr(MI); 1996 return Legalized; 1997 } 1998 case TargetOpcode::G_FREEZE: 1999 Observer.changingInstr(MI); 2000 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2001 widenScalarDst(MI, WideTy); 2002 Observer.changedInstr(MI); 2003 return Legalized; 2004 2005 case TargetOpcode::G_ABS: 2006 Observer.changingInstr(MI); 2007 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2008 widenScalarDst(MI, WideTy); 2009 Observer.changedInstr(MI); 2010 return Legalized; 2011 2012 case TargetOpcode::G_ADD: 2013 case TargetOpcode::G_AND: 2014 case TargetOpcode::G_MUL: 2015 case TargetOpcode::G_OR: 2016 case TargetOpcode::G_XOR: 2017 case TargetOpcode::G_SUB: 2018 // Perform operation at larger width (any extension is fines here, high bits 2019 // don't affect the result) and then truncate the result back to the 2020 // original type. 2021 Observer.changingInstr(MI); 2022 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2023 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2024 widenScalarDst(MI, WideTy); 2025 Observer.changedInstr(MI); 2026 return Legalized; 2027 2028 case TargetOpcode::G_SBFX: 2029 case TargetOpcode::G_UBFX: 2030 Observer.changingInstr(MI); 2031 2032 if (TypeIdx == 0) { 2033 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2034 widenScalarDst(MI, WideTy); 2035 } else { 2036 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2037 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ZEXT); 2038 } 2039 2040 Observer.changedInstr(MI); 2041 return Legalized; 2042 2043 case TargetOpcode::G_SHL: 2044 Observer.changingInstr(MI); 2045 2046 if (TypeIdx == 0) { 2047 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2048 widenScalarDst(MI, WideTy); 2049 } else { 2050 assert(TypeIdx == 1); 2051 // The "number of bits to shift" operand must preserve its value as an 2052 // unsigned integer: 2053 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2054 } 2055 2056 Observer.changedInstr(MI); 2057 return Legalized; 2058 2059 case TargetOpcode::G_SDIV: 2060 case TargetOpcode::G_SREM: 2061 case TargetOpcode::G_SMIN: 2062 case TargetOpcode::G_SMAX: 2063 Observer.changingInstr(MI); 2064 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2065 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2066 widenScalarDst(MI, WideTy); 2067 Observer.changedInstr(MI); 2068 return Legalized; 2069 2070 case TargetOpcode::G_SDIVREM: 2071 Observer.changingInstr(MI); 2072 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2073 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT); 2074 widenScalarDst(MI, WideTy); 2075 widenScalarDst(MI, WideTy, 1); 2076 Observer.changedInstr(MI); 2077 return Legalized; 2078 2079 case TargetOpcode::G_ASHR: 2080 case TargetOpcode::G_LSHR: 2081 Observer.changingInstr(MI); 2082 2083 if (TypeIdx == 0) { 2084 unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ? 2085 TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 2086 2087 widenScalarSrc(MI, WideTy, 1, CvtOp); 2088 widenScalarDst(MI, WideTy); 2089 } else { 2090 assert(TypeIdx == 1); 2091 // The "number of bits to shift" operand must preserve its value as an 2092 // unsigned integer: 2093 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2094 } 2095 2096 Observer.changedInstr(MI); 2097 return Legalized; 2098 case TargetOpcode::G_UDIV: 2099 case TargetOpcode::G_UREM: 2100 case TargetOpcode::G_UMIN: 2101 case TargetOpcode::G_UMAX: 2102 Observer.changingInstr(MI); 2103 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2104 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2105 widenScalarDst(MI, WideTy); 2106 Observer.changedInstr(MI); 2107 return Legalized; 2108 2109 case TargetOpcode::G_UDIVREM: 2110 Observer.changingInstr(MI); 2111 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2112 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ZEXT); 2113 widenScalarDst(MI, WideTy); 2114 widenScalarDst(MI, WideTy, 1); 2115 Observer.changedInstr(MI); 2116 return Legalized; 2117 2118 case TargetOpcode::G_SELECT: 2119 Observer.changingInstr(MI); 2120 if (TypeIdx == 0) { 2121 // Perform operation at larger width (any extension is fine here, high 2122 // bits don't affect the result) and then truncate the result back to the 2123 // original type. 2124 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2125 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT); 2126 widenScalarDst(MI, WideTy); 2127 } else { 2128 bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector(); 2129 // Explicit extension is required here since high bits affect the result. 2130 widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false)); 2131 } 2132 Observer.changedInstr(MI); 2133 return Legalized; 2134 2135 case TargetOpcode::G_FPTOSI: 2136 case TargetOpcode::G_FPTOUI: 2137 Observer.changingInstr(MI); 2138 2139 if (TypeIdx == 0) 2140 widenScalarDst(MI, WideTy); 2141 else 2142 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2143 2144 Observer.changedInstr(MI); 2145 return Legalized; 2146 case TargetOpcode::G_SITOFP: 2147 Observer.changingInstr(MI); 2148 2149 if (TypeIdx == 0) 2150 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2151 else 2152 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2153 2154 Observer.changedInstr(MI); 2155 return Legalized; 2156 case TargetOpcode::G_UITOFP: 2157 Observer.changingInstr(MI); 2158 2159 if (TypeIdx == 0) 2160 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2161 else 2162 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2163 2164 Observer.changedInstr(MI); 2165 return Legalized; 2166 case TargetOpcode::G_LOAD: 2167 case TargetOpcode::G_SEXTLOAD: 2168 case TargetOpcode::G_ZEXTLOAD: 2169 Observer.changingInstr(MI); 2170 widenScalarDst(MI, WideTy); 2171 Observer.changedInstr(MI); 2172 return Legalized; 2173 2174 case TargetOpcode::G_STORE: { 2175 if (TypeIdx != 0) 2176 return UnableToLegalize; 2177 2178 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 2179 if (!Ty.isScalar()) 2180 return UnableToLegalize; 2181 2182 Observer.changingInstr(MI); 2183 2184 unsigned ExtType = Ty.getScalarSizeInBits() == 1 ? 2185 TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT; 2186 widenScalarSrc(MI, WideTy, 0, ExtType); 2187 2188 Observer.changedInstr(MI); 2189 return Legalized; 2190 } 2191 case TargetOpcode::G_CONSTANT: { 2192 MachineOperand &SrcMO = MI.getOperand(1); 2193 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2194 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( 2195 MRI.getType(MI.getOperand(0).getReg())); 2196 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || 2197 ExtOpc == TargetOpcode::G_ANYEXT) && 2198 "Illegal Extend"); 2199 const APInt &SrcVal = SrcMO.getCImm()->getValue(); 2200 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) 2201 ? SrcVal.sext(WideTy.getSizeInBits()) 2202 : SrcVal.zext(WideTy.getSizeInBits()); 2203 Observer.changingInstr(MI); 2204 SrcMO.setCImm(ConstantInt::get(Ctx, Val)); 2205 2206 widenScalarDst(MI, WideTy); 2207 Observer.changedInstr(MI); 2208 return Legalized; 2209 } 2210 case TargetOpcode::G_FCONSTANT: { 2211 MachineOperand &SrcMO = MI.getOperand(1); 2212 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2213 APFloat Val = SrcMO.getFPImm()->getValueAPF(); 2214 bool LosesInfo; 2215 switch (WideTy.getSizeInBits()) { 2216 case 32: 2217 Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, 2218 &LosesInfo); 2219 break; 2220 case 64: 2221 Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 2222 &LosesInfo); 2223 break; 2224 default: 2225 return UnableToLegalize; 2226 } 2227 2228 assert(!LosesInfo && "extend should always be lossless"); 2229 2230 Observer.changingInstr(MI); 2231 SrcMO.setFPImm(ConstantFP::get(Ctx, Val)); 2232 2233 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2234 Observer.changedInstr(MI); 2235 return Legalized; 2236 } 2237 case TargetOpcode::G_IMPLICIT_DEF: { 2238 Observer.changingInstr(MI); 2239 widenScalarDst(MI, WideTy); 2240 Observer.changedInstr(MI); 2241 return Legalized; 2242 } 2243 case TargetOpcode::G_BRCOND: 2244 Observer.changingInstr(MI); 2245 widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false)); 2246 Observer.changedInstr(MI); 2247 return Legalized; 2248 2249 case TargetOpcode::G_FCMP: 2250 Observer.changingInstr(MI); 2251 if (TypeIdx == 0) 2252 widenScalarDst(MI, WideTy); 2253 else { 2254 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT); 2255 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT); 2256 } 2257 Observer.changedInstr(MI); 2258 return Legalized; 2259 2260 case TargetOpcode::G_ICMP: 2261 Observer.changingInstr(MI); 2262 if (TypeIdx == 0) 2263 widenScalarDst(MI, WideTy); 2264 else { 2265 unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>( 2266 MI.getOperand(1).getPredicate())) 2267 ? TargetOpcode::G_SEXT 2268 : TargetOpcode::G_ZEXT; 2269 widenScalarSrc(MI, WideTy, 2, ExtOpcode); 2270 widenScalarSrc(MI, WideTy, 3, ExtOpcode); 2271 } 2272 Observer.changedInstr(MI); 2273 return Legalized; 2274 2275 case TargetOpcode::G_PTR_ADD: 2276 assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD"); 2277 Observer.changingInstr(MI); 2278 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2279 Observer.changedInstr(MI); 2280 return Legalized; 2281 2282 case TargetOpcode::G_PHI: { 2283 assert(TypeIdx == 0 && "Expecting only Idx 0"); 2284 2285 Observer.changingInstr(MI); 2286 for (unsigned I = 1; I < MI.getNumOperands(); I += 2) { 2287 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 2288 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 2289 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT); 2290 } 2291 2292 MachineBasicBlock &MBB = *MI.getParent(); 2293 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 2294 widenScalarDst(MI, WideTy); 2295 Observer.changedInstr(MI); 2296 return Legalized; 2297 } 2298 case TargetOpcode::G_EXTRACT_VECTOR_ELT: { 2299 if (TypeIdx == 0) { 2300 Register VecReg = MI.getOperand(1).getReg(); 2301 LLT VecTy = MRI.getType(VecReg); 2302 Observer.changingInstr(MI); 2303 2304 widenScalarSrc( 2305 MI, LLT::vector(VecTy.getElementCount(), WideTy.getSizeInBits()), 1, 2306 TargetOpcode::G_SEXT); 2307 2308 widenScalarDst(MI, WideTy, 0); 2309 Observer.changedInstr(MI); 2310 return Legalized; 2311 } 2312 2313 if (TypeIdx != 2) 2314 return UnableToLegalize; 2315 Observer.changingInstr(MI); 2316 // TODO: Probably should be zext 2317 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2318 Observer.changedInstr(MI); 2319 return Legalized; 2320 } 2321 case TargetOpcode::G_INSERT_VECTOR_ELT: { 2322 if (TypeIdx == 1) { 2323 Observer.changingInstr(MI); 2324 2325 Register VecReg = MI.getOperand(1).getReg(); 2326 LLT VecTy = MRI.getType(VecReg); 2327 LLT WideVecTy = LLT::vector(VecTy.getElementCount(), WideTy); 2328 2329 widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT); 2330 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2331 widenScalarDst(MI, WideVecTy, 0); 2332 Observer.changedInstr(MI); 2333 return Legalized; 2334 } 2335 2336 if (TypeIdx == 2) { 2337 Observer.changingInstr(MI); 2338 // TODO: Probably should be zext 2339 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT); 2340 Observer.changedInstr(MI); 2341 return Legalized; 2342 } 2343 2344 return UnableToLegalize; 2345 } 2346 case TargetOpcode::G_FADD: 2347 case TargetOpcode::G_FMUL: 2348 case TargetOpcode::G_FSUB: 2349 case TargetOpcode::G_FMA: 2350 case TargetOpcode::G_FMAD: 2351 case TargetOpcode::G_FNEG: 2352 case TargetOpcode::G_FABS: 2353 case TargetOpcode::G_FCANONICALIZE: 2354 case TargetOpcode::G_FMINNUM: 2355 case TargetOpcode::G_FMAXNUM: 2356 case TargetOpcode::G_FMINNUM_IEEE: 2357 case TargetOpcode::G_FMAXNUM_IEEE: 2358 case TargetOpcode::G_FMINIMUM: 2359 case TargetOpcode::G_FMAXIMUM: 2360 case TargetOpcode::G_FDIV: 2361 case TargetOpcode::G_FREM: 2362 case TargetOpcode::G_FCEIL: 2363 case TargetOpcode::G_FFLOOR: 2364 case TargetOpcode::G_FCOS: 2365 case TargetOpcode::G_FSIN: 2366 case TargetOpcode::G_FLOG10: 2367 case TargetOpcode::G_FLOG: 2368 case TargetOpcode::G_FLOG2: 2369 case TargetOpcode::G_FRINT: 2370 case TargetOpcode::G_FNEARBYINT: 2371 case TargetOpcode::G_FSQRT: 2372 case TargetOpcode::G_FEXP: 2373 case TargetOpcode::G_FEXP2: 2374 case TargetOpcode::G_FPOW: 2375 case TargetOpcode::G_INTRINSIC_TRUNC: 2376 case TargetOpcode::G_INTRINSIC_ROUND: 2377 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 2378 assert(TypeIdx == 0); 2379 Observer.changingInstr(MI); 2380 2381 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 2382 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT); 2383 2384 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2385 Observer.changedInstr(MI); 2386 return Legalized; 2387 case TargetOpcode::G_FPOWI: { 2388 if (TypeIdx != 0) 2389 return UnableToLegalize; 2390 Observer.changingInstr(MI); 2391 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2392 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2393 Observer.changedInstr(MI); 2394 return Legalized; 2395 } 2396 case TargetOpcode::G_INTTOPTR: 2397 if (TypeIdx != 1) 2398 return UnableToLegalize; 2399 2400 Observer.changingInstr(MI); 2401 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2402 Observer.changedInstr(MI); 2403 return Legalized; 2404 case TargetOpcode::G_PTRTOINT: 2405 if (TypeIdx != 0) 2406 return UnableToLegalize; 2407 2408 Observer.changingInstr(MI); 2409 widenScalarDst(MI, WideTy, 0); 2410 Observer.changedInstr(MI); 2411 return Legalized; 2412 case TargetOpcode::G_BUILD_VECTOR: { 2413 Observer.changingInstr(MI); 2414 2415 const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType(); 2416 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) 2417 widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT); 2418 2419 // Avoid changing the result vector type if the source element type was 2420 // requested. 2421 if (TypeIdx == 1) { 2422 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); 2423 } else { 2424 widenScalarDst(MI, WideTy, 0); 2425 } 2426 2427 Observer.changedInstr(MI); 2428 return Legalized; 2429 } 2430 case TargetOpcode::G_SEXT_INREG: 2431 if (TypeIdx != 0) 2432 return UnableToLegalize; 2433 2434 Observer.changingInstr(MI); 2435 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2436 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC); 2437 Observer.changedInstr(MI); 2438 return Legalized; 2439 case TargetOpcode::G_PTRMASK: { 2440 if (TypeIdx != 1) 2441 return UnableToLegalize; 2442 Observer.changingInstr(MI); 2443 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2444 Observer.changedInstr(MI); 2445 return Legalized; 2446 } 2447 } 2448 } 2449 2450 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces, 2451 MachineIRBuilder &B, Register Src, LLT Ty) { 2452 auto Unmerge = B.buildUnmerge(Ty, Src); 2453 for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I) 2454 Pieces.push_back(Unmerge.getReg(I)); 2455 } 2456 2457 LegalizerHelper::LegalizeResult 2458 LegalizerHelper::lowerBitcast(MachineInstr &MI) { 2459 Register Dst = MI.getOperand(0).getReg(); 2460 Register Src = MI.getOperand(1).getReg(); 2461 LLT DstTy = MRI.getType(Dst); 2462 LLT SrcTy = MRI.getType(Src); 2463 2464 if (SrcTy.isVector()) { 2465 LLT SrcEltTy = SrcTy.getElementType(); 2466 SmallVector<Register, 8> SrcRegs; 2467 2468 if (DstTy.isVector()) { 2469 int NumDstElt = DstTy.getNumElements(); 2470 int NumSrcElt = SrcTy.getNumElements(); 2471 2472 LLT DstEltTy = DstTy.getElementType(); 2473 LLT DstCastTy = DstEltTy; // Intermediate bitcast result type 2474 LLT SrcPartTy = SrcEltTy; // Original unmerge result type. 2475 2476 // If there's an element size mismatch, insert intermediate casts to match 2477 // the result element type. 2478 if (NumSrcElt < NumDstElt) { // Source element type is larger. 2479 // %1:_(<4 x s8>) = G_BITCAST %0:_(<2 x s16>) 2480 // 2481 // => 2482 // 2483 // %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0 2484 // %3:_(<2 x s8>) = G_BITCAST %2 2485 // %4:_(<2 x s8>) = G_BITCAST %3 2486 // %1:_(<4 x s16>) = G_CONCAT_VECTORS %3, %4 2487 DstCastTy = LLT::fixed_vector(NumDstElt / NumSrcElt, DstEltTy); 2488 SrcPartTy = SrcEltTy; 2489 } else if (NumSrcElt > NumDstElt) { // Source element type is smaller. 2490 // 2491 // %1:_(<2 x s16>) = G_BITCAST %0:_(<4 x s8>) 2492 // 2493 // => 2494 // 2495 // %2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %0 2496 // %3:_(s16) = G_BITCAST %2 2497 // %4:_(s16) = G_BITCAST %3 2498 // %1:_(<2 x s16>) = G_BUILD_VECTOR %3, %4 2499 SrcPartTy = LLT::fixed_vector(NumSrcElt / NumDstElt, SrcEltTy); 2500 DstCastTy = DstEltTy; 2501 } 2502 2503 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcPartTy); 2504 for (Register &SrcReg : SrcRegs) 2505 SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); 2506 } else 2507 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcEltTy); 2508 2509 MIRBuilder.buildMerge(Dst, SrcRegs); 2510 MI.eraseFromParent(); 2511 return Legalized; 2512 } 2513 2514 if (DstTy.isVector()) { 2515 SmallVector<Register, 8> SrcRegs; 2516 getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType()); 2517 MIRBuilder.buildMerge(Dst, SrcRegs); 2518 MI.eraseFromParent(); 2519 return Legalized; 2520 } 2521 2522 return UnableToLegalize; 2523 } 2524 2525 /// Figure out the bit offset into a register when coercing a vector index for 2526 /// the wide element type. This is only for the case when promoting vector to 2527 /// one with larger elements. 2528 // 2529 /// 2530 /// %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2531 /// %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2532 static Register getBitcastWiderVectorElementOffset(MachineIRBuilder &B, 2533 Register Idx, 2534 unsigned NewEltSize, 2535 unsigned OldEltSize) { 2536 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2537 LLT IdxTy = B.getMRI()->getType(Idx); 2538 2539 // Now figure out the amount we need to shift to get the target bits. 2540 auto OffsetMask = B.buildConstant( 2541 IdxTy, ~(APInt::getAllOnesValue(IdxTy.getSizeInBits()) << Log2EltRatio)); 2542 auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask); 2543 return B.buildShl(IdxTy, OffsetIdx, 2544 B.buildConstant(IdxTy, Log2_32(OldEltSize))).getReg(0); 2545 } 2546 2547 /// Perform a G_EXTRACT_VECTOR_ELT in a different sized vector element. If this 2548 /// is casting to a vector with a smaller element size, perform multiple element 2549 /// extracts and merge the results. If this is coercing to a vector with larger 2550 /// elements, index the bitcasted vector and extract the target element with bit 2551 /// operations. This is intended to force the indexing in the native register 2552 /// size for architectures that can dynamically index the register file. 2553 LegalizerHelper::LegalizeResult 2554 LegalizerHelper::bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx, 2555 LLT CastTy) { 2556 if (TypeIdx != 1) 2557 return UnableToLegalize; 2558 2559 Register Dst = MI.getOperand(0).getReg(); 2560 Register SrcVec = MI.getOperand(1).getReg(); 2561 Register Idx = MI.getOperand(2).getReg(); 2562 LLT SrcVecTy = MRI.getType(SrcVec); 2563 LLT IdxTy = MRI.getType(Idx); 2564 2565 LLT SrcEltTy = SrcVecTy.getElementType(); 2566 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2567 unsigned OldNumElts = SrcVecTy.getNumElements(); 2568 2569 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2570 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2571 2572 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2573 const unsigned OldEltSize = SrcEltTy.getSizeInBits(); 2574 if (NewNumElts > OldNumElts) { 2575 // Decreasing the vector element size 2576 // 2577 // e.g. i64 = extract_vector_elt x:v2i64, y:i32 2578 // => 2579 // v4i32:castx = bitcast x:v2i64 2580 // 2581 // i64 = bitcast 2582 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))), 2583 // (i32 (extract_vector_elt castx, (2 * y + 1))) 2584 // 2585 if (NewNumElts % OldNumElts != 0) 2586 return UnableToLegalize; 2587 2588 // Type of the intermediate result vector. 2589 const unsigned NewEltsPerOldElt = NewNumElts / OldNumElts; 2590 LLT MidTy = 2591 LLT::scalarOrVector(ElementCount::getFixed(NewEltsPerOldElt), NewEltTy); 2592 2593 auto NewEltsPerOldEltK = MIRBuilder.buildConstant(IdxTy, NewEltsPerOldElt); 2594 2595 SmallVector<Register, 8> NewOps(NewEltsPerOldElt); 2596 auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, Idx, NewEltsPerOldEltK); 2597 2598 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) { 2599 auto IdxOffset = MIRBuilder.buildConstant(IdxTy, I); 2600 auto TmpIdx = MIRBuilder.buildAdd(IdxTy, NewBaseIdx, IdxOffset); 2601 auto Elt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, TmpIdx); 2602 NewOps[I] = Elt.getReg(0); 2603 } 2604 2605 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); 2606 MIRBuilder.buildBitcast(Dst, NewVec); 2607 MI.eraseFromParent(); 2608 return Legalized; 2609 } 2610 2611 if (NewNumElts < OldNumElts) { 2612 if (NewEltSize % OldEltSize != 0) 2613 return UnableToLegalize; 2614 2615 // This only depends on powers of 2 because we use bit tricks to figure out 2616 // the bit offset we need to shift to get the target element. A general 2617 // expansion could emit division/multiply. 2618 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2619 return UnableToLegalize; 2620 2621 // Increasing the vector element size. 2622 // %elt:_(small_elt) = G_EXTRACT_VECTOR_ELT %vec:_(<N x small_elt>), %idx 2623 // 2624 // => 2625 // 2626 // %cast = G_BITCAST %vec 2627 // %scaled_idx = G_LSHR %idx, Log2(DstEltSize / SrcEltSize) 2628 // %wide_elt = G_EXTRACT_VECTOR_ELT %cast, %scaled_idx 2629 // %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2630 // %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2631 // %elt_bits = G_LSHR %wide_elt, %offset_bits 2632 // %elt = G_TRUNC %elt_bits 2633 2634 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2635 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2636 2637 // Divide to get the index in the wider element type. 2638 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2639 2640 Register WideElt = CastVec; 2641 if (CastTy.isVector()) { 2642 WideElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2643 ScaledIdx).getReg(0); 2644 } 2645 2646 // Compute the bit offset into the register of the target element. 2647 Register OffsetBits = getBitcastWiderVectorElementOffset( 2648 MIRBuilder, Idx, NewEltSize, OldEltSize); 2649 2650 // Shift the wide element to get the target element. 2651 auto ExtractedBits = MIRBuilder.buildLShr(NewEltTy, WideElt, OffsetBits); 2652 MIRBuilder.buildTrunc(Dst, ExtractedBits); 2653 MI.eraseFromParent(); 2654 return Legalized; 2655 } 2656 2657 return UnableToLegalize; 2658 } 2659 2660 /// Emit code to insert \p InsertReg into \p TargetRet at \p OffsetBits in \p 2661 /// TargetReg, while preserving other bits in \p TargetReg. 2662 /// 2663 /// (InsertReg << Offset) | (TargetReg & ~(-1 >> InsertReg.size()) << Offset) 2664 static Register buildBitFieldInsert(MachineIRBuilder &B, 2665 Register TargetReg, Register InsertReg, 2666 Register OffsetBits) { 2667 LLT TargetTy = B.getMRI()->getType(TargetReg); 2668 LLT InsertTy = B.getMRI()->getType(InsertReg); 2669 auto ZextVal = B.buildZExt(TargetTy, InsertReg); 2670 auto ShiftedInsertVal = B.buildShl(TargetTy, ZextVal, OffsetBits); 2671 2672 // Produce a bitmask of the value to insert 2673 auto EltMask = B.buildConstant( 2674 TargetTy, APInt::getLowBitsSet(TargetTy.getSizeInBits(), 2675 InsertTy.getSizeInBits())); 2676 // Shift it into position 2677 auto ShiftedMask = B.buildShl(TargetTy, EltMask, OffsetBits); 2678 auto InvShiftedMask = B.buildNot(TargetTy, ShiftedMask); 2679 2680 // Clear out the bits in the wide element 2681 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); 2682 2683 // The value to insert has all zeros already, so stick it into the masked 2684 // wide element. 2685 return B.buildOr(TargetTy, MaskedOldElt, ShiftedInsertVal).getReg(0); 2686 } 2687 2688 /// Perform a G_INSERT_VECTOR_ELT in a different sized vector element. If this 2689 /// is increasing the element size, perform the indexing in the target element 2690 /// type, and use bit operations to insert at the element position. This is 2691 /// intended for architectures that can dynamically index the register file and 2692 /// want to force indexing in the native register size. 2693 LegalizerHelper::LegalizeResult 2694 LegalizerHelper::bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, 2695 LLT CastTy) { 2696 if (TypeIdx != 0) 2697 return UnableToLegalize; 2698 2699 Register Dst = MI.getOperand(0).getReg(); 2700 Register SrcVec = MI.getOperand(1).getReg(); 2701 Register Val = MI.getOperand(2).getReg(); 2702 Register Idx = MI.getOperand(3).getReg(); 2703 2704 LLT VecTy = MRI.getType(Dst); 2705 LLT IdxTy = MRI.getType(Idx); 2706 2707 LLT VecEltTy = VecTy.getElementType(); 2708 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2709 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2710 const unsigned OldEltSize = VecEltTy.getSizeInBits(); 2711 2712 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2713 unsigned OldNumElts = VecTy.getNumElements(); 2714 2715 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2716 if (NewNumElts < OldNumElts) { 2717 if (NewEltSize % OldEltSize != 0) 2718 return UnableToLegalize; 2719 2720 // This only depends on powers of 2 because we use bit tricks to figure out 2721 // the bit offset we need to shift to get the target element. A general 2722 // expansion could emit division/multiply. 2723 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2724 return UnableToLegalize; 2725 2726 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2727 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2728 2729 // Divide to get the index in the wider element type. 2730 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2731 2732 Register ExtractedElt = CastVec; 2733 if (CastTy.isVector()) { 2734 ExtractedElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2735 ScaledIdx).getReg(0); 2736 } 2737 2738 // Compute the bit offset into the register of the target element. 2739 Register OffsetBits = getBitcastWiderVectorElementOffset( 2740 MIRBuilder, Idx, NewEltSize, OldEltSize); 2741 2742 Register InsertedElt = buildBitFieldInsert(MIRBuilder, ExtractedElt, 2743 Val, OffsetBits); 2744 if (CastTy.isVector()) { 2745 InsertedElt = MIRBuilder.buildInsertVectorElement( 2746 CastTy, CastVec, InsertedElt, ScaledIdx).getReg(0); 2747 } 2748 2749 MIRBuilder.buildBitcast(Dst, InsertedElt); 2750 MI.eraseFromParent(); 2751 return Legalized; 2752 } 2753 2754 return UnableToLegalize; 2755 } 2756 2757 LegalizerHelper::LegalizeResult 2758 LegalizerHelper::lowerLoad(MachineInstr &MI) { 2759 // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT 2760 Register DstReg = MI.getOperand(0).getReg(); 2761 Register PtrReg = MI.getOperand(1).getReg(); 2762 LLT DstTy = MRI.getType(DstReg); 2763 MachineMemOperand &MMO = **MI.memoperands_begin(); 2764 LLT MemTy = MMO.getMemoryType(); 2765 MachineFunction &MF = MIRBuilder.getMF(); 2766 if (MemTy.isVector()) 2767 return UnableToLegalize; 2768 2769 unsigned MemSizeInBits = MemTy.getSizeInBits(); 2770 unsigned MemStoreSizeInBits = 8 * MemTy.getSizeInBytes(); 2771 2772 if (MemSizeInBits != MemStoreSizeInBits) { 2773 // Promote to a byte-sized load if not loading an integral number of 2774 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 2775 LLT WideMemTy = LLT::scalar(MemStoreSizeInBits); 2776 MachineMemOperand *NewMMO = 2777 MF.getMachineMemOperand(&MMO, MMO.getPointerInfo(), WideMemTy); 2778 2779 Register LoadReg = DstReg; 2780 LLT LoadTy = DstTy; 2781 2782 // If this wasn't already an extending load, we need to widen the result 2783 // register to avoid creating a load with a narrower result than the source. 2784 if (MemStoreSizeInBits > DstTy.getSizeInBits()) { 2785 LoadTy = WideMemTy; 2786 LoadReg = MRI.createGenericVirtualRegister(WideMemTy); 2787 } 2788 2789 if (MI.getOpcode() == TargetOpcode::G_SEXTLOAD) { 2790 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); 2791 MIRBuilder.buildSExtInReg(LoadReg, NewLoad, MemSizeInBits); 2792 } else if (MI.getOpcode() == TargetOpcode::G_ZEXTLOAD || 2793 WideMemTy == DstTy) { 2794 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); 2795 // The extra bits are guaranteed to be zero, since we stored them that 2796 // way. A zext load from Wide thus automatically gives zext from MemVT. 2797 MIRBuilder.buildAssertZExt(LoadReg, NewLoad, MemSizeInBits); 2798 } else { 2799 MIRBuilder.buildLoad(LoadReg, PtrReg, *NewMMO); 2800 } 2801 2802 if (DstTy != LoadTy) 2803 MIRBuilder.buildTrunc(DstReg, LoadReg); 2804 2805 MI.eraseFromParent(); 2806 return Legalized; 2807 } 2808 2809 if (DstTy.getSizeInBits() != MMO.getSizeInBits()) 2810 return UnableToLegalize; 2811 2812 if (MI.getOpcode() == TargetOpcode::G_LOAD) { 2813 // This load needs splitting into power of 2 sized loads. 2814 if (DstTy.isVector()) 2815 return UnableToLegalize; 2816 if (isPowerOf2_32(DstTy.getSizeInBits())) 2817 return UnableToLegalize; // Don't know what we're being asked to do. 2818 2819 // Our strategy here is to generate anyextending loads for the smaller 2820 // types up to next power-2 result type, and then combine the two larger 2821 // result values together, before truncating back down to the non-pow-2 2822 // type. 2823 // E.g. v1 = i24 load => 2824 // v2 = i32 zextload (2 byte) 2825 // v3 = i32 load (1 byte) 2826 // v4 = i32 shl v3, 16 2827 // v5 = i32 or v4, v2 2828 // v1 = i24 trunc v5 2829 // By doing this we generate the correct truncate which should get 2830 // combined away as an artifact with a matching extend. 2831 uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits()); 2832 uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize; 2833 2834 MachineFunction &MF = MIRBuilder.getMF(); 2835 MachineMemOperand *LargeMMO = 2836 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2837 MachineMemOperand *SmallMMO = MF.getMachineMemOperand( 2838 &MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2839 2840 LLT PtrTy = MRI.getType(PtrReg); 2841 unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits()); 2842 LLT AnyExtTy = LLT::scalar(AnyExtSize); 2843 auto LargeLoad = MIRBuilder.buildLoadInstr( 2844 TargetOpcode::G_ZEXTLOAD, AnyExtTy, PtrReg, *LargeMMO); 2845 2846 auto OffsetCst = MIRBuilder.buildConstant( 2847 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2848 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2849 auto SmallPtr = 2850 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); 2851 auto SmallLoad = MIRBuilder.buildLoad(AnyExtTy, SmallPtr, 2852 *SmallMMO); 2853 2854 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize); 2855 auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt); 2856 auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad); 2857 MIRBuilder.buildTrunc(DstReg, {Or}); 2858 MI.eraseFromParent(); 2859 return Legalized; 2860 } 2861 2862 return UnableToLegalize; 2863 } 2864 2865 LegalizerHelper::LegalizeResult 2866 LegalizerHelper::lowerStore(MachineInstr &MI) { 2867 // Lower a non-power of 2 store into multiple pow-2 stores. 2868 // E.g. split an i24 store into an i16 store + i8 store. 2869 // We do this by first extending the stored value to the next largest power 2870 // of 2 type, and then using truncating stores to store the components. 2871 // By doing this, likewise with G_LOAD, generate an extend that can be 2872 // artifact-combined away instead of leaving behind extracts. 2873 Register SrcReg = MI.getOperand(0).getReg(); 2874 Register PtrReg = MI.getOperand(1).getReg(); 2875 LLT SrcTy = MRI.getType(SrcReg); 2876 MachineFunction &MF = MIRBuilder.getMF(); 2877 MachineMemOperand &MMO = **MI.memoperands_begin(); 2878 LLT MemTy = MMO.getMemoryType(); 2879 2880 if (SrcTy.isVector()) 2881 return UnableToLegalize; 2882 2883 unsigned StoreWidth = MemTy.getSizeInBits(); 2884 unsigned StoreSizeInBits = 8 * MemTy.getSizeInBytes(); 2885 2886 if (StoreWidth != StoreSizeInBits) { 2887 // Promote to a byte-sized store with upper bits zero if not 2888 // storing an integral number of bytes. For example, promote 2889 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2890 LLT WideTy = LLT::scalar(StoreSizeInBits); 2891 2892 if (StoreSizeInBits > SrcTy.getSizeInBits()) { 2893 // Avoid creating a store with a narrower source than result. 2894 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); 2895 SrcTy = WideTy; 2896 } 2897 2898 auto ZextInReg = MIRBuilder.buildZExtInReg(SrcTy, SrcReg, StoreWidth); 2899 2900 MachineMemOperand *NewMMO = 2901 MF.getMachineMemOperand(&MMO, MMO.getPointerInfo(), WideTy); 2902 MIRBuilder.buildStore(ZextInReg, PtrReg, *NewMMO); 2903 MI.eraseFromParent(); 2904 return Legalized; 2905 } 2906 2907 if (isPowerOf2_32(MemTy.getSizeInBits())) 2908 return UnableToLegalize; // Don't know what we're being asked to do. 2909 2910 // Extend to the next pow-2. 2911 const LLT ExtendTy = LLT::scalar(NextPowerOf2(MemTy.getSizeInBits())); 2912 auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg); 2913 2914 // Obtain the smaller value by shifting away the larger value. 2915 uint64_t LargeSplitSize = PowerOf2Floor(MemTy.getSizeInBits()); 2916 uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize; 2917 auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize); 2918 auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt); 2919 2920 // Generate the PtrAdd and truncating stores. 2921 LLT PtrTy = MRI.getType(PtrReg); 2922 auto OffsetCst = MIRBuilder.buildConstant( 2923 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2924 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2925 auto SmallPtr = 2926 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); 2927 2928 MachineMemOperand *LargeMMO = 2929 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2930 MachineMemOperand *SmallMMO = 2931 MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2932 MIRBuilder.buildStore(ExtVal, PtrReg, *LargeMMO); 2933 MIRBuilder.buildStore(SmallVal, SmallPtr, *SmallMMO); 2934 MI.eraseFromParent(); 2935 return Legalized; 2936 } 2937 2938 LegalizerHelper::LegalizeResult 2939 LegalizerHelper::bitcast(MachineInstr &MI, unsigned TypeIdx, LLT CastTy) { 2940 switch (MI.getOpcode()) { 2941 case TargetOpcode::G_LOAD: { 2942 if (TypeIdx != 0) 2943 return UnableToLegalize; 2944 2945 Observer.changingInstr(MI); 2946 bitcastDst(MI, CastTy, 0); 2947 Observer.changedInstr(MI); 2948 return Legalized; 2949 } 2950 case TargetOpcode::G_STORE: { 2951 if (TypeIdx != 0) 2952 return UnableToLegalize; 2953 2954 Observer.changingInstr(MI); 2955 bitcastSrc(MI, CastTy, 0); 2956 Observer.changedInstr(MI); 2957 return Legalized; 2958 } 2959 case TargetOpcode::G_SELECT: { 2960 if (TypeIdx != 0) 2961 return UnableToLegalize; 2962 2963 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) { 2964 LLVM_DEBUG( 2965 dbgs() << "bitcast action not implemented for vector select\n"); 2966 return UnableToLegalize; 2967 } 2968 2969 Observer.changingInstr(MI); 2970 bitcastSrc(MI, CastTy, 2); 2971 bitcastSrc(MI, CastTy, 3); 2972 bitcastDst(MI, CastTy, 0); 2973 Observer.changedInstr(MI); 2974 return Legalized; 2975 } 2976 case TargetOpcode::G_AND: 2977 case TargetOpcode::G_OR: 2978 case TargetOpcode::G_XOR: { 2979 Observer.changingInstr(MI); 2980 bitcastSrc(MI, CastTy, 1); 2981 bitcastSrc(MI, CastTy, 2); 2982 bitcastDst(MI, CastTy, 0); 2983 Observer.changedInstr(MI); 2984 return Legalized; 2985 } 2986 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 2987 return bitcastExtractVectorElt(MI, TypeIdx, CastTy); 2988 case TargetOpcode::G_INSERT_VECTOR_ELT: 2989 return bitcastInsertVectorElt(MI, TypeIdx, CastTy); 2990 default: 2991 return UnableToLegalize; 2992 } 2993 } 2994 2995 // Legalize an instruction by changing the opcode in place. 2996 void LegalizerHelper::changeOpcode(MachineInstr &MI, unsigned NewOpcode) { 2997 Observer.changingInstr(MI); 2998 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); 2999 Observer.changedInstr(MI); 3000 } 3001 3002 LegalizerHelper::LegalizeResult 3003 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) { 3004 using namespace TargetOpcode; 3005 3006 switch(MI.getOpcode()) { 3007 default: 3008 return UnableToLegalize; 3009 case TargetOpcode::G_BITCAST: 3010 return lowerBitcast(MI); 3011 case TargetOpcode::G_SREM: 3012 case TargetOpcode::G_UREM: { 3013 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3014 auto Quot = 3015 MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {Ty}, 3016 {MI.getOperand(1), MI.getOperand(2)}); 3017 3018 auto Prod = MIRBuilder.buildMul(Ty, Quot, MI.getOperand(2)); 3019 MIRBuilder.buildSub(MI.getOperand(0), MI.getOperand(1), Prod); 3020 MI.eraseFromParent(); 3021 return Legalized; 3022 } 3023 case TargetOpcode::G_SADDO: 3024 case TargetOpcode::G_SSUBO: 3025 return lowerSADDO_SSUBO(MI); 3026 case TargetOpcode::G_UMULH: 3027 case TargetOpcode::G_SMULH: 3028 return lowerSMULH_UMULH(MI); 3029 case TargetOpcode::G_SMULO: 3030 case TargetOpcode::G_UMULO: { 3031 // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the 3032 // result. 3033 Register Res = MI.getOperand(0).getReg(); 3034 Register Overflow = MI.getOperand(1).getReg(); 3035 Register LHS = MI.getOperand(2).getReg(); 3036 Register RHS = MI.getOperand(3).getReg(); 3037 LLT Ty = MRI.getType(Res); 3038 3039 unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO 3040 ? TargetOpcode::G_SMULH 3041 : TargetOpcode::G_UMULH; 3042 3043 Observer.changingInstr(MI); 3044 const auto &TII = MIRBuilder.getTII(); 3045 MI.setDesc(TII.get(TargetOpcode::G_MUL)); 3046 MI.RemoveOperand(1); 3047 Observer.changedInstr(MI); 3048 3049 auto HiPart = MIRBuilder.buildInstr(Opcode, {Ty}, {LHS, RHS}); 3050 auto Zero = MIRBuilder.buildConstant(Ty, 0); 3051 3052 // Move insert point forward so we can use the Res register if needed. 3053 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 3054 3055 // For *signed* multiply, overflow is detected by checking: 3056 // (hi != (lo >> bitwidth-1)) 3057 if (Opcode == TargetOpcode::G_SMULH) { 3058 auto ShiftAmt = MIRBuilder.buildConstant(Ty, Ty.getSizeInBits() - 1); 3059 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); 3060 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted); 3061 } else { 3062 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero); 3063 } 3064 return Legalized; 3065 } 3066 case TargetOpcode::G_FNEG: { 3067 Register Res = MI.getOperand(0).getReg(); 3068 LLT Ty = MRI.getType(Res); 3069 3070 // TODO: Handle vector types once we are able to 3071 // represent them. 3072 if (Ty.isVector()) 3073 return UnableToLegalize; 3074 auto SignMask = 3075 MIRBuilder.buildConstant(Ty, APInt::getSignMask(Ty.getSizeInBits())); 3076 Register SubByReg = MI.getOperand(1).getReg(); 3077 MIRBuilder.buildXor(Res, SubByReg, SignMask); 3078 MI.eraseFromParent(); 3079 return Legalized; 3080 } 3081 case TargetOpcode::G_FSUB: { 3082 Register Res = MI.getOperand(0).getReg(); 3083 LLT Ty = MRI.getType(Res); 3084 3085 // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)). 3086 // First, check if G_FNEG is marked as Lower. If so, we may 3087 // end up with an infinite loop as G_FSUB is used to legalize G_FNEG. 3088 if (LI.getAction({G_FNEG, {Ty}}).Action == Lower) 3089 return UnableToLegalize; 3090 Register LHS = MI.getOperand(1).getReg(); 3091 Register RHS = MI.getOperand(2).getReg(); 3092 Register Neg = MRI.createGenericVirtualRegister(Ty); 3093 MIRBuilder.buildFNeg(Neg, RHS); 3094 MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags()); 3095 MI.eraseFromParent(); 3096 return Legalized; 3097 } 3098 case TargetOpcode::G_FMAD: 3099 return lowerFMad(MI); 3100 case TargetOpcode::G_FFLOOR: 3101 return lowerFFloor(MI); 3102 case TargetOpcode::G_INTRINSIC_ROUND: 3103 return lowerIntrinsicRound(MI); 3104 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 3105 // Since round even is the assumed rounding mode for unconstrained FP 3106 // operations, rint and roundeven are the same operation. 3107 changeOpcode(MI, TargetOpcode::G_FRINT); 3108 return Legalized; 3109 } 3110 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: { 3111 Register OldValRes = MI.getOperand(0).getReg(); 3112 Register SuccessRes = MI.getOperand(1).getReg(); 3113 Register Addr = MI.getOperand(2).getReg(); 3114 Register CmpVal = MI.getOperand(3).getReg(); 3115 Register NewVal = MI.getOperand(4).getReg(); 3116 MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal, 3117 **MI.memoperands_begin()); 3118 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal); 3119 MI.eraseFromParent(); 3120 return Legalized; 3121 } 3122 case TargetOpcode::G_LOAD: 3123 case TargetOpcode::G_SEXTLOAD: 3124 case TargetOpcode::G_ZEXTLOAD: 3125 return lowerLoad(MI); 3126 case TargetOpcode::G_STORE: 3127 return lowerStore(MI); 3128 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 3129 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 3130 case TargetOpcode::G_CTLZ: 3131 case TargetOpcode::G_CTTZ: 3132 case TargetOpcode::G_CTPOP: 3133 return lowerBitCount(MI); 3134 case G_UADDO: { 3135 Register Res = MI.getOperand(0).getReg(); 3136 Register CarryOut = MI.getOperand(1).getReg(); 3137 Register LHS = MI.getOperand(2).getReg(); 3138 Register RHS = MI.getOperand(3).getReg(); 3139 3140 MIRBuilder.buildAdd(Res, LHS, RHS); 3141 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS); 3142 3143 MI.eraseFromParent(); 3144 return Legalized; 3145 } 3146 case G_UADDE: { 3147 Register Res = MI.getOperand(0).getReg(); 3148 Register CarryOut = MI.getOperand(1).getReg(); 3149 Register LHS = MI.getOperand(2).getReg(); 3150 Register RHS = MI.getOperand(3).getReg(); 3151 Register CarryIn = MI.getOperand(4).getReg(); 3152 LLT Ty = MRI.getType(Res); 3153 3154 auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS); 3155 auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); 3156 MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn); 3157 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS); 3158 3159 MI.eraseFromParent(); 3160 return Legalized; 3161 } 3162 case G_USUBO: { 3163 Register Res = MI.getOperand(0).getReg(); 3164 Register BorrowOut = MI.getOperand(1).getReg(); 3165 Register LHS = MI.getOperand(2).getReg(); 3166 Register RHS = MI.getOperand(3).getReg(); 3167 3168 MIRBuilder.buildSub(Res, LHS, RHS); 3169 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS); 3170 3171 MI.eraseFromParent(); 3172 return Legalized; 3173 } 3174 case G_USUBE: { 3175 Register Res = MI.getOperand(0).getReg(); 3176 Register BorrowOut = MI.getOperand(1).getReg(); 3177 Register LHS = MI.getOperand(2).getReg(); 3178 Register RHS = MI.getOperand(3).getReg(); 3179 Register BorrowIn = MI.getOperand(4).getReg(); 3180 const LLT CondTy = MRI.getType(BorrowOut); 3181 const LLT Ty = MRI.getType(Res); 3182 3183 auto TmpRes = MIRBuilder.buildSub(Ty, LHS, RHS); 3184 auto ZExtBorrowIn = MIRBuilder.buildZExt(Ty, BorrowIn); 3185 MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn); 3186 3187 auto LHS_EQ_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, LHS, RHS); 3188 auto LHS_ULT_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, LHS, RHS); 3189 MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS); 3190 3191 MI.eraseFromParent(); 3192 return Legalized; 3193 } 3194 case G_UITOFP: 3195 return lowerUITOFP(MI); 3196 case G_SITOFP: 3197 return lowerSITOFP(MI); 3198 case G_FPTOUI: 3199 return lowerFPTOUI(MI); 3200 case G_FPTOSI: 3201 return lowerFPTOSI(MI); 3202 case G_FPTRUNC: 3203 return lowerFPTRUNC(MI); 3204 case G_FPOWI: 3205 return lowerFPOWI(MI); 3206 case G_SMIN: 3207 case G_SMAX: 3208 case G_UMIN: 3209 case G_UMAX: 3210 return lowerMinMax(MI); 3211 case G_FCOPYSIGN: 3212 return lowerFCopySign(MI); 3213 case G_FMINNUM: 3214 case G_FMAXNUM: 3215 return lowerFMinNumMaxNum(MI); 3216 case G_MERGE_VALUES: 3217 return lowerMergeValues(MI); 3218 case G_UNMERGE_VALUES: 3219 return lowerUnmergeValues(MI); 3220 case TargetOpcode::G_SEXT_INREG: { 3221 assert(MI.getOperand(2).isImm() && "Expected immediate"); 3222 int64_t SizeInBits = MI.getOperand(2).getImm(); 3223 3224 Register DstReg = MI.getOperand(0).getReg(); 3225 Register SrcReg = MI.getOperand(1).getReg(); 3226 LLT DstTy = MRI.getType(DstReg); 3227 Register TmpRes = MRI.createGenericVirtualRegister(DstTy); 3228 3229 auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits); 3230 MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0)); 3231 MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0)); 3232 MI.eraseFromParent(); 3233 return Legalized; 3234 } 3235 case G_EXTRACT_VECTOR_ELT: 3236 case G_INSERT_VECTOR_ELT: 3237 return lowerExtractInsertVectorElt(MI); 3238 case G_SHUFFLE_VECTOR: 3239 return lowerShuffleVector(MI); 3240 case G_DYN_STACKALLOC: 3241 return lowerDynStackAlloc(MI); 3242 case G_EXTRACT: 3243 return lowerExtract(MI); 3244 case G_INSERT: 3245 return lowerInsert(MI); 3246 case G_BSWAP: 3247 return lowerBswap(MI); 3248 case G_BITREVERSE: 3249 return lowerBitreverse(MI); 3250 case G_READ_REGISTER: 3251 case G_WRITE_REGISTER: 3252 return lowerReadWriteRegister(MI); 3253 case G_UADDSAT: 3254 case G_USUBSAT: { 3255 // Try to make a reasonable guess about which lowering strategy to use. The 3256 // target can override this with custom lowering and calling the 3257 // implementation functions. 3258 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3259 if (LI.isLegalOrCustom({G_UMIN, Ty})) 3260 return lowerAddSubSatToMinMax(MI); 3261 return lowerAddSubSatToAddoSubo(MI); 3262 } 3263 case G_SADDSAT: 3264 case G_SSUBSAT: { 3265 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3266 3267 // FIXME: It would probably make more sense to see if G_SADDO is preferred, 3268 // since it's a shorter expansion. However, we would need to figure out the 3269 // preferred boolean type for the carry out for the query. 3270 if (LI.isLegalOrCustom({G_SMIN, Ty}) && LI.isLegalOrCustom({G_SMAX, Ty})) 3271 return lowerAddSubSatToMinMax(MI); 3272 return lowerAddSubSatToAddoSubo(MI); 3273 } 3274 case G_SSHLSAT: 3275 case G_USHLSAT: 3276 return lowerShlSat(MI); 3277 case G_ABS: 3278 return lowerAbsToAddXor(MI); 3279 case G_SELECT: 3280 return lowerSelect(MI); 3281 case G_SDIVREM: 3282 case G_UDIVREM: 3283 return lowerDIVREM(MI); 3284 case G_FSHL: 3285 case G_FSHR: 3286 return lowerFunnelShift(MI); 3287 case G_ROTL: 3288 case G_ROTR: 3289 return lowerRotate(MI); 3290 } 3291 } 3292 3293 Align LegalizerHelper::getStackTemporaryAlignment(LLT Ty, 3294 Align MinAlign) const { 3295 // FIXME: We're missing a way to go back from LLT to llvm::Type to query the 3296 // datalayout for the preferred alignment. Also there should be a target hook 3297 // for this to allow targets to reduce the alignment and ignore the 3298 // datalayout. e.g. AMDGPU should always use a 4-byte alignment, regardless of 3299 // the type. 3300 return std::max(Align(PowerOf2Ceil(Ty.getSizeInBytes())), MinAlign); 3301 } 3302 3303 MachineInstrBuilder 3304 LegalizerHelper::createStackTemporary(TypeSize Bytes, Align Alignment, 3305 MachinePointerInfo &PtrInfo) { 3306 MachineFunction &MF = MIRBuilder.getMF(); 3307 const DataLayout &DL = MIRBuilder.getDataLayout(); 3308 int FrameIdx = MF.getFrameInfo().CreateStackObject(Bytes, Alignment, false); 3309 3310 unsigned AddrSpace = DL.getAllocaAddrSpace(); 3311 LLT FramePtrTy = LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace)); 3312 3313 PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIdx); 3314 return MIRBuilder.buildFrameIndex(FramePtrTy, FrameIdx); 3315 } 3316 3317 static Register clampDynamicVectorIndex(MachineIRBuilder &B, Register IdxReg, 3318 LLT VecTy) { 3319 int64_t IdxVal; 3320 if (mi_match(IdxReg, *B.getMRI(), m_ICst(IdxVal))) 3321 return IdxReg; 3322 3323 LLT IdxTy = B.getMRI()->getType(IdxReg); 3324 unsigned NElts = VecTy.getNumElements(); 3325 if (isPowerOf2_32(NElts)) { 3326 APInt Imm = APInt::getLowBitsSet(IdxTy.getSizeInBits(), Log2_32(NElts)); 3327 return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0); 3328 } 3329 3330 return B.buildUMin(IdxTy, IdxReg, B.buildConstant(IdxTy, NElts - 1)) 3331 .getReg(0); 3332 } 3333 3334 Register LegalizerHelper::getVectorElementPointer(Register VecPtr, LLT VecTy, 3335 Register Index) { 3336 LLT EltTy = VecTy.getElementType(); 3337 3338 // Calculate the element offset and add it to the pointer. 3339 unsigned EltSize = EltTy.getSizeInBits() / 8; // FIXME: should be ABI size. 3340 assert(EltSize * 8 == EltTy.getSizeInBits() && 3341 "Converting bits to bytes lost precision"); 3342 3343 Index = clampDynamicVectorIndex(MIRBuilder, Index, VecTy); 3344 3345 LLT IdxTy = MRI.getType(Index); 3346 auto Mul = MIRBuilder.buildMul(IdxTy, Index, 3347 MIRBuilder.buildConstant(IdxTy, EltSize)); 3348 3349 LLT PtrTy = MRI.getType(VecPtr); 3350 return MIRBuilder.buildPtrAdd(PtrTy, VecPtr, Mul).getReg(0); 3351 } 3352 3353 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef( 3354 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) { 3355 Register DstReg = MI.getOperand(0).getReg(); 3356 LLT DstTy = MRI.getType(DstReg); 3357 LLT LCMTy = getLCMType(DstTy, NarrowTy); 3358 3359 unsigned NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 3360 3361 auto NewUndef = MIRBuilder.buildUndef(NarrowTy); 3362 SmallVector<Register, 8> Parts(NumParts, NewUndef.getReg(0)); 3363 3364 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3365 MI.eraseFromParent(); 3366 return Legalized; 3367 } 3368 3369 // Handle splitting vector operations which need to have the same number of 3370 // elements in each type index, but each type index may have a different element 3371 // type. 3372 // 3373 // e.g. <4 x s64> = G_SHL <4 x s64>, <4 x s32> -> 3374 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3375 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3376 // 3377 // Also handles some irregular breakdown cases, e.g. 3378 // e.g. <3 x s64> = G_SHL <3 x s64>, <3 x s32> -> 3379 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3380 // s64 = G_SHL s64, s32 3381 LegalizerHelper::LegalizeResult 3382 LegalizerHelper::fewerElementsVectorMultiEltType( 3383 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) { 3384 if (TypeIdx != 0) 3385 return UnableToLegalize; 3386 3387 const LLT NarrowTy0 = NarrowTyArg; 3388 const Register DstReg = MI.getOperand(0).getReg(); 3389 LLT DstTy = MRI.getType(DstReg); 3390 LLT LeftoverTy0; 3391 3392 // All of the operands need to have the same number of elements, so if we can 3393 // determine a type breakdown for the result type, we can for all of the 3394 // source types. 3395 int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first; 3396 if (NumParts < 0) 3397 return UnableToLegalize; 3398 3399 SmallVector<MachineInstrBuilder, 4> NewInsts; 3400 3401 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3402 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3403 3404 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) { 3405 Register SrcReg = MI.getOperand(I).getReg(); 3406 LLT SrcTyI = MRI.getType(SrcReg); 3407 const auto NewEC = NarrowTy0.isVector() ? NarrowTy0.getElementCount() 3408 : ElementCount::getFixed(1); 3409 LLT NarrowTyI = LLT::scalarOrVector(NewEC, SrcTyI.getScalarType()); 3410 LLT LeftoverTyI; 3411 3412 // Split this operand into the requested typed registers, and any leftover 3413 // required to reproduce the original type. 3414 if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs, 3415 LeftoverRegs)) 3416 return UnableToLegalize; 3417 3418 if (I == 1) { 3419 // For the first operand, create an instruction for each part and setup 3420 // the result. 3421 for (Register PartReg : PartRegs) { 3422 Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3423 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3424 .addDef(PartDstReg) 3425 .addUse(PartReg)); 3426 DstRegs.push_back(PartDstReg); 3427 } 3428 3429 for (Register LeftoverReg : LeftoverRegs) { 3430 Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0); 3431 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3432 .addDef(PartDstReg) 3433 .addUse(LeftoverReg)); 3434 LeftoverDstRegs.push_back(PartDstReg); 3435 } 3436 } else { 3437 assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size()); 3438 3439 // Add the newly created operand splits to the existing instructions. The 3440 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3441 // pieces. 3442 unsigned InstCount = 0; 3443 for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J) 3444 NewInsts[InstCount++].addUse(PartRegs[J]); 3445 for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J) 3446 NewInsts[InstCount++].addUse(LeftoverRegs[J]); 3447 } 3448 3449 PartRegs.clear(); 3450 LeftoverRegs.clear(); 3451 } 3452 3453 // Insert the newly built operations and rebuild the result register. 3454 for (auto &MIB : NewInsts) 3455 MIRBuilder.insertInstr(MIB); 3456 3457 insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs); 3458 3459 MI.eraseFromParent(); 3460 return Legalized; 3461 } 3462 3463 LegalizerHelper::LegalizeResult 3464 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx, 3465 LLT NarrowTy) { 3466 if (TypeIdx != 0) 3467 return UnableToLegalize; 3468 3469 Register DstReg = MI.getOperand(0).getReg(); 3470 Register SrcReg = MI.getOperand(1).getReg(); 3471 LLT DstTy = MRI.getType(DstReg); 3472 LLT SrcTy = MRI.getType(SrcReg); 3473 3474 LLT NarrowTy0 = NarrowTy; 3475 LLT NarrowTy1; 3476 unsigned NumParts; 3477 3478 if (NarrowTy.isVector()) { 3479 // Uneven breakdown not handled. 3480 NumParts = DstTy.getNumElements() / NarrowTy.getNumElements(); 3481 if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements()) 3482 return UnableToLegalize; 3483 3484 NarrowTy1 = LLT::vector(NarrowTy.getElementCount(), SrcTy.getElementType()); 3485 } else { 3486 NumParts = DstTy.getNumElements(); 3487 NarrowTy1 = SrcTy.getElementType(); 3488 } 3489 3490 SmallVector<Register, 4> SrcRegs, DstRegs; 3491 extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs); 3492 3493 for (unsigned I = 0; I < NumParts; ++I) { 3494 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3495 MachineInstr *NewInst = 3496 MIRBuilder.buildInstr(MI.getOpcode(), {DstReg}, {SrcRegs[I]}); 3497 3498 NewInst->setFlags(MI.getFlags()); 3499 DstRegs.push_back(DstReg); 3500 } 3501 3502 if (NarrowTy.isVector()) 3503 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3504 else 3505 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3506 3507 MI.eraseFromParent(); 3508 return Legalized; 3509 } 3510 3511 LegalizerHelper::LegalizeResult 3512 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx, 3513 LLT NarrowTy) { 3514 Register DstReg = MI.getOperand(0).getReg(); 3515 Register Src0Reg = MI.getOperand(2).getReg(); 3516 LLT DstTy = MRI.getType(DstReg); 3517 LLT SrcTy = MRI.getType(Src0Reg); 3518 3519 unsigned NumParts; 3520 LLT NarrowTy0, NarrowTy1; 3521 3522 if (TypeIdx == 0) { 3523 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3524 unsigned OldElts = DstTy.getNumElements(); 3525 3526 NarrowTy0 = NarrowTy; 3527 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements(); 3528 NarrowTy1 = NarrowTy.isVector() ? LLT::vector(NarrowTy.getElementCount(), 3529 SrcTy.getScalarSizeInBits()) 3530 : SrcTy.getElementType(); 3531 3532 } else { 3533 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3534 unsigned OldElts = SrcTy.getNumElements(); 3535 3536 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : 3537 NarrowTy.getNumElements(); 3538 NarrowTy0 = 3539 LLT::vector(NarrowTy.getElementCount(), DstTy.getScalarSizeInBits()); 3540 NarrowTy1 = NarrowTy; 3541 } 3542 3543 // FIXME: Don't know how to handle the situation where the small vectors 3544 // aren't all the same size yet. 3545 if (NarrowTy1.isVector() && 3546 NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements()) 3547 return UnableToLegalize; 3548 3549 CmpInst::Predicate Pred 3550 = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 3551 3552 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 3553 extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs); 3554 extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs); 3555 3556 for (unsigned I = 0; I < NumParts; ++I) { 3557 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3558 DstRegs.push_back(DstReg); 3559 3560 if (MI.getOpcode() == TargetOpcode::G_ICMP) 3561 MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3562 else { 3563 MachineInstr *NewCmp 3564 = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3565 NewCmp->setFlags(MI.getFlags()); 3566 } 3567 } 3568 3569 if (NarrowTy1.isVector()) 3570 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3571 else 3572 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3573 3574 MI.eraseFromParent(); 3575 return Legalized; 3576 } 3577 3578 LegalizerHelper::LegalizeResult 3579 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, 3580 LLT NarrowTy) { 3581 Register DstReg = MI.getOperand(0).getReg(); 3582 Register CondReg = MI.getOperand(1).getReg(); 3583 3584 unsigned NumParts = 0; 3585 LLT NarrowTy0, NarrowTy1; 3586 3587 LLT DstTy = MRI.getType(DstReg); 3588 LLT CondTy = MRI.getType(CondReg); 3589 unsigned Size = DstTy.getSizeInBits(); 3590 3591 assert(TypeIdx == 0 || CondTy.isVector()); 3592 3593 if (TypeIdx == 0) { 3594 NarrowTy0 = NarrowTy; 3595 NarrowTy1 = CondTy; 3596 3597 unsigned NarrowSize = NarrowTy0.getSizeInBits(); 3598 // FIXME: Don't know how to handle the situation where the small vectors 3599 // aren't all the same size yet. 3600 if (Size % NarrowSize != 0) 3601 return UnableToLegalize; 3602 3603 NumParts = Size / NarrowSize; 3604 3605 // Need to break down the condition type 3606 if (CondTy.isVector()) { 3607 if (CondTy.getNumElements() == NumParts) 3608 NarrowTy1 = CondTy.getElementType(); 3609 else 3610 NarrowTy1 = 3611 LLT::vector(CondTy.getElementCount().divideCoefficientBy(NumParts), 3612 CondTy.getScalarSizeInBits()); 3613 } 3614 } else { 3615 NumParts = CondTy.getNumElements(); 3616 if (NarrowTy.isVector()) { 3617 // TODO: Handle uneven breakdown. 3618 if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements()) 3619 return UnableToLegalize; 3620 3621 return UnableToLegalize; 3622 } else { 3623 NarrowTy0 = DstTy.getElementType(); 3624 NarrowTy1 = NarrowTy; 3625 } 3626 } 3627 3628 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs; 3629 if (CondTy.isVector()) 3630 extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs); 3631 3632 extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs); 3633 extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs); 3634 3635 for (unsigned i = 0; i < NumParts; ++i) { 3636 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3637 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg, 3638 Src1Regs[i], Src2Regs[i]); 3639 DstRegs.push_back(DstReg); 3640 } 3641 3642 if (NarrowTy0.isVector()) 3643 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3644 else 3645 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3646 3647 MI.eraseFromParent(); 3648 return Legalized; 3649 } 3650 3651 LegalizerHelper::LegalizeResult 3652 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 3653 LLT NarrowTy) { 3654 const Register DstReg = MI.getOperand(0).getReg(); 3655 LLT PhiTy = MRI.getType(DstReg); 3656 LLT LeftoverTy; 3657 3658 // All of the operands need to have the same number of elements, so if we can 3659 // determine a type breakdown for the result type, we can for all of the 3660 // source types. 3661 int NumParts, NumLeftover; 3662 std::tie(NumParts, NumLeftover) 3663 = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy); 3664 if (NumParts < 0) 3665 return UnableToLegalize; 3666 3667 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3668 SmallVector<MachineInstrBuilder, 4> NewInsts; 3669 3670 const int TotalNumParts = NumParts + NumLeftover; 3671 3672 // Insert the new phis in the result block first. 3673 for (int I = 0; I != TotalNumParts; ++I) { 3674 LLT Ty = I < NumParts ? NarrowTy : LeftoverTy; 3675 Register PartDstReg = MRI.createGenericVirtualRegister(Ty); 3676 NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI) 3677 .addDef(PartDstReg)); 3678 if (I < NumParts) 3679 DstRegs.push_back(PartDstReg); 3680 else 3681 LeftoverDstRegs.push_back(PartDstReg); 3682 } 3683 3684 MachineBasicBlock *MBB = MI.getParent(); 3685 MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI()); 3686 insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs); 3687 3688 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3689 3690 // Insert code to extract the incoming values in each predecessor block. 3691 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 3692 PartRegs.clear(); 3693 LeftoverRegs.clear(); 3694 3695 Register SrcReg = MI.getOperand(I).getReg(); 3696 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 3697 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 3698 3699 LLT Unused; 3700 if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs, 3701 LeftoverRegs)) 3702 return UnableToLegalize; 3703 3704 // Add the newly created operand splits to the existing instructions. The 3705 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3706 // pieces. 3707 for (int J = 0; J != TotalNumParts; ++J) { 3708 MachineInstrBuilder MIB = NewInsts[J]; 3709 MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]); 3710 MIB.addMBB(&OpMBB); 3711 } 3712 } 3713 3714 MI.eraseFromParent(); 3715 return Legalized; 3716 } 3717 3718 LegalizerHelper::LegalizeResult 3719 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI, 3720 unsigned TypeIdx, 3721 LLT NarrowTy) { 3722 if (TypeIdx != 1) 3723 return UnableToLegalize; 3724 3725 const int NumDst = MI.getNumOperands() - 1; 3726 const Register SrcReg = MI.getOperand(NumDst).getReg(); 3727 LLT SrcTy = MRI.getType(SrcReg); 3728 3729 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 3730 3731 // TODO: Create sequence of extracts. 3732 if (DstTy == NarrowTy) 3733 return UnableToLegalize; 3734 3735 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3736 if (DstTy == GCDTy) { 3737 // This would just be a copy of the same unmerge. 3738 // TODO: Create extracts, pad with undef and create intermediate merges. 3739 return UnableToLegalize; 3740 } 3741 3742 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 3743 const int NumUnmerge = Unmerge->getNumOperands() - 1; 3744 const int PartsPerUnmerge = NumDst / NumUnmerge; 3745 3746 for (int I = 0; I != NumUnmerge; ++I) { 3747 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 3748 3749 for (int J = 0; J != PartsPerUnmerge; ++J) 3750 MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg()); 3751 MIB.addUse(Unmerge.getReg(I)); 3752 } 3753 3754 MI.eraseFromParent(); 3755 return Legalized; 3756 } 3757 3758 LegalizerHelper::LegalizeResult 3759 LegalizerHelper::fewerElementsVectorMulo(MachineInstr &MI, unsigned TypeIdx, 3760 LLT NarrowTy) { 3761 Register Result = MI.getOperand(0).getReg(); 3762 Register Overflow = MI.getOperand(1).getReg(); 3763 Register LHS = MI.getOperand(2).getReg(); 3764 Register RHS = MI.getOperand(3).getReg(); 3765 3766 LLT SrcTy = MRI.getType(LHS); 3767 if (!SrcTy.isVector()) 3768 return UnableToLegalize; 3769 3770 LLT ElementType = SrcTy.getElementType(); 3771 LLT OverflowElementTy = MRI.getType(Overflow).getElementType(); 3772 const ElementCount NumResult = SrcTy.getElementCount(); 3773 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3774 3775 // Unmerge the operands to smaller parts of GCD type. 3776 auto UnmergeLHS = MIRBuilder.buildUnmerge(GCDTy, LHS); 3777 auto UnmergeRHS = MIRBuilder.buildUnmerge(GCDTy, RHS); 3778 3779 const int NumOps = UnmergeLHS->getNumOperands() - 1; 3780 const ElementCount PartsPerUnmerge = NumResult.divideCoefficientBy(NumOps); 3781 LLT OverflowTy = LLT::scalarOrVector(PartsPerUnmerge, OverflowElementTy); 3782 LLT ResultTy = LLT::scalarOrVector(PartsPerUnmerge, ElementType); 3783 3784 // Perform the operation over unmerged parts. 3785 SmallVector<Register, 8> ResultParts; 3786 SmallVector<Register, 8> OverflowParts; 3787 for (int I = 0; I != NumOps; ++I) { 3788 Register Operand1 = UnmergeLHS->getOperand(I).getReg(); 3789 Register Operand2 = UnmergeRHS->getOperand(I).getReg(); 3790 auto PartMul = MIRBuilder.buildInstr(MI.getOpcode(), {ResultTy, OverflowTy}, 3791 {Operand1, Operand2}); 3792 ResultParts.push_back(PartMul->getOperand(0).getReg()); 3793 OverflowParts.push_back(PartMul->getOperand(1).getReg()); 3794 } 3795 3796 LLT ResultLCMTy = buildLCMMergePieces(SrcTy, NarrowTy, GCDTy, ResultParts); 3797 LLT OverflowLCMTy = 3798 LLT::scalarOrVector(ResultLCMTy.getElementCount(), OverflowElementTy); 3799 3800 // Recombine the pieces to the original result and overflow registers. 3801 buildWidenedRemergeToDst(Result, ResultLCMTy, ResultParts); 3802 buildWidenedRemergeToDst(Overflow, OverflowLCMTy, OverflowParts); 3803 MI.eraseFromParent(); 3804 return Legalized; 3805 } 3806 3807 // Handle FewerElementsVector a G_BUILD_VECTOR or G_CONCAT_VECTORS that produces 3808 // a vector 3809 // 3810 // Create a G_BUILD_VECTOR or G_CONCAT_VECTORS of NarrowTy pieces, padding with 3811 // undef as necessary. 3812 // 3813 // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2 3814 // -> <2 x s16> 3815 // 3816 // %4:_(s16) = G_IMPLICIT_DEF 3817 // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1 3818 // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4 3819 // %7:_(<2 x s16>) = G_IMPLICIT_DEF 3820 // %8:_(<6 x s16>) = G_CONCAT_VECTORS %5, %6, %7 3821 // %3:_(<3 x s16>), %8:_(<3 x s16>) = G_UNMERGE_VALUES %8 3822 LegalizerHelper::LegalizeResult 3823 LegalizerHelper::fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx, 3824 LLT NarrowTy) { 3825 Register DstReg = MI.getOperand(0).getReg(); 3826 LLT DstTy = MRI.getType(DstReg); 3827 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 3828 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 3829 3830 // Break into a common type 3831 SmallVector<Register, 16> Parts; 3832 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 3833 extractGCDType(Parts, GCDTy, MI.getOperand(I).getReg()); 3834 3835 // Build the requested new merge, padding with undef. 3836 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, 3837 TargetOpcode::G_ANYEXT); 3838 3839 // Pack into the original result register. 3840 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3841 3842 MI.eraseFromParent(); 3843 return Legalized; 3844 } 3845 3846 LegalizerHelper::LegalizeResult 3847 LegalizerHelper::fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI, 3848 unsigned TypeIdx, 3849 LLT NarrowVecTy) { 3850 Register DstReg = MI.getOperand(0).getReg(); 3851 Register SrcVec = MI.getOperand(1).getReg(); 3852 Register InsertVal; 3853 bool IsInsert = MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT; 3854 3855 assert((IsInsert ? TypeIdx == 0 : TypeIdx == 1) && "not a vector type index"); 3856 if (IsInsert) 3857 InsertVal = MI.getOperand(2).getReg(); 3858 3859 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 3860 3861 // TODO: Handle total scalarization case. 3862 if (!NarrowVecTy.isVector()) 3863 return UnableToLegalize; 3864 3865 LLT VecTy = MRI.getType(SrcVec); 3866 3867 // If the index is a constant, we can really break this down as you would 3868 // expect, and index into the target size pieces. 3869 int64_t IdxVal; 3870 auto MaybeCst = 3871 getConstantVRegValWithLookThrough(Idx, MRI, /*LookThroughInstrs*/ true, 3872 /*HandleFConstants*/ false); 3873 if (MaybeCst) { 3874 IdxVal = MaybeCst->Value.getSExtValue(); 3875 // Avoid out of bounds indexing the pieces. 3876 if (IdxVal >= VecTy.getNumElements()) { 3877 MIRBuilder.buildUndef(DstReg); 3878 MI.eraseFromParent(); 3879 return Legalized; 3880 } 3881 3882 SmallVector<Register, 8> VecParts; 3883 LLT GCDTy = extractGCDType(VecParts, VecTy, NarrowVecTy, SrcVec); 3884 3885 // Build a sequence of NarrowTy pieces in VecParts for this operand. 3886 LLT LCMTy = buildLCMMergePieces(VecTy, NarrowVecTy, GCDTy, VecParts, 3887 TargetOpcode::G_ANYEXT); 3888 3889 unsigned NewNumElts = NarrowVecTy.getNumElements(); 3890 3891 LLT IdxTy = MRI.getType(Idx); 3892 int64_t PartIdx = IdxVal / NewNumElts; 3893 auto NewIdx = 3894 MIRBuilder.buildConstant(IdxTy, IdxVal - NewNumElts * PartIdx); 3895 3896 if (IsInsert) { 3897 LLT PartTy = MRI.getType(VecParts[PartIdx]); 3898 3899 // Use the adjusted index to insert into one of the subvectors. 3900 auto InsertPart = MIRBuilder.buildInsertVectorElement( 3901 PartTy, VecParts[PartIdx], InsertVal, NewIdx); 3902 VecParts[PartIdx] = InsertPart.getReg(0); 3903 3904 // Recombine the inserted subvector with the others to reform the result 3905 // vector. 3906 buildWidenedRemergeToDst(DstReg, LCMTy, VecParts); 3907 } else { 3908 MIRBuilder.buildExtractVectorElement(DstReg, VecParts[PartIdx], NewIdx); 3909 } 3910 3911 MI.eraseFromParent(); 3912 return Legalized; 3913 } 3914 3915 // With a variable index, we can't perform the operation in a smaller type, so 3916 // we're forced to expand this. 3917 // 3918 // TODO: We could emit a chain of compare/select to figure out which piece to 3919 // index. 3920 return lowerExtractInsertVectorElt(MI); 3921 } 3922 3923 LegalizerHelper::LegalizeResult 3924 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx, 3925 LLT NarrowTy) { 3926 // FIXME: Don't know how to handle secondary types yet. 3927 if (TypeIdx != 0) 3928 return UnableToLegalize; 3929 3930 MachineMemOperand *MMO = *MI.memoperands_begin(); 3931 3932 // This implementation doesn't work for atomics. Give up instead of doing 3933 // something invalid. 3934 if (MMO->isAtomic()) 3935 return UnableToLegalize; 3936 3937 bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD; 3938 Register ValReg = MI.getOperand(0).getReg(); 3939 Register AddrReg = MI.getOperand(1).getReg(); 3940 LLT ValTy = MRI.getType(ValReg); 3941 3942 // FIXME: Do we need a distinct NarrowMemory legalize action? 3943 if (ValTy.getSizeInBits() != 8 * MMO->getSize()) { 3944 LLVM_DEBUG(dbgs() << "Can't narrow extload/truncstore\n"); 3945 return UnableToLegalize; 3946 } 3947 3948 int NumParts = -1; 3949 int NumLeftover = -1; 3950 LLT LeftoverTy; 3951 SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs; 3952 if (IsLoad) { 3953 std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy); 3954 } else { 3955 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, 3956 NarrowLeftoverRegs)) { 3957 NumParts = NarrowRegs.size(); 3958 NumLeftover = NarrowLeftoverRegs.size(); 3959 } 3960 } 3961 3962 if (NumParts == -1) 3963 return UnableToLegalize; 3964 3965 LLT PtrTy = MRI.getType(AddrReg); 3966 const LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits()); 3967 3968 unsigned TotalSize = ValTy.getSizeInBits(); 3969 3970 // Split the load/store into PartTy sized pieces starting at Offset. If this 3971 // is a load, return the new registers in ValRegs. For a store, each elements 3972 // of ValRegs should be PartTy. Returns the next offset that needs to be 3973 // handled. 3974 auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs, 3975 unsigned Offset) -> unsigned { 3976 MachineFunction &MF = MIRBuilder.getMF(); 3977 unsigned PartSize = PartTy.getSizeInBits(); 3978 for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize; 3979 Offset += PartSize, ++Idx) { 3980 unsigned ByteOffset = Offset / 8; 3981 Register NewAddrReg; 3982 3983 MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset); 3984 3985 MachineMemOperand *NewMMO = 3986 MF.getMachineMemOperand(MMO, ByteOffset, PartTy); 3987 3988 if (IsLoad) { 3989 Register Dst = MRI.createGenericVirtualRegister(PartTy); 3990 ValRegs.push_back(Dst); 3991 MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO); 3992 } else { 3993 MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO); 3994 } 3995 } 3996 3997 return Offset; 3998 }; 3999 4000 unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0); 4001 4002 // Handle the rest of the register if this isn't an even type breakdown. 4003 if (LeftoverTy.isValid()) 4004 splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset); 4005 4006 if (IsLoad) { 4007 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, 4008 LeftoverTy, NarrowLeftoverRegs); 4009 } 4010 4011 MI.eraseFromParent(); 4012 return Legalized; 4013 } 4014 4015 LegalizerHelper::LegalizeResult 4016 LegalizerHelper::reduceOperationWidth(MachineInstr &MI, unsigned int TypeIdx, 4017 LLT NarrowTy) { 4018 assert(TypeIdx == 0 && "only one type index expected"); 4019 4020 const unsigned Opc = MI.getOpcode(); 4021 const int NumDefOps = MI.getNumExplicitDefs(); 4022 const int NumSrcOps = MI.getNumOperands() - NumDefOps; 4023 const unsigned Flags = MI.getFlags(); 4024 const unsigned NarrowSize = NarrowTy.getSizeInBits(); 4025 const LLT NarrowScalarTy = LLT::scalar(NarrowSize); 4026 4027 assert(MI.getNumOperands() <= 4 && "expected instruction with either 1 " 4028 "result and 1-3 sources or 2 results and " 4029 "1-2 sources"); 4030 4031 SmallVector<Register, 2> DstRegs; 4032 for (int I = 0; I < NumDefOps; ++I) 4033 DstRegs.push_back(MI.getOperand(I).getReg()); 4034 4035 // First of all check whether we are narrowing (changing the element type) 4036 // or reducing the vector elements 4037 const LLT DstTy = MRI.getType(DstRegs[0]); 4038 const bool IsNarrow = NarrowTy.getScalarType() != DstTy.getScalarType(); 4039 4040 SmallVector<Register, 8> ExtractedRegs[3]; 4041 SmallVector<Register, 8> Parts; 4042 4043 // Break down all the sources into NarrowTy pieces we can operate on. This may 4044 // involve creating merges to a wider type, padded with undef. 4045 for (int I = 0; I != NumSrcOps; ++I) { 4046 Register SrcReg = MI.getOperand(I + NumDefOps).getReg(); 4047 LLT SrcTy = MRI.getType(SrcReg); 4048 4049 // The type to narrow SrcReg to. For narrowing, this is a smaller scalar. 4050 // For fewerElements, this is a smaller vector with the same element type. 4051 LLT OpNarrowTy; 4052 if (IsNarrow) { 4053 OpNarrowTy = NarrowScalarTy; 4054 4055 // In case of narrowing, we need to cast vectors to scalars for this to 4056 // work properly 4057 // FIXME: Can we do without the bitcast here if we're narrowing? 4058 if (SrcTy.isVector()) { 4059 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 4060 SrcReg = MIRBuilder.buildBitcast(SrcTy, SrcReg).getReg(0); 4061 } 4062 } else { 4063 auto NarrowEC = NarrowTy.isVector() ? NarrowTy.getElementCount() 4064 : ElementCount::getFixed(1); 4065 OpNarrowTy = LLT::scalarOrVector(NarrowEC, SrcTy.getScalarType()); 4066 } 4067 4068 LLT GCDTy = extractGCDType(ExtractedRegs[I], SrcTy, OpNarrowTy, SrcReg); 4069 4070 // Build a sequence of NarrowTy pieces in ExtractedRegs for this operand. 4071 buildLCMMergePieces(SrcTy, OpNarrowTy, GCDTy, ExtractedRegs[I], 4072 TargetOpcode::G_ANYEXT); 4073 } 4074 4075 SmallVector<Register, 8> ResultRegs[2]; 4076 4077 // Input operands for each sub-instruction. 4078 SmallVector<SrcOp, 4> InputRegs(NumSrcOps, Register()); 4079 4080 int NumParts = ExtractedRegs[0].size(); 4081 const unsigned DstSize = DstTy.getSizeInBits(); 4082 const LLT DstScalarTy = LLT::scalar(DstSize); 4083 4084 // Narrowing needs to use scalar types 4085 LLT DstLCMTy, NarrowDstTy; 4086 if (IsNarrow) { 4087 DstLCMTy = getLCMType(DstScalarTy, NarrowScalarTy); 4088 NarrowDstTy = NarrowScalarTy; 4089 } else { 4090 DstLCMTy = getLCMType(DstTy, NarrowTy); 4091 NarrowDstTy = NarrowTy; 4092 } 4093 4094 // We widened the source registers to satisfy merge/unmerge size 4095 // constraints. We'll have some extra fully undef parts. 4096 const int NumRealParts = (DstSize + NarrowSize - 1) / NarrowSize; 4097 4098 for (int I = 0; I != NumRealParts; ++I) { 4099 // Emit this instruction on each of the split pieces. 4100 for (int J = 0; J != NumSrcOps; ++J) 4101 InputRegs[J] = ExtractedRegs[J][I]; 4102 4103 MachineInstrBuilder Inst; 4104 if (NumDefOps == 1) 4105 Inst = MIRBuilder.buildInstr(Opc, {NarrowDstTy}, InputRegs, Flags); 4106 else 4107 Inst = MIRBuilder.buildInstr(Opc, {NarrowDstTy, NarrowDstTy}, InputRegs, 4108 Flags); 4109 4110 for (int J = 0; J != NumDefOps; ++J) 4111 ResultRegs[J].push_back(Inst.getReg(J)); 4112 } 4113 4114 // Fill out the widened result with undef instead of creating instructions 4115 // with undef inputs. 4116 int NumUndefParts = NumParts - NumRealParts; 4117 if (NumUndefParts != 0) { 4118 Register Undef = MIRBuilder.buildUndef(NarrowDstTy).getReg(0); 4119 for (int I = 0; I != NumDefOps; ++I) 4120 ResultRegs[I].append(NumUndefParts, Undef); 4121 } 4122 4123 // Extract the possibly padded result. Use a scratch register if we need to do 4124 // a final bitcast, otherwise use the original result register. 4125 Register MergeDstReg; 4126 for (int I = 0; I != NumDefOps; ++I) { 4127 if (IsNarrow && DstTy.isVector()) 4128 MergeDstReg = MRI.createGenericVirtualRegister(DstScalarTy); 4129 else 4130 MergeDstReg = DstRegs[I]; 4131 4132 buildWidenedRemergeToDst(MergeDstReg, DstLCMTy, ResultRegs[I]); 4133 4134 // Recast to vector if we narrowed a vector 4135 if (IsNarrow && DstTy.isVector()) 4136 MIRBuilder.buildBitcast(DstRegs[I], MergeDstReg); 4137 } 4138 4139 MI.eraseFromParent(); 4140 return Legalized; 4141 } 4142 4143 LegalizerHelper::LegalizeResult 4144 LegalizerHelper::fewerElementsVectorSextInReg(MachineInstr &MI, unsigned TypeIdx, 4145 LLT NarrowTy) { 4146 Register DstReg = MI.getOperand(0).getReg(); 4147 Register SrcReg = MI.getOperand(1).getReg(); 4148 int64_t Imm = MI.getOperand(2).getImm(); 4149 4150 LLT DstTy = MRI.getType(DstReg); 4151 4152 SmallVector<Register, 8> Parts; 4153 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 4154 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts); 4155 4156 for (Register &R : Parts) 4157 R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0); 4158 4159 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 4160 4161 MI.eraseFromParent(); 4162 return Legalized; 4163 } 4164 4165 LegalizerHelper::LegalizeResult 4166 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, 4167 LLT NarrowTy) { 4168 using namespace TargetOpcode; 4169 4170 switch (MI.getOpcode()) { 4171 case G_IMPLICIT_DEF: 4172 return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy); 4173 case G_TRUNC: 4174 case G_AND: 4175 case G_OR: 4176 case G_XOR: 4177 case G_ADD: 4178 case G_SUB: 4179 case G_MUL: 4180 case G_PTR_ADD: 4181 case G_SMULH: 4182 case G_UMULH: 4183 case G_FADD: 4184 case G_FMUL: 4185 case G_FSUB: 4186 case G_FNEG: 4187 case G_FABS: 4188 case G_FCANONICALIZE: 4189 case G_FDIV: 4190 case G_FREM: 4191 case G_FMA: 4192 case G_FMAD: 4193 case G_FPOW: 4194 case G_FEXP: 4195 case G_FEXP2: 4196 case G_FLOG: 4197 case G_FLOG2: 4198 case G_FLOG10: 4199 case G_FNEARBYINT: 4200 case G_FCEIL: 4201 case G_FFLOOR: 4202 case G_FRINT: 4203 case G_INTRINSIC_ROUND: 4204 case G_INTRINSIC_ROUNDEVEN: 4205 case G_INTRINSIC_TRUNC: 4206 case G_FCOS: 4207 case G_FSIN: 4208 case G_FSQRT: 4209 case G_BSWAP: 4210 case G_BITREVERSE: 4211 case G_SDIV: 4212 case G_UDIV: 4213 case G_SREM: 4214 case G_UREM: 4215 case G_SDIVREM: 4216 case G_UDIVREM: 4217 case G_SMIN: 4218 case G_SMAX: 4219 case G_UMIN: 4220 case G_UMAX: 4221 case G_ABS: 4222 case G_FMINNUM: 4223 case G_FMAXNUM: 4224 case G_FMINNUM_IEEE: 4225 case G_FMAXNUM_IEEE: 4226 case G_FMINIMUM: 4227 case G_FMAXIMUM: 4228 case G_FSHL: 4229 case G_FSHR: 4230 case G_FREEZE: 4231 case G_SADDSAT: 4232 case G_SSUBSAT: 4233 case G_UADDSAT: 4234 case G_USUBSAT: 4235 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 4236 case G_UMULO: 4237 case G_SMULO: 4238 return fewerElementsVectorMulo(MI, TypeIdx, NarrowTy); 4239 case G_SHL: 4240 case G_LSHR: 4241 case G_ASHR: 4242 case G_SSHLSAT: 4243 case G_USHLSAT: 4244 case G_CTLZ: 4245 case G_CTLZ_ZERO_UNDEF: 4246 case G_CTTZ: 4247 case G_CTTZ_ZERO_UNDEF: 4248 case G_CTPOP: 4249 case G_FCOPYSIGN: 4250 return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy); 4251 case G_ZEXT: 4252 case G_SEXT: 4253 case G_ANYEXT: 4254 case G_FPEXT: 4255 case G_FPTRUNC: 4256 case G_SITOFP: 4257 case G_UITOFP: 4258 case G_FPTOSI: 4259 case G_FPTOUI: 4260 case G_INTTOPTR: 4261 case G_PTRTOINT: 4262 case G_ADDRSPACE_CAST: 4263 return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy); 4264 case G_ICMP: 4265 case G_FCMP: 4266 return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy); 4267 case G_SELECT: 4268 return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy); 4269 case G_PHI: 4270 return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy); 4271 case G_UNMERGE_VALUES: 4272 return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy); 4273 case G_BUILD_VECTOR: 4274 assert(TypeIdx == 0 && "not a vector type index"); 4275 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4276 case G_CONCAT_VECTORS: 4277 if (TypeIdx != 1) // TODO: This probably does work as expected already. 4278 return UnableToLegalize; 4279 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4280 case G_EXTRACT_VECTOR_ELT: 4281 case G_INSERT_VECTOR_ELT: 4282 return fewerElementsVectorExtractInsertVectorElt(MI, TypeIdx, NarrowTy); 4283 case G_LOAD: 4284 case G_STORE: 4285 return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy); 4286 case G_SEXT_INREG: 4287 return fewerElementsVectorSextInReg(MI, TypeIdx, NarrowTy); 4288 GISEL_VECREDUCE_CASES_NONSEQ 4289 return fewerElementsVectorReductions(MI, TypeIdx, NarrowTy); 4290 case G_SHUFFLE_VECTOR: 4291 return fewerElementsVectorShuffle(MI, TypeIdx, NarrowTy); 4292 default: 4293 return UnableToLegalize; 4294 } 4295 } 4296 4297 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle( 4298 MachineInstr &MI, unsigned int TypeIdx, LLT NarrowTy) { 4299 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR); 4300 if (TypeIdx != 0) 4301 return UnableToLegalize; 4302 4303 Register DstReg = MI.getOperand(0).getReg(); 4304 Register Src1Reg = MI.getOperand(1).getReg(); 4305 Register Src2Reg = MI.getOperand(2).getReg(); 4306 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 4307 LLT DstTy = MRI.getType(DstReg); 4308 LLT Src1Ty = MRI.getType(Src1Reg); 4309 LLT Src2Ty = MRI.getType(Src2Reg); 4310 // The shuffle should be canonicalized by now. 4311 if (DstTy != Src1Ty) 4312 return UnableToLegalize; 4313 if (DstTy != Src2Ty) 4314 return UnableToLegalize; 4315 4316 if (!isPowerOf2_32(DstTy.getNumElements())) 4317 return UnableToLegalize; 4318 4319 // We only support splitting a shuffle into 2, so adjust NarrowTy accordingly. 4320 // Further legalization attempts will be needed to do split further. 4321 NarrowTy = 4322 DstTy.changeElementCount(DstTy.getElementCount().divideCoefficientBy(2)); 4323 unsigned NewElts = NarrowTy.getNumElements(); 4324 4325 SmallVector<Register> SplitSrc1Regs, SplitSrc2Regs; 4326 extractParts(Src1Reg, NarrowTy, 2, SplitSrc1Regs); 4327 extractParts(Src2Reg, NarrowTy, 2, SplitSrc2Regs); 4328 Register Inputs[4] = {SplitSrc1Regs[0], SplitSrc1Regs[1], SplitSrc2Regs[0], 4329 SplitSrc2Regs[1]}; 4330 4331 Register Hi, Lo; 4332 4333 // If Lo or Hi uses elements from at most two of the four input vectors, then 4334 // express it as a vector shuffle of those two inputs. Otherwise extract the 4335 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 4336 SmallVector<int, 16> Ops; 4337 for (unsigned High = 0; High < 2; ++High) { 4338 Register &Output = High ? Hi : Lo; 4339 4340 // Build a shuffle mask for the output, discovering on the fly which 4341 // input vectors to use as shuffle operands (recorded in InputUsed). 4342 // If building a suitable shuffle vector proves too hard, then bail 4343 // out with useBuildVector set. 4344 unsigned InputUsed[2] = {-1U, -1U}; // Not yet discovered. 4345 unsigned FirstMaskIdx = High * NewElts; 4346 bool UseBuildVector = false; 4347 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 4348 // The mask element. This indexes into the input. 4349 int Idx = Mask[FirstMaskIdx + MaskOffset]; 4350 4351 // The input vector this mask element indexes into. 4352 unsigned Input = (unsigned)Idx / NewElts; 4353 4354 if (Input >= array_lengthof(Inputs)) { 4355 // The mask element does not index into any input vector. 4356 Ops.push_back(-1); 4357 continue; 4358 } 4359 4360 // Turn the index into an offset from the start of the input vector. 4361 Idx -= Input * NewElts; 4362 4363 // Find or create a shuffle vector operand to hold this input. 4364 unsigned OpNo; 4365 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 4366 if (InputUsed[OpNo] == Input) { 4367 // This input vector is already an operand. 4368 break; 4369 } else if (InputUsed[OpNo] == -1U) { 4370 // Create a new operand for this input vector. 4371 InputUsed[OpNo] = Input; 4372 break; 4373 } 4374 } 4375 4376 if (OpNo >= array_lengthof(InputUsed)) { 4377 // More than two input vectors used! Give up on trying to create a 4378 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 4379 UseBuildVector = true; 4380 break; 4381 } 4382 4383 // Add the mask index for the new shuffle vector. 4384 Ops.push_back(Idx + OpNo * NewElts); 4385 } 4386 4387 if (UseBuildVector) { 4388 LLT EltTy = NarrowTy.getElementType(); 4389 SmallVector<Register, 16> SVOps; 4390 4391 // Extract the input elements by hand. 4392 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 4393 // The mask element. This indexes into the input. 4394 int Idx = Mask[FirstMaskIdx + MaskOffset]; 4395 4396 // The input vector this mask element indexes into. 4397 unsigned Input = (unsigned)Idx / NewElts; 4398 4399 if (Input >= array_lengthof(Inputs)) { 4400 // The mask element is "undef" or indexes off the end of the input. 4401 SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0)); 4402 continue; 4403 } 4404 4405 // Turn the index into an offset from the start of the input vector. 4406 Idx -= Input * NewElts; 4407 4408 // Extract the vector element by hand. 4409 SVOps.push_back(MIRBuilder 4410 .buildExtractVectorElement( 4411 EltTy, Inputs[Input], 4412 MIRBuilder.buildConstant(LLT::scalar(32), Idx)) 4413 .getReg(0)); 4414 } 4415 4416 // Construct the Lo/Hi output using a G_BUILD_VECTOR. 4417 Output = MIRBuilder.buildBuildVector(NarrowTy, SVOps).getReg(0); 4418 } else if (InputUsed[0] == -1U) { 4419 // No input vectors were used! The result is undefined. 4420 Output = MIRBuilder.buildUndef(NarrowTy).getReg(0); 4421 } else { 4422 Register Op0 = Inputs[InputUsed[0]]; 4423 // If only one input was used, use an undefined vector for the other. 4424 Register Op1 = InputUsed[1] == -1U 4425 ? MIRBuilder.buildUndef(NarrowTy).getReg(0) 4426 : Inputs[InputUsed[1]]; 4427 // At least one input vector was used. Create a new shuffle vector. 4428 Output = MIRBuilder.buildShuffleVector(NarrowTy, Op0, Op1, Ops).getReg(0); 4429 } 4430 4431 Ops.clear(); 4432 } 4433 4434 MIRBuilder.buildConcatVectors(DstReg, {Lo, Hi}); 4435 MI.eraseFromParent(); 4436 return Legalized; 4437 } 4438 4439 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorReductions( 4440 MachineInstr &MI, unsigned int TypeIdx, LLT NarrowTy) { 4441 unsigned Opc = MI.getOpcode(); 4442 assert(Opc != TargetOpcode::G_VECREDUCE_SEQ_FADD && 4443 Opc != TargetOpcode::G_VECREDUCE_SEQ_FMUL && 4444 "Sequential reductions not expected"); 4445 4446 if (TypeIdx != 1) 4447 return UnableToLegalize; 4448 4449 // The semantics of the normal non-sequential reductions allow us to freely 4450 // re-associate the operation. 4451 Register SrcReg = MI.getOperand(1).getReg(); 4452 LLT SrcTy = MRI.getType(SrcReg); 4453 Register DstReg = MI.getOperand(0).getReg(); 4454 LLT DstTy = MRI.getType(DstReg); 4455 4456 if (SrcTy.getNumElements() % NarrowTy.getNumElements() != 0) 4457 return UnableToLegalize; 4458 4459 SmallVector<Register> SplitSrcs; 4460 const unsigned NumParts = SrcTy.getNumElements() / NarrowTy.getNumElements(); 4461 extractParts(SrcReg, NarrowTy, NumParts, SplitSrcs); 4462 SmallVector<Register> PartialReductions; 4463 for (unsigned Part = 0; Part < NumParts; ++Part) { 4464 PartialReductions.push_back( 4465 MIRBuilder.buildInstr(Opc, {DstTy}, {SplitSrcs[Part]}).getReg(0)); 4466 } 4467 4468 unsigned ScalarOpc; 4469 switch (Opc) { 4470 case TargetOpcode::G_VECREDUCE_FADD: 4471 ScalarOpc = TargetOpcode::G_FADD; 4472 break; 4473 case TargetOpcode::G_VECREDUCE_FMUL: 4474 ScalarOpc = TargetOpcode::G_FMUL; 4475 break; 4476 case TargetOpcode::G_VECREDUCE_FMAX: 4477 ScalarOpc = TargetOpcode::G_FMAXNUM; 4478 break; 4479 case TargetOpcode::G_VECREDUCE_FMIN: 4480 ScalarOpc = TargetOpcode::G_FMINNUM; 4481 break; 4482 case TargetOpcode::G_VECREDUCE_ADD: 4483 ScalarOpc = TargetOpcode::G_ADD; 4484 break; 4485 case TargetOpcode::G_VECREDUCE_MUL: 4486 ScalarOpc = TargetOpcode::G_MUL; 4487 break; 4488 case TargetOpcode::G_VECREDUCE_AND: 4489 ScalarOpc = TargetOpcode::G_AND; 4490 break; 4491 case TargetOpcode::G_VECREDUCE_OR: 4492 ScalarOpc = TargetOpcode::G_OR; 4493 break; 4494 case TargetOpcode::G_VECREDUCE_XOR: 4495 ScalarOpc = TargetOpcode::G_XOR; 4496 break; 4497 case TargetOpcode::G_VECREDUCE_SMAX: 4498 ScalarOpc = TargetOpcode::G_SMAX; 4499 break; 4500 case TargetOpcode::G_VECREDUCE_SMIN: 4501 ScalarOpc = TargetOpcode::G_SMIN; 4502 break; 4503 case TargetOpcode::G_VECREDUCE_UMAX: 4504 ScalarOpc = TargetOpcode::G_UMAX; 4505 break; 4506 case TargetOpcode::G_VECREDUCE_UMIN: 4507 ScalarOpc = TargetOpcode::G_UMIN; 4508 break; 4509 default: 4510 LLVM_DEBUG(dbgs() << "Can't legalize: unknown reduction kind.\n"); 4511 return UnableToLegalize; 4512 } 4513 4514 // If the types involved are powers of 2, we can generate intermediate vector 4515 // ops, before generating a final reduction operation. 4516 if (isPowerOf2_32(SrcTy.getNumElements()) && 4517 isPowerOf2_32(NarrowTy.getNumElements())) { 4518 return tryNarrowPow2Reduction(MI, SrcReg, SrcTy, NarrowTy, ScalarOpc); 4519 } 4520 4521 Register Acc = PartialReductions[0]; 4522 for (unsigned Part = 1; Part < NumParts; ++Part) { 4523 if (Part == NumParts - 1) { 4524 MIRBuilder.buildInstr(ScalarOpc, {DstReg}, 4525 {Acc, PartialReductions[Part]}); 4526 } else { 4527 Acc = MIRBuilder 4528 .buildInstr(ScalarOpc, {DstTy}, {Acc, PartialReductions[Part]}) 4529 .getReg(0); 4530 } 4531 } 4532 MI.eraseFromParent(); 4533 return Legalized; 4534 } 4535 4536 LegalizerHelper::LegalizeResult 4537 LegalizerHelper::tryNarrowPow2Reduction(MachineInstr &MI, Register SrcReg, 4538 LLT SrcTy, LLT NarrowTy, 4539 unsigned ScalarOpc) { 4540 SmallVector<Register> SplitSrcs; 4541 // Split the sources into NarrowTy size pieces. 4542 extractParts(SrcReg, NarrowTy, 4543 SrcTy.getNumElements() / NarrowTy.getNumElements(), SplitSrcs); 4544 // We're going to do a tree reduction using vector operations until we have 4545 // one NarrowTy size value left. 4546 while (SplitSrcs.size() > 1) { 4547 SmallVector<Register> PartialRdxs; 4548 for (unsigned Idx = 0; Idx < SplitSrcs.size()-1; Idx += 2) { 4549 Register LHS = SplitSrcs[Idx]; 4550 Register RHS = SplitSrcs[Idx + 1]; 4551 // Create the intermediate vector op. 4552 Register Res = 4553 MIRBuilder.buildInstr(ScalarOpc, {NarrowTy}, {LHS, RHS}).getReg(0); 4554 PartialRdxs.push_back(Res); 4555 } 4556 SplitSrcs = std::move(PartialRdxs); 4557 } 4558 // Finally generate the requested NarrowTy based reduction. 4559 Observer.changingInstr(MI); 4560 MI.getOperand(1).setReg(SplitSrcs[0]); 4561 Observer.changedInstr(MI); 4562 return Legalized; 4563 } 4564 4565 LegalizerHelper::LegalizeResult 4566 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt, 4567 const LLT HalfTy, const LLT AmtTy) { 4568 4569 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4570 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4571 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4572 4573 if (Amt.isNullValue()) { 4574 MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH}); 4575 MI.eraseFromParent(); 4576 return Legalized; 4577 } 4578 4579 LLT NVT = HalfTy; 4580 unsigned NVTBits = HalfTy.getSizeInBits(); 4581 unsigned VTBits = 2 * NVTBits; 4582 4583 SrcOp Lo(Register(0)), Hi(Register(0)); 4584 if (MI.getOpcode() == TargetOpcode::G_SHL) { 4585 if (Amt.ugt(VTBits)) { 4586 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4587 } else if (Amt.ugt(NVTBits)) { 4588 Lo = MIRBuilder.buildConstant(NVT, 0); 4589 Hi = MIRBuilder.buildShl(NVT, InL, 4590 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4591 } else if (Amt == NVTBits) { 4592 Lo = MIRBuilder.buildConstant(NVT, 0); 4593 Hi = InL; 4594 } else { 4595 Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt)); 4596 auto OrLHS = 4597 MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt)); 4598 auto OrRHS = MIRBuilder.buildLShr( 4599 NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4600 Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4601 } 4602 } else if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4603 if (Amt.ugt(VTBits)) { 4604 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4605 } else if (Amt.ugt(NVTBits)) { 4606 Lo = MIRBuilder.buildLShr(NVT, InH, 4607 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4608 Hi = MIRBuilder.buildConstant(NVT, 0); 4609 } else if (Amt == NVTBits) { 4610 Lo = InH; 4611 Hi = MIRBuilder.buildConstant(NVT, 0); 4612 } else { 4613 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4614 4615 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4616 auto OrRHS = MIRBuilder.buildShl( 4617 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4618 4619 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4620 Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst); 4621 } 4622 } else { 4623 if (Amt.ugt(VTBits)) { 4624 Hi = Lo = MIRBuilder.buildAShr( 4625 NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4626 } else if (Amt.ugt(NVTBits)) { 4627 Lo = MIRBuilder.buildAShr(NVT, InH, 4628 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4629 Hi = MIRBuilder.buildAShr(NVT, InH, 4630 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4631 } else if (Amt == NVTBits) { 4632 Lo = InH; 4633 Hi = MIRBuilder.buildAShr(NVT, InH, 4634 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4635 } else { 4636 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4637 4638 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4639 auto OrRHS = MIRBuilder.buildShl( 4640 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4641 4642 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4643 Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst); 4644 } 4645 } 4646 4647 MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi}); 4648 MI.eraseFromParent(); 4649 4650 return Legalized; 4651 } 4652 4653 // TODO: Optimize if constant shift amount. 4654 LegalizerHelper::LegalizeResult 4655 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, 4656 LLT RequestedTy) { 4657 if (TypeIdx == 1) { 4658 Observer.changingInstr(MI); 4659 narrowScalarSrc(MI, RequestedTy, 2); 4660 Observer.changedInstr(MI); 4661 return Legalized; 4662 } 4663 4664 Register DstReg = MI.getOperand(0).getReg(); 4665 LLT DstTy = MRI.getType(DstReg); 4666 if (DstTy.isVector()) 4667 return UnableToLegalize; 4668 4669 Register Amt = MI.getOperand(2).getReg(); 4670 LLT ShiftAmtTy = MRI.getType(Amt); 4671 const unsigned DstEltSize = DstTy.getScalarSizeInBits(); 4672 if (DstEltSize % 2 != 0) 4673 return UnableToLegalize; 4674 4675 // Ignore the input type. We can only go to exactly half the size of the 4676 // input. If that isn't small enough, the resulting pieces will be further 4677 // legalized. 4678 const unsigned NewBitSize = DstEltSize / 2; 4679 const LLT HalfTy = LLT::scalar(NewBitSize); 4680 const LLT CondTy = LLT::scalar(1); 4681 4682 if (const MachineInstr *KShiftAmt = 4683 getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) { 4684 return narrowScalarShiftByConstant( 4685 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy); 4686 } 4687 4688 // TODO: Expand with known bits. 4689 4690 // Handle the fully general expansion by an unknown amount. 4691 auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize); 4692 4693 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4694 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4695 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4696 4697 auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits); 4698 auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt); 4699 4700 auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0); 4701 auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits); 4702 auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero); 4703 4704 Register ResultRegs[2]; 4705 switch (MI.getOpcode()) { 4706 case TargetOpcode::G_SHL: { 4707 // Short: ShAmt < NewBitSize 4708 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); 4709 4710 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack); 4711 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt); 4712 auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4713 4714 // Long: ShAmt >= NewBitSize 4715 auto LoL = MIRBuilder.buildConstant(HalfTy, 0); // Lo part is zero. 4716 auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part. 4717 4718 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL); 4719 auto Hi = MIRBuilder.buildSelect( 4720 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL)); 4721 4722 ResultRegs[0] = Lo.getReg(0); 4723 ResultRegs[1] = Hi.getReg(0); 4724 break; 4725 } 4726 case TargetOpcode::G_LSHR: 4727 case TargetOpcode::G_ASHR: { 4728 // Short: ShAmt < NewBitSize 4729 auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt}); 4730 4731 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt); 4732 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack); 4733 auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4734 4735 // Long: ShAmt >= NewBitSize 4736 MachineInstrBuilder HiL; 4737 if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4738 HiL = MIRBuilder.buildConstant(HalfTy, 0); // Hi part is zero. 4739 } else { 4740 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1); 4741 HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt); // Sign of Hi part. 4742 } 4743 auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, 4744 {InH, AmtExcess}); // Lo from Hi part. 4745 4746 auto Lo = MIRBuilder.buildSelect( 4747 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL)); 4748 4749 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL); 4750 4751 ResultRegs[0] = Lo.getReg(0); 4752 ResultRegs[1] = Hi.getReg(0); 4753 break; 4754 } 4755 default: 4756 llvm_unreachable("not a shift"); 4757 } 4758 4759 MIRBuilder.buildMerge(DstReg, ResultRegs); 4760 MI.eraseFromParent(); 4761 return Legalized; 4762 } 4763 4764 LegalizerHelper::LegalizeResult 4765 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 4766 LLT MoreTy) { 4767 assert(TypeIdx == 0 && "Expecting only Idx 0"); 4768 4769 Observer.changingInstr(MI); 4770 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 4771 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 4772 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 4773 moreElementsVectorSrc(MI, MoreTy, I); 4774 } 4775 4776 MachineBasicBlock &MBB = *MI.getParent(); 4777 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 4778 moreElementsVectorDst(MI, MoreTy, 0); 4779 Observer.changedInstr(MI); 4780 return Legalized; 4781 } 4782 4783 LegalizerHelper::LegalizeResult 4784 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx, 4785 LLT MoreTy) { 4786 unsigned Opc = MI.getOpcode(); 4787 switch (Opc) { 4788 case TargetOpcode::G_IMPLICIT_DEF: 4789 case TargetOpcode::G_LOAD: { 4790 if (TypeIdx != 0) 4791 return UnableToLegalize; 4792 Observer.changingInstr(MI); 4793 moreElementsVectorDst(MI, MoreTy, 0); 4794 Observer.changedInstr(MI); 4795 return Legalized; 4796 } 4797 case TargetOpcode::G_STORE: 4798 if (TypeIdx != 0) 4799 return UnableToLegalize; 4800 Observer.changingInstr(MI); 4801 moreElementsVectorSrc(MI, MoreTy, 0); 4802 Observer.changedInstr(MI); 4803 return Legalized; 4804 case TargetOpcode::G_AND: 4805 case TargetOpcode::G_OR: 4806 case TargetOpcode::G_XOR: 4807 case TargetOpcode::G_SMIN: 4808 case TargetOpcode::G_SMAX: 4809 case TargetOpcode::G_UMIN: 4810 case TargetOpcode::G_UMAX: 4811 case TargetOpcode::G_FMINNUM: 4812 case TargetOpcode::G_FMAXNUM: 4813 case TargetOpcode::G_FMINNUM_IEEE: 4814 case TargetOpcode::G_FMAXNUM_IEEE: 4815 case TargetOpcode::G_FMINIMUM: 4816 case TargetOpcode::G_FMAXIMUM: { 4817 Observer.changingInstr(MI); 4818 moreElementsVectorSrc(MI, MoreTy, 1); 4819 moreElementsVectorSrc(MI, MoreTy, 2); 4820 moreElementsVectorDst(MI, MoreTy, 0); 4821 Observer.changedInstr(MI); 4822 return Legalized; 4823 } 4824 case TargetOpcode::G_EXTRACT: 4825 if (TypeIdx != 1) 4826 return UnableToLegalize; 4827 Observer.changingInstr(MI); 4828 moreElementsVectorSrc(MI, MoreTy, 1); 4829 Observer.changedInstr(MI); 4830 return Legalized; 4831 case TargetOpcode::G_INSERT: 4832 case TargetOpcode::G_FREEZE: 4833 if (TypeIdx != 0) 4834 return UnableToLegalize; 4835 Observer.changingInstr(MI); 4836 moreElementsVectorSrc(MI, MoreTy, 1); 4837 moreElementsVectorDst(MI, MoreTy, 0); 4838 Observer.changedInstr(MI); 4839 return Legalized; 4840 case TargetOpcode::G_SELECT: 4841 if (TypeIdx != 0) 4842 return UnableToLegalize; 4843 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) 4844 return UnableToLegalize; 4845 4846 Observer.changingInstr(MI); 4847 moreElementsVectorSrc(MI, MoreTy, 2); 4848 moreElementsVectorSrc(MI, MoreTy, 3); 4849 moreElementsVectorDst(MI, MoreTy, 0); 4850 Observer.changedInstr(MI); 4851 return Legalized; 4852 case TargetOpcode::G_UNMERGE_VALUES: { 4853 if (TypeIdx != 1) 4854 return UnableToLegalize; 4855 4856 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 4857 int NumDst = MI.getNumOperands() - 1; 4858 moreElementsVectorSrc(MI, MoreTy, NumDst); 4859 4860 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 4861 for (int I = 0; I != NumDst; ++I) 4862 MIB.addDef(MI.getOperand(I).getReg()); 4863 4864 int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits(); 4865 for (int I = NumDst; I != NewNumDst; ++I) 4866 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 4867 4868 MIB.addUse(MI.getOperand(NumDst).getReg()); 4869 MI.eraseFromParent(); 4870 return Legalized; 4871 } 4872 case TargetOpcode::G_PHI: 4873 return moreElementsVectorPhi(MI, TypeIdx, MoreTy); 4874 case TargetOpcode::G_SHUFFLE_VECTOR: 4875 return moreElementsVectorShuffle(MI, TypeIdx, MoreTy); 4876 default: 4877 return UnableToLegalize; 4878 } 4879 } 4880 4881 LegalizerHelper::LegalizeResult 4882 LegalizerHelper::moreElementsVectorShuffle(MachineInstr &MI, 4883 unsigned int TypeIdx, LLT MoreTy) { 4884 if (TypeIdx != 0) 4885 return UnableToLegalize; 4886 4887 Register DstReg = MI.getOperand(0).getReg(); 4888 Register Src1Reg = MI.getOperand(1).getReg(); 4889 Register Src2Reg = MI.getOperand(2).getReg(); 4890 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 4891 LLT DstTy = MRI.getType(DstReg); 4892 LLT Src1Ty = MRI.getType(Src1Reg); 4893 LLT Src2Ty = MRI.getType(Src2Reg); 4894 unsigned NumElts = DstTy.getNumElements(); 4895 unsigned WidenNumElts = MoreTy.getNumElements(); 4896 4897 // Expect a canonicalized shuffle. 4898 if (DstTy != Src1Ty || DstTy != Src2Ty) 4899 return UnableToLegalize; 4900 4901 moreElementsVectorSrc(MI, MoreTy, 1); 4902 moreElementsVectorSrc(MI, MoreTy, 2); 4903 4904 // Adjust mask based on new input vector length. 4905 SmallVector<int, 16> NewMask; 4906 for (unsigned I = 0; I != NumElts; ++I) { 4907 int Idx = Mask[I]; 4908 if (Idx < static_cast<int>(NumElts)) 4909 NewMask.push_back(Idx); 4910 else 4911 NewMask.push_back(Idx - NumElts + WidenNumElts); 4912 } 4913 for (unsigned I = NumElts; I != WidenNumElts; ++I) 4914 NewMask.push_back(-1); 4915 moreElementsVectorDst(MI, MoreTy, 0); 4916 MIRBuilder.setInstrAndDebugLoc(MI); 4917 MIRBuilder.buildShuffleVector(MI.getOperand(0).getReg(), 4918 MI.getOperand(1).getReg(), 4919 MI.getOperand(2).getReg(), NewMask); 4920 MI.eraseFromParent(); 4921 return Legalized; 4922 } 4923 4924 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs, 4925 ArrayRef<Register> Src1Regs, 4926 ArrayRef<Register> Src2Regs, 4927 LLT NarrowTy) { 4928 MachineIRBuilder &B = MIRBuilder; 4929 unsigned SrcParts = Src1Regs.size(); 4930 unsigned DstParts = DstRegs.size(); 4931 4932 unsigned DstIdx = 0; // Low bits of the result. 4933 Register FactorSum = 4934 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); 4935 DstRegs[DstIdx] = FactorSum; 4936 4937 unsigned CarrySumPrevDstIdx; 4938 SmallVector<Register, 4> Factors; 4939 4940 for (DstIdx = 1; DstIdx < DstParts; DstIdx++) { 4941 // Collect low parts of muls for DstIdx. 4942 for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1; 4943 i <= std::min(DstIdx, SrcParts - 1); ++i) { 4944 MachineInstrBuilder Mul = 4945 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); 4946 Factors.push_back(Mul.getReg(0)); 4947 } 4948 // Collect high parts of muls from previous DstIdx. 4949 for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts; 4950 i <= std::min(DstIdx - 1, SrcParts - 1); ++i) { 4951 MachineInstrBuilder Umulh = 4952 B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]); 4953 Factors.push_back(Umulh.getReg(0)); 4954 } 4955 // Add CarrySum from additions calculated for previous DstIdx. 4956 if (DstIdx != 1) { 4957 Factors.push_back(CarrySumPrevDstIdx); 4958 } 4959 4960 Register CarrySum; 4961 // Add all factors and accumulate all carries into CarrySum. 4962 if (DstIdx != DstParts - 1) { 4963 MachineInstrBuilder Uaddo = 4964 B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]); 4965 FactorSum = Uaddo.getReg(0); 4966 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0); 4967 for (unsigned i = 2; i < Factors.size(); ++i) { 4968 MachineInstrBuilder Uaddo = 4969 B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]); 4970 FactorSum = Uaddo.getReg(0); 4971 MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1)); 4972 CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0); 4973 } 4974 } else { 4975 // Since value for the next index is not calculated, neither is CarrySum. 4976 FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0); 4977 for (unsigned i = 2; i < Factors.size(); ++i) 4978 FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0); 4979 } 4980 4981 CarrySumPrevDstIdx = CarrySum; 4982 DstRegs[DstIdx] = FactorSum; 4983 Factors.clear(); 4984 } 4985 } 4986 4987 LegalizerHelper::LegalizeResult 4988 LegalizerHelper::narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx, 4989 LLT NarrowTy) { 4990 if (TypeIdx != 0) 4991 return UnableToLegalize; 4992 4993 Register DstReg = MI.getOperand(0).getReg(); 4994 LLT DstType = MRI.getType(DstReg); 4995 // FIXME: add support for vector types 4996 if (DstType.isVector()) 4997 return UnableToLegalize; 4998 4999 unsigned Opcode = MI.getOpcode(); 5000 unsigned OpO, OpE, OpF; 5001 switch (Opcode) { 5002 case TargetOpcode::G_SADDO: 5003 case TargetOpcode::G_SADDE: 5004 case TargetOpcode::G_UADDO: 5005 case TargetOpcode::G_UADDE: 5006 case TargetOpcode::G_ADD: 5007 OpO = TargetOpcode::G_UADDO; 5008 OpE = TargetOpcode::G_UADDE; 5009 OpF = TargetOpcode::G_UADDE; 5010 if (Opcode == TargetOpcode::G_SADDO || Opcode == TargetOpcode::G_SADDE) 5011 OpF = TargetOpcode::G_SADDE; 5012 break; 5013 case TargetOpcode::G_SSUBO: 5014 case TargetOpcode::G_SSUBE: 5015 case TargetOpcode::G_USUBO: 5016 case TargetOpcode::G_USUBE: 5017 case TargetOpcode::G_SUB: 5018 OpO = TargetOpcode::G_USUBO; 5019 OpE = TargetOpcode::G_USUBE; 5020 OpF = TargetOpcode::G_USUBE; 5021 if (Opcode == TargetOpcode::G_SSUBO || Opcode == TargetOpcode::G_SSUBE) 5022 OpF = TargetOpcode::G_SSUBE; 5023 break; 5024 default: 5025 llvm_unreachable("Unexpected add/sub opcode!"); 5026 } 5027 5028 // 1 for a plain add/sub, 2 if this is an operation with a carry-out. 5029 unsigned NumDefs = MI.getNumExplicitDefs(); 5030 Register Src1 = MI.getOperand(NumDefs).getReg(); 5031 Register Src2 = MI.getOperand(NumDefs + 1).getReg(); 5032 Register CarryDst, CarryIn; 5033 if (NumDefs == 2) 5034 CarryDst = MI.getOperand(1).getReg(); 5035 if (MI.getNumOperands() == NumDefs + 3) 5036 CarryIn = MI.getOperand(NumDefs + 2).getReg(); 5037 5038 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); 5039 LLT LeftoverTy, DummyTy; 5040 SmallVector<Register, 2> Src1Regs, Src2Regs, Src1Left, Src2Left, DstRegs; 5041 extractParts(Src1, RegTy, NarrowTy, LeftoverTy, Src1Regs, Src1Left); 5042 extractParts(Src2, RegTy, NarrowTy, DummyTy, Src2Regs, Src2Left); 5043 5044 int NarrowParts = Src1Regs.size(); 5045 for (int I = 0, E = Src1Left.size(); I != E; ++I) { 5046 Src1Regs.push_back(Src1Left[I]); 5047 Src2Regs.push_back(Src2Left[I]); 5048 } 5049 DstRegs.reserve(Src1Regs.size()); 5050 5051 for (int i = 0, e = Src1Regs.size(); i != e; ++i) { 5052 Register DstReg = 5053 MRI.createGenericVirtualRegister(MRI.getType(Src1Regs[i])); 5054 Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); 5055 // Forward the final carry-out to the destination register 5056 if (i == e - 1 && CarryDst) 5057 CarryOut = CarryDst; 5058 5059 if (!CarryIn) { 5060 MIRBuilder.buildInstr(OpO, {DstReg, CarryOut}, 5061 {Src1Regs[i], Src2Regs[i]}); 5062 } else if (i == e - 1) { 5063 MIRBuilder.buildInstr(OpF, {DstReg, CarryOut}, 5064 {Src1Regs[i], Src2Regs[i], CarryIn}); 5065 } else { 5066 MIRBuilder.buildInstr(OpE, {DstReg, CarryOut}, 5067 {Src1Regs[i], Src2Regs[i], CarryIn}); 5068 } 5069 5070 DstRegs.push_back(DstReg); 5071 CarryIn = CarryOut; 5072 } 5073 insertParts(MI.getOperand(0).getReg(), RegTy, NarrowTy, 5074 makeArrayRef(DstRegs).take_front(NarrowParts), LeftoverTy, 5075 makeArrayRef(DstRegs).drop_front(NarrowParts)); 5076 5077 MI.eraseFromParent(); 5078 return Legalized; 5079 } 5080 5081 LegalizerHelper::LegalizeResult 5082 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) { 5083 Register DstReg = MI.getOperand(0).getReg(); 5084 Register Src1 = MI.getOperand(1).getReg(); 5085 Register Src2 = MI.getOperand(2).getReg(); 5086 5087 LLT Ty = MRI.getType(DstReg); 5088 if (Ty.isVector()) 5089 return UnableToLegalize; 5090 5091 unsigned SrcSize = MRI.getType(Src1).getSizeInBits(); 5092 unsigned DstSize = Ty.getSizeInBits(); 5093 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5094 if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0) 5095 return UnableToLegalize; 5096 5097 unsigned NumDstParts = DstSize / NarrowSize; 5098 unsigned NumSrcParts = SrcSize / NarrowSize; 5099 bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH; 5100 unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1); 5101 5102 SmallVector<Register, 2> Src1Parts, Src2Parts; 5103 SmallVector<Register, 2> DstTmpRegs(DstTmpParts); 5104 extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts); 5105 extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts); 5106 multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy); 5107 5108 // Take only high half of registers if this is high mul. 5109 ArrayRef<Register> DstRegs( 5110 IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts); 5111 MIRBuilder.buildMerge(DstReg, DstRegs); 5112 MI.eraseFromParent(); 5113 return Legalized; 5114 } 5115 5116 LegalizerHelper::LegalizeResult 5117 LegalizerHelper::narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx, 5118 LLT NarrowTy) { 5119 if (TypeIdx != 0) 5120 return UnableToLegalize; 5121 5122 bool IsSigned = MI.getOpcode() == TargetOpcode::G_FPTOSI; 5123 5124 Register Src = MI.getOperand(1).getReg(); 5125 LLT SrcTy = MRI.getType(Src); 5126 5127 // If all finite floats fit into the narrowed integer type, we can just swap 5128 // out the result type. This is practically only useful for conversions from 5129 // half to at least 16-bits, so just handle the one case. 5130 if (SrcTy.getScalarType() != LLT::scalar(16) || 5131 NarrowTy.getScalarSizeInBits() < (IsSigned ? 17u : 16u)) 5132 return UnableToLegalize; 5133 5134 Observer.changingInstr(MI); 5135 narrowScalarDst(MI, NarrowTy, 0, 5136 IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT); 5137 Observer.changedInstr(MI); 5138 return Legalized; 5139 } 5140 5141 LegalizerHelper::LegalizeResult 5142 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, 5143 LLT NarrowTy) { 5144 if (TypeIdx != 1) 5145 return UnableToLegalize; 5146 5147 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 5148 5149 int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 5150 // FIXME: add support for when SizeOp1 isn't an exact multiple of 5151 // NarrowSize. 5152 if (SizeOp1 % NarrowSize != 0) 5153 return UnableToLegalize; 5154 int NumParts = SizeOp1 / NarrowSize; 5155 5156 SmallVector<Register, 2> SrcRegs, DstRegs; 5157 SmallVector<uint64_t, 2> Indexes; 5158 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 5159 5160 Register OpReg = MI.getOperand(0).getReg(); 5161 uint64_t OpStart = MI.getOperand(2).getImm(); 5162 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 5163 for (int i = 0; i < NumParts; ++i) { 5164 unsigned SrcStart = i * NarrowSize; 5165 5166 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) { 5167 // No part of the extract uses this subregister, ignore it. 5168 continue; 5169 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 5170 // The entire subregister is extracted, forward the value. 5171 DstRegs.push_back(SrcRegs[i]); 5172 continue; 5173 } 5174 5175 // OpSegStart is where this destination segment would start in OpReg if it 5176 // extended infinitely in both directions. 5177 int64_t ExtractOffset; 5178 uint64_t SegSize; 5179 if (OpStart < SrcStart) { 5180 ExtractOffset = 0; 5181 SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart); 5182 } else { 5183 ExtractOffset = OpStart - SrcStart; 5184 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize); 5185 } 5186 5187 Register SegReg = SrcRegs[i]; 5188 if (ExtractOffset != 0 || SegSize != NarrowSize) { 5189 // A genuine extract is needed. 5190 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 5191 MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset); 5192 } 5193 5194 DstRegs.push_back(SegReg); 5195 } 5196 5197 Register DstReg = MI.getOperand(0).getReg(); 5198 if (MRI.getType(DstReg).isVector()) 5199 MIRBuilder.buildBuildVector(DstReg, DstRegs); 5200 else if (DstRegs.size() > 1) 5201 MIRBuilder.buildMerge(DstReg, DstRegs); 5202 else 5203 MIRBuilder.buildCopy(DstReg, DstRegs[0]); 5204 MI.eraseFromParent(); 5205 return Legalized; 5206 } 5207 5208 LegalizerHelper::LegalizeResult 5209 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, 5210 LLT NarrowTy) { 5211 // FIXME: Don't know how to handle secondary types yet. 5212 if (TypeIdx != 0) 5213 return UnableToLegalize; 5214 5215 SmallVector<Register, 2> SrcRegs, LeftoverRegs, DstRegs; 5216 SmallVector<uint64_t, 2> Indexes; 5217 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); 5218 LLT LeftoverTy; 5219 extractParts(MI.getOperand(1).getReg(), RegTy, NarrowTy, LeftoverTy, SrcRegs, 5220 LeftoverRegs); 5221 5222 for (Register Reg : LeftoverRegs) 5223 SrcRegs.push_back(Reg); 5224 5225 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 5226 Register OpReg = MI.getOperand(2).getReg(); 5227 uint64_t OpStart = MI.getOperand(3).getImm(); 5228 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 5229 for (int I = 0, E = SrcRegs.size(); I != E; ++I) { 5230 unsigned DstStart = I * NarrowSize; 5231 5232 if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 5233 // The entire subregister is defined by this insert, forward the new 5234 // value. 5235 DstRegs.push_back(OpReg); 5236 continue; 5237 } 5238 5239 Register SrcReg = SrcRegs[I]; 5240 if (MRI.getType(SrcRegs[I]) == LeftoverTy) { 5241 // The leftover reg is smaller than NarrowTy, so we need to extend it. 5242 SrcReg = MRI.createGenericVirtualRegister(NarrowTy); 5243 MIRBuilder.buildAnyExt(SrcReg, SrcRegs[I]); 5244 } 5245 5246 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) { 5247 // No part of the insert affects this subregister, forward the original. 5248 DstRegs.push_back(SrcReg); 5249 continue; 5250 } 5251 5252 // OpSegStart is where this destination segment would start in OpReg if it 5253 // extended infinitely in both directions. 5254 int64_t ExtractOffset, InsertOffset; 5255 uint64_t SegSize; 5256 if (OpStart < DstStart) { 5257 InsertOffset = 0; 5258 ExtractOffset = DstStart - OpStart; 5259 SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart); 5260 } else { 5261 InsertOffset = OpStart - DstStart; 5262 ExtractOffset = 0; 5263 SegSize = 5264 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart); 5265 } 5266 5267 Register SegReg = OpReg; 5268 if (ExtractOffset != 0 || SegSize != OpSize) { 5269 // A genuine extract is needed. 5270 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 5271 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); 5272 } 5273 5274 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 5275 MIRBuilder.buildInsert(DstReg, SrcReg, SegReg, InsertOffset); 5276 DstRegs.push_back(DstReg); 5277 } 5278 5279 uint64_t WideSize = DstRegs.size() * NarrowSize; 5280 Register DstReg = MI.getOperand(0).getReg(); 5281 if (WideSize > RegTy.getSizeInBits()) { 5282 Register MergeReg = MRI.createGenericVirtualRegister(LLT::scalar(WideSize)); 5283 MIRBuilder.buildMerge(MergeReg, DstRegs); 5284 MIRBuilder.buildTrunc(DstReg, MergeReg); 5285 } else 5286 MIRBuilder.buildMerge(DstReg, DstRegs); 5287 5288 MI.eraseFromParent(); 5289 return Legalized; 5290 } 5291 5292 LegalizerHelper::LegalizeResult 5293 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, 5294 LLT NarrowTy) { 5295 Register DstReg = MI.getOperand(0).getReg(); 5296 LLT DstTy = MRI.getType(DstReg); 5297 5298 assert(MI.getNumOperands() == 3 && TypeIdx == 0); 5299 5300 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 5301 SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs; 5302 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 5303 LLT LeftoverTy; 5304 if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy, 5305 Src0Regs, Src0LeftoverRegs)) 5306 return UnableToLegalize; 5307 5308 LLT Unused; 5309 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused, 5310 Src1Regs, Src1LeftoverRegs)) 5311 llvm_unreachable("inconsistent extractParts result"); 5312 5313 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 5314 auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 5315 {Src0Regs[I], Src1Regs[I]}); 5316 DstRegs.push_back(Inst.getReg(0)); 5317 } 5318 5319 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 5320 auto Inst = MIRBuilder.buildInstr( 5321 MI.getOpcode(), 5322 {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]}); 5323 DstLeftoverRegs.push_back(Inst.getReg(0)); 5324 } 5325 5326 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 5327 LeftoverTy, DstLeftoverRegs); 5328 5329 MI.eraseFromParent(); 5330 return Legalized; 5331 } 5332 5333 LegalizerHelper::LegalizeResult 5334 LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, 5335 LLT NarrowTy) { 5336 if (TypeIdx != 0) 5337 return UnableToLegalize; 5338 5339 Register DstReg = MI.getOperand(0).getReg(); 5340 Register SrcReg = MI.getOperand(1).getReg(); 5341 5342 LLT DstTy = MRI.getType(DstReg); 5343 if (DstTy.isVector()) 5344 return UnableToLegalize; 5345 5346 SmallVector<Register, 8> Parts; 5347 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 5348 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, MI.getOpcode()); 5349 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 5350 5351 MI.eraseFromParent(); 5352 return Legalized; 5353 } 5354 5355 LegalizerHelper::LegalizeResult 5356 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, 5357 LLT NarrowTy) { 5358 if (TypeIdx != 0) 5359 return UnableToLegalize; 5360 5361 Register CondReg = MI.getOperand(1).getReg(); 5362 LLT CondTy = MRI.getType(CondReg); 5363 if (CondTy.isVector()) // TODO: Handle vselect 5364 return UnableToLegalize; 5365 5366 Register DstReg = MI.getOperand(0).getReg(); 5367 LLT DstTy = MRI.getType(DstReg); 5368 5369 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 5370 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 5371 SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs; 5372 LLT LeftoverTy; 5373 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy, 5374 Src1Regs, Src1LeftoverRegs)) 5375 return UnableToLegalize; 5376 5377 LLT Unused; 5378 if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused, 5379 Src2Regs, Src2LeftoverRegs)) 5380 llvm_unreachable("inconsistent extractParts result"); 5381 5382 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 5383 auto Select = MIRBuilder.buildSelect(NarrowTy, 5384 CondReg, Src1Regs[I], Src2Regs[I]); 5385 DstRegs.push_back(Select.getReg(0)); 5386 } 5387 5388 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 5389 auto Select = MIRBuilder.buildSelect( 5390 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); 5391 DstLeftoverRegs.push_back(Select.getReg(0)); 5392 } 5393 5394 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 5395 LeftoverTy, DstLeftoverRegs); 5396 5397 MI.eraseFromParent(); 5398 return Legalized; 5399 } 5400 5401 LegalizerHelper::LegalizeResult 5402 LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, 5403 LLT NarrowTy) { 5404 if (TypeIdx != 1) 5405 return UnableToLegalize; 5406 5407 Register DstReg = MI.getOperand(0).getReg(); 5408 Register SrcReg = MI.getOperand(1).getReg(); 5409 LLT DstTy = MRI.getType(DstReg); 5410 LLT SrcTy = MRI.getType(SrcReg); 5411 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5412 5413 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5414 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF; 5415 5416 MachineIRBuilder &B = MIRBuilder; 5417 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 5418 // ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi) 5419 auto C_0 = B.buildConstant(NarrowTy, 0); 5420 auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 5421 UnmergeSrc.getReg(1), C_0); 5422 auto LoCTLZ = IsUndef ? 5423 B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)) : 5424 B.buildCTLZ(DstTy, UnmergeSrc.getReg(0)); 5425 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 5426 auto HiIsZeroCTLZ = B.buildAdd(DstTy, LoCTLZ, C_NarrowSize); 5427 auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)); 5428 B.buildSelect(DstReg, HiIsZero, HiIsZeroCTLZ, HiCTLZ); 5429 5430 MI.eraseFromParent(); 5431 return Legalized; 5432 } 5433 5434 return UnableToLegalize; 5435 } 5436 5437 LegalizerHelper::LegalizeResult 5438 LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, 5439 LLT NarrowTy) { 5440 if (TypeIdx != 1) 5441 return UnableToLegalize; 5442 5443 Register DstReg = MI.getOperand(0).getReg(); 5444 Register SrcReg = MI.getOperand(1).getReg(); 5445 LLT DstTy = MRI.getType(DstReg); 5446 LLT SrcTy = MRI.getType(SrcReg); 5447 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5448 5449 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5450 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF; 5451 5452 MachineIRBuilder &B = MIRBuilder; 5453 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 5454 // cttz(Hi:Lo) -> Lo == 0 ? (cttz(Hi) + NarrowSize) : cttz(Lo) 5455 auto C_0 = B.buildConstant(NarrowTy, 0); 5456 auto LoIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 5457 UnmergeSrc.getReg(0), C_0); 5458 auto HiCTTZ = IsUndef ? 5459 B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)) : 5460 B.buildCTTZ(DstTy, UnmergeSrc.getReg(1)); 5461 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 5462 auto LoIsZeroCTTZ = B.buildAdd(DstTy, HiCTTZ, C_NarrowSize); 5463 auto LoCTTZ = B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)); 5464 B.buildSelect(DstReg, LoIsZero, LoIsZeroCTTZ, LoCTTZ); 5465 5466 MI.eraseFromParent(); 5467 return Legalized; 5468 } 5469 5470 return UnableToLegalize; 5471 } 5472 5473 LegalizerHelper::LegalizeResult 5474 LegalizerHelper::narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, 5475 LLT NarrowTy) { 5476 if (TypeIdx != 1) 5477 return UnableToLegalize; 5478 5479 Register DstReg = MI.getOperand(0).getReg(); 5480 LLT DstTy = MRI.getType(DstReg); 5481 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 5482 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5483 5484 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5485 auto UnmergeSrc = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 5486 5487 auto LoCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(0)); 5488 auto HiCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(1)); 5489 MIRBuilder.buildAdd(DstReg, HiCTPOP, LoCTPOP); 5490 5491 MI.eraseFromParent(); 5492 return Legalized; 5493 } 5494 5495 return UnableToLegalize; 5496 } 5497 5498 LegalizerHelper::LegalizeResult 5499 LegalizerHelper::lowerBitCount(MachineInstr &MI) { 5500 unsigned Opc = MI.getOpcode(); 5501 const auto &TII = MIRBuilder.getTII(); 5502 auto isSupported = [this](const LegalityQuery &Q) { 5503 auto QAction = LI.getAction(Q).Action; 5504 return QAction == Legal || QAction == Libcall || QAction == Custom; 5505 }; 5506 switch (Opc) { 5507 default: 5508 return UnableToLegalize; 5509 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 5510 // This trivially expands to CTLZ. 5511 Observer.changingInstr(MI); 5512 MI.setDesc(TII.get(TargetOpcode::G_CTLZ)); 5513 Observer.changedInstr(MI); 5514 return Legalized; 5515 } 5516 case TargetOpcode::G_CTLZ: { 5517 Register DstReg = MI.getOperand(0).getReg(); 5518 Register SrcReg = MI.getOperand(1).getReg(); 5519 LLT DstTy = MRI.getType(DstReg); 5520 LLT SrcTy = MRI.getType(SrcReg); 5521 unsigned Len = SrcTy.getSizeInBits(); 5522 5523 if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 5524 // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero. 5525 auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg); 5526 auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0); 5527 auto ICmp = MIRBuilder.buildICmp( 5528 CmpInst::ICMP_EQ, SrcTy.changeElementSize(1), SrcReg, ZeroSrc); 5529 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 5530 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CtlzZU); 5531 MI.eraseFromParent(); 5532 return Legalized; 5533 } 5534 // for now, we do this: 5535 // NewLen = NextPowerOf2(Len); 5536 // x = x | (x >> 1); 5537 // x = x | (x >> 2); 5538 // ... 5539 // x = x | (x >>16); 5540 // x = x | (x >>32); // for 64-bit input 5541 // Upto NewLen/2 5542 // return Len - popcount(x); 5543 // 5544 // Ref: "Hacker's Delight" by Henry Warren 5545 Register Op = SrcReg; 5546 unsigned NewLen = PowerOf2Ceil(Len); 5547 for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) { 5548 auto MIBShiftAmt = MIRBuilder.buildConstant(SrcTy, 1ULL << i); 5549 auto MIBOp = MIRBuilder.buildOr( 5550 SrcTy, Op, MIRBuilder.buildLShr(SrcTy, Op, MIBShiftAmt)); 5551 Op = MIBOp.getReg(0); 5552 } 5553 auto MIBPop = MIRBuilder.buildCTPOP(DstTy, Op); 5554 MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(DstTy, Len), 5555 MIBPop); 5556 MI.eraseFromParent(); 5557 return Legalized; 5558 } 5559 case TargetOpcode::G_CTTZ_ZERO_UNDEF: { 5560 // This trivially expands to CTTZ. 5561 Observer.changingInstr(MI); 5562 MI.setDesc(TII.get(TargetOpcode::G_CTTZ)); 5563 Observer.changedInstr(MI); 5564 return Legalized; 5565 } 5566 case TargetOpcode::G_CTTZ: { 5567 Register DstReg = MI.getOperand(0).getReg(); 5568 Register SrcReg = MI.getOperand(1).getReg(); 5569 LLT DstTy = MRI.getType(DstReg); 5570 LLT SrcTy = MRI.getType(SrcReg); 5571 5572 unsigned Len = SrcTy.getSizeInBits(); 5573 if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 5574 // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with 5575 // zero. 5576 auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg); 5577 auto Zero = MIRBuilder.buildConstant(SrcTy, 0); 5578 auto ICmp = MIRBuilder.buildICmp( 5579 CmpInst::ICMP_EQ, DstTy.changeElementSize(1), SrcReg, Zero); 5580 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 5581 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CttzZU); 5582 MI.eraseFromParent(); 5583 return Legalized; 5584 } 5585 // for now, we use: { return popcount(~x & (x - 1)); } 5586 // unless the target has ctlz but not ctpop, in which case we use: 5587 // { return 32 - nlz(~x & (x-1)); } 5588 // Ref: "Hacker's Delight" by Henry Warren 5589 auto MIBCstNeg1 = MIRBuilder.buildConstant(SrcTy, -1); 5590 auto MIBNot = MIRBuilder.buildXor(SrcTy, SrcReg, MIBCstNeg1); 5591 auto MIBTmp = MIRBuilder.buildAnd( 5592 SrcTy, MIBNot, MIRBuilder.buildAdd(SrcTy, SrcReg, MIBCstNeg1)); 5593 if (!isSupported({TargetOpcode::G_CTPOP, {SrcTy, SrcTy}}) && 5594 isSupported({TargetOpcode::G_CTLZ, {SrcTy, SrcTy}})) { 5595 auto MIBCstLen = MIRBuilder.buildConstant(SrcTy, Len); 5596 MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen, 5597 MIRBuilder.buildCTLZ(SrcTy, MIBTmp)); 5598 MI.eraseFromParent(); 5599 return Legalized; 5600 } 5601 MI.setDesc(TII.get(TargetOpcode::G_CTPOP)); 5602 MI.getOperand(1).setReg(MIBTmp.getReg(0)); 5603 return Legalized; 5604 } 5605 case TargetOpcode::G_CTPOP: { 5606 Register SrcReg = MI.getOperand(1).getReg(); 5607 LLT Ty = MRI.getType(SrcReg); 5608 unsigned Size = Ty.getSizeInBits(); 5609 MachineIRBuilder &B = MIRBuilder; 5610 5611 // Count set bits in blocks of 2 bits. Default approach would be 5612 // B2Count = { val & 0x55555555 } + { (val >> 1) & 0x55555555 } 5613 // We use following formula instead: 5614 // B2Count = val - { (val >> 1) & 0x55555555 } 5615 // since it gives same result in blocks of 2 with one instruction less. 5616 auto C_1 = B.buildConstant(Ty, 1); 5617 auto B2Set1LoTo1Hi = B.buildLShr(Ty, SrcReg, C_1); 5618 APInt B2Mask1HiTo0 = APInt::getSplat(Size, APInt(8, 0x55)); 5619 auto C_B2Mask1HiTo0 = B.buildConstant(Ty, B2Mask1HiTo0); 5620 auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0); 5621 auto B2Count = B.buildSub(Ty, SrcReg, B2Count1Hi); 5622 5623 // In order to get count in blocks of 4 add values from adjacent block of 2. 5624 // B4Count = { B2Count & 0x33333333 } + { (B2Count >> 2) & 0x33333333 } 5625 auto C_2 = B.buildConstant(Ty, 2); 5626 auto B4Set2LoTo2Hi = B.buildLShr(Ty, B2Count, C_2); 5627 APInt B4Mask2HiTo0 = APInt::getSplat(Size, APInt(8, 0x33)); 5628 auto C_B4Mask2HiTo0 = B.buildConstant(Ty, B4Mask2HiTo0); 5629 auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0); 5630 auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0); 5631 auto B4Count = B.buildAdd(Ty, B4HiB2Count, B4LoB2Count); 5632 5633 // For count in blocks of 8 bits we don't have to mask high 4 bits before 5634 // addition since count value sits in range {0,...,8} and 4 bits are enough 5635 // to hold such binary values. After addition high 4 bits still hold count 5636 // of set bits in high 4 bit block, set them to zero and get 8 bit result. 5637 // B8Count = { B4Count + (B4Count >> 4) } & 0x0F0F0F0F 5638 auto C_4 = B.buildConstant(Ty, 4); 5639 auto B8HiB4Count = B.buildLShr(Ty, B4Count, C_4); 5640 auto B8CountDirty4Hi = B.buildAdd(Ty, B8HiB4Count, B4Count); 5641 APInt B8Mask4HiTo0 = APInt::getSplat(Size, APInt(8, 0x0F)); 5642 auto C_B8Mask4HiTo0 = B.buildConstant(Ty, B8Mask4HiTo0); 5643 auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0); 5644 5645 assert(Size<=128 && "Scalar size is too large for CTPOP lower algorithm"); 5646 // 8 bits can hold CTPOP result of 128 bit int or smaller. Mul with this 5647 // bitmask will set 8 msb in ResTmp to sum of all B8Counts in 8 bit blocks. 5648 auto MulMask = B.buildConstant(Ty, APInt::getSplat(Size, APInt(8, 0x01))); 5649 auto ResTmp = B.buildMul(Ty, B8Count, MulMask); 5650 5651 // Shift count result from 8 high bits to low bits. 5652 auto C_SizeM8 = B.buildConstant(Ty, Size - 8); 5653 B.buildLShr(MI.getOperand(0).getReg(), ResTmp, C_SizeM8); 5654 5655 MI.eraseFromParent(); 5656 return Legalized; 5657 } 5658 } 5659 } 5660 5661 // Check that (every element of) Reg is undef or not an exact multiple of BW. 5662 static bool isNonZeroModBitWidthOrUndef(const MachineRegisterInfo &MRI, 5663 Register Reg, unsigned BW) { 5664 return matchUnaryPredicate( 5665 MRI, Reg, 5666 [=](const Constant *C) { 5667 // Null constant here means an undef. 5668 const ConstantInt *CI = dyn_cast_or_null<ConstantInt>(C); 5669 return !CI || CI->getValue().urem(BW) != 0; 5670 }, 5671 /*AllowUndefs*/ true); 5672 } 5673 5674 LegalizerHelper::LegalizeResult 5675 LegalizerHelper::lowerFunnelShiftWithInverse(MachineInstr &MI) { 5676 Register Dst = MI.getOperand(0).getReg(); 5677 Register X = MI.getOperand(1).getReg(); 5678 Register Y = MI.getOperand(2).getReg(); 5679 Register Z = MI.getOperand(3).getReg(); 5680 LLT Ty = MRI.getType(Dst); 5681 LLT ShTy = MRI.getType(Z); 5682 5683 unsigned BW = Ty.getScalarSizeInBits(); 5684 5685 if (!isPowerOf2_32(BW)) 5686 return UnableToLegalize; 5687 5688 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5689 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; 5690 5691 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { 5692 // fshl X, Y, Z -> fshr X, Y, -Z 5693 // fshr X, Y, Z -> fshl X, Y, -Z 5694 auto Zero = MIRBuilder.buildConstant(ShTy, 0); 5695 Z = MIRBuilder.buildSub(Ty, Zero, Z).getReg(0); 5696 } else { 5697 // fshl X, Y, Z -> fshr (srl X, 1), (fshr X, Y, 1), ~Z 5698 // fshr X, Y, Z -> fshl (fshl X, Y, 1), (shl Y, 1), ~Z 5699 auto One = MIRBuilder.buildConstant(ShTy, 1); 5700 if (IsFSHL) { 5701 Y = MIRBuilder.buildInstr(RevOpcode, {Ty}, {X, Y, One}).getReg(0); 5702 X = MIRBuilder.buildLShr(Ty, X, One).getReg(0); 5703 } else { 5704 X = MIRBuilder.buildInstr(RevOpcode, {Ty}, {X, Y, One}).getReg(0); 5705 Y = MIRBuilder.buildShl(Ty, Y, One).getReg(0); 5706 } 5707 5708 Z = MIRBuilder.buildNot(ShTy, Z).getReg(0); 5709 } 5710 5711 MIRBuilder.buildInstr(RevOpcode, {Dst}, {X, Y, Z}); 5712 MI.eraseFromParent(); 5713 return Legalized; 5714 } 5715 5716 LegalizerHelper::LegalizeResult 5717 LegalizerHelper::lowerFunnelShiftAsShifts(MachineInstr &MI) { 5718 Register Dst = MI.getOperand(0).getReg(); 5719 Register X = MI.getOperand(1).getReg(); 5720 Register Y = MI.getOperand(2).getReg(); 5721 Register Z = MI.getOperand(3).getReg(); 5722 LLT Ty = MRI.getType(Dst); 5723 LLT ShTy = MRI.getType(Z); 5724 5725 const unsigned BW = Ty.getScalarSizeInBits(); 5726 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5727 5728 Register ShX, ShY; 5729 Register ShAmt, InvShAmt; 5730 5731 // FIXME: Emit optimized urem by constant instead of letting it expand later. 5732 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { 5733 // fshl: X << C | Y >> (BW - C) 5734 // fshr: X << (BW - C) | Y >> C 5735 // where C = Z % BW is not zero 5736 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); 5737 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); 5738 InvShAmt = MIRBuilder.buildSub(ShTy, BitWidthC, ShAmt).getReg(0); 5739 ShX = MIRBuilder.buildShl(Ty, X, IsFSHL ? ShAmt : InvShAmt).getReg(0); 5740 ShY = MIRBuilder.buildLShr(Ty, Y, IsFSHL ? InvShAmt : ShAmt).getReg(0); 5741 } else { 5742 // fshl: X << (Z % BW) | Y >> 1 >> (BW - 1 - (Z % BW)) 5743 // fshr: X << 1 << (BW - 1 - (Z % BW)) | Y >> (Z % BW) 5744 auto Mask = MIRBuilder.buildConstant(ShTy, BW - 1); 5745 if (isPowerOf2_32(BW)) { 5746 // Z % BW -> Z & (BW - 1) 5747 ShAmt = MIRBuilder.buildAnd(ShTy, Z, Mask).getReg(0); 5748 // (BW - 1) - (Z % BW) -> ~Z & (BW - 1) 5749 auto NotZ = MIRBuilder.buildNot(ShTy, Z); 5750 InvShAmt = MIRBuilder.buildAnd(ShTy, NotZ, Mask).getReg(0); 5751 } else { 5752 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); 5753 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); 5754 InvShAmt = MIRBuilder.buildSub(ShTy, Mask, ShAmt).getReg(0); 5755 } 5756 5757 auto One = MIRBuilder.buildConstant(ShTy, 1); 5758 if (IsFSHL) { 5759 ShX = MIRBuilder.buildShl(Ty, X, ShAmt).getReg(0); 5760 auto ShY1 = MIRBuilder.buildLShr(Ty, Y, One); 5761 ShY = MIRBuilder.buildLShr(Ty, ShY1, InvShAmt).getReg(0); 5762 } else { 5763 auto ShX1 = MIRBuilder.buildShl(Ty, X, One); 5764 ShX = MIRBuilder.buildShl(Ty, ShX1, InvShAmt).getReg(0); 5765 ShY = MIRBuilder.buildLShr(Ty, Y, ShAmt).getReg(0); 5766 } 5767 } 5768 5769 MIRBuilder.buildOr(Dst, ShX, ShY); 5770 MI.eraseFromParent(); 5771 return Legalized; 5772 } 5773 5774 LegalizerHelper::LegalizeResult 5775 LegalizerHelper::lowerFunnelShift(MachineInstr &MI) { 5776 // These operations approximately do the following (while avoiding undefined 5777 // shifts by BW): 5778 // G_FSHL: (X << (Z % BW)) | (Y >> (BW - (Z % BW))) 5779 // G_FSHR: (X << (BW - (Z % BW))) | (Y >> (Z % BW)) 5780 Register Dst = MI.getOperand(0).getReg(); 5781 LLT Ty = MRI.getType(Dst); 5782 LLT ShTy = MRI.getType(MI.getOperand(3).getReg()); 5783 5784 bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5785 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; 5786 5787 // TODO: Use smarter heuristic that accounts for vector legalization. 5788 if (LI.getAction({RevOpcode, {Ty, ShTy}}).Action == Lower) 5789 return lowerFunnelShiftAsShifts(MI); 5790 5791 // This only works for powers of 2, fallback to shifts if it fails. 5792 LegalizerHelper::LegalizeResult Result = lowerFunnelShiftWithInverse(MI); 5793 if (Result == UnableToLegalize) 5794 return lowerFunnelShiftAsShifts(MI); 5795 return Result; 5796 } 5797 5798 LegalizerHelper::LegalizeResult 5799 LegalizerHelper::lowerRotateWithReverseRotate(MachineInstr &MI) { 5800 Register Dst = MI.getOperand(0).getReg(); 5801 Register Src = MI.getOperand(1).getReg(); 5802 Register Amt = MI.getOperand(2).getReg(); 5803 LLT AmtTy = MRI.getType(Amt); 5804 auto Zero = MIRBuilder.buildConstant(AmtTy, 0); 5805 bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL; 5806 unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL; 5807 auto Neg = MIRBuilder.buildSub(AmtTy, Zero, Amt); 5808 MIRBuilder.buildInstr(RevRot, {Dst}, {Src, Neg}); 5809 MI.eraseFromParent(); 5810 return Legalized; 5811 } 5812 5813 LegalizerHelper::LegalizeResult LegalizerHelper::lowerRotate(MachineInstr &MI) { 5814 Register Dst = MI.getOperand(0).getReg(); 5815 Register Src = MI.getOperand(1).getReg(); 5816 Register Amt = MI.getOperand(2).getReg(); 5817 LLT DstTy = MRI.getType(Dst); 5818 LLT SrcTy = MRI.getType(Dst); 5819 LLT AmtTy = MRI.getType(Amt); 5820 5821 unsigned EltSizeInBits = DstTy.getScalarSizeInBits(); 5822 bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL; 5823 5824 MIRBuilder.setInstrAndDebugLoc(MI); 5825 5826 // If a rotate in the other direction is supported, use it. 5827 unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL; 5828 if (LI.isLegalOrCustom({RevRot, {DstTy, SrcTy}}) && 5829 isPowerOf2_32(EltSizeInBits)) 5830 return lowerRotateWithReverseRotate(MI); 5831 5832 auto Zero = MIRBuilder.buildConstant(AmtTy, 0); 5833 unsigned ShOpc = IsLeft ? TargetOpcode::G_SHL : TargetOpcode::G_LSHR; 5834 unsigned RevShiftOpc = IsLeft ? TargetOpcode::G_LSHR : TargetOpcode::G_SHL; 5835 auto BitWidthMinusOneC = MIRBuilder.buildConstant(AmtTy, EltSizeInBits - 1); 5836 Register ShVal; 5837 Register RevShiftVal; 5838 if (isPowerOf2_32(EltSizeInBits)) { 5839 // (rotl x, c) -> x << (c & (w - 1)) | x >> (-c & (w - 1)) 5840 // (rotr x, c) -> x >> (c & (w - 1)) | x << (-c & (w - 1)) 5841 auto NegAmt = MIRBuilder.buildSub(AmtTy, Zero, Amt); 5842 auto ShAmt = MIRBuilder.buildAnd(AmtTy, Amt, BitWidthMinusOneC); 5843 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); 5844 auto RevAmt = MIRBuilder.buildAnd(AmtTy, NegAmt, BitWidthMinusOneC); 5845 RevShiftVal = 5846 MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Src, RevAmt}).getReg(0); 5847 } else { 5848 // (rotl x, c) -> x << (c % w) | x >> 1 >> (w - 1 - (c % w)) 5849 // (rotr x, c) -> x >> (c % w) | x << 1 << (w - 1 - (c % w)) 5850 auto BitWidthC = MIRBuilder.buildConstant(AmtTy, EltSizeInBits); 5851 auto ShAmt = MIRBuilder.buildURem(AmtTy, Amt, BitWidthC); 5852 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); 5853 auto RevAmt = MIRBuilder.buildSub(AmtTy, BitWidthMinusOneC, ShAmt); 5854 auto One = MIRBuilder.buildConstant(AmtTy, 1); 5855 auto Inner = MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Src, One}); 5856 RevShiftVal = 5857 MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Inner, RevAmt}).getReg(0); 5858 } 5859 MIRBuilder.buildOr(Dst, ShVal, RevShiftVal); 5860 MI.eraseFromParent(); 5861 return Legalized; 5862 } 5863 5864 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float 5865 // representation. 5866 LegalizerHelper::LegalizeResult 5867 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) { 5868 Register Dst = MI.getOperand(0).getReg(); 5869 Register Src = MI.getOperand(1).getReg(); 5870 const LLT S64 = LLT::scalar(64); 5871 const LLT S32 = LLT::scalar(32); 5872 const LLT S1 = LLT::scalar(1); 5873 5874 assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32); 5875 5876 // unsigned cul2f(ulong u) { 5877 // uint lz = clz(u); 5878 // uint e = (u != 0) ? 127U + 63U - lz : 0; 5879 // u = (u << lz) & 0x7fffffffffffffffUL; 5880 // ulong t = u & 0xffffffffffUL; 5881 // uint v = (e << 23) | (uint)(u >> 40); 5882 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U); 5883 // return as_float(v + r); 5884 // } 5885 5886 auto Zero32 = MIRBuilder.buildConstant(S32, 0); 5887 auto Zero64 = MIRBuilder.buildConstant(S64, 0); 5888 5889 auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src); 5890 5891 auto K = MIRBuilder.buildConstant(S32, 127U + 63U); 5892 auto Sub = MIRBuilder.buildSub(S32, K, LZ); 5893 5894 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64); 5895 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32); 5896 5897 auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1); 5898 auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ); 5899 5900 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0); 5901 5902 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); 5903 auto T = MIRBuilder.buildAnd(S64, U, Mask1); 5904 5905 auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40)); 5906 auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23)); 5907 auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl)); 5908 5909 auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL); 5910 auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C); 5911 auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C); 5912 auto One = MIRBuilder.buildConstant(S32, 1); 5913 5914 auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One); 5915 auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32); 5916 auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0); 5917 MIRBuilder.buildAdd(Dst, V, R); 5918 5919 MI.eraseFromParent(); 5920 return Legalized; 5921 } 5922 5923 LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) { 5924 Register Dst = MI.getOperand(0).getReg(); 5925 Register Src = MI.getOperand(1).getReg(); 5926 LLT DstTy = MRI.getType(Dst); 5927 LLT SrcTy = MRI.getType(Src); 5928 5929 if (SrcTy == LLT::scalar(1)) { 5930 auto True = MIRBuilder.buildFConstant(DstTy, 1.0); 5931 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5932 MIRBuilder.buildSelect(Dst, Src, True, False); 5933 MI.eraseFromParent(); 5934 return Legalized; 5935 } 5936 5937 if (SrcTy != LLT::scalar(64)) 5938 return UnableToLegalize; 5939 5940 if (DstTy == LLT::scalar(32)) { 5941 // TODO: SelectionDAG has several alternative expansions to port which may 5942 // be more reasonble depending on the available instructions. If a target 5943 // has sitofp, does not have CTLZ, or can efficiently use f64 as an 5944 // intermediate type, this is probably worse. 5945 return lowerU64ToF32BitOps(MI); 5946 } 5947 5948 return UnableToLegalize; 5949 } 5950 5951 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) { 5952 Register Dst = MI.getOperand(0).getReg(); 5953 Register Src = MI.getOperand(1).getReg(); 5954 LLT DstTy = MRI.getType(Dst); 5955 LLT SrcTy = MRI.getType(Src); 5956 5957 const LLT S64 = LLT::scalar(64); 5958 const LLT S32 = LLT::scalar(32); 5959 const LLT S1 = LLT::scalar(1); 5960 5961 if (SrcTy == S1) { 5962 auto True = MIRBuilder.buildFConstant(DstTy, -1.0); 5963 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5964 MIRBuilder.buildSelect(Dst, Src, True, False); 5965 MI.eraseFromParent(); 5966 return Legalized; 5967 } 5968 5969 if (SrcTy != S64) 5970 return UnableToLegalize; 5971 5972 if (DstTy == S32) { 5973 // signed cl2f(long l) { 5974 // long s = l >> 63; 5975 // float r = cul2f((l + s) ^ s); 5976 // return s ? -r : r; 5977 // } 5978 Register L = Src; 5979 auto SignBit = MIRBuilder.buildConstant(S64, 63); 5980 auto S = MIRBuilder.buildAShr(S64, L, SignBit); 5981 5982 auto LPlusS = MIRBuilder.buildAdd(S64, L, S); 5983 auto Xor = MIRBuilder.buildXor(S64, LPlusS, S); 5984 auto R = MIRBuilder.buildUITOFP(S32, Xor); 5985 5986 auto RNeg = MIRBuilder.buildFNeg(S32, R); 5987 auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S, 5988 MIRBuilder.buildConstant(S64, 0)); 5989 MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R); 5990 MI.eraseFromParent(); 5991 return Legalized; 5992 } 5993 5994 return UnableToLegalize; 5995 } 5996 5997 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) { 5998 Register Dst = MI.getOperand(0).getReg(); 5999 Register Src = MI.getOperand(1).getReg(); 6000 LLT DstTy = MRI.getType(Dst); 6001 LLT SrcTy = MRI.getType(Src); 6002 const LLT S64 = LLT::scalar(64); 6003 const LLT S32 = LLT::scalar(32); 6004 6005 if (SrcTy != S64 && SrcTy != S32) 6006 return UnableToLegalize; 6007 if (DstTy != S32 && DstTy != S64) 6008 return UnableToLegalize; 6009 6010 // FPTOSI gives same result as FPTOUI for positive signed integers. 6011 // FPTOUI needs to deal with fp values that convert to unsigned integers 6012 // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp. 6013 6014 APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits()); 6015 APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle() 6016 : APFloat::IEEEdouble(), 6017 APInt::getNullValue(SrcTy.getSizeInBits())); 6018 TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven); 6019 6020 MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src); 6021 6022 MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP); 6023 // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on 6024 // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1. 6025 MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold); 6026 MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub); 6027 MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt); 6028 MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit); 6029 6030 const LLT S1 = LLT::scalar(1); 6031 6032 MachineInstrBuilder FCMP = 6033 MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold); 6034 MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res); 6035 6036 MI.eraseFromParent(); 6037 return Legalized; 6038 } 6039 6040 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) { 6041 Register Dst = MI.getOperand(0).getReg(); 6042 Register Src = MI.getOperand(1).getReg(); 6043 LLT DstTy = MRI.getType(Dst); 6044 LLT SrcTy = MRI.getType(Src); 6045 const LLT S64 = LLT::scalar(64); 6046 const LLT S32 = LLT::scalar(32); 6047 6048 // FIXME: Only f32 to i64 conversions are supported. 6049 if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64) 6050 return UnableToLegalize; 6051 6052 // Expand f32 -> i64 conversion 6053 // This algorithm comes from compiler-rt's implementation of fixsfdi: 6054 // https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/fixsfdi.c 6055 6056 unsigned SrcEltBits = SrcTy.getScalarSizeInBits(); 6057 6058 auto ExponentMask = MIRBuilder.buildConstant(SrcTy, 0x7F800000); 6059 auto ExponentLoBit = MIRBuilder.buildConstant(SrcTy, 23); 6060 6061 auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask); 6062 auto ExponentBits = MIRBuilder.buildLShr(SrcTy, AndExpMask, ExponentLoBit); 6063 6064 auto SignMask = MIRBuilder.buildConstant(SrcTy, 6065 APInt::getSignMask(SrcEltBits)); 6066 auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask); 6067 auto SignLowBit = MIRBuilder.buildConstant(SrcTy, SrcEltBits - 1); 6068 auto Sign = MIRBuilder.buildAShr(SrcTy, AndSignMask, SignLowBit); 6069 Sign = MIRBuilder.buildSExt(DstTy, Sign); 6070 6071 auto MantissaMask = MIRBuilder.buildConstant(SrcTy, 0x007FFFFF); 6072 auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask); 6073 auto K = MIRBuilder.buildConstant(SrcTy, 0x00800000); 6074 6075 auto R = MIRBuilder.buildOr(SrcTy, AndMantissaMask, K); 6076 R = MIRBuilder.buildZExt(DstTy, R); 6077 6078 auto Bias = MIRBuilder.buildConstant(SrcTy, 127); 6079 auto Exponent = MIRBuilder.buildSub(SrcTy, ExponentBits, Bias); 6080 auto SubExponent = MIRBuilder.buildSub(SrcTy, Exponent, ExponentLoBit); 6081 auto ExponentSub = MIRBuilder.buildSub(SrcTy, ExponentLoBit, Exponent); 6082 6083 auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent); 6084 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); 6085 6086 const LLT S1 = LLT::scalar(1); 6087 auto CmpGt = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, 6088 S1, Exponent, ExponentLoBit); 6089 6090 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl); 6091 6092 auto XorSign = MIRBuilder.buildXor(DstTy, R, Sign); 6093 auto Ret = MIRBuilder.buildSub(DstTy, XorSign, Sign); 6094 6095 auto ZeroSrcTy = MIRBuilder.buildConstant(SrcTy, 0); 6096 6097 auto ExponentLt0 = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, 6098 S1, Exponent, ZeroSrcTy); 6099 6100 auto ZeroDstTy = MIRBuilder.buildConstant(DstTy, 0); 6101 MIRBuilder.buildSelect(Dst, ExponentLt0, ZeroDstTy, Ret); 6102 6103 MI.eraseFromParent(); 6104 return Legalized; 6105 } 6106 6107 // f64 -> f16 conversion using round-to-nearest-even rounding mode. 6108 LegalizerHelper::LegalizeResult 6109 LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) { 6110 Register Dst = MI.getOperand(0).getReg(); 6111 Register Src = MI.getOperand(1).getReg(); 6112 6113 if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly. 6114 return UnableToLegalize; 6115 6116 const unsigned ExpMask = 0x7ff; 6117 const unsigned ExpBiasf64 = 1023; 6118 const unsigned ExpBiasf16 = 15; 6119 const LLT S32 = LLT::scalar(32); 6120 const LLT S1 = LLT::scalar(1); 6121 6122 auto Unmerge = MIRBuilder.buildUnmerge(S32, Src); 6123 Register U = Unmerge.getReg(0); 6124 Register UH = Unmerge.getReg(1); 6125 6126 auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20)); 6127 E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask)); 6128 6129 // Subtract the fp64 exponent bias (1023) to get the real exponent and 6130 // add the f16 bias (15) to get the biased exponent for the f16 format. 6131 E = MIRBuilder.buildAdd( 6132 S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16)); 6133 6134 auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8)); 6135 M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe)); 6136 6137 auto MaskedSig = MIRBuilder.buildAnd(S32, UH, 6138 MIRBuilder.buildConstant(S32, 0x1ff)); 6139 MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U); 6140 6141 auto Zero = MIRBuilder.buildConstant(S32, 0); 6142 auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero); 6143 auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0); 6144 M = MIRBuilder.buildOr(S32, M, Lo40Set); 6145 6146 // (M != 0 ? 0x0200 : 0) | 0x7c00; 6147 auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200); 6148 auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero); 6149 auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero); 6150 6151 auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00); 6152 auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00); 6153 6154 // N = M | (E << 12); 6155 auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12)); 6156 auto N = MIRBuilder.buildOr(S32, M, EShl12); 6157 6158 // B = clamp(1-E, 0, 13); 6159 auto One = MIRBuilder.buildConstant(S32, 1); 6160 auto OneSubExp = MIRBuilder.buildSub(S32, One, E); 6161 auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero); 6162 B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13)); 6163 6164 auto SigSetHigh = MIRBuilder.buildOr(S32, M, 6165 MIRBuilder.buildConstant(S32, 0x1000)); 6166 6167 auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B); 6168 auto D0 = MIRBuilder.buildShl(S32, D, B); 6169 6170 auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, 6171 D0, SigSetHigh); 6172 auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh); 6173 D = MIRBuilder.buildOr(S32, D, D1); 6174 6175 auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One); 6176 auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N); 6177 6178 auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7)); 6179 V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2)); 6180 6181 auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3, 6182 MIRBuilder.buildConstant(S32, 3)); 6183 auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3); 6184 6185 auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3, 6186 MIRBuilder.buildConstant(S32, 5)); 6187 auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5); 6188 6189 V1 = MIRBuilder.buildOr(S32, V0, V1); 6190 V = MIRBuilder.buildAdd(S32, V, V1); 6191 6192 auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, 6193 E, MIRBuilder.buildConstant(S32, 30)); 6194 V = MIRBuilder.buildSelect(S32, CmpEGt30, 6195 MIRBuilder.buildConstant(S32, 0x7c00), V); 6196 6197 auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, 6198 E, MIRBuilder.buildConstant(S32, 1039)); 6199 V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V); 6200 6201 // Extract the sign bit. 6202 auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16)); 6203 Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000)); 6204 6205 // Insert the sign bit 6206 V = MIRBuilder.buildOr(S32, Sign, V); 6207 6208 MIRBuilder.buildTrunc(Dst, V); 6209 MI.eraseFromParent(); 6210 return Legalized; 6211 } 6212 6213 LegalizerHelper::LegalizeResult 6214 LegalizerHelper::lowerFPTRUNC(MachineInstr &MI) { 6215 Register Dst = MI.getOperand(0).getReg(); 6216 Register Src = MI.getOperand(1).getReg(); 6217 6218 LLT DstTy = MRI.getType(Dst); 6219 LLT SrcTy = MRI.getType(Src); 6220 const LLT S64 = LLT::scalar(64); 6221 const LLT S16 = LLT::scalar(16); 6222 6223 if (DstTy.getScalarType() == S16 && SrcTy.getScalarType() == S64) 6224 return lowerFPTRUNC_F64_TO_F16(MI); 6225 6226 return UnableToLegalize; 6227 } 6228 6229 // TODO: If RHS is a constant SelectionDAGBuilder expands this into a 6230 // multiplication tree. 6231 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPOWI(MachineInstr &MI) { 6232 Register Dst = MI.getOperand(0).getReg(); 6233 Register Src0 = MI.getOperand(1).getReg(); 6234 Register Src1 = MI.getOperand(2).getReg(); 6235 LLT Ty = MRI.getType(Dst); 6236 6237 auto CvtSrc1 = MIRBuilder.buildSITOFP(Ty, Src1); 6238 MIRBuilder.buildFPow(Dst, Src0, CvtSrc1, MI.getFlags()); 6239 MI.eraseFromParent(); 6240 return Legalized; 6241 } 6242 6243 static CmpInst::Predicate minMaxToCompare(unsigned Opc) { 6244 switch (Opc) { 6245 case TargetOpcode::G_SMIN: 6246 return CmpInst::ICMP_SLT; 6247 case TargetOpcode::G_SMAX: 6248 return CmpInst::ICMP_SGT; 6249 case TargetOpcode::G_UMIN: 6250 return CmpInst::ICMP_ULT; 6251 case TargetOpcode::G_UMAX: 6252 return CmpInst::ICMP_UGT; 6253 default: 6254 llvm_unreachable("not in integer min/max"); 6255 } 6256 } 6257 6258 LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) { 6259 Register Dst = MI.getOperand(0).getReg(); 6260 Register Src0 = MI.getOperand(1).getReg(); 6261 Register Src1 = MI.getOperand(2).getReg(); 6262 6263 const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode()); 6264 LLT CmpType = MRI.getType(Dst).changeElementSize(1); 6265 6266 auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1); 6267 MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1); 6268 6269 MI.eraseFromParent(); 6270 return Legalized; 6271 } 6272 6273 LegalizerHelper::LegalizeResult 6274 LegalizerHelper::lowerFCopySign(MachineInstr &MI) { 6275 Register Dst = MI.getOperand(0).getReg(); 6276 Register Src0 = MI.getOperand(1).getReg(); 6277 Register Src1 = MI.getOperand(2).getReg(); 6278 6279 const LLT Src0Ty = MRI.getType(Src0); 6280 const LLT Src1Ty = MRI.getType(Src1); 6281 6282 const int Src0Size = Src0Ty.getScalarSizeInBits(); 6283 const int Src1Size = Src1Ty.getScalarSizeInBits(); 6284 6285 auto SignBitMask = MIRBuilder.buildConstant( 6286 Src0Ty, APInt::getSignMask(Src0Size)); 6287 6288 auto NotSignBitMask = MIRBuilder.buildConstant( 6289 Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1)); 6290 6291 Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask).getReg(0); 6292 Register And1; 6293 if (Src0Ty == Src1Ty) { 6294 And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask).getReg(0); 6295 } else if (Src0Size > Src1Size) { 6296 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size); 6297 auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1); 6298 auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt); 6299 And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0); 6300 } else { 6301 auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size); 6302 auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt); 6303 auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift); 6304 And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask).getReg(0); 6305 } 6306 6307 // Be careful about setting nsz/nnan/ninf on every instruction, since the 6308 // constants are a nan and -0.0, but the final result should preserve 6309 // everything. 6310 unsigned Flags = MI.getFlags(); 6311 MIRBuilder.buildOr(Dst, And0, And1, Flags); 6312 6313 MI.eraseFromParent(); 6314 return Legalized; 6315 } 6316 6317 LegalizerHelper::LegalizeResult 6318 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) { 6319 unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ? 6320 TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE; 6321 6322 Register Dst = MI.getOperand(0).getReg(); 6323 Register Src0 = MI.getOperand(1).getReg(); 6324 Register Src1 = MI.getOperand(2).getReg(); 6325 LLT Ty = MRI.getType(Dst); 6326 6327 if (!MI.getFlag(MachineInstr::FmNoNans)) { 6328 // Insert canonicalizes if it's possible we need to quiet to get correct 6329 // sNaN behavior. 6330 6331 // Note this must be done here, and not as an optimization combine in the 6332 // absence of a dedicate quiet-snan instruction as we're using an 6333 // omni-purpose G_FCANONICALIZE. 6334 if (!isKnownNeverSNaN(Src0, MRI)) 6335 Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0); 6336 6337 if (!isKnownNeverSNaN(Src1, MRI)) 6338 Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0); 6339 } 6340 6341 // If there are no nans, it's safe to simply replace this with the non-IEEE 6342 // version. 6343 MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags()); 6344 MI.eraseFromParent(); 6345 return Legalized; 6346 } 6347 6348 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) { 6349 // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c 6350 Register DstReg = MI.getOperand(0).getReg(); 6351 LLT Ty = MRI.getType(DstReg); 6352 unsigned Flags = MI.getFlags(); 6353 6354 auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2), 6355 Flags); 6356 MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags); 6357 MI.eraseFromParent(); 6358 return Legalized; 6359 } 6360 6361 LegalizerHelper::LegalizeResult 6362 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) { 6363 Register DstReg = MI.getOperand(0).getReg(); 6364 Register X = MI.getOperand(1).getReg(); 6365 const unsigned Flags = MI.getFlags(); 6366 const LLT Ty = MRI.getType(DstReg); 6367 const LLT CondTy = Ty.changeElementSize(1); 6368 6369 // round(x) => 6370 // t = trunc(x); 6371 // d = fabs(x - t); 6372 // o = copysign(1.0f, x); 6373 // return t + (d >= 0.5 ? o : 0.0); 6374 6375 auto T = MIRBuilder.buildIntrinsicTrunc(Ty, X, Flags); 6376 6377 auto Diff = MIRBuilder.buildFSub(Ty, X, T, Flags); 6378 auto AbsDiff = MIRBuilder.buildFAbs(Ty, Diff, Flags); 6379 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 6380 auto One = MIRBuilder.buildFConstant(Ty, 1.0); 6381 auto Half = MIRBuilder.buildFConstant(Ty, 0.5); 6382 auto SignOne = MIRBuilder.buildFCopysign(Ty, One, X); 6383 6384 auto Cmp = MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half, 6385 Flags); 6386 auto Sel = MIRBuilder.buildSelect(Ty, Cmp, SignOne, Zero, Flags); 6387 6388 MIRBuilder.buildFAdd(DstReg, T, Sel, Flags); 6389 6390 MI.eraseFromParent(); 6391 return Legalized; 6392 } 6393 6394 LegalizerHelper::LegalizeResult 6395 LegalizerHelper::lowerFFloor(MachineInstr &MI) { 6396 Register DstReg = MI.getOperand(0).getReg(); 6397 Register SrcReg = MI.getOperand(1).getReg(); 6398 unsigned Flags = MI.getFlags(); 6399 LLT Ty = MRI.getType(DstReg); 6400 const LLT CondTy = Ty.changeElementSize(1); 6401 6402 // result = trunc(src); 6403 // if (src < 0.0 && src != result) 6404 // result += -1.0. 6405 6406 auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags); 6407 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 6408 6409 auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy, 6410 SrcReg, Zero, Flags); 6411 auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy, 6412 SrcReg, Trunc, Flags); 6413 auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc); 6414 auto AddVal = MIRBuilder.buildSITOFP(Ty, And); 6415 6416 MIRBuilder.buildFAdd(DstReg, Trunc, AddVal, Flags); 6417 MI.eraseFromParent(); 6418 return Legalized; 6419 } 6420 6421 LegalizerHelper::LegalizeResult 6422 LegalizerHelper::lowerMergeValues(MachineInstr &MI) { 6423 const unsigned NumOps = MI.getNumOperands(); 6424 Register DstReg = MI.getOperand(0).getReg(); 6425 Register Src0Reg = MI.getOperand(1).getReg(); 6426 LLT DstTy = MRI.getType(DstReg); 6427 LLT SrcTy = MRI.getType(Src0Reg); 6428 unsigned PartSize = SrcTy.getSizeInBits(); 6429 6430 LLT WideTy = LLT::scalar(DstTy.getSizeInBits()); 6431 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); 6432 6433 for (unsigned I = 2; I != NumOps; ++I) { 6434 const unsigned Offset = (I - 1) * PartSize; 6435 6436 Register SrcReg = MI.getOperand(I).getReg(); 6437 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 6438 6439 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 6440 MRI.createGenericVirtualRegister(WideTy); 6441 6442 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 6443 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 6444 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 6445 ResultReg = NextResult; 6446 } 6447 6448 if (DstTy.isPointer()) { 6449 if (MIRBuilder.getDataLayout().isNonIntegralAddressSpace( 6450 DstTy.getAddressSpace())) { 6451 LLVM_DEBUG(dbgs() << "Not casting nonintegral address space\n"); 6452 return UnableToLegalize; 6453 } 6454 6455 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 6456 } 6457 6458 MI.eraseFromParent(); 6459 return Legalized; 6460 } 6461 6462 LegalizerHelper::LegalizeResult 6463 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) { 6464 const unsigned NumDst = MI.getNumOperands() - 1; 6465 Register SrcReg = MI.getOperand(NumDst).getReg(); 6466 Register Dst0Reg = MI.getOperand(0).getReg(); 6467 LLT DstTy = MRI.getType(Dst0Reg); 6468 if (DstTy.isPointer()) 6469 return UnableToLegalize; // TODO 6470 6471 SrcReg = coerceToScalar(SrcReg); 6472 if (!SrcReg) 6473 return UnableToLegalize; 6474 6475 // Expand scalarizing unmerge as bitcast to integer and shift. 6476 LLT IntTy = MRI.getType(SrcReg); 6477 6478 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 6479 6480 const unsigned DstSize = DstTy.getSizeInBits(); 6481 unsigned Offset = DstSize; 6482 for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) { 6483 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset); 6484 auto Shift = MIRBuilder.buildLShr(IntTy, SrcReg, ShiftAmt); 6485 MIRBuilder.buildTrunc(MI.getOperand(I), Shift); 6486 } 6487 6488 MI.eraseFromParent(); 6489 return Legalized; 6490 } 6491 6492 /// Lower a vector extract or insert by writing the vector to a stack temporary 6493 /// and reloading the element or vector. 6494 /// 6495 /// %dst = G_EXTRACT_VECTOR_ELT %vec, %idx 6496 /// => 6497 /// %stack_temp = G_FRAME_INDEX 6498 /// G_STORE %vec, %stack_temp 6499 /// %idx = clamp(%idx, %vec.getNumElements()) 6500 /// %element_ptr = G_PTR_ADD %stack_temp, %idx 6501 /// %dst = G_LOAD %element_ptr 6502 LegalizerHelper::LegalizeResult 6503 LegalizerHelper::lowerExtractInsertVectorElt(MachineInstr &MI) { 6504 Register DstReg = MI.getOperand(0).getReg(); 6505 Register SrcVec = MI.getOperand(1).getReg(); 6506 Register InsertVal; 6507 if (MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT) 6508 InsertVal = MI.getOperand(2).getReg(); 6509 6510 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 6511 6512 LLT VecTy = MRI.getType(SrcVec); 6513 LLT EltTy = VecTy.getElementType(); 6514 if (!EltTy.isByteSized()) { // Not implemented. 6515 LLVM_DEBUG(dbgs() << "Can't handle non-byte element vectors yet\n"); 6516 return UnableToLegalize; 6517 } 6518 6519 unsigned EltBytes = EltTy.getSizeInBytes(); 6520 Align VecAlign = getStackTemporaryAlignment(VecTy); 6521 Align EltAlign; 6522 6523 MachinePointerInfo PtrInfo; 6524 auto StackTemp = createStackTemporary(TypeSize::Fixed(VecTy.getSizeInBytes()), 6525 VecAlign, PtrInfo); 6526 MIRBuilder.buildStore(SrcVec, StackTemp, PtrInfo, VecAlign); 6527 6528 // Get the pointer to the element, and be sure not to hit undefined behavior 6529 // if the index is out of bounds. 6530 Register EltPtr = getVectorElementPointer(StackTemp.getReg(0), VecTy, Idx); 6531 6532 int64_t IdxVal; 6533 if (mi_match(Idx, MRI, m_ICst(IdxVal))) { 6534 int64_t Offset = IdxVal * EltBytes; 6535 PtrInfo = PtrInfo.getWithOffset(Offset); 6536 EltAlign = commonAlignment(VecAlign, Offset); 6537 } else { 6538 // We lose information with a variable offset. 6539 EltAlign = getStackTemporaryAlignment(EltTy); 6540 PtrInfo = MachinePointerInfo(MRI.getType(EltPtr).getAddressSpace()); 6541 } 6542 6543 if (InsertVal) { 6544 // Write the inserted element 6545 MIRBuilder.buildStore(InsertVal, EltPtr, PtrInfo, EltAlign); 6546 6547 // Reload the whole vector. 6548 MIRBuilder.buildLoad(DstReg, StackTemp, PtrInfo, VecAlign); 6549 } else { 6550 MIRBuilder.buildLoad(DstReg, EltPtr, PtrInfo, EltAlign); 6551 } 6552 6553 MI.eraseFromParent(); 6554 return Legalized; 6555 } 6556 6557 LegalizerHelper::LegalizeResult 6558 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) { 6559 Register DstReg = MI.getOperand(0).getReg(); 6560 Register Src0Reg = MI.getOperand(1).getReg(); 6561 Register Src1Reg = MI.getOperand(2).getReg(); 6562 LLT Src0Ty = MRI.getType(Src0Reg); 6563 LLT DstTy = MRI.getType(DstReg); 6564 LLT IdxTy = LLT::scalar(32); 6565 6566 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 6567 6568 if (DstTy.isScalar()) { 6569 if (Src0Ty.isVector()) 6570 return UnableToLegalize; 6571 6572 // This is just a SELECT. 6573 assert(Mask.size() == 1 && "Expected a single mask element"); 6574 Register Val; 6575 if (Mask[0] < 0 || Mask[0] > 1) 6576 Val = MIRBuilder.buildUndef(DstTy).getReg(0); 6577 else 6578 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; 6579 MIRBuilder.buildCopy(DstReg, Val); 6580 MI.eraseFromParent(); 6581 return Legalized; 6582 } 6583 6584 Register Undef; 6585 SmallVector<Register, 32> BuildVec; 6586 LLT EltTy = DstTy.getElementType(); 6587 6588 for (int Idx : Mask) { 6589 if (Idx < 0) { 6590 if (!Undef.isValid()) 6591 Undef = MIRBuilder.buildUndef(EltTy).getReg(0); 6592 BuildVec.push_back(Undef); 6593 continue; 6594 } 6595 6596 if (Src0Ty.isScalar()) { 6597 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); 6598 } else { 6599 int NumElts = Src0Ty.getNumElements(); 6600 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; 6601 int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts; 6602 auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx); 6603 auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK); 6604 BuildVec.push_back(Extract.getReg(0)); 6605 } 6606 } 6607 6608 MIRBuilder.buildBuildVector(DstReg, BuildVec); 6609 MI.eraseFromParent(); 6610 return Legalized; 6611 } 6612 6613 LegalizerHelper::LegalizeResult 6614 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) { 6615 const auto &MF = *MI.getMF(); 6616 const auto &TFI = *MF.getSubtarget().getFrameLowering(); 6617 if (TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp) 6618 return UnableToLegalize; 6619 6620 Register Dst = MI.getOperand(0).getReg(); 6621 Register AllocSize = MI.getOperand(1).getReg(); 6622 Align Alignment = assumeAligned(MI.getOperand(2).getImm()); 6623 6624 LLT PtrTy = MRI.getType(Dst); 6625 LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits()); 6626 6627 Register SPReg = TLI.getStackPointerRegisterToSaveRestore(); 6628 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); 6629 SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp); 6630 6631 // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't 6632 // have to generate an extra instruction to negate the alloc and then use 6633 // G_PTR_ADD to add the negative offset. 6634 auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize); 6635 if (Alignment > Align(1)) { 6636 APInt AlignMask(IntPtrTy.getSizeInBits(), Alignment.value(), true); 6637 AlignMask.negate(); 6638 auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask); 6639 Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst); 6640 } 6641 6642 SPTmp = MIRBuilder.buildCast(PtrTy, Alloc); 6643 MIRBuilder.buildCopy(SPReg, SPTmp); 6644 MIRBuilder.buildCopy(Dst, SPTmp); 6645 6646 MI.eraseFromParent(); 6647 return Legalized; 6648 } 6649 6650 LegalizerHelper::LegalizeResult 6651 LegalizerHelper::lowerExtract(MachineInstr &MI) { 6652 Register Dst = MI.getOperand(0).getReg(); 6653 Register Src = MI.getOperand(1).getReg(); 6654 unsigned Offset = MI.getOperand(2).getImm(); 6655 6656 LLT DstTy = MRI.getType(Dst); 6657 LLT SrcTy = MRI.getType(Src); 6658 6659 if (DstTy.isScalar() && 6660 (SrcTy.isScalar() || 6661 (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) { 6662 LLT SrcIntTy = SrcTy; 6663 if (!SrcTy.isScalar()) { 6664 SrcIntTy = LLT::scalar(SrcTy.getSizeInBits()); 6665 Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0); 6666 } 6667 6668 if (Offset == 0) 6669 MIRBuilder.buildTrunc(Dst, Src); 6670 else { 6671 auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset); 6672 auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt); 6673 MIRBuilder.buildTrunc(Dst, Shr); 6674 } 6675 6676 MI.eraseFromParent(); 6677 return Legalized; 6678 } 6679 6680 return UnableToLegalize; 6681 } 6682 6683 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) { 6684 Register Dst = MI.getOperand(0).getReg(); 6685 Register Src = MI.getOperand(1).getReg(); 6686 Register InsertSrc = MI.getOperand(2).getReg(); 6687 uint64_t Offset = MI.getOperand(3).getImm(); 6688 6689 LLT DstTy = MRI.getType(Src); 6690 LLT InsertTy = MRI.getType(InsertSrc); 6691 6692 if (InsertTy.isVector() || 6693 (DstTy.isVector() && DstTy.getElementType() != InsertTy)) 6694 return UnableToLegalize; 6695 6696 const DataLayout &DL = MIRBuilder.getDataLayout(); 6697 if ((DstTy.isPointer() && 6698 DL.isNonIntegralAddressSpace(DstTy.getAddressSpace())) || 6699 (InsertTy.isPointer() && 6700 DL.isNonIntegralAddressSpace(InsertTy.getAddressSpace()))) { 6701 LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n"); 6702 return UnableToLegalize; 6703 } 6704 6705 LLT IntDstTy = DstTy; 6706 6707 if (!DstTy.isScalar()) { 6708 IntDstTy = LLT::scalar(DstTy.getSizeInBits()); 6709 Src = MIRBuilder.buildCast(IntDstTy, Src).getReg(0); 6710 } 6711 6712 if (!InsertTy.isScalar()) { 6713 const LLT IntInsertTy = LLT::scalar(InsertTy.getSizeInBits()); 6714 InsertSrc = MIRBuilder.buildPtrToInt(IntInsertTy, InsertSrc).getReg(0); 6715 } 6716 6717 Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0); 6718 if (Offset != 0) { 6719 auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset); 6720 ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0); 6721 } 6722 6723 APInt MaskVal = APInt::getBitsSetWithWrap( 6724 DstTy.getSizeInBits(), Offset + InsertTy.getSizeInBits(), Offset); 6725 6726 auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal); 6727 auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask); 6728 auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc); 6729 6730 MIRBuilder.buildCast(Dst, Or); 6731 MI.eraseFromParent(); 6732 return Legalized; 6733 } 6734 6735 LegalizerHelper::LegalizeResult 6736 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) { 6737 Register Dst0 = MI.getOperand(0).getReg(); 6738 Register Dst1 = MI.getOperand(1).getReg(); 6739 Register LHS = MI.getOperand(2).getReg(); 6740 Register RHS = MI.getOperand(3).getReg(); 6741 const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO; 6742 6743 LLT Ty = MRI.getType(Dst0); 6744 LLT BoolTy = MRI.getType(Dst1); 6745 6746 if (IsAdd) 6747 MIRBuilder.buildAdd(Dst0, LHS, RHS); 6748 else 6749 MIRBuilder.buildSub(Dst0, LHS, RHS); 6750 6751 // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow. 6752 6753 auto Zero = MIRBuilder.buildConstant(Ty, 0); 6754 6755 // For an addition, the result should be less than one of the operands (LHS) 6756 // if and only if the other operand (RHS) is negative, otherwise there will 6757 // be overflow. 6758 // For a subtraction, the result should be less than one of the operands 6759 // (LHS) if and only if the other operand (RHS) is (non-zero) positive, 6760 // otherwise there will be overflow. 6761 auto ResultLowerThanLHS = 6762 MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS); 6763 auto ConditionRHS = MIRBuilder.buildICmp( 6764 IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero); 6765 6766 MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS); 6767 MI.eraseFromParent(); 6768 return Legalized; 6769 } 6770 6771 LegalizerHelper::LegalizeResult 6772 LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI) { 6773 Register Res = MI.getOperand(0).getReg(); 6774 Register LHS = MI.getOperand(1).getReg(); 6775 Register RHS = MI.getOperand(2).getReg(); 6776 LLT Ty = MRI.getType(Res); 6777 bool IsSigned; 6778 bool IsAdd; 6779 unsigned BaseOp; 6780 switch (MI.getOpcode()) { 6781 default: 6782 llvm_unreachable("unexpected addsat/subsat opcode"); 6783 case TargetOpcode::G_UADDSAT: 6784 IsSigned = false; 6785 IsAdd = true; 6786 BaseOp = TargetOpcode::G_ADD; 6787 break; 6788 case TargetOpcode::G_SADDSAT: 6789 IsSigned = true; 6790 IsAdd = true; 6791 BaseOp = TargetOpcode::G_ADD; 6792 break; 6793 case TargetOpcode::G_USUBSAT: 6794 IsSigned = false; 6795 IsAdd = false; 6796 BaseOp = TargetOpcode::G_SUB; 6797 break; 6798 case TargetOpcode::G_SSUBSAT: 6799 IsSigned = true; 6800 IsAdd = false; 6801 BaseOp = TargetOpcode::G_SUB; 6802 break; 6803 } 6804 6805 if (IsSigned) { 6806 // sadd.sat(a, b) -> 6807 // hi = 0x7fffffff - smax(a, 0) 6808 // lo = 0x80000000 - smin(a, 0) 6809 // a + smin(smax(lo, b), hi) 6810 // ssub.sat(a, b) -> 6811 // lo = smax(a, -1) - 0x7fffffff 6812 // hi = smin(a, -1) - 0x80000000 6813 // a - smin(smax(lo, b), hi) 6814 // TODO: AMDGPU can use a "median of 3" instruction here: 6815 // a +/- med3(lo, b, hi) 6816 uint64_t NumBits = Ty.getScalarSizeInBits(); 6817 auto MaxVal = 6818 MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(NumBits)); 6819 auto MinVal = 6820 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6821 MachineInstrBuilder Hi, Lo; 6822 if (IsAdd) { 6823 auto Zero = MIRBuilder.buildConstant(Ty, 0); 6824 Hi = MIRBuilder.buildSub(Ty, MaxVal, MIRBuilder.buildSMax(Ty, LHS, Zero)); 6825 Lo = MIRBuilder.buildSub(Ty, MinVal, MIRBuilder.buildSMin(Ty, LHS, Zero)); 6826 } else { 6827 auto NegOne = MIRBuilder.buildConstant(Ty, -1); 6828 Lo = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMax(Ty, LHS, NegOne), 6829 MaxVal); 6830 Hi = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMin(Ty, LHS, NegOne), 6831 MinVal); 6832 } 6833 auto RHSClamped = 6834 MIRBuilder.buildSMin(Ty, MIRBuilder.buildSMax(Ty, Lo, RHS), Hi); 6835 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped}); 6836 } else { 6837 // uadd.sat(a, b) -> a + umin(~a, b) 6838 // usub.sat(a, b) -> a - umin(a, b) 6839 Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS; 6840 auto Min = MIRBuilder.buildUMin(Ty, Not, RHS); 6841 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min}); 6842 } 6843 6844 MI.eraseFromParent(); 6845 return Legalized; 6846 } 6847 6848 LegalizerHelper::LegalizeResult 6849 LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) { 6850 Register Res = MI.getOperand(0).getReg(); 6851 Register LHS = MI.getOperand(1).getReg(); 6852 Register RHS = MI.getOperand(2).getReg(); 6853 LLT Ty = MRI.getType(Res); 6854 LLT BoolTy = Ty.changeElementSize(1); 6855 bool IsSigned; 6856 bool IsAdd; 6857 unsigned OverflowOp; 6858 switch (MI.getOpcode()) { 6859 default: 6860 llvm_unreachable("unexpected addsat/subsat opcode"); 6861 case TargetOpcode::G_UADDSAT: 6862 IsSigned = false; 6863 IsAdd = true; 6864 OverflowOp = TargetOpcode::G_UADDO; 6865 break; 6866 case TargetOpcode::G_SADDSAT: 6867 IsSigned = true; 6868 IsAdd = true; 6869 OverflowOp = TargetOpcode::G_SADDO; 6870 break; 6871 case TargetOpcode::G_USUBSAT: 6872 IsSigned = false; 6873 IsAdd = false; 6874 OverflowOp = TargetOpcode::G_USUBO; 6875 break; 6876 case TargetOpcode::G_SSUBSAT: 6877 IsSigned = true; 6878 IsAdd = false; 6879 OverflowOp = TargetOpcode::G_SSUBO; 6880 break; 6881 } 6882 6883 auto OverflowRes = 6884 MIRBuilder.buildInstr(OverflowOp, {Ty, BoolTy}, {LHS, RHS}); 6885 Register Tmp = OverflowRes.getReg(0); 6886 Register Ov = OverflowRes.getReg(1); 6887 MachineInstrBuilder Clamp; 6888 if (IsSigned) { 6889 // sadd.sat(a, b) -> 6890 // {tmp, ov} = saddo(a, b) 6891 // ov ? (tmp >>s 31) + 0x80000000 : r 6892 // ssub.sat(a, b) -> 6893 // {tmp, ov} = ssubo(a, b) 6894 // ov ? (tmp >>s 31) + 0x80000000 : r 6895 uint64_t NumBits = Ty.getScalarSizeInBits(); 6896 auto ShiftAmount = MIRBuilder.buildConstant(Ty, NumBits - 1); 6897 auto Sign = MIRBuilder.buildAShr(Ty, Tmp, ShiftAmount); 6898 auto MinVal = 6899 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6900 Clamp = MIRBuilder.buildAdd(Ty, Sign, MinVal); 6901 } else { 6902 // uadd.sat(a, b) -> 6903 // {tmp, ov} = uaddo(a, b) 6904 // ov ? 0xffffffff : tmp 6905 // usub.sat(a, b) -> 6906 // {tmp, ov} = usubo(a, b) 6907 // ov ? 0 : tmp 6908 Clamp = MIRBuilder.buildConstant(Ty, IsAdd ? -1 : 0); 6909 } 6910 MIRBuilder.buildSelect(Res, Ov, Clamp, Tmp); 6911 6912 MI.eraseFromParent(); 6913 return Legalized; 6914 } 6915 6916 LegalizerHelper::LegalizeResult 6917 LegalizerHelper::lowerShlSat(MachineInstr &MI) { 6918 assert((MI.getOpcode() == TargetOpcode::G_SSHLSAT || 6919 MI.getOpcode() == TargetOpcode::G_USHLSAT) && 6920 "Expected shlsat opcode!"); 6921 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SSHLSAT; 6922 Register Res = MI.getOperand(0).getReg(); 6923 Register LHS = MI.getOperand(1).getReg(); 6924 Register RHS = MI.getOperand(2).getReg(); 6925 LLT Ty = MRI.getType(Res); 6926 LLT BoolTy = Ty.changeElementSize(1); 6927 6928 unsigned BW = Ty.getScalarSizeInBits(); 6929 auto Result = MIRBuilder.buildShl(Ty, LHS, RHS); 6930 auto Orig = IsSigned ? MIRBuilder.buildAShr(Ty, Result, RHS) 6931 : MIRBuilder.buildLShr(Ty, Result, RHS); 6932 6933 MachineInstrBuilder SatVal; 6934 if (IsSigned) { 6935 auto SatMin = MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(BW)); 6936 auto SatMax = MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(BW)); 6937 auto Cmp = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, LHS, 6938 MIRBuilder.buildConstant(Ty, 0)); 6939 SatVal = MIRBuilder.buildSelect(Ty, Cmp, SatMin, SatMax); 6940 } else { 6941 SatVal = MIRBuilder.buildConstant(Ty, APInt::getMaxValue(BW)); 6942 } 6943 auto Ov = MIRBuilder.buildICmp(CmpInst::ICMP_NE, BoolTy, LHS, Orig); 6944 MIRBuilder.buildSelect(Res, Ov, SatVal, Result); 6945 6946 MI.eraseFromParent(); 6947 return Legalized; 6948 } 6949 6950 LegalizerHelper::LegalizeResult 6951 LegalizerHelper::lowerBswap(MachineInstr &MI) { 6952 Register Dst = MI.getOperand(0).getReg(); 6953 Register Src = MI.getOperand(1).getReg(); 6954 const LLT Ty = MRI.getType(Src); 6955 unsigned SizeInBytes = (Ty.getScalarSizeInBits() + 7) / 8; 6956 unsigned BaseShiftAmt = (SizeInBytes - 1) * 8; 6957 6958 // Swap most and least significant byte, set remaining bytes in Res to zero. 6959 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt); 6960 auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt); 6961 auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 6962 auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft); 6963 6964 // Set i-th high/low byte in Res to i-th low/high byte from Src. 6965 for (unsigned i = 1; i < SizeInBytes / 2; ++i) { 6966 // AND with Mask leaves byte i unchanged and sets remaining bytes to 0. 6967 APInt APMask(SizeInBytes * 8, 0xFF << (i * 8)); 6968 auto Mask = MIRBuilder.buildConstant(Ty, APMask); 6969 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i); 6970 // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt. 6971 auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask); 6972 auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt); 6973 Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft); 6974 // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask. 6975 auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 6976 auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask); 6977 Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight); 6978 } 6979 Res.getInstr()->getOperand(0).setReg(Dst); 6980 6981 MI.eraseFromParent(); 6982 return Legalized; 6983 } 6984 6985 //{ (Src & Mask) >> N } | { (Src << N) & Mask } 6986 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B, 6987 MachineInstrBuilder Src, APInt Mask) { 6988 const LLT Ty = Dst.getLLTTy(*B.getMRI()); 6989 MachineInstrBuilder C_N = B.buildConstant(Ty, N); 6990 MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask); 6991 auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N); 6992 auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0); 6993 return B.buildOr(Dst, LHS, RHS); 6994 } 6995 6996 LegalizerHelper::LegalizeResult 6997 LegalizerHelper::lowerBitreverse(MachineInstr &MI) { 6998 Register Dst = MI.getOperand(0).getReg(); 6999 Register Src = MI.getOperand(1).getReg(); 7000 const LLT Ty = MRI.getType(Src); 7001 unsigned Size = Ty.getSizeInBits(); 7002 7003 MachineInstrBuilder BSWAP = 7004 MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src}); 7005 7006 // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654 7007 // [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4] 7008 // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0] 7009 MachineInstrBuilder Swap4 = 7010 SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0))); 7011 7012 // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76 7013 // [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2] 7014 // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC] 7015 MachineInstrBuilder Swap2 = 7016 SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC))); 7017 7018 // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7 7019 // [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1] 7020 // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA] 7021 SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA))); 7022 7023 MI.eraseFromParent(); 7024 return Legalized; 7025 } 7026 7027 LegalizerHelper::LegalizeResult 7028 LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) { 7029 MachineFunction &MF = MIRBuilder.getMF(); 7030 7031 bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER; 7032 int NameOpIdx = IsRead ? 1 : 0; 7033 int ValRegIndex = IsRead ? 0 : 1; 7034 7035 Register ValReg = MI.getOperand(ValRegIndex).getReg(); 7036 const LLT Ty = MRI.getType(ValReg); 7037 const MDString *RegStr = cast<MDString>( 7038 cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0)); 7039 7040 Register PhysReg = TLI.getRegisterByName(RegStr->getString().data(), Ty, MF); 7041 if (!PhysReg.isValid()) 7042 return UnableToLegalize; 7043 7044 if (IsRead) 7045 MIRBuilder.buildCopy(ValReg, PhysReg); 7046 else 7047 MIRBuilder.buildCopy(PhysReg, ValReg); 7048 7049 MI.eraseFromParent(); 7050 return Legalized; 7051 } 7052 7053 LegalizerHelper::LegalizeResult 7054 LegalizerHelper::lowerSMULH_UMULH(MachineInstr &MI) { 7055 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULH; 7056 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 7057 Register Result = MI.getOperand(0).getReg(); 7058 LLT OrigTy = MRI.getType(Result); 7059 auto SizeInBits = OrigTy.getScalarSizeInBits(); 7060 LLT WideTy = OrigTy.changeElementSize(SizeInBits * 2); 7061 7062 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)}); 7063 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)}); 7064 auto Mul = MIRBuilder.buildMul(WideTy, LHS, RHS); 7065 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; 7066 7067 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, SizeInBits); 7068 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); 7069 MIRBuilder.buildTrunc(Result, Shifted); 7070 7071 MI.eraseFromParent(); 7072 return Legalized; 7073 } 7074 7075 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) { 7076 // Implement vector G_SELECT in terms of XOR, AND, OR. 7077 Register DstReg = MI.getOperand(0).getReg(); 7078 Register MaskReg = MI.getOperand(1).getReg(); 7079 Register Op1Reg = MI.getOperand(2).getReg(); 7080 Register Op2Reg = MI.getOperand(3).getReg(); 7081 LLT DstTy = MRI.getType(DstReg); 7082 LLT MaskTy = MRI.getType(MaskReg); 7083 LLT Op1Ty = MRI.getType(Op1Reg); 7084 if (!DstTy.isVector()) 7085 return UnableToLegalize; 7086 7087 // Vector selects can have a scalar predicate. If so, splat into a vector and 7088 // finish for later legalization attempts to try again. 7089 if (MaskTy.isScalar()) { 7090 Register MaskElt = MaskReg; 7091 if (MaskTy.getSizeInBits() < DstTy.getScalarSizeInBits()) 7092 MaskElt = MIRBuilder.buildSExt(DstTy.getElementType(), MaskElt).getReg(0); 7093 // Generate a vector splat idiom to be pattern matched later. 7094 auto ShufSplat = MIRBuilder.buildShuffleSplat(DstTy, MaskElt); 7095 Observer.changingInstr(MI); 7096 MI.getOperand(1).setReg(ShufSplat.getReg(0)); 7097 Observer.changedInstr(MI); 7098 return Legalized; 7099 } 7100 7101 if (MaskTy.getSizeInBits() != Op1Ty.getSizeInBits()) { 7102 return UnableToLegalize; 7103 } 7104 7105 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); 7106 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); 7107 auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask); 7108 MIRBuilder.buildOr(DstReg, NewOp1, NewOp2); 7109 MI.eraseFromParent(); 7110 return Legalized; 7111 } 7112 7113 LegalizerHelper::LegalizeResult LegalizerHelper::lowerDIVREM(MachineInstr &MI) { 7114 // Split DIVREM into individual instructions. 7115 unsigned Opcode = MI.getOpcode(); 7116 7117 MIRBuilder.buildInstr( 7118 Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SDIV 7119 : TargetOpcode::G_UDIV, 7120 {MI.getOperand(0).getReg()}, {MI.getOperand(2), MI.getOperand(3)}); 7121 MIRBuilder.buildInstr( 7122 Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SREM 7123 : TargetOpcode::G_UREM, 7124 {MI.getOperand(1).getReg()}, {MI.getOperand(2), MI.getOperand(3)}); 7125 MI.eraseFromParent(); 7126 return Legalized; 7127 } 7128 7129 LegalizerHelper::LegalizeResult 7130 LegalizerHelper::lowerAbsToAddXor(MachineInstr &MI) { 7131 // Expand %res = G_ABS %a into: 7132 // %v1 = G_ASHR %a, scalar_size-1 7133 // %v2 = G_ADD %a, %v1 7134 // %res = G_XOR %v2, %v1 7135 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 7136 Register OpReg = MI.getOperand(1).getReg(); 7137 auto ShiftAmt = 7138 MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - 1); 7139 auto Shift = MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt); 7140 auto Add = MIRBuilder.buildAdd(DstTy, OpReg, Shift); 7141 MIRBuilder.buildXor(MI.getOperand(0).getReg(), Add, Shift); 7142 MI.eraseFromParent(); 7143 return Legalized; 7144 } 7145 7146 LegalizerHelper::LegalizeResult 7147 LegalizerHelper::lowerAbsToMaxNeg(MachineInstr &MI) { 7148 // Expand %res = G_ABS %a into: 7149 // %v1 = G_CONSTANT 0 7150 // %v2 = G_SUB %v1, %a 7151 // %res = G_SMAX %a, %v2 7152 Register SrcReg = MI.getOperand(1).getReg(); 7153 LLT Ty = MRI.getType(SrcReg); 7154 auto Zero = MIRBuilder.buildConstant(Ty, 0).getReg(0); 7155 auto Sub = MIRBuilder.buildSub(Ty, Zero, SrcReg).getReg(0); 7156 MIRBuilder.buildSMax(MI.getOperand(0), SrcReg, Sub); 7157 MI.eraseFromParent(); 7158 return Legalized; 7159 } 7160