1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetInstrInfo.h"
21 #include "llvm/CodeGen/TargetLowering.h"
22 #include "llvm/CodeGen/TargetSubtargetInfo.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Support/raw_ostream.h"
26 
27 #define DEBUG_TYPE "legalizer"
28 
29 using namespace llvm;
30 using namespace LegalizeActions;
31 
32 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
33 ///
34 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
35 /// with any leftover piece as type \p LeftoverTy
36 ///
37 /// Returns -1 in the first element of the pair if the breakdown is not
38 /// satisfiable.
39 static std::pair<int, int>
40 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
41   assert(!LeftoverTy.isValid() && "this is an out argument");
42 
43   unsigned Size = OrigTy.getSizeInBits();
44   unsigned NarrowSize = NarrowTy.getSizeInBits();
45   unsigned NumParts = Size / NarrowSize;
46   unsigned LeftoverSize = Size - NumParts * NarrowSize;
47   assert(Size > NarrowSize);
48 
49   if (LeftoverSize == 0)
50     return {NumParts, 0};
51 
52   if (NarrowTy.isVector()) {
53     unsigned EltSize = OrigTy.getScalarSizeInBits();
54     if (LeftoverSize % EltSize != 0)
55       return {-1, -1};
56     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
57   } else {
58     LeftoverTy = LLT::scalar(LeftoverSize);
59   }
60 
61   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
62   return std::make_pair(NumParts, NumLeftover);
63 }
64 
65 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
66                                  GISelChangeObserver &Observer,
67                                  MachineIRBuilder &Builder)
68     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
69       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
70   MIRBuilder.setMF(MF);
71   MIRBuilder.setChangeObserver(Observer);
72 }
73 
74 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
75                                  GISelChangeObserver &Observer,
76                                  MachineIRBuilder &B)
77     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
78   MIRBuilder.setMF(MF);
79   MIRBuilder.setChangeObserver(Observer);
80 }
81 LegalizerHelper::LegalizeResult
82 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
83   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
84 
85   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
86       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
87     return LI.legalizeIntrinsic(MI, MRI, MIRBuilder) ? Legalized
88                                                      : UnableToLegalize;
89   auto Step = LI.getAction(MI, MRI);
90   switch (Step.Action) {
91   case Legal:
92     LLVM_DEBUG(dbgs() << ".. Already legal\n");
93     return AlreadyLegal;
94   case Libcall:
95     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
96     return libcall(MI);
97   case NarrowScalar:
98     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
99     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
100   case WidenScalar:
101     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
102     return widenScalar(MI, Step.TypeIdx, Step.NewType);
103   case Lower:
104     LLVM_DEBUG(dbgs() << ".. Lower\n");
105     return lower(MI, Step.TypeIdx, Step.NewType);
106   case FewerElements:
107     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
108     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
109   case MoreElements:
110     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
111     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
112   case Custom:
113     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
114     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
115                                                             : UnableToLegalize;
116   default:
117     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
118     return UnableToLegalize;
119   }
120 }
121 
122 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
123                                    SmallVectorImpl<Register> &VRegs) {
124   for (int i = 0; i < NumParts; ++i)
125     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
126   MIRBuilder.buildUnmerge(VRegs, Reg);
127 }
128 
129 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
130                                    LLT MainTy, LLT &LeftoverTy,
131                                    SmallVectorImpl<Register> &VRegs,
132                                    SmallVectorImpl<Register> &LeftoverRegs) {
133   assert(!LeftoverTy.isValid() && "this is an out argument");
134 
135   unsigned RegSize = RegTy.getSizeInBits();
136   unsigned MainSize = MainTy.getSizeInBits();
137   unsigned NumParts = RegSize / MainSize;
138   unsigned LeftoverSize = RegSize - NumParts * MainSize;
139 
140   // Use an unmerge when possible.
141   if (LeftoverSize == 0) {
142     for (unsigned I = 0; I < NumParts; ++I)
143       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
144     MIRBuilder.buildUnmerge(VRegs, Reg);
145     return true;
146   }
147 
148   if (MainTy.isVector()) {
149     unsigned EltSize = MainTy.getScalarSizeInBits();
150     if (LeftoverSize % EltSize != 0)
151       return false;
152     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
153   } else {
154     LeftoverTy = LLT::scalar(LeftoverSize);
155   }
156 
157   // For irregular sizes, extract the individual parts.
158   for (unsigned I = 0; I != NumParts; ++I) {
159     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
160     VRegs.push_back(NewReg);
161     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
162   }
163 
164   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
165        Offset += LeftoverSize) {
166     Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
167     LeftoverRegs.push_back(NewReg);
168     MIRBuilder.buildExtract(NewReg, Reg, Offset);
169   }
170 
171   return true;
172 }
173 
174 void LegalizerHelper::insertParts(Register DstReg,
175                                   LLT ResultTy, LLT PartTy,
176                                   ArrayRef<Register> PartRegs,
177                                   LLT LeftoverTy,
178                                   ArrayRef<Register> LeftoverRegs) {
179   if (!LeftoverTy.isValid()) {
180     assert(LeftoverRegs.empty());
181 
182     if (!ResultTy.isVector()) {
183       MIRBuilder.buildMerge(DstReg, PartRegs);
184       return;
185     }
186 
187     if (PartTy.isVector())
188       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
189     else
190       MIRBuilder.buildBuildVector(DstReg, PartRegs);
191     return;
192   }
193 
194   unsigned PartSize = PartTy.getSizeInBits();
195   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
196 
197   Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
198   MIRBuilder.buildUndef(CurResultReg);
199 
200   unsigned Offset = 0;
201   for (Register PartReg : PartRegs) {
202     Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
203     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
204     CurResultReg = NewResultReg;
205     Offset += PartSize;
206   }
207 
208   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
209     // Use the original output register for the final insert to avoid a copy.
210     Register NewResultReg = (I + 1 == E) ?
211       DstReg : MRI.createGenericVirtualRegister(ResultTy);
212 
213     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
214     CurResultReg = NewResultReg;
215     Offset += LeftoverPartSize;
216   }
217 }
218 
219 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
220   switch (Opcode) {
221   case TargetOpcode::G_SDIV:
222     assert((Size == 32 || Size == 64) && "Unsupported size");
223     return Size == 64 ? RTLIB::SDIV_I64 : RTLIB::SDIV_I32;
224   case TargetOpcode::G_UDIV:
225     assert((Size == 32 || Size == 64) && "Unsupported size");
226     return Size == 64 ? RTLIB::UDIV_I64 : RTLIB::UDIV_I32;
227   case TargetOpcode::G_SREM:
228     assert((Size == 32 || Size == 64) && "Unsupported size");
229     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
230   case TargetOpcode::G_UREM:
231     assert((Size == 32 || Size == 64) && "Unsupported size");
232     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
233   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
234     assert(Size == 32 && "Unsupported size");
235     return RTLIB::CTLZ_I32;
236   case TargetOpcode::G_FADD:
237     assert((Size == 32 || Size == 64) && "Unsupported size");
238     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
239   case TargetOpcode::G_FSUB:
240     assert((Size == 32 || Size == 64) && "Unsupported size");
241     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
242   case TargetOpcode::G_FMUL:
243     assert((Size == 32 || Size == 64) && "Unsupported size");
244     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
245   case TargetOpcode::G_FDIV:
246     assert((Size == 32 || Size == 64) && "Unsupported size");
247     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
248   case TargetOpcode::G_FEXP:
249     assert((Size == 32 || Size == 64) && "Unsupported size");
250     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
251   case TargetOpcode::G_FEXP2:
252     assert((Size == 32 || Size == 64) && "Unsupported size");
253     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
254   case TargetOpcode::G_FREM:
255     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
256   case TargetOpcode::G_FPOW:
257     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
258   case TargetOpcode::G_FMA:
259     assert((Size == 32 || Size == 64) && "Unsupported size");
260     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
261   case TargetOpcode::G_FSIN:
262     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
263     return Size == 128 ? RTLIB::SIN_F128
264                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
265   case TargetOpcode::G_FCOS:
266     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
267     return Size == 128 ? RTLIB::COS_F128
268                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
269   case TargetOpcode::G_FLOG10:
270     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
271     return Size == 128 ? RTLIB::LOG10_F128
272                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
273   case TargetOpcode::G_FLOG:
274     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
275     return Size == 128 ? RTLIB::LOG_F128
276                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
277   case TargetOpcode::G_FLOG2:
278     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
279     return Size == 128 ? RTLIB::LOG2_F128
280                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
281   case TargetOpcode::G_FCEIL:
282     assert((Size == 32 || Size == 64) && "Unsupported size");
283     return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
284   case TargetOpcode::G_FFLOOR:
285     assert((Size == 32 || Size == 64) && "Unsupported size");
286     return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
287   }
288   llvm_unreachable("Unknown libcall function");
289 }
290 
291 LegalizerHelper::LegalizeResult
292 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
293                     const CallLowering::ArgInfo &Result,
294                     ArrayRef<CallLowering::ArgInfo> Args) {
295   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
296   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
297   const char *Name = TLI.getLibcallName(Libcall);
298 
299   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
300   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
301                      MachineOperand::CreateES(Name), Result, Args))
302     return LegalizerHelper::UnableToLegalize;
303 
304   return LegalizerHelper::Legalized;
305 }
306 
307 // Useful for libcalls where all operands have the same type.
308 static LegalizerHelper::LegalizeResult
309 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
310               Type *OpType) {
311   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
312 
313   SmallVector<CallLowering::ArgInfo, 3> Args;
314   for (unsigned i = 1; i < MI.getNumOperands(); i++)
315     Args.push_back({MI.getOperand(i).getReg(), OpType});
316   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
317                        Args);
318 }
319 
320 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
321                                        Type *FromType) {
322   auto ToMVT = MVT::getVT(ToType);
323   auto FromMVT = MVT::getVT(FromType);
324 
325   switch (Opcode) {
326   case TargetOpcode::G_FPEXT:
327     return RTLIB::getFPEXT(FromMVT, ToMVT);
328   case TargetOpcode::G_FPTRUNC:
329     return RTLIB::getFPROUND(FromMVT, ToMVT);
330   case TargetOpcode::G_FPTOSI:
331     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
332   case TargetOpcode::G_FPTOUI:
333     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
334   case TargetOpcode::G_SITOFP:
335     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
336   case TargetOpcode::G_UITOFP:
337     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
338   }
339   llvm_unreachable("Unsupported libcall function");
340 }
341 
342 static LegalizerHelper::LegalizeResult
343 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
344                   Type *FromType) {
345   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
346   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
347                        {{MI.getOperand(1).getReg(), FromType}});
348 }
349 
350 LegalizerHelper::LegalizeResult
351 LegalizerHelper::libcall(MachineInstr &MI) {
352   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
353   unsigned Size = LLTy.getSizeInBits();
354   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
355 
356   MIRBuilder.setInstr(MI);
357 
358   switch (MI.getOpcode()) {
359   default:
360     return UnableToLegalize;
361   case TargetOpcode::G_SDIV:
362   case TargetOpcode::G_UDIV:
363   case TargetOpcode::G_SREM:
364   case TargetOpcode::G_UREM:
365   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
366     Type *HLTy = IntegerType::get(Ctx, Size);
367     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
368     if (Status != Legalized)
369       return Status;
370     break;
371   }
372   case TargetOpcode::G_FADD:
373   case TargetOpcode::G_FSUB:
374   case TargetOpcode::G_FMUL:
375   case TargetOpcode::G_FDIV:
376   case TargetOpcode::G_FMA:
377   case TargetOpcode::G_FPOW:
378   case TargetOpcode::G_FREM:
379   case TargetOpcode::G_FCOS:
380   case TargetOpcode::G_FSIN:
381   case TargetOpcode::G_FLOG10:
382   case TargetOpcode::G_FLOG:
383   case TargetOpcode::G_FLOG2:
384   case TargetOpcode::G_FEXP:
385   case TargetOpcode::G_FEXP2:
386   case TargetOpcode::G_FCEIL:
387   case TargetOpcode::G_FFLOOR: {
388     if (Size > 64) {
389       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
390       return UnableToLegalize;
391     }
392     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
393     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
394     if (Status != Legalized)
395       return Status;
396     break;
397   }
398   case TargetOpcode::G_FPEXT: {
399     // FIXME: Support other floating point types (half, fp128 etc)
400     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
401     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
402     if (ToSize != 64 || FromSize != 32)
403       return UnableToLegalize;
404     LegalizeResult Status = conversionLibcall(
405         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
406     if (Status != Legalized)
407       return Status;
408     break;
409   }
410   case TargetOpcode::G_FPTRUNC: {
411     // FIXME: Support other floating point types (half, fp128 etc)
412     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
413     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
414     if (ToSize != 32 || FromSize != 64)
415       return UnableToLegalize;
416     LegalizeResult Status = conversionLibcall(
417         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
418     if (Status != Legalized)
419       return Status;
420     break;
421   }
422   case TargetOpcode::G_FPTOSI:
423   case TargetOpcode::G_FPTOUI: {
424     // FIXME: Support other types
425     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
426     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
427     if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
428       return UnableToLegalize;
429     LegalizeResult Status = conversionLibcall(
430         MI, MIRBuilder,
431         ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
432         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
433     if (Status != Legalized)
434       return Status;
435     break;
436   }
437   case TargetOpcode::G_SITOFP:
438   case TargetOpcode::G_UITOFP: {
439     // FIXME: Support other types
440     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
441     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
442     if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
443       return UnableToLegalize;
444     LegalizeResult Status = conversionLibcall(
445         MI, MIRBuilder,
446         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
447         FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
448     if (Status != Legalized)
449       return Status;
450     break;
451   }
452   }
453 
454   MI.eraseFromParent();
455   return Legalized;
456 }
457 
458 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
459                                                               unsigned TypeIdx,
460                                                               LLT NarrowTy) {
461   MIRBuilder.setInstr(MI);
462 
463   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
464   uint64_t NarrowSize = NarrowTy.getSizeInBits();
465 
466   switch (MI.getOpcode()) {
467   default:
468     return UnableToLegalize;
469   case TargetOpcode::G_IMPLICIT_DEF: {
470     // FIXME: add support for when SizeOp0 isn't an exact multiple of
471     // NarrowSize.
472     if (SizeOp0 % NarrowSize != 0)
473       return UnableToLegalize;
474     int NumParts = SizeOp0 / NarrowSize;
475 
476     SmallVector<Register, 2> DstRegs;
477     for (int i = 0; i < NumParts; ++i)
478       DstRegs.push_back(
479           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
480 
481     Register DstReg = MI.getOperand(0).getReg();
482     if(MRI.getType(DstReg).isVector())
483       MIRBuilder.buildBuildVector(DstReg, DstRegs);
484     else
485       MIRBuilder.buildMerge(DstReg, DstRegs);
486     MI.eraseFromParent();
487     return Legalized;
488   }
489   case TargetOpcode::G_CONSTANT: {
490     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
491     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
492     unsigned TotalSize = Ty.getSizeInBits();
493     unsigned NarrowSize = NarrowTy.getSizeInBits();
494     int NumParts = TotalSize / NarrowSize;
495 
496     SmallVector<Register, 4> PartRegs;
497     for (int I = 0; I != NumParts; ++I) {
498       unsigned Offset = I * NarrowSize;
499       auto K = MIRBuilder.buildConstant(NarrowTy,
500                                         Val.lshr(Offset).trunc(NarrowSize));
501       PartRegs.push_back(K.getReg(0));
502     }
503 
504     LLT LeftoverTy;
505     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
506     SmallVector<Register, 1> LeftoverRegs;
507     if (LeftoverBits != 0) {
508       LeftoverTy = LLT::scalar(LeftoverBits);
509       auto K = MIRBuilder.buildConstant(
510         LeftoverTy,
511         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
512       LeftoverRegs.push_back(K.getReg(0));
513     }
514 
515     insertParts(MI.getOperand(0).getReg(),
516                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
517 
518     MI.eraseFromParent();
519     return Legalized;
520   }
521   case TargetOpcode::G_ADD: {
522     // FIXME: add support for when SizeOp0 isn't an exact multiple of
523     // NarrowSize.
524     if (SizeOp0 % NarrowSize != 0)
525       return UnableToLegalize;
526     // Expand in terms of carry-setting/consuming G_ADDE instructions.
527     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
528 
529     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
530     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
531     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
532 
533     Register CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
534     MIRBuilder.buildConstant(CarryIn, 0);
535 
536     for (int i = 0; i < NumParts; ++i) {
537       Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
538       Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
539 
540       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
541                             Src2Regs[i], CarryIn);
542 
543       DstRegs.push_back(DstReg);
544       CarryIn = CarryOut;
545     }
546     Register DstReg = MI.getOperand(0).getReg();
547     if(MRI.getType(DstReg).isVector())
548       MIRBuilder.buildBuildVector(DstReg, DstRegs);
549     else
550       MIRBuilder.buildMerge(DstReg, DstRegs);
551     MI.eraseFromParent();
552     return Legalized;
553   }
554   case TargetOpcode::G_SUB: {
555     // FIXME: add support for when SizeOp0 isn't an exact multiple of
556     // NarrowSize.
557     if (SizeOp0 % NarrowSize != 0)
558       return UnableToLegalize;
559 
560     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
561 
562     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
563     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
564     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
565 
566     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
567     Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
568     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
569                           {Src1Regs[0], Src2Regs[0]});
570     DstRegs.push_back(DstReg);
571     Register BorrowIn = BorrowOut;
572     for (int i = 1; i < NumParts; ++i) {
573       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
574       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
575 
576       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
577                             {Src1Regs[i], Src2Regs[i], BorrowIn});
578 
579       DstRegs.push_back(DstReg);
580       BorrowIn = BorrowOut;
581     }
582     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
583     MI.eraseFromParent();
584     return Legalized;
585   }
586   case TargetOpcode::G_MUL:
587   case TargetOpcode::G_UMULH:
588     return narrowScalarMul(MI, NarrowTy);
589   case TargetOpcode::G_EXTRACT:
590     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
591   case TargetOpcode::G_INSERT:
592     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
593   case TargetOpcode::G_LOAD: {
594     const auto &MMO = **MI.memoperands_begin();
595     Register DstReg = MI.getOperand(0).getReg();
596     LLT DstTy = MRI.getType(DstReg);
597     if (DstTy.isVector())
598       return UnableToLegalize;
599 
600     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
601       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
602       auto &MMO = **MI.memoperands_begin();
603       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
604       MIRBuilder.buildAnyExt(DstReg, TmpReg);
605       MI.eraseFromParent();
606       return Legalized;
607     }
608 
609     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
610   }
611   case TargetOpcode::G_ZEXTLOAD:
612   case TargetOpcode::G_SEXTLOAD: {
613     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
614     Register DstReg = MI.getOperand(0).getReg();
615     Register PtrReg = MI.getOperand(1).getReg();
616 
617     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
618     auto &MMO = **MI.memoperands_begin();
619     if (MMO.getSizeInBits() == NarrowSize) {
620       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
621     } else {
622       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
623         : TargetOpcode::G_SEXTLOAD;
624       MIRBuilder.buildInstr(ExtLoad)
625         .addDef(TmpReg)
626         .addUse(PtrReg)
627         .addMemOperand(&MMO);
628     }
629 
630     if (ZExt)
631       MIRBuilder.buildZExt(DstReg, TmpReg);
632     else
633       MIRBuilder.buildSExt(DstReg, TmpReg);
634 
635     MI.eraseFromParent();
636     return Legalized;
637   }
638   case TargetOpcode::G_STORE: {
639     const auto &MMO = **MI.memoperands_begin();
640 
641     Register SrcReg = MI.getOperand(0).getReg();
642     LLT SrcTy = MRI.getType(SrcReg);
643     if (SrcTy.isVector())
644       return UnableToLegalize;
645 
646     int NumParts = SizeOp0 / NarrowSize;
647     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
648     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
649     if (SrcTy.isVector() && LeftoverBits != 0)
650       return UnableToLegalize;
651 
652     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
653       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
654       auto &MMO = **MI.memoperands_begin();
655       MIRBuilder.buildTrunc(TmpReg, SrcReg);
656       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
657       MI.eraseFromParent();
658       return Legalized;
659     }
660 
661     return reduceLoadStoreWidth(MI, 0, NarrowTy);
662   }
663   case TargetOpcode::G_SELECT:
664     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
665   case TargetOpcode::G_AND:
666   case TargetOpcode::G_OR:
667   case TargetOpcode::G_XOR: {
668     // Legalize bitwise operation:
669     // A = BinOp<Ty> B, C
670     // into:
671     // B1, ..., BN = G_UNMERGE_VALUES B
672     // C1, ..., CN = G_UNMERGE_VALUES C
673     // A1 = BinOp<Ty/N> B1, C2
674     // ...
675     // AN = BinOp<Ty/N> BN, CN
676     // A = G_MERGE_VALUES A1, ..., AN
677     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
678   }
679   case TargetOpcode::G_SHL:
680   case TargetOpcode::G_LSHR:
681   case TargetOpcode::G_ASHR:
682     return narrowScalarShift(MI, TypeIdx, NarrowTy);
683   case TargetOpcode::G_CTLZ:
684   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
685   case TargetOpcode::G_CTTZ:
686   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
687   case TargetOpcode::G_CTPOP:
688     if (TypeIdx != 0)
689       return UnableToLegalize; // TODO
690 
691     Observer.changingInstr(MI);
692     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
693     Observer.changedInstr(MI);
694     return Legalized;
695   case TargetOpcode::G_INTTOPTR:
696     if (TypeIdx != 1)
697       return UnableToLegalize;
698 
699     Observer.changingInstr(MI);
700     narrowScalarSrc(MI, NarrowTy, 1);
701     Observer.changedInstr(MI);
702     return Legalized;
703   case TargetOpcode::G_PTRTOINT:
704     if (TypeIdx != 0)
705       return UnableToLegalize;
706 
707     Observer.changingInstr(MI);
708     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
709     Observer.changedInstr(MI);
710     return Legalized;
711   }
712 }
713 
714 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
715                                      unsigned OpIdx, unsigned ExtOpcode) {
716   MachineOperand &MO = MI.getOperand(OpIdx);
717   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
718   MO.setReg(ExtB->getOperand(0).getReg());
719 }
720 
721 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
722                                       unsigned OpIdx) {
723   MachineOperand &MO = MI.getOperand(OpIdx);
724   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
725                                     {MO.getReg()});
726   MO.setReg(ExtB->getOperand(0).getReg());
727 }
728 
729 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
730                                      unsigned OpIdx, unsigned TruncOpcode) {
731   MachineOperand &MO = MI.getOperand(OpIdx);
732   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
733   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
734   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
735   MO.setReg(DstExt);
736 }
737 
738 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
739                                       unsigned OpIdx, unsigned ExtOpcode) {
740   MachineOperand &MO = MI.getOperand(OpIdx);
741   Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
742   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
743   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
744   MO.setReg(DstTrunc);
745 }
746 
747 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
748                                             unsigned OpIdx) {
749   MachineOperand &MO = MI.getOperand(OpIdx);
750   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
751   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
752   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
753   MO.setReg(DstExt);
754 }
755 
756 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
757                                             unsigned OpIdx) {
758   MachineOperand &MO = MI.getOperand(OpIdx);
759 
760   LLT OldTy = MRI.getType(MO.getReg());
761   unsigned OldElts = OldTy.getNumElements();
762   unsigned NewElts = MoreTy.getNumElements();
763 
764   unsigned NumParts = NewElts / OldElts;
765 
766   // Use concat_vectors if the result is a multiple of the number of elements.
767   if (NumParts * OldElts == NewElts) {
768     SmallVector<Register, 8> Parts;
769     Parts.push_back(MO.getReg());
770 
771     Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
772     for (unsigned I = 1; I != NumParts; ++I)
773       Parts.push_back(ImpDef);
774 
775     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
776     MO.setReg(Concat.getReg(0));
777     return;
778   }
779 
780   Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
781   Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
782   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
783   MO.setReg(MoreReg);
784 }
785 
786 LegalizerHelper::LegalizeResult
787 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
788                                         LLT WideTy) {
789   if (TypeIdx != 1)
790     return UnableToLegalize;
791 
792   Register DstReg = MI.getOperand(0).getReg();
793   LLT DstTy = MRI.getType(DstReg);
794   if (!DstTy.isScalar())
795     return UnableToLegalize;
796 
797   Register Src1 = MI.getOperand(1).getReg();
798   LLT SrcTy = MRI.getType(Src1);
799   int NumMerge = DstTy.getSizeInBits() / WideTy.getSizeInBits();
800 
801   // Try to turn this into a merge of merges if we can use the requested type as
802   // the source.
803 
804   // TODO: Pad with undef if DstTy > WideTy
805   if (NumMerge > 1 && WideTy.getSizeInBits() % SrcTy.getSizeInBits() == 0) {
806     int PartsPerMerge = WideTy.getSizeInBits() / SrcTy.getSizeInBits();
807     SmallVector<Register, 4> Parts;
808     SmallVector<Register, 4> SubMerges;
809 
810     for (int I = 0; I != NumMerge; ++I) {
811       for (int J = 0; J != PartsPerMerge; ++J)
812         Parts.push_back(MI.getOperand(I * PartsPerMerge + J + 1).getReg());
813 
814       auto SubMerge = MIRBuilder.buildMerge(WideTy, Parts);
815       SubMerges.push_back(SubMerge.getReg(0));
816       Parts.clear();
817     }
818 
819     MIRBuilder.buildMerge(DstReg, SubMerges);
820     MI.eraseFromParent();
821     return Legalized;
822   }
823 
824   unsigned NumOps = MI.getNumOperands();
825   unsigned NumSrc = MI.getNumOperands() - 1;
826   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
827 
828   Register ResultReg = MIRBuilder.buildZExt(DstTy, Src1).getReg(0);
829 
830   for (unsigned I = 2; I != NumOps; ++I) {
831     const unsigned Offset = (I - 1) * PartSize;
832 
833     Register SrcReg = MI.getOperand(I).getReg();
834     assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
835 
836     auto ZextInput = MIRBuilder.buildZExt(DstTy, SrcReg);
837 
838     Register NextResult = I + 1 == NumOps ? DstReg :
839       MRI.createGenericVirtualRegister(DstTy);
840 
841     auto ShiftAmt = MIRBuilder.buildConstant(DstTy, Offset);
842     auto Shl = MIRBuilder.buildShl(DstTy, ZextInput, ShiftAmt);
843     MIRBuilder.buildOr(NextResult, ResultReg, Shl);
844     ResultReg = NextResult;
845   }
846 
847   MI.eraseFromParent();
848   return Legalized;
849 }
850 
851 LegalizerHelper::LegalizeResult
852 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
853                                           LLT WideTy) {
854   if (TypeIdx != 0)
855     return UnableToLegalize;
856 
857   unsigned NumDst = MI.getNumOperands() - 1;
858   Register SrcReg = MI.getOperand(NumDst).getReg();
859   LLT SrcTy = MRI.getType(SrcReg);
860   if (!SrcTy.isScalar())
861     return UnableToLegalize;
862 
863   Register Dst0Reg = MI.getOperand(0).getReg();
864   LLT DstTy = MRI.getType(Dst0Reg);
865   if (!DstTy.isScalar())
866     return UnableToLegalize;
867 
868   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
869   LLT NewSrcTy = LLT::scalar(NewSrcSize);
870   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
871 
872   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
873 
874   for (unsigned I = 1; I != NumDst; ++I) {
875     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
876     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
877     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
878   }
879 
880   Observer.changingInstr(MI);
881 
882   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
883   for (unsigned I = 0; I != NumDst; ++I)
884     widenScalarDst(MI, WideTy, I);
885 
886   Observer.changedInstr(MI);
887 
888   return Legalized;
889 }
890 
891 LegalizerHelper::LegalizeResult
892 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
893                                     LLT WideTy) {
894   Register DstReg = MI.getOperand(0).getReg();
895   Register SrcReg = MI.getOperand(1).getReg();
896   LLT SrcTy = MRI.getType(SrcReg);
897 
898   LLT DstTy = MRI.getType(DstReg);
899   unsigned Offset = MI.getOperand(2).getImm();
900 
901   if (TypeIdx == 0) {
902     if (SrcTy.isVector() || DstTy.isVector())
903       return UnableToLegalize;
904 
905     SrcOp Src(SrcReg);
906     if (SrcTy.isPointer()) {
907       // Extracts from pointers can be handled only if they are really just
908       // simple integers.
909       const DataLayout &DL = MIRBuilder.getDataLayout();
910       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
911         return UnableToLegalize;
912 
913       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
914       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
915       SrcTy = SrcAsIntTy;
916     }
917 
918     if (DstTy.isPointer())
919       return UnableToLegalize;
920 
921     if (Offset == 0) {
922       // Avoid a shift in the degenerate case.
923       MIRBuilder.buildTrunc(DstReg,
924                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
925       MI.eraseFromParent();
926       return Legalized;
927     }
928 
929     // Do a shift in the source type.
930     LLT ShiftTy = SrcTy;
931     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
932       Src = MIRBuilder.buildAnyExt(WideTy, Src);
933       ShiftTy = WideTy;
934     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
935       return UnableToLegalize;
936 
937     auto LShr = MIRBuilder.buildLShr(
938       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
939     MIRBuilder.buildTrunc(DstReg, LShr);
940     MI.eraseFromParent();
941     return Legalized;
942   }
943 
944   if (SrcTy.isScalar()) {
945     Observer.changingInstr(MI);
946     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
947     Observer.changedInstr(MI);
948     return Legalized;
949   }
950 
951   if (!SrcTy.isVector())
952     return UnableToLegalize;
953 
954   if (DstTy != SrcTy.getElementType())
955     return UnableToLegalize;
956 
957   if (Offset % SrcTy.getScalarSizeInBits() != 0)
958     return UnableToLegalize;
959 
960   Observer.changingInstr(MI);
961   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
962 
963   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
964                           Offset);
965   widenScalarDst(MI, WideTy.getScalarType(), 0);
966   Observer.changedInstr(MI);
967   return Legalized;
968 }
969 
970 LegalizerHelper::LegalizeResult
971 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
972                                    LLT WideTy) {
973   if (TypeIdx != 0)
974     return UnableToLegalize;
975   Observer.changingInstr(MI);
976   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
977   widenScalarDst(MI, WideTy);
978   Observer.changedInstr(MI);
979   return Legalized;
980 }
981 
982 LegalizerHelper::LegalizeResult
983 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
984   MIRBuilder.setInstr(MI);
985 
986   switch (MI.getOpcode()) {
987   default:
988     return UnableToLegalize;
989   case TargetOpcode::G_EXTRACT:
990     return widenScalarExtract(MI, TypeIdx, WideTy);
991   case TargetOpcode::G_INSERT:
992     return widenScalarInsert(MI, TypeIdx, WideTy);
993   case TargetOpcode::G_MERGE_VALUES:
994     return widenScalarMergeValues(MI, TypeIdx, WideTy);
995   case TargetOpcode::G_UNMERGE_VALUES:
996     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
997   case TargetOpcode::G_UADDO:
998   case TargetOpcode::G_USUBO: {
999     if (TypeIdx == 1)
1000       return UnableToLegalize; // TODO
1001     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1002                                          {MI.getOperand(2).getReg()});
1003     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1004                                          {MI.getOperand(3).getReg()});
1005     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1006                           ? TargetOpcode::G_ADD
1007                           : TargetOpcode::G_SUB;
1008     // Do the arithmetic in the larger type.
1009     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1010     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1011     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
1012     auto AndOp = MIRBuilder.buildInstr(
1013         TargetOpcode::G_AND, {WideTy},
1014         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
1015     // There is no overflow if the AndOp is the same as NewOp.
1016     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
1017                          AndOp);
1018     // Now trunc the NewOp to the original result.
1019     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
1020     MI.eraseFromParent();
1021     return Legalized;
1022   }
1023   case TargetOpcode::G_CTTZ:
1024   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1025   case TargetOpcode::G_CTLZ:
1026   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1027   case TargetOpcode::G_CTPOP: {
1028     if (TypeIdx == 0) {
1029       Observer.changingInstr(MI);
1030       widenScalarDst(MI, WideTy, 0);
1031       Observer.changedInstr(MI);
1032       return Legalized;
1033     }
1034 
1035     Register SrcReg = MI.getOperand(1).getReg();
1036 
1037     // First ZEXT the input.
1038     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1039     LLT CurTy = MRI.getType(SrcReg);
1040     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1041       // The count is the same in the larger type except if the original
1042       // value was zero.  This can be handled by setting the bit just off
1043       // the top of the original type.
1044       auto TopBit =
1045           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1046       MIBSrc = MIRBuilder.buildOr(
1047         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1048     }
1049 
1050     // Perform the operation at the larger size.
1051     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1052     // This is already the correct result for CTPOP and CTTZs
1053     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1054         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1055       // The correct result is NewOp - (Difference in widety and current ty).
1056       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1057       MIBNewOp = MIRBuilder.buildInstr(
1058           TargetOpcode::G_SUB, {WideTy},
1059           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1060     }
1061 
1062     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1063     MI.eraseFromParent();
1064     return Legalized;
1065   }
1066   case TargetOpcode::G_BSWAP: {
1067     Observer.changingInstr(MI);
1068     Register DstReg = MI.getOperand(0).getReg();
1069 
1070     Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1071     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1072     Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1073     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1074 
1075     MI.getOperand(0).setReg(DstExt);
1076 
1077     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1078 
1079     LLT Ty = MRI.getType(DstReg);
1080     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1081     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1082     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1083       .addDef(ShrReg)
1084       .addUse(DstExt)
1085       .addUse(ShiftAmtReg);
1086 
1087     MIRBuilder.buildTrunc(DstReg, ShrReg);
1088     Observer.changedInstr(MI);
1089     return Legalized;
1090   }
1091   case TargetOpcode::G_ADD:
1092   case TargetOpcode::G_AND:
1093   case TargetOpcode::G_MUL:
1094   case TargetOpcode::G_OR:
1095   case TargetOpcode::G_XOR:
1096   case TargetOpcode::G_SUB:
1097     // Perform operation at larger width (any extension is fines here, high bits
1098     // don't affect the result) and then truncate the result back to the
1099     // original type.
1100     Observer.changingInstr(MI);
1101     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1102     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1103     widenScalarDst(MI, WideTy);
1104     Observer.changedInstr(MI);
1105     return Legalized;
1106 
1107   case TargetOpcode::G_SHL:
1108     Observer.changingInstr(MI);
1109 
1110     if (TypeIdx == 0) {
1111       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1112       widenScalarDst(MI, WideTy);
1113     } else {
1114       assert(TypeIdx == 1);
1115       // The "number of bits to shift" operand must preserve its value as an
1116       // unsigned integer:
1117       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1118     }
1119 
1120     Observer.changedInstr(MI);
1121     return Legalized;
1122 
1123   case TargetOpcode::G_SDIV:
1124   case TargetOpcode::G_SREM:
1125   case TargetOpcode::G_SMIN:
1126   case TargetOpcode::G_SMAX:
1127     Observer.changingInstr(MI);
1128     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1129     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1130     widenScalarDst(MI, WideTy);
1131     Observer.changedInstr(MI);
1132     return Legalized;
1133 
1134   case TargetOpcode::G_ASHR:
1135   case TargetOpcode::G_LSHR:
1136     Observer.changingInstr(MI);
1137 
1138     if (TypeIdx == 0) {
1139       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1140         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1141 
1142       widenScalarSrc(MI, WideTy, 1, CvtOp);
1143       widenScalarDst(MI, WideTy);
1144     } else {
1145       assert(TypeIdx == 1);
1146       // The "number of bits to shift" operand must preserve its value as an
1147       // unsigned integer:
1148       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1149     }
1150 
1151     Observer.changedInstr(MI);
1152     return Legalized;
1153   case TargetOpcode::G_UDIV:
1154   case TargetOpcode::G_UREM:
1155   case TargetOpcode::G_UMIN:
1156   case TargetOpcode::G_UMAX:
1157     Observer.changingInstr(MI);
1158     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1159     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1160     widenScalarDst(MI, WideTy);
1161     Observer.changedInstr(MI);
1162     return Legalized;
1163 
1164   case TargetOpcode::G_SELECT:
1165     Observer.changingInstr(MI);
1166     if (TypeIdx == 0) {
1167       // Perform operation at larger width (any extension is fine here, high
1168       // bits don't affect the result) and then truncate the result back to the
1169       // original type.
1170       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1171       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1172       widenScalarDst(MI, WideTy);
1173     } else {
1174       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1175       // Explicit extension is required here since high bits affect the result.
1176       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1177     }
1178     Observer.changedInstr(MI);
1179     return Legalized;
1180 
1181   case TargetOpcode::G_FPTOSI:
1182   case TargetOpcode::G_FPTOUI:
1183     if (TypeIdx != 0)
1184       return UnableToLegalize;
1185     Observer.changingInstr(MI);
1186     widenScalarDst(MI, WideTy);
1187     Observer.changedInstr(MI);
1188     return Legalized;
1189 
1190   case TargetOpcode::G_SITOFP:
1191     if (TypeIdx != 1)
1192       return UnableToLegalize;
1193     Observer.changingInstr(MI);
1194     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1195     Observer.changedInstr(MI);
1196     return Legalized;
1197 
1198   case TargetOpcode::G_UITOFP:
1199     if (TypeIdx != 1)
1200       return UnableToLegalize;
1201     Observer.changingInstr(MI);
1202     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1203     Observer.changedInstr(MI);
1204     return Legalized;
1205 
1206   case TargetOpcode::G_LOAD:
1207   case TargetOpcode::G_SEXTLOAD:
1208   case TargetOpcode::G_ZEXTLOAD:
1209     Observer.changingInstr(MI);
1210     widenScalarDst(MI, WideTy);
1211     Observer.changedInstr(MI);
1212     return Legalized;
1213 
1214   case TargetOpcode::G_STORE: {
1215     if (TypeIdx != 0)
1216       return UnableToLegalize;
1217 
1218     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1219     if (!isPowerOf2_32(Ty.getSizeInBits()))
1220       return UnableToLegalize;
1221 
1222     Observer.changingInstr(MI);
1223 
1224     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1225       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1226     widenScalarSrc(MI, WideTy, 0, ExtType);
1227 
1228     Observer.changedInstr(MI);
1229     return Legalized;
1230   }
1231   case TargetOpcode::G_CONSTANT: {
1232     MachineOperand &SrcMO = MI.getOperand(1);
1233     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1234     const APInt &Val = SrcMO.getCImm()->getValue().sext(WideTy.getSizeInBits());
1235     Observer.changingInstr(MI);
1236     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1237 
1238     widenScalarDst(MI, WideTy);
1239     Observer.changedInstr(MI);
1240     return Legalized;
1241   }
1242   case TargetOpcode::G_FCONSTANT: {
1243     MachineOperand &SrcMO = MI.getOperand(1);
1244     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1245     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1246     bool LosesInfo;
1247     switch (WideTy.getSizeInBits()) {
1248     case 32:
1249       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1250                   &LosesInfo);
1251       break;
1252     case 64:
1253       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1254                   &LosesInfo);
1255       break;
1256     default:
1257       return UnableToLegalize;
1258     }
1259 
1260     assert(!LosesInfo && "extend should always be lossless");
1261 
1262     Observer.changingInstr(MI);
1263     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1264 
1265     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1266     Observer.changedInstr(MI);
1267     return Legalized;
1268   }
1269   case TargetOpcode::G_IMPLICIT_DEF: {
1270     Observer.changingInstr(MI);
1271     widenScalarDst(MI, WideTy);
1272     Observer.changedInstr(MI);
1273     return Legalized;
1274   }
1275   case TargetOpcode::G_BRCOND:
1276     Observer.changingInstr(MI);
1277     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1278     Observer.changedInstr(MI);
1279     return Legalized;
1280 
1281   case TargetOpcode::G_FCMP:
1282     Observer.changingInstr(MI);
1283     if (TypeIdx == 0)
1284       widenScalarDst(MI, WideTy);
1285     else {
1286       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1287       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1288     }
1289     Observer.changedInstr(MI);
1290     return Legalized;
1291 
1292   case TargetOpcode::G_ICMP:
1293     Observer.changingInstr(MI);
1294     if (TypeIdx == 0)
1295       widenScalarDst(MI, WideTy);
1296     else {
1297       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1298                                MI.getOperand(1).getPredicate()))
1299                                ? TargetOpcode::G_SEXT
1300                                : TargetOpcode::G_ZEXT;
1301       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1302       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1303     }
1304     Observer.changedInstr(MI);
1305     return Legalized;
1306 
1307   case TargetOpcode::G_GEP:
1308     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
1309     Observer.changingInstr(MI);
1310     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1311     Observer.changedInstr(MI);
1312     return Legalized;
1313 
1314   case TargetOpcode::G_PHI: {
1315     assert(TypeIdx == 0 && "Expecting only Idx 0");
1316 
1317     Observer.changingInstr(MI);
1318     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1319       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1320       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1321       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1322     }
1323 
1324     MachineBasicBlock &MBB = *MI.getParent();
1325     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1326     widenScalarDst(MI, WideTy);
1327     Observer.changedInstr(MI);
1328     return Legalized;
1329   }
1330   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1331     if (TypeIdx == 0) {
1332       Register VecReg = MI.getOperand(1).getReg();
1333       LLT VecTy = MRI.getType(VecReg);
1334       Observer.changingInstr(MI);
1335 
1336       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1337                                      WideTy.getSizeInBits()),
1338                      1, TargetOpcode::G_SEXT);
1339 
1340       widenScalarDst(MI, WideTy, 0);
1341       Observer.changedInstr(MI);
1342       return Legalized;
1343     }
1344 
1345     if (TypeIdx != 2)
1346       return UnableToLegalize;
1347     Observer.changingInstr(MI);
1348     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1349     Observer.changedInstr(MI);
1350     return Legalized;
1351   }
1352   case TargetOpcode::G_FADD:
1353   case TargetOpcode::G_FMUL:
1354   case TargetOpcode::G_FSUB:
1355   case TargetOpcode::G_FMA:
1356   case TargetOpcode::G_FNEG:
1357   case TargetOpcode::G_FABS:
1358   case TargetOpcode::G_FCANONICALIZE:
1359   case TargetOpcode::G_FDIV:
1360   case TargetOpcode::G_FREM:
1361   case TargetOpcode::G_FCEIL:
1362   case TargetOpcode::G_FFLOOR:
1363   case TargetOpcode::G_FCOS:
1364   case TargetOpcode::G_FSIN:
1365   case TargetOpcode::G_FLOG10:
1366   case TargetOpcode::G_FLOG:
1367   case TargetOpcode::G_FLOG2:
1368   case TargetOpcode::G_FRINT:
1369   case TargetOpcode::G_FNEARBYINT:
1370   case TargetOpcode::G_FSQRT:
1371   case TargetOpcode::G_FEXP:
1372   case TargetOpcode::G_FEXP2:
1373   case TargetOpcode::G_FPOW:
1374   case TargetOpcode::G_INTRINSIC_TRUNC:
1375   case TargetOpcode::G_INTRINSIC_ROUND:
1376     assert(TypeIdx == 0);
1377     Observer.changingInstr(MI);
1378 
1379     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1380       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1381 
1382     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1383     Observer.changedInstr(MI);
1384     return Legalized;
1385   case TargetOpcode::G_INTTOPTR:
1386     if (TypeIdx != 1)
1387       return UnableToLegalize;
1388 
1389     Observer.changingInstr(MI);
1390     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1391     Observer.changedInstr(MI);
1392     return Legalized;
1393   case TargetOpcode::G_PTRTOINT:
1394     if (TypeIdx != 0)
1395       return UnableToLegalize;
1396 
1397     Observer.changingInstr(MI);
1398     widenScalarDst(MI, WideTy, 0);
1399     Observer.changedInstr(MI);
1400     return Legalized;
1401   }
1402 }
1403 
1404 LegalizerHelper::LegalizeResult
1405 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1406   using namespace TargetOpcode;
1407   MIRBuilder.setInstr(MI);
1408 
1409   switch(MI.getOpcode()) {
1410   default:
1411     return UnableToLegalize;
1412   case TargetOpcode::G_SREM:
1413   case TargetOpcode::G_UREM: {
1414     Register QuotReg = MRI.createGenericVirtualRegister(Ty);
1415     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1416         .addDef(QuotReg)
1417         .addUse(MI.getOperand(1).getReg())
1418         .addUse(MI.getOperand(2).getReg());
1419 
1420     Register ProdReg = MRI.createGenericVirtualRegister(Ty);
1421     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1422     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1423                         ProdReg);
1424     MI.eraseFromParent();
1425     return Legalized;
1426   }
1427   case TargetOpcode::G_SMULO:
1428   case TargetOpcode::G_UMULO: {
1429     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
1430     // result.
1431     Register Res = MI.getOperand(0).getReg();
1432     Register Overflow = MI.getOperand(1).getReg();
1433     Register LHS = MI.getOperand(2).getReg();
1434     Register RHS = MI.getOperand(3).getReg();
1435 
1436     MIRBuilder.buildMul(Res, LHS, RHS);
1437 
1438     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
1439                           ? TargetOpcode::G_SMULH
1440                           : TargetOpcode::G_UMULH;
1441 
1442     Register HiPart = MRI.createGenericVirtualRegister(Ty);
1443     MIRBuilder.buildInstr(Opcode)
1444       .addDef(HiPart)
1445       .addUse(LHS)
1446       .addUse(RHS);
1447 
1448     Register Zero = MRI.createGenericVirtualRegister(Ty);
1449     MIRBuilder.buildConstant(Zero, 0);
1450 
1451     // For *signed* multiply, overflow is detected by checking:
1452     // (hi != (lo >> bitwidth-1))
1453     if (Opcode == TargetOpcode::G_SMULH) {
1454       Register Shifted = MRI.createGenericVirtualRegister(Ty);
1455       Register ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1456       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
1457       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
1458         .addDef(Shifted)
1459         .addUse(Res)
1460         .addUse(ShiftAmt);
1461       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
1462     } else {
1463       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
1464     }
1465     MI.eraseFromParent();
1466     return Legalized;
1467   }
1468   case TargetOpcode::G_FNEG: {
1469     // TODO: Handle vector types once we are able to
1470     // represent them.
1471     if (Ty.isVector())
1472       return UnableToLegalize;
1473     Register Res = MI.getOperand(0).getReg();
1474     Type *ZeroTy;
1475     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1476     switch (Ty.getSizeInBits()) {
1477     case 16:
1478       ZeroTy = Type::getHalfTy(Ctx);
1479       break;
1480     case 32:
1481       ZeroTy = Type::getFloatTy(Ctx);
1482       break;
1483     case 64:
1484       ZeroTy = Type::getDoubleTy(Ctx);
1485       break;
1486     case 128:
1487       ZeroTy = Type::getFP128Ty(Ctx);
1488       break;
1489     default:
1490       llvm_unreachable("unexpected floating-point type");
1491     }
1492     ConstantFP &ZeroForNegation =
1493         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
1494     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
1495     Register SubByReg = MI.getOperand(1).getReg();
1496     Register ZeroReg = Zero->getOperand(0).getReg();
1497     MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
1498                           MI.getFlags());
1499     MI.eraseFromParent();
1500     return Legalized;
1501   }
1502   case TargetOpcode::G_FSUB: {
1503     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
1504     // First, check if G_FNEG is marked as Lower. If so, we may
1505     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
1506     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
1507       return UnableToLegalize;
1508     Register Res = MI.getOperand(0).getReg();
1509     Register LHS = MI.getOperand(1).getReg();
1510     Register RHS = MI.getOperand(2).getReg();
1511     Register Neg = MRI.createGenericVirtualRegister(Ty);
1512     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
1513     MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
1514     MI.eraseFromParent();
1515     return Legalized;
1516   }
1517   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
1518     Register OldValRes = MI.getOperand(0).getReg();
1519     Register SuccessRes = MI.getOperand(1).getReg();
1520     Register Addr = MI.getOperand(2).getReg();
1521     Register CmpVal = MI.getOperand(3).getReg();
1522     Register NewVal = MI.getOperand(4).getReg();
1523     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
1524                                   **MI.memoperands_begin());
1525     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
1526     MI.eraseFromParent();
1527     return Legalized;
1528   }
1529   case TargetOpcode::G_LOAD:
1530   case TargetOpcode::G_SEXTLOAD:
1531   case TargetOpcode::G_ZEXTLOAD: {
1532     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
1533     Register DstReg = MI.getOperand(0).getReg();
1534     Register PtrReg = MI.getOperand(1).getReg();
1535     LLT DstTy = MRI.getType(DstReg);
1536     auto &MMO = **MI.memoperands_begin();
1537 
1538     if (DstTy.getSizeInBits() == MMO.getSize() /* in bytes */ * 8) {
1539       // In the case of G_LOAD, this was a non-extending load already and we're
1540       // about to lower to the same instruction.
1541       if (MI.getOpcode() == TargetOpcode::G_LOAD)
1542           return UnableToLegalize;
1543       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
1544       MI.eraseFromParent();
1545       return Legalized;
1546     }
1547 
1548     if (DstTy.isScalar()) {
1549       Register TmpReg =
1550           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
1551       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
1552       switch (MI.getOpcode()) {
1553       default:
1554         llvm_unreachable("Unexpected opcode");
1555       case TargetOpcode::G_LOAD:
1556         MIRBuilder.buildAnyExt(DstReg, TmpReg);
1557         break;
1558       case TargetOpcode::G_SEXTLOAD:
1559         MIRBuilder.buildSExt(DstReg, TmpReg);
1560         break;
1561       case TargetOpcode::G_ZEXTLOAD:
1562         MIRBuilder.buildZExt(DstReg, TmpReg);
1563         break;
1564       }
1565       MI.eraseFromParent();
1566       return Legalized;
1567     }
1568 
1569     return UnableToLegalize;
1570   }
1571   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1572   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1573   case TargetOpcode::G_CTLZ:
1574   case TargetOpcode::G_CTTZ:
1575   case TargetOpcode::G_CTPOP:
1576     return lowerBitCount(MI, TypeIdx, Ty);
1577   case G_UADDO: {
1578     Register Res = MI.getOperand(0).getReg();
1579     Register CarryOut = MI.getOperand(1).getReg();
1580     Register LHS = MI.getOperand(2).getReg();
1581     Register RHS = MI.getOperand(3).getReg();
1582 
1583     MIRBuilder.buildAdd(Res, LHS, RHS);
1584     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
1585 
1586     MI.eraseFromParent();
1587     return Legalized;
1588   }
1589   case G_UADDE: {
1590     Register Res = MI.getOperand(0).getReg();
1591     Register CarryOut = MI.getOperand(1).getReg();
1592     Register LHS = MI.getOperand(2).getReg();
1593     Register RHS = MI.getOperand(3).getReg();
1594     Register CarryIn = MI.getOperand(4).getReg();
1595 
1596     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
1597     Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
1598 
1599     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
1600     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
1601     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
1602     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
1603 
1604     MI.eraseFromParent();
1605     return Legalized;
1606   }
1607   case G_USUBO: {
1608     Register Res = MI.getOperand(0).getReg();
1609     Register BorrowOut = MI.getOperand(1).getReg();
1610     Register LHS = MI.getOperand(2).getReg();
1611     Register RHS = MI.getOperand(3).getReg();
1612 
1613     MIRBuilder.buildSub(Res, LHS, RHS);
1614     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
1615 
1616     MI.eraseFromParent();
1617     return Legalized;
1618   }
1619   case G_USUBE: {
1620     Register Res = MI.getOperand(0).getReg();
1621     Register BorrowOut = MI.getOperand(1).getReg();
1622     Register LHS = MI.getOperand(2).getReg();
1623     Register RHS = MI.getOperand(3).getReg();
1624     Register BorrowIn = MI.getOperand(4).getReg();
1625 
1626     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
1627     Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
1628     Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1629     Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
1630 
1631     MIRBuilder.buildSub(TmpRes, LHS, RHS);
1632     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
1633     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
1634     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
1635     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
1636     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
1637 
1638     MI.eraseFromParent();
1639     return Legalized;
1640   }
1641   case G_UITOFP:
1642     return lowerUITOFP(MI, TypeIdx, Ty);
1643   case G_SITOFP:
1644     return lowerSITOFP(MI, TypeIdx, Ty);
1645   case G_SMIN:
1646   case G_SMAX:
1647   case G_UMIN:
1648   case G_UMAX:
1649     return lowerMinMax(MI, TypeIdx, Ty);
1650   }
1651 }
1652 
1653 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
1654     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
1655   SmallVector<Register, 2> DstRegs;
1656 
1657   unsigned NarrowSize = NarrowTy.getSizeInBits();
1658   Register DstReg = MI.getOperand(0).getReg();
1659   unsigned Size = MRI.getType(DstReg).getSizeInBits();
1660   int NumParts = Size / NarrowSize;
1661   // FIXME: Don't know how to handle the situation where the small vectors
1662   // aren't all the same size yet.
1663   if (Size % NarrowSize != 0)
1664     return UnableToLegalize;
1665 
1666   for (int i = 0; i < NumParts; ++i) {
1667     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
1668     MIRBuilder.buildUndef(TmpReg);
1669     DstRegs.push_back(TmpReg);
1670   }
1671 
1672   if (NarrowTy.isVector())
1673     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1674   else
1675     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1676 
1677   MI.eraseFromParent();
1678   return Legalized;
1679 }
1680 
1681 LegalizerHelper::LegalizeResult
1682 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
1683                                           LLT NarrowTy) {
1684   const unsigned Opc = MI.getOpcode();
1685   const unsigned NumOps = MI.getNumOperands() - 1;
1686   const unsigned NarrowSize = NarrowTy.getSizeInBits();
1687   const Register DstReg = MI.getOperand(0).getReg();
1688   const unsigned Flags = MI.getFlags();
1689   const LLT DstTy = MRI.getType(DstReg);
1690   const unsigned Size = DstTy.getSizeInBits();
1691   const int NumParts = Size / NarrowSize;
1692   const LLT EltTy = DstTy.getElementType();
1693   const unsigned EltSize = EltTy.getSizeInBits();
1694   const unsigned BitsForNumParts = NarrowSize * NumParts;
1695 
1696   // Check if we have any leftovers. If we do, then only handle the case where
1697   // the leftover is one element.
1698   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
1699     return UnableToLegalize;
1700 
1701   if (BitsForNumParts != Size) {
1702     Register AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
1703     MIRBuilder.buildUndef(AccumDstReg);
1704 
1705     // Handle the pieces which evenly divide into the requested type with
1706     // extract/op/insert sequence.
1707     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
1708       SmallVector<SrcOp, 4> SrcOps;
1709       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1710         Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
1711         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
1712         SrcOps.push_back(PartOpReg);
1713       }
1714 
1715       Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
1716       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1717 
1718       Register PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
1719       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
1720       AccumDstReg = PartInsertReg;
1721     }
1722 
1723     // Handle the remaining element sized leftover piece.
1724     SmallVector<SrcOp, 4> SrcOps;
1725     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1726       Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
1727       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
1728                               BitsForNumParts);
1729       SrcOps.push_back(PartOpReg);
1730     }
1731 
1732     Register PartDstReg = MRI.createGenericVirtualRegister(EltTy);
1733     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
1734     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
1735     MI.eraseFromParent();
1736 
1737     return Legalized;
1738   }
1739 
1740   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
1741 
1742   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
1743 
1744   if (NumOps >= 2)
1745     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
1746 
1747   if (NumOps >= 3)
1748     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
1749 
1750   for (int i = 0; i < NumParts; ++i) {
1751     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
1752 
1753     if (NumOps == 1)
1754       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
1755     else if (NumOps == 2) {
1756       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
1757     } else if (NumOps == 3) {
1758       MIRBuilder.buildInstr(Opc, {DstReg},
1759                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
1760     }
1761 
1762     DstRegs.push_back(DstReg);
1763   }
1764 
1765   if (NarrowTy.isVector())
1766     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1767   else
1768     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1769 
1770   MI.eraseFromParent();
1771   return Legalized;
1772 }
1773 
1774 // Handle splitting vector operations which need to have the same number of
1775 // elements in each type index, but each type index may have a different element
1776 // type.
1777 //
1778 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
1779 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1780 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1781 //
1782 // Also handles some irregular breakdown cases, e.g.
1783 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
1784 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
1785 //             s64 = G_SHL s64, s32
1786 LegalizerHelper::LegalizeResult
1787 LegalizerHelper::fewerElementsVectorMultiEltType(
1788   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
1789   if (TypeIdx != 0)
1790     return UnableToLegalize;
1791 
1792   const LLT NarrowTy0 = NarrowTyArg;
1793   const unsigned NewNumElts =
1794       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
1795 
1796   const Register DstReg = MI.getOperand(0).getReg();
1797   LLT DstTy = MRI.getType(DstReg);
1798   LLT LeftoverTy0;
1799 
1800   int NumParts, NumLeftover;
1801   // All of the operands need to have the same number of elements, so if we can
1802   // determine a type breakdown for the result type, we can for all of the
1803   // source types.
1804   std::tie(NumParts, NumLeftover)
1805     = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0);
1806   if (NumParts < 0)
1807     return UnableToLegalize;
1808 
1809   SmallVector<MachineInstrBuilder, 4> NewInsts;
1810 
1811   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
1812   SmallVector<Register, 4> PartRegs, LeftoverRegs;
1813 
1814   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
1815     LLT LeftoverTy;
1816     Register SrcReg = MI.getOperand(I).getReg();
1817     LLT SrcTyI = MRI.getType(SrcReg);
1818     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
1819     LLT LeftoverTyI;
1820 
1821     // Split this operand into the requested typed registers, and any leftover
1822     // required to reproduce the original type.
1823     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
1824                       LeftoverRegs))
1825       return UnableToLegalize;
1826 
1827     if (I == 1) {
1828       // For the first operand, create an instruction for each part and setup
1829       // the result.
1830       for (Register PartReg : PartRegs) {
1831         Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1832         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
1833                                .addDef(PartDstReg)
1834                                .addUse(PartReg));
1835         DstRegs.push_back(PartDstReg);
1836       }
1837 
1838       for (Register LeftoverReg : LeftoverRegs) {
1839         Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
1840         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
1841                                .addDef(PartDstReg)
1842                                .addUse(LeftoverReg));
1843         LeftoverDstRegs.push_back(PartDstReg);
1844       }
1845     } else {
1846       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
1847 
1848       // Add the newly created operand splits to the existing instructions. The
1849       // odd-sized pieces are ordered after the requested NarrowTyArg sized
1850       // pieces.
1851       unsigned InstCount = 0;
1852       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
1853         NewInsts[InstCount++].addUse(PartRegs[J]);
1854       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
1855         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
1856     }
1857 
1858     PartRegs.clear();
1859     LeftoverRegs.clear();
1860   }
1861 
1862   // Insert the newly built operations and rebuild the result register.
1863   for (auto &MIB : NewInsts)
1864     MIRBuilder.insertInstr(MIB);
1865 
1866   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
1867 
1868   MI.eraseFromParent();
1869   return Legalized;
1870 }
1871 
1872 LegalizerHelper::LegalizeResult
1873 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
1874                                           LLT NarrowTy) {
1875   if (TypeIdx != 0)
1876     return UnableToLegalize;
1877 
1878   Register DstReg = MI.getOperand(0).getReg();
1879   Register SrcReg = MI.getOperand(1).getReg();
1880   LLT DstTy = MRI.getType(DstReg);
1881   LLT SrcTy = MRI.getType(SrcReg);
1882 
1883   LLT NarrowTy0 = NarrowTy;
1884   LLT NarrowTy1;
1885   unsigned NumParts;
1886 
1887   if (NarrowTy.isVector()) {
1888     // Uneven breakdown not handled.
1889     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
1890     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
1891       return UnableToLegalize;
1892 
1893     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
1894   } else {
1895     NumParts = DstTy.getNumElements();
1896     NarrowTy1 = SrcTy.getElementType();
1897   }
1898 
1899   SmallVector<Register, 4> SrcRegs, DstRegs;
1900   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
1901 
1902   for (unsigned I = 0; I < NumParts; ++I) {
1903     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1904     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
1905       .addDef(DstReg)
1906       .addUse(SrcRegs[I]);
1907 
1908     NewInst->setFlags(MI.getFlags());
1909     DstRegs.push_back(DstReg);
1910   }
1911 
1912   if (NarrowTy.isVector())
1913     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1914   else
1915     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1916 
1917   MI.eraseFromParent();
1918   return Legalized;
1919 }
1920 
1921 LegalizerHelper::LegalizeResult
1922 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
1923                                         LLT NarrowTy) {
1924   Register DstReg = MI.getOperand(0).getReg();
1925   Register Src0Reg = MI.getOperand(2).getReg();
1926   LLT DstTy = MRI.getType(DstReg);
1927   LLT SrcTy = MRI.getType(Src0Reg);
1928 
1929   unsigned NumParts;
1930   LLT NarrowTy0, NarrowTy1;
1931 
1932   if (TypeIdx == 0) {
1933     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
1934     unsigned OldElts = DstTy.getNumElements();
1935 
1936     NarrowTy0 = NarrowTy;
1937     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
1938     NarrowTy1 = NarrowTy.isVector() ?
1939       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
1940       SrcTy.getElementType();
1941 
1942   } else {
1943     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
1944     unsigned OldElts = SrcTy.getNumElements();
1945 
1946     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
1947       NarrowTy.getNumElements();
1948     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
1949                             DstTy.getScalarSizeInBits());
1950     NarrowTy1 = NarrowTy;
1951   }
1952 
1953   // FIXME: Don't know how to handle the situation where the small vectors
1954   // aren't all the same size yet.
1955   if (NarrowTy1.isVector() &&
1956       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
1957     return UnableToLegalize;
1958 
1959   CmpInst::Predicate Pred
1960     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
1961 
1962   SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
1963   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
1964   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
1965 
1966   for (unsigned I = 0; I < NumParts; ++I) {
1967     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
1968     DstRegs.push_back(DstReg);
1969 
1970     if (MI.getOpcode() == TargetOpcode::G_ICMP)
1971       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
1972     else {
1973       MachineInstr *NewCmp
1974         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
1975       NewCmp->setFlags(MI.getFlags());
1976     }
1977   }
1978 
1979   if (NarrowTy1.isVector())
1980     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
1981   else
1982     MIRBuilder.buildBuildVector(DstReg, DstRegs);
1983 
1984   MI.eraseFromParent();
1985   return Legalized;
1986 }
1987 
1988 LegalizerHelper::LegalizeResult
1989 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
1990                                            LLT NarrowTy) {
1991   Register DstReg = MI.getOperand(0).getReg();
1992   Register CondReg = MI.getOperand(1).getReg();
1993 
1994   unsigned NumParts = 0;
1995   LLT NarrowTy0, NarrowTy1;
1996 
1997   LLT DstTy = MRI.getType(DstReg);
1998   LLT CondTy = MRI.getType(CondReg);
1999   unsigned Size = DstTy.getSizeInBits();
2000 
2001   assert(TypeIdx == 0 || CondTy.isVector());
2002 
2003   if (TypeIdx == 0) {
2004     NarrowTy0 = NarrowTy;
2005     NarrowTy1 = CondTy;
2006 
2007     unsigned NarrowSize = NarrowTy0.getSizeInBits();
2008     // FIXME: Don't know how to handle the situation where the small vectors
2009     // aren't all the same size yet.
2010     if (Size % NarrowSize != 0)
2011       return UnableToLegalize;
2012 
2013     NumParts = Size / NarrowSize;
2014 
2015     // Need to break down the condition type
2016     if (CondTy.isVector()) {
2017       if (CondTy.getNumElements() == NumParts)
2018         NarrowTy1 = CondTy.getElementType();
2019       else
2020         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
2021                                 CondTy.getScalarSizeInBits());
2022     }
2023   } else {
2024     NumParts = CondTy.getNumElements();
2025     if (NarrowTy.isVector()) {
2026       // TODO: Handle uneven breakdown.
2027       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
2028         return UnableToLegalize;
2029 
2030       return UnableToLegalize;
2031     } else {
2032       NarrowTy0 = DstTy.getElementType();
2033       NarrowTy1 = NarrowTy;
2034     }
2035   }
2036 
2037   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2038   if (CondTy.isVector())
2039     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2040 
2041   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2042   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2043 
2044   for (unsigned i = 0; i < NumParts; ++i) {
2045     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2046     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
2047                            Src1Regs[i], Src2Regs[i]);
2048     DstRegs.push_back(DstReg);
2049   }
2050 
2051   if (NarrowTy0.isVector())
2052     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2053   else
2054     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2055 
2056   MI.eraseFromParent();
2057   return Legalized;
2058 }
2059 
2060 LegalizerHelper::LegalizeResult
2061 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2062                                         LLT NarrowTy) {
2063   const Register DstReg = MI.getOperand(0).getReg();
2064   LLT PhiTy = MRI.getType(DstReg);
2065   LLT LeftoverTy;
2066 
2067   // All of the operands need to have the same number of elements, so if we can
2068   // determine a type breakdown for the result type, we can for all of the
2069   // source types.
2070   int NumParts, NumLeftover;
2071   std::tie(NumParts, NumLeftover)
2072     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2073   if (NumParts < 0)
2074     return UnableToLegalize;
2075 
2076   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2077   SmallVector<MachineInstrBuilder, 4> NewInsts;
2078 
2079   const int TotalNumParts = NumParts + NumLeftover;
2080 
2081   // Insert the new phis in the result block first.
2082   for (int I = 0; I != TotalNumParts; ++I) {
2083     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2084     Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
2085     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2086                        .addDef(PartDstReg));
2087     if (I < NumParts)
2088       DstRegs.push_back(PartDstReg);
2089     else
2090       LeftoverDstRegs.push_back(PartDstReg);
2091   }
2092 
2093   MachineBasicBlock *MBB = MI.getParent();
2094   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2095   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2096 
2097   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2098 
2099   // Insert code to extract the incoming values in each predecessor block.
2100   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2101     PartRegs.clear();
2102     LeftoverRegs.clear();
2103 
2104     Register SrcReg = MI.getOperand(I).getReg();
2105     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2106     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2107 
2108     LLT Unused;
2109     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2110                       LeftoverRegs))
2111       return UnableToLegalize;
2112 
2113     // Add the newly created operand splits to the existing instructions. The
2114     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2115     // pieces.
2116     for (int J = 0; J != TotalNumParts; ++J) {
2117       MachineInstrBuilder MIB = NewInsts[J];
2118       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2119       MIB.addMBB(&OpMBB);
2120     }
2121   }
2122 
2123   MI.eraseFromParent();
2124   return Legalized;
2125 }
2126 
2127 LegalizerHelper::LegalizeResult
2128 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2129                                       LLT NarrowTy) {
2130   // FIXME: Don't know how to handle secondary types yet.
2131   if (TypeIdx != 0)
2132     return UnableToLegalize;
2133 
2134   MachineMemOperand *MMO = *MI.memoperands_begin();
2135 
2136   // This implementation doesn't work for atomics. Give up instead of doing
2137   // something invalid.
2138   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2139       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2140     return UnableToLegalize;
2141 
2142   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2143   Register ValReg = MI.getOperand(0).getReg();
2144   Register AddrReg = MI.getOperand(1).getReg();
2145   LLT ValTy = MRI.getType(ValReg);
2146 
2147   int NumParts = -1;
2148   int NumLeftover = -1;
2149   LLT LeftoverTy;
2150   SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
2151   if (IsLoad) {
2152     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2153   } else {
2154     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2155                      NarrowLeftoverRegs)) {
2156       NumParts = NarrowRegs.size();
2157       NumLeftover = NarrowLeftoverRegs.size();
2158     }
2159   }
2160 
2161   if (NumParts == -1)
2162     return UnableToLegalize;
2163 
2164   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2165 
2166   unsigned TotalSize = ValTy.getSizeInBits();
2167 
2168   // Split the load/store into PartTy sized pieces starting at Offset. If this
2169   // is a load, return the new registers in ValRegs. For a store, each elements
2170   // of ValRegs should be PartTy. Returns the next offset that needs to be
2171   // handled.
2172   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
2173                              unsigned Offset) -> unsigned {
2174     MachineFunction &MF = MIRBuilder.getMF();
2175     unsigned PartSize = PartTy.getSizeInBits();
2176     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2177          Offset += PartSize, ++Idx) {
2178       unsigned ByteSize = PartSize / 8;
2179       unsigned ByteOffset = Offset / 8;
2180       Register NewAddrReg;
2181 
2182       MIRBuilder.materializeGEP(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2183 
2184       MachineMemOperand *NewMMO =
2185         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2186 
2187       if (IsLoad) {
2188         Register Dst = MRI.createGenericVirtualRegister(PartTy);
2189         ValRegs.push_back(Dst);
2190         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
2191       } else {
2192         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
2193       }
2194     }
2195 
2196     return Offset;
2197   };
2198 
2199   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
2200 
2201   // Handle the rest of the register if this isn't an even type breakdown.
2202   if (LeftoverTy.isValid())
2203     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
2204 
2205   if (IsLoad) {
2206     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
2207                 LeftoverTy, NarrowLeftoverRegs);
2208   }
2209 
2210   MI.eraseFromParent();
2211   return Legalized;
2212 }
2213 
2214 LegalizerHelper::LegalizeResult
2215 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
2216                                      LLT NarrowTy) {
2217   using namespace TargetOpcode;
2218 
2219   MIRBuilder.setInstr(MI);
2220   switch (MI.getOpcode()) {
2221   case G_IMPLICIT_DEF:
2222     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
2223   case G_AND:
2224   case G_OR:
2225   case G_XOR:
2226   case G_ADD:
2227   case G_SUB:
2228   case G_MUL:
2229   case G_SMULH:
2230   case G_UMULH:
2231   case G_FADD:
2232   case G_FMUL:
2233   case G_FSUB:
2234   case G_FNEG:
2235   case G_FABS:
2236   case G_FCANONICALIZE:
2237   case G_FDIV:
2238   case G_FREM:
2239   case G_FMA:
2240   case G_FPOW:
2241   case G_FEXP:
2242   case G_FEXP2:
2243   case G_FLOG:
2244   case G_FLOG2:
2245   case G_FLOG10:
2246   case G_FNEARBYINT:
2247   case G_FCEIL:
2248   case G_FFLOOR:
2249   case G_FRINT:
2250   case G_INTRINSIC_ROUND:
2251   case G_INTRINSIC_TRUNC:
2252   case G_FCOS:
2253   case G_FSIN:
2254   case G_FSQRT:
2255   case G_BSWAP:
2256   case G_SDIV:
2257   case G_SMIN:
2258   case G_SMAX:
2259   case G_UMIN:
2260   case G_UMAX:
2261     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
2262   case G_SHL:
2263   case G_LSHR:
2264   case G_ASHR:
2265   case G_CTLZ:
2266   case G_CTLZ_ZERO_UNDEF:
2267   case G_CTTZ:
2268   case G_CTTZ_ZERO_UNDEF:
2269   case G_CTPOP:
2270   case G_FCOPYSIGN:
2271     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
2272   case G_ZEXT:
2273   case G_SEXT:
2274   case G_ANYEXT:
2275   case G_FPEXT:
2276   case G_FPTRUNC:
2277   case G_SITOFP:
2278   case G_UITOFP:
2279   case G_FPTOSI:
2280   case G_FPTOUI:
2281   case G_INTTOPTR:
2282   case G_PTRTOINT:
2283   case G_ADDRSPACE_CAST:
2284     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
2285   case G_ICMP:
2286   case G_FCMP:
2287     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
2288   case G_SELECT:
2289     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
2290   case G_PHI:
2291     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
2292   case G_LOAD:
2293   case G_STORE:
2294     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
2295   default:
2296     return UnableToLegalize;
2297   }
2298 }
2299 
2300 LegalizerHelper::LegalizeResult
2301 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
2302                                              const LLT HalfTy, const LLT AmtTy) {
2303 
2304   Register InL = MRI.createGenericVirtualRegister(HalfTy);
2305   Register InH = MRI.createGenericVirtualRegister(HalfTy);
2306   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2307 
2308   if (Amt.isNullValue()) {
2309     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
2310     MI.eraseFromParent();
2311     return Legalized;
2312   }
2313 
2314   LLT NVT = HalfTy;
2315   unsigned NVTBits = HalfTy.getSizeInBits();
2316   unsigned VTBits = 2 * NVTBits;
2317 
2318   SrcOp Lo(Register(0)), Hi(Register(0));
2319   if (MI.getOpcode() == TargetOpcode::G_SHL) {
2320     if (Amt.ugt(VTBits)) {
2321       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2322     } else if (Amt.ugt(NVTBits)) {
2323       Lo = MIRBuilder.buildConstant(NVT, 0);
2324       Hi = MIRBuilder.buildShl(NVT, InL,
2325                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2326     } else if (Amt == NVTBits) {
2327       Lo = MIRBuilder.buildConstant(NVT, 0);
2328       Hi = InL;
2329     } else {
2330       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
2331       auto OrLHS =
2332           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
2333       auto OrRHS = MIRBuilder.buildLShr(
2334           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2335       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2336     }
2337   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
2338     if (Amt.ugt(VTBits)) {
2339       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2340     } else if (Amt.ugt(NVTBits)) {
2341       Lo = MIRBuilder.buildLShr(NVT, InH,
2342                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2343       Hi = MIRBuilder.buildConstant(NVT, 0);
2344     } else if (Amt == NVTBits) {
2345       Lo = InH;
2346       Hi = MIRBuilder.buildConstant(NVT, 0);
2347     } else {
2348       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2349 
2350       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2351       auto OrRHS = MIRBuilder.buildShl(
2352           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2353 
2354       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2355       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
2356     }
2357   } else {
2358     if (Amt.ugt(VTBits)) {
2359       Hi = Lo = MIRBuilder.buildAShr(
2360           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2361     } else if (Amt.ugt(NVTBits)) {
2362       Lo = MIRBuilder.buildAShr(NVT, InH,
2363                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2364       Hi = MIRBuilder.buildAShr(NVT, InH,
2365                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2366     } else if (Amt == NVTBits) {
2367       Lo = InH;
2368       Hi = MIRBuilder.buildAShr(NVT, InH,
2369                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
2370     } else {
2371       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2372 
2373       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2374       auto OrRHS = MIRBuilder.buildShl(
2375           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2376 
2377       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2378       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
2379     }
2380   }
2381 
2382   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
2383   MI.eraseFromParent();
2384 
2385   return Legalized;
2386 }
2387 
2388 // TODO: Optimize if constant shift amount.
2389 LegalizerHelper::LegalizeResult
2390 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
2391                                    LLT RequestedTy) {
2392   if (TypeIdx == 1) {
2393     Observer.changingInstr(MI);
2394     narrowScalarSrc(MI, RequestedTy, 2);
2395     Observer.changedInstr(MI);
2396     return Legalized;
2397   }
2398 
2399   Register DstReg = MI.getOperand(0).getReg();
2400   LLT DstTy = MRI.getType(DstReg);
2401   if (DstTy.isVector())
2402     return UnableToLegalize;
2403 
2404   Register Amt = MI.getOperand(2).getReg();
2405   LLT ShiftAmtTy = MRI.getType(Amt);
2406   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
2407   if (DstEltSize % 2 != 0)
2408     return UnableToLegalize;
2409 
2410   // Ignore the input type. We can only go to exactly half the size of the
2411   // input. If that isn't small enough, the resulting pieces will be further
2412   // legalized.
2413   const unsigned NewBitSize = DstEltSize / 2;
2414   const LLT HalfTy = LLT::scalar(NewBitSize);
2415   const LLT CondTy = LLT::scalar(1);
2416 
2417   if (const MachineInstr *KShiftAmt =
2418           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
2419     return narrowScalarShiftByConstant(
2420         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
2421   }
2422 
2423   // TODO: Expand with known bits.
2424 
2425   // Handle the fully general expansion by an unknown amount.
2426   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
2427 
2428   Register InL = MRI.createGenericVirtualRegister(HalfTy);
2429   Register InH = MRI.createGenericVirtualRegister(HalfTy);
2430   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2431 
2432   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
2433   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
2434 
2435   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
2436   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
2437   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
2438 
2439   Register ResultRegs[2];
2440   switch (MI.getOpcode()) {
2441   case TargetOpcode::G_SHL: {
2442     // Short: ShAmt < NewBitSize
2443     auto LoS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2444 
2445     auto OrLHS = MIRBuilder.buildShl(HalfTy, InH, Amt);
2446     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
2447     auto HiS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2448 
2449     // Long: ShAmt >= NewBitSize
2450     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
2451     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
2452 
2453     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
2454     auto Hi = MIRBuilder.buildSelect(
2455         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
2456 
2457     ResultRegs[0] = Lo.getReg(0);
2458     ResultRegs[1] = Hi.getReg(0);
2459     break;
2460   }
2461   case TargetOpcode::G_LSHR: {
2462     // Short: ShAmt < NewBitSize
2463     auto HiS = MIRBuilder.buildLShr(HalfTy, InH, Amt);
2464 
2465     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2466     auto OrRHS = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
2467     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2468 
2469     // Long: ShAmt >= NewBitSize
2470     auto HiL = MIRBuilder.buildConstant(HalfTy, 0);          // Hi part is zero.
2471     auto LoL = MIRBuilder.buildLShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2472 
2473     auto Lo = MIRBuilder.buildSelect(
2474         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2475     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2476 
2477     ResultRegs[0] = Lo.getReg(0);
2478     ResultRegs[1] = Hi.getReg(0);
2479     break;
2480   }
2481   case TargetOpcode::G_ASHR: {
2482     // Short: ShAmt < NewBitSize
2483     auto HiS = MIRBuilder.buildAShr(HalfTy, InH, Amt);
2484 
2485     auto OrLHS = MIRBuilder.buildLShr(HalfTy, InL, Amt);
2486     auto OrRHS = MIRBuilder.buildLShr(HalfTy, InH, AmtLack);
2487     auto LoS = MIRBuilder.buildOr(HalfTy, OrLHS, OrRHS);
2488 
2489     // Long: ShAmt >= NewBitSize
2490 
2491     // Sign of Hi part.
2492     auto HiL = MIRBuilder.buildAShr(
2493         HalfTy, InH, MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1));
2494 
2495     auto LoL = MIRBuilder.buildAShr(HalfTy, InH, AmtExcess); // Lo from Hi part.
2496 
2497     auto Lo = MIRBuilder.buildSelect(
2498         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
2499 
2500     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
2501 
2502     ResultRegs[0] = Lo.getReg(0);
2503     ResultRegs[1] = Hi.getReg(0);
2504     break;
2505   }
2506   default:
2507     llvm_unreachable("not a shift");
2508   }
2509 
2510   MIRBuilder.buildMerge(DstReg, ResultRegs);
2511   MI.eraseFromParent();
2512   return Legalized;
2513 }
2514 
2515 LegalizerHelper::LegalizeResult
2516 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2517                                        LLT MoreTy) {
2518   assert(TypeIdx == 0 && "Expecting only Idx 0");
2519 
2520   Observer.changingInstr(MI);
2521   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2522     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2523     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2524     moreElementsVectorSrc(MI, MoreTy, I);
2525   }
2526 
2527   MachineBasicBlock &MBB = *MI.getParent();
2528   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
2529   moreElementsVectorDst(MI, MoreTy, 0);
2530   Observer.changedInstr(MI);
2531   return Legalized;
2532 }
2533 
2534 LegalizerHelper::LegalizeResult
2535 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
2536                                     LLT MoreTy) {
2537   MIRBuilder.setInstr(MI);
2538   unsigned Opc = MI.getOpcode();
2539   switch (Opc) {
2540   case TargetOpcode::G_IMPLICIT_DEF: {
2541     Observer.changingInstr(MI);
2542     moreElementsVectorDst(MI, MoreTy, 0);
2543     Observer.changedInstr(MI);
2544     return Legalized;
2545   }
2546   case TargetOpcode::G_AND:
2547   case TargetOpcode::G_OR:
2548   case TargetOpcode::G_XOR:
2549   case TargetOpcode::G_SMIN:
2550   case TargetOpcode::G_SMAX:
2551   case TargetOpcode::G_UMIN:
2552   case TargetOpcode::G_UMAX: {
2553     Observer.changingInstr(MI);
2554     moreElementsVectorSrc(MI, MoreTy, 1);
2555     moreElementsVectorSrc(MI, MoreTy, 2);
2556     moreElementsVectorDst(MI, MoreTy, 0);
2557     Observer.changedInstr(MI);
2558     return Legalized;
2559   }
2560   case TargetOpcode::G_EXTRACT:
2561     if (TypeIdx != 1)
2562       return UnableToLegalize;
2563     Observer.changingInstr(MI);
2564     moreElementsVectorSrc(MI, MoreTy, 1);
2565     Observer.changedInstr(MI);
2566     return Legalized;
2567   case TargetOpcode::G_INSERT:
2568     if (TypeIdx != 0)
2569       return UnableToLegalize;
2570     Observer.changingInstr(MI);
2571     moreElementsVectorSrc(MI, MoreTy, 1);
2572     moreElementsVectorDst(MI, MoreTy, 0);
2573     Observer.changedInstr(MI);
2574     return Legalized;
2575   case TargetOpcode::G_SELECT:
2576     if (TypeIdx != 0)
2577       return UnableToLegalize;
2578     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
2579       return UnableToLegalize;
2580 
2581     Observer.changingInstr(MI);
2582     moreElementsVectorSrc(MI, MoreTy, 2);
2583     moreElementsVectorSrc(MI, MoreTy, 3);
2584     moreElementsVectorDst(MI, MoreTy, 0);
2585     Observer.changedInstr(MI);
2586     return Legalized;
2587   case TargetOpcode::G_PHI:
2588     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
2589   default:
2590     return UnableToLegalize;
2591   }
2592 }
2593 
2594 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
2595                                         ArrayRef<Register> Src1Regs,
2596                                         ArrayRef<Register> Src2Regs,
2597                                         LLT NarrowTy) {
2598   MachineIRBuilder &B = MIRBuilder;
2599   unsigned SrcParts = Src1Regs.size();
2600   unsigned DstParts = DstRegs.size();
2601 
2602   unsigned DstIdx = 0; // Low bits of the result.
2603   Register FactorSum =
2604       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
2605   DstRegs[DstIdx] = FactorSum;
2606 
2607   unsigned CarrySumPrevDstIdx;
2608   SmallVector<Register, 4> Factors;
2609 
2610   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
2611     // Collect low parts of muls for DstIdx.
2612     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
2613          i <= std::min(DstIdx, SrcParts - 1); ++i) {
2614       MachineInstrBuilder Mul =
2615           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
2616       Factors.push_back(Mul.getReg(0));
2617     }
2618     // Collect high parts of muls from previous DstIdx.
2619     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
2620          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
2621       MachineInstrBuilder Umulh =
2622           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
2623       Factors.push_back(Umulh.getReg(0));
2624     }
2625     // Add CarrySum from additons calculated for previous DstIdx.
2626     if (DstIdx != 1) {
2627       Factors.push_back(CarrySumPrevDstIdx);
2628     }
2629 
2630     Register CarrySum;
2631     // Add all factors and accumulate all carries into CarrySum.
2632     if (DstIdx != DstParts - 1) {
2633       MachineInstrBuilder Uaddo =
2634           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
2635       FactorSum = Uaddo.getReg(0);
2636       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
2637       for (unsigned i = 2; i < Factors.size(); ++i) {
2638         MachineInstrBuilder Uaddo =
2639             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
2640         FactorSum = Uaddo.getReg(0);
2641         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
2642         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
2643       }
2644     } else {
2645       // Since value for the next index is not calculated, neither is CarrySum.
2646       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
2647       for (unsigned i = 2; i < Factors.size(); ++i)
2648         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
2649     }
2650 
2651     CarrySumPrevDstIdx = CarrySum;
2652     DstRegs[DstIdx] = FactorSum;
2653     Factors.clear();
2654   }
2655 }
2656 
2657 LegalizerHelper::LegalizeResult
2658 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
2659   Register DstReg = MI.getOperand(0).getReg();
2660   Register Src1 = MI.getOperand(1).getReg();
2661   Register Src2 = MI.getOperand(2).getReg();
2662 
2663   LLT Ty = MRI.getType(DstReg);
2664   if (Ty.isVector())
2665     return UnableToLegalize;
2666 
2667   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
2668   unsigned DstSize = Ty.getSizeInBits();
2669   unsigned NarrowSize = NarrowTy.getSizeInBits();
2670   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
2671     return UnableToLegalize;
2672 
2673   unsigned NumDstParts = DstSize / NarrowSize;
2674   unsigned NumSrcParts = SrcSize / NarrowSize;
2675   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
2676   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
2677 
2678   SmallVector<Register, 2> Src1Parts, Src2Parts, DstTmpRegs;
2679   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
2680   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
2681   DstTmpRegs.resize(DstTmpParts);
2682   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
2683 
2684   // Take only high half of registers if this is high mul.
2685   ArrayRef<Register> DstRegs(
2686       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
2687   MIRBuilder.buildMerge(DstReg, DstRegs);
2688   MI.eraseFromParent();
2689   return Legalized;
2690 }
2691 
2692 LegalizerHelper::LegalizeResult
2693 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
2694                                      LLT NarrowTy) {
2695   if (TypeIdx != 1)
2696     return UnableToLegalize;
2697 
2698   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2699 
2700   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2701   // FIXME: add support for when SizeOp1 isn't an exact multiple of
2702   // NarrowSize.
2703   if (SizeOp1 % NarrowSize != 0)
2704     return UnableToLegalize;
2705   int NumParts = SizeOp1 / NarrowSize;
2706 
2707   SmallVector<Register, 2> SrcRegs, DstRegs;
2708   SmallVector<uint64_t, 2> Indexes;
2709   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
2710 
2711   Register OpReg = MI.getOperand(0).getReg();
2712   uint64_t OpStart = MI.getOperand(2).getImm();
2713   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
2714   for (int i = 0; i < NumParts; ++i) {
2715     unsigned SrcStart = i * NarrowSize;
2716 
2717     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
2718       // No part of the extract uses this subregister, ignore it.
2719       continue;
2720     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
2721       // The entire subregister is extracted, forward the value.
2722       DstRegs.push_back(SrcRegs[i]);
2723       continue;
2724     }
2725 
2726     // OpSegStart is where this destination segment would start in OpReg if it
2727     // extended infinitely in both directions.
2728     int64_t ExtractOffset;
2729     uint64_t SegSize;
2730     if (OpStart < SrcStart) {
2731       ExtractOffset = 0;
2732       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
2733     } else {
2734       ExtractOffset = OpStart - SrcStart;
2735       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
2736     }
2737 
2738     Register SegReg = SrcRegs[i];
2739     if (ExtractOffset != 0 || SegSize != NarrowSize) {
2740       // A genuine extract is needed.
2741       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
2742       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
2743     }
2744 
2745     DstRegs.push_back(SegReg);
2746   }
2747 
2748   Register DstReg = MI.getOperand(0).getReg();
2749   if(MRI.getType(DstReg).isVector())
2750     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2751   else
2752     MIRBuilder.buildMerge(DstReg, DstRegs);
2753   MI.eraseFromParent();
2754   return Legalized;
2755 }
2756 
2757 LegalizerHelper::LegalizeResult
2758 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
2759                                     LLT NarrowTy) {
2760   // FIXME: Don't know how to handle secondary types yet.
2761   if (TypeIdx != 0)
2762     return UnableToLegalize;
2763 
2764   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2765   uint64_t NarrowSize = NarrowTy.getSizeInBits();
2766 
2767   // FIXME: add support for when SizeOp0 isn't an exact multiple of
2768   // NarrowSize.
2769   if (SizeOp0 % NarrowSize != 0)
2770     return UnableToLegalize;
2771 
2772   int NumParts = SizeOp0 / NarrowSize;
2773 
2774   SmallVector<Register, 2> SrcRegs, DstRegs;
2775   SmallVector<uint64_t, 2> Indexes;
2776   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
2777 
2778   Register OpReg = MI.getOperand(2).getReg();
2779   uint64_t OpStart = MI.getOperand(3).getImm();
2780   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
2781   for (int i = 0; i < NumParts; ++i) {
2782     unsigned DstStart = i * NarrowSize;
2783 
2784     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
2785       // No part of the insert affects this subregister, forward the original.
2786       DstRegs.push_back(SrcRegs[i]);
2787       continue;
2788     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
2789       // The entire subregister is defined by this insert, forward the new
2790       // value.
2791       DstRegs.push_back(OpReg);
2792       continue;
2793     }
2794 
2795     // OpSegStart is where this destination segment would start in OpReg if it
2796     // extended infinitely in both directions.
2797     int64_t ExtractOffset, InsertOffset;
2798     uint64_t SegSize;
2799     if (OpStart < DstStart) {
2800       InsertOffset = 0;
2801       ExtractOffset = DstStart - OpStart;
2802       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
2803     } else {
2804       InsertOffset = OpStart - DstStart;
2805       ExtractOffset = 0;
2806       SegSize =
2807         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
2808     }
2809 
2810     Register SegReg = OpReg;
2811     if (ExtractOffset != 0 || SegSize != OpSize) {
2812       // A genuine extract is needed.
2813       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
2814       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
2815     }
2816 
2817     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2818     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
2819     DstRegs.push_back(DstReg);
2820   }
2821 
2822   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
2823   Register DstReg = MI.getOperand(0).getReg();
2824   if(MRI.getType(DstReg).isVector())
2825     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2826   else
2827     MIRBuilder.buildMerge(DstReg, DstRegs);
2828   MI.eraseFromParent();
2829   return Legalized;
2830 }
2831 
2832 LegalizerHelper::LegalizeResult
2833 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
2834                                    LLT NarrowTy) {
2835   Register DstReg = MI.getOperand(0).getReg();
2836   LLT DstTy = MRI.getType(DstReg);
2837 
2838   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
2839 
2840   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
2841   SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
2842   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
2843   LLT LeftoverTy;
2844   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
2845                     Src0Regs, Src0LeftoverRegs))
2846     return UnableToLegalize;
2847 
2848   LLT Unused;
2849   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
2850                     Src1Regs, Src1LeftoverRegs))
2851     llvm_unreachable("inconsistent extractParts result");
2852 
2853   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
2854     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
2855                                         {Src0Regs[I], Src1Regs[I]});
2856     DstRegs.push_back(Inst->getOperand(0).getReg());
2857   }
2858 
2859   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
2860     auto Inst = MIRBuilder.buildInstr(
2861       MI.getOpcode(),
2862       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
2863     DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
2864   }
2865 
2866   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
2867               LeftoverTy, DstLeftoverRegs);
2868 
2869   MI.eraseFromParent();
2870   return Legalized;
2871 }
2872 
2873 LegalizerHelper::LegalizeResult
2874 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
2875                                     LLT NarrowTy) {
2876   if (TypeIdx != 0)
2877     return UnableToLegalize;
2878 
2879   Register CondReg = MI.getOperand(1).getReg();
2880   LLT CondTy = MRI.getType(CondReg);
2881   if (CondTy.isVector()) // TODO: Handle vselect
2882     return UnableToLegalize;
2883 
2884   Register DstReg = MI.getOperand(0).getReg();
2885   LLT DstTy = MRI.getType(DstReg);
2886 
2887   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
2888   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
2889   SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
2890   LLT LeftoverTy;
2891   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
2892                     Src1Regs, Src1LeftoverRegs))
2893     return UnableToLegalize;
2894 
2895   LLT Unused;
2896   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
2897                     Src2Regs, Src2LeftoverRegs))
2898     llvm_unreachable("inconsistent extractParts result");
2899 
2900   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
2901     auto Select = MIRBuilder.buildSelect(NarrowTy,
2902                                          CondReg, Src1Regs[I], Src2Regs[I]);
2903     DstRegs.push_back(Select->getOperand(0).getReg());
2904   }
2905 
2906   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
2907     auto Select = MIRBuilder.buildSelect(
2908       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
2909     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
2910   }
2911 
2912   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
2913               LeftoverTy, DstLeftoverRegs);
2914 
2915   MI.eraseFromParent();
2916   return Legalized;
2917 }
2918 
2919 LegalizerHelper::LegalizeResult
2920 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
2921   unsigned Opc = MI.getOpcode();
2922   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
2923   auto isSupported = [this](const LegalityQuery &Q) {
2924     auto QAction = LI.getAction(Q).Action;
2925     return QAction == Legal || QAction == Libcall || QAction == Custom;
2926   };
2927   switch (Opc) {
2928   default:
2929     return UnableToLegalize;
2930   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
2931     // This trivially expands to CTLZ.
2932     Observer.changingInstr(MI);
2933     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
2934     Observer.changedInstr(MI);
2935     return Legalized;
2936   }
2937   case TargetOpcode::G_CTLZ: {
2938     Register SrcReg = MI.getOperand(1).getReg();
2939     unsigned Len = Ty.getSizeInBits();
2940     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
2941       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
2942       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
2943                                              {Ty}, {SrcReg});
2944       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
2945       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
2946       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
2947                                           SrcReg, MIBZero);
2948       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
2949                              MIBCtlzZU);
2950       MI.eraseFromParent();
2951       return Legalized;
2952     }
2953     // for now, we do this:
2954     // NewLen = NextPowerOf2(Len);
2955     // x = x | (x >> 1);
2956     // x = x | (x >> 2);
2957     // ...
2958     // x = x | (x >>16);
2959     // x = x | (x >>32); // for 64-bit input
2960     // Upto NewLen/2
2961     // return Len - popcount(x);
2962     //
2963     // Ref: "Hacker's Delight" by Henry Warren
2964     Register Op = SrcReg;
2965     unsigned NewLen = PowerOf2Ceil(Len);
2966     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
2967       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
2968       auto MIBOp = MIRBuilder.buildInstr(
2969           TargetOpcode::G_OR, {Ty},
2970           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
2971                                      {Op, MIBShiftAmt})});
2972       Op = MIBOp->getOperand(0).getReg();
2973     }
2974     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
2975     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
2976                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
2977     MI.eraseFromParent();
2978     return Legalized;
2979   }
2980   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
2981     // This trivially expands to CTTZ.
2982     Observer.changingInstr(MI);
2983     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
2984     Observer.changedInstr(MI);
2985     return Legalized;
2986   }
2987   case TargetOpcode::G_CTTZ: {
2988     Register SrcReg = MI.getOperand(1).getReg();
2989     unsigned Len = Ty.getSizeInBits();
2990     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
2991       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
2992       // zero.
2993       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
2994                                              {Ty}, {SrcReg});
2995       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
2996       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
2997       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
2998                                           SrcReg, MIBZero);
2999       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3000                              MIBCttzZU);
3001       MI.eraseFromParent();
3002       return Legalized;
3003     }
3004     // for now, we use: { return popcount(~x & (x - 1)); }
3005     // unless the target has ctlz but not ctpop, in which case we use:
3006     // { return 32 - nlz(~x & (x-1)); }
3007     // Ref: "Hacker's Delight" by Henry Warren
3008     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
3009     auto MIBNot =
3010         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
3011     auto MIBTmp = MIRBuilder.buildInstr(
3012         TargetOpcode::G_AND, {Ty},
3013         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
3014                                        {SrcReg, MIBCstNeg1})});
3015     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
3016         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
3017       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
3018       MIRBuilder.buildInstr(
3019           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3020           {MIBCstLen,
3021            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
3022       MI.eraseFromParent();
3023       return Legalized;
3024     }
3025     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
3026     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3027     return Legalized;
3028   }
3029   }
3030 }
3031 
3032 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
3033 // representation.
3034 LegalizerHelper::LegalizeResult
3035 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
3036   Register Dst = MI.getOperand(0).getReg();
3037   Register Src = MI.getOperand(1).getReg();
3038   const LLT S64 = LLT::scalar(64);
3039   const LLT S32 = LLT::scalar(32);
3040   const LLT S1 = LLT::scalar(1);
3041 
3042   assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
3043 
3044   // unsigned cul2f(ulong u) {
3045   //   uint lz = clz(u);
3046   //   uint e = (u != 0) ? 127U + 63U - lz : 0;
3047   //   u = (u << lz) & 0x7fffffffffffffffUL;
3048   //   ulong t = u & 0xffffffffffUL;
3049   //   uint v = (e << 23) | (uint)(u >> 40);
3050   //   uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
3051   //   return as_float(v + r);
3052   // }
3053 
3054   auto Zero32 = MIRBuilder.buildConstant(S32, 0);
3055   auto Zero64 = MIRBuilder.buildConstant(S64, 0);
3056 
3057   auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
3058 
3059   auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
3060   auto Sub = MIRBuilder.buildSub(S32, K, LZ);
3061 
3062   auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
3063   auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
3064 
3065   auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
3066   auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
3067 
3068   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
3069 
3070   auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
3071   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
3072 
3073   auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
3074   auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
3075   auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
3076 
3077   auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
3078   auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
3079   auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
3080   auto One = MIRBuilder.buildConstant(S32, 1);
3081 
3082   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
3083   auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
3084   auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
3085   MIRBuilder.buildAdd(Dst, V, R);
3086 
3087   return Legalized;
3088 }
3089 
3090 LegalizerHelper::LegalizeResult
3091 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3092   Register Dst = MI.getOperand(0).getReg();
3093   Register Src = MI.getOperand(1).getReg();
3094   LLT DstTy = MRI.getType(Dst);
3095   LLT SrcTy = MRI.getType(Src);
3096 
3097   if (SrcTy != LLT::scalar(64))
3098     return UnableToLegalize;
3099 
3100   if (DstTy == LLT::scalar(32)) {
3101     // TODO: SelectionDAG has several alternative expansions to port which may
3102     // be more reasonble depending on the available instructions. If a target
3103     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
3104     // intermediate type, this is probably worse.
3105     return lowerU64ToF32BitOps(MI);
3106   }
3107 
3108   return UnableToLegalize;
3109 }
3110 
3111 LegalizerHelper::LegalizeResult
3112 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3113   Register Dst = MI.getOperand(0).getReg();
3114   Register Src = MI.getOperand(1).getReg();
3115   LLT DstTy = MRI.getType(Dst);
3116   LLT SrcTy = MRI.getType(Src);
3117 
3118   const LLT S64 = LLT::scalar(64);
3119   const LLT S32 = LLT::scalar(32);
3120   const LLT S1 = LLT::scalar(1);
3121 
3122   if (SrcTy != S64)
3123     return UnableToLegalize;
3124 
3125   if (DstTy == S32) {
3126     // signed cl2f(long l) {
3127     //   long s = l >> 63;
3128     //   float r = cul2f((l + s) ^ s);
3129     //   return s ? -r : r;
3130     // }
3131     Register L = Src;
3132     auto SignBit = MIRBuilder.buildConstant(S64, 63);
3133     auto S = MIRBuilder.buildAShr(S64, L, SignBit);
3134 
3135     auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
3136     auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
3137     auto R = MIRBuilder.buildUITOFP(S32, Xor);
3138 
3139     auto RNeg = MIRBuilder.buildFNeg(S32, R);
3140     auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
3141                                             MIRBuilder.buildConstant(S64, 0));
3142     MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
3143     return Legalized;
3144   }
3145 
3146   return UnableToLegalize;
3147 }
3148 
3149 static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
3150   switch (Opc) {
3151   case TargetOpcode::G_SMIN:
3152     return CmpInst::ICMP_SLT;
3153   case TargetOpcode::G_SMAX:
3154     return CmpInst::ICMP_SGT;
3155   case TargetOpcode::G_UMIN:
3156     return CmpInst::ICMP_ULT;
3157   case TargetOpcode::G_UMAX:
3158     return CmpInst::ICMP_UGT;
3159   default:
3160     llvm_unreachable("not in integer min/max");
3161   }
3162 }
3163 
3164 LegalizerHelper::LegalizeResult
3165 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3166   Register Dst = MI.getOperand(0).getReg();
3167   Register Src0 = MI.getOperand(1).getReg();
3168   Register Src1 = MI.getOperand(2).getReg();
3169 
3170   const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
3171   LLT CmpType = MRI.getType(Dst).changeElementSize(1);
3172 
3173   auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
3174   MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
3175 
3176   MI.eraseFromParent();
3177   return Legalized;
3178 }
3179