1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 /// \file This file implements the LegalizerHelper class to legalize 10 /// individual instructions and the LegalizeMachineIR wrapper pass for the 11 /// primary legalization. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" 16 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" 18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h" 19 #include "llvm/CodeGen/GlobalISel/LostDebugLocObserver.h" 20 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h" 21 #include "llvm/CodeGen/GlobalISel/Utils.h" 22 #include "llvm/CodeGen/MachineRegisterInfo.h" 23 #include "llvm/CodeGen/TargetFrameLowering.h" 24 #include "llvm/CodeGen/TargetInstrInfo.h" 25 #include "llvm/CodeGen/TargetLowering.h" 26 #include "llvm/CodeGen/TargetOpcodes.h" 27 #include "llvm/CodeGen/TargetSubtargetInfo.h" 28 #include "llvm/IR/Instructions.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/MathExtras.h" 31 #include "llvm/Support/raw_ostream.h" 32 33 #define DEBUG_TYPE "legalizer" 34 35 using namespace llvm; 36 using namespace LegalizeActions; 37 using namespace MIPatternMatch; 38 39 /// Try to break down \p OrigTy into \p NarrowTy sized pieces. 40 /// 41 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy, 42 /// with any leftover piece as type \p LeftoverTy 43 /// 44 /// Returns -1 in the first element of the pair if the breakdown is not 45 /// satisfiable. 46 static std::pair<int, int> 47 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) { 48 assert(!LeftoverTy.isValid() && "this is an out argument"); 49 50 unsigned Size = OrigTy.getSizeInBits(); 51 unsigned NarrowSize = NarrowTy.getSizeInBits(); 52 unsigned NumParts = Size / NarrowSize; 53 unsigned LeftoverSize = Size - NumParts * NarrowSize; 54 assert(Size > NarrowSize); 55 56 if (LeftoverSize == 0) 57 return {NumParts, 0}; 58 59 if (NarrowTy.isVector()) { 60 unsigned EltSize = OrigTy.getScalarSizeInBits(); 61 if (LeftoverSize % EltSize != 0) 62 return {-1, -1}; 63 LeftoverTy = LLT::scalarOrVector( 64 ElementCount::getFixed(LeftoverSize / EltSize), EltSize); 65 } else { 66 LeftoverTy = LLT::scalar(LeftoverSize); 67 } 68 69 int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits(); 70 return std::make_pair(NumParts, NumLeftover); 71 } 72 73 static Type *getFloatTypeForLLT(LLVMContext &Ctx, LLT Ty) { 74 75 if (!Ty.isScalar()) 76 return nullptr; 77 78 switch (Ty.getSizeInBits()) { 79 case 16: 80 return Type::getHalfTy(Ctx); 81 case 32: 82 return Type::getFloatTy(Ctx); 83 case 64: 84 return Type::getDoubleTy(Ctx); 85 case 80: 86 return Type::getX86_FP80Ty(Ctx); 87 case 128: 88 return Type::getFP128Ty(Ctx); 89 default: 90 return nullptr; 91 } 92 } 93 94 LegalizerHelper::LegalizerHelper(MachineFunction &MF, 95 GISelChangeObserver &Observer, 96 MachineIRBuilder &Builder) 97 : MIRBuilder(Builder), Observer(Observer), MRI(MF.getRegInfo()), 98 LI(*MF.getSubtarget().getLegalizerInfo()), 99 TLI(*MF.getSubtarget().getTargetLowering()) { } 100 101 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI, 102 GISelChangeObserver &Observer, 103 MachineIRBuilder &B) 104 : MIRBuilder(B), Observer(Observer), MRI(MF.getRegInfo()), LI(LI), 105 TLI(*MF.getSubtarget().getTargetLowering()) { } 106 107 LegalizerHelper::LegalizeResult 108 LegalizerHelper::legalizeInstrStep(MachineInstr &MI, 109 LostDebugLocObserver &LocObserver) { 110 LLVM_DEBUG(dbgs() << "Legalizing: " << MI); 111 112 MIRBuilder.setInstrAndDebugLoc(MI); 113 114 if (MI.getOpcode() == TargetOpcode::G_INTRINSIC || 115 MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS) 116 return LI.legalizeIntrinsic(*this, MI) ? Legalized : UnableToLegalize; 117 auto Step = LI.getAction(MI, MRI); 118 switch (Step.Action) { 119 case Legal: 120 LLVM_DEBUG(dbgs() << ".. Already legal\n"); 121 return AlreadyLegal; 122 case Libcall: 123 LLVM_DEBUG(dbgs() << ".. Convert to libcall\n"); 124 return libcall(MI, LocObserver); 125 case NarrowScalar: 126 LLVM_DEBUG(dbgs() << ".. Narrow scalar\n"); 127 return narrowScalar(MI, Step.TypeIdx, Step.NewType); 128 case WidenScalar: 129 LLVM_DEBUG(dbgs() << ".. Widen scalar\n"); 130 return widenScalar(MI, Step.TypeIdx, Step.NewType); 131 case Bitcast: 132 LLVM_DEBUG(dbgs() << ".. Bitcast type\n"); 133 return bitcast(MI, Step.TypeIdx, Step.NewType); 134 case Lower: 135 LLVM_DEBUG(dbgs() << ".. Lower\n"); 136 return lower(MI, Step.TypeIdx, Step.NewType); 137 case FewerElements: 138 LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n"); 139 return fewerElementsVector(MI, Step.TypeIdx, Step.NewType); 140 case MoreElements: 141 LLVM_DEBUG(dbgs() << ".. Increase number of elements\n"); 142 return moreElementsVector(MI, Step.TypeIdx, Step.NewType); 143 case Custom: 144 LLVM_DEBUG(dbgs() << ".. Custom legalization\n"); 145 return LI.legalizeCustom(*this, MI) ? Legalized : UnableToLegalize; 146 default: 147 LLVM_DEBUG(dbgs() << ".. Unable to legalize\n"); 148 return UnableToLegalize; 149 } 150 } 151 152 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts, 153 SmallVectorImpl<Register> &VRegs) { 154 for (int i = 0; i < NumParts; ++i) 155 VRegs.push_back(MRI.createGenericVirtualRegister(Ty)); 156 MIRBuilder.buildUnmerge(VRegs, Reg); 157 } 158 159 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy, 160 LLT MainTy, LLT &LeftoverTy, 161 SmallVectorImpl<Register> &VRegs, 162 SmallVectorImpl<Register> &LeftoverRegs) { 163 assert(!LeftoverTy.isValid() && "this is an out argument"); 164 165 unsigned RegSize = RegTy.getSizeInBits(); 166 unsigned MainSize = MainTy.getSizeInBits(); 167 unsigned NumParts = RegSize / MainSize; 168 unsigned LeftoverSize = RegSize - NumParts * MainSize; 169 170 // Use an unmerge when possible. 171 if (LeftoverSize == 0) { 172 for (unsigned I = 0; I < NumParts; ++I) 173 VRegs.push_back(MRI.createGenericVirtualRegister(MainTy)); 174 MIRBuilder.buildUnmerge(VRegs, Reg); 175 return true; 176 } 177 178 if (MainTy.isVector()) { 179 unsigned EltSize = MainTy.getScalarSizeInBits(); 180 if (LeftoverSize % EltSize != 0) 181 return false; 182 LeftoverTy = LLT::scalarOrVector( 183 ElementCount::getFixed(LeftoverSize / EltSize), EltSize); 184 } else { 185 LeftoverTy = LLT::scalar(LeftoverSize); 186 } 187 188 // For irregular sizes, extract the individual parts. 189 for (unsigned I = 0; I != NumParts; ++I) { 190 Register NewReg = MRI.createGenericVirtualRegister(MainTy); 191 VRegs.push_back(NewReg); 192 MIRBuilder.buildExtract(NewReg, Reg, MainSize * I); 193 } 194 195 for (unsigned Offset = MainSize * NumParts; Offset < RegSize; 196 Offset += LeftoverSize) { 197 Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy); 198 LeftoverRegs.push_back(NewReg); 199 MIRBuilder.buildExtract(NewReg, Reg, Offset); 200 } 201 202 return true; 203 } 204 205 void LegalizerHelper::insertParts(Register DstReg, 206 LLT ResultTy, LLT PartTy, 207 ArrayRef<Register> PartRegs, 208 LLT LeftoverTy, 209 ArrayRef<Register> LeftoverRegs) { 210 if (!LeftoverTy.isValid()) { 211 assert(LeftoverRegs.empty()); 212 213 if (!ResultTy.isVector()) { 214 MIRBuilder.buildMerge(DstReg, PartRegs); 215 return; 216 } 217 218 if (PartTy.isVector()) 219 MIRBuilder.buildConcatVectors(DstReg, PartRegs); 220 else 221 MIRBuilder.buildBuildVector(DstReg, PartRegs); 222 return; 223 } 224 225 SmallVector<Register> GCDRegs; 226 LLT GCDTy = getGCDType(getGCDType(ResultTy, LeftoverTy), PartTy); 227 for (auto PartReg : concat<const Register>(PartRegs, LeftoverRegs)) 228 extractGCDType(GCDRegs, GCDTy, PartReg); 229 LLT ResultLCMTy = buildLCMMergePieces(ResultTy, LeftoverTy, GCDTy, GCDRegs); 230 buildWidenedRemergeToDst(DstReg, ResultLCMTy, GCDRegs); 231 } 232 233 /// Append the result registers of G_UNMERGE_VALUES \p MI to \p Regs. 234 static void getUnmergeResults(SmallVectorImpl<Register> &Regs, 235 const MachineInstr &MI) { 236 assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES); 237 238 const int StartIdx = Regs.size(); 239 const int NumResults = MI.getNumOperands() - 1; 240 Regs.resize(Regs.size() + NumResults); 241 for (int I = 0; I != NumResults; ++I) 242 Regs[StartIdx + I] = MI.getOperand(I).getReg(); 243 } 244 245 void LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, 246 LLT GCDTy, Register SrcReg) { 247 LLT SrcTy = MRI.getType(SrcReg); 248 if (SrcTy == GCDTy) { 249 // If the source already evenly divides the result type, we don't need to do 250 // anything. 251 Parts.push_back(SrcReg); 252 } else { 253 // Need to split into common type sized pieces. 254 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 255 getUnmergeResults(Parts, *Unmerge); 256 } 257 } 258 259 LLT LegalizerHelper::extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy, 260 LLT NarrowTy, Register SrcReg) { 261 LLT SrcTy = MRI.getType(SrcReg); 262 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 263 extractGCDType(Parts, GCDTy, SrcReg); 264 return GCDTy; 265 } 266 267 LLT LegalizerHelper::buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy, 268 SmallVectorImpl<Register> &VRegs, 269 unsigned PadStrategy) { 270 LLT LCMTy = getLCMType(DstTy, NarrowTy); 271 272 int NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 273 int NumSubParts = NarrowTy.getSizeInBits() / GCDTy.getSizeInBits(); 274 int NumOrigSrc = VRegs.size(); 275 276 Register PadReg; 277 278 // Get a value we can use to pad the source value if the sources won't evenly 279 // cover the result type. 280 if (NumOrigSrc < NumParts * NumSubParts) { 281 if (PadStrategy == TargetOpcode::G_ZEXT) 282 PadReg = MIRBuilder.buildConstant(GCDTy, 0).getReg(0); 283 else if (PadStrategy == TargetOpcode::G_ANYEXT) 284 PadReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 285 else { 286 assert(PadStrategy == TargetOpcode::G_SEXT); 287 288 // Shift the sign bit of the low register through the high register. 289 auto ShiftAmt = 290 MIRBuilder.buildConstant(LLT::scalar(64), GCDTy.getSizeInBits() - 1); 291 PadReg = MIRBuilder.buildAShr(GCDTy, VRegs.back(), ShiftAmt).getReg(0); 292 } 293 } 294 295 // Registers for the final merge to be produced. 296 SmallVector<Register, 4> Remerge(NumParts); 297 298 // Registers needed for intermediate merges, which will be merged into a 299 // source for Remerge. 300 SmallVector<Register, 4> SubMerge(NumSubParts); 301 302 // Once we've fully read off the end of the original source bits, we can reuse 303 // the same high bits for remaining padding elements. 304 Register AllPadReg; 305 306 // Build merges to the LCM type to cover the original result type. 307 for (int I = 0; I != NumParts; ++I) { 308 bool AllMergePartsArePadding = true; 309 310 // Build the requested merges to the requested type. 311 for (int J = 0; J != NumSubParts; ++J) { 312 int Idx = I * NumSubParts + J; 313 if (Idx >= NumOrigSrc) { 314 SubMerge[J] = PadReg; 315 continue; 316 } 317 318 SubMerge[J] = VRegs[Idx]; 319 320 // There are meaningful bits here we can't reuse later. 321 AllMergePartsArePadding = false; 322 } 323 324 // If we've filled up a complete piece with padding bits, we can directly 325 // emit the natural sized constant if applicable, rather than a merge of 326 // smaller constants. 327 if (AllMergePartsArePadding && !AllPadReg) { 328 if (PadStrategy == TargetOpcode::G_ANYEXT) 329 AllPadReg = MIRBuilder.buildUndef(NarrowTy).getReg(0); 330 else if (PadStrategy == TargetOpcode::G_ZEXT) 331 AllPadReg = MIRBuilder.buildConstant(NarrowTy, 0).getReg(0); 332 333 // If this is a sign extension, we can't materialize a trivial constant 334 // with the right type and have to produce a merge. 335 } 336 337 if (AllPadReg) { 338 // Avoid creating additional instructions if we're just adding additional 339 // copies of padding bits. 340 Remerge[I] = AllPadReg; 341 continue; 342 } 343 344 if (NumSubParts == 1) 345 Remerge[I] = SubMerge[0]; 346 else 347 Remerge[I] = MIRBuilder.buildMerge(NarrowTy, SubMerge).getReg(0); 348 349 // In the sign extend padding case, re-use the first all-signbit merge. 350 if (AllMergePartsArePadding && !AllPadReg) 351 AllPadReg = Remerge[I]; 352 } 353 354 VRegs = std::move(Remerge); 355 return LCMTy; 356 } 357 358 void LegalizerHelper::buildWidenedRemergeToDst(Register DstReg, LLT LCMTy, 359 ArrayRef<Register> RemergeRegs) { 360 LLT DstTy = MRI.getType(DstReg); 361 362 // Create the merge to the widened source, and extract the relevant bits into 363 // the result. 364 365 if (DstTy == LCMTy) { 366 MIRBuilder.buildMerge(DstReg, RemergeRegs); 367 return; 368 } 369 370 auto Remerge = MIRBuilder.buildMerge(LCMTy, RemergeRegs); 371 if (DstTy.isScalar() && LCMTy.isScalar()) { 372 MIRBuilder.buildTrunc(DstReg, Remerge); 373 return; 374 } 375 376 if (LCMTy.isVector()) { 377 unsigned NumDefs = LCMTy.getSizeInBits() / DstTy.getSizeInBits(); 378 SmallVector<Register, 8> UnmergeDefs(NumDefs); 379 UnmergeDefs[0] = DstReg; 380 for (unsigned I = 1; I != NumDefs; ++I) 381 UnmergeDefs[I] = MRI.createGenericVirtualRegister(DstTy); 382 383 MIRBuilder.buildUnmerge(UnmergeDefs, 384 MIRBuilder.buildMerge(LCMTy, RemergeRegs)); 385 return; 386 } 387 388 llvm_unreachable("unhandled case"); 389 } 390 391 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) { 392 #define RTLIBCASE_INT(LibcallPrefix) \ 393 do { \ 394 switch (Size) { \ 395 case 32: \ 396 return RTLIB::LibcallPrefix##32; \ 397 case 64: \ 398 return RTLIB::LibcallPrefix##64; \ 399 case 128: \ 400 return RTLIB::LibcallPrefix##128; \ 401 default: \ 402 llvm_unreachable("unexpected size"); \ 403 } \ 404 } while (0) 405 406 #define RTLIBCASE(LibcallPrefix) \ 407 do { \ 408 switch (Size) { \ 409 case 32: \ 410 return RTLIB::LibcallPrefix##32; \ 411 case 64: \ 412 return RTLIB::LibcallPrefix##64; \ 413 case 80: \ 414 return RTLIB::LibcallPrefix##80; \ 415 case 128: \ 416 return RTLIB::LibcallPrefix##128; \ 417 default: \ 418 llvm_unreachable("unexpected size"); \ 419 } \ 420 } while (0) 421 422 switch (Opcode) { 423 case TargetOpcode::G_SDIV: 424 RTLIBCASE_INT(SDIV_I); 425 case TargetOpcode::G_UDIV: 426 RTLIBCASE_INT(UDIV_I); 427 case TargetOpcode::G_SREM: 428 RTLIBCASE_INT(SREM_I); 429 case TargetOpcode::G_UREM: 430 RTLIBCASE_INT(UREM_I); 431 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 432 RTLIBCASE_INT(CTLZ_I); 433 case TargetOpcode::G_FADD: 434 RTLIBCASE(ADD_F); 435 case TargetOpcode::G_FSUB: 436 RTLIBCASE(SUB_F); 437 case TargetOpcode::G_FMUL: 438 RTLIBCASE(MUL_F); 439 case TargetOpcode::G_FDIV: 440 RTLIBCASE(DIV_F); 441 case TargetOpcode::G_FEXP: 442 RTLIBCASE(EXP_F); 443 case TargetOpcode::G_FEXP2: 444 RTLIBCASE(EXP2_F); 445 case TargetOpcode::G_FREM: 446 RTLIBCASE(REM_F); 447 case TargetOpcode::G_FPOW: 448 RTLIBCASE(POW_F); 449 case TargetOpcode::G_FMA: 450 RTLIBCASE(FMA_F); 451 case TargetOpcode::G_FSIN: 452 RTLIBCASE(SIN_F); 453 case TargetOpcode::G_FCOS: 454 RTLIBCASE(COS_F); 455 case TargetOpcode::G_FLOG10: 456 RTLIBCASE(LOG10_F); 457 case TargetOpcode::G_FLOG: 458 RTLIBCASE(LOG_F); 459 case TargetOpcode::G_FLOG2: 460 RTLIBCASE(LOG2_F); 461 case TargetOpcode::G_FCEIL: 462 RTLIBCASE(CEIL_F); 463 case TargetOpcode::G_FFLOOR: 464 RTLIBCASE(FLOOR_F); 465 case TargetOpcode::G_FMINNUM: 466 RTLIBCASE(FMIN_F); 467 case TargetOpcode::G_FMAXNUM: 468 RTLIBCASE(FMAX_F); 469 case TargetOpcode::G_FSQRT: 470 RTLIBCASE(SQRT_F); 471 case TargetOpcode::G_FRINT: 472 RTLIBCASE(RINT_F); 473 case TargetOpcode::G_FNEARBYINT: 474 RTLIBCASE(NEARBYINT_F); 475 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 476 RTLIBCASE(ROUNDEVEN_F); 477 } 478 llvm_unreachable("Unknown libcall function"); 479 } 480 481 /// True if an instruction is in tail position in its caller. Intended for 482 /// legalizing libcalls as tail calls when possible. 483 static bool isLibCallInTailPosition(const TargetInstrInfo &TII, 484 MachineInstr &MI) { 485 MachineBasicBlock &MBB = *MI.getParent(); 486 const Function &F = MBB.getParent()->getFunction(); 487 488 // Conservatively require the attributes of the call to match those of 489 // the return. Ignore NoAlias and NonNull because they don't affect the 490 // call sequence. 491 AttributeList CallerAttrs = F.getAttributes(); 492 if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex) 493 .removeAttribute(Attribute::NoAlias) 494 .removeAttribute(Attribute::NonNull) 495 .hasAttributes()) 496 return false; 497 498 // It's not safe to eliminate the sign / zero extension of the return value. 499 if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) || 500 CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt)) 501 return false; 502 503 // Only tail call if the following instruction is a standard return. 504 auto Next = next_nodbg(MI.getIterator(), MBB.instr_end()); 505 if (Next == MBB.instr_end() || TII.isTailCall(*Next) || !Next->isReturn()) 506 return false; 507 508 return true; 509 } 510 511 LegalizerHelper::LegalizeResult 512 llvm::createLibcall(MachineIRBuilder &MIRBuilder, const char *Name, 513 const CallLowering::ArgInfo &Result, 514 ArrayRef<CallLowering::ArgInfo> Args, 515 const CallingConv::ID CC) { 516 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 517 518 CallLowering::CallLoweringInfo Info; 519 Info.CallConv = CC; 520 Info.Callee = MachineOperand::CreateES(Name); 521 Info.OrigRet = Result; 522 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 523 if (!CLI.lowerCall(MIRBuilder, Info)) 524 return LegalizerHelper::UnableToLegalize; 525 526 return LegalizerHelper::Legalized; 527 } 528 529 LegalizerHelper::LegalizeResult 530 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall, 531 const CallLowering::ArgInfo &Result, 532 ArrayRef<CallLowering::ArgInfo> Args) { 533 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 534 const char *Name = TLI.getLibcallName(Libcall); 535 const CallingConv::ID CC = TLI.getLibcallCallingConv(Libcall); 536 return createLibcall(MIRBuilder, Name, Result, Args, CC); 537 } 538 539 // Useful for libcalls where all operands have the same type. 540 static LegalizerHelper::LegalizeResult 541 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size, 542 Type *OpType) { 543 auto Libcall = getRTLibDesc(MI.getOpcode(), Size); 544 545 // FIXME: What does the original arg index mean here? 546 SmallVector<CallLowering::ArgInfo, 3> Args; 547 for (unsigned i = 1; i < MI.getNumOperands(); i++) 548 Args.push_back({MI.getOperand(i).getReg(), OpType, 0}); 549 return createLibcall(MIRBuilder, Libcall, 550 {MI.getOperand(0).getReg(), OpType, 0}, Args); 551 } 552 553 LegalizerHelper::LegalizeResult 554 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI, 555 MachineInstr &MI, LostDebugLocObserver &LocObserver) { 556 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 557 558 SmallVector<CallLowering::ArgInfo, 3> Args; 559 // Add all the args, except for the last which is an imm denoting 'tail'. 560 for (unsigned i = 0; i < MI.getNumOperands() - 1; ++i) { 561 Register Reg = MI.getOperand(i).getReg(); 562 563 // Need derive an IR type for call lowering. 564 LLT OpLLT = MRI.getType(Reg); 565 Type *OpTy = nullptr; 566 if (OpLLT.isPointer()) 567 OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace()); 568 else 569 OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits()); 570 Args.push_back({Reg, OpTy, 0}); 571 } 572 573 auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering(); 574 auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering(); 575 RTLIB::Libcall RTLibcall; 576 unsigned Opc = MI.getOpcode(); 577 switch (Opc) { 578 case TargetOpcode::G_BZERO: 579 RTLibcall = RTLIB::BZERO; 580 break; 581 case TargetOpcode::G_MEMCPY: 582 RTLibcall = RTLIB::MEMCPY; 583 break; 584 case TargetOpcode::G_MEMMOVE: 585 RTLibcall = RTLIB::MEMMOVE; 586 break; 587 case TargetOpcode::G_MEMSET: 588 RTLibcall = RTLIB::MEMSET; 589 break; 590 default: 591 return LegalizerHelper::UnableToLegalize; 592 } 593 const char *Name = TLI.getLibcallName(RTLibcall); 594 595 // Unsupported libcall on the target. 596 if (!Name) { 597 LLVM_DEBUG(dbgs() << ".. .. Could not find libcall name for " 598 << MIRBuilder.getTII().getName(Opc) << "\n"); 599 return LegalizerHelper::UnableToLegalize; 600 } 601 602 CallLowering::CallLoweringInfo Info; 603 Info.CallConv = TLI.getLibcallCallingConv(RTLibcall); 604 Info.Callee = MachineOperand::CreateES(Name); 605 Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx), 0); 606 Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() && 607 isLibCallInTailPosition(MIRBuilder.getTII(), MI); 608 609 std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs)); 610 if (!CLI.lowerCall(MIRBuilder, Info)) 611 return LegalizerHelper::UnableToLegalize; 612 613 614 if (Info.LoweredTailCall) { 615 assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?"); 616 617 // Check debug locations before removing the return. 618 LocObserver.checkpoint(true); 619 620 // We must have a return following the call (or debug insts) to get past 621 // isLibCallInTailPosition. 622 do { 623 MachineInstr *Next = MI.getNextNode(); 624 assert(Next && (Next->isReturn() || Next->isDebugInstr()) && 625 "Expected instr following MI to be return or debug inst?"); 626 // We lowered a tail call, so the call is now the return from the block. 627 // Delete the old return. 628 Next->eraseFromParent(); 629 } while (MI.getNextNode()); 630 631 // We expect to lose the debug location from the return. 632 LocObserver.checkpoint(false); 633 } 634 635 return LegalizerHelper::Legalized; 636 } 637 638 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType, 639 Type *FromType) { 640 auto ToMVT = MVT::getVT(ToType); 641 auto FromMVT = MVT::getVT(FromType); 642 643 switch (Opcode) { 644 case TargetOpcode::G_FPEXT: 645 return RTLIB::getFPEXT(FromMVT, ToMVT); 646 case TargetOpcode::G_FPTRUNC: 647 return RTLIB::getFPROUND(FromMVT, ToMVT); 648 case TargetOpcode::G_FPTOSI: 649 return RTLIB::getFPTOSINT(FromMVT, ToMVT); 650 case TargetOpcode::G_FPTOUI: 651 return RTLIB::getFPTOUINT(FromMVT, ToMVT); 652 case TargetOpcode::G_SITOFP: 653 return RTLIB::getSINTTOFP(FromMVT, ToMVT); 654 case TargetOpcode::G_UITOFP: 655 return RTLIB::getUINTTOFP(FromMVT, ToMVT); 656 } 657 llvm_unreachable("Unsupported libcall function"); 658 } 659 660 static LegalizerHelper::LegalizeResult 661 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType, 662 Type *FromType) { 663 RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType); 664 return createLibcall(MIRBuilder, Libcall, 665 {MI.getOperand(0).getReg(), ToType, 0}, 666 {{MI.getOperand(1).getReg(), FromType, 0}}); 667 } 668 669 LegalizerHelper::LegalizeResult 670 LegalizerHelper::libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver) { 671 LLT LLTy = MRI.getType(MI.getOperand(0).getReg()); 672 unsigned Size = LLTy.getSizeInBits(); 673 auto &Ctx = MIRBuilder.getMF().getFunction().getContext(); 674 675 switch (MI.getOpcode()) { 676 default: 677 return UnableToLegalize; 678 case TargetOpcode::G_SDIV: 679 case TargetOpcode::G_UDIV: 680 case TargetOpcode::G_SREM: 681 case TargetOpcode::G_UREM: 682 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 683 Type *HLTy = IntegerType::get(Ctx, Size); 684 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 685 if (Status != Legalized) 686 return Status; 687 break; 688 } 689 case TargetOpcode::G_FADD: 690 case TargetOpcode::G_FSUB: 691 case TargetOpcode::G_FMUL: 692 case TargetOpcode::G_FDIV: 693 case TargetOpcode::G_FMA: 694 case TargetOpcode::G_FPOW: 695 case TargetOpcode::G_FREM: 696 case TargetOpcode::G_FCOS: 697 case TargetOpcode::G_FSIN: 698 case TargetOpcode::G_FLOG10: 699 case TargetOpcode::G_FLOG: 700 case TargetOpcode::G_FLOG2: 701 case TargetOpcode::G_FEXP: 702 case TargetOpcode::G_FEXP2: 703 case TargetOpcode::G_FCEIL: 704 case TargetOpcode::G_FFLOOR: 705 case TargetOpcode::G_FMINNUM: 706 case TargetOpcode::G_FMAXNUM: 707 case TargetOpcode::G_FSQRT: 708 case TargetOpcode::G_FRINT: 709 case TargetOpcode::G_FNEARBYINT: 710 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 711 Type *HLTy = getFloatTypeForLLT(Ctx, LLTy); 712 if (!HLTy || (Size != 32 && Size != 64 && Size != 80 && Size != 128)) { 713 LLVM_DEBUG(dbgs() << "No libcall available for type " << LLTy << ".\n"); 714 return UnableToLegalize; 715 } 716 auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy); 717 if (Status != Legalized) 718 return Status; 719 break; 720 } 721 case TargetOpcode::G_FPEXT: 722 case TargetOpcode::G_FPTRUNC: { 723 Type *FromTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(1).getReg())); 724 Type *ToTy = getFloatTypeForLLT(Ctx, MRI.getType(MI.getOperand(0).getReg())); 725 if (!FromTy || !ToTy) 726 return UnableToLegalize; 727 LegalizeResult Status = conversionLibcall(MI, MIRBuilder, ToTy, FromTy ); 728 if (Status != Legalized) 729 return Status; 730 break; 731 } 732 case TargetOpcode::G_FPTOSI: 733 case TargetOpcode::G_FPTOUI: { 734 // FIXME: Support other types 735 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 736 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 737 if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64)) 738 return UnableToLegalize; 739 LegalizeResult Status = conversionLibcall( 740 MI, MIRBuilder, 741 ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx), 742 FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx)); 743 if (Status != Legalized) 744 return Status; 745 break; 746 } 747 case TargetOpcode::G_SITOFP: 748 case TargetOpcode::G_UITOFP: { 749 // FIXME: Support other types 750 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 751 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 752 if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64)) 753 return UnableToLegalize; 754 LegalizeResult Status = conversionLibcall( 755 MI, MIRBuilder, 756 ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx), 757 FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx)); 758 if (Status != Legalized) 759 return Status; 760 break; 761 } 762 case TargetOpcode::G_BZERO: 763 case TargetOpcode::G_MEMCPY: 764 case TargetOpcode::G_MEMMOVE: 765 case TargetOpcode::G_MEMSET: { 766 LegalizeResult Result = 767 createMemLibcall(MIRBuilder, *MIRBuilder.getMRI(), MI, LocObserver); 768 if (Result != Legalized) 769 return Result; 770 MI.eraseFromParent(); 771 return Result; 772 } 773 } 774 775 MI.eraseFromParent(); 776 return Legalized; 777 } 778 779 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI, 780 unsigned TypeIdx, 781 LLT NarrowTy) { 782 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(); 783 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 784 785 switch (MI.getOpcode()) { 786 default: 787 return UnableToLegalize; 788 case TargetOpcode::G_IMPLICIT_DEF: { 789 Register DstReg = MI.getOperand(0).getReg(); 790 LLT DstTy = MRI.getType(DstReg); 791 792 // If SizeOp0 is not an exact multiple of NarrowSize, emit 793 // G_ANYEXT(G_IMPLICIT_DEF). Cast result to vector if needed. 794 // FIXME: Although this would also be legal for the general case, it causes 795 // a lot of regressions in the emitted code (superfluous COPYs, artifact 796 // combines not being hit). This seems to be a problem related to the 797 // artifact combiner. 798 if (SizeOp0 % NarrowSize != 0) { 799 LLT ImplicitTy = NarrowTy; 800 if (DstTy.isVector()) 801 ImplicitTy = LLT::vector(DstTy.getElementCount(), ImplicitTy); 802 803 Register ImplicitReg = MIRBuilder.buildUndef(ImplicitTy).getReg(0); 804 MIRBuilder.buildAnyExt(DstReg, ImplicitReg); 805 806 MI.eraseFromParent(); 807 return Legalized; 808 } 809 810 int NumParts = SizeOp0 / NarrowSize; 811 812 SmallVector<Register, 2> DstRegs; 813 for (int i = 0; i < NumParts; ++i) 814 DstRegs.push_back(MIRBuilder.buildUndef(NarrowTy).getReg(0)); 815 816 if (DstTy.isVector()) 817 MIRBuilder.buildBuildVector(DstReg, DstRegs); 818 else 819 MIRBuilder.buildMerge(DstReg, DstRegs); 820 MI.eraseFromParent(); 821 return Legalized; 822 } 823 case TargetOpcode::G_CONSTANT: { 824 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 825 const APInt &Val = MI.getOperand(1).getCImm()->getValue(); 826 unsigned TotalSize = Ty.getSizeInBits(); 827 unsigned NarrowSize = NarrowTy.getSizeInBits(); 828 int NumParts = TotalSize / NarrowSize; 829 830 SmallVector<Register, 4> PartRegs; 831 for (int I = 0; I != NumParts; ++I) { 832 unsigned Offset = I * NarrowSize; 833 auto K = MIRBuilder.buildConstant(NarrowTy, 834 Val.lshr(Offset).trunc(NarrowSize)); 835 PartRegs.push_back(K.getReg(0)); 836 } 837 838 LLT LeftoverTy; 839 unsigned LeftoverBits = TotalSize - NumParts * NarrowSize; 840 SmallVector<Register, 1> LeftoverRegs; 841 if (LeftoverBits != 0) { 842 LeftoverTy = LLT::scalar(LeftoverBits); 843 auto K = MIRBuilder.buildConstant( 844 LeftoverTy, 845 Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits)); 846 LeftoverRegs.push_back(K.getReg(0)); 847 } 848 849 insertParts(MI.getOperand(0).getReg(), 850 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs); 851 852 MI.eraseFromParent(); 853 return Legalized; 854 } 855 case TargetOpcode::G_SEXT: 856 case TargetOpcode::G_ZEXT: 857 case TargetOpcode::G_ANYEXT: 858 return narrowScalarExt(MI, TypeIdx, NarrowTy); 859 case TargetOpcode::G_TRUNC: { 860 if (TypeIdx != 1) 861 return UnableToLegalize; 862 863 uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 864 if (NarrowTy.getSizeInBits() * 2 != SizeOp1) { 865 LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n"); 866 return UnableToLegalize; 867 } 868 869 auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 870 MIRBuilder.buildCopy(MI.getOperand(0), Unmerge.getReg(0)); 871 MI.eraseFromParent(); 872 return Legalized; 873 } 874 875 case TargetOpcode::G_FREEZE: 876 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 877 case TargetOpcode::G_ADD: 878 case TargetOpcode::G_SUB: 879 case TargetOpcode::G_SADDO: 880 case TargetOpcode::G_SSUBO: 881 case TargetOpcode::G_SADDE: 882 case TargetOpcode::G_SSUBE: 883 case TargetOpcode::G_UADDO: 884 case TargetOpcode::G_USUBO: 885 case TargetOpcode::G_UADDE: 886 case TargetOpcode::G_USUBE: 887 return narrowScalarAddSub(MI, TypeIdx, NarrowTy); 888 case TargetOpcode::G_MUL: 889 case TargetOpcode::G_UMULH: 890 return narrowScalarMul(MI, NarrowTy); 891 case TargetOpcode::G_EXTRACT: 892 return narrowScalarExtract(MI, TypeIdx, NarrowTy); 893 case TargetOpcode::G_INSERT: 894 return narrowScalarInsert(MI, TypeIdx, NarrowTy); 895 case TargetOpcode::G_LOAD: { 896 auto &LoadMI = cast<GLoad>(MI); 897 Register DstReg = LoadMI.getDstReg(); 898 LLT DstTy = MRI.getType(DstReg); 899 if (DstTy.isVector()) 900 return UnableToLegalize; 901 902 if (8 * LoadMI.getMemSize() != DstTy.getSizeInBits()) { 903 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 904 MIRBuilder.buildLoad(TmpReg, LoadMI.getPointerReg(), LoadMI.getMMO()); 905 MIRBuilder.buildAnyExt(DstReg, TmpReg); 906 LoadMI.eraseFromParent(); 907 return Legalized; 908 } 909 910 return reduceLoadStoreWidth(LoadMI, TypeIdx, NarrowTy); 911 } 912 case TargetOpcode::G_ZEXTLOAD: 913 case TargetOpcode::G_SEXTLOAD: { 914 auto &LoadMI = cast<GExtLoad>(MI); 915 Register DstReg = LoadMI.getDstReg(); 916 Register PtrReg = LoadMI.getPointerReg(); 917 918 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 919 auto &MMO = LoadMI.getMMO(); 920 unsigned MemSize = MMO.getSizeInBits(); 921 922 if (MemSize == NarrowSize) { 923 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); 924 } else if (MemSize < NarrowSize) { 925 MIRBuilder.buildLoadInstr(LoadMI.getOpcode(), TmpReg, PtrReg, MMO); 926 } else if (MemSize > NarrowSize) { 927 // FIXME: Need to split the load. 928 return UnableToLegalize; 929 } 930 931 if (isa<GZExtLoad>(LoadMI)) 932 MIRBuilder.buildZExt(DstReg, TmpReg); 933 else 934 MIRBuilder.buildSExt(DstReg, TmpReg); 935 936 LoadMI.eraseFromParent(); 937 return Legalized; 938 } 939 case TargetOpcode::G_STORE: { 940 auto &StoreMI = cast<GStore>(MI); 941 942 Register SrcReg = StoreMI.getValueReg(); 943 LLT SrcTy = MRI.getType(SrcReg); 944 if (SrcTy.isVector()) 945 return UnableToLegalize; 946 947 int NumParts = SizeOp0 / NarrowSize; 948 unsigned HandledSize = NumParts * NarrowTy.getSizeInBits(); 949 unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize; 950 if (SrcTy.isVector() && LeftoverBits != 0) 951 return UnableToLegalize; 952 953 if (8 * StoreMI.getMemSize() != SrcTy.getSizeInBits()) { 954 Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy); 955 MIRBuilder.buildTrunc(TmpReg, SrcReg); 956 MIRBuilder.buildStore(TmpReg, StoreMI.getPointerReg(), StoreMI.getMMO()); 957 StoreMI.eraseFromParent(); 958 return Legalized; 959 } 960 961 return reduceLoadStoreWidth(StoreMI, 0, NarrowTy); 962 } 963 case TargetOpcode::G_SELECT: 964 return narrowScalarSelect(MI, TypeIdx, NarrowTy); 965 case TargetOpcode::G_AND: 966 case TargetOpcode::G_OR: 967 case TargetOpcode::G_XOR: { 968 // Legalize bitwise operation: 969 // A = BinOp<Ty> B, C 970 // into: 971 // B1, ..., BN = G_UNMERGE_VALUES B 972 // C1, ..., CN = G_UNMERGE_VALUES C 973 // A1 = BinOp<Ty/N> B1, C2 974 // ... 975 // AN = BinOp<Ty/N> BN, CN 976 // A = G_MERGE_VALUES A1, ..., AN 977 return narrowScalarBasic(MI, TypeIdx, NarrowTy); 978 } 979 case TargetOpcode::G_SHL: 980 case TargetOpcode::G_LSHR: 981 case TargetOpcode::G_ASHR: 982 return narrowScalarShift(MI, TypeIdx, NarrowTy); 983 case TargetOpcode::G_CTLZ: 984 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 985 case TargetOpcode::G_CTTZ: 986 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 987 case TargetOpcode::G_CTPOP: 988 if (TypeIdx == 1) 989 switch (MI.getOpcode()) { 990 case TargetOpcode::G_CTLZ: 991 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 992 return narrowScalarCTLZ(MI, TypeIdx, NarrowTy); 993 case TargetOpcode::G_CTTZ: 994 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 995 return narrowScalarCTTZ(MI, TypeIdx, NarrowTy); 996 case TargetOpcode::G_CTPOP: 997 return narrowScalarCTPOP(MI, TypeIdx, NarrowTy); 998 default: 999 return UnableToLegalize; 1000 } 1001 1002 Observer.changingInstr(MI); 1003 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1004 Observer.changedInstr(MI); 1005 return Legalized; 1006 case TargetOpcode::G_INTTOPTR: 1007 if (TypeIdx != 1) 1008 return UnableToLegalize; 1009 1010 Observer.changingInstr(MI); 1011 narrowScalarSrc(MI, NarrowTy, 1); 1012 Observer.changedInstr(MI); 1013 return Legalized; 1014 case TargetOpcode::G_PTRTOINT: 1015 if (TypeIdx != 0) 1016 return UnableToLegalize; 1017 1018 Observer.changingInstr(MI); 1019 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT); 1020 Observer.changedInstr(MI); 1021 return Legalized; 1022 case TargetOpcode::G_PHI: { 1023 // FIXME: add support for when SizeOp0 isn't an exact multiple of 1024 // NarrowSize. 1025 if (SizeOp0 % NarrowSize != 0) 1026 return UnableToLegalize; 1027 1028 unsigned NumParts = SizeOp0 / NarrowSize; 1029 SmallVector<Register, 2> DstRegs(NumParts); 1030 SmallVector<SmallVector<Register, 2>, 2> SrcRegs(MI.getNumOperands() / 2); 1031 Observer.changingInstr(MI); 1032 for (unsigned i = 1; i < MI.getNumOperands(); i += 2) { 1033 MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB(); 1034 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 1035 extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts, 1036 SrcRegs[i / 2]); 1037 } 1038 MachineBasicBlock &MBB = *MI.getParent(); 1039 MIRBuilder.setInsertPt(MBB, MI); 1040 for (unsigned i = 0; i < NumParts; ++i) { 1041 DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy); 1042 MachineInstrBuilder MIB = 1043 MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]); 1044 for (unsigned j = 1; j < MI.getNumOperands(); j += 2) 1045 MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1)); 1046 } 1047 MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI()); 1048 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1049 Observer.changedInstr(MI); 1050 MI.eraseFromParent(); 1051 return Legalized; 1052 } 1053 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 1054 case TargetOpcode::G_INSERT_VECTOR_ELT: { 1055 if (TypeIdx != 2) 1056 return UnableToLegalize; 1057 1058 int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3; 1059 Observer.changingInstr(MI); 1060 narrowScalarSrc(MI, NarrowTy, OpIdx); 1061 Observer.changedInstr(MI); 1062 return Legalized; 1063 } 1064 case TargetOpcode::G_ICMP: { 1065 Register LHS = MI.getOperand(2).getReg(); 1066 LLT SrcTy = MRI.getType(LHS); 1067 uint64_t SrcSize = SrcTy.getSizeInBits(); 1068 CmpInst::Predicate Pred = 1069 static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 1070 1071 // TODO: Handle the non-equality case for weird sizes. 1072 if (NarrowSize * 2 != SrcSize && !ICmpInst::isEquality(Pred)) 1073 return UnableToLegalize; 1074 1075 LLT LeftoverTy; // Example: s88 -> s64 (NarrowTy) + s24 (leftover) 1076 SmallVector<Register, 4> LHSPartRegs, LHSLeftoverRegs; 1077 if (!extractParts(LHS, SrcTy, NarrowTy, LeftoverTy, LHSPartRegs, 1078 LHSLeftoverRegs)) 1079 return UnableToLegalize; 1080 1081 LLT Unused; // Matches LeftoverTy; G_ICMP LHS and RHS are the same type. 1082 SmallVector<Register, 4> RHSPartRegs, RHSLeftoverRegs; 1083 if (!extractParts(MI.getOperand(3).getReg(), SrcTy, NarrowTy, Unused, 1084 RHSPartRegs, RHSLeftoverRegs)) 1085 return UnableToLegalize; 1086 1087 // We now have the LHS and RHS of the compare split into narrow-type 1088 // registers, plus potentially some leftover type. 1089 Register Dst = MI.getOperand(0).getReg(); 1090 LLT ResTy = MRI.getType(Dst); 1091 if (ICmpInst::isEquality(Pred)) { 1092 // For each part on the LHS and RHS, keep track of the result of XOR-ing 1093 // them together. For each equal part, the result should be all 0s. For 1094 // each non-equal part, we'll get at least one 1. 1095 auto Zero = MIRBuilder.buildConstant(NarrowTy, 0); 1096 SmallVector<Register, 4> Xors; 1097 for (auto LHSAndRHS : zip(LHSPartRegs, RHSPartRegs)) { 1098 auto LHS = std::get<0>(LHSAndRHS); 1099 auto RHS = std::get<1>(LHSAndRHS); 1100 auto Xor = MIRBuilder.buildXor(NarrowTy, LHS, RHS).getReg(0); 1101 Xors.push_back(Xor); 1102 } 1103 1104 // Build a G_XOR for each leftover register. Each G_XOR must be widened 1105 // to the desired narrow type so that we can OR them together later. 1106 SmallVector<Register, 4> WidenedXors; 1107 for (auto LHSAndRHS : zip(LHSLeftoverRegs, RHSLeftoverRegs)) { 1108 auto LHS = std::get<0>(LHSAndRHS); 1109 auto RHS = std::get<1>(LHSAndRHS); 1110 auto Xor = MIRBuilder.buildXor(LeftoverTy, LHS, RHS).getReg(0); 1111 LLT GCDTy = extractGCDType(WidenedXors, NarrowTy, LeftoverTy, Xor); 1112 buildLCMMergePieces(LeftoverTy, NarrowTy, GCDTy, WidenedXors, 1113 /* PadStrategy = */ TargetOpcode::G_ZEXT); 1114 Xors.insert(Xors.end(), WidenedXors.begin(), WidenedXors.end()); 1115 } 1116 1117 // Now, for each part we broke up, we know if they are equal/not equal 1118 // based off the G_XOR. We can OR these all together and compare against 1119 // 0 to get the result. 1120 assert(Xors.size() >= 2 && "Should have gotten at least two Xors?"); 1121 auto Or = MIRBuilder.buildOr(NarrowTy, Xors[0], Xors[1]); 1122 for (unsigned I = 2, E = Xors.size(); I < E; ++I) 1123 Or = MIRBuilder.buildOr(NarrowTy, Or, Xors[I]); 1124 MIRBuilder.buildICmp(Pred, Dst, Or, Zero); 1125 } else { 1126 // TODO: Handle non-power-of-two types. 1127 assert(LHSPartRegs.size() == 2 && "Expected exactly 2 LHS part regs?"); 1128 assert(RHSPartRegs.size() == 2 && "Expected exactly 2 RHS part regs?"); 1129 Register LHSL = LHSPartRegs[0]; 1130 Register LHSH = LHSPartRegs[1]; 1131 Register RHSL = RHSPartRegs[0]; 1132 Register RHSH = RHSPartRegs[1]; 1133 MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH); 1134 MachineInstrBuilder CmpHEQ = 1135 MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH); 1136 MachineInstrBuilder CmpLU = MIRBuilder.buildICmp( 1137 ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL); 1138 MIRBuilder.buildSelect(Dst, CmpHEQ, CmpLU, CmpH); 1139 } 1140 MI.eraseFromParent(); 1141 return Legalized; 1142 } 1143 case TargetOpcode::G_SEXT_INREG: { 1144 if (TypeIdx != 0) 1145 return UnableToLegalize; 1146 1147 int64_t SizeInBits = MI.getOperand(2).getImm(); 1148 1149 // So long as the new type has more bits than the bits we're extending we 1150 // don't need to break it apart. 1151 if (NarrowTy.getScalarSizeInBits() >= SizeInBits) { 1152 Observer.changingInstr(MI); 1153 // We don't lose any non-extension bits by truncating the src and 1154 // sign-extending the dst. 1155 MachineOperand &MO1 = MI.getOperand(1); 1156 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1); 1157 MO1.setReg(TruncMIB.getReg(0)); 1158 1159 MachineOperand &MO2 = MI.getOperand(0); 1160 Register DstExt = MRI.createGenericVirtualRegister(NarrowTy); 1161 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1162 MIRBuilder.buildSExt(MO2, DstExt); 1163 MO2.setReg(DstExt); 1164 Observer.changedInstr(MI); 1165 return Legalized; 1166 } 1167 1168 // Break it apart. Components below the extension point are unmodified. The 1169 // component containing the extension point becomes a narrower SEXT_INREG. 1170 // Components above it are ashr'd from the component containing the 1171 // extension point. 1172 if (SizeOp0 % NarrowSize != 0) 1173 return UnableToLegalize; 1174 int NumParts = SizeOp0 / NarrowSize; 1175 1176 // List the registers where the destination will be scattered. 1177 SmallVector<Register, 2> DstRegs; 1178 // List the registers where the source will be split. 1179 SmallVector<Register, 2> SrcRegs; 1180 1181 // Create all the temporary registers. 1182 for (int i = 0; i < NumParts; ++i) { 1183 Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy); 1184 1185 SrcRegs.push_back(SrcReg); 1186 } 1187 1188 // Explode the big arguments into smaller chunks. 1189 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1)); 1190 1191 Register AshrCstReg = 1192 MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1) 1193 .getReg(0); 1194 Register FullExtensionReg = 0; 1195 Register PartialExtensionReg = 0; 1196 1197 // Do the operation on each small part. 1198 for (int i = 0; i < NumParts; ++i) { 1199 if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits) 1200 DstRegs.push_back(SrcRegs[i]); 1201 else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) { 1202 assert(PartialExtensionReg && 1203 "Expected to visit partial extension before full"); 1204 if (FullExtensionReg) { 1205 DstRegs.push_back(FullExtensionReg); 1206 continue; 1207 } 1208 DstRegs.push_back( 1209 MIRBuilder.buildAShr(NarrowTy, PartialExtensionReg, AshrCstReg) 1210 .getReg(0)); 1211 FullExtensionReg = DstRegs.back(); 1212 } else { 1213 DstRegs.push_back( 1214 MIRBuilder 1215 .buildInstr( 1216 TargetOpcode::G_SEXT_INREG, {NarrowTy}, 1217 {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()}) 1218 .getReg(0)); 1219 PartialExtensionReg = DstRegs.back(); 1220 } 1221 } 1222 1223 // Gather the destination registers into the final destination. 1224 Register DstReg = MI.getOperand(0).getReg(); 1225 MIRBuilder.buildMerge(DstReg, DstRegs); 1226 MI.eraseFromParent(); 1227 return Legalized; 1228 } 1229 case TargetOpcode::G_BSWAP: 1230 case TargetOpcode::G_BITREVERSE: { 1231 if (SizeOp0 % NarrowSize != 0) 1232 return UnableToLegalize; 1233 1234 Observer.changingInstr(MI); 1235 SmallVector<Register, 2> SrcRegs, DstRegs; 1236 unsigned NumParts = SizeOp0 / NarrowSize; 1237 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 1238 1239 for (unsigned i = 0; i < NumParts; ++i) { 1240 auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 1241 {SrcRegs[NumParts - 1 - i]}); 1242 DstRegs.push_back(DstPart.getReg(0)); 1243 } 1244 1245 MIRBuilder.buildMerge(MI.getOperand(0), DstRegs); 1246 1247 Observer.changedInstr(MI); 1248 MI.eraseFromParent(); 1249 return Legalized; 1250 } 1251 case TargetOpcode::G_PTR_ADD: 1252 case TargetOpcode::G_PTRMASK: { 1253 if (TypeIdx != 1) 1254 return UnableToLegalize; 1255 Observer.changingInstr(MI); 1256 narrowScalarSrc(MI, NarrowTy, 2); 1257 Observer.changedInstr(MI); 1258 return Legalized; 1259 } 1260 case TargetOpcode::G_FPTOUI: 1261 case TargetOpcode::G_FPTOSI: 1262 return narrowScalarFPTOI(MI, TypeIdx, NarrowTy); 1263 case TargetOpcode::G_FPEXT: 1264 if (TypeIdx != 0) 1265 return UnableToLegalize; 1266 Observer.changingInstr(MI); 1267 narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_FPEXT); 1268 Observer.changedInstr(MI); 1269 return Legalized; 1270 } 1271 } 1272 1273 Register LegalizerHelper::coerceToScalar(Register Val) { 1274 LLT Ty = MRI.getType(Val); 1275 if (Ty.isScalar()) 1276 return Val; 1277 1278 const DataLayout &DL = MIRBuilder.getDataLayout(); 1279 LLT NewTy = LLT::scalar(Ty.getSizeInBits()); 1280 if (Ty.isPointer()) { 1281 if (DL.isNonIntegralAddressSpace(Ty.getAddressSpace())) 1282 return Register(); 1283 return MIRBuilder.buildPtrToInt(NewTy, Val).getReg(0); 1284 } 1285 1286 Register NewVal = Val; 1287 1288 assert(Ty.isVector()); 1289 LLT EltTy = Ty.getElementType(); 1290 if (EltTy.isPointer()) 1291 NewVal = MIRBuilder.buildPtrToInt(NewTy, NewVal).getReg(0); 1292 return MIRBuilder.buildBitcast(NewTy, NewVal).getReg(0); 1293 } 1294 1295 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy, 1296 unsigned OpIdx, unsigned ExtOpcode) { 1297 MachineOperand &MO = MI.getOperand(OpIdx); 1298 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO}); 1299 MO.setReg(ExtB.getReg(0)); 1300 } 1301 1302 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, 1303 unsigned OpIdx) { 1304 MachineOperand &MO = MI.getOperand(OpIdx); 1305 auto ExtB = MIRBuilder.buildTrunc(NarrowTy, MO); 1306 MO.setReg(ExtB.getReg(0)); 1307 } 1308 1309 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy, 1310 unsigned OpIdx, unsigned TruncOpcode) { 1311 MachineOperand &MO = MI.getOperand(OpIdx); 1312 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 1313 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1314 MIRBuilder.buildInstr(TruncOpcode, {MO}, {DstExt}); 1315 MO.setReg(DstExt); 1316 } 1317 1318 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy, 1319 unsigned OpIdx, unsigned ExtOpcode) { 1320 MachineOperand &MO = MI.getOperand(OpIdx); 1321 Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy); 1322 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1323 MIRBuilder.buildInstr(ExtOpcode, {MO}, {DstTrunc}); 1324 MO.setReg(DstTrunc); 1325 } 1326 1327 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy, 1328 unsigned OpIdx) { 1329 MachineOperand &MO = MI.getOperand(OpIdx); 1330 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1331 MO.setReg(widenWithUnmerge(WideTy, MO.getReg())); 1332 } 1333 1334 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, 1335 unsigned OpIdx) { 1336 MachineOperand &MO = MI.getOperand(OpIdx); 1337 1338 LLT OldTy = MRI.getType(MO.getReg()); 1339 unsigned OldElts = OldTy.getNumElements(); 1340 unsigned NewElts = MoreTy.getNumElements(); 1341 1342 unsigned NumParts = NewElts / OldElts; 1343 1344 // Use concat_vectors if the result is a multiple of the number of elements. 1345 if (NumParts * OldElts == NewElts) { 1346 SmallVector<Register, 8> Parts; 1347 Parts.push_back(MO.getReg()); 1348 1349 Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0); 1350 for (unsigned I = 1; I != NumParts; ++I) 1351 Parts.push_back(ImpDef); 1352 1353 auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts); 1354 MO.setReg(Concat.getReg(0)); 1355 return; 1356 } 1357 1358 Register MoreReg = MRI.createGenericVirtualRegister(MoreTy); 1359 Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0); 1360 MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0); 1361 MO.setReg(MoreReg); 1362 } 1363 1364 void LegalizerHelper::bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1365 MachineOperand &Op = MI.getOperand(OpIdx); 1366 Op.setReg(MIRBuilder.buildBitcast(CastTy, Op).getReg(0)); 1367 } 1368 1369 void LegalizerHelper::bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx) { 1370 MachineOperand &MO = MI.getOperand(OpIdx); 1371 Register CastDst = MRI.createGenericVirtualRegister(CastTy); 1372 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 1373 MIRBuilder.buildBitcast(MO, CastDst); 1374 MO.setReg(CastDst); 1375 } 1376 1377 LegalizerHelper::LegalizeResult 1378 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, 1379 LLT WideTy) { 1380 if (TypeIdx != 1) 1381 return UnableToLegalize; 1382 1383 Register DstReg = MI.getOperand(0).getReg(); 1384 LLT DstTy = MRI.getType(DstReg); 1385 if (DstTy.isVector()) 1386 return UnableToLegalize; 1387 1388 Register Src1 = MI.getOperand(1).getReg(); 1389 LLT SrcTy = MRI.getType(Src1); 1390 const int DstSize = DstTy.getSizeInBits(); 1391 const int SrcSize = SrcTy.getSizeInBits(); 1392 const int WideSize = WideTy.getSizeInBits(); 1393 const int NumMerge = (DstSize + WideSize - 1) / WideSize; 1394 1395 unsigned NumOps = MI.getNumOperands(); 1396 unsigned NumSrc = MI.getNumOperands() - 1; 1397 unsigned PartSize = DstTy.getSizeInBits() / NumSrc; 1398 1399 if (WideSize >= DstSize) { 1400 // Directly pack the bits in the target type. 1401 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0); 1402 1403 for (unsigned I = 2; I != NumOps; ++I) { 1404 const unsigned Offset = (I - 1) * PartSize; 1405 1406 Register SrcReg = MI.getOperand(I).getReg(); 1407 assert(MRI.getType(SrcReg) == LLT::scalar(PartSize)); 1408 1409 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 1410 1411 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 1412 MRI.createGenericVirtualRegister(WideTy); 1413 1414 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 1415 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 1416 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 1417 ResultReg = NextResult; 1418 } 1419 1420 if (WideSize > DstSize) 1421 MIRBuilder.buildTrunc(DstReg, ResultReg); 1422 else if (DstTy.isPointer()) 1423 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 1424 1425 MI.eraseFromParent(); 1426 return Legalized; 1427 } 1428 1429 // Unmerge the original values to the GCD type, and recombine to the next 1430 // multiple greater than the original type. 1431 // 1432 // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6 1433 // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0 1434 // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1 1435 // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2 1436 // %10:_(s6) = G_MERGE_VALUES %4, %5, %6 1437 // %11:_(s6) = G_MERGE_VALUES %7, %8, %9 1438 // %12:_(s12) = G_MERGE_VALUES %10, %11 1439 // 1440 // Padding with undef if necessary: 1441 // 1442 // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6 1443 // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0 1444 // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1 1445 // %7:_(s2) = G_IMPLICIT_DEF 1446 // %8:_(s6) = G_MERGE_VALUES %3, %4, %5 1447 // %9:_(s6) = G_MERGE_VALUES %6, %7, %7 1448 // %10:_(s12) = G_MERGE_VALUES %8, %9 1449 1450 const int GCD = greatestCommonDivisor(SrcSize, WideSize); 1451 LLT GCDTy = LLT::scalar(GCD); 1452 1453 SmallVector<Register, 8> Parts; 1454 SmallVector<Register, 8> NewMergeRegs; 1455 SmallVector<Register, 8> Unmerges; 1456 LLT WideDstTy = LLT::scalar(NumMerge * WideSize); 1457 1458 // Decompose the original operands if they don't evenly divide. 1459 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) { 1460 Register SrcReg = MI.getOperand(I).getReg(); 1461 if (GCD == SrcSize) { 1462 Unmerges.push_back(SrcReg); 1463 } else { 1464 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 1465 for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J) 1466 Unmerges.push_back(Unmerge.getReg(J)); 1467 } 1468 } 1469 1470 // Pad with undef to the next size that is a multiple of the requested size. 1471 if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) { 1472 Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0); 1473 for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I) 1474 Unmerges.push_back(UndefReg); 1475 } 1476 1477 const int PartsPerGCD = WideSize / GCD; 1478 1479 // Build merges of each piece. 1480 ArrayRef<Register> Slicer(Unmerges); 1481 for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) { 1482 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD)); 1483 NewMergeRegs.push_back(Merge.getReg(0)); 1484 } 1485 1486 // A truncate may be necessary if the requested type doesn't evenly divide the 1487 // original result type. 1488 if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) { 1489 MIRBuilder.buildMerge(DstReg, NewMergeRegs); 1490 } else { 1491 auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs); 1492 MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0)); 1493 } 1494 1495 MI.eraseFromParent(); 1496 return Legalized; 1497 } 1498 1499 Register LegalizerHelper::widenWithUnmerge(LLT WideTy, Register OrigReg) { 1500 Register WideReg = MRI.createGenericVirtualRegister(WideTy); 1501 LLT OrigTy = MRI.getType(OrigReg); 1502 LLT LCMTy = getLCMType(WideTy, OrigTy); 1503 1504 const int NumMergeParts = LCMTy.getSizeInBits() / WideTy.getSizeInBits(); 1505 const int NumUnmergeParts = LCMTy.getSizeInBits() / OrigTy.getSizeInBits(); 1506 1507 Register UnmergeSrc = WideReg; 1508 1509 // Create a merge to the LCM type, padding with undef 1510 // %0:_(<3 x s32>) = G_FOO => <4 x s32> 1511 // => 1512 // %1:_(<4 x s32>) = G_FOO 1513 // %2:_(<4 x s32>) = G_IMPLICIT_DEF 1514 // %3:_(<12 x s32>) = G_CONCAT_VECTORS %1, %2, %2 1515 // %0:_(<3 x s32>), %4:_, %5:_, %6:_ = G_UNMERGE_VALUES %3 1516 if (NumMergeParts > 1) { 1517 Register Undef = MIRBuilder.buildUndef(WideTy).getReg(0); 1518 SmallVector<Register, 8> MergeParts(NumMergeParts, Undef); 1519 MergeParts[0] = WideReg; 1520 UnmergeSrc = MIRBuilder.buildMerge(LCMTy, MergeParts).getReg(0); 1521 } 1522 1523 // Unmerge to the original register and pad with dead defs. 1524 SmallVector<Register, 8> UnmergeResults(NumUnmergeParts); 1525 UnmergeResults[0] = OrigReg; 1526 for (int I = 1; I != NumUnmergeParts; ++I) 1527 UnmergeResults[I] = MRI.createGenericVirtualRegister(OrigTy); 1528 1529 MIRBuilder.buildUnmerge(UnmergeResults, UnmergeSrc); 1530 return WideReg; 1531 } 1532 1533 LegalizerHelper::LegalizeResult 1534 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, 1535 LLT WideTy) { 1536 if (TypeIdx != 0) 1537 return UnableToLegalize; 1538 1539 int NumDst = MI.getNumOperands() - 1; 1540 Register SrcReg = MI.getOperand(NumDst).getReg(); 1541 LLT SrcTy = MRI.getType(SrcReg); 1542 if (SrcTy.isVector()) 1543 return UnableToLegalize; 1544 1545 Register Dst0Reg = MI.getOperand(0).getReg(); 1546 LLT DstTy = MRI.getType(Dst0Reg); 1547 if (!DstTy.isScalar()) 1548 return UnableToLegalize; 1549 1550 if (WideTy.getSizeInBits() >= SrcTy.getSizeInBits()) { 1551 if (SrcTy.isPointer()) { 1552 const DataLayout &DL = MIRBuilder.getDataLayout(); 1553 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) { 1554 LLVM_DEBUG( 1555 dbgs() << "Not casting non-integral address space integer\n"); 1556 return UnableToLegalize; 1557 } 1558 1559 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 1560 SrcReg = MIRBuilder.buildPtrToInt(SrcTy, SrcReg).getReg(0); 1561 } 1562 1563 // Widen SrcTy to WideTy. This does not affect the result, but since the 1564 // user requested this size, it is probably better handled than SrcTy and 1565 // should reduce the total number of legalization artifacts 1566 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1567 SrcTy = WideTy; 1568 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); 1569 } 1570 1571 // Theres no unmerge type to target. Directly extract the bits from the 1572 // source type 1573 unsigned DstSize = DstTy.getSizeInBits(); 1574 1575 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 1576 for (int I = 1; I != NumDst; ++I) { 1577 auto ShiftAmt = MIRBuilder.buildConstant(SrcTy, DstSize * I); 1578 auto Shr = MIRBuilder.buildLShr(SrcTy, SrcReg, ShiftAmt); 1579 MIRBuilder.buildTrunc(MI.getOperand(I), Shr); 1580 } 1581 1582 MI.eraseFromParent(); 1583 return Legalized; 1584 } 1585 1586 // Extend the source to a wider type. 1587 LLT LCMTy = getLCMType(SrcTy, WideTy); 1588 1589 Register WideSrc = SrcReg; 1590 if (LCMTy.getSizeInBits() != SrcTy.getSizeInBits()) { 1591 // TODO: If this is an integral address space, cast to integer and anyext. 1592 if (SrcTy.isPointer()) { 1593 LLVM_DEBUG(dbgs() << "Widening pointer source types not implemented\n"); 1594 return UnableToLegalize; 1595 } 1596 1597 WideSrc = MIRBuilder.buildAnyExt(LCMTy, WideSrc).getReg(0); 1598 } 1599 1600 auto Unmerge = MIRBuilder.buildUnmerge(WideTy, WideSrc); 1601 1602 // Create a sequence of unmerges and merges to the original results. Since we 1603 // may have widened the source, we will need to pad the results with dead defs 1604 // to cover the source register. 1605 // e.g. widen s48 to s64: 1606 // %1:_(s48), %2:_(s48) = G_UNMERGE_VALUES %0:_(s96) 1607 // 1608 // => 1609 // %4:_(s192) = G_ANYEXT %0:_(s96) 1610 // %5:_(s64), %6, %7 = G_UNMERGE_VALUES %4 ; Requested unmerge 1611 // ; unpack to GCD type, with extra dead defs 1612 // %8:_(s16), %9, %10, %11 = G_UNMERGE_VALUES %5:_(s64) 1613 // %12:_(s16), %13, dead %14, dead %15 = G_UNMERGE_VALUES %6:_(s64) 1614 // dead %16:_(s16), dead %17, dead %18, dead %18 = G_UNMERGE_VALUES %7:_(s64) 1615 // %1:_(s48) = G_MERGE_VALUES %8:_(s16), %9, %10 ; Remerge to destination 1616 // %2:_(s48) = G_MERGE_VALUES %11:_(s16), %12, %13 ; Remerge to destination 1617 const LLT GCDTy = getGCDType(WideTy, DstTy); 1618 const int NumUnmerge = Unmerge->getNumOperands() - 1; 1619 const int PartsPerRemerge = DstTy.getSizeInBits() / GCDTy.getSizeInBits(); 1620 1621 // Directly unmerge to the destination without going through a GCD type 1622 // if possible 1623 if (PartsPerRemerge == 1) { 1624 const int PartsPerUnmerge = WideTy.getSizeInBits() / DstTy.getSizeInBits(); 1625 1626 for (int I = 0; I != NumUnmerge; ++I) { 1627 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 1628 1629 for (int J = 0; J != PartsPerUnmerge; ++J) { 1630 int Idx = I * PartsPerUnmerge + J; 1631 if (Idx < NumDst) 1632 MIB.addDef(MI.getOperand(Idx).getReg()); 1633 else { 1634 // Create dead def for excess components. 1635 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 1636 } 1637 } 1638 1639 MIB.addUse(Unmerge.getReg(I)); 1640 } 1641 } else { 1642 SmallVector<Register, 16> Parts; 1643 for (int J = 0; J != NumUnmerge; ++J) 1644 extractGCDType(Parts, GCDTy, Unmerge.getReg(J)); 1645 1646 SmallVector<Register, 8> RemergeParts; 1647 for (int I = 0; I != NumDst; ++I) { 1648 for (int J = 0; J < PartsPerRemerge; ++J) { 1649 const int Idx = I * PartsPerRemerge + J; 1650 RemergeParts.emplace_back(Parts[Idx]); 1651 } 1652 1653 MIRBuilder.buildMerge(MI.getOperand(I).getReg(), RemergeParts); 1654 RemergeParts.clear(); 1655 } 1656 } 1657 1658 MI.eraseFromParent(); 1659 return Legalized; 1660 } 1661 1662 LegalizerHelper::LegalizeResult 1663 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, 1664 LLT WideTy) { 1665 Register DstReg = MI.getOperand(0).getReg(); 1666 Register SrcReg = MI.getOperand(1).getReg(); 1667 LLT SrcTy = MRI.getType(SrcReg); 1668 1669 LLT DstTy = MRI.getType(DstReg); 1670 unsigned Offset = MI.getOperand(2).getImm(); 1671 1672 if (TypeIdx == 0) { 1673 if (SrcTy.isVector() || DstTy.isVector()) 1674 return UnableToLegalize; 1675 1676 SrcOp Src(SrcReg); 1677 if (SrcTy.isPointer()) { 1678 // Extracts from pointers can be handled only if they are really just 1679 // simple integers. 1680 const DataLayout &DL = MIRBuilder.getDataLayout(); 1681 if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace())) 1682 return UnableToLegalize; 1683 1684 LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits()); 1685 Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src); 1686 SrcTy = SrcAsIntTy; 1687 } 1688 1689 if (DstTy.isPointer()) 1690 return UnableToLegalize; 1691 1692 if (Offset == 0) { 1693 // Avoid a shift in the degenerate case. 1694 MIRBuilder.buildTrunc(DstReg, 1695 MIRBuilder.buildAnyExtOrTrunc(WideTy, Src)); 1696 MI.eraseFromParent(); 1697 return Legalized; 1698 } 1699 1700 // Do a shift in the source type. 1701 LLT ShiftTy = SrcTy; 1702 if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) { 1703 Src = MIRBuilder.buildAnyExt(WideTy, Src); 1704 ShiftTy = WideTy; 1705 } 1706 1707 auto LShr = MIRBuilder.buildLShr( 1708 ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset)); 1709 MIRBuilder.buildTrunc(DstReg, LShr); 1710 MI.eraseFromParent(); 1711 return Legalized; 1712 } 1713 1714 if (SrcTy.isScalar()) { 1715 Observer.changingInstr(MI); 1716 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1717 Observer.changedInstr(MI); 1718 return Legalized; 1719 } 1720 1721 if (!SrcTy.isVector()) 1722 return UnableToLegalize; 1723 1724 if (DstTy != SrcTy.getElementType()) 1725 return UnableToLegalize; 1726 1727 if (Offset % SrcTy.getScalarSizeInBits() != 0) 1728 return UnableToLegalize; 1729 1730 Observer.changingInstr(MI); 1731 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1732 1733 MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) * 1734 Offset); 1735 widenScalarDst(MI, WideTy.getScalarType(), 0); 1736 Observer.changedInstr(MI); 1737 return Legalized; 1738 } 1739 1740 LegalizerHelper::LegalizeResult 1741 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, 1742 LLT WideTy) { 1743 if (TypeIdx != 0 || WideTy.isVector()) 1744 return UnableToLegalize; 1745 Observer.changingInstr(MI); 1746 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 1747 widenScalarDst(MI, WideTy); 1748 Observer.changedInstr(MI); 1749 return Legalized; 1750 } 1751 1752 LegalizerHelper::LegalizeResult 1753 LegalizerHelper::widenScalarAddSubOverflow(MachineInstr &MI, unsigned TypeIdx, 1754 LLT WideTy) { 1755 if (TypeIdx == 1) 1756 return UnableToLegalize; // TODO 1757 1758 unsigned Opcode; 1759 unsigned ExtOpcode; 1760 Optional<Register> CarryIn = None; 1761 switch (MI.getOpcode()) { 1762 default: 1763 llvm_unreachable("Unexpected opcode!"); 1764 case TargetOpcode::G_SADDO: 1765 Opcode = TargetOpcode::G_ADD; 1766 ExtOpcode = TargetOpcode::G_SEXT; 1767 break; 1768 case TargetOpcode::G_SSUBO: 1769 Opcode = TargetOpcode::G_SUB; 1770 ExtOpcode = TargetOpcode::G_SEXT; 1771 break; 1772 case TargetOpcode::G_UADDO: 1773 Opcode = TargetOpcode::G_ADD; 1774 ExtOpcode = TargetOpcode::G_ZEXT; 1775 break; 1776 case TargetOpcode::G_USUBO: 1777 Opcode = TargetOpcode::G_SUB; 1778 ExtOpcode = TargetOpcode::G_ZEXT; 1779 break; 1780 case TargetOpcode::G_SADDE: 1781 Opcode = TargetOpcode::G_UADDE; 1782 ExtOpcode = TargetOpcode::G_SEXT; 1783 CarryIn = MI.getOperand(4).getReg(); 1784 break; 1785 case TargetOpcode::G_SSUBE: 1786 Opcode = TargetOpcode::G_USUBE; 1787 ExtOpcode = TargetOpcode::G_SEXT; 1788 CarryIn = MI.getOperand(4).getReg(); 1789 break; 1790 case TargetOpcode::G_UADDE: 1791 Opcode = TargetOpcode::G_UADDE; 1792 ExtOpcode = TargetOpcode::G_ZEXT; 1793 CarryIn = MI.getOperand(4).getReg(); 1794 break; 1795 case TargetOpcode::G_USUBE: 1796 Opcode = TargetOpcode::G_USUBE; 1797 ExtOpcode = TargetOpcode::G_ZEXT; 1798 CarryIn = MI.getOperand(4).getReg(); 1799 break; 1800 } 1801 1802 auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)}); 1803 auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)}); 1804 // Do the arithmetic in the larger type. 1805 Register NewOp; 1806 if (CarryIn) { 1807 LLT CarryOutTy = MRI.getType(MI.getOperand(1).getReg()); 1808 NewOp = MIRBuilder 1809 .buildInstr(Opcode, {WideTy, CarryOutTy}, 1810 {LHSExt, RHSExt, *CarryIn}) 1811 .getReg(0); 1812 } else { 1813 NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt}).getReg(0); 1814 } 1815 LLT OrigTy = MRI.getType(MI.getOperand(0).getReg()); 1816 auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp); 1817 auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp}); 1818 // There is no overflow if the ExtOp is the same as NewOp. 1819 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp); 1820 // Now trunc the NewOp to the original result. 1821 MIRBuilder.buildTrunc(MI.getOperand(0), NewOp); 1822 MI.eraseFromParent(); 1823 return Legalized; 1824 } 1825 1826 LegalizerHelper::LegalizeResult 1827 LegalizerHelper::widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx, 1828 LLT WideTy) { 1829 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SADDSAT || 1830 MI.getOpcode() == TargetOpcode::G_SSUBSAT || 1831 MI.getOpcode() == TargetOpcode::G_SSHLSAT; 1832 bool IsShift = MI.getOpcode() == TargetOpcode::G_SSHLSAT || 1833 MI.getOpcode() == TargetOpcode::G_USHLSAT; 1834 // We can convert this to: 1835 // 1. Any extend iN to iM 1836 // 2. SHL by M-N 1837 // 3. [US][ADD|SUB|SHL]SAT 1838 // 4. L/ASHR by M-N 1839 // 1840 // It may be more efficient to lower this to a min and a max operation in 1841 // the higher precision arithmetic if the promoted operation isn't legal, 1842 // but this decision is up to the target's lowering request. 1843 Register DstReg = MI.getOperand(0).getReg(); 1844 1845 unsigned NewBits = WideTy.getScalarSizeInBits(); 1846 unsigned SHLAmount = NewBits - MRI.getType(DstReg).getScalarSizeInBits(); 1847 1848 // Shifts must zero-extend the RHS to preserve the unsigned quantity, and 1849 // must not left shift the RHS to preserve the shift amount. 1850 auto LHS = MIRBuilder.buildAnyExt(WideTy, MI.getOperand(1)); 1851 auto RHS = IsShift ? MIRBuilder.buildZExt(WideTy, MI.getOperand(2)) 1852 : MIRBuilder.buildAnyExt(WideTy, MI.getOperand(2)); 1853 auto ShiftK = MIRBuilder.buildConstant(WideTy, SHLAmount); 1854 auto ShiftL = MIRBuilder.buildShl(WideTy, LHS, ShiftK); 1855 auto ShiftR = IsShift ? RHS : MIRBuilder.buildShl(WideTy, RHS, ShiftK); 1856 1857 auto WideInst = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, 1858 {ShiftL, ShiftR}, MI.getFlags()); 1859 1860 // Use a shift that will preserve the number of sign bits when the trunc is 1861 // folded away. 1862 auto Result = IsSigned ? MIRBuilder.buildAShr(WideTy, WideInst, ShiftK) 1863 : MIRBuilder.buildLShr(WideTy, WideInst, ShiftK); 1864 1865 MIRBuilder.buildTrunc(DstReg, Result); 1866 MI.eraseFromParent(); 1867 return Legalized; 1868 } 1869 1870 LegalizerHelper::LegalizeResult 1871 LegalizerHelper::widenScalarMulo(MachineInstr &MI, unsigned TypeIdx, 1872 LLT WideTy) { 1873 if (TypeIdx == 1) 1874 return UnableToLegalize; 1875 1876 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULO; 1877 Register Result = MI.getOperand(0).getReg(); 1878 Register OriginalOverflow = MI.getOperand(1).getReg(); 1879 Register LHS = MI.getOperand(2).getReg(); 1880 Register RHS = MI.getOperand(3).getReg(); 1881 LLT SrcTy = MRI.getType(LHS); 1882 LLT OverflowTy = MRI.getType(OriginalOverflow); 1883 unsigned SrcBitWidth = SrcTy.getScalarSizeInBits(); 1884 1885 // To determine if the result overflowed in the larger type, we extend the 1886 // input to the larger type, do the multiply (checking if it overflows), 1887 // then also check the high bits of the result to see if overflow happened 1888 // there. 1889 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 1890 auto LeftOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {LHS}); 1891 auto RightOperand = MIRBuilder.buildInstr(ExtOp, {WideTy}, {RHS}); 1892 1893 auto Mulo = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy, OverflowTy}, 1894 {LeftOperand, RightOperand}); 1895 auto Mul = Mulo->getOperand(0); 1896 MIRBuilder.buildTrunc(Result, Mul); 1897 1898 MachineInstrBuilder ExtResult; 1899 // Overflow occurred if it occurred in the larger type, or if the high part 1900 // of the result does not zero/sign-extend the low part. Check this second 1901 // possibility first. 1902 if (IsSigned) { 1903 // For signed, overflow occurred when the high part does not sign-extend 1904 // the low part. 1905 ExtResult = MIRBuilder.buildSExtInReg(WideTy, Mul, SrcBitWidth); 1906 } else { 1907 // Unsigned overflow occurred when the high part does not zero-extend the 1908 // low part. 1909 ExtResult = MIRBuilder.buildZExtInReg(WideTy, Mul, SrcBitWidth); 1910 } 1911 1912 // Multiplication cannot overflow if the WideTy is >= 2 * original width, 1913 // so we don't need to check the overflow result of larger type Mulo. 1914 if (WideTy.getScalarSizeInBits() < 2 * SrcBitWidth) { 1915 auto Overflow = 1916 MIRBuilder.buildICmp(CmpInst::ICMP_NE, OverflowTy, Mul, ExtResult); 1917 // Finally check if the multiplication in the larger type itself overflowed. 1918 MIRBuilder.buildOr(OriginalOverflow, Mulo->getOperand(1), Overflow); 1919 } else { 1920 MIRBuilder.buildICmp(CmpInst::ICMP_NE, OriginalOverflow, Mul, ExtResult); 1921 } 1922 MI.eraseFromParent(); 1923 return Legalized; 1924 } 1925 1926 LegalizerHelper::LegalizeResult 1927 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) { 1928 switch (MI.getOpcode()) { 1929 default: 1930 return UnableToLegalize; 1931 case TargetOpcode::G_EXTRACT: 1932 return widenScalarExtract(MI, TypeIdx, WideTy); 1933 case TargetOpcode::G_INSERT: 1934 return widenScalarInsert(MI, TypeIdx, WideTy); 1935 case TargetOpcode::G_MERGE_VALUES: 1936 return widenScalarMergeValues(MI, TypeIdx, WideTy); 1937 case TargetOpcode::G_UNMERGE_VALUES: 1938 return widenScalarUnmergeValues(MI, TypeIdx, WideTy); 1939 case TargetOpcode::G_SADDO: 1940 case TargetOpcode::G_SSUBO: 1941 case TargetOpcode::G_UADDO: 1942 case TargetOpcode::G_USUBO: 1943 case TargetOpcode::G_SADDE: 1944 case TargetOpcode::G_SSUBE: 1945 case TargetOpcode::G_UADDE: 1946 case TargetOpcode::G_USUBE: 1947 return widenScalarAddSubOverflow(MI, TypeIdx, WideTy); 1948 case TargetOpcode::G_UMULO: 1949 case TargetOpcode::G_SMULO: 1950 return widenScalarMulo(MI, TypeIdx, WideTy); 1951 case TargetOpcode::G_SADDSAT: 1952 case TargetOpcode::G_SSUBSAT: 1953 case TargetOpcode::G_SSHLSAT: 1954 case TargetOpcode::G_UADDSAT: 1955 case TargetOpcode::G_USUBSAT: 1956 case TargetOpcode::G_USHLSAT: 1957 return widenScalarAddSubShlSat(MI, TypeIdx, WideTy); 1958 case TargetOpcode::G_CTTZ: 1959 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 1960 case TargetOpcode::G_CTLZ: 1961 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 1962 case TargetOpcode::G_CTPOP: { 1963 if (TypeIdx == 0) { 1964 Observer.changingInstr(MI); 1965 widenScalarDst(MI, WideTy, 0); 1966 Observer.changedInstr(MI); 1967 return Legalized; 1968 } 1969 1970 Register SrcReg = MI.getOperand(1).getReg(); 1971 1972 // First ZEXT the input. 1973 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg); 1974 LLT CurTy = MRI.getType(SrcReg); 1975 if (MI.getOpcode() == TargetOpcode::G_CTTZ) { 1976 // The count is the same in the larger type except if the original 1977 // value was zero. This can be handled by setting the bit just off 1978 // the top of the original type. 1979 auto TopBit = 1980 APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits()); 1981 MIBSrc = MIRBuilder.buildOr( 1982 WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit)); 1983 } 1984 1985 // Perform the operation at the larger size. 1986 auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc}); 1987 // This is already the correct result for CTPOP and CTTZs 1988 if (MI.getOpcode() == TargetOpcode::G_CTLZ || 1989 MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) { 1990 // The correct result is NewOp - (Difference in widety and current ty). 1991 unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits(); 1992 MIBNewOp = MIRBuilder.buildSub( 1993 WideTy, MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)); 1994 } 1995 1996 MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp); 1997 MI.eraseFromParent(); 1998 return Legalized; 1999 } 2000 case TargetOpcode::G_BSWAP: { 2001 Observer.changingInstr(MI); 2002 Register DstReg = MI.getOperand(0).getReg(); 2003 2004 Register ShrReg = MRI.createGenericVirtualRegister(WideTy); 2005 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 2006 Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy); 2007 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2008 2009 MI.getOperand(0).setReg(DstExt); 2010 2011 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 2012 2013 LLT Ty = MRI.getType(DstReg); 2014 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 2015 MIRBuilder.buildConstant(ShiftAmtReg, DiffBits); 2016 MIRBuilder.buildLShr(ShrReg, DstExt, ShiftAmtReg); 2017 2018 MIRBuilder.buildTrunc(DstReg, ShrReg); 2019 Observer.changedInstr(MI); 2020 return Legalized; 2021 } 2022 case TargetOpcode::G_BITREVERSE: { 2023 Observer.changingInstr(MI); 2024 2025 Register DstReg = MI.getOperand(0).getReg(); 2026 LLT Ty = MRI.getType(DstReg); 2027 unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits(); 2028 2029 Register DstExt = MRI.createGenericVirtualRegister(WideTy); 2030 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2031 MI.getOperand(0).setReg(DstExt); 2032 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 2033 2034 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits); 2035 auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt); 2036 MIRBuilder.buildTrunc(DstReg, Shift); 2037 Observer.changedInstr(MI); 2038 return Legalized; 2039 } 2040 case TargetOpcode::G_FREEZE: 2041 Observer.changingInstr(MI); 2042 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2043 widenScalarDst(MI, WideTy); 2044 Observer.changedInstr(MI); 2045 return Legalized; 2046 2047 case TargetOpcode::G_ABS: 2048 Observer.changingInstr(MI); 2049 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2050 widenScalarDst(MI, WideTy); 2051 Observer.changedInstr(MI); 2052 return Legalized; 2053 2054 case TargetOpcode::G_ADD: 2055 case TargetOpcode::G_AND: 2056 case TargetOpcode::G_MUL: 2057 case TargetOpcode::G_OR: 2058 case TargetOpcode::G_XOR: 2059 case TargetOpcode::G_SUB: 2060 // Perform operation at larger width (any extension is fines here, high bits 2061 // don't affect the result) and then truncate the result back to the 2062 // original type. 2063 Observer.changingInstr(MI); 2064 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2065 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2066 widenScalarDst(MI, WideTy); 2067 Observer.changedInstr(MI); 2068 return Legalized; 2069 2070 case TargetOpcode::G_SBFX: 2071 case TargetOpcode::G_UBFX: 2072 Observer.changingInstr(MI); 2073 2074 if (TypeIdx == 0) { 2075 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2076 widenScalarDst(MI, WideTy); 2077 } else { 2078 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2079 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ZEXT); 2080 } 2081 2082 Observer.changedInstr(MI); 2083 return Legalized; 2084 2085 case TargetOpcode::G_SHL: 2086 Observer.changingInstr(MI); 2087 2088 if (TypeIdx == 0) { 2089 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2090 widenScalarDst(MI, WideTy); 2091 } else { 2092 assert(TypeIdx == 1); 2093 // The "number of bits to shift" operand must preserve its value as an 2094 // unsigned integer: 2095 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2096 } 2097 2098 Observer.changedInstr(MI); 2099 return Legalized; 2100 2101 case TargetOpcode::G_SDIV: 2102 case TargetOpcode::G_SREM: 2103 case TargetOpcode::G_SMIN: 2104 case TargetOpcode::G_SMAX: 2105 Observer.changingInstr(MI); 2106 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2107 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2108 widenScalarDst(MI, WideTy); 2109 Observer.changedInstr(MI); 2110 return Legalized; 2111 2112 case TargetOpcode::G_SDIVREM: 2113 Observer.changingInstr(MI); 2114 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2115 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT); 2116 widenScalarDst(MI, WideTy); 2117 widenScalarDst(MI, WideTy, 1); 2118 Observer.changedInstr(MI); 2119 return Legalized; 2120 2121 case TargetOpcode::G_ASHR: 2122 case TargetOpcode::G_LSHR: 2123 Observer.changingInstr(MI); 2124 2125 if (TypeIdx == 0) { 2126 unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ? 2127 TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 2128 2129 widenScalarSrc(MI, WideTy, 1, CvtOp); 2130 widenScalarDst(MI, WideTy); 2131 } else { 2132 assert(TypeIdx == 1); 2133 // The "number of bits to shift" operand must preserve its value as an 2134 // unsigned integer: 2135 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2136 } 2137 2138 Observer.changedInstr(MI); 2139 return Legalized; 2140 case TargetOpcode::G_UDIV: 2141 case TargetOpcode::G_UREM: 2142 case TargetOpcode::G_UMIN: 2143 case TargetOpcode::G_UMAX: 2144 Observer.changingInstr(MI); 2145 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2146 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2147 widenScalarDst(MI, WideTy); 2148 Observer.changedInstr(MI); 2149 return Legalized; 2150 2151 case TargetOpcode::G_UDIVREM: 2152 Observer.changingInstr(MI); 2153 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2154 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ZEXT); 2155 widenScalarDst(MI, WideTy); 2156 widenScalarDst(MI, WideTy, 1); 2157 Observer.changedInstr(MI); 2158 return Legalized; 2159 2160 case TargetOpcode::G_SELECT: 2161 Observer.changingInstr(MI); 2162 if (TypeIdx == 0) { 2163 // Perform operation at larger width (any extension is fine here, high 2164 // bits don't affect the result) and then truncate the result back to the 2165 // original type. 2166 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2167 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT); 2168 widenScalarDst(MI, WideTy); 2169 } else { 2170 bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector(); 2171 // Explicit extension is required here since high bits affect the result. 2172 widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false)); 2173 } 2174 Observer.changedInstr(MI); 2175 return Legalized; 2176 2177 case TargetOpcode::G_FPTOSI: 2178 case TargetOpcode::G_FPTOUI: 2179 Observer.changingInstr(MI); 2180 2181 if (TypeIdx == 0) 2182 widenScalarDst(MI, WideTy); 2183 else 2184 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2185 2186 Observer.changedInstr(MI); 2187 return Legalized; 2188 case TargetOpcode::G_SITOFP: 2189 Observer.changingInstr(MI); 2190 2191 if (TypeIdx == 0) 2192 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2193 else 2194 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT); 2195 2196 Observer.changedInstr(MI); 2197 return Legalized; 2198 case TargetOpcode::G_UITOFP: 2199 Observer.changingInstr(MI); 2200 2201 if (TypeIdx == 0) 2202 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2203 else 2204 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2205 2206 Observer.changedInstr(MI); 2207 return Legalized; 2208 case TargetOpcode::G_LOAD: 2209 case TargetOpcode::G_SEXTLOAD: 2210 case TargetOpcode::G_ZEXTLOAD: 2211 Observer.changingInstr(MI); 2212 widenScalarDst(MI, WideTy); 2213 Observer.changedInstr(MI); 2214 return Legalized; 2215 2216 case TargetOpcode::G_STORE: { 2217 if (TypeIdx != 0) 2218 return UnableToLegalize; 2219 2220 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 2221 if (!Ty.isScalar()) 2222 return UnableToLegalize; 2223 2224 Observer.changingInstr(MI); 2225 2226 unsigned ExtType = Ty.getScalarSizeInBits() == 1 ? 2227 TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT; 2228 widenScalarSrc(MI, WideTy, 0, ExtType); 2229 2230 Observer.changedInstr(MI); 2231 return Legalized; 2232 } 2233 case TargetOpcode::G_CONSTANT: { 2234 MachineOperand &SrcMO = MI.getOperand(1); 2235 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2236 unsigned ExtOpc = LI.getExtOpcodeForWideningConstant( 2237 MRI.getType(MI.getOperand(0).getReg())); 2238 assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT || 2239 ExtOpc == TargetOpcode::G_ANYEXT) && 2240 "Illegal Extend"); 2241 const APInt &SrcVal = SrcMO.getCImm()->getValue(); 2242 const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT) 2243 ? SrcVal.sext(WideTy.getSizeInBits()) 2244 : SrcVal.zext(WideTy.getSizeInBits()); 2245 Observer.changingInstr(MI); 2246 SrcMO.setCImm(ConstantInt::get(Ctx, Val)); 2247 2248 widenScalarDst(MI, WideTy); 2249 Observer.changedInstr(MI); 2250 return Legalized; 2251 } 2252 case TargetOpcode::G_FCONSTANT: { 2253 MachineOperand &SrcMO = MI.getOperand(1); 2254 LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext(); 2255 APFloat Val = SrcMO.getFPImm()->getValueAPF(); 2256 bool LosesInfo; 2257 switch (WideTy.getSizeInBits()) { 2258 case 32: 2259 Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven, 2260 &LosesInfo); 2261 break; 2262 case 64: 2263 Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven, 2264 &LosesInfo); 2265 break; 2266 default: 2267 return UnableToLegalize; 2268 } 2269 2270 assert(!LosesInfo && "extend should always be lossless"); 2271 2272 Observer.changingInstr(MI); 2273 SrcMO.setFPImm(ConstantFP::get(Ctx, Val)); 2274 2275 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2276 Observer.changedInstr(MI); 2277 return Legalized; 2278 } 2279 case TargetOpcode::G_IMPLICIT_DEF: { 2280 Observer.changingInstr(MI); 2281 widenScalarDst(MI, WideTy); 2282 Observer.changedInstr(MI); 2283 return Legalized; 2284 } 2285 case TargetOpcode::G_BRCOND: 2286 Observer.changingInstr(MI); 2287 widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false)); 2288 Observer.changedInstr(MI); 2289 return Legalized; 2290 2291 case TargetOpcode::G_FCMP: 2292 Observer.changingInstr(MI); 2293 if (TypeIdx == 0) 2294 widenScalarDst(MI, WideTy); 2295 else { 2296 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT); 2297 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT); 2298 } 2299 Observer.changedInstr(MI); 2300 return Legalized; 2301 2302 case TargetOpcode::G_ICMP: 2303 Observer.changingInstr(MI); 2304 if (TypeIdx == 0) 2305 widenScalarDst(MI, WideTy); 2306 else { 2307 unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>( 2308 MI.getOperand(1).getPredicate())) 2309 ? TargetOpcode::G_SEXT 2310 : TargetOpcode::G_ZEXT; 2311 widenScalarSrc(MI, WideTy, 2, ExtOpcode); 2312 widenScalarSrc(MI, WideTy, 3, ExtOpcode); 2313 } 2314 Observer.changedInstr(MI); 2315 return Legalized; 2316 2317 case TargetOpcode::G_PTR_ADD: 2318 assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD"); 2319 Observer.changingInstr(MI); 2320 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2321 Observer.changedInstr(MI); 2322 return Legalized; 2323 2324 case TargetOpcode::G_PHI: { 2325 assert(TypeIdx == 0 && "Expecting only Idx 0"); 2326 2327 Observer.changingInstr(MI); 2328 for (unsigned I = 1; I < MI.getNumOperands(); I += 2) { 2329 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 2330 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 2331 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT); 2332 } 2333 2334 MachineBasicBlock &MBB = *MI.getParent(); 2335 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 2336 widenScalarDst(MI, WideTy); 2337 Observer.changedInstr(MI); 2338 return Legalized; 2339 } 2340 case TargetOpcode::G_EXTRACT_VECTOR_ELT: { 2341 if (TypeIdx == 0) { 2342 Register VecReg = MI.getOperand(1).getReg(); 2343 LLT VecTy = MRI.getType(VecReg); 2344 Observer.changingInstr(MI); 2345 2346 widenScalarSrc( 2347 MI, LLT::vector(VecTy.getElementCount(), WideTy.getSizeInBits()), 1, 2348 TargetOpcode::G_SEXT); 2349 2350 widenScalarDst(MI, WideTy, 0); 2351 Observer.changedInstr(MI); 2352 return Legalized; 2353 } 2354 2355 if (TypeIdx != 2) 2356 return UnableToLegalize; 2357 Observer.changingInstr(MI); 2358 // TODO: Probably should be zext 2359 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT); 2360 Observer.changedInstr(MI); 2361 return Legalized; 2362 } 2363 case TargetOpcode::G_INSERT_VECTOR_ELT: { 2364 if (TypeIdx == 1) { 2365 Observer.changingInstr(MI); 2366 2367 Register VecReg = MI.getOperand(1).getReg(); 2368 LLT VecTy = MRI.getType(VecReg); 2369 LLT WideVecTy = LLT::vector(VecTy.getElementCount(), WideTy); 2370 2371 widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT); 2372 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT); 2373 widenScalarDst(MI, WideVecTy, 0); 2374 Observer.changedInstr(MI); 2375 return Legalized; 2376 } 2377 2378 if (TypeIdx == 2) { 2379 Observer.changingInstr(MI); 2380 // TODO: Probably should be zext 2381 widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT); 2382 Observer.changedInstr(MI); 2383 return Legalized; 2384 } 2385 2386 return UnableToLegalize; 2387 } 2388 case TargetOpcode::G_FADD: 2389 case TargetOpcode::G_FMUL: 2390 case TargetOpcode::G_FSUB: 2391 case TargetOpcode::G_FMA: 2392 case TargetOpcode::G_FMAD: 2393 case TargetOpcode::G_FNEG: 2394 case TargetOpcode::G_FABS: 2395 case TargetOpcode::G_FCANONICALIZE: 2396 case TargetOpcode::G_FMINNUM: 2397 case TargetOpcode::G_FMAXNUM: 2398 case TargetOpcode::G_FMINNUM_IEEE: 2399 case TargetOpcode::G_FMAXNUM_IEEE: 2400 case TargetOpcode::G_FMINIMUM: 2401 case TargetOpcode::G_FMAXIMUM: 2402 case TargetOpcode::G_FDIV: 2403 case TargetOpcode::G_FREM: 2404 case TargetOpcode::G_FCEIL: 2405 case TargetOpcode::G_FFLOOR: 2406 case TargetOpcode::G_FCOS: 2407 case TargetOpcode::G_FSIN: 2408 case TargetOpcode::G_FLOG10: 2409 case TargetOpcode::G_FLOG: 2410 case TargetOpcode::G_FLOG2: 2411 case TargetOpcode::G_FRINT: 2412 case TargetOpcode::G_FNEARBYINT: 2413 case TargetOpcode::G_FSQRT: 2414 case TargetOpcode::G_FEXP: 2415 case TargetOpcode::G_FEXP2: 2416 case TargetOpcode::G_FPOW: 2417 case TargetOpcode::G_INTRINSIC_TRUNC: 2418 case TargetOpcode::G_INTRINSIC_ROUND: 2419 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: 2420 assert(TypeIdx == 0); 2421 Observer.changingInstr(MI); 2422 2423 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 2424 widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT); 2425 2426 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2427 Observer.changedInstr(MI); 2428 return Legalized; 2429 case TargetOpcode::G_FPOWI: { 2430 if (TypeIdx != 0) 2431 return UnableToLegalize; 2432 Observer.changingInstr(MI); 2433 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT); 2434 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC); 2435 Observer.changedInstr(MI); 2436 return Legalized; 2437 } 2438 case TargetOpcode::G_INTTOPTR: 2439 if (TypeIdx != 1) 2440 return UnableToLegalize; 2441 2442 Observer.changingInstr(MI); 2443 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT); 2444 Observer.changedInstr(MI); 2445 return Legalized; 2446 case TargetOpcode::G_PTRTOINT: 2447 if (TypeIdx != 0) 2448 return UnableToLegalize; 2449 2450 Observer.changingInstr(MI); 2451 widenScalarDst(MI, WideTy, 0); 2452 Observer.changedInstr(MI); 2453 return Legalized; 2454 case TargetOpcode::G_BUILD_VECTOR: { 2455 Observer.changingInstr(MI); 2456 2457 const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType(); 2458 for (int I = 1, E = MI.getNumOperands(); I != E; ++I) 2459 widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT); 2460 2461 // Avoid changing the result vector type if the source element type was 2462 // requested. 2463 if (TypeIdx == 1) { 2464 MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BUILD_VECTOR_TRUNC)); 2465 } else { 2466 widenScalarDst(MI, WideTy, 0); 2467 } 2468 2469 Observer.changedInstr(MI); 2470 return Legalized; 2471 } 2472 case TargetOpcode::G_SEXT_INREG: 2473 if (TypeIdx != 0) 2474 return UnableToLegalize; 2475 2476 Observer.changingInstr(MI); 2477 widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT); 2478 widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC); 2479 Observer.changedInstr(MI); 2480 return Legalized; 2481 case TargetOpcode::G_PTRMASK: { 2482 if (TypeIdx != 1) 2483 return UnableToLegalize; 2484 Observer.changingInstr(MI); 2485 widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT); 2486 Observer.changedInstr(MI); 2487 return Legalized; 2488 } 2489 } 2490 } 2491 2492 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces, 2493 MachineIRBuilder &B, Register Src, LLT Ty) { 2494 auto Unmerge = B.buildUnmerge(Ty, Src); 2495 for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I) 2496 Pieces.push_back(Unmerge.getReg(I)); 2497 } 2498 2499 LegalizerHelper::LegalizeResult 2500 LegalizerHelper::lowerBitcast(MachineInstr &MI) { 2501 Register Dst = MI.getOperand(0).getReg(); 2502 Register Src = MI.getOperand(1).getReg(); 2503 LLT DstTy = MRI.getType(Dst); 2504 LLT SrcTy = MRI.getType(Src); 2505 2506 if (SrcTy.isVector()) { 2507 LLT SrcEltTy = SrcTy.getElementType(); 2508 SmallVector<Register, 8> SrcRegs; 2509 2510 if (DstTy.isVector()) { 2511 int NumDstElt = DstTy.getNumElements(); 2512 int NumSrcElt = SrcTy.getNumElements(); 2513 2514 LLT DstEltTy = DstTy.getElementType(); 2515 LLT DstCastTy = DstEltTy; // Intermediate bitcast result type 2516 LLT SrcPartTy = SrcEltTy; // Original unmerge result type. 2517 2518 // If there's an element size mismatch, insert intermediate casts to match 2519 // the result element type. 2520 if (NumSrcElt < NumDstElt) { // Source element type is larger. 2521 // %1:_(<4 x s8>) = G_BITCAST %0:_(<2 x s16>) 2522 // 2523 // => 2524 // 2525 // %2:_(s16), %3:_(s16) = G_UNMERGE_VALUES %0 2526 // %3:_(<2 x s8>) = G_BITCAST %2 2527 // %4:_(<2 x s8>) = G_BITCAST %3 2528 // %1:_(<4 x s16>) = G_CONCAT_VECTORS %3, %4 2529 DstCastTy = LLT::fixed_vector(NumDstElt / NumSrcElt, DstEltTy); 2530 SrcPartTy = SrcEltTy; 2531 } else if (NumSrcElt > NumDstElt) { // Source element type is smaller. 2532 // 2533 // %1:_(<2 x s16>) = G_BITCAST %0:_(<4 x s8>) 2534 // 2535 // => 2536 // 2537 // %2:_(<2 x s8>), %3:_(<2 x s8>) = G_UNMERGE_VALUES %0 2538 // %3:_(s16) = G_BITCAST %2 2539 // %4:_(s16) = G_BITCAST %3 2540 // %1:_(<2 x s16>) = G_BUILD_VECTOR %3, %4 2541 SrcPartTy = LLT::fixed_vector(NumSrcElt / NumDstElt, SrcEltTy); 2542 DstCastTy = DstEltTy; 2543 } 2544 2545 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcPartTy); 2546 for (Register &SrcReg : SrcRegs) 2547 SrcReg = MIRBuilder.buildBitcast(DstCastTy, SrcReg).getReg(0); 2548 } else 2549 getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcEltTy); 2550 2551 MIRBuilder.buildMerge(Dst, SrcRegs); 2552 MI.eraseFromParent(); 2553 return Legalized; 2554 } 2555 2556 if (DstTy.isVector()) { 2557 SmallVector<Register, 8> SrcRegs; 2558 getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType()); 2559 MIRBuilder.buildMerge(Dst, SrcRegs); 2560 MI.eraseFromParent(); 2561 return Legalized; 2562 } 2563 2564 return UnableToLegalize; 2565 } 2566 2567 /// Figure out the bit offset into a register when coercing a vector index for 2568 /// the wide element type. This is only for the case when promoting vector to 2569 /// one with larger elements. 2570 // 2571 /// 2572 /// %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2573 /// %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2574 static Register getBitcastWiderVectorElementOffset(MachineIRBuilder &B, 2575 Register Idx, 2576 unsigned NewEltSize, 2577 unsigned OldEltSize) { 2578 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2579 LLT IdxTy = B.getMRI()->getType(Idx); 2580 2581 // Now figure out the amount we need to shift to get the target bits. 2582 auto OffsetMask = B.buildConstant( 2583 IdxTy, ~(APInt::getAllOnesValue(IdxTy.getSizeInBits()) << Log2EltRatio)); 2584 auto OffsetIdx = B.buildAnd(IdxTy, Idx, OffsetMask); 2585 return B.buildShl(IdxTy, OffsetIdx, 2586 B.buildConstant(IdxTy, Log2_32(OldEltSize))).getReg(0); 2587 } 2588 2589 /// Perform a G_EXTRACT_VECTOR_ELT in a different sized vector element. If this 2590 /// is casting to a vector with a smaller element size, perform multiple element 2591 /// extracts and merge the results. If this is coercing to a vector with larger 2592 /// elements, index the bitcasted vector and extract the target element with bit 2593 /// operations. This is intended to force the indexing in the native register 2594 /// size for architectures that can dynamically index the register file. 2595 LegalizerHelper::LegalizeResult 2596 LegalizerHelper::bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx, 2597 LLT CastTy) { 2598 if (TypeIdx != 1) 2599 return UnableToLegalize; 2600 2601 Register Dst = MI.getOperand(0).getReg(); 2602 Register SrcVec = MI.getOperand(1).getReg(); 2603 Register Idx = MI.getOperand(2).getReg(); 2604 LLT SrcVecTy = MRI.getType(SrcVec); 2605 LLT IdxTy = MRI.getType(Idx); 2606 2607 LLT SrcEltTy = SrcVecTy.getElementType(); 2608 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2609 unsigned OldNumElts = SrcVecTy.getNumElements(); 2610 2611 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2612 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2613 2614 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2615 const unsigned OldEltSize = SrcEltTy.getSizeInBits(); 2616 if (NewNumElts > OldNumElts) { 2617 // Decreasing the vector element size 2618 // 2619 // e.g. i64 = extract_vector_elt x:v2i64, y:i32 2620 // => 2621 // v4i32:castx = bitcast x:v2i64 2622 // 2623 // i64 = bitcast 2624 // (v2i32 build_vector (i32 (extract_vector_elt castx, (2 * y))), 2625 // (i32 (extract_vector_elt castx, (2 * y + 1))) 2626 // 2627 if (NewNumElts % OldNumElts != 0) 2628 return UnableToLegalize; 2629 2630 // Type of the intermediate result vector. 2631 const unsigned NewEltsPerOldElt = NewNumElts / OldNumElts; 2632 LLT MidTy = 2633 LLT::scalarOrVector(ElementCount::getFixed(NewEltsPerOldElt), NewEltTy); 2634 2635 auto NewEltsPerOldEltK = MIRBuilder.buildConstant(IdxTy, NewEltsPerOldElt); 2636 2637 SmallVector<Register, 8> NewOps(NewEltsPerOldElt); 2638 auto NewBaseIdx = MIRBuilder.buildMul(IdxTy, Idx, NewEltsPerOldEltK); 2639 2640 for (unsigned I = 0; I < NewEltsPerOldElt; ++I) { 2641 auto IdxOffset = MIRBuilder.buildConstant(IdxTy, I); 2642 auto TmpIdx = MIRBuilder.buildAdd(IdxTy, NewBaseIdx, IdxOffset); 2643 auto Elt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, TmpIdx); 2644 NewOps[I] = Elt.getReg(0); 2645 } 2646 2647 auto NewVec = MIRBuilder.buildBuildVector(MidTy, NewOps); 2648 MIRBuilder.buildBitcast(Dst, NewVec); 2649 MI.eraseFromParent(); 2650 return Legalized; 2651 } 2652 2653 if (NewNumElts < OldNumElts) { 2654 if (NewEltSize % OldEltSize != 0) 2655 return UnableToLegalize; 2656 2657 // This only depends on powers of 2 because we use bit tricks to figure out 2658 // the bit offset we need to shift to get the target element. A general 2659 // expansion could emit division/multiply. 2660 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2661 return UnableToLegalize; 2662 2663 // Increasing the vector element size. 2664 // %elt:_(small_elt) = G_EXTRACT_VECTOR_ELT %vec:_(<N x small_elt>), %idx 2665 // 2666 // => 2667 // 2668 // %cast = G_BITCAST %vec 2669 // %scaled_idx = G_LSHR %idx, Log2(DstEltSize / SrcEltSize) 2670 // %wide_elt = G_EXTRACT_VECTOR_ELT %cast, %scaled_idx 2671 // %offset_idx = G_AND %idx, ~(-1 << Log2(DstEltSize / SrcEltSize)) 2672 // %offset_bits = G_SHL %offset_idx, Log2(SrcEltSize) 2673 // %elt_bits = G_LSHR %wide_elt, %offset_bits 2674 // %elt = G_TRUNC %elt_bits 2675 2676 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2677 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2678 2679 // Divide to get the index in the wider element type. 2680 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2681 2682 Register WideElt = CastVec; 2683 if (CastTy.isVector()) { 2684 WideElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2685 ScaledIdx).getReg(0); 2686 } 2687 2688 // Compute the bit offset into the register of the target element. 2689 Register OffsetBits = getBitcastWiderVectorElementOffset( 2690 MIRBuilder, Idx, NewEltSize, OldEltSize); 2691 2692 // Shift the wide element to get the target element. 2693 auto ExtractedBits = MIRBuilder.buildLShr(NewEltTy, WideElt, OffsetBits); 2694 MIRBuilder.buildTrunc(Dst, ExtractedBits); 2695 MI.eraseFromParent(); 2696 return Legalized; 2697 } 2698 2699 return UnableToLegalize; 2700 } 2701 2702 /// Emit code to insert \p InsertReg into \p TargetRet at \p OffsetBits in \p 2703 /// TargetReg, while preserving other bits in \p TargetReg. 2704 /// 2705 /// (InsertReg << Offset) | (TargetReg & ~(-1 >> InsertReg.size()) << Offset) 2706 static Register buildBitFieldInsert(MachineIRBuilder &B, 2707 Register TargetReg, Register InsertReg, 2708 Register OffsetBits) { 2709 LLT TargetTy = B.getMRI()->getType(TargetReg); 2710 LLT InsertTy = B.getMRI()->getType(InsertReg); 2711 auto ZextVal = B.buildZExt(TargetTy, InsertReg); 2712 auto ShiftedInsertVal = B.buildShl(TargetTy, ZextVal, OffsetBits); 2713 2714 // Produce a bitmask of the value to insert 2715 auto EltMask = B.buildConstant( 2716 TargetTy, APInt::getLowBitsSet(TargetTy.getSizeInBits(), 2717 InsertTy.getSizeInBits())); 2718 // Shift it into position 2719 auto ShiftedMask = B.buildShl(TargetTy, EltMask, OffsetBits); 2720 auto InvShiftedMask = B.buildNot(TargetTy, ShiftedMask); 2721 2722 // Clear out the bits in the wide element 2723 auto MaskedOldElt = B.buildAnd(TargetTy, TargetReg, InvShiftedMask); 2724 2725 // The value to insert has all zeros already, so stick it into the masked 2726 // wide element. 2727 return B.buildOr(TargetTy, MaskedOldElt, ShiftedInsertVal).getReg(0); 2728 } 2729 2730 /// Perform a G_INSERT_VECTOR_ELT in a different sized vector element. If this 2731 /// is increasing the element size, perform the indexing in the target element 2732 /// type, and use bit operations to insert at the element position. This is 2733 /// intended for architectures that can dynamically index the register file and 2734 /// want to force indexing in the native register size. 2735 LegalizerHelper::LegalizeResult 2736 LegalizerHelper::bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx, 2737 LLT CastTy) { 2738 if (TypeIdx != 0) 2739 return UnableToLegalize; 2740 2741 Register Dst = MI.getOperand(0).getReg(); 2742 Register SrcVec = MI.getOperand(1).getReg(); 2743 Register Val = MI.getOperand(2).getReg(); 2744 Register Idx = MI.getOperand(3).getReg(); 2745 2746 LLT VecTy = MRI.getType(Dst); 2747 LLT IdxTy = MRI.getType(Idx); 2748 2749 LLT VecEltTy = VecTy.getElementType(); 2750 LLT NewEltTy = CastTy.isVector() ? CastTy.getElementType() : CastTy; 2751 const unsigned NewEltSize = NewEltTy.getSizeInBits(); 2752 const unsigned OldEltSize = VecEltTy.getSizeInBits(); 2753 2754 unsigned NewNumElts = CastTy.isVector() ? CastTy.getNumElements() : 1; 2755 unsigned OldNumElts = VecTy.getNumElements(); 2756 2757 Register CastVec = MIRBuilder.buildBitcast(CastTy, SrcVec).getReg(0); 2758 if (NewNumElts < OldNumElts) { 2759 if (NewEltSize % OldEltSize != 0) 2760 return UnableToLegalize; 2761 2762 // This only depends on powers of 2 because we use bit tricks to figure out 2763 // the bit offset we need to shift to get the target element. A general 2764 // expansion could emit division/multiply. 2765 if (!isPowerOf2_32(NewEltSize / OldEltSize)) 2766 return UnableToLegalize; 2767 2768 const unsigned Log2EltRatio = Log2_32(NewEltSize / OldEltSize); 2769 auto Log2Ratio = MIRBuilder.buildConstant(IdxTy, Log2EltRatio); 2770 2771 // Divide to get the index in the wider element type. 2772 auto ScaledIdx = MIRBuilder.buildLShr(IdxTy, Idx, Log2Ratio); 2773 2774 Register ExtractedElt = CastVec; 2775 if (CastTy.isVector()) { 2776 ExtractedElt = MIRBuilder.buildExtractVectorElement(NewEltTy, CastVec, 2777 ScaledIdx).getReg(0); 2778 } 2779 2780 // Compute the bit offset into the register of the target element. 2781 Register OffsetBits = getBitcastWiderVectorElementOffset( 2782 MIRBuilder, Idx, NewEltSize, OldEltSize); 2783 2784 Register InsertedElt = buildBitFieldInsert(MIRBuilder, ExtractedElt, 2785 Val, OffsetBits); 2786 if (CastTy.isVector()) { 2787 InsertedElt = MIRBuilder.buildInsertVectorElement( 2788 CastTy, CastVec, InsertedElt, ScaledIdx).getReg(0); 2789 } 2790 2791 MIRBuilder.buildBitcast(Dst, InsertedElt); 2792 MI.eraseFromParent(); 2793 return Legalized; 2794 } 2795 2796 return UnableToLegalize; 2797 } 2798 2799 LegalizerHelper::LegalizeResult LegalizerHelper::lowerLoad(GAnyLoad &LoadMI) { 2800 // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT 2801 Register DstReg = LoadMI.getDstReg(); 2802 Register PtrReg = LoadMI.getPointerReg(); 2803 LLT DstTy = MRI.getType(DstReg); 2804 MachineMemOperand &MMO = LoadMI.getMMO(); 2805 LLT MemTy = MMO.getMemoryType(); 2806 MachineFunction &MF = MIRBuilder.getMF(); 2807 if (MemTy.isVector()) 2808 return UnableToLegalize; 2809 2810 unsigned MemSizeInBits = MemTy.getSizeInBits(); 2811 unsigned MemStoreSizeInBits = 8 * MemTy.getSizeInBytes(); 2812 2813 if (MemSizeInBits != MemStoreSizeInBits) { 2814 // Promote to a byte-sized load if not loading an integral number of 2815 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 2816 LLT WideMemTy = LLT::scalar(MemStoreSizeInBits); 2817 MachineMemOperand *NewMMO = 2818 MF.getMachineMemOperand(&MMO, MMO.getPointerInfo(), WideMemTy); 2819 2820 Register LoadReg = DstReg; 2821 LLT LoadTy = DstTy; 2822 2823 // If this wasn't already an extending load, we need to widen the result 2824 // register to avoid creating a load with a narrower result than the source. 2825 if (MemStoreSizeInBits > DstTy.getSizeInBits()) { 2826 LoadTy = WideMemTy; 2827 LoadReg = MRI.createGenericVirtualRegister(WideMemTy); 2828 } 2829 2830 if (isa<GSExtLoad>(LoadMI)) { 2831 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); 2832 MIRBuilder.buildSExtInReg(LoadReg, NewLoad, MemSizeInBits); 2833 } else if (isa<GZExtLoad>(LoadMI) || WideMemTy == DstTy) { 2834 auto NewLoad = MIRBuilder.buildLoad(LoadTy, PtrReg, *NewMMO); 2835 // The extra bits are guaranteed to be zero, since we stored them that 2836 // way. A zext load from Wide thus automatically gives zext from MemVT. 2837 MIRBuilder.buildAssertZExt(LoadReg, NewLoad, MemSizeInBits); 2838 } else { 2839 MIRBuilder.buildLoad(LoadReg, PtrReg, *NewMMO); 2840 } 2841 2842 if (DstTy != LoadTy) 2843 MIRBuilder.buildTrunc(DstReg, LoadReg); 2844 2845 LoadMI.eraseFromParent(); 2846 return Legalized; 2847 } 2848 2849 // This load needs splitting into power of 2 sized loads. 2850 if (DstTy.isVector()) 2851 return UnableToLegalize; 2852 if (isPowerOf2_32(MemSizeInBits)) 2853 return UnableToLegalize; // Don't know what we're being asked to do. 2854 2855 // Big endian lowering not implemented. 2856 if (MIRBuilder.getDataLayout().isBigEndian()) 2857 return UnableToLegalize; 2858 2859 // Our strategy here is to generate anyextending loads for the smaller 2860 // types up to next power-2 result type, and then combine the two larger 2861 // result values together, before truncating back down to the non-pow-2 2862 // type. 2863 // E.g. v1 = i24 load => 2864 // v2 = i32 zextload (2 byte) 2865 // v3 = i32 load (1 byte) 2866 // v4 = i32 shl v3, 16 2867 // v5 = i32 or v4, v2 2868 // v1 = i24 trunc v5 2869 // By doing this we generate the correct truncate which should get 2870 // combined away as an artifact with a matching extend. 2871 uint64_t LargeSplitSize = PowerOf2Floor(MemSizeInBits); 2872 uint64_t SmallSplitSize = MemSizeInBits - LargeSplitSize; 2873 2874 MachineMemOperand *LargeMMO = 2875 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2876 MachineMemOperand *SmallMMO = 2877 MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2878 2879 LLT PtrTy = MRI.getType(PtrReg); 2880 unsigned AnyExtSize = PowerOf2Ceil(DstTy.getSizeInBits()); 2881 LLT AnyExtTy = LLT::scalar(AnyExtSize); 2882 auto LargeLoad = MIRBuilder.buildLoadInstr(TargetOpcode::G_ZEXTLOAD, AnyExtTy, 2883 PtrReg, *LargeMMO); 2884 2885 auto OffsetCst = MIRBuilder.buildConstant(LLT::scalar(PtrTy.getSizeInBits()), 2886 LargeSplitSize / 8); 2887 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2888 auto SmallPtr = MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); 2889 auto SmallLoad = MIRBuilder.buildLoadInstr(LoadMI.getOpcode(), AnyExtTy, 2890 SmallPtr, *SmallMMO); 2891 2892 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize); 2893 auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt); 2894 2895 if (AnyExtTy == DstTy) 2896 MIRBuilder.buildOr(DstReg, Shift, LargeLoad); 2897 else { 2898 auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad); 2899 MIRBuilder.buildTrunc(DstReg, {Or}); 2900 } 2901 2902 LoadMI.eraseFromParent(); 2903 return Legalized; 2904 } 2905 2906 LegalizerHelper::LegalizeResult LegalizerHelper::lowerStore(GStore &StoreMI) { 2907 // Lower a non-power of 2 store into multiple pow-2 stores. 2908 // E.g. split an i24 store into an i16 store + i8 store. 2909 // We do this by first extending the stored value to the next largest power 2910 // of 2 type, and then using truncating stores to store the components. 2911 // By doing this, likewise with G_LOAD, generate an extend that can be 2912 // artifact-combined away instead of leaving behind extracts. 2913 Register SrcReg = StoreMI.getValueReg(); 2914 Register PtrReg = StoreMI.getPointerReg(); 2915 LLT SrcTy = MRI.getType(SrcReg); 2916 MachineFunction &MF = MIRBuilder.getMF(); 2917 MachineMemOperand &MMO = **StoreMI.memoperands_begin(); 2918 LLT MemTy = MMO.getMemoryType(); 2919 2920 if (SrcTy.isVector()) 2921 return UnableToLegalize; 2922 2923 unsigned StoreWidth = MemTy.getSizeInBits(); 2924 unsigned StoreSizeInBits = 8 * MemTy.getSizeInBytes(); 2925 2926 if (StoreWidth != StoreSizeInBits) { 2927 // Promote to a byte-sized store with upper bits zero if not 2928 // storing an integral number of bytes. For example, promote 2929 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 2930 LLT WideTy = LLT::scalar(StoreSizeInBits); 2931 2932 if (StoreSizeInBits > SrcTy.getSizeInBits()) { 2933 // Avoid creating a store with a narrower source than result. 2934 SrcReg = MIRBuilder.buildAnyExt(WideTy, SrcReg).getReg(0); 2935 SrcTy = WideTy; 2936 } 2937 2938 auto ZextInReg = MIRBuilder.buildZExtInReg(SrcTy, SrcReg, StoreWidth); 2939 2940 MachineMemOperand *NewMMO = 2941 MF.getMachineMemOperand(&MMO, MMO.getPointerInfo(), WideTy); 2942 MIRBuilder.buildStore(ZextInReg, PtrReg, *NewMMO); 2943 StoreMI.eraseFromParent(); 2944 return Legalized; 2945 } 2946 2947 if (isPowerOf2_32(MemTy.getSizeInBits())) 2948 return UnableToLegalize; // Don't know what we're being asked to do. 2949 2950 // Extend to the next pow-2. 2951 const LLT ExtendTy = LLT::scalar(NextPowerOf2(MemTy.getSizeInBits())); 2952 auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg); 2953 2954 // Obtain the smaller value by shifting away the larger value. 2955 uint64_t LargeSplitSize = PowerOf2Floor(MemTy.getSizeInBits()); 2956 uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize; 2957 auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize); 2958 auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt); 2959 2960 // Generate the PtrAdd and truncating stores. 2961 LLT PtrTy = MRI.getType(PtrReg); 2962 auto OffsetCst = MIRBuilder.buildConstant( 2963 LLT::scalar(PtrTy.getSizeInBits()), LargeSplitSize / 8); 2964 Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy); 2965 auto SmallPtr = 2966 MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst); 2967 2968 MachineMemOperand *LargeMMO = 2969 MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8); 2970 MachineMemOperand *SmallMMO = 2971 MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8); 2972 MIRBuilder.buildStore(ExtVal, PtrReg, *LargeMMO); 2973 MIRBuilder.buildStore(SmallVal, SmallPtr, *SmallMMO); 2974 StoreMI.eraseFromParent(); 2975 return Legalized; 2976 } 2977 2978 LegalizerHelper::LegalizeResult 2979 LegalizerHelper::bitcast(MachineInstr &MI, unsigned TypeIdx, LLT CastTy) { 2980 switch (MI.getOpcode()) { 2981 case TargetOpcode::G_LOAD: { 2982 if (TypeIdx != 0) 2983 return UnableToLegalize; 2984 2985 Observer.changingInstr(MI); 2986 bitcastDst(MI, CastTy, 0); 2987 Observer.changedInstr(MI); 2988 return Legalized; 2989 } 2990 case TargetOpcode::G_STORE: { 2991 if (TypeIdx != 0) 2992 return UnableToLegalize; 2993 2994 Observer.changingInstr(MI); 2995 bitcastSrc(MI, CastTy, 0); 2996 Observer.changedInstr(MI); 2997 return Legalized; 2998 } 2999 case TargetOpcode::G_SELECT: { 3000 if (TypeIdx != 0) 3001 return UnableToLegalize; 3002 3003 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) { 3004 LLVM_DEBUG( 3005 dbgs() << "bitcast action not implemented for vector select\n"); 3006 return UnableToLegalize; 3007 } 3008 3009 Observer.changingInstr(MI); 3010 bitcastSrc(MI, CastTy, 2); 3011 bitcastSrc(MI, CastTy, 3); 3012 bitcastDst(MI, CastTy, 0); 3013 Observer.changedInstr(MI); 3014 return Legalized; 3015 } 3016 case TargetOpcode::G_AND: 3017 case TargetOpcode::G_OR: 3018 case TargetOpcode::G_XOR: { 3019 Observer.changingInstr(MI); 3020 bitcastSrc(MI, CastTy, 1); 3021 bitcastSrc(MI, CastTy, 2); 3022 bitcastDst(MI, CastTy, 0); 3023 Observer.changedInstr(MI); 3024 return Legalized; 3025 } 3026 case TargetOpcode::G_EXTRACT_VECTOR_ELT: 3027 return bitcastExtractVectorElt(MI, TypeIdx, CastTy); 3028 case TargetOpcode::G_INSERT_VECTOR_ELT: 3029 return bitcastInsertVectorElt(MI, TypeIdx, CastTy); 3030 default: 3031 return UnableToLegalize; 3032 } 3033 } 3034 3035 // Legalize an instruction by changing the opcode in place. 3036 void LegalizerHelper::changeOpcode(MachineInstr &MI, unsigned NewOpcode) { 3037 Observer.changingInstr(MI); 3038 MI.setDesc(MIRBuilder.getTII().get(NewOpcode)); 3039 Observer.changedInstr(MI); 3040 } 3041 3042 LegalizerHelper::LegalizeResult 3043 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT LowerHintTy) { 3044 using namespace TargetOpcode; 3045 3046 switch(MI.getOpcode()) { 3047 default: 3048 return UnableToLegalize; 3049 case TargetOpcode::G_BITCAST: 3050 return lowerBitcast(MI); 3051 case TargetOpcode::G_SREM: 3052 case TargetOpcode::G_UREM: { 3053 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3054 auto Quot = 3055 MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV, {Ty}, 3056 {MI.getOperand(1), MI.getOperand(2)}); 3057 3058 auto Prod = MIRBuilder.buildMul(Ty, Quot, MI.getOperand(2)); 3059 MIRBuilder.buildSub(MI.getOperand(0), MI.getOperand(1), Prod); 3060 MI.eraseFromParent(); 3061 return Legalized; 3062 } 3063 case TargetOpcode::G_SADDO: 3064 case TargetOpcode::G_SSUBO: 3065 return lowerSADDO_SSUBO(MI); 3066 case TargetOpcode::G_UMULH: 3067 case TargetOpcode::G_SMULH: 3068 return lowerSMULH_UMULH(MI); 3069 case TargetOpcode::G_SMULO: 3070 case TargetOpcode::G_UMULO: { 3071 // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the 3072 // result. 3073 Register Res = MI.getOperand(0).getReg(); 3074 Register Overflow = MI.getOperand(1).getReg(); 3075 Register LHS = MI.getOperand(2).getReg(); 3076 Register RHS = MI.getOperand(3).getReg(); 3077 LLT Ty = MRI.getType(Res); 3078 3079 unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO 3080 ? TargetOpcode::G_SMULH 3081 : TargetOpcode::G_UMULH; 3082 3083 Observer.changingInstr(MI); 3084 const auto &TII = MIRBuilder.getTII(); 3085 MI.setDesc(TII.get(TargetOpcode::G_MUL)); 3086 MI.RemoveOperand(1); 3087 Observer.changedInstr(MI); 3088 3089 auto HiPart = MIRBuilder.buildInstr(Opcode, {Ty}, {LHS, RHS}); 3090 auto Zero = MIRBuilder.buildConstant(Ty, 0); 3091 3092 // Move insert point forward so we can use the Res register if needed. 3093 MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt()); 3094 3095 // For *signed* multiply, overflow is detected by checking: 3096 // (hi != (lo >> bitwidth-1)) 3097 if (Opcode == TargetOpcode::G_SMULH) { 3098 auto ShiftAmt = MIRBuilder.buildConstant(Ty, Ty.getSizeInBits() - 1); 3099 auto Shifted = MIRBuilder.buildAShr(Ty, Res, ShiftAmt); 3100 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted); 3101 } else { 3102 MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero); 3103 } 3104 return Legalized; 3105 } 3106 case TargetOpcode::G_FNEG: { 3107 Register Res = MI.getOperand(0).getReg(); 3108 LLT Ty = MRI.getType(Res); 3109 3110 // TODO: Handle vector types once we are able to 3111 // represent them. 3112 if (Ty.isVector()) 3113 return UnableToLegalize; 3114 auto SignMask = 3115 MIRBuilder.buildConstant(Ty, APInt::getSignMask(Ty.getSizeInBits())); 3116 Register SubByReg = MI.getOperand(1).getReg(); 3117 MIRBuilder.buildXor(Res, SubByReg, SignMask); 3118 MI.eraseFromParent(); 3119 return Legalized; 3120 } 3121 case TargetOpcode::G_FSUB: { 3122 Register Res = MI.getOperand(0).getReg(); 3123 LLT Ty = MRI.getType(Res); 3124 3125 // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)). 3126 // First, check if G_FNEG is marked as Lower. If so, we may 3127 // end up with an infinite loop as G_FSUB is used to legalize G_FNEG. 3128 if (LI.getAction({G_FNEG, {Ty}}).Action == Lower) 3129 return UnableToLegalize; 3130 Register LHS = MI.getOperand(1).getReg(); 3131 Register RHS = MI.getOperand(2).getReg(); 3132 Register Neg = MRI.createGenericVirtualRegister(Ty); 3133 MIRBuilder.buildFNeg(Neg, RHS); 3134 MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags()); 3135 MI.eraseFromParent(); 3136 return Legalized; 3137 } 3138 case TargetOpcode::G_FMAD: 3139 return lowerFMad(MI); 3140 case TargetOpcode::G_FFLOOR: 3141 return lowerFFloor(MI); 3142 case TargetOpcode::G_INTRINSIC_ROUND: 3143 return lowerIntrinsicRound(MI); 3144 case TargetOpcode::G_INTRINSIC_ROUNDEVEN: { 3145 // Since round even is the assumed rounding mode for unconstrained FP 3146 // operations, rint and roundeven are the same operation. 3147 changeOpcode(MI, TargetOpcode::G_FRINT); 3148 return Legalized; 3149 } 3150 case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: { 3151 Register OldValRes = MI.getOperand(0).getReg(); 3152 Register SuccessRes = MI.getOperand(1).getReg(); 3153 Register Addr = MI.getOperand(2).getReg(); 3154 Register CmpVal = MI.getOperand(3).getReg(); 3155 Register NewVal = MI.getOperand(4).getReg(); 3156 MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal, 3157 **MI.memoperands_begin()); 3158 MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal); 3159 MI.eraseFromParent(); 3160 return Legalized; 3161 } 3162 case TargetOpcode::G_LOAD: 3163 case TargetOpcode::G_SEXTLOAD: 3164 case TargetOpcode::G_ZEXTLOAD: 3165 return lowerLoad(cast<GAnyLoad>(MI)); 3166 case TargetOpcode::G_STORE: 3167 return lowerStore(cast<GStore>(MI)); 3168 case TargetOpcode::G_CTLZ_ZERO_UNDEF: 3169 case TargetOpcode::G_CTTZ_ZERO_UNDEF: 3170 case TargetOpcode::G_CTLZ: 3171 case TargetOpcode::G_CTTZ: 3172 case TargetOpcode::G_CTPOP: 3173 return lowerBitCount(MI); 3174 case G_UADDO: { 3175 Register Res = MI.getOperand(0).getReg(); 3176 Register CarryOut = MI.getOperand(1).getReg(); 3177 Register LHS = MI.getOperand(2).getReg(); 3178 Register RHS = MI.getOperand(3).getReg(); 3179 3180 MIRBuilder.buildAdd(Res, LHS, RHS); 3181 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS); 3182 3183 MI.eraseFromParent(); 3184 return Legalized; 3185 } 3186 case G_UADDE: { 3187 Register Res = MI.getOperand(0).getReg(); 3188 Register CarryOut = MI.getOperand(1).getReg(); 3189 Register LHS = MI.getOperand(2).getReg(); 3190 Register RHS = MI.getOperand(3).getReg(); 3191 Register CarryIn = MI.getOperand(4).getReg(); 3192 LLT Ty = MRI.getType(Res); 3193 3194 auto TmpRes = MIRBuilder.buildAdd(Ty, LHS, RHS); 3195 auto ZExtCarryIn = MIRBuilder.buildZExt(Ty, CarryIn); 3196 MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn); 3197 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS); 3198 3199 MI.eraseFromParent(); 3200 return Legalized; 3201 } 3202 case G_USUBO: { 3203 Register Res = MI.getOperand(0).getReg(); 3204 Register BorrowOut = MI.getOperand(1).getReg(); 3205 Register LHS = MI.getOperand(2).getReg(); 3206 Register RHS = MI.getOperand(3).getReg(); 3207 3208 MIRBuilder.buildSub(Res, LHS, RHS); 3209 MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS); 3210 3211 MI.eraseFromParent(); 3212 return Legalized; 3213 } 3214 case G_USUBE: { 3215 Register Res = MI.getOperand(0).getReg(); 3216 Register BorrowOut = MI.getOperand(1).getReg(); 3217 Register LHS = MI.getOperand(2).getReg(); 3218 Register RHS = MI.getOperand(3).getReg(); 3219 Register BorrowIn = MI.getOperand(4).getReg(); 3220 const LLT CondTy = MRI.getType(BorrowOut); 3221 const LLT Ty = MRI.getType(Res); 3222 3223 auto TmpRes = MIRBuilder.buildSub(Ty, LHS, RHS); 3224 auto ZExtBorrowIn = MIRBuilder.buildZExt(Ty, BorrowIn); 3225 MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn); 3226 3227 auto LHS_EQ_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, CondTy, LHS, RHS); 3228 auto LHS_ULT_RHS = MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CondTy, LHS, RHS); 3229 MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS); 3230 3231 MI.eraseFromParent(); 3232 return Legalized; 3233 } 3234 case G_UITOFP: 3235 return lowerUITOFP(MI); 3236 case G_SITOFP: 3237 return lowerSITOFP(MI); 3238 case G_FPTOUI: 3239 return lowerFPTOUI(MI); 3240 case G_FPTOSI: 3241 return lowerFPTOSI(MI); 3242 case G_FPTRUNC: 3243 return lowerFPTRUNC(MI); 3244 case G_FPOWI: 3245 return lowerFPOWI(MI); 3246 case G_SMIN: 3247 case G_SMAX: 3248 case G_UMIN: 3249 case G_UMAX: 3250 return lowerMinMax(MI); 3251 case G_FCOPYSIGN: 3252 return lowerFCopySign(MI); 3253 case G_FMINNUM: 3254 case G_FMAXNUM: 3255 return lowerFMinNumMaxNum(MI); 3256 case G_MERGE_VALUES: 3257 return lowerMergeValues(MI); 3258 case G_UNMERGE_VALUES: 3259 return lowerUnmergeValues(MI); 3260 case TargetOpcode::G_SEXT_INREG: { 3261 assert(MI.getOperand(2).isImm() && "Expected immediate"); 3262 int64_t SizeInBits = MI.getOperand(2).getImm(); 3263 3264 Register DstReg = MI.getOperand(0).getReg(); 3265 Register SrcReg = MI.getOperand(1).getReg(); 3266 LLT DstTy = MRI.getType(DstReg); 3267 Register TmpRes = MRI.createGenericVirtualRegister(DstTy); 3268 3269 auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits); 3270 MIRBuilder.buildShl(TmpRes, SrcReg, MIBSz->getOperand(0)); 3271 MIRBuilder.buildAShr(DstReg, TmpRes, MIBSz->getOperand(0)); 3272 MI.eraseFromParent(); 3273 return Legalized; 3274 } 3275 case G_EXTRACT_VECTOR_ELT: 3276 case G_INSERT_VECTOR_ELT: 3277 return lowerExtractInsertVectorElt(MI); 3278 case G_SHUFFLE_VECTOR: 3279 return lowerShuffleVector(MI); 3280 case G_DYN_STACKALLOC: 3281 return lowerDynStackAlloc(MI); 3282 case G_EXTRACT: 3283 return lowerExtract(MI); 3284 case G_INSERT: 3285 return lowerInsert(MI); 3286 case G_BSWAP: 3287 return lowerBswap(MI); 3288 case G_BITREVERSE: 3289 return lowerBitreverse(MI); 3290 case G_READ_REGISTER: 3291 case G_WRITE_REGISTER: 3292 return lowerReadWriteRegister(MI); 3293 case G_UADDSAT: 3294 case G_USUBSAT: { 3295 // Try to make a reasonable guess about which lowering strategy to use. The 3296 // target can override this with custom lowering and calling the 3297 // implementation functions. 3298 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3299 if (LI.isLegalOrCustom({G_UMIN, Ty})) 3300 return lowerAddSubSatToMinMax(MI); 3301 return lowerAddSubSatToAddoSubo(MI); 3302 } 3303 case G_SADDSAT: 3304 case G_SSUBSAT: { 3305 LLT Ty = MRI.getType(MI.getOperand(0).getReg()); 3306 3307 // FIXME: It would probably make more sense to see if G_SADDO is preferred, 3308 // since it's a shorter expansion. However, we would need to figure out the 3309 // preferred boolean type for the carry out for the query. 3310 if (LI.isLegalOrCustom({G_SMIN, Ty}) && LI.isLegalOrCustom({G_SMAX, Ty})) 3311 return lowerAddSubSatToMinMax(MI); 3312 return lowerAddSubSatToAddoSubo(MI); 3313 } 3314 case G_SSHLSAT: 3315 case G_USHLSAT: 3316 return lowerShlSat(MI); 3317 case G_ABS: 3318 return lowerAbsToAddXor(MI); 3319 case G_SELECT: 3320 return lowerSelect(MI); 3321 case G_SDIVREM: 3322 case G_UDIVREM: 3323 return lowerDIVREM(MI); 3324 case G_FSHL: 3325 case G_FSHR: 3326 return lowerFunnelShift(MI); 3327 case G_ROTL: 3328 case G_ROTR: 3329 return lowerRotate(MI); 3330 } 3331 } 3332 3333 Align LegalizerHelper::getStackTemporaryAlignment(LLT Ty, 3334 Align MinAlign) const { 3335 // FIXME: We're missing a way to go back from LLT to llvm::Type to query the 3336 // datalayout for the preferred alignment. Also there should be a target hook 3337 // for this to allow targets to reduce the alignment and ignore the 3338 // datalayout. e.g. AMDGPU should always use a 4-byte alignment, regardless of 3339 // the type. 3340 return std::max(Align(PowerOf2Ceil(Ty.getSizeInBytes())), MinAlign); 3341 } 3342 3343 MachineInstrBuilder 3344 LegalizerHelper::createStackTemporary(TypeSize Bytes, Align Alignment, 3345 MachinePointerInfo &PtrInfo) { 3346 MachineFunction &MF = MIRBuilder.getMF(); 3347 const DataLayout &DL = MIRBuilder.getDataLayout(); 3348 int FrameIdx = MF.getFrameInfo().CreateStackObject(Bytes, Alignment, false); 3349 3350 unsigned AddrSpace = DL.getAllocaAddrSpace(); 3351 LLT FramePtrTy = LLT::pointer(AddrSpace, DL.getPointerSizeInBits(AddrSpace)); 3352 3353 PtrInfo = MachinePointerInfo::getFixedStack(MF, FrameIdx); 3354 return MIRBuilder.buildFrameIndex(FramePtrTy, FrameIdx); 3355 } 3356 3357 static Register clampDynamicVectorIndex(MachineIRBuilder &B, Register IdxReg, 3358 LLT VecTy) { 3359 int64_t IdxVal; 3360 if (mi_match(IdxReg, *B.getMRI(), m_ICst(IdxVal))) 3361 return IdxReg; 3362 3363 LLT IdxTy = B.getMRI()->getType(IdxReg); 3364 unsigned NElts = VecTy.getNumElements(); 3365 if (isPowerOf2_32(NElts)) { 3366 APInt Imm = APInt::getLowBitsSet(IdxTy.getSizeInBits(), Log2_32(NElts)); 3367 return B.buildAnd(IdxTy, IdxReg, B.buildConstant(IdxTy, Imm)).getReg(0); 3368 } 3369 3370 return B.buildUMin(IdxTy, IdxReg, B.buildConstant(IdxTy, NElts - 1)) 3371 .getReg(0); 3372 } 3373 3374 Register LegalizerHelper::getVectorElementPointer(Register VecPtr, LLT VecTy, 3375 Register Index) { 3376 LLT EltTy = VecTy.getElementType(); 3377 3378 // Calculate the element offset and add it to the pointer. 3379 unsigned EltSize = EltTy.getSizeInBits() / 8; // FIXME: should be ABI size. 3380 assert(EltSize * 8 == EltTy.getSizeInBits() && 3381 "Converting bits to bytes lost precision"); 3382 3383 Index = clampDynamicVectorIndex(MIRBuilder, Index, VecTy); 3384 3385 LLT IdxTy = MRI.getType(Index); 3386 auto Mul = MIRBuilder.buildMul(IdxTy, Index, 3387 MIRBuilder.buildConstant(IdxTy, EltSize)); 3388 3389 LLT PtrTy = MRI.getType(VecPtr); 3390 return MIRBuilder.buildPtrAdd(PtrTy, VecPtr, Mul).getReg(0); 3391 } 3392 3393 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef( 3394 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) { 3395 Register DstReg = MI.getOperand(0).getReg(); 3396 LLT DstTy = MRI.getType(DstReg); 3397 LLT LCMTy = getLCMType(DstTy, NarrowTy); 3398 3399 unsigned NumParts = LCMTy.getSizeInBits() / NarrowTy.getSizeInBits(); 3400 3401 auto NewUndef = MIRBuilder.buildUndef(NarrowTy); 3402 SmallVector<Register, 8> Parts(NumParts, NewUndef.getReg(0)); 3403 3404 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3405 MI.eraseFromParent(); 3406 return Legalized; 3407 } 3408 3409 // Handle splitting vector operations which need to have the same number of 3410 // elements in each type index, but each type index may have a different element 3411 // type. 3412 // 3413 // e.g. <4 x s64> = G_SHL <4 x s64>, <4 x s32> -> 3414 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3415 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3416 // 3417 // Also handles some irregular breakdown cases, e.g. 3418 // e.g. <3 x s64> = G_SHL <3 x s64>, <3 x s32> -> 3419 // <2 x s64> = G_SHL <2 x s64>, <2 x s32> 3420 // s64 = G_SHL s64, s32 3421 LegalizerHelper::LegalizeResult 3422 LegalizerHelper::fewerElementsVectorMultiEltType( 3423 MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) { 3424 if (TypeIdx != 0) 3425 return UnableToLegalize; 3426 3427 const LLT NarrowTy0 = NarrowTyArg; 3428 const Register DstReg = MI.getOperand(0).getReg(); 3429 LLT DstTy = MRI.getType(DstReg); 3430 LLT LeftoverTy0; 3431 3432 // All of the operands need to have the same number of elements, so if we can 3433 // determine a type breakdown for the result type, we can for all of the 3434 // source types. 3435 int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first; 3436 if (NumParts < 0) 3437 return UnableToLegalize; 3438 3439 SmallVector<MachineInstrBuilder, 4> NewInsts; 3440 3441 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3442 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3443 3444 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) { 3445 Register SrcReg = MI.getOperand(I).getReg(); 3446 LLT SrcTyI = MRI.getType(SrcReg); 3447 const auto NewEC = NarrowTy0.isVector() ? NarrowTy0.getElementCount() 3448 : ElementCount::getFixed(1); 3449 LLT NarrowTyI = LLT::scalarOrVector(NewEC, SrcTyI.getScalarType()); 3450 LLT LeftoverTyI; 3451 3452 // Split this operand into the requested typed registers, and any leftover 3453 // required to reproduce the original type. 3454 if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs, 3455 LeftoverRegs)) 3456 return UnableToLegalize; 3457 3458 if (I == 1) { 3459 // For the first operand, create an instruction for each part and setup 3460 // the result. 3461 for (Register PartReg : PartRegs) { 3462 Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3463 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3464 .addDef(PartDstReg) 3465 .addUse(PartReg)); 3466 DstRegs.push_back(PartDstReg); 3467 } 3468 3469 for (Register LeftoverReg : LeftoverRegs) { 3470 Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0); 3471 NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode()) 3472 .addDef(PartDstReg) 3473 .addUse(LeftoverReg)); 3474 LeftoverDstRegs.push_back(PartDstReg); 3475 } 3476 } else { 3477 assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size()); 3478 3479 // Add the newly created operand splits to the existing instructions. The 3480 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3481 // pieces. 3482 unsigned InstCount = 0; 3483 for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J) 3484 NewInsts[InstCount++].addUse(PartRegs[J]); 3485 for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J) 3486 NewInsts[InstCount++].addUse(LeftoverRegs[J]); 3487 } 3488 3489 PartRegs.clear(); 3490 LeftoverRegs.clear(); 3491 } 3492 3493 // Insert the newly built operations and rebuild the result register. 3494 for (auto &MIB : NewInsts) 3495 MIRBuilder.insertInstr(MIB); 3496 3497 insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs); 3498 3499 MI.eraseFromParent(); 3500 return Legalized; 3501 } 3502 3503 LegalizerHelper::LegalizeResult 3504 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx, 3505 LLT NarrowTy) { 3506 if (TypeIdx != 0) 3507 return UnableToLegalize; 3508 3509 Register DstReg = MI.getOperand(0).getReg(); 3510 Register SrcReg = MI.getOperand(1).getReg(); 3511 LLT DstTy = MRI.getType(DstReg); 3512 LLT SrcTy = MRI.getType(SrcReg); 3513 3514 LLT NarrowTy0 = NarrowTy; 3515 LLT NarrowTy1; 3516 unsigned NumParts; 3517 3518 if (NarrowTy.isVector()) { 3519 // Uneven breakdown not handled. 3520 NumParts = DstTy.getNumElements() / NarrowTy.getNumElements(); 3521 if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements()) 3522 return UnableToLegalize; 3523 3524 NarrowTy1 = LLT::vector(NarrowTy.getElementCount(), SrcTy.getElementType()); 3525 } else { 3526 NumParts = DstTy.getNumElements(); 3527 NarrowTy1 = SrcTy.getElementType(); 3528 } 3529 3530 SmallVector<Register, 4> SrcRegs, DstRegs; 3531 extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs); 3532 3533 for (unsigned I = 0; I < NumParts; ++I) { 3534 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3535 MachineInstr *NewInst = 3536 MIRBuilder.buildInstr(MI.getOpcode(), {DstReg}, {SrcRegs[I]}); 3537 3538 NewInst->setFlags(MI.getFlags()); 3539 DstRegs.push_back(DstReg); 3540 } 3541 3542 if (NarrowTy.isVector()) 3543 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3544 else 3545 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3546 3547 MI.eraseFromParent(); 3548 return Legalized; 3549 } 3550 3551 LegalizerHelper::LegalizeResult 3552 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx, 3553 LLT NarrowTy) { 3554 Register DstReg = MI.getOperand(0).getReg(); 3555 Register Src0Reg = MI.getOperand(2).getReg(); 3556 LLT DstTy = MRI.getType(DstReg); 3557 LLT SrcTy = MRI.getType(Src0Reg); 3558 3559 unsigned NumParts; 3560 LLT NarrowTy0, NarrowTy1; 3561 3562 if (TypeIdx == 0) { 3563 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3564 unsigned OldElts = DstTy.getNumElements(); 3565 3566 NarrowTy0 = NarrowTy; 3567 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements(); 3568 NarrowTy1 = NarrowTy.isVector() ? LLT::vector(NarrowTy.getElementCount(), 3569 SrcTy.getScalarSizeInBits()) 3570 : SrcTy.getElementType(); 3571 3572 } else { 3573 unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1; 3574 unsigned OldElts = SrcTy.getNumElements(); 3575 3576 NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : 3577 NarrowTy.getNumElements(); 3578 NarrowTy0 = 3579 LLT::vector(NarrowTy.getElementCount(), DstTy.getScalarSizeInBits()); 3580 NarrowTy1 = NarrowTy; 3581 } 3582 3583 // FIXME: Don't know how to handle the situation where the small vectors 3584 // aren't all the same size yet. 3585 if (NarrowTy1.isVector() && 3586 NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements()) 3587 return UnableToLegalize; 3588 3589 CmpInst::Predicate Pred 3590 = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()); 3591 3592 SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs; 3593 extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs); 3594 extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs); 3595 3596 for (unsigned I = 0; I < NumParts; ++I) { 3597 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3598 DstRegs.push_back(DstReg); 3599 3600 if (MI.getOpcode() == TargetOpcode::G_ICMP) 3601 MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3602 else { 3603 MachineInstr *NewCmp 3604 = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]); 3605 NewCmp->setFlags(MI.getFlags()); 3606 } 3607 } 3608 3609 if (NarrowTy1.isVector()) 3610 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3611 else 3612 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3613 3614 MI.eraseFromParent(); 3615 return Legalized; 3616 } 3617 3618 LegalizerHelper::LegalizeResult 3619 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, 3620 LLT NarrowTy) { 3621 Register DstReg = MI.getOperand(0).getReg(); 3622 Register CondReg = MI.getOperand(1).getReg(); 3623 3624 unsigned NumParts = 0; 3625 LLT NarrowTy0, NarrowTy1; 3626 3627 LLT DstTy = MRI.getType(DstReg); 3628 LLT CondTy = MRI.getType(CondReg); 3629 unsigned Size = DstTy.getSizeInBits(); 3630 3631 assert(TypeIdx == 0 || CondTy.isVector()); 3632 3633 if (TypeIdx == 0) { 3634 NarrowTy0 = NarrowTy; 3635 NarrowTy1 = CondTy; 3636 3637 unsigned NarrowSize = NarrowTy0.getSizeInBits(); 3638 // FIXME: Don't know how to handle the situation where the small vectors 3639 // aren't all the same size yet. 3640 if (Size % NarrowSize != 0) 3641 return UnableToLegalize; 3642 3643 NumParts = Size / NarrowSize; 3644 3645 // Need to break down the condition type 3646 if (CondTy.isVector()) { 3647 if (CondTy.getNumElements() == NumParts) 3648 NarrowTy1 = CondTy.getElementType(); 3649 else 3650 NarrowTy1 = 3651 LLT::vector(CondTy.getElementCount().divideCoefficientBy(NumParts), 3652 CondTy.getScalarSizeInBits()); 3653 } 3654 } else { 3655 NumParts = CondTy.getNumElements(); 3656 if (NarrowTy.isVector()) { 3657 // TODO: Handle uneven breakdown. 3658 if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements()) 3659 return UnableToLegalize; 3660 3661 return UnableToLegalize; 3662 } else { 3663 NarrowTy0 = DstTy.getElementType(); 3664 NarrowTy1 = NarrowTy; 3665 } 3666 } 3667 3668 SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs; 3669 if (CondTy.isVector()) 3670 extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs); 3671 3672 extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs); 3673 extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs); 3674 3675 for (unsigned i = 0; i < NumParts; ++i) { 3676 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0); 3677 MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg, 3678 Src1Regs[i], Src2Regs[i]); 3679 DstRegs.push_back(DstReg); 3680 } 3681 3682 if (NarrowTy0.isVector()) 3683 MIRBuilder.buildConcatVectors(DstReg, DstRegs); 3684 else 3685 MIRBuilder.buildBuildVector(DstReg, DstRegs); 3686 3687 MI.eraseFromParent(); 3688 return Legalized; 3689 } 3690 3691 LegalizerHelper::LegalizeResult 3692 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 3693 LLT NarrowTy) { 3694 const Register DstReg = MI.getOperand(0).getReg(); 3695 LLT PhiTy = MRI.getType(DstReg); 3696 LLT LeftoverTy; 3697 3698 // All of the operands need to have the same number of elements, so if we can 3699 // determine a type breakdown for the result type, we can for all of the 3700 // source types. 3701 int NumParts, NumLeftover; 3702 std::tie(NumParts, NumLeftover) 3703 = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy); 3704 if (NumParts < 0) 3705 return UnableToLegalize; 3706 3707 SmallVector<Register, 4> DstRegs, LeftoverDstRegs; 3708 SmallVector<MachineInstrBuilder, 4> NewInsts; 3709 3710 const int TotalNumParts = NumParts + NumLeftover; 3711 3712 // Insert the new phis in the result block first. 3713 for (int I = 0; I != TotalNumParts; ++I) { 3714 LLT Ty = I < NumParts ? NarrowTy : LeftoverTy; 3715 Register PartDstReg = MRI.createGenericVirtualRegister(Ty); 3716 NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI) 3717 .addDef(PartDstReg)); 3718 if (I < NumParts) 3719 DstRegs.push_back(PartDstReg); 3720 else 3721 LeftoverDstRegs.push_back(PartDstReg); 3722 } 3723 3724 MachineBasicBlock *MBB = MI.getParent(); 3725 MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI()); 3726 insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs); 3727 3728 SmallVector<Register, 4> PartRegs, LeftoverRegs; 3729 3730 // Insert code to extract the incoming values in each predecessor block. 3731 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 3732 PartRegs.clear(); 3733 LeftoverRegs.clear(); 3734 3735 Register SrcReg = MI.getOperand(I).getReg(); 3736 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 3737 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 3738 3739 LLT Unused; 3740 if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs, 3741 LeftoverRegs)) 3742 return UnableToLegalize; 3743 3744 // Add the newly created operand splits to the existing instructions. The 3745 // odd-sized pieces are ordered after the requested NarrowTyArg sized 3746 // pieces. 3747 for (int J = 0; J != TotalNumParts; ++J) { 3748 MachineInstrBuilder MIB = NewInsts[J]; 3749 MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]); 3750 MIB.addMBB(&OpMBB); 3751 } 3752 } 3753 3754 MI.eraseFromParent(); 3755 return Legalized; 3756 } 3757 3758 LegalizerHelper::LegalizeResult 3759 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI, 3760 unsigned TypeIdx, 3761 LLT NarrowTy) { 3762 if (TypeIdx != 1) 3763 return UnableToLegalize; 3764 3765 const int NumDst = MI.getNumOperands() - 1; 3766 const Register SrcReg = MI.getOperand(NumDst).getReg(); 3767 LLT SrcTy = MRI.getType(SrcReg); 3768 3769 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 3770 3771 // TODO: Create sequence of extracts. 3772 if (DstTy == NarrowTy) 3773 return UnableToLegalize; 3774 3775 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3776 if (DstTy == GCDTy) { 3777 // This would just be a copy of the same unmerge. 3778 // TODO: Create extracts, pad with undef and create intermediate merges. 3779 return UnableToLegalize; 3780 } 3781 3782 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg); 3783 const int NumUnmerge = Unmerge->getNumOperands() - 1; 3784 const int PartsPerUnmerge = NumDst / NumUnmerge; 3785 3786 for (int I = 0; I != NumUnmerge; ++I) { 3787 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 3788 3789 for (int J = 0; J != PartsPerUnmerge; ++J) 3790 MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg()); 3791 MIB.addUse(Unmerge.getReg(I)); 3792 } 3793 3794 MI.eraseFromParent(); 3795 return Legalized; 3796 } 3797 3798 LegalizerHelper::LegalizeResult 3799 LegalizerHelper::fewerElementsVectorMulo(MachineInstr &MI, unsigned TypeIdx, 3800 LLT NarrowTy) { 3801 Register Result = MI.getOperand(0).getReg(); 3802 Register Overflow = MI.getOperand(1).getReg(); 3803 Register LHS = MI.getOperand(2).getReg(); 3804 Register RHS = MI.getOperand(3).getReg(); 3805 3806 LLT SrcTy = MRI.getType(LHS); 3807 if (!SrcTy.isVector()) 3808 return UnableToLegalize; 3809 3810 LLT ElementType = SrcTy.getElementType(); 3811 LLT OverflowElementTy = MRI.getType(Overflow).getElementType(); 3812 const ElementCount NumResult = SrcTy.getElementCount(); 3813 LLT GCDTy = getGCDType(SrcTy, NarrowTy); 3814 3815 // Unmerge the operands to smaller parts of GCD type. 3816 auto UnmergeLHS = MIRBuilder.buildUnmerge(GCDTy, LHS); 3817 auto UnmergeRHS = MIRBuilder.buildUnmerge(GCDTy, RHS); 3818 3819 const int NumOps = UnmergeLHS->getNumOperands() - 1; 3820 const ElementCount PartsPerUnmerge = NumResult.divideCoefficientBy(NumOps); 3821 LLT OverflowTy = LLT::scalarOrVector(PartsPerUnmerge, OverflowElementTy); 3822 LLT ResultTy = LLT::scalarOrVector(PartsPerUnmerge, ElementType); 3823 3824 // Perform the operation over unmerged parts. 3825 SmallVector<Register, 8> ResultParts; 3826 SmallVector<Register, 8> OverflowParts; 3827 for (int I = 0; I != NumOps; ++I) { 3828 Register Operand1 = UnmergeLHS->getOperand(I).getReg(); 3829 Register Operand2 = UnmergeRHS->getOperand(I).getReg(); 3830 auto PartMul = MIRBuilder.buildInstr(MI.getOpcode(), {ResultTy, OverflowTy}, 3831 {Operand1, Operand2}); 3832 ResultParts.push_back(PartMul->getOperand(0).getReg()); 3833 OverflowParts.push_back(PartMul->getOperand(1).getReg()); 3834 } 3835 3836 LLT ResultLCMTy = buildLCMMergePieces(SrcTy, NarrowTy, GCDTy, ResultParts); 3837 LLT OverflowLCMTy = 3838 LLT::scalarOrVector(ResultLCMTy.getElementCount(), OverflowElementTy); 3839 3840 // Recombine the pieces to the original result and overflow registers. 3841 buildWidenedRemergeToDst(Result, ResultLCMTy, ResultParts); 3842 buildWidenedRemergeToDst(Overflow, OverflowLCMTy, OverflowParts); 3843 MI.eraseFromParent(); 3844 return Legalized; 3845 } 3846 3847 // Handle FewerElementsVector a G_BUILD_VECTOR or G_CONCAT_VECTORS that produces 3848 // a vector 3849 // 3850 // Create a G_BUILD_VECTOR or G_CONCAT_VECTORS of NarrowTy pieces, padding with 3851 // undef as necessary. 3852 // 3853 // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2 3854 // -> <2 x s16> 3855 // 3856 // %4:_(s16) = G_IMPLICIT_DEF 3857 // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1 3858 // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4 3859 // %7:_(<2 x s16>) = G_IMPLICIT_DEF 3860 // %8:_(<6 x s16>) = G_CONCAT_VECTORS %5, %6, %7 3861 // %3:_(<3 x s16>), %8:_(<3 x s16>) = G_UNMERGE_VALUES %8 3862 LegalizerHelper::LegalizeResult 3863 LegalizerHelper::fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx, 3864 LLT NarrowTy) { 3865 Register DstReg = MI.getOperand(0).getReg(); 3866 LLT DstTy = MRI.getType(DstReg); 3867 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 3868 LLT GCDTy = getGCDType(getGCDType(SrcTy, NarrowTy), DstTy); 3869 3870 // Break into a common type 3871 SmallVector<Register, 16> Parts; 3872 for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) 3873 extractGCDType(Parts, GCDTy, MI.getOperand(I).getReg()); 3874 3875 // Build the requested new merge, padding with undef. 3876 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, 3877 TargetOpcode::G_ANYEXT); 3878 3879 // Pack into the original result register. 3880 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 3881 3882 MI.eraseFromParent(); 3883 return Legalized; 3884 } 3885 3886 LegalizerHelper::LegalizeResult 3887 LegalizerHelper::fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI, 3888 unsigned TypeIdx, 3889 LLT NarrowVecTy) { 3890 Register DstReg = MI.getOperand(0).getReg(); 3891 Register SrcVec = MI.getOperand(1).getReg(); 3892 Register InsertVal; 3893 bool IsInsert = MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT; 3894 3895 assert((IsInsert ? TypeIdx == 0 : TypeIdx == 1) && "not a vector type index"); 3896 if (IsInsert) 3897 InsertVal = MI.getOperand(2).getReg(); 3898 3899 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 3900 3901 // TODO: Handle total scalarization case. 3902 if (!NarrowVecTy.isVector()) 3903 return UnableToLegalize; 3904 3905 LLT VecTy = MRI.getType(SrcVec); 3906 3907 // If the index is a constant, we can really break this down as you would 3908 // expect, and index into the target size pieces. 3909 int64_t IdxVal; 3910 auto MaybeCst = 3911 getConstantVRegValWithLookThrough(Idx, MRI, /*LookThroughInstrs*/ true, 3912 /*HandleFConstants*/ false); 3913 if (MaybeCst) { 3914 IdxVal = MaybeCst->Value.getSExtValue(); 3915 // Avoid out of bounds indexing the pieces. 3916 if (IdxVal >= VecTy.getNumElements()) { 3917 MIRBuilder.buildUndef(DstReg); 3918 MI.eraseFromParent(); 3919 return Legalized; 3920 } 3921 3922 SmallVector<Register, 8> VecParts; 3923 LLT GCDTy = extractGCDType(VecParts, VecTy, NarrowVecTy, SrcVec); 3924 3925 // Build a sequence of NarrowTy pieces in VecParts for this operand. 3926 LLT LCMTy = buildLCMMergePieces(VecTy, NarrowVecTy, GCDTy, VecParts, 3927 TargetOpcode::G_ANYEXT); 3928 3929 unsigned NewNumElts = NarrowVecTy.getNumElements(); 3930 3931 LLT IdxTy = MRI.getType(Idx); 3932 int64_t PartIdx = IdxVal / NewNumElts; 3933 auto NewIdx = 3934 MIRBuilder.buildConstant(IdxTy, IdxVal - NewNumElts * PartIdx); 3935 3936 if (IsInsert) { 3937 LLT PartTy = MRI.getType(VecParts[PartIdx]); 3938 3939 // Use the adjusted index to insert into one of the subvectors. 3940 auto InsertPart = MIRBuilder.buildInsertVectorElement( 3941 PartTy, VecParts[PartIdx], InsertVal, NewIdx); 3942 VecParts[PartIdx] = InsertPart.getReg(0); 3943 3944 // Recombine the inserted subvector with the others to reform the result 3945 // vector. 3946 buildWidenedRemergeToDst(DstReg, LCMTy, VecParts); 3947 } else { 3948 MIRBuilder.buildExtractVectorElement(DstReg, VecParts[PartIdx], NewIdx); 3949 } 3950 3951 MI.eraseFromParent(); 3952 return Legalized; 3953 } 3954 3955 // With a variable index, we can't perform the operation in a smaller type, so 3956 // we're forced to expand this. 3957 // 3958 // TODO: We could emit a chain of compare/select to figure out which piece to 3959 // index. 3960 return lowerExtractInsertVectorElt(MI); 3961 } 3962 3963 LegalizerHelper::LegalizeResult 3964 LegalizerHelper::reduceLoadStoreWidth(GLoadStore &LdStMI, unsigned TypeIdx, 3965 LLT NarrowTy) { 3966 // FIXME: Don't know how to handle secondary types yet. 3967 if (TypeIdx != 0) 3968 return UnableToLegalize; 3969 3970 // This implementation doesn't work for atomics. Give up instead of doing 3971 // something invalid. 3972 if (LdStMI.isAtomic()) 3973 return UnableToLegalize; 3974 3975 bool IsLoad = isa<GLoad>(LdStMI); 3976 Register ValReg = LdStMI.getReg(0); 3977 Register AddrReg = LdStMI.getPointerReg(); 3978 LLT ValTy = MRI.getType(ValReg); 3979 3980 // FIXME: Do we need a distinct NarrowMemory legalize action? 3981 if (ValTy.getSizeInBits() != 8 * LdStMI.getMemSize()) { 3982 LLVM_DEBUG(dbgs() << "Can't narrow extload/truncstore\n"); 3983 return UnableToLegalize; 3984 } 3985 3986 int NumParts = -1; 3987 int NumLeftover = -1; 3988 LLT LeftoverTy; 3989 SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs; 3990 if (IsLoad) { 3991 std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy); 3992 } else { 3993 if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs, 3994 NarrowLeftoverRegs)) { 3995 NumParts = NarrowRegs.size(); 3996 NumLeftover = NarrowLeftoverRegs.size(); 3997 } 3998 } 3999 4000 if (NumParts == -1) 4001 return UnableToLegalize; 4002 4003 LLT PtrTy = MRI.getType(AddrReg); 4004 const LLT OffsetTy = LLT::scalar(PtrTy.getSizeInBits()); 4005 4006 unsigned TotalSize = ValTy.getSizeInBits(); 4007 4008 // Split the load/store into PartTy sized pieces starting at Offset. If this 4009 // is a load, return the new registers in ValRegs. For a store, each elements 4010 // of ValRegs should be PartTy. Returns the next offset that needs to be 4011 // handled. 4012 auto MMO = LdStMI.getMMO(); 4013 auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs, 4014 unsigned Offset) -> unsigned { 4015 MachineFunction &MF = MIRBuilder.getMF(); 4016 unsigned PartSize = PartTy.getSizeInBits(); 4017 for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize; 4018 Offset += PartSize, ++Idx) { 4019 unsigned ByteOffset = Offset / 8; 4020 Register NewAddrReg; 4021 4022 MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset); 4023 4024 MachineMemOperand *NewMMO = 4025 MF.getMachineMemOperand(&MMO, ByteOffset, PartTy); 4026 4027 if (IsLoad) { 4028 Register Dst = MRI.createGenericVirtualRegister(PartTy); 4029 ValRegs.push_back(Dst); 4030 MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO); 4031 } else { 4032 MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO); 4033 } 4034 } 4035 4036 return Offset; 4037 }; 4038 4039 unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0); 4040 4041 // Handle the rest of the register if this isn't an even type breakdown. 4042 if (LeftoverTy.isValid()) 4043 splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset); 4044 4045 if (IsLoad) { 4046 insertParts(ValReg, ValTy, NarrowTy, NarrowRegs, 4047 LeftoverTy, NarrowLeftoverRegs); 4048 } 4049 4050 LdStMI.eraseFromParent(); 4051 return Legalized; 4052 } 4053 4054 LegalizerHelper::LegalizeResult 4055 LegalizerHelper::reduceOperationWidth(MachineInstr &MI, unsigned int TypeIdx, 4056 LLT NarrowTy) { 4057 assert(TypeIdx == 0 && "only one type index expected"); 4058 4059 const unsigned Opc = MI.getOpcode(); 4060 const int NumDefOps = MI.getNumExplicitDefs(); 4061 const int NumSrcOps = MI.getNumOperands() - NumDefOps; 4062 const unsigned Flags = MI.getFlags(); 4063 const unsigned NarrowSize = NarrowTy.getSizeInBits(); 4064 const LLT NarrowScalarTy = LLT::scalar(NarrowSize); 4065 4066 assert(MI.getNumOperands() <= 4 && "expected instruction with either 1 " 4067 "result and 1-3 sources or 2 results and " 4068 "1-2 sources"); 4069 4070 SmallVector<Register, 2> DstRegs; 4071 for (int I = 0; I < NumDefOps; ++I) 4072 DstRegs.push_back(MI.getOperand(I).getReg()); 4073 4074 // First of all check whether we are narrowing (changing the element type) 4075 // or reducing the vector elements 4076 const LLT DstTy = MRI.getType(DstRegs[0]); 4077 const bool IsNarrow = NarrowTy.getScalarType() != DstTy.getScalarType(); 4078 4079 SmallVector<Register, 8> ExtractedRegs[3]; 4080 SmallVector<Register, 8> Parts; 4081 4082 // Break down all the sources into NarrowTy pieces we can operate on. This may 4083 // involve creating merges to a wider type, padded with undef. 4084 for (int I = 0; I != NumSrcOps; ++I) { 4085 Register SrcReg = MI.getOperand(I + NumDefOps).getReg(); 4086 LLT SrcTy = MRI.getType(SrcReg); 4087 4088 // The type to narrow SrcReg to. For narrowing, this is a smaller scalar. 4089 // For fewerElements, this is a smaller vector with the same element type. 4090 LLT OpNarrowTy; 4091 if (IsNarrow) { 4092 OpNarrowTy = NarrowScalarTy; 4093 4094 // In case of narrowing, we need to cast vectors to scalars for this to 4095 // work properly 4096 // FIXME: Can we do without the bitcast here if we're narrowing? 4097 if (SrcTy.isVector()) { 4098 SrcTy = LLT::scalar(SrcTy.getSizeInBits()); 4099 SrcReg = MIRBuilder.buildBitcast(SrcTy, SrcReg).getReg(0); 4100 } 4101 } else { 4102 auto NarrowEC = NarrowTy.isVector() ? NarrowTy.getElementCount() 4103 : ElementCount::getFixed(1); 4104 OpNarrowTy = LLT::scalarOrVector(NarrowEC, SrcTy.getScalarType()); 4105 } 4106 4107 LLT GCDTy = extractGCDType(ExtractedRegs[I], SrcTy, OpNarrowTy, SrcReg); 4108 4109 // Build a sequence of NarrowTy pieces in ExtractedRegs for this operand. 4110 buildLCMMergePieces(SrcTy, OpNarrowTy, GCDTy, ExtractedRegs[I], 4111 TargetOpcode::G_ANYEXT); 4112 } 4113 4114 SmallVector<Register, 8> ResultRegs[2]; 4115 4116 // Input operands for each sub-instruction. 4117 SmallVector<SrcOp, 4> InputRegs(NumSrcOps, Register()); 4118 4119 int NumParts = ExtractedRegs[0].size(); 4120 const unsigned DstSize = DstTy.getSizeInBits(); 4121 const LLT DstScalarTy = LLT::scalar(DstSize); 4122 4123 // Narrowing needs to use scalar types 4124 LLT DstLCMTy, NarrowDstTy; 4125 if (IsNarrow) { 4126 DstLCMTy = getLCMType(DstScalarTy, NarrowScalarTy); 4127 NarrowDstTy = NarrowScalarTy; 4128 } else { 4129 DstLCMTy = getLCMType(DstTy, NarrowTy); 4130 NarrowDstTy = NarrowTy; 4131 } 4132 4133 // We widened the source registers to satisfy merge/unmerge size 4134 // constraints. We'll have some extra fully undef parts. 4135 const int NumRealParts = (DstSize + NarrowSize - 1) / NarrowSize; 4136 4137 for (int I = 0; I != NumRealParts; ++I) { 4138 // Emit this instruction on each of the split pieces. 4139 for (int J = 0; J != NumSrcOps; ++J) 4140 InputRegs[J] = ExtractedRegs[J][I]; 4141 4142 MachineInstrBuilder Inst; 4143 if (NumDefOps == 1) 4144 Inst = MIRBuilder.buildInstr(Opc, {NarrowDstTy}, InputRegs, Flags); 4145 else 4146 Inst = MIRBuilder.buildInstr(Opc, {NarrowDstTy, NarrowDstTy}, InputRegs, 4147 Flags); 4148 4149 for (int J = 0; J != NumDefOps; ++J) 4150 ResultRegs[J].push_back(Inst.getReg(J)); 4151 } 4152 4153 // Fill out the widened result with undef instead of creating instructions 4154 // with undef inputs. 4155 int NumUndefParts = NumParts - NumRealParts; 4156 if (NumUndefParts != 0) { 4157 Register Undef = MIRBuilder.buildUndef(NarrowDstTy).getReg(0); 4158 for (int I = 0; I != NumDefOps; ++I) 4159 ResultRegs[I].append(NumUndefParts, Undef); 4160 } 4161 4162 // Extract the possibly padded result. Use a scratch register if we need to do 4163 // a final bitcast, otherwise use the original result register. 4164 Register MergeDstReg; 4165 for (int I = 0; I != NumDefOps; ++I) { 4166 if (IsNarrow && DstTy.isVector()) 4167 MergeDstReg = MRI.createGenericVirtualRegister(DstScalarTy); 4168 else 4169 MergeDstReg = DstRegs[I]; 4170 4171 buildWidenedRemergeToDst(MergeDstReg, DstLCMTy, ResultRegs[I]); 4172 4173 // Recast to vector if we narrowed a vector 4174 if (IsNarrow && DstTy.isVector()) 4175 MIRBuilder.buildBitcast(DstRegs[I], MergeDstReg); 4176 } 4177 4178 MI.eraseFromParent(); 4179 return Legalized; 4180 } 4181 4182 LegalizerHelper::LegalizeResult 4183 LegalizerHelper::fewerElementsVectorSextInReg(MachineInstr &MI, unsigned TypeIdx, 4184 LLT NarrowTy) { 4185 Register DstReg = MI.getOperand(0).getReg(); 4186 Register SrcReg = MI.getOperand(1).getReg(); 4187 int64_t Imm = MI.getOperand(2).getImm(); 4188 4189 LLT DstTy = MRI.getType(DstReg); 4190 4191 SmallVector<Register, 8> Parts; 4192 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 4193 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts); 4194 4195 for (Register &R : Parts) 4196 R = MIRBuilder.buildSExtInReg(NarrowTy, R, Imm).getReg(0); 4197 4198 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 4199 4200 MI.eraseFromParent(); 4201 return Legalized; 4202 } 4203 4204 LegalizerHelper::LegalizeResult 4205 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, 4206 LLT NarrowTy) { 4207 using namespace TargetOpcode; 4208 4209 switch (MI.getOpcode()) { 4210 case G_IMPLICIT_DEF: 4211 return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy); 4212 case G_TRUNC: 4213 case G_AND: 4214 case G_OR: 4215 case G_XOR: 4216 case G_ADD: 4217 case G_SUB: 4218 case G_MUL: 4219 case G_PTR_ADD: 4220 case G_SMULH: 4221 case G_UMULH: 4222 case G_FADD: 4223 case G_FMUL: 4224 case G_FSUB: 4225 case G_FNEG: 4226 case G_FABS: 4227 case G_FCANONICALIZE: 4228 case G_FDIV: 4229 case G_FREM: 4230 case G_FMA: 4231 case G_FMAD: 4232 case G_FPOW: 4233 case G_FEXP: 4234 case G_FEXP2: 4235 case G_FLOG: 4236 case G_FLOG2: 4237 case G_FLOG10: 4238 case G_FNEARBYINT: 4239 case G_FCEIL: 4240 case G_FFLOOR: 4241 case G_FRINT: 4242 case G_INTRINSIC_ROUND: 4243 case G_INTRINSIC_ROUNDEVEN: 4244 case G_INTRINSIC_TRUNC: 4245 case G_FCOS: 4246 case G_FSIN: 4247 case G_FSQRT: 4248 case G_BSWAP: 4249 case G_BITREVERSE: 4250 case G_SDIV: 4251 case G_UDIV: 4252 case G_SREM: 4253 case G_UREM: 4254 case G_SDIVREM: 4255 case G_UDIVREM: 4256 case G_SMIN: 4257 case G_SMAX: 4258 case G_UMIN: 4259 case G_UMAX: 4260 case G_ABS: 4261 case G_FMINNUM: 4262 case G_FMAXNUM: 4263 case G_FMINNUM_IEEE: 4264 case G_FMAXNUM_IEEE: 4265 case G_FMINIMUM: 4266 case G_FMAXIMUM: 4267 case G_FSHL: 4268 case G_FSHR: 4269 case G_FREEZE: 4270 case G_SADDSAT: 4271 case G_SSUBSAT: 4272 case G_UADDSAT: 4273 case G_USUBSAT: 4274 return reduceOperationWidth(MI, TypeIdx, NarrowTy); 4275 case G_UMULO: 4276 case G_SMULO: 4277 return fewerElementsVectorMulo(MI, TypeIdx, NarrowTy); 4278 case G_SHL: 4279 case G_LSHR: 4280 case G_ASHR: 4281 case G_SSHLSAT: 4282 case G_USHLSAT: 4283 case G_CTLZ: 4284 case G_CTLZ_ZERO_UNDEF: 4285 case G_CTTZ: 4286 case G_CTTZ_ZERO_UNDEF: 4287 case G_CTPOP: 4288 case G_FCOPYSIGN: 4289 return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy); 4290 case G_ZEXT: 4291 case G_SEXT: 4292 case G_ANYEXT: 4293 case G_FPEXT: 4294 case G_FPTRUNC: 4295 case G_SITOFP: 4296 case G_UITOFP: 4297 case G_FPTOSI: 4298 case G_FPTOUI: 4299 case G_INTTOPTR: 4300 case G_PTRTOINT: 4301 case G_ADDRSPACE_CAST: 4302 return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy); 4303 case G_ICMP: 4304 case G_FCMP: 4305 return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy); 4306 case G_SELECT: 4307 return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy); 4308 case G_PHI: 4309 return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy); 4310 case G_UNMERGE_VALUES: 4311 return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy); 4312 case G_BUILD_VECTOR: 4313 assert(TypeIdx == 0 && "not a vector type index"); 4314 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4315 case G_CONCAT_VECTORS: 4316 if (TypeIdx != 1) // TODO: This probably does work as expected already. 4317 return UnableToLegalize; 4318 return fewerElementsVectorMerge(MI, TypeIdx, NarrowTy); 4319 case G_EXTRACT_VECTOR_ELT: 4320 case G_INSERT_VECTOR_ELT: 4321 return fewerElementsVectorExtractInsertVectorElt(MI, TypeIdx, NarrowTy); 4322 case G_LOAD: 4323 case G_STORE: 4324 return reduceLoadStoreWidth(cast<GLoadStore>(MI), TypeIdx, NarrowTy); 4325 case G_SEXT_INREG: 4326 return fewerElementsVectorSextInReg(MI, TypeIdx, NarrowTy); 4327 GISEL_VECREDUCE_CASES_NONSEQ 4328 return fewerElementsVectorReductions(MI, TypeIdx, NarrowTy); 4329 case G_SHUFFLE_VECTOR: 4330 return fewerElementsVectorShuffle(MI, TypeIdx, NarrowTy); 4331 default: 4332 return UnableToLegalize; 4333 } 4334 } 4335 4336 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorShuffle( 4337 MachineInstr &MI, unsigned int TypeIdx, LLT NarrowTy) { 4338 assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR); 4339 if (TypeIdx != 0) 4340 return UnableToLegalize; 4341 4342 Register DstReg = MI.getOperand(0).getReg(); 4343 Register Src1Reg = MI.getOperand(1).getReg(); 4344 Register Src2Reg = MI.getOperand(2).getReg(); 4345 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 4346 LLT DstTy = MRI.getType(DstReg); 4347 LLT Src1Ty = MRI.getType(Src1Reg); 4348 LLT Src2Ty = MRI.getType(Src2Reg); 4349 // The shuffle should be canonicalized by now. 4350 if (DstTy != Src1Ty) 4351 return UnableToLegalize; 4352 if (DstTy != Src2Ty) 4353 return UnableToLegalize; 4354 4355 if (!isPowerOf2_32(DstTy.getNumElements())) 4356 return UnableToLegalize; 4357 4358 // We only support splitting a shuffle into 2, so adjust NarrowTy accordingly. 4359 // Further legalization attempts will be needed to do split further. 4360 NarrowTy = 4361 DstTy.changeElementCount(DstTy.getElementCount().divideCoefficientBy(2)); 4362 unsigned NewElts = NarrowTy.getNumElements(); 4363 4364 SmallVector<Register> SplitSrc1Regs, SplitSrc2Regs; 4365 extractParts(Src1Reg, NarrowTy, 2, SplitSrc1Regs); 4366 extractParts(Src2Reg, NarrowTy, 2, SplitSrc2Regs); 4367 Register Inputs[4] = {SplitSrc1Regs[0], SplitSrc1Regs[1], SplitSrc2Regs[0], 4368 SplitSrc2Regs[1]}; 4369 4370 Register Hi, Lo; 4371 4372 // If Lo or Hi uses elements from at most two of the four input vectors, then 4373 // express it as a vector shuffle of those two inputs. Otherwise extract the 4374 // input elements by hand and construct the Lo/Hi output using a BUILD_VECTOR. 4375 SmallVector<int, 16> Ops; 4376 for (unsigned High = 0; High < 2; ++High) { 4377 Register &Output = High ? Hi : Lo; 4378 4379 // Build a shuffle mask for the output, discovering on the fly which 4380 // input vectors to use as shuffle operands (recorded in InputUsed). 4381 // If building a suitable shuffle vector proves too hard, then bail 4382 // out with useBuildVector set. 4383 unsigned InputUsed[2] = {-1U, -1U}; // Not yet discovered. 4384 unsigned FirstMaskIdx = High * NewElts; 4385 bool UseBuildVector = false; 4386 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 4387 // The mask element. This indexes into the input. 4388 int Idx = Mask[FirstMaskIdx + MaskOffset]; 4389 4390 // The input vector this mask element indexes into. 4391 unsigned Input = (unsigned)Idx / NewElts; 4392 4393 if (Input >= array_lengthof(Inputs)) { 4394 // The mask element does not index into any input vector. 4395 Ops.push_back(-1); 4396 continue; 4397 } 4398 4399 // Turn the index into an offset from the start of the input vector. 4400 Idx -= Input * NewElts; 4401 4402 // Find or create a shuffle vector operand to hold this input. 4403 unsigned OpNo; 4404 for (OpNo = 0; OpNo < array_lengthof(InputUsed); ++OpNo) { 4405 if (InputUsed[OpNo] == Input) { 4406 // This input vector is already an operand. 4407 break; 4408 } else if (InputUsed[OpNo] == -1U) { 4409 // Create a new operand for this input vector. 4410 InputUsed[OpNo] = Input; 4411 break; 4412 } 4413 } 4414 4415 if (OpNo >= array_lengthof(InputUsed)) { 4416 // More than two input vectors used! Give up on trying to create a 4417 // shuffle vector. Insert all elements into a BUILD_VECTOR instead. 4418 UseBuildVector = true; 4419 break; 4420 } 4421 4422 // Add the mask index for the new shuffle vector. 4423 Ops.push_back(Idx + OpNo * NewElts); 4424 } 4425 4426 if (UseBuildVector) { 4427 LLT EltTy = NarrowTy.getElementType(); 4428 SmallVector<Register, 16> SVOps; 4429 4430 // Extract the input elements by hand. 4431 for (unsigned MaskOffset = 0; MaskOffset < NewElts; ++MaskOffset) { 4432 // The mask element. This indexes into the input. 4433 int Idx = Mask[FirstMaskIdx + MaskOffset]; 4434 4435 // The input vector this mask element indexes into. 4436 unsigned Input = (unsigned)Idx / NewElts; 4437 4438 if (Input >= array_lengthof(Inputs)) { 4439 // The mask element is "undef" or indexes off the end of the input. 4440 SVOps.push_back(MIRBuilder.buildUndef(EltTy).getReg(0)); 4441 continue; 4442 } 4443 4444 // Turn the index into an offset from the start of the input vector. 4445 Idx -= Input * NewElts; 4446 4447 // Extract the vector element by hand. 4448 SVOps.push_back(MIRBuilder 4449 .buildExtractVectorElement( 4450 EltTy, Inputs[Input], 4451 MIRBuilder.buildConstant(LLT::scalar(32), Idx)) 4452 .getReg(0)); 4453 } 4454 4455 // Construct the Lo/Hi output using a G_BUILD_VECTOR. 4456 Output = MIRBuilder.buildBuildVector(NarrowTy, SVOps).getReg(0); 4457 } else if (InputUsed[0] == -1U) { 4458 // No input vectors were used! The result is undefined. 4459 Output = MIRBuilder.buildUndef(NarrowTy).getReg(0); 4460 } else { 4461 Register Op0 = Inputs[InputUsed[0]]; 4462 // If only one input was used, use an undefined vector for the other. 4463 Register Op1 = InputUsed[1] == -1U 4464 ? MIRBuilder.buildUndef(NarrowTy).getReg(0) 4465 : Inputs[InputUsed[1]]; 4466 // At least one input vector was used. Create a new shuffle vector. 4467 Output = MIRBuilder.buildShuffleVector(NarrowTy, Op0, Op1, Ops).getReg(0); 4468 } 4469 4470 Ops.clear(); 4471 } 4472 4473 MIRBuilder.buildConcatVectors(DstReg, {Lo, Hi}); 4474 MI.eraseFromParent(); 4475 return Legalized; 4476 } 4477 4478 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorReductions( 4479 MachineInstr &MI, unsigned int TypeIdx, LLT NarrowTy) { 4480 unsigned Opc = MI.getOpcode(); 4481 assert(Opc != TargetOpcode::G_VECREDUCE_SEQ_FADD && 4482 Opc != TargetOpcode::G_VECREDUCE_SEQ_FMUL && 4483 "Sequential reductions not expected"); 4484 4485 if (TypeIdx != 1) 4486 return UnableToLegalize; 4487 4488 // The semantics of the normal non-sequential reductions allow us to freely 4489 // re-associate the operation. 4490 Register SrcReg = MI.getOperand(1).getReg(); 4491 LLT SrcTy = MRI.getType(SrcReg); 4492 Register DstReg = MI.getOperand(0).getReg(); 4493 LLT DstTy = MRI.getType(DstReg); 4494 4495 if (SrcTy.getNumElements() % NarrowTy.getNumElements() != 0) 4496 return UnableToLegalize; 4497 4498 SmallVector<Register> SplitSrcs; 4499 const unsigned NumParts = SrcTy.getNumElements() / NarrowTy.getNumElements(); 4500 extractParts(SrcReg, NarrowTy, NumParts, SplitSrcs); 4501 SmallVector<Register> PartialReductions; 4502 for (unsigned Part = 0; Part < NumParts; ++Part) { 4503 PartialReductions.push_back( 4504 MIRBuilder.buildInstr(Opc, {DstTy}, {SplitSrcs[Part]}).getReg(0)); 4505 } 4506 4507 unsigned ScalarOpc; 4508 switch (Opc) { 4509 case TargetOpcode::G_VECREDUCE_FADD: 4510 ScalarOpc = TargetOpcode::G_FADD; 4511 break; 4512 case TargetOpcode::G_VECREDUCE_FMUL: 4513 ScalarOpc = TargetOpcode::G_FMUL; 4514 break; 4515 case TargetOpcode::G_VECREDUCE_FMAX: 4516 ScalarOpc = TargetOpcode::G_FMAXNUM; 4517 break; 4518 case TargetOpcode::G_VECREDUCE_FMIN: 4519 ScalarOpc = TargetOpcode::G_FMINNUM; 4520 break; 4521 case TargetOpcode::G_VECREDUCE_ADD: 4522 ScalarOpc = TargetOpcode::G_ADD; 4523 break; 4524 case TargetOpcode::G_VECREDUCE_MUL: 4525 ScalarOpc = TargetOpcode::G_MUL; 4526 break; 4527 case TargetOpcode::G_VECREDUCE_AND: 4528 ScalarOpc = TargetOpcode::G_AND; 4529 break; 4530 case TargetOpcode::G_VECREDUCE_OR: 4531 ScalarOpc = TargetOpcode::G_OR; 4532 break; 4533 case TargetOpcode::G_VECREDUCE_XOR: 4534 ScalarOpc = TargetOpcode::G_XOR; 4535 break; 4536 case TargetOpcode::G_VECREDUCE_SMAX: 4537 ScalarOpc = TargetOpcode::G_SMAX; 4538 break; 4539 case TargetOpcode::G_VECREDUCE_SMIN: 4540 ScalarOpc = TargetOpcode::G_SMIN; 4541 break; 4542 case TargetOpcode::G_VECREDUCE_UMAX: 4543 ScalarOpc = TargetOpcode::G_UMAX; 4544 break; 4545 case TargetOpcode::G_VECREDUCE_UMIN: 4546 ScalarOpc = TargetOpcode::G_UMIN; 4547 break; 4548 default: 4549 LLVM_DEBUG(dbgs() << "Can't legalize: unknown reduction kind.\n"); 4550 return UnableToLegalize; 4551 } 4552 4553 // If the types involved are powers of 2, we can generate intermediate vector 4554 // ops, before generating a final reduction operation. 4555 if (isPowerOf2_32(SrcTy.getNumElements()) && 4556 isPowerOf2_32(NarrowTy.getNumElements())) { 4557 return tryNarrowPow2Reduction(MI, SrcReg, SrcTy, NarrowTy, ScalarOpc); 4558 } 4559 4560 Register Acc = PartialReductions[0]; 4561 for (unsigned Part = 1; Part < NumParts; ++Part) { 4562 if (Part == NumParts - 1) { 4563 MIRBuilder.buildInstr(ScalarOpc, {DstReg}, 4564 {Acc, PartialReductions[Part]}); 4565 } else { 4566 Acc = MIRBuilder 4567 .buildInstr(ScalarOpc, {DstTy}, {Acc, PartialReductions[Part]}) 4568 .getReg(0); 4569 } 4570 } 4571 MI.eraseFromParent(); 4572 return Legalized; 4573 } 4574 4575 LegalizerHelper::LegalizeResult 4576 LegalizerHelper::tryNarrowPow2Reduction(MachineInstr &MI, Register SrcReg, 4577 LLT SrcTy, LLT NarrowTy, 4578 unsigned ScalarOpc) { 4579 SmallVector<Register> SplitSrcs; 4580 // Split the sources into NarrowTy size pieces. 4581 extractParts(SrcReg, NarrowTy, 4582 SrcTy.getNumElements() / NarrowTy.getNumElements(), SplitSrcs); 4583 // We're going to do a tree reduction using vector operations until we have 4584 // one NarrowTy size value left. 4585 while (SplitSrcs.size() > 1) { 4586 SmallVector<Register> PartialRdxs; 4587 for (unsigned Idx = 0; Idx < SplitSrcs.size()-1; Idx += 2) { 4588 Register LHS = SplitSrcs[Idx]; 4589 Register RHS = SplitSrcs[Idx + 1]; 4590 // Create the intermediate vector op. 4591 Register Res = 4592 MIRBuilder.buildInstr(ScalarOpc, {NarrowTy}, {LHS, RHS}).getReg(0); 4593 PartialRdxs.push_back(Res); 4594 } 4595 SplitSrcs = std::move(PartialRdxs); 4596 } 4597 // Finally generate the requested NarrowTy based reduction. 4598 Observer.changingInstr(MI); 4599 MI.getOperand(1).setReg(SplitSrcs[0]); 4600 Observer.changedInstr(MI); 4601 return Legalized; 4602 } 4603 4604 LegalizerHelper::LegalizeResult 4605 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt, 4606 const LLT HalfTy, const LLT AmtTy) { 4607 4608 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4609 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4610 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4611 4612 if (Amt.isNullValue()) { 4613 MIRBuilder.buildMerge(MI.getOperand(0), {InL, InH}); 4614 MI.eraseFromParent(); 4615 return Legalized; 4616 } 4617 4618 LLT NVT = HalfTy; 4619 unsigned NVTBits = HalfTy.getSizeInBits(); 4620 unsigned VTBits = 2 * NVTBits; 4621 4622 SrcOp Lo(Register(0)), Hi(Register(0)); 4623 if (MI.getOpcode() == TargetOpcode::G_SHL) { 4624 if (Amt.ugt(VTBits)) { 4625 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4626 } else if (Amt.ugt(NVTBits)) { 4627 Lo = MIRBuilder.buildConstant(NVT, 0); 4628 Hi = MIRBuilder.buildShl(NVT, InL, 4629 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4630 } else if (Amt == NVTBits) { 4631 Lo = MIRBuilder.buildConstant(NVT, 0); 4632 Hi = InL; 4633 } else { 4634 Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt)); 4635 auto OrLHS = 4636 MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt)); 4637 auto OrRHS = MIRBuilder.buildLShr( 4638 NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4639 Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4640 } 4641 } else if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4642 if (Amt.ugt(VTBits)) { 4643 Lo = Hi = MIRBuilder.buildConstant(NVT, 0); 4644 } else if (Amt.ugt(NVTBits)) { 4645 Lo = MIRBuilder.buildLShr(NVT, InH, 4646 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4647 Hi = MIRBuilder.buildConstant(NVT, 0); 4648 } else if (Amt == NVTBits) { 4649 Lo = InH; 4650 Hi = MIRBuilder.buildConstant(NVT, 0); 4651 } else { 4652 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4653 4654 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4655 auto OrRHS = MIRBuilder.buildShl( 4656 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4657 4658 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4659 Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst); 4660 } 4661 } else { 4662 if (Amt.ugt(VTBits)) { 4663 Hi = Lo = MIRBuilder.buildAShr( 4664 NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4665 } else if (Amt.ugt(NVTBits)) { 4666 Lo = MIRBuilder.buildAShr(NVT, InH, 4667 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits)); 4668 Hi = MIRBuilder.buildAShr(NVT, InH, 4669 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4670 } else if (Amt == NVTBits) { 4671 Lo = InH; 4672 Hi = MIRBuilder.buildAShr(NVT, InH, 4673 MIRBuilder.buildConstant(AmtTy, NVTBits - 1)); 4674 } else { 4675 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt); 4676 4677 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst); 4678 auto OrRHS = MIRBuilder.buildShl( 4679 NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits)); 4680 4681 Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS); 4682 Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst); 4683 } 4684 } 4685 4686 MIRBuilder.buildMerge(MI.getOperand(0), {Lo, Hi}); 4687 MI.eraseFromParent(); 4688 4689 return Legalized; 4690 } 4691 4692 // TODO: Optimize if constant shift amount. 4693 LegalizerHelper::LegalizeResult 4694 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, 4695 LLT RequestedTy) { 4696 if (TypeIdx == 1) { 4697 Observer.changingInstr(MI); 4698 narrowScalarSrc(MI, RequestedTy, 2); 4699 Observer.changedInstr(MI); 4700 return Legalized; 4701 } 4702 4703 Register DstReg = MI.getOperand(0).getReg(); 4704 LLT DstTy = MRI.getType(DstReg); 4705 if (DstTy.isVector()) 4706 return UnableToLegalize; 4707 4708 Register Amt = MI.getOperand(2).getReg(); 4709 LLT ShiftAmtTy = MRI.getType(Amt); 4710 const unsigned DstEltSize = DstTy.getScalarSizeInBits(); 4711 if (DstEltSize % 2 != 0) 4712 return UnableToLegalize; 4713 4714 // Ignore the input type. We can only go to exactly half the size of the 4715 // input. If that isn't small enough, the resulting pieces will be further 4716 // legalized. 4717 const unsigned NewBitSize = DstEltSize / 2; 4718 const LLT HalfTy = LLT::scalar(NewBitSize); 4719 const LLT CondTy = LLT::scalar(1); 4720 4721 if (const MachineInstr *KShiftAmt = 4722 getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) { 4723 return narrowScalarShiftByConstant( 4724 MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy); 4725 } 4726 4727 // TODO: Expand with known bits. 4728 4729 // Handle the fully general expansion by an unknown amount. 4730 auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize); 4731 4732 Register InL = MRI.createGenericVirtualRegister(HalfTy); 4733 Register InH = MRI.createGenericVirtualRegister(HalfTy); 4734 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1)); 4735 4736 auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits); 4737 auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt); 4738 4739 auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0); 4740 auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits); 4741 auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero); 4742 4743 Register ResultRegs[2]; 4744 switch (MI.getOpcode()) { 4745 case TargetOpcode::G_SHL: { 4746 // Short: ShAmt < NewBitSize 4747 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt); 4748 4749 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack); 4750 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt); 4751 auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4752 4753 // Long: ShAmt >= NewBitSize 4754 auto LoL = MIRBuilder.buildConstant(HalfTy, 0); // Lo part is zero. 4755 auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part. 4756 4757 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL); 4758 auto Hi = MIRBuilder.buildSelect( 4759 HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL)); 4760 4761 ResultRegs[0] = Lo.getReg(0); 4762 ResultRegs[1] = Hi.getReg(0); 4763 break; 4764 } 4765 case TargetOpcode::G_LSHR: 4766 case TargetOpcode::G_ASHR: { 4767 // Short: ShAmt < NewBitSize 4768 auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt}); 4769 4770 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt); 4771 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack); 4772 auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr); 4773 4774 // Long: ShAmt >= NewBitSize 4775 MachineInstrBuilder HiL; 4776 if (MI.getOpcode() == TargetOpcode::G_LSHR) { 4777 HiL = MIRBuilder.buildConstant(HalfTy, 0); // Hi part is zero. 4778 } else { 4779 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1); 4780 HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt); // Sign of Hi part. 4781 } 4782 auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, 4783 {InH, AmtExcess}); // Lo from Hi part. 4784 4785 auto Lo = MIRBuilder.buildSelect( 4786 HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL)); 4787 4788 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL); 4789 4790 ResultRegs[0] = Lo.getReg(0); 4791 ResultRegs[1] = Hi.getReg(0); 4792 break; 4793 } 4794 default: 4795 llvm_unreachable("not a shift"); 4796 } 4797 4798 MIRBuilder.buildMerge(DstReg, ResultRegs); 4799 MI.eraseFromParent(); 4800 return Legalized; 4801 } 4802 4803 LegalizerHelper::LegalizeResult 4804 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx, 4805 LLT MoreTy) { 4806 assert(TypeIdx == 0 && "Expecting only Idx 0"); 4807 4808 Observer.changingInstr(MI); 4809 for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) { 4810 MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB(); 4811 MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator()); 4812 moreElementsVectorSrc(MI, MoreTy, I); 4813 } 4814 4815 MachineBasicBlock &MBB = *MI.getParent(); 4816 MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI()); 4817 moreElementsVectorDst(MI, MoreTy, 0); 4818 Observer.changedInstr(MI); 4819 return Legalized; 4820 } 4821 4822 LegalizerHelper::LegalizeResult 4823 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx, 4824 LLT MoreTy) { 4825 unsigned Opc = MI.getOpcode(); 4826 switch (Opc) { 4827 case TargetOpcode::G_IMPLICIT_DEF: 4828 case TargetOpcode::G_LOAD: { 4829 if (TypeIdx != 0) 4830 return UnableToLegalize; 4831 Observer.changingInstr(MI); 4832 moreElementsVectorDst(MI, MoreTy, 0); 4833 Observer.changedInstr(MI); 4834 return Legalized; 4835 } 4836 case TargetOpcode::G_STORE: 4837 if (TypeIdx != 0) 4838 return UnableToLegalize; 4839 Observer.changingInstr(MI); 4840 moreElementsVectorSrc(MI, MoreTy, 0); 4841 Observer.changedInstr(MI); 4842 return Legalized; 4843 case TargetOpcode::G_AND: 4844 case TargetOpcode::G_OR: 4845 case TargetOpcode::G_XOR: 4846 case TargetOpcode::G_SMIN: 4847 case TargetOpcode::G_SMAX: 4848 case TargetOpcode::G_UMIN: 4849 case TargetOpcode::G_UMAX: 4850 case TargetOpcode::G_FMINNUM: 4851 case TargetOpcode::G_FMAXNUM: 4852 case TargetOpcode::G_FMINNUM_IEEE: 4853 case TargetOpcode::G_FMAXNUM_IEEE: 4854 case TargetOpcode::G_FMINIMUM: 4855 case TargetOpcode::G_FMAXIMUM: { 4856 Observer.changingInstr(MI); 4857 moreElementsVectorSrc(MI, MoreTy, 1); 4858 moreElementsVectorSrc(MI, MoreTy, 2); 4859 moreElementsVectorDst(MI, MoreTy, 0); 4860 Observer.changedInstr(MI); 4861 return Legalized; 4862 } 4863 case TargetOpcode::G_EXTRACT: 4864 if (TypeIdx != 1) 4865 return UnableToLegalize; 4866 Observer.changingInstr(MI); 4867 moreElementsVectorSrc(MI, MoreTy, 1); 4868 Observer.changedInstr(MI); 4869 return Legalized; 4870 case TargetOpcode::G_INSERT: 4871 case TargetOpcode::G_FREEZE: 4872 if (TypeIdx != 0) 4873 return UnableToLegalize; 4874 Observer.changingInstr(MI); 4875 moreElementsVectorSrc(MI, MoreTy, 1); 4876 moreElementsVectorDst(MI, MoreTy, 0); 4877 Observer.changedInstr(MI); 4878 return Legalized; 4879 case TargetOpcode::G_SELECT: 4880 if (TypeIdx != 0) 4881 return UnableToLegalize; 4882 if (MRI.getType(MI.getOperand(1).getReg()).isVector()) 4883 return UnableToLegalize; 4884 4885 Observer.changingInstr(MI); 4886 moreElementsVectorSrc(MI, MoreTy, 2); 4887 moreElementsVectorSrc(MI, MoreTy, 3); 4888 moreElementsVectorDst(MI, MoreTy, 0); 4889 Observer.changedInstr(MI); 4890 return Legalized; 4891 case TargetOpcode::G_UNMERGE_VALUES: { 4892 if (TypeIdx != 1) 4893 return UnableToLegalize; 4894 4895 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 4896 int NumDst = MI.getNumOperands() - 1; 4897 moreElementsVectorSrc(MI, MoreTy, NumDst); 4898 4899 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES); 4900 for (int I = 0; I != NumDst; ++I) 4901 MIB.addDef(MI.getOperand(I).getReg()); 4902 4903 int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits(); 4904 for (int I = NumDst; I != NewNumDst; ++I) 4905 MIB.addDef(MRI.createGenericVirtualRegister(DstTy)); 4906 4907 MIB.addUse(MI.getOperand(NumDst).getReg()); 4908 MI.eraseFromParent(); 4909 return Legalized; 4910 } 4911 case TargetOpcode::G_PHI: 4912 return moreElementsVectorPhi(MI, TypeIdx, MoreTy); 4913 case TargetOpcode::G_SHUFFLE_VECTOR: 4914 return moreElementsVectorShuffle(MI, TypeIdx, MoreTy); 4915 default: 4916 return UnableToLegalize; 4917 } 4918 } 4919 4920 LegalizerHelper::LegalizeResult 4921 LegalizerHelper::moreElementsVectorShuffle(MachineInstr &MI, 4922 unsigned int TypeIdx, LLT MoreTy) { 4923 if (TypeIdx != 0) 4924 return UnableToLegalize; 4925 4926 Register DstReg = MI.getOperand(0).getReg(); 4927 Register Src1Reg = MI.getOperand(1).getReg(); 4928 Register Src2Reg = MI.getOperand(2).getReg(); 4929 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 4930 LLT DstTy = MRI.getType(DstReg); 4931 LLT Src1Ty = MRI.getType(Src1Reg); 4932 LLT Src2Ty = MRI.getType(Src2Reg); 4933 unsigned NumElts = DstTy.getNumElements(); 4934 unsigned WidenNumElts = MoreTy.getNumElements(); 4935 4936 // Expect a canonicalized shuffle. 4937 if (DstTy != Src1Ty || DstTy != Src2Ty) 4938 return UnableToLegalize; 4939 4940 moreElementsVectorSrc(MI, MoreTy, 1); 4941 moreElementsVectorSrc(MI, MoreTy, 2); 4942 4943 // Adjust mask based on new input vector length. 4944 SmallVector<int, 16> NewMask; 4945 for (unsigned I = 0; I != NumElts; ++I) { 4946 int Idx = Mask[I]; 4947 if (Idx < static_cast<int>(NumElts)) 4948 NewMask.push_back(Idx); 4949 else 4950 NewMask.push_back(Idx - NumElts + WidenNumElts); 4951 } 4952 for (unsigned I = NumElts; I != WidenNumElts; ++I) 4953 NewMask.push_back(-1); 4954 moreElementsVectorDst(MI, MoreTy, 0); 4955 MIRBuilder.setInstrAndDebugLoc(MI); 4956 MIRBuilder.buildShuffleVector(MI.getOperand(0).getReg(), 4957 MI.getOperand(1).getReg(), 4958 MI.getOperand(2).getReg(), NewMask); 4959 MI.eraseFromParent(); 4960 return Legalized; 4961 } 4962 4963 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs, 4964 ArrayRef<Register> Src1Regs, 4965 ArrayRef<Register> Src2Regs, 4966 LLT NarrowTy) { 4967 MachineIRBuilder &B = MIRBuilder; 4968 unsigned SrcParts = Src1Regs.size(); 4969 unsigned DstParts = DstRegs.size(); 4970 4971 unsigned DstIdx = 0; // Low bits of the result. 4972 Register FactorSum = 4973 B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0); 4974 DstRegs[DstIdx] = FactorSum; 4975 4976 unsigned CarrySumPrevDstIdx; 4977 SmallVector<Register, 4> Factors; 4978 4979 for (DstIdx = 1; DstIdx < DstParts; DstIdx++) { 4980 // Collect low parts of muls for DstIdx. 4981 for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1; 4982 i <= std::min(DstIdx, SrcParts - 1); ++i) { 4983 MachineInstrBuilder Mul = 4984 B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]); 4985 Factors.push_back(Mul.getReg(0)); 4986 } 4987 // Collect high parts of muls from previous DstIdx. 4988 for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts; 4989 i <= std::min(DstIdx - 1, SrcParts - 1); ++i) { 4990 MachineInstrBuilder Umulh = 4991 B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]); 4992 Factors.push_back(Umulh.getReg(0)); 4993 } 4994 // Add CarrySum from additions calculated for previous DstIdx. 4995 if (DstIdx != 1) { 4996 Factors.push_back(CarrySumPrevDstIdx); 4997 } 4998 4999 Register CarrySum; 5000 // Add all factors and accumulate all carries into CarrySum. 5001 if (DstIdx != DstParts - 1) { 5002 MachineInstrBuilder Uaddo = 5003 B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]); 5004 FactorSum = Uaddo.getReg(0); 5005 CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0); 5006 for (unsigned i = 2; i < Factors.size(); ++i) { 5007 MachineInstrBuilder Uaddo = 5008 B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]); 5009 FactorSum = Uaddo.getReg(0); 5010 MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1)); 5011 CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0); 5012 } 5013 } else { 5014 // Since value for the next index is not calculated, neither is CarrySum. 5015 FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0); 5016 for (unsigned i = 2; i < Factors.size(); ++i) 5017 FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0); 5018 } 5019 5020 CarrySumPrevDstIdx = CarrySum; 5021 DstRegs[DstIdx] = FactorSum; 5022 Factors.clear(); 5023 } 5024 } 5025 5026 LegalizerHelper::LegalizeResult 5027 LegalizerHelper::narrowScalarAddSub(MachineInstr &MI, unsigned TypeIdx, 5028 LLT NarrowTy) { 5029 if (TypeIdx != 0) 5030 return UnableToLegalize; 5031 5032 Register DstReg = MI.getOperand(0).getReg(); 5033 LLT DstType = MRI.getType(DstReg); 5034 // FIXME: add support for vector types 5035 if (DstType.isVector()) 5036 return UnableToLegalize; 5037 5038 unsigned Opcode = MI.getOpcode(); 5039 unsigned OpO, OpE, OpF; 5040 switch (Opcode) { 5041 case TargetOpcode::G_SADDO: 5042 case TargetOpcode::G_SADDE: 5043 case TargetOpcode::G_UADDO: 5044 case TargetOpcode::G_UADDE: 5045 case TargetOpcode::G_ADD: 5046 OpO = TargetOpcode::G_UADDO; 5047 OpE = TargetOpcode::G_UADDE; 5048 OpF = TargetOpcode::G_UADDE; 5049 if (Opcode == TargetOpcode::G_SADDO || Opcode == TargetOpcode::G_SADDE) 5050 OpF = TargetOpcode::G_SADDE; 5051 break; 5052 case TargetOpcode::G_SSUBO: 5053 case TargetOpcode::G_SSUBE: 5054 case TargetOpcode::G_USUBO: 5055 case TargetOpcode::G_USUBE: 5056 case TargetOpcode::G_SUB: 5057 OpO = TargetOpcode::G_USUBO; 5058 OpE = TargetOpcode::G_USUBE; 5059 OpF = TargetOpcode::G_USUBE; 5060 if (Opcode == TargetOpcode::G_SSUBO || Opcode == TargetOpcode::G_SSUBE) 5061 OpF = TargetOpcode::G_SSUBE; 5062 break; 5063 default: 5064 llvm_unreachable("Unexpected add/sub opcode!"); 5065 } 5066 5067 // 1 for a plain add/sub, 2 if this is an operation with a carry-out. 5068 unsigned NumDefs = MI.getNumExplicitDefs(); 5069 Register Src1 = MI.getOperand(NumDefs).getReg(); 5070 Register Src2 = MI.getOperand(NumDefs + 1).getReg(); 5071 Register CarryDst, CarryIn; 5072 if (NumDefs == 2) 5073 CarryDst = MI.getOperand(1).getReg(); 5074 if (MI.getNumOperands() == NumDefs + 3) 5075 CarryIn = MI.getOperand(NumDefs + 2).getReg(); 5076 5077 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); 5078 LLT LeftoverTy, DummyTy; 5079 SmallVector<Register, 2> Src1Regs, Src2Regs, Src1Left, Src2Left, DstRegs; 5080 extractParts(Src1, RegTy, NarrowTy, LeftoverTy, Src1Regs, Src1Left); 5081 extractParts(Src2, RegTy, NarrowTy, DummyTy, Src2Regs, Src2Left); 5082 5083 int NarrowParts = Src1Regs.size(); 5084 for (int I = 0, E = Src1Left.size(); I != E; ++I) { 5085 Src1Regs.push_back(Src1Left[I]); 5086 Src2Regs.push_back(Src2Left[I]); 5087 } 5088 DstRegs.reserve(Src1Regs.size()); 5089 5090 for (int i = 0, e = Src1Regs.size(); i != e; ++i) { 5091 Register DstReg = 5092 MRI.createGenericVirtualRegister(MRI.getType(Src1Regs[i])); 5093 Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1)); 5094 // Forward the final carry-out to the destination register 5095 if (i == e - 1 && CarryDst) 5096 CarryOut = CarryDst; 5097 5098 if (!CarryIn) { 5099 MIRBuilder.buildInstr(OpO, {DstReg, CarryOut}, 5100 {Src1Regs[i], Src2Regs[i]}); 5101 } else if (i == e - 1) { 5102 MIRBuilder.buildInstr(OpF, {DstReg, CarryOut}, 5103 {Src1Regs[i], Src2Regs[i], CarryIn}); 5104 } else { 5105 MIRBuilder.buildInstr(OpE, {DstReg, CarryOut}, 5106 {Src1Regs[i], Src2Regs[i], CarryIn}); 5107 } 5108 5109 DstRegs.push_back(DstReg); 5110 CarryIn = CarryOut; 5111 } 5112 insertParts(MI.getOperand(0).getReg(), RegTy, NarrowTy, 5113 makeArrayRef(DstRegs).take_front(NarrowParts), LeftoverTy, 5114 makeArrayRef(DstRegs).drop_front(NarrowParts)); 5115 5116 MI.eraseFromParent(); 5117 return Legalized; 5118 } 5119 5120 LegalizerHelper::LegalizeResult 5121 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) { 5122 Register DstReg = MI.getOperand(0).getReg(); 5123 Register Src1 = MI.getOperand(1).getReg(); 5124 Register Src2 = MI.getOperand(2).getReg(); 5125 5126 LLT Ty = MRI.getType(DstReg); 5127 if (Ty.isVector()) 5128 return UnableToLegalize; 5129 5130 unsigned SrcSize = MRI.getType(Src1).getSizeInBits(); 5131 unsigned DstSize = Ty.getSizeInBits(); 5132 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5133 if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0) 5134 return UnableToLegalize; 5135 5136 unsigned NumDstParts = DstSize / NarrowSize; 5137 unsigned NumSrcParts = SrcSize / NarrowSize; 5138 bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH; 5139 unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1); 5140 5141 SmallVector<Register, 2> Src1Parts, Src2Parts; 5142 SmallVector<Register, 2> DstTmpRegs(DstTmpParts); 5143 extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts); 5144 extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts); 5145 multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy); 5146 5147 // Take only high half of registers if this is high mul. 5148 ArrayRef<Register> DstRegs( 5149 IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts); 5150 MIRBuilder.buildMerge(DstReg, DstRegs); 5151 MI.eraseFromParent(); 5152 return Legalized; 5153 } 5154 5155 LegalizerHelper::LegalizeResult 5156 LegalizerHelper::narrowScalarFPTOI(MachineInstr &MI, unsigned TypeIdx, 5157 LLT NarrowTy) { 5158 if (TypeIdx != 0) 5159 return UnableToLegalize; 5160 5161 bool IsSigned = MI.getOpcode() == TargetOpcode::G_FPTOSI; 5162 5163 Register Src = MI.getOperand(1).getReg(); 5164 LLT SrcTy = MRI.getType(Src); 5165 5166 // If all finite floats fit into the narrowed integer type, we can just swap 5167 // out the result type. This is practically only useful for conversions from 5168 // half to at least 16-bits, so just handle the one case. 5169 if (SrcTy.getScalarType() != LLT::scalar(16) || 5170 NarrowTy.getScalarSizeInBits() < (IsSigned ? 17u : 16u)) 5171 return UnableToLegalize; 5172 5173 Observer.changingInstr(MI); 5174 narrowScalarDst(MI, NarrowTy, 0, 5175 IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT); 5176 Observer.changedInstr(MI); 5177 return Legalized; 5178 } 5179 5180 LegalizerHelper::LegalizeResult 5181 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, 5182 LLT NarrowTy) { 5183 if (TypeIdx != 1) 5184 return UnableToLegalize; 5185 5186 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 5187 5188 int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits(); 5189 // FIXME: add support for when SizeOp1 isn't an exact multiple of 5190 // NarrowSize. 5191 if (SizeOp1 % NarrowSize != 0) 5192 return UnableToLegalize; 5193 int NumParts = SizeOp1 / NarrowSize; 5194 5195 SmallVector<Register, 2> SrcRegs, DstRegs; 5196 SmallVector<uint64_t, 2> Indexes; 5197 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs); 5198 5199 Register OpReg = MI.getOperand(0).getReg(); 5200 uint64_t OpStart = MI.getOperand(2).getImm(); 5201 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 5202 for (int i = 0; i < NumParts; ++i) { 5203 unsigned SrcStart = i * NarrowSize; 5204 5205 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) { 5206 // No part of the extract uses this subregister, ignore it. 5207 continue; 5208 } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 5209 // The entire subregister is extracted, forward the value. 5210 DstRegs.push_back(SrcRegs[i]); 5211 continue; 5212 } 5213 5214 // OpSegStart is where this destination segment would start in OpReg if it 5215 // extended infinitely in both directions. 5216 int64_t ExtractOffset; 5217 uint64_t SegSize; 5218 if (OpStart < SrcStart) { 5219 ExtractOffset = 0; 5220 SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart); 5221 } else { 5222 ExtractOffset = OpStart - SrcStart; 5223 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize); 5224 } 5225 5226 Register SegReg = SrcRegs[i]; 5227 if (ExtractOffset != 0 || SegSize != NarrowSize) { 5228 // A genuine extract is needed. 5229 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 5230 MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset); 5231 } 5232 5233 DstRegs.push_back(SegReg); 5234 } 5235 5236 Register DstReg = MI.getOperand(0).getReg(); 5237 if (MRI.getType(DstReg).isVector()) 5238 MIRBuilder.buildBuildVector(DstReg, DstRegs); 5239 else if (DstRegs.size() > 1) 5240 MIRBuilder.buildMerge(DstReg, DstRegs); 5241 else 5242 MIRBuilder.buildCopy(DstReg, DstRegs[0]); 5243 MI.eraseFromParent(); 5244 return Legalized; 5245 } 5246 5247 LegalizerHelper::LegalizeResult 5248 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, 5249 LLT NarrowTy) { 5250 // FIXME: Don't know how to handle secondary types yet. 5251 if (TypeIdx != 0) 5252 return UnableToLegalize; 5253 5254 SmallVector<Register, 2> SrcRegs, LeftoverRegs, DstRegs; 5255 SmallVector<uint64_t, 2> Indexes; 5256 LLT RegTy = MRI.getType(MI.getOperand(0).getReg()); 5257 LLT LeftoverTy; 5258 extractParts(MI.getOperand(1).getReg(), RegTy, NarrowTy, LeftoverTy, SrcRegs, 5259 LeftoverRegs); 5260 5261 for (Register Reg : LeftoverRegs) 5262 SrcRegs.push_back(Reg); 5263 5264 uint64_t NarrowSize = NarrowTy.getSizeInBits(); 5265 Register OpReg = MI.getOperand(2).getReg(); 5266 uint64_t OpStart = MI.getOperand(3).getImm(); 5267 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); 5268 for (int I = 0, E = SrcRegs.size(); I != E; ++I) { 5269 unsigned DstStart = I * NarrowSize; 5270 5271 if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) { 5272 // The entire subregister is defined by this insert, forward the new 5273 // value. 5274 DstRegs.push_back(OpReg); 5275 continue; 5276 } 5277 5278 Register SrcReg = SrcRegs[I]; 5279 if (MRI.getType(SrcRegs[I]) == LeftoverTy) { 5280 // The leftover reg is smaller than NarrowTy, so we need to extend it. 5281 SrcReg = MRI.createGenericVirtualRegister(NarrowTy); 5282 MIRBuilder.buildAnyExt(SrcReg, SrcRegs[I]); 5283 } 5284 5285 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) { 5286 // No part of the insert affects this subregister, forward the original. 5287 DstRegs.push_back(SrcReg); 5288 continue; 5289 } 5290 5291 // OpSegStart is where this destination segment would start in OpReg if it 5292 // extended infinitely in both directions. 5293 int64_t ExtractOffset, InsertOffset; 5294 uint64_t SegSize; 5295 if (OpStart < DstStart) { 5296 InsertOffset = 0; 5297 ExtractOffset = DstStart - OpStart; 5298 SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart); 5299 } else { 5300 InsertOffset = OpStart - DstStart; 5301 ExtractOffset = 0; 5302 SegSize = 5303 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart); 5304 } 5305 5306 Register SegReg = OpReg; 5307 if (ExtractOffset != 0 || SegSize != OpSize) { 5308 // A genuine extract is needed. 5309 SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize)); 5310 MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset); 5311 } 5312 5313 Register DstReg = MRI.createGenericVirtualRegister(NarrowTy); 5314 MIRBuilder.buildInsert(DstReg, SrcReg, SegReg, InsertOffset); 5315 DstRegs.push_back(DstReg); 5316 } 5317 5318 uint64_t WideSize = DstRegs.size() * NarrowSize; 5319 Register DstReg = MI.getOperand(0).getReg(); 5320 if (WideSize > RegTy.getSizeInBits()) { 5321 Register MergeReg = MRI.createGenericVirtualRegister(LLT::scalar(WideSize)); 5322 MIRBuilder.buildMerge(MergeReg, DstRegs); 5323 MIRBuilder.buildTrunc(DstReg, MergeReg); 5324 } else 5325 MIRBuilder.buildMerge(DstReg, DstRegs); 5326 5327 MI.eraseFromParent(); 5328 return Legalized; 5329 } 5330 5331 LegalizerHelper::LegalizeResult 5332 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, 5333 LLT NarrowTy) { 5334 Register DstReg = MI.getOperand(0).getReg(); 5335 LLT DstTy = MRI.getType(DstReg); 5336 5337 assert(MI.getNumOperands() == 3 && TypeIdx == 0); 5338 5339 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 5340 SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs; 5341 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 5342 LLT LeftoverTy; 5343 if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy, 5344 Src0Regs, Src0LeftoverRegs)) 5345 return UnableToLegalize; 5346 5347 LLT Unused; 5348 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused, 5349 Src1Regs, Src1LeftoverRegs)) 5350 llvm_unreachable("inconsistent extractParts result"); 5351 5352 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 5353 auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy}, 5354 {Src0Regs[I], Src1Regs[I]}); 5355 DstRegs.push_back(Inst.getReg(0)); 5356 } 5357 5358 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 5359 auto Inst = MIRBuilder.buildInstr( 5360 MI.getOpcode(), 5361 {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]}); 5362 DstLeftoverRegs.push_back(Inst.getReg(0)); 5363 } 5364 5365 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 5366 LeftoverTy, DstLeftoverRegs); 5367 5368 MI.eraseFromParent(); 5369 return Legalized; 5370 } 5371 5372 LegalizerHelper::LegalizeResult 5373 LegalizerHelper::narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, 5374 LLT NarrowTy) { 5375 if (TypeIdx != 0) 5376 return UnableToLegalize; 5377 5378 Register DstReg = MI.getOperand(0).getReg(); 5379 Register SrcReg = MI.getOperand(1).getReg(); 5380 5381 LLT DstTy = MRI.getType(DstReg); 5382 if (DstTy.isVector()) 5383 return UnableToLegalize; 5384 5385 SmallVector<Register, 8> Parts; 5386 LLT GCDTy = extractGCDType(Parts, DstTy, NarrowTy, SrcReg); 5387 LLT LCMTy = buildLCMMergePieces(DstTy, NarrowTy, GCDTy, Parts, MI.getOpcode()); 5388 buildWidenedRemergeToDst(DstReg, LCMTy, Parts); 5389 5390 MI.eraseFromParent(); 5391 return Legalized; 5392 } 5393 5394 LegalizerHelper::LegalizeResult 5395 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, 5396 LLT NarrowTy) { 5397 if (TypeIdx != 0) 5398 return UnableToLegalize; 5399 5400 Register CondReg = MI.getOperand(1).getReg(); 5401 LLT CondTy = MRI.getType(CondReg); 5402 if (CondTy.isVector()) // TODO: Handle vselect 5403 return UnableToLegalize; 5404 5405 Register DstReg = MI.getOperand(0).getReg(); 5406 LLT DstTy = MRI.getType(DstReg); 5407 5408 SmallVector<Register, 4> DstRegs, DstLeftoverRegs; 5409 SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs; 5410 SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs; 5411 LLT LeftoverTy; 5412 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy, 5413 Src1Regs, Src1LeftoverRegs)) 5414 return UnableToLegalize; 5415 5416 LLT Unused; 5417 if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused, 5418 Src2Regs, Src2LeftoverRegs)) 5419 llvm_unreachable("inconsistent extractParts result"); 5420 5421 for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) { 5422 auto Select = MIRBuilder.buildSelect(NarrowTy, 5423 CondReg, Src1Regs[I], Src2Regs[I]); 5424 DstRegs.push_back(Select.getReg(0)); 5425 } 5426 5427 for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) { 5428 auto Select = MIRBuilder.buildSelect( 5429 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); 5430 DstLeftoverRegs.push_back(Select.getReg(0)); 5431 } 5432 5433 insertParts(DstReg, DstTy, NarrowTy, DstRegs, 5434 LeftoverTy, DstLeftoverRegs); 5435 5436 MI.eraseFromParent(); 5437 return Legalized; 5438 } 5439 5440 LegalizerHelper::LegalizeResult 5441 LegalizerHelper::narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, 5442 LLT NarrowTy) { 5443 if (TypeIdx != 1) 5444 return UnableToLegalize; 5445 5446 Register DstReg = MI.getOperand(0).getReg(); 5447 Register SrcReg = MI.getOperand(1).getReg(); 5448 LLT DstTy = MRI.getType(DstReg); 5449 LLT SrcTy = MRI.getType(SrcReg); 5450 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5451 5452 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5453 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF; 5454 5455 MachineIRBuilder &B = MIRBuilder; 5456 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 5457 // ctlz(Hi:Lo) -> Hi == 0 ? (NarrowSize + ctlz(Lo)) : ctlz(Hi) 5458 auto C_0 = B.buildConstant(NarrowTy, 0); 5459 auto HiIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 5460 UnmergeSrc.getReg(1), C_0); 5461 auto LoCTLZ = IsUndef ? 5462 B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)) : 5463 B.buildCTLZ(DstTy, UnmergeSrc.getReg(0)); 5464 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 5465 auto HiIsZeroCTLZ = B.buildAdd(DstTy, LoCTLZ, C_NarrowSize); 5466 auto HiCTLZ = B.buildCTLZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)); 5467 B.buildSelect(DstReg, HiIsZero, HiIsZeroCTLZ, HiCTLZ); 5468 5469 MI.eraseFromParent(); 5470 return Legalized; 5471 } 5472 5473 return UnableToLegalize; 5474 } 5475 5476 LegalizerHelper::LegalizeResult 5477 LegalizerHelper::narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, 5478 LLT NarrowTy) { 5479 if (TypeIdx != 1) 5480 return UnableToLegalize; 5481 5482 Register DstReg = MI.getOperand(0).getReg(); 5483 Register SrcReg = MI.getOperand(1).getReg(); 5484 LLT DstTy = MRI.getType(DstReg); 5485 LLT SrcTy = MRI.getType(SrcReg); 5486 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5487 5488 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5489 const bool IsUndef = MI.getOpcode() == TargetOpcode::G_CTTZ_ZERO_UNDEF; 5490 5491 MachineIRBuilder &B = MIRBuilder; 5492 auto UnmergeSrc = B.buildUnmerge(NarrowTy, SrcReg); 5493 // cttz(Hi:Lo) -> Lo == 0 ? (cttz(Hi) + NarrowSize) : cttz(Lo) 5494 auto C_0 = B.buildConstant(NarrowTy, 0); 5495 auto LoIsZero = B.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1), 5496 UnmergeSrc.getReg(0), C_0); 5497 auto HiCTTZ = IsUndef ? 5498 B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(1)) : 5499 B.buildCTTZ(DstTy, UnmergeSrc.getReg(1)); 5500 auto C_NarrowSize = B.buildConstant(DstTy, NarrowSize); 5501 auto LoIsZeroCTTZ = B.buildAdd(DstTy, HiCTTZ, C_NarrowSize); 5502 auto LoCTTZ = B.buildCTTZ_ZERO_UNDEF(DstTy, UnmergeSrc.getReg(0)); 5503 B.buildSelect(DstReg, LoIsZero, LoIsZeroCTTZ, LoCTTZ); 5504 5505 MI.eraseFromParent(); 5506 return Legalized; 5507 } 5508 5509 return UnableToLegalize; 5510 } 5511 5512 LegalizerHelper::LegalizeResult 5513 LegalizerHelper::narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, 5514 LLT NarrowTy) { 5515 if (TypeIdx != 1) 5516 return UnableToLegalize; 5517 5518 Register DstReg = MI.getOperand(0).getReg(); 5519 LLT DstTy = MRI.getType(DstReg); 5520 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg()); 5521 unsigned NarrowSize = NarrowTy.getSizeInBits(); 5522 5523 if (SrcTy.isScalar() && SrcTy.getSizeInBits() == 2 * NarrowSize) { 5524 auto UnmergeSrc = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1)); 5525 5526 auto LoCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(0)); 5527 auto HiCTPOP = MIRBuilder.buildCTPOP(DstTy, UnmergeSrc.getReg(1)); 5528 MIRBuilder.buildAdd(DstReg, HiCTPOP, LoCTPOP); 5529 5530 MI.eraseFromParent(); 5531 return Legalized; 5532 } 5533 5534 return UnableToLegalize; 5535 } 5536 5537 LegalizerHelper::LegalizeResult 5538 LegalizerHelper::lowerBitCount(MachineInstr &MI) { 5539 unsigned Opc = MI.getOpcode(); 5540 const auto &TII = MIRBuilder.getTII(); 5541 auto isSupported = [this](const LegalityQuery &Q) { 5542 auto QAction = LI.getAction(Q).Action; 5543 return QAction == Legal || QAction == Libcall || QAction == Custom; 5544 }; 5545 switch (Opc) { 5546 default: 5547 return UnableToLegalize; 5548 case TargetOpcode::G_CTLZ_ZERO_UNDEF: { 5549 // This trivially expands to CTLZ. 5550 Observer.changingInstr(MI); 5551 MI.setDesc(TII.get(TargetOpcode::G_CTLZ)); 5552 Observer.changedInstr(MI); 5553 return Legalized; 5554 } 5555 case TargetOpcode::G_CTLZ: { 5556 Register DstReg = MI.getOperand(0).getReg(); 5557 Register SrcReg = MI.getOperand(1).getReg(); 5558 LLT DstTy = MRI.getType(DstReg); 5559 LLT SrcTy = MRI.getType(SrcReg); 5560 unsigned Len = SrcTy.getSizeInBits(); 5561 5562 if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 5563 // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero. 5564 auto CtlzZU = MIRBuilder.buildCTLZ_ZERO_UNDEF(DstTy, SrcReg); 5565 auto ZeroSrc = MIRBuilder.buildConstant(SrcTy, 0); 5566 auto ICmp = MIRBuilder.buildICmp( 5567 CmpInst::ICMP_EQ, SrcTy.changeElementSize(1), SrcReg, ZeroSrc); 5568 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 5569 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CtlzZU); 5570 MI.eraseFromParent(); 5571 return Legalized; 5572 } 5573 // for now, we do this: 5574 // NewLen = NextPowerOf2(Len); 5575 // x = x | (x >> 1); 5576 // x = x | (x >> 2); 5577 // ... 5578 // x = x | (x >>16); 5579 // x = x | (x >>32); // for 64-bit input 5580 // Upto NewLen/2 5581 // return Len - popcount(x); 5582 // 5583 // Ref: "Hacker's Delight" by Henry Warren 5584 Register Op = SrcReg; 5585 unsigned NewLen = PowerOf2Ceil(Len); 5586 for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) { 5587 auto MIBShiftAmt = MIRBuilder.buildConstant(SrcTy, 1ULL << i); 5588 auto MIBOp = MIRBuilder.buildOr( 5589 SrcTy, Op, MIRBuilder.buildLShr(SrcTy, Op, MIBShiftAmt)); 5590 Op = MIBOp.getReg(0); 5591 } 5592 auto MIBPop = MIRBuilder.buildCTPOP(DstTy, Op); 5593 MIRBuilder.buildSub(MI.getOperand(0), MIRBuilder.buildConstant(DstTy, Len), 5594 MIBPop); 5595 MI.eraseFromParent(); 5596 return Legalized; 5597 } 5598 case TargetOpcode::G_CTTZ_ZERO_UNDEF: { 5599 // This trivially expands to CTTZ. 5600 Observer.changingInstr(MI); 5601 MI.setDesc(TII.get(TargetOpcode::G_CTTZ)); 5602 Observer.changedInstr(MI); 5603 return Legalized; 5604 } 5605 case TargetOpcode::G_CTTZ: { 5606 Register DstReg = MI.getOperand(0).getReg(); 5607 Register SrcReg = MI.getOperand(1).getReg(); 5608 LLT DstTy = MRI.getType(DstReg); 5609 LLT SrcTy = MRI.getType(SrcReg); 5610 5611 unsigned Len = SrcTy.getSizeInBits(); 5612 if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {DstTy, SrcTy}})) { 5613 // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with 5614 // zero. 5615 auto CttzZU = MIRBuilder.buildCTTZ_ZERO_UNDEF(DstTy, SrcReg); 5616 auto Zero = MIRBuilder.buildConstant(SrcTy, 0); 5617 auto ICmp = MIRBuilder.buildICmp( 5618 CmpInst::ICMP_EQ, DstTy.changeElementSize(1), SrcReg, Zero); 5619 auto LenConst = MIRBuilder.buildConstant(DstTy, Len); 5620 MIRBuilder.buildSelect(DstReg, ICmp, LenConst, CttzZU); 5621 MI.eraseFromParent(); 5622 return Legalized; 5623 } 5624 // for now, we use: { return popcount(~x & (x - 1)); } 5625 // unless the target has ctlz but not ctpop, in which case we use: 5626 // { return 32 - nlz(~x & (x-1)); } 5627 // Ref: "Hacker's Delight" by Henry Warren 5628 auto MIBCstNeg1 = MIRBuilder.buildConstant(SrcTy, -1); 5629 auto MIBNot = MIRBuilder.buildXor(SrcTy, SrcReg, MIBCstNeg1); 5630 auto MIBTmp = MIRBuilder.buildAnd( 5631 SrcTy, MIBNot, MIRBuilder.buildAdd(SrcTy, SrcReg, MIBCstNeg1)); 5632 if (!isSupported({TargetOpcode::G_CTPOP, {SrcTy, SrcTy}}) && 5633 isSupported({TargetOpcode::G_CTLZ, {SrcTy, SrcTy}})) { 5634 auto MIBCstLen = MIRBuilder.buildConstant(SrcTy, Len); 5635 MIRBuilder.buildSub(MI.getOperand(0), MIBCstLen, 5636 MIRBuilder.buildCTLZ(SrcTy, MIBTmp)); 5637 MI.eraseFromParent(); 5638 return Legalized; 5639 } 5640 MI.setDesc(TII.get(TargetOpcode::G_CTPOP)); 5641 MI.getOperand(1).setReg(MIBTmp.getReg(0)); 5642 return Legalized; 5643 } 5644 case TargetOpcode::G_CTPOP: { 5645 Register SrcReg = MI.getOperand(1).getReg(); 5646 LLT Ty = MRI.getType(SrcReg); 5647 unsigned Size = Ty.getSizeInBits(); 5648 MachineIRBuilder &B = MIRBuilder; 5649 5650 // Count set bits in blocks of 2 bits. Default approach would be 5651 // B2Count = { val & 0x55555555 } + { (val >> 1) & 0x55555555 } 5652 // We use following formula instead: 5653 // B2Count = val - { (val >> 1) & 0x55555555 } 5654 // since it gives same result in blocks of 2 with one instruction less. 5655 auto C_1 = B.buildConstant(Ty, 1); 5656 auto B2Set1LoTo1Hi = B.buildLShr(Ty, SrcReg, C_1); 5657 APInt B2Mask1HiTo0 = APInt::getSplat(Size, APInt(8, 0x55)); 5658 auto C_B2Mask1HiTo0 = B.buildConstant(Ty, B2Mask1HiTo0); 5659 auto B2Count1Hi = B.buildAnd(Ty, B2Set1LoTo1Hi, C_B2Mask1HiTo0); 5660 auto B2Count = B.buildSub(Ty, SrcReg, B2Count1Hi); 5661 5662 // In order to get count in blocks of 4 add values from adjacent block of 2. 5663 // B4Count = { B2Count & 0x33333333 } + { (B2Count >> 2) & 0x33333333 } 5664 auto C_2 = B.buildConstant(Ty, 2); 5665 auto B4Set2LoTo2Hi = B.buildLShr(Ty, B2Count, C_2); 5666 APInt B4Mask2HiTo0 = APInt::getSplat(Size, APInt(8, 0x33)); 5667 auto C_B4Mask2HiTo0 = B.buildConstant(Ty, B4Mask2HiTo0); 5668 auto B4HiB2Count = B.buildAnd(Ty, B4Set2LoTo2Hi, C_B4Mask2HiTo0); 5669 auto B4LoB2Count = B.buildAnd(Ty, B2Count, C_B4Mask2HiTo0); 5670 auto B4Count = B.buildAdd(Ty, B4HiB2Count, B4LoB2Count); 5671 5672 // For count in blocks of 8 bits we don't have to mask high 4 bits before 5673 // addition since count value sits in range {0,...,8} and 4 bits are enough 5674 // to hold such binary values. After addition high 4 bits still hold count 5675 // of set bits in high 4 bit block, set them to zero and get 8 bit result. 5676 // B8Count = { B4Count + (B4Count >> 4) } & 0x0F0F0F0F 5677 auto C_4 = B.buildConstant(Ty, 4); 5678 auto B8HiB4Count = B.buildLShr(Ty, B4Count, C_4); 5679 auto B8CountDirty4Hi = B.buildAdd(Ty, B8HiB4Count, B4Count); 5680 APInt B8Mask4HiTo0 = APInt::getSplat(Size, APInt(8, 0x0F)); 5681 auto C_B8Mask4HiTo0 = B.buildConstant(Ty, B8Mask4HiTo0); 5682 auto B8Count = B.buildAnd(Ty, B8CountDirty4Hi, C_B8Mask4HiTo0); 5683 5684 assert(Size<=128 && "Scalar size is too large for CTPOP lower algorithm"); 5685 // 8 bits can hold CTPOP result of 128 bit int or smaller. Mul with this 5686 // bitmask will set 8 msb in ResTmp to sum of all B8Counts in 8 bit blocks. 5687 auto MulMask = B.buildConstant(Ty, APInt::getSplat(Size, APInt(8, 0x01))); 5688 auto ResTmp = B.buildMul(Ty, B8Count, MulMask); 5689 5690 // Shift count result from 8 high bits to low bits. 5691 auto C_SizeM8 = B.buildConstant(Ty, Size - 8); 5692 B.buildLShr(MI.getOperand(0).getReg(), ResTmp, C_SizeM8); 5693 5694 MI.eraseFromParent(); 5695 return Legalized; 5696 } 5697 } 5698 } 5699 5700 // Check that (every element of) Reg is undef or not an exact multiple of BW. 5701 static bool isNonZeroModBitWidthOrUndef(const MachineRegisterInfo &MRI, 5702 Register Reg, unsigned BW) { 5703 return matchUnaryPredicate( 5704 MRI, Reg, 5705 [=](const Constant *C) { 5706 // Null constant here means an undef. 5707 const ConstantInt *CI = dyn_cast_or_null<ConstantInt>(C); 5708 return !CI || CI->getValue().urem(BW) != 0; 5709 }, 5710 /*AllowUndefs*/ true); 5711 } 5712 5713 LegalizerHelper::LegalizeResult 5714 LegalizerHelper::lowerFunnelShiftWithInverse(MachineInstr &MI) { 5715 Register Dst = MI.getOperand(0).getReg(); 5716 Register X = MI.getOperand(1).getReg(); 5717 Register Y = MI.getOperand(2).getReg(); 5718 Register Z = MI.getOperand(3).getReg(); 5719 LLT Ty = MRI.getType(Dst); 5720 LLT ShTy = MRI.getType(Z); 5721 5722 unsigned BW = Ty.getScalarSizeInBits(); 5723 5724 if (!isPowerOf2_32(BW)) 5725 return UnableToLegalize; 5726 5727 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5728 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; 5729 5730 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { 5731 // fshl X, Y, Z -> fshr X, Y, -Z 5732 // fshr X, Y, Z -> fshl X, Y, -Z 5733 auto Zero = MIRBuilder.buildConstant(ShTy, 0); 5734 Z = MIRBuilder.buildSub(Ty, Zero, Z).getReg(0); 5735 } else { 5736 // fshl X, Y, Z -> fshr (srl X, 1), (fshr X, Y, 1), ~Z 5737 // fshr X, Y, Z -> fshl (fshl X, Y, 1), (shl Y, 1), ~Z 5738 auto One = MIRBuilder.buildConstant(ShTy, 1); 5739 if (IsFSHL) { 5740 Y = MIRBuilder.buildInstr(RevOpcode, {Ty}, {X, Y, One}).getReg(0); 5741 X = MIRBuilder.buildLShr(Ty, X, One).getReg(0); 5742 } else { 5743 X = MIRBuilder.buildInstr(RevOpcode, {Ty}, {X, Y, One}).getReg(0); 5744 Y = MIRBuilder.buildShl(Ty, Y, One).getReg(0); 5745 } 5746 5747 Z = MIRBuilder.buildNot(ShTy, Z).getReg(0); 5748 } 5749 5750 MIRBuilder.buildInstr(RevOpcode, {Dst}, {X, Y, Z}); 5751 MI.eraseFromParent(); 5752 return Legalized; 5753 } 5754 5755 LegalizerHelper::LegalizeResult 5756 LegalizerHelper::lowerFunnelShiftAsShifts(MachineInstr &MI) { 5757 Register Dst = MI.getOperand(0).getReg(); 5758 Register X = MI.getOperand(1).getReg(); 5759 Register Y = MI.getOperand(2).getReg(); 5760 Register Z = MI.getOperand(3).getReg(); 5761 LLT Ty = MRI.getType(Dst); 5762 LLT ShTy = MRI.getType(Z); 5763 5764 const unsigned BW = Ty.getScalarSizeInBits(); 5765 const bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5766 5767 Register ShX, ShY; 5768 Register ShAmt, InvShAmt; 5769 5770 // FIXME: Emit optimized urem by constant instead of letting it expand later. 5771 if (isNonZeroModBitWidthOrUndef(MRI, Z, BW)) { 5772 // fshl: X << C | Y >> (BW - C) 5773 // fshr: X << (BW - C) | Y >> C 5774 // where C = Z % BW is not zero 5775 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); 5776 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); 5777 InvShAmt = MIRBuilder.buildSub(ShTy, BitWidthC, ShAmt).getReg(0); 5778 ShX = MIRBuilder.buildShl(Ty, X, IsFSHL ? ShAmt : InvShAmt).getReg(0); 5779 ShY = MIRBuilder.buildLShr(Ty, Y, IsFSHL ? InvShAmt : ShAmt).getReg(0); 5780 } else { 5781 // fshl: X << (Z % BW) | Y >> 1 >> (BW - 1 - (Z % BW)) 5782 // fshr: X << 1 << (BW - 1 - (Z % BW)) | Y >> (Z % BW) 5783 auto Mask = MIRBuilder.buildConstant(ShTy, BW - 1); 5784 if (isPowerOf2_32(BW)) { 5785 // Z % BW -> Z & (BW - 1) 5786 ShAmt = MIRBuilder.buildAnd(ShTy, Z, Mask).getReg(0); 5787 // (BW - 1) - (Z % BW) -> ~Z & (BW - 1) 5788 auto NotZ = MIRBuilder.buildNot(ShTy, Z); 5789 InvShAmt = MIRBuilder.buildAnd(ShTy, NotZ, Mask).getReg(0); 5790 } else { 5791 auto BitWidthC = MIRBuilder.buildConstant(ShTy, BW); 5792 ShAmt = MIRBuilder.buildURem(ShTy, Z, BitWidthC).getReg(0); 5793 InvShAmt = MIRBuilder.buildSub(ShTy, Mask, ShAmt).getReg(0); 5794 } 5795 5796 auto One = MIRBuilder.buildConstant(ShTy, 1); 5797 if (IsFSHL) { 5798 ShX = MIRBuilder.buildShl(Ty, X, ShAmt).getReg(0); 5799 auto ShY1 = MIRBuilder.buildLShr(Ty, Y, One); 5800 ShY = MIRBuilder.buildLShr(Ty, ShY1, InvShAmt).getReg(0); 5801 } else { 5802 auto ShX1 = MIRBuilder.buildShl(Ty, X, One); 5803 ShX = MIRBuilder.buildShl(Ty, ShX1, InvShAmt).getReg(0); 5804 ShY = MIRBuilder.buildLShr(Ty, Y, ShAmt).getReg(0); 5805 } 5806 } 5807 5808 MIRBuilder.buildOr(Dst, ShX, ShY); 5809 MI.eraseFromParent(); 5810 return Legalized; 5811 } 5812 5813 LegalizerHelper::LegalizeResult 5814 LegalizerHelper::lowerFunnelShift(MachineInstr &MI) { 5815 // These operations approximately do the following (while avoiding undefined 5816 // shifts by BW): 5817 // G_FSHL: (X << (Z % BW)) | (Y >> (BW - (Z % BW))) 5818 // G_FSHR: (X << (BW - (Z % BW))) | (Y >> (Z % BW)) 5819 Register Dst = MI.getOperand(0).getReg(); 5820 LLT Ty = MRI.getType(Dst); 5821 LLT ShTy = MRI.getType(MI.getOperand(3).getReg()); 5822 5823 bool IsFSHL = MI.getOpcode() == TargetOpcode::G_FSHL; 5824 unsigned RevOpcode = IsFSHL ? TargetOpcode::G_FSHR : TargetOpcode::G_FSHL; 5825 5826 // TODO: Use smarter heuristic that accounts for vector legalization. 5827 if (LI.getAction({RevOpcode, {Ty, ShTy}}).Action == Lower) 5828 return lowerFunnelShiftAsShifts(MI); 5829 5830 // This only works for powers of 2, fallback to shifts if it fails. 5831 LegalizerHelper::LegalizeResult Result = lowerFunnelShiftWithInverse(MI); 5832 if (Result == UnableToLegalize) 5833 return lowerFunnelShiftAsShifts(MI); 5834 return Result; 5835 } 5836 5837 LegalizerHelper::LegalizeResult 5838 LegalizerHelper::lowerRotateWithReverseRotate(MachineInstr &MI) { 5839 Register Dst = MI.getOperand(0).getReg(); 5840 Register Src = MI.getOperand(1).getReg(); 5841 Register Amt = MI.getOperand(2).getReg(); 5842 LLT AmtTy = MRI.getType(Amt); 5843 auto Zero = MIRBuilder.buildConstant(AmtTy, 0); 5844 bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL; 5845 unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL; 5846 auto Neg = MIRBuilder.buildSub(AmtTy, Zero, Amt); 5847 MIRBuilder.buildInstr(RevRot, {Dst}, {Src, Neg}); 5848 MI.eraseFromParent(); 5849 return Legalized; 5850 } 5851 5852 LegalizerHelper::LegalizeResult LegalizerHelper::lowerRotate(MachineInstr &MI) { 5853 Register Dst = MI.getOperand(0).getReg(); 5854 Register Src = MI.getOperand(1).getReg(); 5855 Register Amt = MI.getOperand(2).getReg(); 5856 LLT DstTy = MRI.getType(Dst); 5857 LLT SrcTy = MRI.getType(Dst); 5858 LLT AmtTy = MRI.getType(Amt); 5859 5860 unsigned EltSizeInBits = DstTy.getScalarSizeInBits(); 5861 bool IsLeft = MI.getOpcode() == TargetOpcode::G_ROTL; 5862 5863 MIRBuilder.setInstrAndDebugLoc(MI); 5864 5865 // If a rotate in the other direction is supported, use it. 5866 unsigned RevRot = IsLeft ? TargetOpcode::G_ROTR : TargetOpcode::G_ROTL; 5867 if (LI.isLegalOrCustom({RevRot, {DstTy, SrcTy}}) && 5868 isPowerOf2_32(EltSizeInBits)) 5869 return lowerRotateWithReverseRotate(MI); 5870 5871 auto Zero = MIRBuilder.buildConstant(AmtTy, 0); 5872 unsigned ShOpc = IsLeft ? TargetOpcode::G_SHL : TargetOpcode::G_LSHR; 5873 unsigned RevShiftOpc = IsLeft ? TargetOpcode::G_LSHR : TargetOpcode::G_SHL; 5874 auto BitWidthMinusOneC = MIRBuilder.buildConstant(AmtTy, EltSizeInBits - 1); 5875 Register ShVal; 5876 Register RevShiftVal; 5877 if (isPowerOf2_32(EltSizeInBits)) { 5878 // (rotl x, c) -> x << (c & (w - 1)) | x >> (-c & (w - 1)) 5879 // (rotr x, c) -> x >> (c & (w - 1)) | x << (-c & (w - 1)) 5880 auto NegAmt = MIRBuilder.buildSub(AmtTy, Zero, Amt); 5881 auto ShAmt = MIRBuilder.buildAnd(AmtTy, Amt, BitWidthMinusOneC); 5882 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); 5883 auto RevAmt = MIRBuilder.buildAnd(AmtTy, NegAmt, BitWidthMinusOneC); 5884 RevShiftVal = 5885 MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Src, RevAmt}).getReg(0); 5886 } else { 5887 // (rotl x, c) -> x << (c % w) | x >> 1 >> (w - 1 - (c % w)) 5888 // (rotr x, c) -> x >> (c % w) | x << 1 << (w - 1 - (c % w)) 5889 auto BitWidthC = MIRBuilder.buildConstant(AmtTy, EltSizeInBits); 5890 auto ShAmt = MIRBuilder.buildURem(AmtTy, Amt, BitWidthC); 5891 ShVal = MIRBuilder.buildInstr(ShOpc, {DstTy}, {Src, ShAmt}).getReg(0); 5892 auto RevAmt = MIRBuilder.buildSub(AmtTy, BitWidthMinusOneC, ShAmt); 5893 auto One = MIRBuilder.buildConstant(AmtTy, 1); 5894 auto Inner = MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Src, One}); 5895 RevShiftVal = 5896 MIRBuilder.buildInstr(RevShiftOpc, {DstTy}, {Inner, RevAmt}).getReg(0); 5897 } 5898 MIRBuilder.buildOr(Dst, ShVal, RevShiftVal); 5899 MI.eraseFromParent(); 5900 return Legalized; 5901 } 5902 5903 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float 5904 // representation. 5905 LegalizerHelper::LegalizeResult 5906 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) { 5907 Register Dst = MI.getOperand(0).getReg(); 5908 Register Src = MI.getOperand(1).getReg(); 5909 const LLT S64 = LLT::scalar(64); 5910 const LLT S32 = LLT::scalar(32); 5911 const LLT S1 = LLT::scalar(1); 5912 5913 assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32); 5914 5915 // unsigned cul2f(ulong u) { 5916 // uint lz = clz(u); 5917 // uint e = (u != 0) ? 127U + 63U - lz : 0; 5918 // u = (u << lz) & 0x7fffffffffffffffUL; 5919 // ulong t = u & 0xffffffffffUL; 5920 // uint v = (e << 23) | (uint)(u >> 40); 5921 // uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U); 5922 // return as_float(v + r); 5923 // } 5924 5925 auto Zero32 = MIRBuilder.buildConstant(S32, 0); 5926 auto Zero64 = MIRBuilder.buildConstant(S64, 0); 5927 5928 auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src); 5929 5930 auto K = MIRBuilder.buildConstant(S32, 127U + 63U); 5931 auto Sub = MIRBuilder.buildSub(S32, K, LZ); 5932 5933 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64); 5934 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32); 5935 5936 auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1); 5937 auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ); 5938 5939 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0); 5940 5941 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL); 5942 auto T = MIRBuilder.buildAnd(S64, U, Mask1); 5943 5944 auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40)); 5945 auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23)); 5946 auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl)); 5947 5948 auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL); 5949 auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C); 5950 auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C); 5951 auto One = MIRBuilder.buildConstant(S32, 1); 5952 5953 auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One); 5954 auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32); 5955 auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0); 5956 MIRBuilder.buildAdd(Dst, V, R); 5957 5958 MI.eraseFromParent(); 5959 return Legalized; 5960 } 5961 5962 LegalizerHelper::LegalizeResult LegalizerHelper::lowerUITOFP(MachineInstr &MI) { 5963 Register Dst = MI.getOperand(0).getReg(); 5964 Register Src = MI.getOperand(1).getReg(); 5965 LLT DstTy = MRI.getType(Dst); 5966 LLT SrcTy = MRI.getType(Src); 5967 5968 if (SrcTy == LLT::scalar(1)) { 5969 auto True = MIRBuilder.buildFConstant(DstTy, 1.0); 5970 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 5971 MIRBuilder.buildSelect(Dst, Src, True, False); 5972 MI.eraseFromParent(); 5973 return Legalized; 5974 } 5975 5976 if (SrcTy != LLT::scalar(64)) 5977 return UnableToLegalize; 5978 5979 if (DstTy == LLT::scalar(32)) { 5980 // TODO: SelectionDAG has several alternative expansions to port which may 5981 // be more reasonble depending on the available instructions. If a target 5982 // has sitofp, does not have CTLZ, or can efficiently use f64 as an 5983 // intermediate type, this is probably worse. 5984 return lowerU64ToF32BitOps(MI); 5985 } 5986 5987 return UnableToLegalize; 5988 } 5989 5990 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSITOFP(MachineInstr &MI) { 5991 Register Dst = MI.getOperand(0).getReg(); 5992 Register Src = MI.getOperand(1).getReg(); 5993 LLT DstTy = MRI.getType(Dst); 5994 LLT SrcTy = MRI.getType(Src); 5995 5996 const LLT S64 = LLT::scalar(64); 5997 const LLT S32 = LLT::scalar(32); 5998 const LLT S1 = LLT::scalar(1); 5999 6000 if (SrcTy == S1) { 6001 auto True = MIRBuilder.buildFConstant(DstTy, -1.0); 6002 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); 6003 MIRBuilder.buildSelect(Dst, Src, True, False); 6004 MI.eraseFromParent(); 6005 return Legalized; 6006 } 6007 6008 if (SrcTy != S64) 6009 return UnableToLegalize; 6010 6011 if (DstTy == S32) { 6012 // signed cl2f(long l) { 6013 // long s = l >> 63; 6014 // float r = cul2f((l + s) ^ s); 6015 // return s ? -r : r; 6016 // } 6017 Register L = Src; 6018 auto SignBit = MIRBuilder.buildConstant(S64, 63); 6019 auto S = MIRBuilder.buildAShr(S64, L, SignBit); 6020 6021 auto LPlusS = MIRBuilder.buildAdd(S64, L, S); 6022 auto Xor = MIRBuilder.buildXor(S64, LPlusS, S); 6023 auto R = MIRBuilder.buildUITOFP(S32, Xor); 6024 6025 auto RNeg = MIRBuilder.buildFNeg(S32, R); 6026 auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S, 6027 MIRBuilder.buildConstant(S64, 0)); 6028 MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R); 6029 MI.eraseFromParent(); 6030 return Legalized; 6031 } 6032 6033 return UnableToLegalize; 6034 } 6035 6036 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOUI(MachineInstr &MI) { 6037 Register Dst = MI.getOperand(0).getReg(); 6038 Register Src = MI.getOperand(1).getReg(); 6039 LLT DstTy = MRI.getType(Dst); 6040 LLT SrcTy = MRI.getType(Src); 6041 const LLT S64 = LLT::scalar(64); 6042 const LLT S32 = LLT::scalar(32); 6043 6044 if (SrcTy != S64 && SrcTy != S32) 6045 return UnableToLegalize; 6046 if (DstTy != S32 && DstTy != S64) 6047 return UnableToLegalize; 6048 6049 // FPTOSI gives same result as FPTOUI for positive signed integers. 6050 // FPTOUI needs to deal with fp values that convert to unsigned integers 6051 // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp. 6052 6053 APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits()); 6054 APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle() 6055 : APFloat::IEEEdouble(), 6056 APInt::getNullValue(SrcTy.getSizeInBits())); 6057 TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven); 6058 6059 MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src); 6060 6061 MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP); 6062 // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on 6063 // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1. 6064 MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold); 6065 MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub); 6066 MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt); 6067 MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit); 6068 6069 const LLT S1 = LLT::scalar(1); 6070 6071 MachineInstrBuilder FCMP = 6072 MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold); 6073 MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res); 6074 6075 MI.eraseFromParent(); 6076 return Legalized; 6077 } 6078 6079 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPTOSI(MachineInstr &MI) { 6080 Register Dst = MI.getOperand(0).getReg(); 6081 Register Src = MI.getOperand(1).getReg(); 6082 LLT DstTy = MRI.getType(Dst); 6083 LLT SrcTy = MRI.getType(Src); 6084 const LLT S64 = LLT::scalar(64); 6085 const LLT S32 = LLT::scalar(32); 6086 6087 // FIXME: Only f32 to i64 conversions are supported. 6088 if (SrcTy.getScalarType() != S32 || DstTy.getScalarType() != S64) 6089 return UnableToLegalize; 6090 6091 // Expand f32 -> i64 conversion 6092 // This algorithm comes from compiler-rt's implementation of fixsfdi: 6093 // https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/fixsfdi.c 6094 6095 unsigned SrcEltBits = SrcTy.getScalarSizeInBits(); 6096 6097 auto ExponentMask = MIRBuilder.buildConstant(SrcTy, 0x7F800000); 6098 auto ExponentLoBit = MIRBuilder.buildConstant(SrcTy, 23); 6099 6100 auto AndExpMask = MIRBuilder.buildAnd(SrcTy, Src, ExponentMask); 6101 auto ExponentBits = MIRBuilder.buildLShr(SrcTy, AndExpMask, ExponentLoBit); 6102 6103 auto SignMask = MIRBuilder.buildConstant(SrcTy, 6104 APInt::getSignMask(SrcEltBits)); 6105 auto AndSignMask = MIRBuilder.buildAnd(SrcTy, Src, SignMask); 6106 auto SignLowBit = MIRBuilder.buildConstant(SrcTy, SrcEltBits - 1); 6107 auto Sign = MIRBuilder.buildAShr(SrcTy, AndSignMask, SignLowBit); 6108 Sign = MIRBuilder.buildSExt(DstTy, Sign); 6109 6110 auto MantissaMask = MIRBuilder.buildConstant(SrcTy, 0x007FFFFF); 6111 auto AndMantissaMask = MIRBuilder.buildAnd(SrcTy, Src, MantissaMask); 6112 auto K = MIRBuilder.buildConstant(SrcTy, 0x00800000); 6113 6114 auto R = MIRBuilder.buildOr(SrcTy, AndMantissaMask, K); 6115 R = MIRBuilder.buildZExt(DstTy, R); 6116 6117 auto Bias = MIRBuilder.buildConstant(SrcTy, 127); 6118 auto Exponent = MIRBuilder.buildSub(SrcTy, ExponentBits, Bias); 6119 auto SubExponent = MIRBuilder.buildSub(SrcTy, Exponent, ExponentLoBit); 6120 auto ExponentSub = MIRBuilder.buildSub(SrcTy, ExponentLoBit, Exponent); 6121 6122 auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent); 6123 auto Srl = MIRBuilder.buildLShr(DstTy, R, ExponentSub); 6124 6125 const LLT S1 = LLT::scalar(1); 6126 auto CmpGt = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, 6127 S1, Exponent, ExponentLoBit); 6128 6129 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl); 6130 6131 auto XorSign = MIRBuilder.buildXor(DstTy, R, Sign); 6132 auto Ret = MIRBuilder.buildSub(DstTy, XorSign, Sign); 6133 6134 auto ZeroSrcTy = MIRBuilder.buildConstant(SrcTy, 0); 6135 6136 auto ExponentLt0 = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, 6137 S1, Exponent, ZeroSrcTy); 6138 6139 auto ZeroDstTy = MIRBuilder.buildConstant(DstTy, 0); 6140 MIRBuilder.buildSelect(Dst, ExponentLt0, ZeroDstTy, Ret); 6141 6142 MI.eraseFromParent(); 6143 return Legalized; 6144 } 6145 6146 // f64 -> f16 conversion using round-to-nearest-even rounding mode. 6147 LegalizerHelper::LegalizeResult 6148 LegalizerHelper::lowerFPTRUNC_F64_TO_F16(MachineInstr &MI) { 6149 Register Dst = MI.getOperand(0).getReg(); 6150 Register Src = MI.getOperand(1).getReg(); 6151 6152 if (MRI.getType(Src).isVector()) // TODO: Handle vectors directly. 6153 return UnableToLegalize; 6154 6155 const unsigned ExpMask = 0x7ff; 6156 const unsigned ExpBiasf64 = 1023; 6157 const unsigned ExpBiasf16 = 15; 6158 const LLT S32 = LLT::scalar(32); 6159 const LLT S1 = LLT::scalar(1); 6160 6161 auto Unmerge = MIRBuilder.buildUnmerge(S32, Src); 6162 Register U = Unmerge.getReg(0); 6163 Register UH = Unmerge.getReg(1); 6164 6165 auto E = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 20)); 6166 E = MIRBuilder.buildAnd(S32, E, MIRBuilder.buildConstant(S32, ExpMask)); 6167 6168 // Subtract the fp64 exponent bias (1023) to get the real exponent and 6169 // add the f16 bias (15) to get the biased exponent for the f16 format. 6170 E = MIRBuilder.buildAdd( 6171 S32, E, MIRBuilder.buildConstant(S32, -ExpBiasf64 + ExpBiasf16)); 6172 6173 auto M = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 8)); 6174 M = MIRBuilder.buildAnd(S32, M, MIRBuilder.buildConstant(S32, 0xffe)); 6175 6176 auto MaskedSig = MIRBuilder.buildAnd(S32, UH, 6177 MIRBuilder.buildConstant(S32, 0x1ff)); 6178 MaskedSig = MIRBuilder.buildOr(S32, MaskedSig, U); 6179 6180 auto Zero = MIRBuilder.buildConstant(S32, 0); 6181 auto SigCmpNE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, MaskedSig, Zero); 6182 auto Lo40Set = MIRBuilder.buildZExt(S32, SigCmpNE0); 6183 M = MIRBuilder.buildOr(S32, M, Lo40Set); 6184 6185 // (M != 0 ? 0x0200 : 0) | 0x7c00; 6186 auto Bits0x200 = MIRBuilder.buildConstant(S32, 0x0200); 6187 auto CmpM_NE0 = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, M, Zero); 6188 auto SelectCC = MIRBuilder.buildSelect(S32, CmpM_NE0, Bits0x200, Zero); 6189 6190 auto Bits0x7c00 = MIRBuilder.buildConstant(S32, 0x7c00); 6191 auto I = MIRBuilder.buildOr(S32, SelectCC, Bits0x7c00); 6192 6193 // N = M | (E << 12); 6194 auto EShl12 = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 12)); 6195 auto N = MIRBuilder.buildOr(S32, M, EShl12); 6196 6197 // B = clamp(1-E, 0, 13); 6198 auto One = MIRBuilder.buildConstant(S32, 1); 6199 auto OneSubExp = MIRBuilder.buildSub(S32, One, E); 6200 auto B = MIRBuilder.buildSMax(S32, OneSubExp, Zero); 6201 B = MIRBuilder.buildSMin(S32, B, MIRBuilder.buildConstant(S32, 13)); 6202 6203 auto SigSetHigh = MIRBuilder.buildOr(S32, M, 6204 MIRBuilder.buildConstant(S32, 0x1000)); 6205 6206 auto D = MIRBuilder.buildLShr(S32, SigSetHigh, B); 6207 auto D0 = MIRBuilder.buildShl(S32, D, B); 6208 6209 auto D0_NE_SigSetHigh = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, 6210 D0, SigSetHigh); 6211 auto D1 = MIRBuilder.buildZExt(S32, D0_NE_SigSetHigh); 6212 D = MIRBuilder.buildOr(S32, D, D1); 6213 6214 auto CmpELtOne = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, S1, E, One); 6215 auto V = MIRBuilder.buildSelect(S32, CmpELtOne, D, N); 6216 6217 auto VLow3 = MIRBuilder.buildAnd(S32, V, MIRBuilder.buildConstant(S32, 7)); 6218 V = MIRBuilder.buildLShr(S32, V, MIRBuilder.buildConstant(S32, 2)); 6219 6220 auto VLow3Eq3 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, VLow3, 6221 MIRBuilder.buildConstant(S32, 3)); 6222 auto V0 = MIRBuilder.buildZExt(S32, VLow3Eq3); 6223 6224 auto VLow3Gt5 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, VLow3, 6225 MIRBuilder.buildConstant(S32, 5)); 6226 auto V1 = MIRBuilder.buildZExt(S32, VLow3Gt5); 6227 6228 V1 = MIRBuilder.buildOr(S32, V0, V1); 6229 V = MIRBuilder.buildAdd(S32, V, V1); 6230 6231 auto CmpEGt30 = MIRBuilder.buildICmp(CmpInst::ICMP_SGT, S1, 6232 E, MIRBuilder.buildConstant(S32, 30)); 6233 V = MIRBuilder.buildSelect(S32, CmpEGt30, 6234 MIRBuilder.buildConstant(S32, 0x7c00), V); 6235 6236 auto CmpEGt1039 = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, 6237 E, MIRBuilder.buildConstant(S32, 1039)); 6238 V = MIRBuilder.buildSelect(S32, CmpEGt1039, I, V); 6239 6240 // Extract the sign bit. 6241 auto Sign = MIRBuilder.buildLShr(S32, UH, MIRBuilder.buildConstant(S32, 16)); 6242 Sign = MIRBuilder.buildAnd(S32, Sign, MIRBuilder.buildConstant(S32, 0x8000)); 6243 6244 // Insert the sign bit 6245 V = MIRBuilder.buildOr(S32, Sign, V); 6246 6247 MIRBuilder.buildTrunc(Dst, V); 6248 MI.eraseFromParent(); 6249 return Legalized; 6250 } 6251 6252 LegalizerHelper::LegalizeResult 6253 LegalizerHelper::lowerFPTRUNC(MachineInstr &MI) { 6254 Register Dst = MI.getOperand(0).getReg(); 6255 Register Src = MI.getOperand(1).getReg(); 6256 6257 LLT DstTy = MRI.getType(Dst); 6258 LLT SrcTy = MRI.getType(Src); 6259 const LLT S64 = LLT::scalar(64); 6260 const LLT S16 = LLT::scalar(16); 6261 6262 if (DstTy.getScalarType() == S16 && SrcTy.getScalarType() == S64) 6263 return lowerFPTRUNC_F64_TO_F16(MI); 6264 6265 return UnableToLegalize; 6266 } 6267 6268 // TODO: If RHS is a constant SelectionDAGBuilder expands this into a 6269 // multiplication tree. 6270 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFPOWI(MachineInstr &MI) { 6271 Register Dst = MI.getOperand(0).getReg(); 6272 Register Src0 = MI.getOperand(1).getReg(); 6273 Register Src1 = MI.getOperand(2).getReg(); 6274 LLT Ty = MRI.getType(Dst); 6275 6276 auto CvtSrc1 = MIRBuilder.buildSITOFP(Ty, Src1); 6277 MIRBuilder.buildFPow(Dst, Src0, CvtSrc1, MI.getFlags()); 6278 MI.eraseFromParent(); 6279 return Legalized; 6280 } 6281 6282 static CmpInst::Predicate minMaxToCompare(unsigned Opc) { 6283 switch (Opc) { 6284 case TargetOpcode::G_SMIN: 6285 return CmpInst::ICMP_SLT; 6286 case TargetOpcode::G_SMAX: 6287 return CmpInst::ICMP_SGT; 6288 case TargetOpcode::G_UMIN: 6289 return CmpInst::ICMP_ULT; 6290 case TargetOpcode::G_UMAX: 6291 return CmpInst::ICMP_UGT; 6292 default: 6293 llvm_unreachable("not in integer min/max"); 6294 } 6295 } 6296 6297 LegalizerHelper::LegalizeResult LegalizerHelper::lowerMinMax(MachineInstr &MI) { 6298 Register Dst = MI.getOperand(0).getReg(); 6299 Register Src0 = MI.getOperand(1).getReg(); 6300 Register Src1 = MI.getOperand(2).getReg(); 6301 6302 const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode()); 6303 LLT CmpType = MRI.getType(Dst).changeElementSize(1); 6304 6305 auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1); 6306 MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1); 6307 6308 MI.eraseFromParent(); 6309 return Legalized; 6310 } 6311 6312 LegalizerHelper::LegalizeResult 6313 LegalizerHelper::lowerFCopySign(MachineInstr &MI) { 6314 Register Dst = MI.getOperand(0).getReg(); 6315 Register Src0 = MI.getOperand(1).getReg(); 6316 Register Src1 = MI.getOperand(2).getReg(); 6317 6318 const LLT Src0Ty = MRI.getType(Src0); 6319 const LLT Src1Ty = MRI.getType(Src1); 6320 6321 const int Src0Size = Src0Ty.getScalarSizeInBits(); 6322 const int Src1Size = Src1Ty.getScalarSizeInBits(); 6323 6324 auto SignBitMask = MIRBuilder.buildConstant( 6325 Src0Ty, APInt::getSignMask(Src0Size)); 6326 6327 auto NotSignBitMask = MIRBuilder.buildConstant( 6328 Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1)); 6329 6330 Register And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask).getReg(0); 6331 Register And1; 6332 if (Src0Ty == Src1Ty) { 6333 And1 = MIRBuilder.buildAnd(Src1Ty, Src1, SignBitMask).getReg(0); 6334 } else if (Src0Size > Src1Size) { 6335 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size); 6336 auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1); 6337 auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt); 6338 And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask).getReg(0); 6339 } else { 6340 auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size); 6341 auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt); 6342 auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift); 6343 And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask).getReg(0); 6344 } 6345 6346 // Be careful about setting nsz/nnan/ninf on every instruction, since the 6347 // constants are a nan and -0.0, but the final result should preserve 6348 // everything. 6349 unsigned Flags = MI.getFlags(); 6350 MIRBuilder.buildOr(Dst, And0, And1, Flags); 6351 6352 MI.eraseFromParent(); 6353 return Legalized; 6354 } 6355 6356 LegalizerHelper::LegalizeResult 6357 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) { 6358 unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ? 6359 TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE; 6360 6361 Register Dst = MI.getOperand(0).getReg(); 6362 Register Src0 = MI.getOperand(1).getReg(); 6363 Register Src1 = MI.getOperand(2).getReg(); 6364 LLT Ty = MRI.getType(Dst); 6365 6366 if (!MI.getFlag(MachineInstr::FmNoNans)) { 6367 // Insert canonicalizes if it's possible we need to quiet to get correct 6368 // sNaN behavior. 6369 6370 // Note this must be done here, and not as an optimization combine in the 6371 // absence of a dedicate quiet-snan instruction as we're using an 6372 // omni-purpose G_FCANONICALIZE. 6373 if (!isKnownNeverSNaN(Src0, MRI)) 6374 Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0); 6375 6376 if (!isKnownNeverSNaN(Src1, MRI)) 6377 Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0); 6378 } 6379 6380 // If there are no nans, it's safe to simply replace this with the non-IEEE 6381 // version. 6382 MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags()); 6383 MI.eraseFromParent(); 6384 return Legalized; 6385 } 6386 6387 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) { 6388 // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c 6389 Register DstReg = MI.getOperand(0).getReg(); 6390 LLT Ty = MRI.getType(DstReg); 6391 unsigned Flags = MI.getFlags(); 6392 6393 auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2), 6394 Flags); 6395 MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags); 6396 MI.eraseFromParent(); 6397 return Legalized; 6398 } 6399 6400 LegalizerHelper::LegalizeResult 6401 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) { 6402 Register DstReg = MI.getOperand(0).getReg(); 6403 Register X = MI.getOperand(1).getReg(); 6404 const unsigned Flags = MI.getFlags(); 6405 const LLT Ty = MRI.getType(DstReg); 6406 const LLT CondTy = Ty.changeElementSize(1); 6407 6408 // round(x) => 6409 // t = trunc(x); 6410 // d = fabs(x - t); 6411 // o = copysign(1.0f, x); 6412 // return t + (d >= 0.5 ? o : 0.0); 6413 6414 auto T = MIRBuilder.buildIntrinsicTrunc(Ty, X, Flags); 6415 6416 auto Diff = MIRBuilder.buildFSub(Ty, X, T, Flags); 6417 auto AbsDiff = MIRBuilder.buildFAbs(Ty, Diff, Flags); 6418 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 6419 auto One = MIRBuilder.buildFConstant(Ty, 1.0); 6420 auto Half = MIRBuilder.buildFConstant(Ty, 0.5); 6421 auto SignOne = MIRBuilder.buildFCopysign(Ty, One, X); 6422 6423 auto Cmp = MIRBuilder.buildFCmp(CmpInst::FCMP_OGE, CondTy, AbsDiff, Half, 6424 Flags); 6425 auto Sel = MIRBuilder.buildSelect(Ty, Cmp, SignOne, Zero, Flags); 6426 6427 MIRBuilder.buildFAdd(DstReg, T, Sel, Flags); 6428 6429 MI.eraseFromParent(); 6430 return Legalized; 6431 } 6432 6433 LegalizerHelper::LegalizeResult 6434 LegalizerHelper::lowerFFloor(MachineInstr &MI) { 6435 Register DstReg = MI.getOperand(0).getReg(); 6436 Register SrcReg = MI.getOperand(1).getReg(); 6437 unsigned Flags = MI.getFlags(); 6438 LLT Ty = MRI.getType(DstReg); 6439 const LLT CondTy = Ty.changeElementSize(1); 6440 6441 // result = trunc(src); 6442 // if (src < 0.0 && src != result) 6443 // result += -1.0. 6444 6445 auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags); 6446 auto Zero = MIRBuilder.buildFConstant(Ty, 0.0); 6447 6448 auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy, 6449 SrcReg, Zero, Flags); 6450 auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy, 6451 SrcReg, Trunc, Flags); 6452 auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc); 6453 auto AddVal = MIRBuilder.buildSITOFP(Ty, And); 6454 6455 MIRBuilder.buildFAdd(DstReg, Trunc, AddVal, Flags); 6456 MI.eraseFromParent(); 6457 return Legalized; 6458 } 6459 6460 LegalizerHelper::LegalizeResult 6461 LegalizerHelper::lowerMergeValues(MachineInstr &MI) { 6462 const unsigned NumOps = MI.getNumOperands(); 6463 Register DstReg = MI.getOperand(0).getReg(); 6464 Register Src0Reg = MI.getOperand(1).getReg(); 6465 LLT DstTy = MRI.getType(DstReg); 6466 LLT SrcTy = MRI.getType(Src0Reg); 6467 unsigned PartSize = SrcTy.getSizeInBits(); 6468 6469 LLT WideTy = LLT::scalar(DstTy.getSizeInBits()); 6470 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); 6471 6472 for (unsigned I = 2; I != NumOps; ++I) { 6473 const unsigned Offset = (I - 1) * PartSize; 6474 6475 Register SrcReg = MI.getOperand(I).getReg(); 6476 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg); 6477 6478 Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg : 6479 MRI.createGenericVirtualRegister(WideTy); 6480 6481 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset); 6482 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt); 6483 MIRBuilder.buildOr(NextResult, ResultReg, Shl); 6484 ResultReg = NextResult; 6485 } 6486 6487 if (DstTy.isPointer()) { 6488 if (MIRBuilder.getDataLayout().isNonIntegralAddressSpace( 6489 DstTy.getAddressSpace())) { 6490 LLVM_DEBUG(dbgs() << "Not casting nonintegral address space\n"); 6491 return UnableToLegalize; 6492 } 6493 6494 MIRBuilder.buildIntToPtr(DstReg, ResultReg); 6495 } 6496 6497 MI.eraseFromParent(); 6498 return Legalized; 6499 } 6500 6501 LegalizerHelper::LegalizeResult 6502 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) { 6503 const unsigned NumDst = MI.getNumOperands() - 1; 6504 Register SrcReg = MI.getOperand(NumDst).getReg(); 6505 Register Dst0Reg = MI.getOperand(0).getReg(); 6506 LLT DstTy = MRI.getType(Dst0Reg); 6507 if (DstTy.isPointer()) 6508 return UnableToLegalize; // TODO 6509 6510 SrcReg = coerceToScalar(SrcReg); 6511 if (!SrcReg) 6512 return UnableToLegalize; 6513 6514 // Expand scalarizing unmerge as bitcast to integer and shift. 6515 LLT IntTy = MRI.getType(SrcReg); 6516 6517 MIRBuilder.buildTrunc(Dst0Reg, SrcReg); 6518 6519 const unsigned DstSize = DstTy.getSizeInBits(); 6520 unsigned Offset = DstSize; 6521 for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) { 6522 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset); 6523 auto Shift = MIRBuilder.buildLShr(IntTy, SrcReg, ShiftAmt); 6524 MIRBuilder.buildTrunc(MI.getOperand(I), Shift); 6525 } 6526 6527 MI.eraseFromParent(); 6528 return Legalized; 6529 } 6530 6531 /// Lower a vector extract or insert by writing the vector to a stack temporary 6532 /// and reloading the element or vector. 6533 /// 6534 /// %dst = G_EXTRACT_VECTOR_ELT %vec, %idx 6535 /// => 6536 /// %stack_temp = G_FRAME_INDEX 6537 /// G_STORE %vec, %stack_temp 6538 /// %idx = clamp(%idx, %vec.getNumElements()) 6539 /// %element_ptr = G_PTR_ADD %stack_temp, %idx 6540 /// %dst = G_LOAD %element_ptr 6541 LegalizerHelper::LegalizeResult 6542 LegalizerHelper::lowerExtractInsertVectorElt(MachineInstr &MI) { 6543 Register DstReg = MI.getOperand(0).getReg(); 6544 Register SrcVec = MI.getOperand(1).getReg(); 6545 Register InsertVal; 6546 if (MI.getOpcode() == TargetOpcode::G_INSERT_VECTOR_ELT) 6547 InsertVal = MI.getOperand(2).getReg(); 6548 6549 Register Idx = MI.getOperand(MI.getNumOperands() - 1).getReg(); 6550 6551 LLT VecTy = MRI.getType(SrcVec); 6552 LLT EltTy = VecTy.getElementType(); 6553 if (!EltTy.isByteSized()) { // Not implemented. 6554 LLVM_DEBUG(dbgs() << "Can't handle non-byte element vectors yet\n"); 6555 return UnableToLegalize; 6556 } 6557 6558 unsigned EltBytes = EltTy.getSizeInBytes(); 6559 Align VecAlign = getStackTemporaryAlignment(VecTy); 6560 Align EltAlign; 6561 6562 MachinePointerInfo PtrInfo; 6563 auto StackTemp = createStackTemporary(TypeSize::Fixed(VecTy.getSizeInBytes()), 6564 VecAlign, PtrInfo); 6565 MIRBuilder.buildStore(SrcVec, StackTemp, PtrInfo, VecAlign); 6566 6567 // Get the pointer to the element, and be sure not to hit undefined behavior 6568 // if the index is out of bounds. 6569 Register EltPtr = getVectorElementPointer(StackTemp.getReg(0), VecTy, Idx); 6570 6571 int64_t IdxVal; 6572 if (mi_match(Idx, MRI, m_ICst(IdxVal))) { 6573 int64_t Offset = IdxVal * EltBytes; 6574 PtrInfo = PtrInfo.getWithOffset(Offset); 6575 EltAlign = commonAlignment(VecAlign, Offset); 6576 } else { 6577 // We lose information with a variable offset. 6578 EltAlign = getStackTemporaryAlignment(EltTy); 6579 PtrInfo = MachinePointerInfo(MRI.getType(EltPtr).getAddressSpace()); 6580 } 6581 6582 if (InsertVal) { 6583 // Write the inserted element 6584 MIRBuilder.buildStore(InsertVal, EltPtr, PtrInfo, EltAlign); 6585 6586 // Reload the whole vector. 6587 MIRBuilder.buildLoad(DstReg, StackTemp, PtrInfo, VecAlign); 6588 } else { 6589 MIRBuilder.buildLoad(DstReg, EltPtr, PtrInfo, EltAlign); 6590 } 6591 6592 MI.eraseFromParent(); 6593 return Legalized; 6594 } 6595 6596 LegalizerHelper::LegalizeResult 6597 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) { 6598 Register DstReg = MI.getOperand(0).getReg(); 6599 Register Src0Reg = MI.getOperand(1).getReg(); 6600 Register Src1Reg = MI.getOperand(2).getReg(); 6601 LLT Src0Ty = MRI.getType(Src0Reg); 6602 LLT DstTy = MRI.getType(DstReg); 6603 LLT IdxTy = LLT::scalar(32); 6604 6605 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); 6606 6607 if (DstTy.isScalar()) { 6608 if (Src0Ty.isVector()) 6609 return UnableToLegalize; 6610 6611 // This is just a SELECT. 6612 assert(Mask.size() == 1 && "Expected a single mask element"); 6613 Register Val; 6614 if (Mask[0] < 0 || Mask[0] > 1) 6615 Val = MIRBuilder.buildUndef(DstTy).getReg(0); 6616 else 6617 Val = Mask[0] == 0 ? Src0Reg : Src1Reg; 6618 MIRBuilder.buildCopy(DstReg, Val); 6619 MI.eraseFromParent(); 6620 return Legalized; 6621 } 6622 6623 Register Undef; 6624 SmallVector<Register, 32> BuildVec; 6625 LLT EltTy = DstTy.getElementType(); 6626 6627 for (int Idx : Mask) { 6628 if (Idx < 0) { 6629 if (!Undef.isValid()) 6630 Undef = MIRBuilder.buildUndef(EltTy).getReg(0); 6631 BuildVec.push_back(Undef); 6632 continue; 6633 } 6634 6635 if (Src0Ty.isScalar()) { 6636 BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg); 6637 } else { 6638 int NumElts = Src0Ty.getNumElements(); 6639 Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg; 6640 int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts; 6641 auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx); 6642 auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK); 6643 BuildVec.push_back(Extract.getReg(0)); 6644 } 6645 } 6646 6647 MIRBuilder.buildBuildVector(DstReg, BuildVec); 6648 MI.eraseFromParent(); 6649 return Legalized; 6650 } 6651 6652 LegalizerHelper::LegalizeResult 6653 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) { 6654 const auto &MF = *MI.getMF(); 6655 const auto &TFI = *MF.getSubtarget().getFrameLowering(); 6656 if (TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp) 6657 return UnableToLegalize; 6658 6659 Register Dst = MI.getOperand(0).getReg(); 6660 Register AllocSize = MI.getOperand(1).getReg(); 6661 Align Alignment = assumeAligned(MI.getOperand(2).getImm()); 6662 6663 LLT PtrTy = MRI.getType(Dst); 6664 LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits()); 6665 6666 Register SPReg = TLI.getStackPointerRegisterToSaveRestore(); 6667 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg); 6668 SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp); 6669 6670 // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't 6671 // have to generate an extra instruction to negate the alloc and then use 6672 // G_PTR_ADD to add the negative offset. 6673 auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize); 6674 if (Alignment > Align(1)) { 6675 APInt AlignMask(IntPtrTy.getSizeInBits(), Alignment.value(), true); 6676 AlignMask.negate(); 6677 auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask); 6678 Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst); 6679 } 6680 6681 SPTmp = MIRBuilder.buildCast(PtrTy, Alloc); 6682 MIRBuilder.buildCopy(SPReg, SPTmp); 6683 MIRBuilder.buildCopy(Dst, SPTmp); 6684 6685 MI.eraseFromParent(); 6686 return Legalized; 6687 } 6688 6689 LegalizerHelper::LegalizeResult 6690 LegalizerHelper::lowerExtract(MachineInstr &MI) { 6691 Register Dst = MI.getOperand(0).getReg(); 6692 Register Src = MI.getOperand(1).getReg(); 6693 unsigned Offset = MI.getOperand(2).getImm(); 6694 6695 LLT DstTy = MRI.getType(Dst); 6696 LLT SrcTy = MRI.getType(Src); 6697 6698 if (DstTy.isScalar() && 6699 (SrcTy.isScalar() || 6700 (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) { 6701 LLT SrcIntTy = SrcTy; 6702 if (!SrcTy.isScalar()) { 6703 SrcIntTy = LLT::scalar(SrcTy.getSizeInBits()); 6704 Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0); 6705 } 6706 6707 if (Offset == 0) 6708 MIRBuilder.buildTrunc(Dst, Src); 6709 else { 6710 auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset); 6711 auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt); 6712 MIRBuilder.buildTrunc(Dst, Shr); 6713 } 6714 6715 MI.eraseFromParent(); 6716 return Legalized; 6717 } 6718 6719 return UnableToLegalize; 6720 } 6721 6722 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) { 6723 Register Dst = MI.getOperand(0).getReg(); 6724 Register Src = MI.getOperand(1).getReg(); 6725 Register InsertSrc = MI.getOperand(2).getReg(); 6726 uint64_t Offset = MI.getOperand(3).getImm(); 6727 6728 LLT DstTy = MRI.getType(Src); 6729 LLT InsertTy = MRI.getType(InsertSrc); 6730 6731 if (InsertTy.isVector() || 6732 (DstTy.isVector() && DstTy.getElementType() != InsertTy)) 6733 return UnableToLegalize; 6734 6735 const DataLayout &DL = MIRBuilder.getDataLayout(); 6736 if ((DstTy.isPointer() && 6737 DL.isNonIntegralAddressSpace(DstTy.getAddressSpace())) || 6738 (InsertTy.isPointer() && 6739 DL.isNonIntegralAddressSpace(InsertTy.getAddressSpace()))) { 6740 LLVM_DEBUG(dbgs() << "Not casting non-integral address space integer\n"); 6741 return UnableToLegalize; 6742 } 6743 6744 LLT IntDstTy = DstTy; 6745 6746 if (!DstTy.isScalar()) { 6747 IntDstTy = LLT::scalar(DstTy.getSizeInBits()); 6748 Src = MIRBuilder.buildCast(IntDstTy, Src).getReg(0); 6749 } 6750 6751 if (!InsertTy.isScalar()) { 6752 const LLT IntInsertTy = LLT::scalar(InsertTy.getSizeInBits()); 6753 InsertSrc = MIRBuilder.buildPtrToInt(IntInsertTy, InsertSrc).getReg(0); 6754 } 6755 6756 Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0); 6757 if (Offset != 0) { 6758 auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset); 6759 ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0); 6760 } 6761 6762 APInt MaskVal = APInt::getBitsSetWithWrap( 6763 DstTy.getSizeInBits(), Offset + InsertTy.getSizeInBits(), Offset); 6764 6765 auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal); 6766 auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask); 6767 auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc); 6768 6769 MIRBuilder.buildCast(Dst, Or); 6770 MI.eraseFromParent(); 6771 return Legalized; 6772 } 6773 6774 LegalizerHelper::LegalizeResult 6775 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) { 6776 Register Dst0 = MI.getOperand(0).getReg(); 6777 Register Dst1 = MI.getOperand(1).getReg(); 6778 Register LHS = MI.getOperand(2).getReg(); 6779 Register RHS = MI.getOperand(3).getReg(); 6780 const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO; 6781 6782 LLT Ty = MRI.getType(Dst0); 6783 LLT BoolTy = MRI.getType(Dst1); 6784 6785 if (IsAdd) 6786 MIRBuilder.buildAdd(Dst0, LHS, RHS); 6787 else 6788 MIRBuilder.buildSub(Dst0, LHS, RHS); 6789 6790 // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow. 6791 6792 auto Zero = MIRBuilder.buildConstant(Ty, 0); 6793 6794 // For an addition, the result should be less than one of the operands (LHS) 6795 // if and only if the other operand (RHS) is negative, otherwise there will 6796 // be overflow. 6797 // For a subtraction, the result should be less than one of the operands 6798 // (LHS) if and only if the other operand (RHS) is (non-zero) positive, 6799 // otherwise there will be overflow. 6800 auto ResultLowerThanLHS = 6801 MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS); 6802 auto ConditionRHS = MIRBuilder.buildICmp( 6803 IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero); 6804 6805 MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS); 6806 MI.eraseFromParent(); 6807 return Legalized; 6808 } 6809 6810 LegalizerHelper::LegalizeResult 6811 LegalizerHelper::lowerAddSubSatToMinMax(MachineInstr &MI) { 6812 Register Res = MI.getOperand(0).getReg(); 6813 Register LHS = MI.getOperand(1).getReg(); 6814 Register RHS = MI.getOperand(2).getReg(); 6815 LLT Ty = MRI.getType(Res); 6816 bool IsSigned; 6817 bool IsAdd; 6818 unsigned BaseOp; 6819 switch (MI.getOpcode()) { 6820 default: 6821 llvm_unreachable("unexpected addsat/subsat opcode"); 6822 case TargetOpcode::G_UADDSAT: 6823 IsSigned = false; 6824 IsAdd = true; 6825 BaseOp = TargetOpcode::G_ADD; 6826 break; 6827 case TargetOpcode::G_SADDSAT: 6828 IsSigned = true; 6829 IsAdd = true; 6830 BaseOp = TargetOpcode::G_ADD; 6831 break; 6832 case TargetOpcode::G_USUBSAT: 6833 IsSigned = false; 6834 IsAdd = false; 6835 BaseOp = TargetOpcode::G_SUB; 6836 break; 6837 case TargetOpcode::G_SSUBSAT: 6838 IsSigned = true; 6839 IsAdd = false; 6840 BaseOp = TargetOpcode::G_SUB; 6841 break; 6842 } 6843 6844 if (IsSigned) { 6845 // sadd.sat(a, b) -> 6846 // hi = 0x7fffffff - smax(a, 0) 6847 // lo = 0x80000000 - smin(a, 0) 6848 // a + smin(smax(lo, b), hi) 6849 // ssub.sat(a, b) -> 6850 // lo = smax(a, -1) - 0x7fffffff 6851 // hi = smin(a, -1) - 0x80000000 6852 // a - smin(smax(lo, b), hi) 6853 // TODO: AMDGPU can use a "median of 3" instruction here: 6854 // a +/- med3(lo, b, hi) 6855 uint64_t NumBits = Ty.getScalarSizeInBits(); 6856 auto MaxVal = 6857 MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(NumBits)); 6858 auto MinVal = 6859 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6860 MachineInstrBuilder Hi, Lo; 6861 if (IsAdd) { 6862 auto Zero = MIRBuilder.buildConstant(Ty, 0); 6863 Hi = MIRBuilder.buildSub(Ty, MaxVal, MIRBuilder.buildSMax(Ty, LHS, Zero)); 6864 Lo = MIRBuilder.buildSub(Ty, MinVal, MIRBuilder.buildSMin(Ty, LHS, Zero)); 6865 } else { 6866 auto NegOne = MIRBuilder.buildConstant(Ty, -1); 6867 Lo = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMax(Ty, LHS, NegOne), 6868 MaxVal); 6869 Hi = MIRBuilder.buildSub(Ty, MIRBuilder.buildSMin(Ty, LHS, NegOne), 6870 MinVal); 6871 } 6872 auto RHSClamped = 6873 MIRBuilder.buildSMin(Ty, MIRBuilder.buildSMax(Ty, Lo, RHS), Hi); 6874 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, RHSClamped}); 6875 } else { 6876 // uadd.sat(a, b) -> a + umin(~a, b) 6877 // usub.sat(a, b) -> a - umin(a, b) 6878 Register Not = IsAdd ? MIRBuilder.buildNot(Ty, LHS).getReg(0) : LHS; 6879 auto Min = MIRBuilder.buildUMin(Ty, Not, RHS); 6880 MIRBuilder.buildInstr(BaseOp, {Res}, {LHS, Min}); 6881 } 6882 6883 MI.eraseFromParent(); 6884 return Legalized; 6885 } 6886 6887 LegalizerHelper::LegalizeResult 6888 LegalizerHelper::lowerAddSubSatToAddoSubo(MachineInstr &MI) { 6889 Register Res = MI.getOperand(0).getReg(); 6890 Register LHS = MI.getOperand(1).getReg(); 6891 Register RHS = MI.getOperand(2).getReg(); 6892 LLT Ty = MRI.getType(Res); 6893 LLT BoolTy = Ty.changeElementSize(1); 6894 bool IsSigned; 6895 bool IsAdd; 6896 unsigned OverflowOp; 6897 switch (MI.getOpcode()) { 6898 default: 6899 llvm_unreachable("unexpected addsat/subsat opcode"); 6900 case TargetOpcode::G_UADDSAT: 6901 IsSigned = false; 6902 IsAdd = true; 6903 OverflowOp = TargetOpcode::G_UADDO; 6904 break; 6905 case TargetOpcode::G_SADDSAT: 6906 IsSigned = true; 6907 IsAdd = true; 6908 OverflowOp = TargetOpcode::G_SADDO; 6909 break; 6910 case TargetOpcode::G_USUBSAT: 6911 IsSigned = false; 6912 IsAdd = false; 6913 OverflowOp = TargetOpcode::G_USUBO; 6914 break; 6915 case TargetOpcode::G_SSUBSAT: 6916 IsSigned = true; 6917 IsAdd = false; 6918 OverflowOp = TargetOpcode::G_SSUBO; 6919 break; 6920 } 6921 6922 auto OverflowRes = 6923 MIRBuilder.buildInstr(OverflowOp, {Ty, BoolTy}, {LHS, RHS}); 6924 Register Tmp = OverflowRes.getReg(0); 6925 Register Ov = OverflowRes.getReg(1); 6926 MachineInstrBuilder Clamp; 6927 if (IsSigned) { 6928 // sadd.sat(a, b) -> 6929 // {tmp, ov} = saddo(a, b) 6930 // ov ? (tmp >>s 31) + 0x80000000 : r 6931 // ssub.sat(a, b) -> 6932 // {tmp, ov} = ssubo(a, b) 6933 // ov ? (tmp >>s 31) + 0x80000000 : r 6934 uint64_t NumBits = Ty.getScalarSizeInBits(); 6935 auto ShiftAmount = MIRBuilder.buildConstant(Ty, NumBits - 1); 6936 auto Sign = MIRBuilder.buildAShr(Ty, Tmp, ShiftAmount); 6937 auto MinVal = 6938 MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(NumBits)); 6939 Clamp = MIRBuilder.buildAdd(Ty, Sign, MinVal); 6940 } else { 6941 // uadd.sat(a, b) -> 6942 // {tmp, ov} = uaddo(a, b) 6943 // ov ? 0xffffffff : tmp 6944 // usub.sat(a, b) -> 6945 // {tmp, ov} = usubo(a, b) 6946 // ov ? 0 : tmp 6947 Clamp = MIRBuilder.buildConstant(Ty, IsAdd ? -1 : 0); 6948 } 6949 MIRBuilder.buildSelect(Res, Ov, Clamp, Tmp); 6950 6951 MI.eraseFromParent(); 6952 return Legalized; 6953 } 6954 6955 LegalizerHelper::LegalizeResult 6956 LegalizerHelper::lowerShlSat(MachineInstr &MI) { 6957 assert((MI.getOpcode() == TargetOpcode::G_SSHLSAT || 6958 MI.getOpcode() == TargetOpcode::G_USHLSAT) && 6959 "Expected shlsat opcode!"); 6960 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SSHLSAT; 6961 Register Res = MI.getOperand(0).getReg(); 6962 Register LHS = MI.getOperand(1).getReg(); 6963 Register RHS = MI.getOperand(2).getReg(); 6964 LLT Ty = MRI.getType(Res); 6965 LLT BoolTy = Ty.changeElementSize(1); 6966 6967 unsigned BW = Ty.getScalarSizeInBits(); 6968 auto Result = MIRBuilder.buildShl(Ty, LHS, RHS); 6969 auto Orig = IsSigned ? MIRBuilder.buildAShr(Ty, Result, RHS) 6970 : MIRBuilder.buildLShr(Ty, Result, RHS); 6971 6972 MachineInstrBuilder SatVal; 6973 if (IsSigned) { 6974 auto SatMin = MIRBuilder.buildConstant(Ty, APInt::getSignedMinValue(BW)); 6975 auto SatMax = MIRBuilder.buildConstant(Ty, APInt::getSignedMaxValue(BW)); 6976 auto Cmp = MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, LHS, 6977 MIRBuilder.buildConstant(Ty, 0)); 6978 SatVal = MIRBuilder.buildSelect(Ty, Cmp, SatMin, SatMax); 6979 } else { 6980 SatVal = MIRBuilder.buildConstant(Ty, APInt::getMaxValue(BW)); 6981 } 6982 auto Ov = MIRBuilder.buildICmp(CmpInst::ICMP_NE, BoolTy, LHS, Orig); 6983 MIRBuilder.buildSelect(Res, Ov, SatVal, Result); 6984 6985 MI.eraseFromParent(); 6986 return Legalized; 6987 } 6988 6989 LegalizerHelper::LegalizeResult 6990 LegalizerHelper::lowerBswap(MachineInstr &MI) { 6991 Register Dst = MI.getOperand(0).getReg(); 6992 Register Src = MI.getOperand(1).getReg(); 6993 const LLT Ty = MRI.getType(Src); 6994 unsigned SizeInBytes = (Ty.getScalarSizeInBits() + 7) / 8; 6995 unsigned BaseShiftAmt = (SizeInBytes - 1) * 8; 6996 6997 // Swap most and least significant byte, set remaining bytes in Res to zero. 6998 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt); 6999 auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt); 7000 auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 7001 auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft); 7002 7003 // Set i-th high/low byte in Res to i-th low/high byte from Src. 7004 for (unsigned i = 1; i < SizeInBytes / 2; ++i) { 7005 // AND with Mask leaves byte i unchanged and sets remaining bytes to 0. 7006 APInt APMask(SizeInBytes * 8, 0xFF << (i * 8)); 7007 auto Mask = MIRBuilder.buildConstant(Ty, APMask); 7008 auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i); 7009 // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt. 7010 auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask); 7011 auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt); 7012 Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft); 7013 // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask. 7014 auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt); 7015 auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask); 7016 Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight); 7017 } 7018 Res.getInstr()->getOperand(0).setReg(Dst); 7019 7020 MI.eraseFromParent(); 7021 return Legalized; 7022 } 7023 7024 //{ (Src & Mask) >> N } | { (Src << N) & Mask } 7025 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B, 7026 MachineInstrBuilder Src, APInt Mask) { 7027 const LLT Ty = Dst.getLLTTy(*B.getMRI()); 7028 MachineInstrBuilder C_N = B.buildConstant(Ty, N); 7029 MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask); 7030 auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N); 7031 auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0); 7032 return B.buildOr(Dst, LHS, RHS); 7033 } 7034 7035 LegalizerHelper::LegalizeResult 7036 LegalizerHelper::lowerBitreverse(MachineInstr &MI) { 7037 Register Dst = MI.getOperand(0).getReg(); 7038 Register Src = MI.getOperand(1).getReg(); 7039 const LLT Ty = MRI.getType(Src); 7040 unsigned Size = Ty.getSizeInBits(); 7041 7042 MachineInstrBuilder BSWAP = 7043 MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src}); 7044 7045 // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654 7046 // [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4] 7047 // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0] 7048 MachineInstrBuilder Swap4 = 7049 SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0))); 7050 7051 // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76 7052 // [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2] 7053 // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC] 7054 MachineInstrBuilder Swap2 = 7055 SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC))); 7056 7057 // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7 7058 // [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1] 7059 // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA] 7060 SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA))); 7061 7062 MI.eraseFromParent(); 7063 return Legalized; 7064 } 7065 7066 LegalizerHelper::LegalizeResult 7067 LegalizerHelper::lowerReadWriteRegister(MachineInstr &MI) { 7068 MachineFunction &MF = MIRBuilder.getMF(); 7069 7070 bool IsRead = MI.getOpcode() == TargetOpcode::G_READ_REGISTER; 7071 int NameOpIdx = IsRead ? 1 : 0; 7072 int ValRegIndex = IsRead ? 0 : 1; 7073 7074 Register ValReg = MI.getOperand(ValRegIndex).getReg(); 7075 const LLT Ty = MRI.getType(ValReg); 7076 const MDString *RegStr = cast<MDString>( 7077 cast<MDNode>(MI.getOperand(NameOpIdx).getMetadata())->getOperand(0)); 7078 7079 Register PhysReg = TLI.getRegisterByName(RegStr->getString().data(), Ty, MF); 7080 if (!PhysReg.isValid()) 7081 return UnableToLegalize; 7082 7083 if (IsRead) 7084 MIRBuilder.buildCopy(ValReg, PhysReg); 7085 else 7086 MIRBuilder.buildCopy(PhysReg, ValReg); 7087 7088 MI.eraseFromParent(); 7089 return Legalized; 7090 } 7091 7092 LegalizerHelper::LegalizeResult 7093 LegalizerHelper::lowerSMULH_UMULH(MachineInstr &MI) { 7094 bool IsSigned = MI.getOpcode() == TargetOpcode::G_SMULH; 7095 unsigned ExtOp = IsSigned ? TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT; 7096 Register Result = MI.getOperand(0).getReg(); 7097 LLT OrigTy = MRI.getType(Result); 7098 auto SizeInBits = OrigTy.getScalarSizeInBits(); 7099 LLT WideTy = OrigTy.changeElementSize(SizeInBits * 2); 7100 7101 auto LHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(1)}); 7102 auto RHS = MIRBuilder.buildInstr(ExtOp, {WideTy}, {MI.getOperand(2)}); 7103 auto Mul = MIRBuilder.buildMul(WideTy, LHS, RHS); 7104 unsigned ShiftOp = IsSigned ? TargetOpcode::G_ASHR : TargetOpcode::G_LSHR; 7105 7106 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, SizeInBits); 7107 auto Shifted = MIRBuilder.buildInstr(ShiftOp, {WideTy}, {Mul, ShiftAmt}); 7108 MIRBuilder.buildTrunc(Result, Shifted); 7109 7110 MI.eraseFromParent(); 7111 return Legalized; 7112 } 7113 7114 LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) { 7115 // Implement vector G_SELECT in terms of XOR, AND, OR. 7116 Register DstReg = MI.getOperand(0).getReg(); 7117 Register MaskReg = MI.getOperand(1).getReg(); 7118 Register Op1Reg = MI.getOperand(2).getReg(); 7119 Register Op2Reg = MI.getOperand(3).getReg(); 7120 LLT DstTy = MRI.getType(DstReg); 7121 LLT MaskTy = MRI.getType(MaskReg); 7122 LLT Op1Ty = MRI.getType(Op1Reg); 7123 if (!DstTy.isVector()) 7124 return UnableToLegalize; 7125 7126 // Vector selects can have a scalar predicate. If so, splat into a vector and 7127 // finish for later legalization attempts to try again. 7128 if (MaskTy.isScalar()) { 7129 Register MaskElt = MaskReg; 7130 if (MaskTy.getSizeInBits() < DstTy.getScalarSizeInBits()) 7131 MaskElt = MIRBuilder.buildSExt(DstTy.getElementType(), MaskElt).getReg(0); 7132 // Generate a vector splat idiom to be pattern matched later. 7133 auto ShufSplat = MIRBuilder.buildShuffleSplat(DstTy, MaskElt); 7134 Observer.changingInstr(MI); 7135 MI.getOperand(1).setReg(ShufSplat.getReg(0)); 7136 Observer.changedInstr(MI); 7137 return Legalized; 7138 } 7139 7140 if (MaskTy.getSizeInBits() != Op1Ty.getSizeInBits()) { 7141 return UnableToLegalize; 7142 } 7143 7144 auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg); 7145 auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg); 7146 auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask); 7147 MIRBuilder.buildOr(DstReg, NewOp1, NewOp2); 7148 MI.eraseFromParent(); 7149 return Legalized; 7150 } 7151 7152 LegalizerHelper::LegalizeResult LegalizerHelper::lowerDIVREM(MachineInstr &MI) { 7153 // Split DIVREM into individual instructions. 7154 unsigned Opcode = MI.getOpcode(); 7155 7156 MIRBuilder.buildInstr( 7157 Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SDIV 7158 : TargetOpcode::G_UDIV, 7159 {MI.getOperand(0).getReg()}, {MI.getOperand(2), MI.getOperand(3)}); 7160 MIRBuilder.buildInstr( 7161 Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SREM 7162 : TargetOpcode::G_UREM, 7163 {MI.getOperand(1).getReg()}, {MI.getOperand(2), MI.getOperand(3)}); 7164 MI.eraseFromParent(); 7165 return Legalized; 7166 } 7167 7168 LegalizerHelper::LegalizeResult 7169 LegalizerHelper::lowerAbsToAddXor(MachineInstr &MI) { 7170 // Expand %res = G_ABS %a into: 7171 // %v1 = G_ASHR %a, scalar_size-1 7172 // %v2 = G_ADD %a, %v1 7173 // %res = G_XOR %v2, %v1 7174 LLT DstTy = MRI.getType(MI.getOperand(0).getReg()); 7175 Register OpReg = MI.getOperand(1).getReg(); 7176 auto ShiftAmt = 7177 MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - 1); 7178 auto Shift = MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt); 7179 auto Add = MIRBuilder.buildAdd(DstTy, OpReg, Shift); 7180 MIRBuilder.buildXor(MI.getOperand(0).getReg(), Add, Shift); 7181 MI.eraseFromParent(); 7182 return Legalized; 7183 } 7184 7185 LegalizerHelper::LegalizeResult 7186 LegalizerHelper::lowerAbsToMaxNeg(MachineInstr &MI) { 7187 // Expand %res = G_ABS %a into: 7188 // %v1 = G_CONSTANT 0 7189 // %v2 = G_SUB %v1, %a 7190 // %res = G_SMAX %a, %v2 7191 Register SrcReg = MI.getOperand(1).getReg(); 7192 LLT Ty = MRI.getType(SrcReg); 7193 auto Zero = MIRBuilder.buildConstant(Ty, 0).getReg(0); 7194 auto Sub = MIRBuilder.buildSub(Ty, Zero, SrcReg).getReg(0); 7195 MIRBuilder.buildSMax(MI.getOperand(0), SrcReg, Sub); 7196 MI.eraseFromParent(); 7197 return Legalized; 7198 } 7199