1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file implements the LegalizerHelper class to legalize
11 /// individual instructions and the LegalizeMachineIR wrapper pass for the
12 /// primary legalization.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
17 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
24 
25 #include <sstream>
26 
27 #define DEBUG_TYPE "legalizer"
28 
29 using namespace llvm;
30 
31 LegalizerHelper::LegalizerHelper(MachineFunction &MF)
32     : MRI(MF.getRegInfo()), LI(*MF.getSubtarget().getLegalizerInfo()) {
33   MIRBuilder.setMF(MF);
34 }
35 
36 LegalizerHelper::LegalizeResult
37 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
38   DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
39 
40   auto Action = LI.getAction(MI, MRI);
41   switch (std::get<0>(Action)) {
42   case LegalizerInfo::Legal:
43     DEBUG(dbgs() << ".. Already legal\n");
44     return AlreadyLegal;
45   case LegalizerInfo::Libcall:
46     DEBUG(dbgs() << ".. Convert to libcall\n");
47     return libcall(MI);
48   case LegalizerInfo::NarrowScalar:
49     DEBUG(dbgs() << ".. Narrow scalar\n");
50     return narrowScalar(MI, std::get<1>(Action), std::get<2>(Action));
51   case LegalizerInfo::WidenScalar:
52     DEBUG(dbgs() << ".. Widen scalar\n");
53     return widenScalar(MI, std::get<1>(Action), std::get<2>(Action));
54   case LegalizerInfo::Lower:
55     DEBUG(dbgs() << ".. Lower\n");
56     return lower(MI, std::get<1>(Action), std::get<2>(Action));
57   case LegalizerInfo::FewerElements:
58     DEBUG(dbgs() << ".. Reduce number of elements\n");
59     return fewerElementsVector(MI, std::get<1>(Action), std::get<2>(Action));
60   case LegalizerInfo::Custom:
61     DEBUG(dbgs() << ".. Custom legalization\n");
62     return LI.legalizeCustom(MI, MRI, MIRBuilder) ? Legalized
63                                                   : UnableToLegalize;
64   default:
65     DEBUG(dbgs() << ".. Unable to legalize\n");
66     return UnableToLegalize;
67   }
68 }
69 
70 void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
71                                    SmallVectorImpl<unsigned> &VRegs) {
72   for (int i = 0; i < NumParts; ++i)
73     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
74   MIRBuilder.buildUnmerge(VRegs, Reg);
75 }
76 
77 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
78   switch (Opcode) {
79   case TargetOpcode::G_SDIV:
80     assert(Size == 32 && "Unsupported size");
81     return RTLIB::SDIV_I32;
82   case TargetOpcode::G_UDIV:
83     assert(Size == 32 && "Unsupported size");
84     return RTLIB::UDIV_I32;
85   case TargetOpcode::G_SREM:
86     assert(Size == 32 && "Unsupported size");
87     return RTLIB::SREM_I32;
88   case TargetOpcode::G_UREM:
89     assert(Size == 32 && "Unsupported size");
90     return RTLIB::UREM_I32;
91   case TargetOpcode::G_FADD:
92     assert((Size == 32 || Size == 64) && "Unsupported size");
93     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
94   case TargetOpcode::G_FREM:
95     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
96   case TargetOpcode::G_FPOW:
97     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
98   }
99   llvm_unreachable("Unknown libcall function");
100 }
101 
102 LegalizerHelper::LegalizeResult llvm::replaceWithLibcall(
103     MachineInstr &MI, MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
104     const CallLowering::ArgInfo &Result, ArrayRef<CallLowering::ArgInfo> Args) {
105   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
106   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
107   const char *Name = TLI.getLibcallName(Libcall);
108   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
109   MIRBuilder.setInstr(MI);
110   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
111                      MachineOperand::CreateES(Name), Result, Args))
112     return LegalizerHelper::UnableToLegalize;
113 
114   // We're about to remove MI, so move the insert point after it.
115   MIRBuilder.setInsertPt(MIRBuilder.getMBB(),
116                          std::next(MIRBuilder.getInsertPt()));
117 
118   MI.eraseFromParent();
119   return LegalizerHelper::Legalized;
120 }
121 
122 static LegalizerHelper::LegalizeResult
123 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
124               Type *OpType) {
125   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
126   return replaceWithLibcall(MI, MIRBuilder, Libcall,
127                             {MI.getOperand(0).getReg(), OpType},
128                             {{MI.getOperand(1).getReg(), OpType},
129                              {MI.getOperand(2).getReg(), OpType}});
130 }
131 
132 LegalizerHelper::LegalizeResult
133 LegalizerHelper::libcall(MachineInstr &MI) {
134   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
135   unsigned Size = LLTy.getSizeInBits();
136   auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
137 
138   switch (MI.getOpcode()) {
139   default:
140     return UnableToLegalize;
141   case TargetOpcode::G_SDIV:
142   case TargetOpcode::G_UDIV:
143   case TargetOpcode::G_SREM:
144   case TargetOpcode::G_UREM: {
145     Type *HLTy = Type::getInt32Ty(Ctx);
146     return simpleLibcall(MI, MIRBuilder, Size, HLTy);
147   }
148   case TargetOpcode::G_FADD:
149   case TargetOpcode::G_FPOW:
150   case TargetOpcode::G_FREM: {
151     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
152     return simpleLibcall(MI, MIRBuilder, Size, HLTy);
153   }
154   }
155 }
156 
157 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
158                                                               unsigned TypeIdx,
159                                                               LLT NarrowTy) {
160   // FIXME: Don't know how to handle secondary types yet.
161   if (TypeIdx != 0 && MI.getOpcode() != TargetOpcode::G_EXTRACT)
162     return UnableToLegalize;
163 
164   MIRBuilder.setInstr(MI);
165 
166   switch (MI.getOpcode()) {
167   default:
168     return UnableToLegalize;
169   case TargetOpcode::G_ADD: {
170     // Expand in terms of carry-setting/consuming G_ADDE instructions.
171     int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
172                    NarrowTy.getSizeInBits();
173 
174     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
175     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
176     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
177 
178     unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
179     MIRBuilder.buildConstant(CarryIn, 0);
180 
181     for (int i = 0; i < NumParts; ++i) {
182       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
183       unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
184 
185       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
186                             Src2Regs[i], CarryIn);
187 
188       DstRegs.push_back(DstReg);
189       CarryIn = CarryOut;
190     }
191     unsigned DstReg = MI.getOperand(0).getReg();
192     MIRBuilder.buildMerge(DstReg, DstRegs);
193     MI.eraseFromParent();
194     return Legalized;
195   }
196   case TargetOpcode::G_EXTRACT: {
197     if (TypeIdx != 1)
198       return UnableToLegalize;
199 
200     int64_t NarrowSize = NarrowTy.getSizeInBits();
201     int NumParts =
202         MRI.getType(MI.getOperand(1).getReg()).getSizeInBits() / NarrowSize;
203 
204     SmallVector<unsigned, 2> SrcRegs, DstRegs;
205     SmallVector<uint64_t, 2> Indexes;
206     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
207 
208     unsigned OpReg = MI.getOperand(0).getReg();
209     int64_t OpStart = MI.getOperand(2).getImm();
210     int64_t OpSize = MRI.getType(OpReg).getSizeInBits();
211     for (int i = 0; i < NumParts; ++i) {
212       unsigned SrcStart = i * NarrowSize;
213 
214       if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
215         // No part of the extract uses this subregister, ignore it.
216         continue;
217       } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
218         // The entire subregister is extracted, forward the value.
219         DstRegs.push_back(SrcRegs[i]);
220         continue;
221       }
222 
223       // OpSegStart is where this destination segment would start in OpReg if it
224       // extended infinitely in both directions.
225       int64_t ExtractOffset, SegSize;
226       if (OpStart < SrcStart) {
227         ExtractOffset = 0;
228         SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
229       } else {
230         ExtractOffset = OpStart - SrcStart;
231         SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
232       }
233 
234       unsigned SegReg = SrcRegs[i];
235       if (ExtractOffset != 0 || SegSize != NarrowSize) {
236         // A genuine extract is needed.
237         SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
238         MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
239       }
240 
241       DstRegs.push_back(SegReg);
242     }
243 
244     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
245     MI.eraseFromParent();
246     return Legalized;
247   }
248   case TargetOpcode::G_INSERT: {
249     if (TypeIdx != 0)
250       return UnableToLegalize;
251 
252     int64_t NarrowSize = NarrowTy.getSizeInBits();
253     int NumParts =
254         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
255 
256     SmallVector<unsigned, 2> SrcRegs, DstRegs;
257     SmallVector<uint64_t, 2> Indexes;
258     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
259 
260     unsigned OpReg = MI.getOperand(2).getReg();
261     int64_t OpStart = MI.getOperand(3).getImm();
262     int64_t OpSize = MRI.getType(OpReg).getSizeInBits();
263     for (int i = 0; i < NumParts; ++i) {
264       unsigned DstStart = i * NarrowSize;
265 
266       if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
267         // No part of the insert affects this subregister, forward the original.
268         DstRegs.push_back(SrcRegs[i]);
269         continue;
270       } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
271         // The entire subregister is defined by this insert, forward the new
272         // value.
273         DstRegs.push_back(OpReg);
274         continue;
275       }
276 
277       // OpSegStart is where this destination segment would start in OpReg if it
278       // extended infinitely in both directions.
279       int64_t ExtractOffset, InsertOffset, SegSize;
280       if (OpStart < DstStart) {
281         InsertOffset = 0;
282         ExtractOffset = DstStart - OpStart;
283         SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
284       } else {
285         InsertOffset = OpStart - DstStart;
286         ExtractOffset = 0;
287         SegSize =
288             std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
289       }
290 
291       unsigned SegReg = OpReg;
292       if (ExtractOffset != 0 || SegSize != OpSize) {
293         // A genuine extract is needed.
294         SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
295         MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
296       }
297 
298       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
299       MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
300       DstRegs.push_back(DstReg);
301     }
302 
303     assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
304     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
305     MI.eraseFromParent();
306     return Legalized;
307   }
308   case TargetOpcode::G_LOAD: {
309     unsigned NarrowSize = NarrowTy.getSizeInBits();
310     int NumParts =
311         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
312     LLT OffsetTy = LLT::scalar(
313         MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
314 
315     SmallVector<unsigned, 2> DstRegs;
316     for (int i = 0; i < NumParts; ++i) {
317       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
318       unsigned SrcReg = 0;
319       unsigned Adjustment = i * NarrowSize / 8;
320 
321       MIRBuilder.materializeGEP(SrcReg, MI.getOperand(1).getReg(), OffsetTy,
322                                 Adjustment);
323 
324       // TODO: This is conservatively correct, but we probably want to split the
325       // memory operands in the future.
326       MIRBuilder.buildLoad(DstReg, SrcReg, **MI.memoperands_begin());
327 
328       DstRegs.push_back(DstReg);
329     }
330     unsigned DstReg = MI.getOperand(0).getReg();
331     MIRBuilder.buildMerge(DstReg, DstRegs);
332     MI.eraseFromParent();
333     return Legalized;
334   }
335   case TargetOpcode::G_STORE: {
336     unsigned NarrowSize = NarrowTy.getSizeInBits();
337     int NumParts =
338         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
339     LLT OffsetTy = LLT::scalar(
340         MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
341 
342     SmallVector<unsigned, 2> SrcRegs;
343     extractParts(MI.getOperand(0).getReg(), NarrowTy, NumParts, SrcRegs);
344 
345     for (int i = 0; i < NumParts; ++i) {
346       unsigned DstReg = 0;
347       unsigned Adjustment = i * NarrowSize / 8;
348 
349       MIRBuilder.materializeGEP(DstReg, MI.getOperand(1).getReg(), OffsetTy,
350                                 Adjustment);
351 
352       // TODO: This is conservatively correct, but we probably want to split the
353       // memory operands in the future.
354       MIRBuilder.buildStore(SrcRegs[i], DstReg, **MI.memoperands_begin());
355     }
356     MI.eraseFromParent();
357     return Legalized;
358   }
359   case TargetOpcode::G_CONSTANT: {
360     unsigned NarrowSize = NarrowTy.getSizeInBits();
361     int NumParts =
362         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
363     const APInt &Cst = MI.getOperand(1).getCImm()->getValue();
364     LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
365 
366     SmallVector<unsigned, 2> DstRegs;
367     for (int i = 0; i < NumParts; ++i) {
368       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
369       ConstantInt *CI =
370           ConstantInt::get(Ctx, Cst.lshr(NarrowSize * i).trunc(NarrowSize));
371       MIRBuilder.buildConstant(DstReg, *CI);
372       DstRegs.push_back(DstReg);
373     }
374     unsigned DstReg = MI.getOperand(0).getReg();
375     MIRBuilder.buildMerge(DstReg, DstRegs);
376     MI.eraseFromParent();
377     return Legalized;
378   }
379   }
380 }
381 
382 LegalizerHelper::LegalizeResult
383 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
384   MIRBuilder.setInstr(MI);
385 
386   switch (MI.getOpcode()) {
387   default:
388     return UnableToLegalize;
389   case TargetOpcode::G_ADD:
390   case TargetOpcode::G_AND:
391   case TargetOpcode::G_MUL:
392   case TargetOpcode::G_OR:
393   case TargetOpcode::G_XOR:
394   case TargetOpcode::G_SUB:
395   case TargetOpcode::G_SHL: {
396     // Perform operation at larger width (any extension is fine here, high bits
397     // don't affect the result) and then truncate the result back to the
398     // original type.
399     unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
400     unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
401     MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(1).getReg());
402     MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(2).getReg());
403 
404     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
405     MIRBuilder.buildInstr(MI.getOpcode())
406         .addDef(DstExt)
407         .addUse(Src1Ext)
408         .addUse(Src2Ext);
409 
410     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
411     MI.eraseFromParent();
412     return Legalized;
413   }
414   case TargetOpcode::G_SDIV:
415   case TargetOpcode::G_UDIV:
416   case TargetOpcode::G_ASHR:
417   case TargetOpcode::G_LSHR: {
418     unsigned ExtOp = MI.getOpcode() == TargetOpcode::G_SDIV ||
419                              MI.getOpcode() == TargetOpcode::G_ASHR
420                          ? TargetOpcode::G_SEXT
421                          : TargetOpcode::G_ZEXT;
422 
423     unsigned LHSExt = MRI.createGenericVirtualRegister(WideTy);
424     MIRBuilder.buildInstr(ExtOp).addDef(LHSExt).addUse(
425         MI.getOperand(1).getReg());
426 
427     unsigned RHSExt = MRI.createGenericVirtualRegister(WideTy);
428     MIRBuilder.buildInstr(ExtOp).addDef(RHSExt).addUse(
429         MI.getOperand(2).getReg());
430 
431     unsigned ResExt = MRI.createGenericVirtualRegister(WideTy);
432     MIRBuilder.buildInstr(MI.getOpcode())
433         .addDef(ResExt)
434         .addUse(LHSExt)
435         .addUse(RHSExt);
436 
437     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), ResExt);
438     MI.eraseFromParent();
439     return Legalized;
440   }
441   case TargetOpcode::G_SELECT: {
442     if (TypeIdx != 0)
443       return UnableToLegalize;
444 
445     // Perform operation at larger width (any extension is fine here, high bits
446     // don't affect the result) and then truncate the result back to the
447     // original type.
448     unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
449     unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
450     MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(2).getReg());
451     MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(3).getReg());
452 
453     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
454     MIRBuilder.buildInstr(TargetOpcode::G_SELECT)
455         .addDef(DstExt)
456         .addReg(MI.getOperand(1).getReg())
457         .addUse(Src1Ext)
458         .addUse(Src2Ext);
459 
460     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
461     MI.eraseFromParent();
462     return Legalized;
463   }
464   case TargetOpcode::G_FPTOSI:
465   case TargetOpcode::G_FPTOUI: {
466     if (TypeIdx != 0)
467       return UnableToLegalize;
468 
469     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
470     MIRBuilder.buildInstr(MI.getOpcode())
471         .addDef(DstExt)
472         .addUse(MI.getOperand(1).getReg());
473 
474     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
475     MI.eraseFromParent();
476     return Legalized;
477   }
478   case TargetOpcode::G_SITOFP:
479   case TargetOpcode::G_UITOFP: {
480     if (TypeIdx != 1)
481       return UnableToLegalize;
482 
483     unsigned Src = MI.getOperand(1).getReg();
484     unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
485 
486     if (MI.getOpcode() == TargetOpcode::G_SITOFP) {
487       MIRBuilder.buildSExt(SrcExt, Src);
488     } else {
489       assert(MI.getOpcode() == TargetOpcode::G_UITOFP && "Unexpected conv op");
490       MIRBuilder.buildZExt(SrcExt, Src);
491     }
492 
493     MIRBuilder.buildInstr(MI.getOpcode())
494         .addDef(MI.getOperand(0).getReg())
495         .addUse(SrcExt);
496 
497     MI.eraseFromParent();
498     return Legalized;
499   }
500   case TargetOpcode::G_INSERT: {
501     if (TypeIdx != 0)
502       return UnableToLegalize;
503 
504     unsigned Src = MI.getOperand(1).getReg();
505     unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
506     MIRBuilder.buildAnyExt(SrcExt, Src);
507 
508     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
509     auto MIB = MIRBuilder.buildInsert(DstExt, SrcExt, MI.getOperand(2).getReg(),
510                                       MI.getOperand(3).getImm());
511     for (unsigned OpNum = 4; OpNum < MI.getNumOperands(); OpNum += 2) {
512       MIB.addReg(MI.getOperand(OpNum).getReg());
513       MIB.addImm(MI.getOperand(OpNum + 1).getImm());
514     }
515 
516     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
517     MI.eraseFromParent();
518     return Legalized;
519   }
520   case TargetOpcode::G_LOAD: {
521     assert(alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) ==
522                WideTy.getSizeInBits() &&
523            "illegal to increase number of bytes loaded");
524 
525     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
526     MIRBuilder.buildLoad(DstExt, MI.getOperand(1).getReg(),
527                          **MI.memoperands_begin());
528     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
529     MI.eraseFromParent();
530     return Legalized;
531   }
532   case TargetOpcode::G_STORE: {
533     if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(1) ||
534         WideTy != LLT::scalar(8))
535       return UnableToLegalize;
536 
537     auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
538     auto Content = TLI.getBooleanContents(false, false);
539 
540     unsigned ExtOp = TargetOpcode::G_ANYEXT;
541     if (Content == TargetLoweringBase::ZeroOrOneBooleanContent)
542       ExtOp = TargetOpcode::G_ZEXT;
543     else if (Content == TargetLoweringBase::ZeroOrNegativeOneBooleanContent)
544       ExtOp = TargetOpcode::G_SEXT;
545     else
546       ExtOp = TargetOpcode::G_ANYEXT;
547 
548     unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
549     MIRBuilder.buildInstr(ExtOp).addDef(SrcExt).addUse(
550         MI.getOperand(0).getReg());
551     MIRBuilder.buildStore(SrcExt, MI.getOperand(1).getReg(),
552                           **MI.memoperands_begin());
553     MI.eraseFromParent();
554     return Legalized;
555   }
556   case TargetOpcode::G_CONSTANT: {
557     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
558     MIRBuilder.buildConstant(DstExt, *MI.getOperand(1).getCImm());
559     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
560     MI.eraseFromParent();
561     return Legalized;
562   }
563   case TargetOpcode::G_FCONSTANT: {
564     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
565     MIRBuilder.buildFConstant(DstExt, *MI.getOperand(1).getFPImm());
566     MIRBuilder.buildFPTrunc(MI.getOperand(0).getReg(), DstExt);
567     MI.eraseFromParent();
568     return Legalized;
569   }
570   case TargetOpcode::G_BRCOND: {
571     unsigned TstExt = MRI.createGenericVirtualRegister(WideTy);
572     MIRBuilder.buildAnyExt(TstExt, MI.getOperand(0).getReg());
573     MIRBuilder.buildBrCond(TstExt, *MI.getOperand(1).getMBB());
574     MI.eraseFromParent();
575     return Legalized;
576   }
577   case TargetOpcode::G_ICMP: {
578     assert(TypeIdx == 1 && "unable to legalize predicate");
579     bool IsSigned = CmpInst::isSigned(
580         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
581     unsigned Op0Ext = MRI.createGenericVirtualRegister(WideTy);
582     unsigned Op1Ext = MRI.createGenericVirtualRegister(WideTy);
583     if (IsSigned) {
584       MIRBuilder.buildSExt(Op0Ext, MI.getOperand(2).getReg());
585       MIRBuilder.buildSExt(Op1Ext, MI.getOperand(3).getReg());
586     } else {
587       MIRBuilder.buildZExt(Op0Ext, MI.getOperand(2).getReg());
588       MIRBuilder.buildZExt(Op1Ext, MI.getOperand(3).getReg());
589     }
590     MIRBuilder.buildICmp(
591         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
592         MI.getOperand(0).getReg(), Op0Ext, Op1Ext);
593     MI.eraseFromParent();
594     return Legalized;
595   }
596   case TargetOpcode::G_GEP: {
597     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
598     unsigned OffsetExt = MRI.createGenericVirtualRegister(WideTy);
599     MIRBuilder.buildSExt(OffsetExt, MI.getOperand(2).getReg());
600     MI.getOperand(2).setReg(OffsetExt);
601     return Legalized;
602   }
603   }
604 }
605 
606 LegalizerHelper::LegalizeResult
607 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
608   using namespace TargetOpcode;
609   MIRBuilder.setInstr(MI);
610 
611   switch(MI.getOpcode()) {
612   default:
613     return UnableToLegalize;
614   case TargetOpcode::G_SREM:
615   case TargetOpcode::G_UREM: {
616     unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
617     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
618         .addDef(QuotReg)
619         .addUse(MI.getOperand(1).getReg())
620         .addUse(MI.getOperand(2).getReg());
621 
622     unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
623     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
624     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
625                         ProdReg);
626     MI.eraseFromParent();
627     return Legalized;
628   }
629   case TargetOpcode::G_SMULO:
630   case TargetOpcode::G_UMULO: {
631     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
632     // result.
633     unsigned Res = MI.getOperand(0).getReg();
634     unsigned Overflow = MI.getOperand(1).getReg();
635     unsigned LHS = MI.getOperand(2).getReg();
636     unsigned RHS = MI.getOperand(3).getReg();
637 
638     MIRBuilder.buildMul(Res, LHS, RHS);
639 
640     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
641                           ? TargetOpcode::G_SMULH
642                           : TargetOpcode::G_UMULH;
643 
644     unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
645     MIRBuilder.buildInstr(Opcode)
646       .addDef(HiPart)
647       .addUse(LHS)
648       .addUse(RHS);
649 
650     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
651     MIRBuilder.buildConstant(Zero, 0);
652     MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
653     MI.eraseFromParent();
654     return Legalized;
655   }
656   case TargetOpcode::G_FNEG: {
657     // TODO: Handle vector types once we are able to
658     // represent them.
659     if (Ty.isVector())
660       return UnableToLegalize;
661     unsigned Res = MI.getOperand(0).getReg();
662     Type *ZeroTy;
663     LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
664     switch (Ty.getSizeInBits()) {
665     case 16:
666       ZeroTy = Type::getHalfTy(Ctx);
667       break;
668     case 32:
669       ZeroTy = Type::getFloatTy(Ctx);
670       break;
671     case 64:
672       ZeroTy = Type::getDoubleTy(Ctx);
673       break;
674     default:
675       llvm_unreachable("unexpected floating-point type");
676     }
677     ConstantFP &ZeroForNegation =
678         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
679     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
680     MIRBuilder.buildFConstant(Zero, ZeroForNegation);
681     MIRBuilder.buildInstr(TargetOpcode::G_FSUB)
682         .addDef(Res)
683         .addUse(Zero)
684         .addUse(MI.getOperand(1).getReg());
685     MI.eraseFromParent();
686     return Legalized;
687   }
688   case TargetOpcode::G_FSUB: {
689     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
690     // First, check if G_FNEG is marked as Lower. If so, we may
691     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
692     if (LI.getAction({G_FNEG, Ty}).first == LegalizerInfo::Lower)
693       return UnableToLegalize;
694     unsigned Res = MI.getOperand(0).getReg();
695     unsigned LHS = MI.getOperand(1).getReg();
696     unsigned RHS = MI.getOperand(2).getReg();
697     unsigned Neg = MRI.createGenericVirtualRegister(Ty);
698     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
699     MIRBuilder.buildInstr(TargetOpcode::G_FADD)
700         .addDef(Res)
701         .addUse(LHS)
702         .addUse(Neg);
703     MI.eraseFromParent();
704     return Legalized;
705   }
706   }
707 }
708 
709 LegalizerHelper::LegalizeResult
710 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
711                                      LLT NarrowTy) {
712   // FIXME: Don't know how to handle secondary types yet.
713   if (TypeIdx != 0)
714     return UnableToLegalize;
715   switch (MI.getOpcode()) {
716   default:
717     return UnableToLegalize;
718   case TargetOpcode::G_ADD: {
719     unsigned NarrowSize = NarrowTy.getSizeInBits();
720     unsigned DstReg = MI.getOperand(0).getReg();
721     int NumParts = MRI.getType(DstReg).getSizeInBits() / NarrowSize;
722 
723     MIRBuilder.setInstr(MI);
724 
725     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
726     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
727     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
728 
729     for (int i = 0; i < NumParts; ++i) {
730       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
731       MIRBuilder.buildAdd(DstReg, Src1Regs[i], Src2Regs[i]);
732       DstRegs.push_back(DstReg);
733     }
734 
735     MIRBuilder.buildMerge(DstReg, DstRegs);
736     MI.eraseFromParent();
737     return Legalized;
738   }
739   }
740 }
741