1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetFrameLowering.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetLowering.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 
28 #define DEBUG_TYPE "legalizer"
29 
30 using namespace llvm;
31 using namespace LegalizeActions;
32 
33 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
34 ///
35 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
36 /// with any leftover piece as type \p LeftoverTy
37 ///
38 /// Returns -1 in the first element of the pair if the breakdown is not
39 /// satisfiable.
40 static std::pair<int, int>
41 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
42   assert(!LeftoverTy.isValid() && "this is an out argument");
43 
44   unsigned Size = OrigTy.getSizeInBits();
45   unsigned NarrowSize = NarrowTy.getSizeInBits();
46   unsigned NumParts = Size / NarrowSize;
47   unsigned LeftoverSize = Size - NumParts * NarrowSize;
48   assert(Size > NarrowSize);
49 
50   if (LeftoverSize == 0)
51     return {NumParts, 0};
52 
53   if (NarrowTy.isVector()) {
54     unsigned EltSize = OrigTy.getScalarSizeInBits();
55     if (LeftoverSize % EltSize != 0)
56       return {-1, -1};
57     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
58   } else {
59     LeftoverTy = LLT::scalar(LeftoverSize);
60   }
61 
62   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
63   return std::make_pair(NumParts, NumLeftover);
64 }
65 
66 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
67                                  GISelChangeObserver &Observer,
68                                  MachineIRBuilder &Builder)
69     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
70       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
71   MIRBuilder.setMF(MF);
72   MIRBuilder.setChangeObserver(Observer);
73 }
74 
75 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
76                                  GISelChangeObserver &Observer,
77                                  MachineIRBuilder &B)
78     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
79   MIRBuilder.setMF(MF);
80   MIRBuilder.setChangeObserver(Observer);
81 }
82 LegalizerHelper::LegalizeResult
83 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
84   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
85 
86   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
87       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
88     return LI.legalizeIntrinsic(MI, MRI, MIRBuilder) ? Legalized
89                                                      : UnableToLegalize;
90   auto Step = LI.getAction(MI, MRI);
91   switch (Step.Action) {
92   case Legal:
93     LLVM_DEBUG(dbgs() << ".. Already legal\n");
94     return AlreadyLegal;
95   case Libcall:
96     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
97     return libcall(MI);
98   case NarrowScalar:
99     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
100     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
101   case WidenScalar:
102     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
103     return widenScalar(MI, Step.TypeIdx, Step.NewType);
104   case Lower:
105     LLVM_DEBUG(dbgs() << ".. Lower\n");
106     return lower(MI, Step.TypeIdx, Step.NewType);
107   case FewerElements:
108     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
109     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
110   case MoreElements:
111     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
112     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
113   case Custom:
114     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
115     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
116                                                             : UnableToLegalize;
117   default:
118     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
119     return UnableToLegalize;
120   }
121 }
122 
123 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
124                                    SmallVectorImpl<Register> &VRegs) {
125   for (int i = 0; i < NumParts; ++i)
126     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
127   MIRBuilder.buildUnmerge(VRegs, Reg);
128 }
129 
130 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
131                                    LLT MainTy, LLT &LeftoverTy,
132                                    SmallVectorImpl<Register> &VRegs,
133                                    SmallVectorImpl<Register> &LeftoverRegs) {
134   assert(!LeftoverTy.isValid() && "this is an out argument");
135 
136   unsigned RegSize = RegTy.getSizeInBits();
137   unsigned MainSize = MainTy.getSizeInBits();
138   unsigned NumParts = RegSize / MainSize;
139   unsigned LeftoverSize = RegSize - NumParts * MainSize;
140 
141   // Use an unmerge when possible.
142   if (LeftoverSize == 0) {
143     for (unsigned I = 0; I < NumParts; ++I)
144       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
145     MIRBuilder.buildUnmerge(VRegs, Reg);
146     return true;
147   }
148 
149   if (MainTy.isVector()) {
150     unsigned EltSize = MainTy.getScalarSizeInBits();
151     if (LeftoverSize % EltSize != 0)
152       return false;
153     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
154   } else {
155     LeftoverTy = LLT::scalar(LeftoverSize);
156   }
157 
158   // For irregular sizes, extract the individual parts.
159   for (unsigned I = 0; I != NumParts; ++I) {
160     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
161     VRegs.push_back(NewReg);
162     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
163   }
164 
165   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
166        Offset += LeftoverSize) {
167     Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
168     LeftoverRegs.push_back(NewReg);
169     MIRBuilder.buildExtract(NewReg, Reg, Offset);
170   }
171 
172   return true;
173 }
174 
175 static LLT getGCDType(LLT OrigTy, LLT TargetTy) {
176   if (OrigTy.isVector() && TargetTy.isVector()) {
177     assert(OrigTy.getElementType() == TargetTy.getElementType());
178     int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
179                                     TargetTy.getNumElements());
180     return LLT::scalarOrVector(GCD, OrigTy.getElementType());
181   }
182 
183   if (OrigTy.isVector() && !TargetTy.isVector()) {
184     assert(OrigTy.getElementType() == TargetTy);
185     return TargetTy;
186   }
187 
188   assert(!OrigTy.isVector() && !TargetTy.isVector());
189 
190   int GCD = greatestCommonDivisor(OrigTy.getSizeInBits(),
191                                   TargetTy.getSizeInBits());
192   return LLT::scalar(GCD);
193 }
194 
195 void LegalizerHelper::insertParts(Register DstReg,
196                                   LLT ResultTy, LLT PartTy,
197                                   ArrayRef<Register> PartRegs,
198                                   LLT LeftoverTy,
199                                   ArrayRef<Register> LeftoverRegs) {
200   if (!LeftoverTy.isValid()) {
201     assert(LeftoverRegs.empty());
202 
203     if (!ResultTy.isVector()) {
204       MIRBuilder.buildMerge(DstReg, PartRegs);
205       return;
206     }
207 
208     if (PartTy.isVector())
209       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
210     else
211       MIRBuilder.buildBuildVector(DstReg, PartRegs);
212     return;
213   }
214 
215   unsigned PartSize = PartTy.getSizeInBits();
216   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
217 
218   Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
219   MIRBuilder.buildUndef(CurResultReg);
220 
221   unsigned Offset = 0;
222   for (Register PartReg : PartRegs) {
223     Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
224     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
225     CurResultReg = NewResultReg;
226     Offset += PartSize;
227   }
228 
229   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
230     // Use the original output register for the final insert to avoid a copy.
231     Register NewResultReg = (I + 1 == E) ?
232       DstReg : MRI.createGenericVirtualRegister(ResultTy);
233 
234     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
235     CurResultReg = NewResultReg;
236     Offset += LeftoverPartSize;
237   }
238 }
239 
240 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
241   switch (Opcode) {
242   case TargetOpcode::G_SDIV:
243     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
244     switch (Size) {
245     case 32:
246       return RTLIB::SDIV_I32;
247     case 64:
248       return RTLIB::SDIV_I64;
249     case 128:
250       return RTLIB::SDIV_I128;
251     default:
252       llvm_unreachable("unexpected size");
253     }
254   case TargetOpcode::G_UDIV:
255     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
256     switch (Size) {
257     case 32:
258       return RTLIB::UDIV_I32;
259     case 64:
260       return RTLIB::UDIV_I64;
261     case 128:
262       return RTLIB::UDIV_I128;
263     default:
264       llvm_unreachable("unexpected size");
265     }
266   case TargetOpcode::G_SREM:
267     assert((Size == 32 || Size == 64) && "Unsupported size");
268     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
269   case TargetOpcode::G_UREM:
270     assert((Size == 32 || Size == 64) && "Unsupported size");
271     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
272   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
273     assert(Size == 32 && "Unsupported size");
274     return RTLIB::CTLZ_I32;
275   case TargetOpcode::G_FADD:
276     assert((Size == 32 || Size == 64) && "Unsupported size");
277     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
278   case TargetOpcode::G_FSUB:
279     assert((Size == 32 || Size == 64) && "Unsupported size");
280     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
281   case TargetOpcode::G_FMUL:
282     assert((Size == 32 || Size == 64) && "Unsupported size");
283     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
284   case TargetOpcode::G_FDIV:
285     assert((Size == 32 || Size == 64) && "Unsupported size");
286     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
287   case TargetOpcode::G_FEXP:
288     assert((Size == 32 || Size == 64) && "Unsupported size");
289     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
290   case TargetOpcode::G_FEXP2:
291     assert((Size == 32 || Size == 64) && "Unsupported size");
292     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
293   case TargetOpcode::G_FREM:
294     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
295   case TargetOpcode::G_FPOW:
296     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
297   case TargetOpcode::G_FMA:
298     assert((Size == 32 || Size == 64) && "Unsupported size");
299     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
300   case TargetOpcode::G_FSIN:
301     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
302     return Size == 128 ? RTLIB::SIN_F128
303                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
304   case TargetOpcode::G_FCOS:
305     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
306     return Size == 128 ? RTLIB::COS_F128
307                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
308   case TargetOpcode::G_FLOG10:
309     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
310     return Size == 128 ? RTLIB::LOG10_F128
311                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
312   case TargetOpcode::G_FLOG:
313     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
314     return Size == 128 ? RTLIB::LOG_F128
315                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
316   case TargetOpcode::G_FLOG2:
317     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
318     return Size == 128 ? RTLIB::LOG2_F128
319                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
320   case TargetOpcode::G_FCEIL:
321     assert((Size == 32 || Size == 64) && "Unsupported size");
322     return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
323   case TargetOpcode::G_FFLOOR:
324     assert((Size == 32 || Size == 64) && "Unsupported size");
325     return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
326   }
327   llvm_unreachable("Unknown libcall function");
328 }
329 
330 /// True if an instruction is in tail position in its caller. Intended for
331 /// legalizing libcalls as tail calls when possible.
332 static bool isLibCallInTailPosition(MachineInstr &MI) {
333   const Function &F = MI.getParent()->getParent()->getFunction();
334 
335   // Conservatively require the attributes of the call to match those of
336   // the return. Ignore NoAlias and NonNull because they don't affect the
337   // call sequence.
338   AttributeList CallerAttrs = F.getAttributes();
339   if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
340           .removeAttribute(Attribute::NoAlias)
341           .removeAttribute(Attribute::NonNull)
342           .hasAttributes())
343     return false;
344 
345   // It's not safe to eliminate the sign / zero extension of the return value.
346   if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
347       CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
348     return false;
349 
350   // Only tail call if the following instruction is a standard return.
351   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
352   MachineInstr *Next = MI.getNextNode();
353   if (!Next || TII.isTailCall(*Next) || !Next->isReturn())
354     return false;
355 
356   return true;
357 }
358 
359 LegalizerHelper::LegalizeResult
360 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
361                     const CallLowering::ArgInfo &Result,
362                     ArrayRef<CallLowering::ArgInfo> Args) {
363   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
364   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
365   const char *Name = TLI.getLibcallName(Libcall);
366 
367   CallLowering::CallLoweringInfo Info;
368   Info.CallConv = TLI.getLibcallCallingConv(Libcall);
369   Info.Callee = MachineOperand::CreateES(Name);
370   Info.OrigRet = Result;
371   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
372   if (!CLI.lowerCall(MIRBuilder, Info))
373     return LegalizerHelper::UnableToLegalize;
374 
375   return LegalizerHelper::Legalized;
376 }
377 
378 // Useful for libcalls where all operands have the same type.
379 static LegalizerHelper::LegalizeResult
380 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
381               Type *OpType) {
382   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
383 
384   SmallVector<CallLowering::ArgInfo, 3> Args;
385   for (unsigned i = 1; i < MI.getNumOperands(); i++)
386     Args.push_back({MI.getOperand(i).getReg(), OpType});
387   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
388                        Args);
389 }
390 
391 LegalizerHelper::LegalizeResult
392 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
393                        MachineInstr &MI) {
394   assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
395   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
396 
397   SmallVector<CallLowering::ArgInfo, 3> Args;
398   // Add all the args, except for the last which is an imm denoting 'tail'.
399   for (unsigned i = 1; i < MI.getNumOperands() - 1; i++) {
400     Register Reg = MI.getOperand(i).getReg();
401 
402     // Need derive an IR type for call lowering.
403     LLT OpLLT = MRI.getType(Reg);
404     Type *OpTy = nullptr;
405     if (OpLLT.isPointer())
406       OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace());
407     else
408       OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits());
409     Args.push_back({Reg, OpTy});
410   }
411 
412   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
413   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
414   Intrinsic::ID ID = MI.getOperand(0).getIntrinsicID();
415   RTLIB::Libcall RTLibcall;
416   switch (ID) {
417   case Intrinsic::memcpy:
418     RTLibcall = RTLIB::MEMCPY;
419     break;
420   case Intrinsic::memset:
421     RTLibcall = RTLIB::MEMSET;
422     break;
423   case Intrinsic::memmove:
424     RTLibcall = RTLIB::MEMMOVE;
425     break;
426   default:
427     return LegalizerHelper::UnableToLegalize;
428   }
429   const char *Name = TLI.getLibcallName(RTLibcall);
430 
431   MIRBuilder.setInstr(MI);
432 
433   CallLowering::CallLoweringInfo Info;
434   Info.CallConv = TLI.getLibcallCallingConv(RTLibcall);
435   Info.Callee = MachineOperand::CreateES(Name);
436   Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx));
437   Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() == 1 &&
438                     isLibCallInTailPosition(MI);
439 
440   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
441   if (!CLI.lowerCall(MIRBuilder, Info))
442     return LegalizerHelper::UnableToLegalize;
443 
444   if (Info.LoweredTailCall) {
445     assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?");
446     // We must have a return following the call to get past
447     // isLibCallInTailPosition.
448     assert(MI.getNextNode() && MI.getNextNode()->isReturn() &&
449            "Expected instr following MI to be a return?");
450 
451     // We lowered a tail call, so the call is now the return from the block.
452     // Delete the old return.
453     MI.getNextNode()->eraseFromParent();
454   }
455 
456   return LegalizerHelper::Legalized;
457 }
458 
459 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
460                                        Type *FromType) {
461   auto ToMVT = MVT::getVT(ToType);
462   auto FromMVT = MVT::getVT(FromType);
463 
464   switch (Opcode) {
465   case TargetOpcode::G_FPEXT:
466     return RTLIB::getFPEXT(FromMVT, ToMVT);
467   case TargetOpcode::G_FPTRUNC:
468     return RTLIB::getFPROUND(FromMVT, ToMVT);
469   case TargetOpcode::G_FPTOSI:
470     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
471   case TargetOpcode::G_FPTOUI:
472     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
473   case TargetOpcode::G_SITOFP:
474     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
475   case TargetOpcode::G_UITOFP:
476     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
477   }
478   llvm_unreachable("Unsupported libcall function");
479 }
480 
481 static LegalizerHelper::LegalizeResult
482 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
483                   Type *FromType) {
484   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
485   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
486                        {{MI.getOperand(1).getReg(), FromType}});
487 }
488 
489 LegalizerHelper::LegalizeResult
490 LegalizerHelper::libcall(MachineInstr &MI) {
491   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
492   unsigned Size = LLTy.getSizeInBits();
493   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
494 
495   MIRBuilder.setInstr(MI);
496 
497   switch (MI.getOpcode()) {
498   default:
499     return UnableToLegalize;
500   case TargetOpcode::G_SDIV:
501   case TargetOpcode::G_UDIV:
502   case TargetOpcode::G_SREM:
503   case TargetOpcode::G_UREM:
504   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
505     Type *HLTy = IntegerType::get(Ctx, Size);
506     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
507     if (Status != Legalized)
508       return Status;
509     break;
510   }
511   case TargetOpcode::G_FADD:
512   case TargetOpcode::G_FSUB:
513   case TargetOpcode::G_FMUL:
514   case TargetOpcode::G_FDIV:
515   case TargetOpcode::G_FMA:
516   case TargetOpcode::G_FPOW:
517   case TargetOpcode::G_FREM:
518   case TargetOpcode::G_FCOS:
519   case TargetOpcode::G_FSIN:
520   case TargetOpcode::G_FLOG10:
521   case TargetOpcode::G_FLOG:
522   case TargetOpcode::G_FLOG2:
523   case TargetOpcode::G_FEXP:
524   case TargetOpcode::G_FEXP2:
525   case TargetOpcode::G_FCEIL:
526   case TargetOpcode::G_FFLOOR: {
527     if (Size > 64) {
528       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
529       return UnableToLegalize;
530     }
531     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
532     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
533     if (Status != Legalized)
534       return Status;
535     break;
536   }
537   case TargetOpcode::G_FPEXT: {
538     // FIXME: Support other floating point types (half, fp128 etc)
539     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
540     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
541     if (ToSize != 64 || FromSize != 32)
542       return UnableToLegalize;
543     LegalizeResult Status = conversionLibcall(
544         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
545     if (Status != Legalized)
546       return Status;
547     break;
548   }
549   case TargetOpcode::G_FPTRUNC: {
550     // FIXME: Support other floating point types (half, fp128 etc)
551     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
552     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
553     if (ToSize != 32 || FromSize != 64)
554       return UnableToLegalize;
555     LegalizeResult Status = conversionLibcall(
556         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
557     if (Status != Legalized)
558       return Status;
559     break;
560   }
561   case TargetOpcode::G_FPTOSI:
562   case TargetOpcode::G_FPTOUI: {
563     // FIXME: Support other types
564     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
565     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
566     if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
567       return UnableToLegalize;
568     LegalizeResult Status = conversionLibcall(
569         MI, MIRBuilder,
570         ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
571         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
572     if (Status != Legalized)
573       return Status;
574     break;
575   }
576   case TargetOpcode::G_SITOFP:
577   case TargetOpcode::G_UITOFP: {
578     // FIXME: Support other types
579     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
580     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
581     if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
582       return UnableToLegalize;
583     LegalizeResult Status = conversionLibcall(
584         MI, MIRBuilder,
585         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
586         FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
587     if (Status != Legalized)
588       return Status;
589     break;
590   }
591   }
592 
593   MI.eraseFromParent();
594   return Legalized;
595 }
596 
597 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
598                                                               unsigned TypeIdx,
599                                                               LLT NarrowTy) {
600   MIRBuilder.setInstr(MI);
601 
602   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
603   uint64_t NarrowSize = NarrowTy.getSizeInBits();
604 
605   switch (MI.getOpcode()) {
606   default:
607     return UnableToLegalize;
608   case TargetOpcode::G_IMPLICIT_DEF: {
609     // FIXME: add support for when SizeOp0 isn't an exact multiple of
610     // NarrowSize.
611     if (SizeOp0 % NarrowSize != 0)
612       return UnableToLegalize;
613     int NumParts = SizeOp0 / NarrowSize;
614 
615     SmallVector<Register, 2> DstRegs;
616     for (int i = 0; i < NumParts; ++i)
617       DstRegs.push_back(
618           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
619 
620     Register DstReg = MI.getOperand(0).getReg();
621     if(MRI.getType(DstReg).isVector())
622       MIRBuilder.buildBuildVector(DstReg, DstRegs);
623     else
624       MIRBuilder.buildMerge(DstReg, DstRegs);
625     MI.eraseFromParent();
626     return Legalized;
627   }
628   case TargetOpcode::G_CONSTANT: {
629     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
630     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
631     unsigned TotalSize = Ty.getSizeInBits();
632     unsigned NarrowSize = NarrowTy.getSizeInBits();
633     int NumParts = TotalSize / NarrowSize;
634 
635     SmallVector<Register, 4> PartRegs;
636     for (int I = 0; I != NumParts; ++I) {
637       unsigned Offset = I * NarrowSize;
638       auto K = MIRBuilder.buildConstant(NarrowTy,
639                                         Val.lshr(Offset).trunc(NarrowSize));
640       PartRegs.push_back(K.getReg(0));
641     }
642 
643     LLT LeftoverTy;
644     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
645     SmallVector<Register, 1> LeftoverRegs;
646     if (LeftoverBits != 0) {
647       LeftoverTy = LLT::scalar(LeftoverBits);
648       auto K = MIRBuilder.buildConstant(
649         LeftoverTy,
650         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
651       LeftoverRegs.push_back(K.getReg(0));
652     }
653 
654     insertParts(MI.getOperand(0).getReg(),
655                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
656 
657     MI.eraseFromParent();
658     return Legalized;
659   }
660   case TargetOpcode::G_SEXT: {
661     if (TypeIdx != 0)
662       return UnableToLegalize;
663 
664     Register SrcReg = MI.getOperand(1).getReg();
665     LLT SrcTy = MRI.getType(SrcReg);
666 
667     // FIXME: support the general case where the requested NarrowTy may not be
668     // the same as the source type. E.g. s128 = sext(s32)
669     if ((SrcTy.getSizeInBits() != SizeOp0 / 2) ||
670         SrcTy.getSizeInBits() != NarrowTy.getSizeInBits()) {
671       LLVM_DEBUG(dbgs() << "Can't narrow sext to type " << NarrowTy << "\n");
672       return UnableToLegalize;
673     }
674 
675     // Shift the sign bit of the low register through the high register.
676     auto ShiftAmt =
677         MIRBuilder.buildConstant(LLT::scalar(64), NarrowTy.getSizeInBits() - 1);
678     auto Shift = MIRBuilder.buildAShr(NarrowTy, SrcReg, ShiftAmt);
679     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)});
680     MI.eraseFromParent();
681     return Legalized;
682   }
683   case TargetOpcode::G_ZEXT: {
684     if (TypeIdx != 0)
685       return UnableToLegalize;
686 
687     LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
688     uint64_t SizeOp1 = SrcTy.getSizeInBits();
689     if (SizeOp0 % SizeOp1 != 0)
690       return UnableToLegalize;
691 
692     // Generate a merge where the bottom bits are taken from the source, and
693     // zero everything else.
694     Register ZeroReg = MIRBuilder.buildConstant(SrcTy, 0).getReg(0);
695     unsigned NumParts = SizeOp0 / SizeOp1;
696     SmallVector<Register, 4> Srcs = {MI.getOperand(1).getReg()};
697     for (unsigned Part = 1; Part < NumParts; ++Part)
698       Srcs.push_back(ZeroReg);
699     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs);
700     MI.eraseFromParent();
701     return Legalized;
702   }
703   case TargetOpcode::G_TRUNC: {
704     if (TypeIdx != 1)
705       return UnableToLegalize;
706 
707     uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
708     if (NarrowTy.getSizeInBits() * 2 != SizeOp1) {
709       LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n");
710       return UnableToLegalize;
711     }
712 
713     auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg());
714     MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0));
715     MI.eraseFromParent();
716     return Legalized;
717   }
718 
719   case TargetOpcode::G_ADD: {
720     // FIXME: add support for when SizeOp0 isn't an exact multiple of
721     // NarrowSize.
722     if (SizeOp0 % NarrowSize != 0)
723       return UnableToLegalize;
724     // Expand in terms of carry-setting/consuming G_ADDE instructions.
725     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
726 
727     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
728     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
729     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
730 
731     Register CarryIn;
732     for (int i = 0; i < NumParts; ++i) {
733       Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
734       Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
735 
736       if (i == 0)
737         MIRBuilder.buildUAddo(DstReg, CarryOut, Src1Regs[i], Src2Regs[i]);
738       else {
739         MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
740                               Src2Regs[i], CarryIn);
741       }
742 
743       DstRegs.push_back(DstReg);
744       CarryIn = CarryOut;
745     }
746     Register DstReg = MI.getOperand(0).getReg();
747     if(MRI.getType(DstReg).isVector())
748       MIRBuilder.buildBuildVector(DstReg, DstRegs);
749     else
750       MIRBuilder.buildMerge(DstReg, DstRegs);
751     MI.eraseFromParent();
752     return Legalized;
753   }
754   case TargetOpcode::G_SUB: {
755     // FIXME: add support for when SizeOp0 isn't an exact multiple of
756     // NarrowSize.
757     if (SizeOp0 % NarrowSize != 0)
758       return UnableToLegalize;
759 
760     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
761 
762     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
763     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
764     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
765 
766     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
767     Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
768     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
769                           {Src1Regs[0], Src2Regs[0]});
770     DstRegs.push_back(DstReg);
771     Register BorrowIn = BorrowOut;
772     for (int i = 1; i < NumParts; ++i) {
773       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
774       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
775 
776       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
777                             {Src1Regs[i], Src2Regs[i], BorrowIn});
778 
779       DstRegs.push_back(DstReg);
780       BorrowIn = BorrowOut;
781     }
782     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
783     MI.eraseFromParent();
784     return Legalized;
785   }
786   case TargetOpcode::G_MUL:
787   case TargetOpcode::G_UMULH:
788     return narrowScalarMul(MI, NarrowTy);
789   case TargetOpcode::G_EXTRACT:
790     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
791   case TargetOpcode::G_INSERT:
792     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
793   case TargetOpcode::G_LOAD: {
794     const auto &MMO = **MI.memoperands_begin();
795     Register DstReg = MI.getOperand(0).getReg();
796     LLT DstTy = MRI.getType(DstReg);
797     if (DstTy.isVector())
798       return UnableToLegalize;
799 
800     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
801       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
802       auto &MMO = **MI.memoperands_begin();
803       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
804       MIRBuilder.buildAnyExt(DstReg, TmpReg);
805       MI.eraseFromParent();
806       return Legalized;
807     }
808 
809     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
810   }
811   case TargetOpcode::G_ZEXTLOAD:
812   case TargetOpcode::G_SEXTLOAD: {
813     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
814     Register DstReg = MI.getOperand(0).getReg();
815     Register PtrReg = MI.getOperand(1).getReg();
816 
817     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
818     auto &MMO = **MI.memoperands_begin();
819     if (MMO.getSizeInBits() == NarrowSize) {
820       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
821     } else {
822       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
823         : TargetOpcode::G_SEXTLOAD;
824       MIRBuilder.buildInstr(ExtLoad)
825         .addDef(TmpReg)
826         .addUse(PtrReg)
827         .addMemOperand(&MMO);
828     }
829 
830     if (ZExt)
831       MIRBuilder.buildZExt(DstReg, TmpReg);
832     else
833       MIRBuilder.buildSExt(DstReg, TmpReg);
834 
835     MI.eraseFromParent();
836     return Legalized;
837   }
838   case TargetOpcode::G_STORE: {
839     const auto &MMO = **MI.memoperands_begin();
840 
841     Register SrcReg = MI.getOperand(0).getReg();
842     LLT SrcTy = MRI.getType(SrcReg);
843     if (SrcTy.isVector())
844       return UnableToLegalize;
845 
846     int NumParts = SizeOp0 / NarrowSize;
847     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
848     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
849     if (SrcTy.isVector() && LeftoverBits != 0)
850       return UnableToLegalize;
851 
852     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
853       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
854       auto &MMO = **MI.memoperands_begin();
855       MIRBuilder.buildTrunc(TmpReg, SrcReg);
856       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
857       MI.eraseFromParent();
858       return Legalized;
859     }
860 
861     return reduceLoadStoreWidth(MI, 0, NarrowTy);
862   }
863   case TargetOpcode::G_SELECT:
864     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
865   case TargetOpcode::G_AND:
866   case TargetOpcode::G_OR:
867   case TargetOpcode::G_XOR: {
868     // Legalize bitwise operation:
869     // A = BinOp<Ty> B, C
870     // into:
871     // B1, ..., BN = G_UNMERGE_VALUES B
872     // C1, ..., CN = G_UNMERGE_VALUES C
873     // A1 = BinOp<Ty/N> B1, C2
874     // ...
875     // AN = BinOp<Ty/N> BN, CN
876     // A = G_MERGE_VALUES A1, ..., AN
877     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
878   }
879   case TargetOpcode::G_SHL:
880   case TargetOpcode::G_LSHR:
881   case TargetOpcode::G_ASHR:
882     return narrowScalarShift(MI, TypeIdx, NarrowTy);
883   case TargetOpcode::G_CTLZ:
884   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
885   case TargetOpcode::G_CTTZ:
886   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
887   case TargetOpcode::G_CTPOP:
888     if (TypeIdx != 0)
889       return UnableToLegalize; // TODO
890 
891     Observer.changingInstr(MI);
892     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
893     Observer.changedInstr(MI);
894     return Legalized;
895   case TargetOpcode::G_INTTOPTR:
896     if (TypeIdx != 1)
897       return UnableToLegalize;
898 
899     Observer.changingInstr(MI);
900     narrowScalarSrc(MI, NarrowTy, 1);
901     Observer.changedInstr(MI);
902     return Legalized;
903   case TargetOpcode::G_PTRTOINT:
904     if (TypeIdx != 0)
905       return UnableToLegalize;
906 
907     Observer.changingInstr(MI);
908     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
909     Observer.changedInstr(MI);
910     return Legalized;
911   case TargetOpcode::G_PHI: {
912     unsigned NumParts = SizeOp0 / NarrowSize;
913     SmallVector<Register, 2> DstRegs;
914     SmallVector<SmallVector<Register, 2>, 2> SrcRegs;
915     DstRegs.resize(NumParts);
916     SrcRegs.resize(MI.getNumOperands() / 2);
917     Observer.changingInstr(MI);
918     for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
919       MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
920       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
921       extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
922                    SrcRegs[i / 2]);
923     }
924     MachineBasicBlock &MBB = *MI.getParent();
925     MIRBuilder.setInsertPt(MBB, MI);
926     for (unsigned i = 0; i < NumParts; ++i) {
927       DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
928       MachineInstrBuilder MIB =
929           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
930       for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
931         MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
932     }
933     MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
934     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
935     Observer.changedInstr(MI);
936     MI.eraseFromParent();
937     return Legalized;
938   }
939   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
940   case TargetOpcode::G_INSERT_VECTOR_ELT: {
941     if (TypeIdx != 2)
942       return UnableToLegalize;
943 
944     int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
945     Observer.changingInstr(MI);
946     narrowScalarSrc(MI, NarrowTy, OpIdx);
947     Observer.changedInstr(MI);
948     return Legalized;
949   }
950   case TargetOpcode::G_ICMP: {
951     uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
952     if (NarrowSize * 2 != SrcSize)
953       return UnableToLegalize;
954 
955     Observer.changingInstr(MI);
956     Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
957     Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
958     MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg());
959 
960     Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
961     Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
962     MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg());
963 
964     CmpInst::Predicate Pred =
965         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
966     LLT ResTy = MRI.getType(MI.getOperand(0).getReg());
967 
968     if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) {
969       MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
970       MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
971       MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
972       MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
973       MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero);
974     } else {
975       MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
976       MachineInstrBuilder CmpHEQ =
977           MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
978       MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
979           ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
980       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH);
981     }
982     Observer.changedInstr(MI);
983     MI.eraseFromParent();
984     return Legalized;
985   }
986   case TargetOpcode::G_SEXT_INREG: {
987     if (TypeIdx != 0)
988       return UnableToLegalize;
989 
990     if (!MI.getOperand(2).isImm())
991       return UnableToLegalize;
992     int64_t SizeInBits = MI.getOperand(2).getImm();
993 
994     // So long as the new type has more bits than the bits we're extending we
995     // don't need to break it apart.
996     if (NarrowTy.getScalarSizeInBits() >= SizeInBits) {
997       Observer.changingInstr(MI);
998       // We don't lose any non-extension bits by truncating the src and
999       // sign-extending the dst.
1000       MachineOperand &MO1 = MI.getOperand(1);
1001       auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1.getReg());
1002       MO1.setReg(TruncMIB->getOperand(0).getReg());
1003 
1004       MachineOperand &MO2 = MI.getOperand(0);
1005       Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
1006       MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1007       MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt});
1008       MO2.setReg(DstExt);
1009       Observer.changedInstr(MI);
1010       return Legalized;
1011     }
1012 
1013     // Break it apart. Components below the extension point are unmodified. The
1014     // component containing the extension point becomes a narrower SEXT_INREG.
1015     // Components above it are ashr'd from the component containing the
1016     // extension point.
1017     if (SizeOp0 % NarrowSize != 0)
1018       return UnableToLegalize;
1019     int NumParts = SizeOp0 / NarrowSize;
1020 
1021     // List the registers where the destination will be scattered.
1022     SmallVector<Register, 2> DstRegs;
1023     // List the registers where the source will be split.
1024     SmallVector<Register, 2> SrcRegs;
1025 
1026     // Create all the temporary registers.
1027     for (int i = 0; i < NumParts; ++i) {
1028       Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy);
1029 
1030       SrcRegs.push_back(SrcReg);
1031     }
1032 
1033     // Explode the big arguments into smaller chunks.
1034     MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg());
1035 
1036     Register AshrCstReg =
1037         MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
1038             ->getOperand(0)
1039             .getReg();
1040     Register FullExtensionReg = 0;
1041     Register PartialExtensionReg = 0;
1042 
1043     // Do the operation on each small part.
1044     for (int i = 0; i < NumParts; ++i) {
1045       if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits)
1046         DstRegs.push_back(SrcRegs[i]);
1047       else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) {
1048         assert(PartialExtensionReg &&
1049                "Expected to visit partial extension before full");
1050         if (FullExtensionReg) {
1051           DstRegs.push_back(FullExtensionReg);
1052           continue;
1053         }
1054         DstRegs.push_back(MIRBuilder
1055                               .buildInstr(TargetOpcode::G_ASHR, {NarrowTy},
1056                                           {PartialExtensionReg, AshrCstReg})
1057                               ->getOperand(0)
1058                               .getReg());
1059         FullExtensionReg = DstRegs.back();
1060       } else {
1061         DstRegs.push_back(
1062             MIRBuilder
1063                 .buildInstr(
1064                     TargetOpcode::G_SEXT_INREG, {NarrowTy},
1065                     {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
1066                 ->getOperand(0)
1067                 .getReg());
1068         PartialExtensionReg = DstRegs.back();
1069       }
1070     }
1071 
1072     // Gather the destination registers into the final destination.
1073     Register DstReg = MI.getOperand(0).getReg();
1074     MIRBuilder.buildMerge(DstReg, DstRegs);
1075     MI.eraseFromParent();
1076     return Legalized;
1077   }
1078   }
1079 }
1080 
1081 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
1082                                      unsigned OpIdx, unsigned ExtOpcode) {
1083   MachineOperand &MO = MI.getOperand(OpIdx);
1084   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
1085   MO.setReg(ExtB->getOperand(0).getReg());
1086 }
1087 
1088 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
1089                                       unsigned OpIdx) {
1090   MachineOperand &MO = MI.getOperand(OpIdx);
1091   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
1092                                     {MO.getReg()});
1093   MO.setReg(ExtB->getOperand(0).getReg());
1094 }
1095 
1096 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
1097                                      unsigned OpIdx, unsigned TruncOpcode) {
1098   MachineOperand &MO = MI.getOperand(OpIdx);
1099   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1100   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1101   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
1102   MO.setReg(DstExt);
1103 }
1104 
1105 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
1106                                       unsigned OpIdx, unsigned ExtOpcode) {
1107   MachineOperand &MO = MI.getOperand(OpIdx);
1108   Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
1109   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1110   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
1111   MO.setReg(DstTrunc);
1112 }
1113 
1114 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
1115                                             unsigned OpIdx) {
1116   MachineOperand &MO = MI.getOperand(OpIdx);
1117   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1118   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1119   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
1120   MO.setReg(DstExt);
1121 }
1122 
1123 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
1124                                             unsigned OpIdx) {
1125   MachineOperand &MO = MI.getOperand(OpIdx);
1126 
1127   LLT OldTy = MRI.getType(MO.getReg());
1128   unsigned OldElts = OldTy.getNumElements();
1129   unsigned NewElts = MoreTy.getNumElements();
1130 
1131   unsigned NumParts = NewElts / OldElts;
1132 
1133   // Use concat_vectors if the result is a multiple of the number of elements.
1134   if (NumParts * OldElts == NewElts) {
1135     SmallVector<Register, 8> Parts;
1136     Parts.push_back(MO.getReg());
1137 
1138     Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
1139     for (unsigned I = 1; I != NumParts; ++I)
1140       Parts.push_back(ImpDef);
1141 
1142     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
1143     MO.setReg(Concat.getReg(0));
1144     return;
1145   }
1146 
1147   Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
1148   Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
1149   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
1150   MO.setReg(MoreReg);
1151 }
1152 
1153 LegalizerHelper::LegalizeResult
1154 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
1155                                         LLT WideTy) {
1156   if (TypeIdx != 1)
1157     return UnableToLegalize;
1158 
1159   Register DstReg = MI.getOperand(0).getReg();
1160   LLT DstTy = MRI.getType(DstReg);
1161   if (DstTy.isVector())
1162     return UnableToLegalize;
1163 
1164   Register Src1 = MI.getOperand(1).getReg();
1165   LLT SrcTy = MRI.getType(Src1);
1166   const int DstSize = DstTy.getSizeInBits();
1167   const int SrcSize = SrcTy.getSizeInBits();
1168   const int WideSize = WideTy.getSizeInBits();
1169   const int NumMerge = (DstSize + WideSize - 1) / WideSize;
1170 
1171   unsigned NumOps = MI.getNumOperands();
1172   unsigned NumSrc = MI.getNumOperands() - 1;
1173   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
1174 
1175   if (WideSize >= DstSize) {
1176     // Directly pack the bits in the target type.
1177     Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1178 
1179     for (unsigned I = 2; I != NumOps; ++I) {
1180       const unsigned Offset = (I - 1) * PartSize;
1181 
1182       Register SrcReg = MI.getOperand(I).getReg();
1183       assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
1184 
1185       auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
1186 
1187       Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
1188         MRI.createGenericVirtualRegister(WideTy);
1189 
1190       auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
1191       auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
1192       MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1193       ResultReg = NextResult;
1194     }
1195 
1196     if (WideSize > DstSize)
1197       MIRBuilder.buildTrunc(DstReg, ResultReg);
1198     else if (DstTy.isPointer())
1199       MIRBuilder.buildIntToPtr(DstReg, ResultReg);
1200 
1201     MI.eraseFromParent();
1202     return Legalized;
1203   }
1204 
1205   // Unmerge the original values to the GCD type, and recombine to the next
1206   // multiple greater than the original type.
1207   //
1208   // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6
1209   // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0
1210   // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1
1211   // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2
1212   // %10:_(s6) = G_MERGE_VALUES %4, %5, %6
1213   // %11:_(s6) = G_MERGE_VALUES %7, %8, %9
1214   // %12:_(s12) = G_MERGE_VALUES %10, %11
1215   //
1216   // Padding with undef if necessary:
1217   //
1218   // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6
1219   // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0
1220   // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1
1221   // %7:_(s2) = G_IMPLICIT_DEF
1222   // %8:_(s6) = G_MERGE_VALUES %3, %4, %5
1223   // %9:_(s6) = G_MERGE_VALUES %6, %7, %7
1224   // %10:_(s12) = G_MERGE_VALUES %8, %9
1225 
1226   const int GCD = greatestCommonDivisor(SrcSize, WideSize);
1227   LLT GCDTy = LLT::scalar(GCD);
1228 
1229   SmallVector<Register, 8> Parts;
1230   SmallVector<Register, 8> NewMergeRegs;
1231   SmallVector<Register, 8> Unmerges;
1232   LLT WideDstTy = LLT::scalar(NumMerge * WideSize);
1233 
1234   // Decompose the original operands if they don't evenly divide.
1235   for (int I = 1, E = MI.getNumOperands(); I != E; ++I) {
1236     Register SrcReg = MI.getOperand(I).getReg();
1237     if (GCD == SrcSize) {
1238       Unmerges.push_back(SrcReg);
1239     } else {
1240       auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
1241       for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J)
1242         Unmerges.push_back(Unmerge.getReg(J));
1243     }
1244   }
1245 
1246   // Pad with undef to the next size that is a multiple of the requested size.
1247   if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) {
1248     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1249     for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I)
1250       Unmerges.push_back(UndefReg);
1251   }
1252 
1253   const int PartsPerGCD = WideSize / GCD;
1254 
1255   // Build merges of each piece.
1256   ArrayRef<Register> Slicer(Unmerges);
1257   for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) {
1258     auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
1259     NewMergeRegs.push_back(Merge.getReg(0));
1260   }
1261 
1262   // A truncate may be necessary if the requested type doesn't evenly divide the
1263   // original result type.
1264   if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
1265     MIRBuilder.buildMerge(DstReg, NewMergeRegs);
1266   } else {
1267     auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
1268     MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
1269   }
1270 
1271   MI.eraseFromParent();
1272   return Legalized;
1273 }
1274 
1275 LegalizerHelper::LegalizeResult
1276 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
1277                                           LLT WideTy) {
1278   if (TypeIdx != 0)
1279     return UnableToLegalize;
1280 
1281   unsigned NumDst = MI.getNumOperands() - 1;
1282   Register SrcReg = MI.getOperand(NumDst).getReg();
1283   LLT SrcTy = MRI.getType(SrcReg);
1284   if (!SrcTy.isScalar())
1285     return UnableToLegalize;
1286 
1287   Register Dst0Reg = MI.getOperand(0).getReg();
1288   LLT DstTy = MRI.getType(Dst0Reg);
1289   if (!DstTy.isScalar())
1290     return UnableToLegalize;
1291 
1292   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
1293   LLT NewSrcTy = LLT::scalar(NewSrcSize);
1294   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
1295 
1296   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
1297 
1298   for (unsigned I = 1; I != NumDst; ++I) {
1299     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
1300     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
1301     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
1302   }
1303 
1304   Observer.changingInstr(MI);
1305 
1306   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
1307   for (unsigned I = 0; I != NumDst; ++I)
1308     widenScalarDst(MI, WideTy, I);
1309 
1310   Observer.changedInstr(MI);
1311 
1312   return Legalized;
1313 }
1314 
1315 LegalizerHelper::LegalizeResult
1316 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
1317                                     LLT WideTy) {
1318   Register DstReg = MI.getOperand(0).getReg();
1319   Register SrcReg = MI.getOperand(1).getReg();
1320   LLT SrcTy = MRI.getType(SrcReg);
1321 
1322   LLT DstTy = MRI.getType(DstReg);
1323   unsigned Offset = MI.getOperand(2).getImm();
1324 
1325   if (TypeIdx == 0) {
1326     if (SrcTy.isVector() || DstTy.isVector())
1327       return UnableToLegalize;
1328 
1329     SrcOp Src(SrcReg);
1330     if (SrcTy.isPointer()) {
1331       // Extracts from pointers can be handled only if they are really just
1332       // simple integers.
1333       const DataLayout &DL = MIRBuilder.getDataLayout();
1334       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
1335         return UnableToLegalize;
1336 
1337       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
1338       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
1339       SrcTy = SrcAsIntTy;
1340     }
1341 
1342     if (DstTy.isPointer())
1343       return UnableToLegalize;
1344 
1345     if (Offset == 0) {
1346       // Avoid a shift in the degenerate case.
1347       MIRBuilder.buildTrunc(DstReg,
1348                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
1349       MI.eraseFromParent();
1350       return Legalized;
1351     }
1352 
1353     // Do a shift in the source type.
1354     LLT ShiftTy = SrcTy;
1355     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1356       Src = MIRBuilder.buildAnyExt(WideTy, Src);
1357       ShiftTy = WideTy;
1358     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
1359       return UnableToLegalize;
1360 
1361     auto LShr = MIRBuilder.buildLShr(
1362       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
1363     MIRBuilder.buildTrunc(DstReg, LShr);
1364     MI.eraseFromParent();
1365     return Legalized;
1366   }
1367 
1368   if (SrcTy.isScalar()) {
1369     Observer.changingInstr(MI);
1370     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1371     Observer.changedInstr(MI);
1372     return Legalized;
1373   }
1374 
1375   if (!SrcTy.isVector())
1376     return UnableToLegalize;
1377 
1378   if (DstTy != SrcTy.getElementType())
1379     return UnableToLegalize;
1380 
1381   if (Offset % SrcTy.getScalarSizeInBits() != 0)
1382     return UnableToLegalize;
1383 
1384   Observer.changingInstr(MI);
1385   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1386 
1387   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
1388                           Offset);
1389   widenScalarDst(MI, WideTy.getScalarType(), 0);
1390   Observer.changedInstr(MI);
1391   return Legalized;
1392 }
1393 
1394 LegalizerHelper::LegalizeResult
1395 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
1396                                    LLT WideTy) {
1397   if (TypeIdx != 0)
1398     return UnableToLegalize;
1399   Observer.changingInstr(MI);
1400   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1401   widenScalarDst(MI, WideTy);
1402   Observer.changedInstr(MI);
1403   return Legalized;
1404 }
1405 
1406 LegalizerHelper::LegalizeResult
1407 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
1408   MIRBuilder.setInstr(MI);
1409 
1410   switch (MI.getOpcode()) {
1411   default:
1412     return UnableToLegalize;
1413   case TargetOpcode::G_EXTRACT:
1414     return widenScalarExtract(MI, TypeIdx, WideTy);
1415   case TargetOpcode::G_INSERT:
1416     return widenScalarInsert(MI, TypeIdx, WideTy);
1417   case TargetOpcode::G_MERGE_VALUES:
1418     return widenScalarMergeValues(MI, TypeIdx, WideTy);
1419   case TargetOpcode::G_UNMERGE_VALUES:
1420     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
1421   case TargetOpcode::G_UADDO:
1422   case TargetOpcode::G_USUBO: {
1423     if (TypeIdx == 1)
1424       return UnableToLegalize; // TODO
1425     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1426                                          {MI.getOperand(2).getReg()});
1427     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1428                                          {MI.getOperand(3).getReg()});
1429     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1430                           ? TargetOpcode::G_ADD
1431                           : TargetOpcode::G_SUB;
1432     // Do the arithmetic in the larger type.
1433     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1434     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1435     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
1436     auto AndOp = MIRBuilder.buildInstr(
1437         TargetOpcode::G_AND, {WideTy},
1438         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
1439     // There is no overflow if the AndOp is the same as NewOp.
1440     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
1441                          AndOp);
1442     // Now trunc the NewOp to the original result.
1443     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
1444     MI.eraseFromParent();
1445     return Legalized;
1446   }
1447   case TargetOpcode::G_CTTZ:
1448   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1449   case TargetOpcode::G_CTLZ:
1450   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1451   case TargetOpcode::G_CTPOP: {
1452     if (TypeIdx == 0) {
1453       Observer.changingInstr(MI);
1454       widenScalarDst(MI, WideTy, 0);
1455       Observer.changedInstr(MI);
1456       return Legalized;
1457     }
1458 
1459     Register SrcReg = MI.getOperand(1).getReg();
1460 
1461     // First ZEXT the input.
1462     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1463     LLT CurTy = MRI.getType(SrcReg);
1464     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1465       // The count is the same in the larger type except if the original
1466       // value was zero.  This can be handled by setting the bit just off
1467       // the top of the original type.
1468       auto TopBit =
1469           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1470       MIBSrc = MIRBuilder.buildOr(
1471         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1472     }
1473 
1474     // Perform the operation at the larger size.
1475     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1476     // This is already the correct result for CTPOP and CTTZs
1477     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1478         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1479       // The correct result is NewOp - (Difference in widety and current ty).
1480       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1481       MIBNewOp = MIRBuilder.buildInstr(
1482           TargetOpcode::G_SUB, {WideTy},
1483           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1484     }
1485 
1486     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1487     MI.eraseFromParent();
1488     return Legalized;
1489   }
1490   case TargetOpcode::G_BSWAP: {
1491     Observer.changingInstr(MI);
1492     Register DstReg = MI.getOperand(0).getReg();
1493 
1494     Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1495     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1496     Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1497     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1498 
1499     MI.getOperand(0).setReg(DstExt);
1500 
1501     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1502 
1503     LLT Ty = MRI.getType(DstReg);
1504     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1505     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1506     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1507       .addDef(ShrReg)
1508       .addUse(DstExt)
1509       .addUse(ShiftAmtReg);
1510 
1511     MIRBuilder.buildTrunc(DstReg, ShrReg);
1512     Observer.changedInstr(MI);
1513     return Legalized;
1514   }
1515   case TargetOpcode::G_BITREVERSE: {
1516     Observer.changingInstr(MI);
1517 
1518     Register DstReg = MI.getOperand(0).getReg();
1519     LLT Ty = MRI.getType(DstReg);
1520     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1521 
1522     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1523     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1524     MI.getOperand(0).setReg(DstExt);
1525     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1526 
1527     auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
1528     auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt);
1529     MIRBuilder.buildTrunc(DstReg, Shift);
1530     Observer.changedInstr(MI);
1531     return Legalized;
1532   }
1533   case TargetOpcode::G_ADD:
1534   case TargetOpcode::G_AND:
1535   case TargetOpcode::G_MUL:
1536   case TargetOpcode::G_OR:
1537   case TargetOpcode::G_XOR:
1538   case TargetOpcode::G_SUB:
1539     // Perform operation at larger width (any extension is fines here, high bits
1540     // don't affect the result) and then truncate the result back to the
1541     // original type.
1542     Observer.changingInstr(MI);
1543     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1544     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1545     widenScalarDst(MI, WideTy);
1546     Observer.changedInstr(MI);
1547     return Legalized;
1548 
1549   case TargetOpcode::G_SHL:
1550     Observer.changingInstr(MI);
1551 
1552     if (TypeIdx == 0) {
1553       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1554       widenScalarDst(MI, WideTy);
1555     } else {
1556       assert(TypeIdx == 1);
1557       // The "number of bits to shift" operand must preserve its value as an
1558       // unsigned integer:
1559       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1560     }
1561 
1562     Observer.changedInstr(MI);
1563     return Legalized;
1564 
1565   case TargetOpcode::G_SDIV:
1566   case TargetOpcode::G_SREM:
1567   case TargetOpcode::G_SMIN:
1568   case TargetOpcode::G_SMAX:
1569     Observer.changingInstr(MI);
1570     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1571     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1572     widenScalarDst(MI, WideTy);
1573     Observer.changedInstr(MI);
1574     return Legalized;
1575 
1576   case TargetOpcode::G_ASHR:
1577   case TargetOpcode::G_LSHR:
1578     Observer.changingInstr(MI);
1579 
1580     if (TypeIdx == 0) {
1581       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1582         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1583 
1584       widenScalarSrc(MI, WideTy, 1, CvtOp);
1585       widenScalarDst(MI, WideTy);
1586     } else {
1587       assert(TypeIdx == 1);
1588       // The "number of bits to shift" operand must preserve its value as an
1589       // unsigned integer:
1590       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1591     }
1592 
1593     Observer.changedInstr(MI);
1594     return Legalized;
1595   case TargetOpcode::G_UDIV:
1596   case TargetOpcode::G_UREM:
1597   case TargetOpcode::G_UMIN:
1598   case TargetOpcode::G_UMAX:
1599     Observer.changingInstr(MI);
1600     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1601     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1602     widenScalarDst(MI, WideTy);
1603     Observer.changedInstr(MI);
1604     return Legalized;
1605 
1606   case TargetOpcode::G_SELECT:
1607     Observer.changingInstr(MI);
1608     if (TypeIdx == 0) {
1609       // Perform operation at larger width (any extension is fine here, high
1610       // bits don't affect the result) and then truncate the result back to the
1611       // original type.
1612       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1613       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1614       widenScalarDst(MI, WideTy);
1615     } else {
1616       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1617       // Explicit extension is required here since high bits affect the result.
1618       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1619     }
1620     Observer.changedInstr(MI);
1621     return Legalized;
1622 
1623   case TargetOpcode::G_FPTOSI:
1624   case TargetOpcode::G_FPTOUI:
1625     if (TypeIdx != 0)
1626       return UnableToLegalize;
1627     Observer.changingInstr(MI);
1628     widenScalarDst(MI, WideTy);
1629     Observer.changedInstr(MI);
1630     return Legalized;
1631 
1632   case TargetOpcode::G_SITOFP:
1633     if (TypeIdx != 1)
1634       return UnableToLegalize;
1635     Observer.changingInstr(MI);
1636     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1637     Observer.changedInstr(MI);
1638     return Legalized;
1639 
1640   case TargetOpcode::G_UITOFP:
1641     if (TypeIdx != 1)
1642       return UnableToLegalize;
1643     Observer.changingInstr(MI);
1644     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1645     Observer.changedInstr(MI);
1646     return Legalized;
1647 
1648   case TargetOpcode::G_LOAD:
1649   case TargetOpcode::G_SEXTLOAD:
1650   case TargetOpcode::G_ZEXTLOAD:
1651     Observer.changingInstr(MI);
1652     widenScalarDst(MI, WideTy);
1653     Observer.changedInstr(MI);
1654     return Legalized;
1655 
1656   case TargetOpcode::G_STORE: {
1657     if (TypeIdx != 0)
1658       return UnableToLegalize;
1659 
1660     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1661     if (!isPowerOf2_32(Ty.getSizeInBits()))
1662       return UnableToLegalize;
1663 
1664     Observer.changingInstr(MI);
1665 
1666     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1667       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1668     widenScalarSrc(MI, WideTy, 0, ExtType);
1669 
1670     Observer.changedInstr(MI);
1671     return Legalized;
1672   }
1673   case TargetOpcode::G_CONSTANT: {
1674     MachineOperand &SrcMO = MI.getOperand(1);
1675     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1676     const APInt &Val = SrcMO.getCImm()->getValue().sext(WideTy.getSizeInBits());
1677     Observer.changingInstr(MI);
1678     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1679 
1680     widenScalarDst(MI, WideTy);
1681     Observer.changedInstr(MI);
1682     return Legalized;
1683   }
1684   case TargetOpcode::G_FCONSTANT: {
1685     MachineOperand &SrcMO = MI.getOperand(1);
1686     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1687     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1688     bool LosesInfo;
1689     switch (WideTy.getSizeInBits()) {
1690     case 32:
1691       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1692                   &LosesInfo);
1693       break;
1694     case 64:
1695       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1696                   &LosesInfo);
1697       break;
1698     default:
1699       return UnableToLegalize;
1700     }
1701 
1702     assert(!LosesInfo && "extend should always be lossless");
1703 
1704     Observer.changingInstr(MI);
1705     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1706 
1707     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1708     Observer.changedInstr(MI);
1709     return Legalized;
1710   }
1711   case TargetOpcode::G_IMPLICIT_DEF: {
1712     Observer.changingInstr(MI);
1713     widenScalarDst(MI, WideTy);
1714     Observer.changedInstr(MI);
1715     return Legalized;
1716   }
1717   case TargetOpcode::G_BRCOND:
1718     Observer.changingInstr(MI);
1719     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1720     Observer.changedInstr(MI);
1721     return Legalized;
1722 
1723   case TargetOpcode::G_FCMP:
1724     Observer.changingInstr(MI);
1725     if (TypeIdx == 0)
1726       widenScalarDst(MI, WideTy);
1727     else {
1728       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1729       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1730     }
1731     Observer.changedInstr(MI);
1732     return Legalized;
1733 
1734   case TargetOpcode::G_ICMP:
1735     Observer.changingInstr(MI);
1736     if (TypeIdx == 0)
1737       widenScalarDst(MI, WideTy);
1738     else {
1739       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1740                                MI.getOperand(1).getPredicate()))
1741                                ? TargetOpcode::G_SEXT
1742                                : TargetOpcode::G_ZEXT;
1743       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1744       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1745     }
1746     Observer.changedInstr(MI);
1747     return Legalized;
1748 
1749   case TargetOpcode::G_GEP:
1750     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
1751     Observer.changingInstr(MI);
1752     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1753     Observer.changedInstr(MI);
1754     return Legalized;
1755 
1756   case TargetOpcode::G_PHI: {
1757     assert(TypeIdx == 0 && "Expecting only Idx 0");
1758 
1759     Observer.changingInstr(MI);
1760     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1761       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1762       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1763       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1764     }
1765 
1766     MachineBasicBlock &MBB = *MI.getParent();
1767     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1768     widenScalarDst(MI, WideTy);
1769     Observer.changedInstr(MI);
1770     return Legalized;
1771   }
1772   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1773     if (TypeIdx == 0) {
1774       Register VecReg = MI.getOperand(1).getReg();
1775       LLT VecTy = MRI.getType(VecReg);
1776       Observer.changingInstr(MI);
1777 
1778       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1779                                      WideTy.getSizeInBits()),
1780                      1, TargetOpcode::G_SEXT);
1781 
1782       widenScalarDst(MI, WideTy, 0);
1783       Observer.changedInstr(MI);
1784       return Legalized;
1785     }
1786 
1787     if (TypeIdx != 2)
1788       return UnableToLegalize;
1789     Observer.changingInstr(MI);
1790     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1791     Observer.changedInstr(MI);
1792     return Legalized;
1793   }
1794   case TargetOpcode::G_FADD:
1795   case TargetOpcode::G_FMUL:
1796   case TargetOpcode::G_FSUB:
1797   case TargetOpcode::G_FMA:
1798   case TargetOpcode::G_FMAD:
1799   case TargetOpcode::G_FNEG:
1800   case TargetOpcode::G_FABS:
1801   case TargetOpcode::G_FCANONICALIZE:
1802   case TargetOpcode::G_FMINNUM:
1803   case TargetOpcode::G_FMAXNUM:
1804   case TargetOpcode::G_FMINNUM_IEEE:
1805   case TargetOpcode::G_FMAXNUM_IEEE:
1806   case TargetOpcode::G_FMINIMUM:
1807   case TargetOpcode::G_FMAXIMUM:
1808   case TargetOpcode::G_FDIV:
1809   case TargetOpcode::G_FREM:
1810   case TargetOpcode::G_FCEIL:
1811   case TargetOpcode::G_FFLOOR:
1812   case TargetOpcode::G_FCOS:
1813   case TargetOpcode::G_FSIN:
1814   case TargetOpcode::G_FLOG10:
1815   case TargetOpcode::G_FLOG:
1816   case TargetOpcode::G_FLOG2:
1817   case TargetOpcode::G_FRINT:
1818   case TargetOpcode::G_FNEARBYINT:
1819   case TargetOpcode::G_FSQRT:
1820   case TargetOpcode::G_FEXP:
1821   case TargetOpcode::G_FEXP2:
1822   case TargetOpcode::G_FPOW:
1823   case TargetOpcode::G_INTRINSIC_TRUNC:
1824   case TargetOpcode::G_INTRINSIC_ROUND:
1825     assert(TypeIdx == 0);
1826     Observer.changingInstr(MI);
1827 
1828     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1829       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1830 
1831     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1832     Observer.changedInstr(MI);
1833     return Legalized;
1834   case TargetOpcode::G_INTTOPTR:
1835     if (TypeIdx != 1)
1836       return UnableToLegalize;
1837 
1838     Observer.changingInstr(MI);
1839     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1840     Observer.changedInstr(MI);
1841     return Legalized;
1842   case TargetOpcode::G_PTRTOINT:
1843     if (TypeIdx != 0)
1844       return UnableToLegalize;
1845 
1846     Observer.changingInstr(MI);
1847     widenScalarDst(MI, WideTy, 0);
1848     Observer.changedInstr(MI);
1849     return Legalized;
1850   case TargetOpcode::G_BUILD_VECTOR: {
1851     Observer.changingInstr(MI);
1852 
1853     const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
1854     for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
1855       widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT);
1856 
1857     // Avoid changing the result vector type if the source element type was
1858     // requested.
1859     if (TypeIdx == 1) {
1860       auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
1861       MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
1862     } else {
1863       widenScalarDst(MI, WideTy, 0);
1864     }
1865 
1866     Observer.changedInstr(MI);
1867     return Legalized;
1868   }
1869   case TargetOpcode::G_SEXT_INREG:
1870     if (TypeIdx != 0)
1871       return UnableToLegalize;
1872 
1873     Observer.changingInstr(MI);
1874     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1875     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC);
1876     Observer.changedInstr(MI);
1877     return Legalized;
1878   }
1879 }
1880 
1881 LegalizerHelper::LegalizeResult
1882 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1883   using namespace TargetOpcode;
1884   MIRBuilder.setInstr(MI);
1885 
1886   switch(MI.getOpcode()) {
1887   default:
1888     return UnableToLegalize;
1889   case TargetOpcode::G_SREM:
1890   case TargetOpcode::G_UREM: {
1891     Register QuotReg = MRI.createGenericVirtualRegister(Ty);
1892     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1893         .addDef(QuotReg)
1894         .addUse(MI.getOperand(1).getReg())
1895         .addUse(MI.getOperand(2).getReg());
1896 
1897     Register ProdReg = MRI.createGenericVirtualRegister(Ty);
1898     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1899     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1900                         ProdReg);
1901     MI.eraseFromParent();
1902     return Legalized;
1903   }
1904   case TargetOpcode::G_SMULO:
1905   case TargetOpcode::G_UMULO: {
1906     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
1907     // result.
1908     Register Res = MI.getOperand(0).getReg();
1909     Register Overflow = MI.getOperand(1).getReg();
1910     Register LHS = MI.getOperand(2).getReg();
1911     Register RHS = MI.getOperand(3).getReg();
1912 
1913     MIRBuilder.buildMul(Res, LHS, RHS);
1914 
1915     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
1916                           ? TargetOpcode::G_SMULH
1917                           : TargetOpcode::G_UMULH;
1918 
1919     Register HiPart = MRI.createGenericVirtualRegister(Ty);
1920     MIRBuilder.buildInstr(Opcode)
1921       .addDef(HiPart)
1922       .addUse(LHS)
1923       .addUse(RHS);
1924 
1925     Register Zero = MRI.createGenericVirtualRegister(Ty);
1926     MIRBuilder.buildConstant(Zero, 0);
1927 
1928     // For *signed* multiply, overflow is detected by checking:
1929     // (hi != (lo >> bitwidth-1))
1930     if (Opcode == TargetOpcode::G_SMULH) {
1931       Register Shifted = MRI.createGenericVirtualRegister(Ty);
1932       Register ShiftAmt = MRI.createGenericVirtualRegister(Ty);
1933       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
1934       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
1935         .addDef(Shifted)
1936         .addUse(Res)
1937         .addUse(ShiftAmt);
1938       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
1939     } else {
1940       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
1941     }
1942     MI.eraseFromParent();
1943     return Legalized;
1944   }
1945   case TargetOpcode::G_FNEG: {
1946     // TODO: Handle vector types once we are able to
1947     // represent them.
1948     if (Ty.isVector())
1949       return UnableToLegalize;
1950     Register Res = MI.getOperand(0).getReg();
1951     Type *ZeroTy;
1952     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1953     switch (Ty.getSizeInBits()) {
1954     case 16:
1955       ZeroTy = Type::getHalfTy(Ctx);
1956       break;
1957     case 32:
1958       ZeroTy = Type::getFloatTy(Ctx);
1959       break;
1960     case 64:
1961       ZeroTy = Type::getDoubleTy(Ctx);
1962       break;
1963     case 128:
1964       ZeroTy = Type::getFP128Ty(Ctx);
1965       break;
1966     default:
1967       llvm_unreachable("unexpected floating-point type");
1968     }
1969     ConstantFP &ZeroForNegation =
1970         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
1971     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
1972     Register SubByReg = MI.getOperand(1).getReg();
1973     Register ZeroReg = Zero->getOperand(0).getReg();
1974     MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
1975                           MI.getFlags());
1976     MI.eraseFromParent();
1977     return Legalized;
1978   }
1979   case TargetOpcode::G_FSUB: {
1980     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
1981     // First, check if G_FNEG is marked as Lower. If so, we may
1982     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
1983     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
1984       return UnableToLegalize;
1985     Register Res = MI.getOperand(0).getReg();
1986     Register LHS = MI.getOperand(1).getReg();
1987     Register RHS = MI.getOperand(2).getReg();
1988     Register Neg = MRI.createGenericVirtualRegister(Ty);
1989     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
1990     MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
1991     MI.eraseFromParent();
1992     return Legalized;
1993   }
1994   case TargetOpcode::G_FMAD:
1995     return lowerFMad(MI);
1996   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
1997     Register OldValRes = MI.getOperand(0).getReg();
1998     Register SuccessRes = MI.getOperand(1).getReg();
1999     Register Addr = MI.getOperand(2).getReg();
2000     Register CmpVal = MI.getOperand(3).getReg();
2001     Register NewVal = MI.getOperand(4).getReg();
2002     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
2003                                   **MI.memoperands_begin());
2004     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
2005     MI.eraseFromParent();
2006     return Legalized;
2007   }
2008   case TargetOpcode::G_LOAD:
2009   case TargetOpcode::G_SEXTLOAD:
2010   case TargetOpcode::G_ZEXTLOAD: {
2011     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
2012     Register DstReg = MI.getOperand(0).getReg();
2013     Register PtrReg = MI.getOperand(1).getReg();
2014     LLT DstTy = MRI.getType(DstReg);
2015     auto &MMO = **MI.memoperands_begin();
2016 
2017     if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
2018       if (MI.getOpcode() == TargetOpcode::G_LOAD) {
2019         // This load needs splitting into power of 2 sized loads.
2020         if (DstTy.isVector())
2021           return UnableToLegalize;
2022         if (isPowerOf2_32(DstTy.getSizeInBits()))
2023           return UnableToLegalize; // Don't know what we're being asked to do.
2024 
2025         // Our strategy here is to generate anyextending loads for the smaller
2026         // types up to next power-2 result type, and then combine the two larger
2027         // result values together, before truncating back down to the non-pow-2
2028         // type.
2029         // E.g. v1 = i24 load =>
2030         // v2 = i32 load (2 byte)
2031         // v3 = i32 load (1 byte)
2032         // v4 = i32 shl v3, 16
2033         // v5 = i32 or v4, v2
2034         // v1 = i24 trunc v5
2035         // By doing this we generate the correct truncate which should get
2036         // combined away as an artifact with a matching extend.
2037         uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits());
2038         uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize;
2039 
2040         MachineFunction &MF = MIRBuilder.getMF();
2041         MachineMemOperand *LargeMMO =
2042             MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2043         MachineMemOperand *SmallMMO = MF.getMachineMemOperand(
2044             &MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2045 
2046         LLT PtrTy = MRI.getType(PtrReg);
2047         unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits());
2048         LLT AnyExtTy = LLT::scalar(AnyExtSize);
2049         Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2050         Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2051         auto LargeLoad =
2052             MIRBuilder.buildLoad(LargeLdReg, PtrReg, *LargeMMO);
2053 
2054         auto OffsetCst =
2055             MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2056         Register GEPReg = MRI.createGenericVirtualRegister(PtrTy);
2057         auto SmallPtr = MIRBuilder.buildGEP(GEPReg, PtrReg, OffsetCst.getReg(0));
2058         auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
2059                                               *SmallMMO);
2060 
2061         auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
2062         auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt);
2063         auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
2064         MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)});
2065         MI.eraseFromParent();
2066         return Legalized;
2067       }
2068       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
2069       MI.eraseFromParent();
2070       return Legalized;
2071     }
2072 
2073     if (DstTy.isScalar()) {
2074       Register TmpReg =
2075           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
2076       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
2077       switch (MI.getOpcode()) {
2078       default:
2079         llvm_unreachable("Unexpected opcode");
2080       case TargetOpcode::G_LOAD:
2081         MIRBuilder.buildAnyExt(DstReg, TmpReg);
2082         break;
2083       case TargetOpcode::G_SEXTLOAD:
2084         MIRBuilder.buildSExt(DstReg, TmpReg);
2085         break;
2086       case TargetOpcode::G_ZEXTLOAD:
2087         MIRBuilder.buildZExt(DstReg, TmpReg);
2088         break;
2089       }
2090       MI.eraseFromParent();
2091       return Legalized;
2092     }
2093 
2094     return UnableToLegalize;
2095   }
2096   case TargetOpcode::G_STORE: {
2097     // Lower a non-power of 2 store into multiple pow-2 stores.
2098     // E.g. split an i24 store into an i16 store + i8 store.
2099     // We do this by first extending the stored value to the next largest power
2100     // of 2 type, and then using truncating stores to store the components.
2101     // By doing this, likewise with G_LOAD, generate an extend that can be
2102     // artifact-combined away instead of leaving behind extracts.
2103     Register SrcReg = MI.getOperand(0).getReg();
2104     Register PtrReg = MI.getOperand(1).getReg();
2105     LLT SrcTy = MRI.getType(SrcReg);
2106     MachineMemOperand &MMO = **MI.memoperands_begin();
2107     if (SrcTy.getSizeInBits() != MMO.getSizeInBits())
2108       return UnableToLegalize;
2109     if (SrcTy.isVector())
2110       return UnableToLegalize;
2111     if (isPowerOf2_32(SrcTy.getSizeInBits()))
2112       return UnableToLegalize; // Don't know what we're being asked to do.
2113 
2114     // Extend to the next pow-2.
2115     const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits()));
2116     auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg);
2117 
2118     // Obtain the smaller value by shifting away the larger value.
2119     uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits());
2120     uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize;
2121     auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize);
2122     auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt);
2123 
2124     // Generate the GEP and truncating stores.
2125     LLT PtrTy = MRI.getType(PtrReg);
2126     auto OffsetCst =
2127         MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2128     Register GEPReg = MRI.createGenericVirtualRegister(PtrTy);
2129     auto SmallPtr = MIRBuilder.buildGEP(GEPReg, PtrReg, OffsetCst.getReg(0));
2130 
2131     MachineFunction &MF = MIRBuilder.getMF();
2132     MachineMemOperand *LargeMMO =
2133         MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2134     MachineMemOperand *SmallMMO =
2135         MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2136     MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO);
2137     MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO);
2138     MI.eraseFromParent();
2139     return Legalized;
2140   }
2141   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
2142   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
2143   case TargetOpcode::G_CTLZ:
2144   case TargetOpcode::G_CTTZ:
2145   case TargetOpcode::G_CTPOP:
2146     return lowerBitCount(MI, TypeIdx, Ty);
2147   case G_UADDO: {
2148     Register Res = MI.getOperand(0).getReg();
2149     Register CarryOut = MI.getOperand(1).getReg();
2150     Register LHS = MI.getOperand(2).getReg();
2151     Register RHS = MI.getOperand(3).getReg();
2152 
2153     MIRBuilder.buildAdd(Res, LHS, RHS);
2154     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
2155 
2156     MI.eraseFromParent();
2157     return Legalized;
2158   }
2159   case G_UADDE: {
2160     Register Res = MI.getOperand(0).getReg();
2161     Register CarryOut = MI.getOperand(1).getReg();
2162     Register LHS = MI.getOperand(2).getReg();
2163     Register RHS = MI.getOperand(3).getReg();
2164     Register CarryIn = MI.getOperand(4).getReg();
2165 
2166     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2167     Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
2168 
2169     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
2170     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
2171     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
2172     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
2173 
2174     MI.eraseFromParent();
2175     return Legalized;
2176   }
2177   case G_USUBO: {
2178     Register Res = MI.getOperand(0).getReg();
2179     Register BorrowOut = MI.getOperand(1).getReg();
2180     Register LHS = MI.getOperand(2).getReg();
2181     Register RHS = MI.getOperand(3).getReg();
2182 
2183     MIRBuilder.buildSub(Res, LHS, RHS);
2184     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
2185 
2186     MI.eraseFromParent();
2187     return Legalized;
2188   }
2189   case G_USUBE: {
2190     Register Res = MI.getOperand(0).getReg();
2191     Register BorrowOut = MI.getOperand(1).getReg();
2192     Register LHS = MI.getOperand(2).getReg();
2193     Register RHS = MI.getOperand(3).getReg();
2194     Register BorrowIn = MI.getOperand(4).getReg();
2195 
2196     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2197     Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
2198     Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2199     Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2200 
2201     MIRBuilder.buildSub(TmpRes, LHS, RHS);
2202     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
2203     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
2204     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
2205     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
2206     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
2207 
2208     MI.eraseFromParent();
2209     return Legalized;
2210   }
2211   case G_UITOFP:
2212     return lowerUITOFP(MI, TypeIdx, Ty);
2213   case G_SITOFP:
2214     return lowerSITOFP(MI, TypeIdx, Ty);
2215   case G_FPTOUI:
2216     return lowerFPTOUI(MI, TypeIdx, Ty);
2217   case G_SMIN:
2218   case G_SMAX:
2219   case G_UMIN:
2220   case G_UMAX:
2221     return lowerMinMax(MI, TypeIdx, Ty);
2222   case G_FCOPYSIGN:
2223     return lowerFCopySign(MI, TypeIdx, Ty);
2224   case G_FMINNUM:
2225   case G_FMAXNUM:
2226     return lowerFMinNumMaxNum(MI);
2227   case G_UNMERGE_VALUES:
2228     return lowerUnmergeValues(MI);
2229   case TargetOpcode::G_SEXT_INREG: {
2230     assert(MI.getOperand(2).isImm() && "Expected immediate");
2231     int64_t SizeInBits = MI.getOperand(2).getImm();
2232 
2233     Register DstReg = MI.getOperand(0).getReg();
2234     Register SrcReg = MI.getOperand(1).getReg();
2235     LLT DstTy = MRI.getType(DstReg);
2236     Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
2237 
2238     auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
2239     MIRBuilder.buildInstr(TargetOpcode::G_SHL, {TmpRes}, {SrcReg, MIBSz->getOperand(0).getReg()});
2240     MIRBuilder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {TmpRes, MIBSz->getOperand(0).getReg()});
2241     MI.eraseFromParent();
2242     return Legalized;
2243   }
2244   case G_SHUFFLE_VECTOR:
2245     return lowerShuffleVector(MI);
2246   case G_DYN_STACKALLOC:
2247     return lowerDynStackAlloc(MI);
2248   }
2249 }
2250 
2251 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
2252     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
2253   SmallVector<Register, 2> DstRegs;
2254 
2255   unsigned NarrowSize = NarrowTy.getSizeInBits();
2256   Register DstReg = MI.getOperand(0).getReg();
2257   unsigned Size = MRI.getType(DstReg).getSizeInBits();
2258   int NumParts = Size / NarrowSize;
2259   // FIXME: Don't know how to handle the situation where the small vectors
2260   // aren't all the same size yet.
2261   if (Size % NarrowSize != 0)
2262     return UnableToLegalize;
2263 
2264   for (int i = 0; i < NumParts; ++i) {
2265     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
2266     MIRBuilder.buildUndef(TmpReg);
2267     DstRegs.push_back(TmpReg);
2268   }
2269 
2270   if (NarrowTy.isVector())
2271     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2272   else
2273     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2274 
2275   MI.eraseFromParent();
2276   return Legalized;
2277 }
2278 
2279 LegalizerHelper::LegalizeResult
2280 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
2281                                           LLT NarrowTy) {
2282   const unsigned Opc = MI.getOpcode();
2283   const unsigned NumOps = MI.getNumOperands() - 1;
2284   const unsigned NarrowSize = NarrowTy.getSizeInBits();
2285   const Register DstReg = MI.getOperand(0).getReg();
2286   const unsigned Flags = MI.getFlags();
2287   const LLT DstTy = MRI.getType(DstReg);
2288   const unsigned Size = DstTy.getSizeInBits();
2289   const int NumParts = Size / NarrowSize;
2290   const LLT EltTy = DstTy.getElementType();
2291   const unsigned EltSize = EltTy.getSizeInBits();
2292   const unsigned BitsForNumParts = NarrowSize * NumParts;
2293 
2294   // Check if we have any leftovers. If we do, then only handle the case where
2295   // the leftover is one element.
2296   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
2297     return UnableToLegalize;
2298 
2299   if (BitsForNumParts != Size) {
2300     Register AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
2301     MIRBuilder.buildUndef(AccumDstReg);
2302 
2303     // Handle the pieces which evenly divide into the requested type with
2304     // extract/op/insert sequence.
2305     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
2306       SmallVector<SrcOp, 4> SrcOps;
2307       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2308         Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
2309         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
2310         SrcOps.push_back(PartOpReg);
2311       }
2312 
2313       Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
2314       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2315 
2316       Register PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
2317       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
2318       AccumDstReg = PartInsertReg;
2319     }
2320 
2321     // Handle the remaining element sized leftover piece.
2322     SmallVector<SrcOp, 4> SrcOps;
2323     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2324       Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
2325       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
2326                               BitsForNumParts);
2327       SrcOps.push_back(PartOpReg);
2328     }
2329 
2330     Register PartDstReg = MRI.createGenericVirtualRegister(EltTy);
2331     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2332     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
2333     MI.eraseFromParent();
2334 
2335     return Legalized;
2336   }
2337 
2338   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2339 
2340   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
2341 
2342   if (NumOps >= 2)
2343     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
2344 
2345   if (NumOps >= 3)
2346     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
2347 
2348   for (int i = 0; i < NumParts; ++i) {
2349     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2350 
2351     if (NumOps == 1)
2352       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
2353     else if (NumOps == 2) {
2354       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
2355     } else if (NumOps == 3) {
2356       MIRBuilder.buildInstr(Opc, {DstReg},
2357                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
2358     }
2359 
2360     DstRegs.push_back(DstReg);
2361   }
2362 
2363   if (NarrowTy.isVector())
2364     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2365   else
2366     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2367 
2368   MI.eraseFromParent();
2369   return Legalized;
2370 }
2371 
2372 // Handle splitting vector operations which need to have the same number of
2373 // elements in each type index, but each type index may have a different element
2374 // type.
2375 //
2376 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
2377 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2378 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2379 //
2380 // Also handles some irregular breakdown cases, e.g.
2381 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
2382 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2383 //             s64 = G_SHL s64, s32
2384 LegalizerHelper::LegalizeResult
2385 LegalizerHelper::fewerElementsVectorMultiEltType(
2386   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
2387   if (TypeIdx != 0)
2388     return UnableToLegalize;
2389 
2390   const LLT NarrowTy0 = NarrowTyArg;
2391   const unsigned NewNumElts =
2392       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
2393 
2394   const Register DstReg = MI.getOperand(0).getReg();
2395   LLT DstTy = MRI.getType(DstReg);
2396   LLT LeftoverTy0;
2397 
2398   // All of the operands need to have the same number of elements, so if we can
2399   // determine a type breakdown for the result type, we can for all of the
2400   // source types.
2401   int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first;
2402   if (NumParts < 0)
2403     return UnableToLegalize;
2404 
2405   SmallVector<MachineInstrBuilder, 4> NewInsts;
2406 
2407   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2408   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2409 
2410   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2411     LLT LeftoverTy;
2412     Register SrcReg = MI.getOperand(I).getReg();
2413     LLT SrcTyI = MRI.getType(SrcReg);
2414     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
2415     LLT LeftoverTyI;
2416 
2417     // Split this operand into the requested typed registers, and any leftover
2418     // required to reproduce the original type.
2419     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
2420                       LeftoverRegs))
2421       return UnableToLegalize;
2422 
2423     if (I == 1) {
2424       // For the first operand, create an instruction for each part and setup
2425       // the result.
2426       for (Register PartReg : PartRegs) {
2427         Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2428         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2429                                .addDef(PartDstReg)
2430                                .addUse(PartReg));
2431         DstRegs.push_back(PartDstReg);
2432       }
2433 
2434       for (Register LeftoverReg : LeftoverRegs) {
2435         Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
2436         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2437                                .addDef(PartDstReg)
2438                                .addUse(LeftoverReg));
2439         LeftoverDstRegs.push_back(PartDstReg);
2440       }
2441     } else {
2442       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
2443 
2444       // Add the newly created operand splits to the existing instructions. The
2445       // odd-sized pieces are ordered after the requested NarrowTyArg sized
2446       // pieces.
2447       unsigned InstCount = 0;
2448       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
2449         NewInsts[InstCount++].addUse(PartRegs[J]);
2450       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
2451         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
2452     }
2453 
2454     PartRegs.clear();
2455     LeftoverRegs.clear();
2456   }
2457 
2458   // Insert the newly built operations and rebuild the result register.
2459   for (auto &MIB : NewInsts)
2460     MIRBuilder.insertInstr(MIB);
2461 
2462   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
2463 
2464   MI.eraseFromParent();
2465   return Legalized;
2466 }
2467 
2468 LegalizerHelper::LegalizeResult
2469 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
2470                                           LLT NarrowTy) {
2471   if (TypeIdx != 0)
2472     return UnableToLegalize;
2473 
2474   Register DstReg = MI.getOperand(0).getReg();
2475   Register SrcReg = MI.getOperand(1).getReg();
2476   LLT DstTy = MRI.getType(DstReg);
2477   LLT SrcTy = MRI.getType(SrcReg);
2478 
2479   LLT NarrowTy0 = NarrowTy;
2480   LLT NarrowTy1;
2481   unsigned NumParts;
2482 
2483   if (NarrowTy.isVector()) {
2484     // Uneven breakdown not handled.
2485     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
2486     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
2487       return UnableToLegalize;
2488 
2489     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
2490   } else {
2491     NumParts = DstTy.getNumElements();
2492     NarrowTy1 = SrcTy.getElementType();
2493   }
2494 
2495   SmallVector<Register, 4> SrcRegs, DstRegs;
2496   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
2497 
2498   for (unsigned I = 0; I < NumParts; ++I) {
2499     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2500     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
2501       .addDef(DstReg)
2502       .addUse(SrcRegs[I]);
2503 
2504     NewInst->setFlags(MI.getFlags());
2505     DstRegs.push_back(DstReg);
2506   }
2507 
2508   if (NarrowTy.isVector())
2509     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2510   else
2511     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2512 
2513   MI.eraseFromParent();
2514   return Legalized;
2515 }
2516 
2517 LegalizerHelper::LegalizeResult
2518 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
2519                                         LLT NarrowTy) {
2520   Register DstReg = MI.getOperand(0).getReg();
2521   Register Src0Reg = MI.getOperand(2).getReg();
2522   LLT DstTy = MRI.getType(DstReg);
2523   LLT SrcTy = MRI.getType(Src0Reg);
2524 
2525   unsigned NumParts;
2526   LLT NarrowTy0, NarrowTy1;
2527 
2528   if (TypeIdx == 0) {
2529     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2530     unsigned OldElts = DstTy.getNumElements();
2531 
2532     NarrowTy0 = NarrowTy;
2533     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
2534     NarrowTy1 = NarrowTy.isVector() ?
2535       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
2536       SrcTy.getElementType();
2537 
2538   } else {
2539     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2540     unsigned OldElts = SrcTy.getNumElements();
2541 
2542     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
2543       NarrowTy.getNumElements();
2544     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
2545                             DstTy.getScalarSizeInBits());
2546     NarrowTy1 = NarrowTy;
2547   }
2548 
2549   // FIXME: Don't know how to handle the situation where the small vectors
2550   // aren't all the same size yet.
2551   if (NarrowTy1.isVector() &&
2552       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
2553     return UnableToLegalize;
2554 
2555   CmpInst::Predicate Pred
2556     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
2557 
2558   SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
2559   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
2560   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
2561 
2562   for (unsigned I = 0; I < NumParts; ++I) {
2563     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2564     DstRegs.push_back(DstReg);
2565 
2566     if (MI.getOpcode() == TargetOpcode::G_ICMP)
2567       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2568     else {
2569       MachineInstr *NewCmp
2570         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2571       NewCmp->setFlags(MI.getFlags());
2572     }
2573   }
2574 
2575   if (NarrowTy1.isVector())
2576     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2577   else
2578     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2579 
2580   MI.eraseFromParent();
2581   return Legalized;
2582 }
2583 
2584 LegalizerHelper::LegalizeResult
2585 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
2586                                            LLT NarrowTy) {
2587   Register DstReg = MI.getOperand(0).getReg();
2588   Register CondReg = MI.getOperand(1).getReg();
2589 
2590   unsigned NumParts = 0;
2591   LLT NarrowTy0, NarrowTy1;
2592 
2593   LLT DstTy = MRI.getType(DstReg);
2594   LLT CondTy = MRI.getType(CondReg);
2595   unsigned Size = DstTy.getSizeInBits();
2596 
2597   assert(TypeIdx == 0 || CondTy.isVector());
2598 
2599   if (TypeIdx == 0) {
2600     NarrowTy0 = NarrowTy;
2601     NarrowTy1 = CondTy;
2602 
2603     unsigned NarrowSize = NarrowTy0.getSizeInBits();
2604     // FIXME: Don't know how to handle the situation where the small vectors
2605     // aren't all the same size yet.
2606     if (Size % NarrowSize != 0)
2607       return UnableToLegalize;
2608 
2609     NumParts = Size / NarrowSize;
2610 
2611     // Need to break down the condition type
2612     if (CondTy.isVector()) {
2613       if (CondTy.getNumElements() == NumParts)
2614         NarrowTy1 = CondTy.getElementType();
2615       else
2616         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
2617                                 CondTy.getScalarSizeInBits());
2618     }
2619   } else {
2620     NumParts = CondTy.getNumElements();
2621     if (NarrowTy.isVector()) {
2622       // TODO: Handle uneven breakdown.
2623       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
2624         return UnableToLegalize;
2625 
2626       return UnableToLegalize;
2627     } else {
2628       NarrowTy0 = DstTy.getElementType();
2629       NarrowTy1 = NarrowTy;
2630     }
2631   }
2632 
2633   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2634   if (CondTy.isVector())
2635     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2636 
2637   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2638   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2639 
2640   for (unsigned i = 0; i < NumParts; ++i) {
2641     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2642     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
2643                            Src1Regs[i], Src2Regs[i]);
2644     DstRegs.push_back(DstReg);
2645   }
2646 
2647   if (NarrowTy0.isVector())
2648     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2649   else
2650     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2651 
2652   MI.eraseFromParent();
2653   return Legalized;
2654 }
2655 
2656 LegalizerHelper::LegalizeResult
2657 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2658                                         LLT NarrowTy) {
2659   const Register DstReg = MI.getOperand(0).getReg();
2660   LLT PhiTy = MRI.getType(DstReg);
2661   LLT LeftoverTy;
2662 
2663   // All of the operands need to have the same number of elements, so if we can
2664   // determine a type breakdown for the result type, we can for all of the
2665   // source types.
2666   int NumParts, NumLeftover;
2667   std::tie(NumParts, NumLeftover)
2668     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2669   if (NumParts < 0)
2670     return UnableToLegalize;
2671 
2672   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2673   SmallVector<MachineInstrBuilder, 4> NewInsts;
2674 
2675   const int TotalNumParts = NumParts + NumLeftover;
2676 
2677   // Insert the new phis in the result block first.
2678   for (int I = 0; I != TotalNumParts; ++I) {
2679     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2680     Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
2681     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2682                        .addDef(PartDstReg));
2683     if (I < NumParts)
2684       DstRegs.push_back(PartDstReg);
2685     else
2686       LeftoverDstRegs.push_back(PartDstReg);
2687   }
2688 
2689   MachineBasicBlock *MBB = MI.getParent();
2690   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2691   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2692 
2693   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2694 
2695   // Insert code to extract the incoming values in each predecessor block.
2696   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2697     PartRegs.clear();
2698     LeftoverRegs.clear();
2699 
2700     Register SrcReg = MI.getOperand(I).getReg();
2701     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2702     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2703 
2704     LLT Unused;
2705     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2706                       LeftoverRegs))
2707       return UnableToLegalize;
2708 
2709     // Add the newly created operand splits to the existing instructions. The
2710     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2711     // pieces.
2712     for (int J = 0; J != TotalNumParts; ++J) {
2713       MachineInstrBuilder MIB = NewInsts[J];
2714       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2715       MIB.addMBB(&OpMBB);
2716     }
2717   }
2718 
2719   MI.eraseFromParent();
2720   return Legalized;
2721 }
2722 
2723 LegalizerHelper::LegalizeResult
2724 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
2725                                                   unsigned TypeIdx,
2726                                                   LLT NarrowTy) {
2727   if (TypeIdx != 1)
2728     return UnableToLegalize;
2729 
2730   const int NumDst = MI.getNumOperands() - 1;
2731   const Register SrcReg = MI.getOperand(NumDst).getReg();
2732   LLT SrcTy = MRI.getType(SrcReg);
2733 
2734   LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2735 
2736   // TODO: Create sequence of extracts.
2737   if (DstTy == NarrowTy)
2738     return UnableToLegalize;
2739 
2740   LLT GCDTy = getGCDType(SrcTy, NarrowTy);
2741   if (DstTy == GCDTy) {
2742     // This would just be a copy of the same unmerge.
2743     // TODO: Create extracts, pad with undef and create intermediate merges.
2744     return UnableToLegalize;
2745   }
2746 
2747   auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
2748   const int NumUnmerge = Unmerge->getNumOperands() - 1;
2749   const int PartsPerUnmerge = NumDst / NumUnmerge;
2750 
2751   for (int I = 0; I != NumUnmerge; ++I) {
2752     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
2753 
2754     for (int J = 0; J != PartsPerUnmerge; ++J)
2755       MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg());
2756     MIB.addUse(Unmerge.getReg(I));
2757   }
2758 
2759   MI.eraseFromParent();
2760   return Legalized;
2761 }
2762 
2763 LegalizerHelper::LegalizeResult
2764 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2765                                       LLT NarrowTy) {
2766   // FIXME: Don't know how to handle secondary types yet.
2767   if (TypeIdx != 0)
2768     return UnableToLegalize;
2769 
2770   MachineMemOperand *MMO = *MI.memoperands_begin();
2771 
2772   // This implementation doesn't work for atomics. Give up instead of doing
2773   // something invalid.
2774   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2775       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2776     return UnableToLegalize;
2777 
2778   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2779   Register ValReg = MI.getOperand(0).getReg();
2780   Register AddrReg = MI.getOperand(1).getReg();
2781   LLT ValTy = MRI.getType(ValReg);
2782 
2783   int NumParts = -1;
2784   int NumLeftover = -1;
2785   LLT LeftoverTy;
2786   SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
2787   if (IsLoad) {
2788     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2789   } else {
2790     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2791                      NarrowLeftoverRegs)) {
2792       NumParts = NarrowRegs.size();
2793       NumLeftover = NarrowLeftoverRegs.size();
2794     }
2795   }
2796 
2797   if (NumParts == -1)
2798     return UnableToLegalize;
2799 
2800   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2801 
2802   unsigned TotalSize = ValTy.getSizeInBits();
2803 
2804   // Split the load/store into PartTy sized pieces starting at Offset. If this
2805   // is a load, return the new registers in ValRegs. For a store, each elements
2806   // of ValRegs should be PartTy. Returns the next offset that needs to be
2807   // handled.
2808   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
2809                              unsigned Offset) -> unsigned {
2810     MachineFunction &MF = MIRBuilder.getMF();
2811     unsigned PartSize = PartTy.getSizeInBits();
2812     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2813          Offset += PartSize, ++Idx) {
2814       unsigned ByteSize = PartSize / 8;
2815       unsigned ByteOffset = Offset / 8;
2816       Register NewAddrReg;
2817 
2818       MIRBuilder.materializeGEP(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2819 
2820       MachineMemOperand *NewMMO =
2821         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2822 
2823       if (IsLoad) {
2824         Register Dst = MRI.createGenericVirtualRegister(PartTy);
2825         ValRegs.push_back(Dst);
2826         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
2827       } else {
2828         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
2829       }
2830     }
2831 
2832     return Offset;
2833   };
2834 
2835   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
2836 
2837   // Handle the rest of the register if this isn't an even type breakdown.
2838   if (LeftoverTy.isValid())
2839     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
2840 
2841   if (IsLoad) {
2842     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
2843                 LeftoverTy, NarrowLeftoverRegs);
2844   }
2845 
2846   MI.eraseFromParent();
2847   return Legalized;
2848 }
2849 
2850 LegalizerHelper::LegalizeResult
2851 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
2852                                      LLT NarrowTy) {
2853   using namespace TargetOpcode;
2854 
2855   MIRBuilder.setInstr(MI);
2856   switch (MI.getOpcode()) {
2857   case G_IMPLICIT_DEF:
2858     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
2859   case G_AND:
2860   case G_OR:
2861   case G_XOR:
2862   case G_ADD:
2863   case G_SUB:
2864   case G_MUL:
2865   case G_SMULH:
2866   case G_UMULH:
2867   case G_FADD:
2868   case G_FMUL:
2869   case G_FSUB:
2870   case G_FNEG:
2871   case G_FABS:
2872   case G_FCANONICALIZE:
2873   case G_FDIV:
2874   case G_FREM:
2875   case G_FMA:
2876   case G_FMAD:
2877   case G_FPOW:
2878   case G_FEXP:
2879   case G_FEXP2:
2880   case G_FLOG:
2881   case G_FLOG2:
2882   case G_FLOG10:
2883   case G_FNEARBYINT:
2884   case G_FCEIL:
2885   case G_FFLOOR:
2886   case G_FRINT:
2887   case G_INTRINSIC_ROUND:
2888   case G_INTRINSIC_TRUNC:
2889   case G_FCOS:
2890   case G_FSIN:
2891   case G_FSQRT:
2892   case G_BSWAP:
2893   case G_BITREVERSE:
2894   case G_SDIV:
2895   case G_SMIN:
2896   case G_SMAX:
2897   case G_UMIN:
2898   case G_UMAX:
2899   case G_FMINNUM:
2900   case G_FMAXNUM:
2901   case G_FMINNUM_IEEE:
2902   case G_FMAXNUM_IEEE:
2903   case G_FMINIMUM:
2904   case G_FMAXIMUM:
2905     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
2906   case G_SHL:
2907   case G_LSHR:
2908   case G_ASHR:
2909   case G_CTLZ:
2910   case G_CTLZ_ZERO_UNDEF:
2911   case G_CTTZ:
2912   case G_CTTZ_ZERO_UNDEF:
2913   case G_CTPOP:
2914   case G_FCOPYSIGN:
2915     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
2916   case G_ZEXT:
2917   case G_SEXT:
2918   case G_ANYEXT:
2919   case G_FPEXT:
2920   case G_FPTRUNC:
2921   case G_SITOFP:
2922   case G_UITOFP:
2923   case G_FPTOSI:
2924   case G_FPTOUI:
2925   case G_INTTOPTR:
2926   case G_PTRTOINT:
2927   case G_ADDRSPACE_CAST:
2928     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
2929   case G_ICMP:
2930   case G_FCMP:
2931     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
2932   case G_SELECT:
2933     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
2934   case G_PHI:
2935     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
2936   case G_UNMERGE_VALUES:
2937     return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy);
2938   case G_LOAD:
2939   case G_STORE:
2940     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
2941   default:
2942     return UnableToLegalize;
2943   }
2944 }
2945 
2946 LegalizerHelper::LegalizeResult
2947 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
2948                                              const LLT HalfTy, const LLT AmtTy) {
2949 
2950   Register InL = MRI.createGenericVirtualRegister(HalfTy);
2951   Register InH = MRI.createGenericVirtualRegister(HalfTy);
2952   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
2953 
2954   if (Amt.isNullValue()) {
2955     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
2956     MI.eraseFromParent();
2957     return Legalized;
2958   }
2959 
2960   LLT NVT = HalfTy;
2961   unsigned NVTBits = HalfTy.getSizeInBits();
2962   unsigned VTBits = 2 * NVTBits;
2963 
2964   SrcOp Lo(Register(0)), Hi(Register(0));
2965   if (MI.getOpcode() == TargetOpcode::G_SHL) {
2966     if (Amt.ugt(VTBits)) {
2967       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2968     } else if (Amt.ugt(NVTBits)) {
2969       Lo = MIRBuilder.buildConstant(NVT, 0);
2970       Hi = MIRBuilder.buildShl(NVT, InL,
2971                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2972     } else if (Amt == NVTBits) {
2973       Lo = MIRBuilder.buildConstant(NVT, 0);
2974       Hi = InL;
2975     } else {
2976       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
2977       auto OrLHS =
2978           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
2979       auto OrRHS = MIRBuilder.buildLShr(
2980           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2981       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
2982     }
2983   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
2984     if (Amt.ugt(VTBits)) {
2985       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
2986     } else if (Amt.ugt(NVTBits)) {
2987       Lo = MIRBuilder.buildLShr(NVT, InH,
2988                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
2989       Hi = MIRBuilder.buildConstant(NVT, 0);
2990     } else if (Amt == NVTBits) {
2991       Lo = InH;
2992       Hi = MIRBuilder.buildConstant(NVT, 0);
2993     } else {
2994       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
2995 
2996       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
2997       auto OrRHS = MIRBuilder.buildShl(
2998           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
2999 
3000       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3001       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
3002     }
3003   } else {
3004     if (Amt.ugt(VTBits)) {
3005       Hi = Lo = MIRBuilder.buildAShr(
3006           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3007     } else if (Amt.ugt(NVTBits)) {
3008       Lo = MIRBuilder.buildAShr(NVT, InH,
3009                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3010       Hi = MIRBuilder.buildAShr(NVT, InH,
3011                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3012     } else if (Amt == NVTBits) {
3013       Lo = InH;
3014       Hi = MIRBuilder.buildAShr(NVT, InH,
3015                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3016     } else {
3017       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3018 
3019       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3020       auto OrRHS = MIRBuilder.buildShl(
3021           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3022 
3023       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3024       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
3025     }
3026   }
3027 
3028   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
3029   MI.eraseFromParent();
3030 
3031   return Legalized;
3032 }
3033 
3034 // TODO: Optimize if constant shift amount.
3035 LegalizerHelper::LegalizeResult
3036 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
3037                                    LLT RequestedTy) {
3038   if (TypeIdx == 1) {
3039     Observer.changingInstr(MI);
3040     narrowScalarSrc(MI, RequestedTy, 2);
3041     Observer.changedInstr(MI);
3042     return Legalized;
3043   }
3044 
3045   Register DstReg = MI.getOperand(0).getReg();
3046   LLT DstTy = MRI.getType(DstReg);
3047   if (DstTy.isVector())
3048     return UnableToLegalize;
3049 
3050   Register Amt = MI.getOperand(2).getReg();
3051   LLT ShiftAmtTy = MRI.getType(Amt);
3052   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
3053   if (DstEltSize % 2 != 0)
3054     return UnableToLegalize;
3055 
3056   // Ignore the input type. We can only go to exactly half the size of the
3057   // input. If that isn't small enough, the resulting pieces will be further
3058   // legalized.
3059   const unsigned NewBitSize = DstEltSize / 2;
3060   const LLT HalfTy = LLT::scalar(NewBitSize);
3061   const LLT CondTy = LLT::scalar(1);
3062 
3063   if (const MachineInstr *KShiftAmt =
3064           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
3065     return narrowScalarShiftByConstant(
3066         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
3067   }
3068 
3069   // TODO: Expand with known bits.
3070 
3071   // Handle the fully general expansion by an unknown amount.
3072   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
3073 
3074   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3075   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3076   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3077 
3078   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
3079   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
3080 
3081   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
3082   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
3083   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
3084 
3085   Register ResultRegs[2];
3086   switch (MI.getOpcode()) {
3087   case TargetOpcode::G_SHL: {
3088     // Short: ShAmt < NewBitSize
3089     auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt);
3090 
3091     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
3092     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt);
3093     auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3094 
3095     // Long: ShAmt >= NewBitSize
3096     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
3097     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
3098 
3099     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
3100     auto Hi = MIRBuilder.buildSelect(
3101         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
3102 
3103     ResultRegs[0] = Lo.getReg(0);
3104     ResultRegs[1] = Hi.getReg(0);
3105     break;
3106   }
3107   case TargetOpcode::G_LSHR:
3108   case TargetOpcode::G_ASHR: {
3109     // Short: ShAmt < NewBitSize
3110     auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt});
3111 
3112     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt);
3113     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
3114     auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3115 
3116     // Long: ShAmt >= NewBitSize
3117     MachineInstrBuilder HiL;
3118     if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3119       HiL = MIRBuilder.buildConstant(HalfTy, 0);            // Hi part is zero.
3120     } else {
3121       auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1);
3122       HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt);    // Sign of Hi part.
3123     }
3124     auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy},
3125                                      {InH, AmtExcess});     // Lo from Hi part.
3126 
3127     auto Lo = MIRBuilder.buildSelect(
3128         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
3129 
3130     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
3131 
3132     ResultRegs[0] = Lo.getReg(0);
3133     ResultRegs[1] = Hi.getReg(0);
3134     break;
3135   }
3136   default:
3137     llvm_unreachable("not a shift");
3138   }
3139 
3140   MIRBuilder.buildMerge(DstReg, ResultRegs);
3141   MI.eraseFromParent();
3142   return Legalized;
3143 }
3144 
3145 LegalizerHelper::LegalizeResult
3146 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
3147                                        LLT MoreTy) {
3148   assert(TypeIdx == 0 && "Expecting only Idx 0");
3149 
3150   Observer.changingInstr(MI);
3151   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
3152     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
3153     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
3154     moreElementsVectorSrc(MI, MoreTy, I);
3155   }
3156 
3157   MachineBasicBlock &MBB = *MI.getParent();
3158   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
3159   moreElementsVectorDst(MI, MoreTy, 0);
3160   Observer.changedInstr(MI);
3161   return Legalized;
3162 }
3163 
3164 LegalizerHelper::LegalizeResult
3165 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
3166                                     LLT MoreTy) {
3167   MIRBuilder.setInstr(MI);
3168   unsigned Opc = MI.getOpcode();
3169   switch (Opc) {
3170   case TargetOpcode::G_IMPLICIT_DEF:
3171   case TargetOpcode::G_LOAD: {
3172     if (TypeIdx != 0)
3173       return UnableToLegalize;
3174     Observer.changingInstr(MI);
3175     moreElementsVectorDst(MI, MoreTy, 0);
3176     Observer.changedInstr(MI);
3177     return Legalized;
3178   }
3179   case TargetOpcode::G_STORE:
3180     if (TypeIdx != 0)
3181       return UnableToLegalize;
3182     Observer.changingInstr(MI);
3183     moreElementsVectorSrc(MI, MoreTy, 0);
3184     Observer.changedInstr(MI);
3185     return Legalized;
3186   case TargetOpcode::G_AND:
3187   case TargetOpcode::G_OR:
3188   case TargetOpcode::G_XOR:
3189   case TargetOpcode::G_SMIN:
3190   case TargetOpcode::G_SMAX:
3191   case TargetOpcode::G_UMIN:
3192   case TargetOpcode::G_UMAX: {
3193     Observer.changingInstr(MI);
3194     moreElementsVectorSrc(MI, MoreTy, 1);
3195     moreElementsVectorSrc(MI, MoreTy, 2);
3196     moreElementsVectorDst(MI, MoreTy, 0);
3197     Observer.changedInstr(MI);
3198     return Legalized;
3199   }
3200   case TargetOpcode::G_EXTRACT:
3201     if (TypeIdx != 1)
3202       return UnableToLegalize;
3203     Observer.changingInstr(MI);
3204     moreElementsVectorSrc(MI, MoreTy, 1);
3205     Observer.changedInstr(MI);
3206     return Legalized;
3207   case TargetOpcode::G_INSERT:
3208     if (TypeIdx != 0)
3209       return UnableToLegalize;
3210     Observer.changingInstr(MI);
3211     moreElementsVectorSrc(MI, MoreTy, 1);
3212     moreElementsVectorDst(MI, MoreTy, 0);
3213     Observer.changedInstr(MI);
3214     return Legalized;
3215   case TargetOpcode::G_SELECT:
3216     if (TypeIdx != 0)
3217       return UnableToLegalize;
3218     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
3219       return UnableToLegalize;
3220 
3221     Observer.changingInstr(MI);
3222     moreElementsVectorSrc(MI, MoreTy, 2);
3223     moreElementsVectorSrc(MI, MoreTy, 3);
3224     moreElementsVectorDst(MI, MoreTy, 0);
3225     Observer.changedInstr(MI);
3226     return Legalized;
3227   case TargetOpcode::G_UNMERGE_VALUES: {
3228     if (TypeIdx != 1)
3229       return UnableToLegalize;
3230 
3231     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
3232     int NumDst = MI.getNumOperands() - 1;
3233     moreElementsVectorSrc(MI, MoreTy, NumDst);
3234 
3235     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
3236     for (int I = 0; I != NumDst; ++I)
3237       MIB.addDef(MI.getOperand(I).getReg());
3238 
3239     int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits();
3240     for (int I = NumDst; I != NewNumDst; ++I)
3241       MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
3242 
3243     MIB.addUse(MI.getOperand(NumDst).getReg());
3244     MI.eraseFromParent();
3245     return Legalized;
3246   }
3247   case TargetOpcode::G_PHI:
3248     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
3249   default:
3250     return UnableToLegalize;
3251   }
3252 }
3253 
3254 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
3255                                         ArrayRef<Register> Src1Regs,
3256                                         ArrayRef<Register> Src2Regs,
3257                                         LLT NarrowTy) {
3258   MachineIRBuilder &B = MIRBuilder;
3259   unsigned SrcParts = Src1Regs.size();
3260   unsigned DstParts = DstRegs.size();
3261 
3262   unsigned DstIdx = 0; // Low bits of the result.
3263   Register FactorSum =
3264       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
3265   DstRegs[DstIdx] = FactorSum;
3266 
3267   unsigned CarrySumPrevDstIdx;
3268   SmallVector<Register, 4> Factors;
3269 
3270   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
3271     // Collect low parts of muls for DstIdx.
3272     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
3273          i <= std::min(DstIdx, SrcParts - 1); ++i) {
3274       MachineInstrBuilder Mul =
3275           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
3276       Factors.push_back(Mul.getReg(0));
3277     }
3278     // Collect high parts of muls from previous DstIdx.
3279     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
3280          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
3281       MachineInstrBuilder Umulh =
3282           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
3283       Factors.push_back(Umulh.getReg(0));
3284     }
3285     // Add CarrySum from additons calculated for previous DstIdx.
3286     if (DstIdx != 1) {
3287       Factors.push_back(CarrySumPrevDstIdx);
3288     }
3289 
3290     Register CarrySum;
3291     // Add all factors and accumulate all carries into CarrySum.
3292     if (DstIdx != DstParts - 1) {
3293       MachineInstrBuilder Uaddo =
3294           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
3295       FactorSum = Uaddo.getReg(0);
3296       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
3297       for (unsigned i = 2; i < Factors.size(); ++i) {
3298         MachineInstrBuilder Uaddo =
3299             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
3300         FactorSum = Uaddo.getReg(0);
3301         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
3302         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
3303       }
3304     } else {
3305       // Since value for the next index is not calculated, neither is CarrySum.
3306       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
3307       for (unsigned i = 2; i < Factors.size(); ++i)
3308         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
3309     }
3310 
3311     CarrySumPrevDstIdx = CarrySum;
3312     DstRegs[DstIdx] = FactorSum;
3313     Factors.clear();
3314   }
3315 }
3316 
3317 LegalizerHelper::LegalizeResult
3318 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
3319   Register DstReg = MI.getOperand(0).getReg();
3320   Register Src1 = MI.getOperand(1).getReg();
3321   Register Src2 = MI.getOperand(2).getReg();
3322 
3323   LLT Ty = MRI.getType(DstReg);
3324   if (Ty.isVector())
3325     return UnableToLegalize;
3326 
3327   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
3328   unsigned DstSize = Ty.getSizeInBits();
3329   unsigned NarrowSize = NarrowTy.getSizeInBits();
3330   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
3331     return UnableToLegalize;
3332 
3333   unsigned NumDstParts = DstSize / NarrowSize;
3334   unsigned NumSrcParts = SrcSize / NarrowSize;
3335   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
3336   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
3337 
3338   SmallVector<Register, 2> Src1Parts, Src2Parts, DstTmpRegs;
3339   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
3340   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
3341   DstTmpRegs.resize(DstTmpParts);
3342   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
3343 
3344   // Take only high half of registers if this is high mul.
3345   ArrayRef<Register> DstRegs(
3346       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
3347   MIRBuilder.buildMerge(DstReg, DstRegs);
3348   MI.eraseFromParent();
3349   return Legalized;
3350 }
3351 
3352 LegalizerHelper::LegalizeResult
3353 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
3354                                      LLT NarrowTy) {
3355   if (TypeIdx != 1)
3356     return UnableToLegalize;
3357 
3358   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3359 
3360   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
3361   // FIXME: add support for when SizeOp1 isn't an exact multiple of
3362   // NarrowSize.
3363   if (SizeOp1 % NarrowSize != 0)
3364     return UnableToLegalize;
3365   int NumParts = SizeOp1 / NarrowSize;
3366 
3367   SmallVector<Register, 2> SrcRegs, DstRegs;
3368   SmallVector<uint64_t, 2> Indexes;
3369   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3370 
3371   Register OpReg = MI.getOperand(0).getReg();
3372   uint64_t OpStart = MI.getOperand(2).getImm();
3373   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3374   for (int i = 0; i < NumParts; ++i) {
3375     unsigned SrcStart = i * NarrowSize;
3376 
3377     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
3378       // No part of the extract uses this subregister, ignore it.
3379       continue;
3380     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3381       // The entire subregister is extracted, forward the value.
3382       DstRegs.push_back(SrcRegs[i]);
3383       continue;
3384     }
3385 
3386     // OpSegStart is where this destination segment would start in OpReg if it
3387     // extended infinitely in both directions.
3388     int64_t ExtractOffset;
3389     uint64_t SegSize;
3390     if (OpStart < SrcStart) {
3391       ExtractOffset = 0;
3392       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
3393     } else {
3394       ExtractOffset = OpStart - SrcStart;
3395       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
3396     }
3397 
3398     Register SegReg = SrcRegs[i];
3399     if (ExtractOffset != 0 || SegSize != NarrowSize) {
3400       // A genuine extract is needed.
3401       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3402       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
3403     }
3404 
3405     DstRegs.push_back(SegReg);
3406   }
3407 
3408   Register DstReg = MI.getOperand(0).getReg();
3409   if(MRI.getType(DstReg).isVector())
3410     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3411   else
3412     MIRBuilder.buildMerge(DstReg, DstRegs);
3413   MI.eraseFromParent();
3414   return Legalized;
3415 }
3416 
3417 LegalizerHelper::LegalizeResult
3418 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
3419                                     LLT NarrowTy) {
3420   // FIXME: Don't know how to handle secondary types yet.
3421   if (TypeIdx != 0)
3422     return UnableToLegalize;
3423 
3424   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
3425   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3426 
3427   // FIXME: add support for when SizeOp0 isn't an exact multiple of
3428   // NarrowSize.
3429   if (SizeOp0 % NarrowSize != 0)
3430     return UnableToLegalize;
3431 
3432   int NumParts = SizeOp0 / NarrowSize;
3433 
3434   SmallVector<Register, 2> SrcRegs, DstRegs;
3435   SmallVector<uint64_t, 2> Indexes;
3436   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3437 
3438   Register OpReg = MI.getOperand(2).getReg();
3439   uint64_t OpStart = MI.getOperand(3).getImm();
3440   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3441   for (int i = 0; i < NumParts; ++i) {
3442     unsigned DstStart = i * NarrowSize;
3443 
3444     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
3445       // No part of the insert affects this subregister, forward the original.
3446       DstRegs.push_back(SrcRegs[i]);
3447       continue;
3448     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3449       // The entire subregister is defined by this insert, forward the new
3450       // value.
3451       DstRegs.push_back(OpReg);
3452       continue;
3453     }
3454 
3455     // OpSegStart is where this destination segment would start in OpReg if it
3456     // extended infinitely in both directions.
3457     int64_t ExtractOffset, InsertOffset;
3458     uint64_t SegSize;
3459     if (OpStart < DstStart) {
3460       InsertOffset = 0;
3461       ExtractOffset = DstStart - OpStart;
3462       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
3463     } else {
3464       InsertOffset = OpStart - DstStart;
3465       ExtractOffset = 0;
3466       SegSize =
3467         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
3468     }
3469 
3470     Register SegReg = OpReg;
3471     if (ExtractOffset != 0 || SegSize != OpSize) {
3472       // A genuine extract is needed.
3473       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3474       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
3475     }
3476 
3477     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
3478     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
3479     DstRegs.push_back(DstReg);
3480   }
3481 
3482   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
3483   Register DstReg = MI.getOperand(0).getReg();
3484   if(MRI.getType(DstReg).isVector())
3485     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3486   else
3487     MIRBuilder.buildMerge(DstReg, DstRegs);
3488   MI.eraseFromParent();
3489   return Legalized;
3490 }
3491 
3492 LegalizerHelper::LegalizeResult
3493 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
3494                                    LLT NarrowTy) {
3495   Register DstReg = MI.getOperand(0).getReg();
3496   LLT DstTy = MRI.getType(DstReg);
3497 
3498   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
3499 
3500   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3501   SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
3502   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3503   LLT LeftoverTy;
3504   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
3505                     Src0Regs, Src0LeftoverRegs))
3506     return UnableToLegalize;
3507 
3508   LLT Unused;
3509   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
3510                     Src1Regs, Src1LeftoverRegs))
3511     llvm_unreachable("inconsistent extractParts result");
3512 
3513   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3514     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
3515                                         {Src0Regs[I], Src1Regs[I]});
3516     DstRegs.push_back(Inst->getOperand(0).getReg());
3517   }
3518 
3519   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3520     auto Inst = MIRBuilder.buildInstr(
3521       MI.getOpcode(),
3522       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
3523     DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
3524   }
3525 
3526   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3527               LeftoverTy, DstLeftoverRegs);
3528 
3529   MI.eraseFromParent();
3530   return Legalized;
3531 }
3532 
3533 LegalizerHelper::LegalizeResult
3534 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
3535                                     LLT NarrowTy) {
3536   if (TypeIdx != 0)
3537     return UnableToLegalize;
3538 
3539   Register CondReg = MI.getOperand(1).getReg();
3540   LLT CondTy = MRI.getType(CondReg);
3541   if (CondTy.isVector()) // TODO: Handle vselect
3542     return UnableToLegalize;
3543 
3544   Register DstReg = MI.getOperand(0).getReg();
3545   LLT DstTy = MRI.getType(DstReg);
3546 
3547   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3548   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3549   SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
3550   LLT LeftoverTy;
3551   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
3552                     Src1Regs, Src1LeftoverRegs))
3553     return UnableToLegalize;
3554 
3555   LLT Unused;
3556   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
3557                     Src2Regs, Src2LeftoverRegs))
3558     llvm_unreachable("inconsistent extractParts result");
3559 
3560   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3561     auto Select = MIRBuilder.buildSelect(NarrowTy,
3562                                          CondReg, Src1Regs[I], Src2Regs[I]);
3563     DstRegs.push_back(Select->getOperand(0).getReg());
3564   }
3565 
3566   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3567     auto Select = MIRBuilder.buildSelect(
3568       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
3569     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
3570   }
3571 
3572   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3573               LeftoverTy, DstLeftoverRegs);
3574 
3575   MI.eraseFromParent();
3576   return Legalized;
3577 }
3578 
3579 LegalizerHelper::LegalizeResult
3580 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3581   unsigned Opc = MI.getOpcode();
3582   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
3583   auto isSupported = [this](const LegalityQuery &Q) {
3584     auto QAction = LI.getAction(Q).Action;
3585     return QAction == Legal || QAction == Libcall || QAction == Custom;
3586   };
3587   switch (Opc) {
3588   default:
3589     return UnableToLegalize;
3590   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
3591     // This trivially expands to CTLZ.
3592     Observer.changingInstr(MI);
3593     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
3594     Observer.changedInstr(MI);
3595     return Legalized;
3596   }
3597   case TargetOpcode::G_CTLZ: {
3598     Register SrcReg = MI.getOperand(1).getReg();
3599     unsigned Len = Ty.getSizeInBits();
3600     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
3601       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
3602       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
3603                                              {Ty}, {SrcReg});
3604       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3605       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3606       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3607                                           SrcReg, MIBZero);
3608       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3609                              MIBCtlzZU);
3610       MI.eraseFromParent();
3611       return Legalized;
3612     }
3613     // for now, we do this:
3614     // NewLen = NextPowerOf2(Len);
3615     // x = x | (x >> 1);
3616     // x = x | (x >> 2);
3617     // ...
3618     // x = x | (x >>16);
3619     // x = x | (x >>32); // for 64-bit input
3620     // Upto NewLen/2
3621     // return Len - popcount(x);
3622     //
3623     // Ref: "Hacker's Delight" by Henry Warren
3624     Register Op = SrcReg;
3625     unsigned NewLen = PowerOf2Ceil(Len);
3626     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
3627       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
3628       auto MIBOp = MIRBuilder.buildInstr(
3629           TargetOpcode::G_OR, {Ty},
3630           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
3631                                      {Op, MIBShiftAmt})});
3632       Op = MIBOp->getOperand(0).getReg();
3633     }
3634     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
3635     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3636                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
3637     MI.eraseFromParent();
3638     return Legalized;
3639   }
3640   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
3641     // This trivially expands to CTTZ.
3642     Observer.changingInstr(MI);
3643     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
3644     Observer.changedInstr(MI);
3645     return Legalized;
3646   }
3647   case TargetOpcode::G_CTTZ: {
3648     Register SrcReg = MI.getOperand(1).getReg();
3649     unsigned Len = Ty.getSizeInBits();
3650     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
3651       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
3652       // zero.
3653       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
3654                                              {Ty}, {SrcReg});
3655       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3656       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3657       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3658                                           SrcReg, MIBZero);
3659       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3660                              MIBCttzZU);
3661       MI.eraseFromParent();
3662       return Legalized;
3663     }
3664     // for now, we use: { return popcount(~x & (x - 1)); }
3665     // unless the target has ctlz but not ctpop, in which case we use:
3666     // { return 32 - nlz(~x & (x-1)); }
3667     // Ref: "Hacker's Delight" by Henry Warren
3668     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
3669     auto MIBNot =
3670         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
3671     auto MIBTmp = MIRBuilder.buildInstr(
3672         TargetOpcode::G_AND, {Ty},
3673         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
3674                                        {SrcReg, MIBCstNeg1})});
3675     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
3676         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
3677       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
3678       MIRBuilder.buildInstr(
3679           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3680           {MIBCstLen,
3681            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
3682       MI.eraseFromParent();
3683       return Legalized;
3684     }
3685     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
3686     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3687     return Legalized;
3688   }
3689   }
3690 }
3691 
3692 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
3693 // representation.
3694 LegalizerHelper::LegalizeResult
3695 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
3696   Register Dst = MI.getOperand(0).getReg();
3697   Register Src = MI.getOperand(1).getReg();
3698   const LLT S64 = LLT::scalar(64);
3699   const LLT S32 = LLT::scalar(32);
3700   const LLT S1 = LLT::scalar(1);
3701 
3702   assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
3703 
3704   // unsigned cul2f(ulong u) {
3705   //   uint lz = clz(u);
3706   //   uint e = (u != 0) ? 127U + 63U - lz : 0;
3707   //   u = (u << lz) & 0x7fffffffffffffffUL;
3708   //   ulong t = u & 0xffffffffffUL;
3709   //   uint v = (e << 23) | (uint)(u >> 40);
3710   //   uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
3711   //   return as_float(v + r);
3712   // }
3713 
3714   auto Zero32 = MIRBuilder.buildConstant(S32, 0);
3715   auto Zero64 = MIRBuilder.buildConstant(S64, 0);
3716 
3717   auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
3718 
3719   auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
3720   auto Sub = MIRBuilder.buildSub(S32, K, LZ);
3721 
3722   auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
3723   auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
3724 
3725   auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
3726   auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
3727 
3728   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
3729 
3730   auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
3731   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
3732 
3733   auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
3734   auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
3735   auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
3736 
3737   auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
3738   auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
3739   auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
3740   auto One = MIRBuilder.buildConstant(S32, 1);
3741 
3742   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
3743   auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
3744   auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
3745   MIRBuilder.buildAdd(Dst, V, R);
3746 
3747   return Legalized;
3748 }
3749 
3750 LegalizerHelper::LegalizeResult
3751 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3752   Register Dst = MI.getOperand(0).getReg();
3753   Register Src = MI.getOperand(1).getReg();
3754   LLT DstTy = MRI.getType(Dst);
3755   LLT SrcTy = MRI.getType(Src);
3756 
3757   if (SrcTy != LLT::scalar(64))
3758     return UnableToLegalize;
3759 
3760   if (DstTy == LLT::scalar(32)) {
3761     // TODO: SelectionDAG has several alternative expansions to port which may
3762     // be more reasonble depending on the available instructions. If a target
3763     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
3764     // intermediate type, this is probably worse.
3765     return lowerU64ToF32BitOps(MI);
3766   }
3767 
3768   return UnableToLegalize;
3769 }
3770 
3771 LegalizerHelper::LegalizeResult
3772 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3773   Register Dst = MI.getOperand(0).getReg();
3774   Register Src = MI.getOperand(1).getReg();
3775   LLT DstTy = MRI.getType(Dst);
3776   LLT SrcTy = MRI.getType(Src);
3777 
3778   const LLT S64 = LLT::scalar(64);
3779   const LLT S32 = LLT::scalar(32);
3780   const LLT S1 = LLT::scalar(1);
3781 
3782   if (SrcTy != S64)
3783     return UnableToLegalize;
3784 
3785   if (DstTy == S32) {
3786     // signed cl2f(long l) {
3787     //   long s = l >> 63;
3788     //   float r = cul2f((l + s) ^ s);
3789     //   return s ? -r : r;
3790     // }
3791     Register L = Src;
3792     auto SignBit = MIRBuilder.buildConstant(S64, 63);
3793     auto S = MIRBuilder.buildAShr(S64, L, SignBit);
3794 
3795     auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
3796     auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
3797     auto R = MIRBuilder.buildUITOFP(S32, Xor);
3798 
3799     auto RNeg = MIRBuilder.buildFNeg(S32, R);
3800     auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
3801                                             MIRBuilder.buildConstant(S64, 0));
3802     MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
3803     return Legalized;
3804   }
3805 
3806   return UnableToLegalize;
3807 }
3808 
3809 LegalizerHelper::LegalizeResult
3810 LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3811   Register Dst = MI.getOperand(0).getReg();
3812   Register Src = MI.getOperand(1).getReg();
3813   LLT DstTy = MRI.getType(Dst);
3814   LLT SrcTy = MRI.getType(Src);
3815   const LLT S64 = LLT::scalar(64);
3816   const LLT S32 = LLT::scalar(32);
3817 
3818   if (SrcTy != S64 && SrcTy != S32)
3819     return UnableToLegalize;
3820   if (DstTy != S32 && DstTy != S64)
3821     return UnableToLegalize;
3822 
3823   // FPTOSI gives same result as FPTOUI for positive signed integers.
3824   // FPTOUI needs to deal with fp values that convert to unsigned integers
3825   // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp.
3826 
3827   APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits());
3828   APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle()
3829                                                 : APFloat::IEEEdouble(),
3830                     APInt::getNullValue(SrcTy.getSizeInBits()));
3831   TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven);
3832 
3833   MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src);
3834 
3835   MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP);
3836   // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on
3837   // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1.
3838   MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold);
3839   MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub);
3840   MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt);
3841   MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit);
3842 
3843   MachineInstrBuilder FCMP =
3844       MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, DstTy, Src, Threshold);
3845   MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res);
3846 
3847   MI.eraseFromParent();
3848   return Legalized;
3849 }
3850 
3851 static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
3852   switch (Opc) {
3853   case TargetOpcode::G_SMIN:
3854     return CmpInst::ICMP_SLT;
3855   case TargetOpcode::G_SMAX:
3856     return CmpInst::ICMP_SGT;
3857   case TargetOpcode::G_UMIN:
3858     return CmpInst::ICMP_ULT;
3859   case TargetOpcode::G_UMAX:
3860     return CmpInst::ICMP_UGT;
3861   default:
3862     llvm_unreachable("not in integer min/max");
3863   }
3864 }
3865 
3866 LegalizerHelper::LegalizeResult
3867 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3868   Register Dst = MI.getOperand(0).getReg();
3869   Register Src0 = MI.getOperand(1).getReg();
3870   Register Src1 = MI.getOperand(2).getReg();
3871 
3872   const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
3873   LLT CmpType = MRI.getType(Dst).changeElementSize(1);
3874 
3875   auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
3876   MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
3877 
3878   MI.eraseFromParent();
3879   return Legalized;
3880 }
3881 
3882 LegalizerHelper::LegalizeResult
3883 LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3884   Register Dst = MI.getOperand(0).getReg();
3885   Register Src0 = MI.getOperand(1).getReg();
3886   Register Src1 = MI.getOperand(2).getReg();
3887 
3888   const LLT Src0Ty = MRI.getType(Src0);
3889   const LLT Src1Ty = MRI.getType(Src1);
3890 
3891   const int Src0Size = Src0Ty.getScalarSizeInBits();
3892   const int Src1Size = Src1Ty.getScalarSizeInBits();
3893 
3894   auto SignBitMask = MIRBuilder.buildConstant(
3895     Src0Ty, APInt::getSignMask(Src0Size));
3896 
3897   auto NotSignBitMask = MIRBuilder.buildConstant(
3898     Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
3899 
3900   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
3901   MachineInstr *Or;
3902 
3903   if (Src0Ty == Src1Ty) {
3904     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
3905     Or = MIRBuilder.buildOr(Dst, And0, And1);
3906   } else if (Src0Size > Src1Size) {
3907     auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
3908     auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
3909     auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
3910     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
3911     Or = MIRBuilder.buildOr(Dst, And0, And1);
3912   } else {
3913     auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
3914     auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
3915     auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
3916     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
3917     Or = MIRBuilder.buildOr(Dst, And0, And1);
3918   }
3919 
3920   // Be careful about setting nsz/nnan/ninf on every instruction, since the
3921   // constants are a nan and -0.0, but the final result should preserve
3922   // everything.
3923   if (unsigned Flags = MI.getFlags())
3924     Or->setFlags(Flags);
3925 
3926   MI.eraseFromParent();
3927   return Legalized;
3928 }
3929 
3930 LegalizerHelper::LegalizeResult
3931 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
3932   unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ?
3933     TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE;
3934 
3935   Register Dst = MI.getOperand(0).getReg();
3936   Register Src0 = MI.getOperand(1).getReg();
3937   Register Src1 = MI.getOperand(2).getReg();
3938   LLT Ty = MRI.getType(Dst);
3939 
3940   if (!MI.getFlag(MachineInstr::FmNoNans)) {
3941     // Insert canonicalizes if it's possible we need to quiet to get correct
3942     // sNaN behavior.
3943 
3944     // Note this must be done here, and not as an optimization combine in the
3945     // absence of a dedicate quiet-snan instruction as we're using an
3946     // omni-purpose G_FCANONICALIZE.
3947     if (!isKnownNeverSNaN(Src0, MRI))
3948       Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0);
3949 
3950     if (!isKnownNeverSNaN(Src1, MRI))
3951       Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0);
3952   }
3953 
3954   // If there are no nans, it's safe to simply replace this with the non-IEEE
3955   // version.
3956   MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags());
3957   MI.eraseFromParent();
3958   return Legalized;
3959 }
3960 
3961 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) {
3962   // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c
3963   Register DstReg = MI.getOperand(0).getReg();
3964   LLT Ty = MRI.getType(DstReg);
3965   unsigned Flags = MI.getFlags();
3966 
3967   auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2),
3968                                   Flags);
3969   MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags);
3970   MI.eraseFromParent();
3971   return Legalized;
3972 }
3973 
3974 LegalizerHelper::LegalizeResult
3975 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
3976   const unsigned NumDst = MI.getNumOperands() - 1;
3977   const Register SrcReg = MI.getOperand(NumDst).getReg();
3978   LLT SrcTy = MRI.getType(SrcReg);
3979 
3980   Register Dst0Reg = MI.getOperand(0).getReg();
3981   LLT DstTy = MRI.getType(Dst0Reg);
3982 
3983 
3984   // Expand scalarizing unmerge as bitcast to integer and shift.
3985   if (!DstTy.isVector() && SrcTy.isVector() &&
3986       SrcTy.getElementType() == DstTy) {
3987     LLT IntTy = LLT::scalar(SrcTy.getSizeInBits());
3988     Register Cast = MIRBuilder.buildBitcast(IntTy, SrcReg).getReg(0);
3989 
3990     MIRBuilder.buildTrunc(Dst0Reg, Cast);
3991 
3992     const unsigned DstSize = DstTy.getSizeInBits();
3993     unsigned Offset = DstSize;
3994     for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
3995       auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
3996       auto Shift = MIRBuilder.buildLShr(IntTy, Cast, ShiftAmt);
3997       MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
3998     }
3999 
4000     MI.eraseFromParent();
4001     return Legalized;
4002   }
4003 
4004   return UnableToLegalize;
4005 }
4006 
4007 LegalizerHelper::LegalizeResult
4008 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
4009   Register DstReg = MI.getOperand(0).getReg();
4010   Register Src0Reg = MI.getOperand(1).getReg();
4011   Register Src1Reg = MI.getOperand(2).getReg();
4012   LLT Src0Ty = MRI.getType(Src0Reg);
4013   LLT DstTy = MRI.getType(DstReg);
4014   LLT IdxTy = LLT::scalar(32);
4015 
4016   const Constant *ShufMask = MI.getOperand(3).getShuffleMask();
4017 
4018   SmallVector<int, 32> Mask;
4019   ShuffleVectorInst::getShuffleMask(ShufMask, Mask);
4020 
4021   if (DstTy.isScalar()) {
4022     if (Src0Ty.isVector())
4023       return UnableToLegalize;
4024 
4025     // This is just a SELECT.
4026     assert(Mask.size() == 1 && "Expected a single mask element");
4027     Register Val;
4028     if (Mask[0] < 0 || Mask[0] > 1)
4029       Val = MIRBuilder.buildUndef(DstTy).getReg(0);
4030     else
4031       Val = Mask[0] == 0 ? Src0Reg : Src1Reg;
4032     MIRBuilder.buildCopy(DstReg, Val);
4033     MI.eraseFromParent();
4034     return Legalized;
4035   }
4036 
4037   Register Undef;
4038   SmallVector<Register, 32> BuildVec;
4039   LLT EltTy = DstTy.getElementType();
4040 
4041   for (int Idx : Mask) {
4042     if (Idx < 0) {
4043       if (!Undef.isValid())
4044         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);
4045       BuildVec.push_back(Undef);
4046       continue;
4047     }
4048 
4049     if (Src0Ty.isScalar()) {
4050       BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
4051     } else {
4052       int NumElts = Src0Ty.getNumElements();
4053       Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
4054       int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
4055       auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
4056       auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
4057       BuildVec.push_back(Extract.getReg(0));
4058     }
4059   }
4060 
4061   MIRBuilder.buildBuildVector(DstReg, BuildVec);
4062   MI.eraseFromParent();
4063   return Legalized;
4064 }
4065 
4066 LegalizerHelper::LegalizeResult
4067 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) {
4068   Register Dst = MI.getOperand(0).getReg();
4069   Register AllocSize = MI.getOperand(1).getReg();
4070   unsigned Align = MI.getOperand(2).getImm();
4071 
4072   const auto &MF = *MI.getMF();
4073   const auto &TLI = *MF.getSubtarget().getTargetLowering();
4074 
4075   LLT PtrTy = MRI.getType(Dst);
4076   LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
4077 
4078   Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
4079   auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg);
4080   SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp);
4081 
4082   // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't
4083   // have to generate an extra instruction to negate the alloc and then use
4084   // G_GEP to add the negative offset.
4085   auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize);
4086   if (Align) {
4087     APInt AlignMask(IntPtrTy.getSizeInBits(), Align, true);
4088     AlignMask.negate();
4089     auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask);
4090     Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst);
4091   }
4092 
4093   SPTmp = MIRBuilder.buildCast(PtrTy, Alloc);
4094   MIRBuilder.buildCopy(SPReg, SPTmp);
4095   MIRBuilder.buildCopy(Dst, SPTmp);
4096 
4097   MI.eraseFromParent();
4098   return Legalized;
4099 }
4100