1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file implements the LegalizerHelper class to legalize
11 /// individual instructions and the LegalizeMachineIR wrapper pass for the
12 /// primary legalization.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
17 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetLowering.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
24 
25 #include <sstream>
26 
27 #define DEBUG_TYPE "legalizer"
28 
29 using namespace llvm;
30 
31 LegalizerHelper::LegalizerHelper(MachineFunction &MF)
32     : MRI(MF.getRegInfo()), LI(*MF.getSubtarget().getLegalizerInfo()) {
33   MIRBuilder.setMF(MF);
34 }
35 
36 LegalizerHelper::LegalizeResult
37 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
38   DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
39 
40   auto Action = LI.getAction(MI, MRI);
41   switch (std::get<0>(Action)) {
42   case LegalizerInfo::Legal:
43     DEBUG(dbgs() << ".. Already legal\n");
44     return AlreadyLegal;
45   case LegalizerInfo::Libcall:
46     DEBUG(dbgs() << ".. Convert to libcall\n");
47     return libcall(MI);
48   case LegalizerInfo::NarrowScalar:
49     DEBUG(dbgs() << ".. Narrow scalar\n");
50     return narrowScalar(MI, std::get<1>(Action), std::get<2>(Action));
51   case LegalizerInfo::WidenScalar:
52     DEBUG(dbgs() << ".. Widen scalar\n");
53     return widenScalar(MI, std::get<1>(Action), std::get<2>(Action));
54   case LegalizerInfo::Lower:
55     DEBUG(dbgs() << ".. Lower\n");
56     return lower(MI, std::get<1>(Action), std::get<2>(Action));
57   case LegalizerInfo::FewerElements:
58     DEBUG(dbgs() << ".. Reduce number of elements\n");
59     return fewerElementsVector(MI, std::get<1>(Action), std::get<2>(Action));
60   case LegalizerInfo::Custom:
61     DEBUG(dbgs() << ".. Custom legalization\n");
62     return LI.legalizeCustom(MI, MRI, MIRBuilder) ? Legalized
63                                                   : UnableToLegalize;
64   default:
65     DEBUG(dbgs() << ".. Unable to legalize\n");
66     return UnableToLegalize;
67   }
68 }
69 
70 void LegalizerHelper::extractParts(unsigned Reg, LLT Ty, int NumParts,
71                                    SmallVectorImpl<unsigned> &VRegs) {
72   for (int i = 0; i < NumParts; ++i)
73     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
74   MIRBuilder.buildUnmerge(VRegs, Reg);
75 }
76 
77 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
78   switch (Opcode) {
79   case TargetOpcode::G_SDIV:
80     assert(Size == 32 && "Unsupported size");
81     return RTLIB::SDIV_I32;
82   case TargetOpcode::G_UDIV:
83     assert(Size == 32 && "Unsupported size");
84     return RTLIB::UDIV_I32;
85   case TargetOpcode::G_SREM:
86     assert(Size == 32 && "Unsupported size");
87     return RTLIB::SREM_I32;
88   case TargetOpcode::G_UREM:
89     assert(Size == 32 && "Unsupported size");
90     return RTLIB::UREM_I32;
91   case TargetOpcode::G_FADD:
92     assert((Size == 32 || Size == 64) && "Unsupported size");
93     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
94   case TargetOpcode::G_FREM:
95     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
96   case TargetOpcode::G_FPOW:
97     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
98   }
99   llvm_unreachable("Unknown libcall function");
100 }
101 
102 LegalizerHelper::LegalizeResult
103 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
104                     const CallLowering::ArgInfo &Result,
105                     ArrayRef<CallLowering::ArgInfo> Args) {
106   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
107   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
108   const char *Name = TLI.getLibcallName(Libcall);
109 
110   MIRBuilder.getMF().getFrameInfo().setHasCalls(true);
111   if (!CLI.lowerCall(MIRBuilder, TLI.getLibcallCallingConv(Libcall),
112                      MachineOperand::CreateES(Name), Result, Args))
113     return LegalizerHelper::UnableToLegalize;
114 
115   return LegalizerHelper::Legalized;
116 }
117 
118 static LegalizerHelper::LegalizeResult
119 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
120               Type *OpType) {
121   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
122   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
123                        {{MI.getOperand(1).getReg(), OpType},
124                         {MI.getOperand(2).getReg(), OpType}});
125 }
126 
127 LegalizerHelper::LegalizeResult
128 LegalizerHelper::libcall(MachineInstr &MI) {
129   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
130   unsigned Size = LLTy.getSizeInBits();
131   auto &Ctx = MIRBuilder.getMF().getFunction()->getContext();
132 
133   MIRBuilder.setInstr(MI);
134 
135   switch (MI.getOpcode()) {
136   default:
137     return UnableToLegalize;
138   case TargetOpcode::G_SDIV:
139   case TargetOpcode::G_UDIV:
140   case TargetOpcode::G_SREM:
141   case TargetOpcode::G_UREM: {
142     Type *HLTy = Type::getInt32Ty(Ctx);
143     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
144     if (Status != Legalized)
145       return Status;
146     break;
147   }
148   case TargetOpcode::G_FADD:
149   case TargetOpcode::G_FPOW:
150   case TargetOpcode::G_FREM: {
151     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
152     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
153     if (Status != Legalized)
154       return Status;
155     break;
156   }
157   }
158 
159   MI.eraseFromParent();
160   return Legalized;
161 }
162 
163 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
164                                                               unsigned TypeIdx,
165                                                               LLT NarrowTy) {
166   // FIXME: Don't know how to handle secondary types yet.
167   if (TypeIdx != 0 && MI.getOpcode() != TargetOpcode::G_EXTRACT)
168     return UnableToLegalize;
169 
170   MIRBuilder.setInstr(MI);
171 
172   switch (MI.getOpcode()) {
173   default:
174     return UnableToLegalize;
175   case TargetOpcode::G_IMPLICIT_DEF: {
176     int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
177                    NarrowTy.getSizeInBits();
178 
179     SmallVector<unsigned, 2> DstRegs;
180     for (int i = 0; i < NumParts; ++i) {
181       unsigned Dst = MRI.createGenericVirtualRegister(NarrowTy);
182       MIRBuilder.buildUndef(Dst);
183       DstRegs.push_back(Dst);
184     }
185     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
186     MI.eraseFromParent();
187     return Legalized;
188   }
189   case TargetOpcode::G_ADD: {
190     // Expand in terms of carry-setting/consuming G_ADDE instructions.
191     int NumParts = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() /
192                    NarrowTy.getSizeInBits();
193 
194     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
195     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
196     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
197 
198     unsigned CarryIn = MRI.createGenericVirtualRegister(LLT::scalar(1));
199     MIRBuilder.buildConstant(CarryIn, 0);
200 
201     for (int i = 0; i < NumParts; ++i) {
202       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
203       unsigned CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
204 
205       MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
206                             Src2Regs[i], CarryIn);
207 
208       DstRegs.push_back(DstReg);
209       CarryIn = CarryOut;
210     }
211     unsigned DstReg = MI.getOperand(0).getReg();
212     MIRBuilder.buildMerge(DstReg, DstRegs);
213     MI.eraseFromParent();
214     return Legalized;
215   }
216   case TargetOpcode::G_EXTRACT: {
217     if (TypeIdx != 1)
218       return UnableToLegalize;
219 
220     int64_t NarrowSize = NarrowTy.getSizeInBits();
221     int NumParts =
222         MRI.getType(MI.getOperand(1).getReg()).getSizeInBits() / NarrowSize;
223 
224     SmallVector<unsigned, 2> SrcRegs, DstRegs;
225     SmallVector<uint64_t, 2> Indexes;
226     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
227 
228     unsigned OpReg = MI.getOperand(0).getReg();
229     int64_t OpStart = MI.getOperand(2).getImm();
230     int64_t OpSize = MRI.getType(OpReg).getSizeInBits();
231     for (int i = 0; i < NumParts; ++i) {
232       unsigned SrcStart = i * NarrowSize;
233 
234       if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
235         // No part of the extract uses this subregister, ignore it.
236         continue;
237       } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
238         // The entire subregister is extracted, forward the value.
239         DstRegs.push_back(SrcRegs[i]);
240         continue;
241       }
242 
243       // OpSegStart is where this destination segment would start in OpReg if it
244       // extended infinitely in both directions.
245       int64_t ExtractOffset, SegSize;
246       if (OpStart < SrcStart) {
247         ExtractOffset = 0;
248         SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
249       } else {
250         ExtractOffset = OpStart - SrcStart;
251         SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
252       }
253 
254       unsigned SegReg = SrcRegs[i];
255       if (ExtractOffset != 0 || SegSize != NarrowSize) {
256         // A genuine extract is needed.
257         SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
258         MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
259       }
260 
261       DstRegs.push_back(SegReg);
262     }
263 
264     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
265     MI.eraseFromParent();
266     return Legalized;
267   }
268   case TargetOpcode::G_INSERT: {
269     if (TypeIdx != 0)
270       return UnableToLegalize;
271 
272     int64_t NarrowSize = NarrowTy.getSizeInBits();
273     int NumParts =
274         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
275 
276     SmallVector<unsigned, 2> SrcRegs, DstRegs;
277     SmallVector<uint64_t, 2> Indexes;
278     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
279 
280     unsigned OpReg = MI.getOperand(2).getReg();
281     int64_t OpStart = MI.getOperand(3).getImm();
282     int64_t OpSize = MRI.getType(OpReg).getSizeInBits();
283     for (int i = 0; i < NumParts; ++i) {
284       unsigned DstStart = i * NarrowSize;
285 
286       if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
287         // No part of the insert affects this subregister, forward the original.
288         DstRegs.push_back(SrcRegs[i]);
289         continue;
290       } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
291         // The entire subregister is defined by this insert, forward the new
292         // value.
293         DstRegs.push_back(OpReg);
294         continue;
295       }
296 
297       // OpSegStart is where this destination segment would start in OpReg if it
298       // extended infinitely in both directions.
299       int64_t ExtractOffset, InsertOffset, SegSize;
300       if (OpStart < DstStart) {
301         InsertOffset = 0;
302         ExtractOffset = DstStart - OpStart;
303         SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
304       } else {
305         InsertOffset = OpStart - DstStart;
306         ExtractOffset = 0;
307         SegSize =
308             std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
309       }
310 
311       unsigned SegReg = OpReg;
312       if (ExtractOffset != 0 || SegSize != OpSize) {
313         // A genuine extract is needed.
314         SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
315         MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
316       }
317 
318       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
319       MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
320       DstRegs.push_back(DstReg);
321     }
322 
323     assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
324     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
325     MI.eraseFromParent();
326     return Legalized;
327   }
328   case TargetOpcode::G_LOAD: {
329     unsigned NarrowSize = NarrowTy.getSizeInBits();
330     int NumParts =
331         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
332     LLT OffsetTy = LLT::scalar(
333         MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
334 
335     SmallVector<unsigned, 2> DstRegs;
336     for (int i = 0; i < NumParts; ++i) {
337       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
338       unsigned SrcReg = 0;
339       unsigned Adjustment = i * NarrowSize / 8;
340 
341       MIRBuilder.materializeGEP(SrcReg, MI.getOperand(1).getReg(), OffsetTy,
342                                 Adjustment);
343 
344       // TODO: This is conservatively correct, but we probably want to split the
345       // memory operands in the future.
346       MIRBuilder.buildLoad(DstReg, SrcReg, **MI.memoperands_begin());
347 
348       DstRegs.push_back(DstReg);
349     }
350     unsigned DstReg = MI.getOperand(0).getReg();
351     MIRBuilder.buildMerge(DstReg, DstRegs);
352     MI.eraseFromParent();
353     return Legalized;
354   }
355   case TargetOpcode::G_STORE: {
356     unsigned NarrowSize = NarrowTy.getSizeInBits();
357     int NumParts =
358         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
359     LLT OffsetTy = LLT::scalar(
360         MRI.getType(MI.getOperand(1).getReg()).getScalarSizeInBits());
361 
362     SmallVector<unsigned, 2> SrcRegs;
363     extractParts(MI.getOperand(0).getReg(), NarrowTy, NumParts, SrcRegs);
364 
365     for (int i = 0; i < NumParts; ++i) {
366       unsigned DstReg = 0;
367       unsigned Adjustment = i * NarrowSize / 8;
368 
369       MIRBuilder.materializeGEP(DstReg, MI.getOperand(1).getReg(), OffsetTy,
370                                 Adjustment);
371 
372       // TODO: This is conservatively correct, but we probably want to split the
373       // memory operands in the future.
374       MIRBuilder.buildStore(SrcRegs[i], DstReg, **MI.memoperands_begin());
375     }
376     MI.eraseFromParent();
377     return Legalized;
378   }
379   case TargetOpcode::G_CONSTANT: {
380     unsigned NarrowSize = NarrowTy.getSizeInBits();
381     int NumParts =
382         MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() / NarrowSize;
383     const APInt &Cst = MI.getOperand(1).getCImm()->getValue();
384     LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
385 
386     SmallVector<unsigned, 2> DstRegs;
387     for (int i = 0; i < NumParts; ++i) {
388       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
389       ConstantInt *CI =
390           ConstantInt::get(Ctx, Cst.lshr(NarrowSize * i).trunc(NarrowSize));
391       MIRBuilder.buildConstant(DstReg, *CI);
392       DstRegs.push_back(DstReg);
393     }
394     unsigned DstReg = MI.getOperand(0).getReg();
395     MIRBuilder.buildMerge(DstReg, DstRegs);
396     MI.eraseFromParent();
397     return Legalized;
398   }
399   }
400 }
401 
402 LegalizerHelper::LegalizeResult
403 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
404   MIRBuilder.setInstr(MI);
405 
406   switch (MI.getOpcode()) {
407   default:
408     return UnableToLegalize;
409   case TargetOpcode::G_ADD:
410   case TargetOpcode::G_AND:
411   case TargetOpcode::G_MUL:
412   case TargetOpcode::G_OR:
413   case TargetOpcode::G_XOR:
414   case TargetOpcode::G_SUB:
415   case TargetOpcode::G_SHL: {
416     // Perform operation at larger width (any extension is fine here, high bits
417     // don't affect the result) and then truncate the result back to the
418     // original type.
419     unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
420     unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
421     MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(1).getReg());
422     MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(2).getReg());
423 
424     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
425     MIRBuilder.buildInstr(MI.getOpcode())
426         .addDef(DstExt)
427         .addUse(Src1Ext)
428         .addUse(Src2Ext);
429 
430     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
431     MI.eraseFromParent();
432     return Legalized;
433   }
434   case TargetOpcode::G_SDIV:
435   case TargetOpcode::G_UDIV:
436   case TargetOpcode::G_ASHR:
437   case TargetOpcode::G_LSHR: {
438     unsigned ExtOp = MI.getOpcode() == TargetOpcode::G_SDIV ||
439                              MI.getOpcode() == TargetOpcode::G_ASHR
440                          ? TargetOpcode::G_SEXT
441                          : TargetOpcode::G_ZEXT;
442 
443     unsigned LHSExt = MRI.createGenericVirtualRegister(WideTy);
444     MIRBuilder.buildInstr(ExtOp).addDef(LHSExt).addUse(
445         MI.getOperand(1).getReg());
446 
447     unsigned RHSExt = MRI.createGenericVirtualRegister(WideTy);
448     MIRBuilder.buildInstr(ExtOp).addDef(RHSExt).addUse(
449         MI.getOperand(2).getReg());
450 
451     unsigned ResExt = MRI.createGenericVirtualRegister(WideTy);
452     MIRBuilder.buildInstr(MI.getOpcode())
453         .addDef(ResExt)
454         .addUse(LHSExt)
455         .addUse(RHSExt);
456 
457     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), ResExt);
458     MI.eraseFromParent();
459     return Legalized;
460   }
461   case TargetOpcode::G_SELECT: {
462     if (TypeIdx != 0)
463       return UnableToLegalize;
464 
465     // Perform operation at larger width (any extension is fine here, high bits
466     // don't affect the result) and then truncate the result back to the
467     // original type.
468     unsigned Src1Ext = MRI.createGenericVirtualRegister(WideTy);
469     unsigned Src2Ext = MRI.createGenericVirtualRegister(WideTy);
470     MIRBuilder.buildAnyExt(Src1Ext, MI.getOperand(2).getReg());
471     MIRBuilder.buildAnyExt(Src2Ext, MI.getOperand(3).getReg());
472 
473     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
474     MIRBuilder.buildInstr(TargetOpcode::G_SELECT)
475         .addDef(DstExt)
476         .addReg(MI.getOperand(1).getReg())
477         .addUse(Src1Ext)
478         .addUse(Src2Ext);
479 
480     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
481     MI.eraseFromParent();
482     return Legalized;
483   }
484   case TargetOpcode::G_FPTOSI:
485   case TargetOpcode::G_FPTOUI: {
486     if (TypeIdx != 0)
487       return UnableToLegalize;
488 
489     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
490     MIRBuilder.buildInstr(MI.getOpcode())
491         .addDef(DstExt)
492         .addUse(MI.getOperand(1).getReg());
493 
494     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
495     MI.eraseFromParent();
496     return Legalized;
497   }
498   case TargetOpcode::G_SITOFP:
499   case TargetOpcode::G_UITOFP: {
500     if (TypeIdx != 1)
501       return UnableToLegalize;
502 
503     unsigned Src = MI.getOperand(1).getReg();
504     unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
505 
506     if (MI.getOpcode() == TargetOpcode::G_SITOFP) {
507       MIRBuilder.buildSExt(SrcExt, Src);
508     } else {
509       assert(MI.getOpcode() == TargetOpcode::G_UITOFP && "Unexpected conv op");
510       MIRBuilder.buildZExt(SrcExt, Src);
511     }
512 
513     MIRBuilder.buildInstr(MI.getOpcode())
514         .addDef(MI.getOperand(0).getReg())
515         .addUse(SrcExt);
516 
517     MI.eraseFromParent();
518     return Legalized;
519   }
520   case TargetOpcode::G_INSERT: {
521     if (TypeIdx != 0)
522       return UnableToLegalize;
523 
524     unsigned Src = MI.getOperand(1).getReg();
525     unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
526     MIRBuilder.buildAnyExt(SrcExt, Src);
527 
528     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
529     auto MIB = MIRBuilder.buildInsert(DstExt, SrcExt, MI.getOperand(2).getReg(),
530                                       MI.getOperand(3).getImm());
531     for (unsigned OpNum = 4; OpNum < MI.getNumOperands(); OpNum += 2) {
532       MIB.addReg(MI.getOperand(OpNum).getReg());
533       MIB.addImm(MI.getOperand(OpNum + 1).getImm());
534     }
535 
536     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
537     MI.eraseFromParent();
538     return Legalized;
539   }
540   case TargetOpcode::G_LOAD: {
541     assert(alignTo(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits(), 8) ==
542                WideTy.getSizeInBits() &&
543            "illegal to increase number of bytes loaded");
544 
545     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
546     MIRBuilder.buildLoad(DstExt, MI.getOperand(1).getReg(),
547                          **MI.memoperands_begin());
548     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
549     MI.eraseFromParent();
550     return Legalized;
551   }
552   case TargetOpcode::G_STORE: {
553     if (MRI.getType(MI.getOperand(0).getReg()) != LLT::scalar(1) ||
554         WideTy != LLT::scalar(8))
555       return UnableToLegalize;
556 
557     auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
558     auto Content = TLI.getBooleanContents(false, false);
559 
560     unsigned ExtOp = TargetOpcode::G_ANYEXT;
561     if (Content == TargetLoweringBase::ZeroOrOneBooleanContent)
562       ExtOp = TargetOpcode::G_ZEXT;
563     else if (Content == TargetLoweringBase::ZeroOrNegativeOneBooleanContent)
564       ExtOp = TargetOpcode::G_SEXT;
565     else
566       ExtOp = TargetOpcode::G_ANYEXT;
567 
568     unsigned SrcExt = MRI.createGenericVirtualRegister(WideTy);
569     MIRBuilder.buildInstr(ExtOp).addDef(SrcExt).addUse(
570         MI.getOperand(0).getReg());
571     MIRBuilder.buildStore(SrcExt, MI.getOperand(1).getReg(),
572                           **MI.memoperands_begin());
573     MI.eraseFromParent();
574     return Legalized;
575   }
576   case TargetOpcode::G_CONSTANT: {
577     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
578     MIRBuilder.buildConstant(DstExt, *MI.getOperand(1).getCImm());
579     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), DstExt);
580     MI.eraseFromParent();
581     return Legalized;
582   }
583   case TargetOpcode::G_FCONSTANT: {
584     unsigned DstExt = MRI.createGenericVirtualRegister(WideTy);
585     MIRBuilder.buildFConstant(DstExt, *MI.getOperand(1).getFPImm());
586     MIRBuilder.buildFPTrunc(MI.getOperand(0).getReg(), DstExt);
587     MI.eraseFromParent();
588     return Legalized;
589   }
590   case TargetOpcode::G_BRCOND: {
591     unsigned TstExt = MRI.createGenericVirtualRegister(WideTy);
592     MIRBuilder.buildAnyExt(TstExt, MI.getOperand(0).getReg());
593     MIRBuilder.buildBrCond(TstExt, *MI.getOperand(1).getMBB());
594     MI.eraseFromParent();
595     return Legalized;
596   }
597   case TargetOpcode::G_ICMP: {
598     assert(TypeIdx == 1 && "unable to legalize predicate");
599     bool IsSigned = CmpInst::isSigned(
600         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()));
601     unsigned Op0Ext = MRI.createGenericVirtualRegister(WideTy);
602     unsigned Op1Ext = MRI.createGenericVirtualRegister(WideTy);
603     if (IsSigned) {
604       MIRBuilder.buildSExt(Op0Ext, MI.getOperand(2).getReg());
605       MIRBuilder.buildSExt(Op1Ext, MI.getOperand(3).getReg());
606     } else {
607       MIRBuilder.buildZExt(Op0Ext, MI.getOperand(2).getReg());
608       MIRBuilder.buildZExt(Op1Ext, MI.getOperand(3).getReg());
609     }
610     MIRBuilder.buildICmp(
611         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate()),
612         MI.getOperand(0).getReg(), Op0Ext, Op1Ext);
613     MI.eraseFromParent();
614     return Legalized;
615   }
616   case TargetOpcode::G_GEP: {
617     assert(TypeIdx == 1 && "unable to legalize pointer of GEP");
618     unsigned OffsetExt = MRI.createGenericVirtualRegister(WideTy);
619     MIRBuilder.buildSExt(OffsetExt, MI.getOperand(2).getReg());
620     MI.getOperand(2).setReg(OffsetExt);
621     return Legalized;
622   }
623   }
624 }
625 
626 LegalizerHelper::LegalizeResult
627 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
628   using namespace TargetOpcode;
629   MIRBuilder.setInstr(MI);
630 
631   switch(MI.getOpcode()) {
632   default:
633     return UnableToLegalize;
634   case TargetOpcode::G_SREM:
635   case TargetOpcode::G_UREM: {
636     unsigned QuotReg = MRI.createGenericVirtualRegister(Ty);
637     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
638         .addDef(QuotReg)
639         .addUse(MI.getOperand(1).getReg())
640         .addUse(MI.getOperand(2).getReg());
641 
642     unsigned ProdReg = MRI.createGenericVirtualRegister(Ty);
643     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
644     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
645                         ProdReg);
646     MI.eraseFromParent();
647     return Legalized;
648   }
649   case TargetOpcode::G_SMULO:
650   case TargetOpcode::G_UMULO: {
651     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
652     // result.
653     unsigned Res = MI.getOperand(0).getReg();
654     unsigned Overflow = MI.getOperand(1).getReg();
655     unsigned LHS = MI.getOperand(2).getReg();
656     unsigned RHS = MI.getOperand(3).getReg();
657 
658     MIRBuilder.buildMul(Res, LHS, RHS);
659 
660     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
661                           ? TargetOpcode::G_SMULH
662                           : TargetOpcode::G_UMULH;
663 
664     unsigned HiPart = MRI.createGenericVirtualRegister(Ty);
665     MIRBuilder.buildInstr(Opcode)
666       .addDef(HiPart)
667       .addUse(LHS)
668       .addUse(RHS);
669 
670     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
671     MIRBuilder.buildConstant(Zero, 0);
672     MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
673     MI.eraseFromParent();
674     return Legalized;
675   }
676   case TargetOpcode::G_FNEG: {
677     // TODO: Handle vector types once we are able to
678     // represent them.
679     if (Ty.isVector())
680       return UnableToLegalize;
681     unsigned Res = MI.getOperand(0).getReg();
682     Type *ZeroTy;
683     LLVMContext &Ctx = MIRBuilder.getMF().getFunction()->getContext();
684     switch (Ty.getSizeInBits()) {
685     case 16:
686       ZeroTy = Type::getHalfTy(Ctx);
687       break;
688     case 32:
689       ZeroTy = Type::getFloatTy(Ctx);
690       break;
691     case 64:
692       ZeroTy = Type::getDoubleTy(Ctx);
693       break;
694     default:
695       llvm_unreachable("unexpected floating-point type");
696     }
697     ConstantFP &ZeroForNegation =
698         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
699     unsigned Zero = MRI.createGenericVirtualRegister(Ty);
700     MIRBuilder.buildFConstant(Zero, ZeroForNegation);
701     MIRBuilder.buildInstr(TargetOpcode::G_FSUB)
702         .addDef(Res)
703         .addUse(Zero)
704         .addUse(MI.getOperand(1).getReg());
705     MI.eraseFromParent();
706     return Legalized;
707   }
708   case TargetOpcode::G_FSUB: {
709     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
710     // First, check if G_FNEG is marked as Lower. If so, we may
711     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
712     if (LI.getAction({G_FNEG, Ty}).first == LegalizerInfo::Lower)
713       return UnableToLegalize;
714     unsigned Res = MI.getOperand(0).getReg();
715     unsigned LHS = MI.getOperand(1).getReg();
716     unsigned RHS = MI.getOperand(2).getReg();
717     unsigned Neg = MRI.createGenericVirtualRegister(Ty);
718     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
719     MIRBuilder.buildInstr(TargetOpcode::G_FADD)
720         .addDef(Res)
721         .addUse(LHS)
722         .addUse(Neg);
723     MI.eraseFromParent();
724     return Legalized;
725   }
726   }
727 }
728 
729 LegalizerHelper::LegalizeResult
730 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
731                                      LLT NarrowTy) {
732   // FIXME: Don't know how to handle secondary types yet.
733   if (TypeIdx != 0)
734     return UnableToLegalize;
735   switch (MI.getOpcode()) {
736   default:
737     return UnableToLegalize;
738   case TargetOpcode::G_ADD: {
739     unsigned NarrowSize = NarrowTy.getSizeInBits();
740     unsigned DstReg = MI.getOperand(0).getReg();
741     int NumParts = MRI.getType(DstReg).getSizeInBits() / NarrowSize;
742 
743     MIRBuilder.setInstr(MI);
744 
745     SmallVector<unsigned, 2> Src1Regs, Src2Regs, DstRegs;
746     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
747     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
748 
749     for (int i = 0; i < NumParts; ++i) {
750       unsigned DstReg = MRI.createGenericVirtualRegister(NarrowTy);
751       MIRBuilder.buildAdd(DstReg, Src1Regs[i], Src2Regs[i]);
752       DstRegs.push_back(DstReg);
753     }
754 
755     MIRBuilder.buildMerge(DstReg, DstRegs);
756     MI.eraseFromParent();
757     return Legalized;
758   }
759   }
760 }
761