1 //===-- llvm/CodeGen/GlobalISel/LegalizerHelper.cpp -----------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 /// \file This file implements the LegalizerHelper class to legalize
10 /// individual instructions and the LegalizeMachineIR wrapper pass for the
11 /// primary legalization.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
18 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetFrameLowering.h"
21 #include "llvm/CodeGen/TargetInstrInfo.h"
22 #include "llvm/CodeGen/TargetLowering.h"
23 #include "llvm/CodeGen/TargetSubtargetInfo.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/raw_ostream.h"
27 
28 #define DEBUG_TYPE "legalizer"
29 
30 using namespace llvm;
31 using namespace LegalizeActions;
32 
33 /// Try to break down \p OrigTy into \p NarrowTy sized pieces.
34 ///
35 /// Returns the number of \p NarrowTy elements needed to reconstruct \p OrigTy,
36 /// with any leftover piece as type \p LeftoverTy
37 ///
38 /// Returns -1 in the first element of the pair if the breakdown is not
39 /// satisfiable.
40 static std::pair<int, int>
41 getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
42   assert(!LeftoverTy.isValid() && "this is an out argument");
43 
44   unsigned Size = OrigTy.getSizeInBits();
45   unsigned NarrowSize = NarrowTy.getSizeInBits();
46   unsigned NumParts = Size / NarrowSize;
47   unsigned LeftoverSize = Size - NumParts * NarrowSize;
48   assert(Size > NarrowSize);
49 
50   if (LeftoverSize == 0)
51     return {NumParts, 0};
52 
53   if (NarrowTy.isVector()) {
54     unsigned EltSize = OrigTy.getScalarSizeInBits();
55     if (LeftoverSize % EltSize != 0)
56       return {-1, -1};
57     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
58   } else {
59     LeftoverTy = LLT::scalar(LeftoverSize);
60   }
61 
62   int NumLeftover = LeftoverSize / LeftoverTy.getSizeInBits();
63   return std::make_pair(NumParts, NumLeftover);
64 }
65 
66 LegalizerHelper::LegalizerHelper(MachineFunction &MF,
67                                  GISelChangeObserver &Observer,
68                                  MachineIRBuilder &Builder)
69     : MIRBuilder(Builder), MRI(MF.getRegInfo()),
70       LI(*MF.getSubtarget().getLegalizerInfo()), Observer(Observer) {
71   MIRBuilder.setMF(MF);
72   MIRBuilder.setChangeObserver(Observer);
73 }
74 
75 LegalizerHelper::LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
76                                  GISelChangeObserver &Observer,
77                                  MachineIRBuilder &B)
78     : MIRBuilder(B), MRI(MF.getRegInfo()), LI(LI), Observer(Observer) {
79   MIRBuilder.setMF(MF);
80   MIRBuilder.setChangeObserver(Observer);
81 }
82 LegalizerHelper::LegalizeResult
83 LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
84   LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
85 
86   if (MI.getOpcode() == TargetOpcode::G_INTRINSIC ||
87       MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
88     return LI.legalizeIntrinsic(MI, MRI, MIRBuilder) ? Legalized
89                                                      : UnableToLegalize;
90   auto Step = LI.getAction(MI, MRI);
91   switch (Step.Action) {
92   case Legal:
93     LLVM_DEBUG(dbgs() << ".. Already legal\n");
94     return AlreadyLegal;
95   case Libcall:
96     LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
97     return libcall(MI);
98   case NarrowScalar:
99     LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
100     return narrowScalar(MI, Step.TypeIdx, Step.NewType);
101   case WidenScalar:
102     LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
103     return widenScalar(MI, Step.TypeIdx, Step.NewType);
104   case Lower:
105     LLVM_DEBUG(dbgs() << ".. Lower\n");
106     return lower(MI, Step.TypeIdx, Step.NewType);
107   case FewerElements:
108     LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
109     return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
110   case MoreElements:
111     LLVM_DEBUG(dbgs() << ".. Increase number of elements\n");
112     return moreElementsVector(MI, Step.TypeIdx, Step.NewType);
113   case Custom:
114     LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
115     return LI.legalizeCustom(MI, MRI, MIRBuilder, Observer) ? Legalized
116                                                             : UnableToLegalize;
117   default:
118     LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
119     return UnableToLegalize;
120   }
121 }
122 
123 void LegalizerHelper::extractParts(Register Reg, LLT Ty, int NumParts,
124                                    SmallVectorImpl<Register> &VRegs) {
125   for (int i = 0; i < NumParts; ++i)
126     VRegs.push_back(MRI.createGenericVirtualRegister(Ty));
127   MIRBuilder.buildUnmerge(VRegs, Reg);
128 }
129 
130 bool LegalizerHelper::extractParts(Register Reg, LLT RegTy,
131                                    LLT MainTy, LLT &LeftoverTy,
132                                    SmallVectorImpl<Register> &VRegs,
133                                    SmallVectorImpl<Register> &LeftoverRegs) {
134   assert(!LeftoverTy.isValid() && "this is an out argument");
135 
136   unsigned RegSize = RegTy.getSizeInBits();
137   unsigned MainSize = MainTy.getSizeInBits();
138   unsigned NumParts = RegSize / MainSize;
139   unsigned LeftoverSize = RegSize - NumParts * MainSize;
140 
141   // Use an unmerge when possible.
142   if (LeftoverSize == 0) {
143     for (unsigned I = 0; I < NumParts; ++I)
144       VRegs.push_back(MRI.createGenericVirtualRegister(MainTy));
145     MIRBuilder.buildUnmerge(VRegs, Reg);
146     return true;
147   }
148 
149   if (MainTy.isVector()) {
150     unsigned EltSize = MainTy.getScalarSizeInBits();
151     if (LeftoverSize % EltSize != 0)
152       return false;
153     LeftoverTy = LLT::scalarOrVector(LeftoverSize / EltSize, EltSize);
154   } else {
155     LeftoverTy = LLT::scalar(LeftoverSize);
156   }
157 
158   // For irregular sizes, extract the individual parts.
159   for (unsigned I = 0; I != NumParts; ++I) {
160     Register NewReg = MRI.createGenericVirtualRegister(MainTy);
161     VRegs.push_back(NewReg);
162     MIRBuilder.buildExtract(NewReg, Reg, MainSize * I);
163   }
164 
165   for (unsigned Offset = MainSize * NumParts; Offset < RegSize;
166        Offset += LeftoverSize) {
167     Register NewReg = MRI.createGenericVirtualRegister(LeftoverTy);
168     LeftoverRegs.push_back(NewReg);
169     MIRBuilder.buildExtract(NewReg, Reg, Offset);
170   }
171 
172   return true;
173 }
174 
175 static LLT getGCDType(LLT OrigTy, LLT TargetTy) {
176   if (OrigTy.isVector() && TargetTy.isVector()) {
177     assert(OrigTy.getElementType() == TargetTy.getElementType());
178     int GCD = greatestCommonDivisor(OrigTy.getNumElements(),
179                                     TargetTy.getNumElements());
180     return LLT::scalarOrVector(GCD, OrigTy.getElementType());
181   }
182 
183   if (OrigTy.isVector() && !TargetTy.isVector()) {
184     assert(OrigTy.getElementType() == TargetTy);
185     return TargetTy;
186   }
187 
188   assert(!OrigTy.isVector() && !TargetTy.isVector());
189 
190   int GCD = greatestCommonDivisor(OrigTy.getSizeInBits(),
191                                   TargetTy.getSizeInBits());
192   return LLT::scalar(GCD);
193 }
194 
195 void LegalizerHelper::insertParts(Register DstReg,
196                                   LLT ResultTy, LLT PartTy,
197                                   ArrayRef<Register> PartRegs,
198                                   LLT LeftoverTy,
199                                   ArrayRef<Register> LeftoverRegs) {
200   if (!LeftoverTy.isValid()) {
201     assert(LeftoverRegs.empty());
202 
203     if (!ResultTy.isVector()) {
204       MIRBuilder.buildMerge(DstReg, PartRegs);
205       return;
206     }
207 
208     if (PartTy.isVector())
209       MIRBuilder.buildConcatVectors(DstReg, PartRegs);
210     else
211       MIRBuilder.buildBuildVector(DstReg, PartRegs);
212     return;
213   }
214 
215   unsigned PartSize = PartTy.getSizeInBits();
216   unsigned LeftoverPartSize = LeftoverTy.getSizeInBits();
217 
218   Register CurResultReg = MRI.createGenericVirtualRegister(ResultTy);
219   MIRBuilder.buildUndef(CurResultReg);
220 
221   unsigned Offset = 0;
222   for (Register PartReg : PartRegs) {
223     Register NewResultReg = MRI.createGenericVirtualRegister(ResultTy);
224     MIRBuilder.buildInsert(NewResultReg, CurResultReg, PartReg, Offset);
225     CurResultReg = NewResultReg;
226     Offset += PartSize;
227   }
228 
229   for (unsigned I = 0, E = LeftoverRegs.size(); I != E; ++I) {
230     // Use the original output register for the final insert to avoid a copy.
231     Register NewResultReg = (I + 1 == E) ?
232       DstReg : MRI.createGenericVirtualRegister(ResultTy);
233 
234     MIRBuilder.buildInsert(NewResultReg, CurResultReg, LeftoverRegs[I], Offset);
235     CurResultReg = NewResultReg;
236     Offset += LeftoverPartSize;
237   }
238 }
239 
240 static RTLIB::Libcall getRTLibDesc(unsigned Opcode, unsigned Size) {
241   switch (Opcode) {
242   case TargetOpcode::G_SDIV:
243     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
244     switch (Size) {
245     case 32:
246       return RTLIB::SDIV_I32;
247     case 64:
248       return RTLIB::SDIV_I64;
249     case 128:
250       return RTLIB::SDIV_I128;
251     default:
252       llvm_unreachable("unexpected size");
253     }
254   case TargetOpcode::G_UDIV:
255     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
256     switch (Size) {
257     case 32:
258       return RTLIB::UDIV_I32;
259     case 64:
260       return RTLIB::UDIV_I64;
261     case 128:
262       return RTLIB::UDIV_I128;
263     default:
264       llvm_unreachable("unexpected size");
265     }
266   case TargetOpcode::G_SREM:
267     assert((Size == 32 || Size == 64) && "Unsupported size");
268     return Size == 64 ? RTLIB::SREM_I64 : RTLIB::SREM_I32;
269   case TargetOpcode::G_UREM:
270     assert((Size == 32 || Size == 64) && "Unsupported size");
271     return Size == 64 ? RTLIB::UREM_I64 : RTLIB::UREM_I32;
272   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
273     assert(Size == 32 && "Unsupported size");
274     return RTLIB::CTLZ_I32;
275   case TargetOpcode::G_FADD:
276     assert((Size == 32 || Size == 64) && "Unsupported size");
277     return Size == 64 ? RTLIB::ADD_F64 : RTLIB::ADD_F32;
278   case TargetOpcode::G_FSUB:
279     assert((Size == 32 || Size == 64) && "Unsupported size");
280     return Size == 64 ? RTLIB::SUB_F64 : RTLIB::SUB_F32;
281   case TargetOpcode::G_FMUL:
282     assert((Size == 32 || Size == 64) && "Unsupported size");
283     return Size == 64 ? RTLIB::MUL_F64 : RTLIB::MUL_F32;
284   case TargetOpcode::G_FDIV:
285     assert((Size == 32 || Size == 64) && "Unsupported size");
286     return Size == 64 ? RTLIB::DIV_F64 : RTLIB::DIV_F32;
287   case TargetOpcode::G_FEXP:
288     assert((Size == 32 || Size == 64) && "Unsupported size");
289     return Size == 64 ? RTLIB::EXP_F64 : RTLIB::EXP_F32;
290   case TargetOpcode::G_FEXP2:
291     assert((Size == 32 || Size == 64) && "Unsupported size");
292     return Size == 64 ? RTLIB::EXP2_F64 : RTLIB::EXP2_F32;
293   case TargetOpcode::G_FREM:
294     return Size == 64 ? RTLIB::REM_F64 : RTLIB::REM_F32;
295   case TargetOpcode::G_FPOW:
296     return Size == 64 ? RTLIB::POW_F64 : RTLIB::POW_F32;
297   case TargetOpcode::G_FMA:
298     assert((Size == 32 || Size == 64) && "Unsupported size");
299     return Size == 64 ? RTLIB::FMA_F64 : RTLIB::FMA_F32;
300   case TargetOpcode::G_FSIN:
301     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
302     return Size == 128 ? RTLIB::SIN_F128
303                        : Size == 64 ? RTLIB::SIN_F64 : RTLIB::SIN_F32;
304   case TargetOpcode::G_FCOS:
305     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
306     return Size == 128 ? RTLIB::COS_F128
307                        : Size == 64 ? RTLIB::COS_F64 : RTLIB::COS_F32;
308   case TargetOpcode::G_FLOG10:
309     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
310     return Size == 128 ? RTLIB::LOG10_F128
311                        : Size == 64 ? RTLIB::LOG10_F64 : RTLIB::LOG10_F32;
312   case TargetOpcode::G_FLOG:
313     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
314     return Size == 128 ? RTLIB::LOG_F128
315                        : Size == 64 ? RTLIB::LOG_F64 : RTLIB::LOG_F32;
316   case TargetOpcode::G_FLOG2:
317     assert((Size == 32 || Size == 64 || Size == 128) && "Unsupported size");
318     return Size == 128 ? RTLIB::LOG2_F128
319                        : Size == 64 ? RTLIB::LOG2_F64 : RTLIB::LOG2_F32;
320   case TargetOpcode::G_FCEIL:
321     assert((Size == 32 || Size == 64) && "Unsupported size");
322     return Size == 64 ? RTLIB::CEIL_F64 : RTLIB::CEIL_F32;
323   case TargetOpcode::G_FFLOOR:
324     assert((Size == 32 || Size == 64) && "Unsupported size");
325     return Size == 64 ? RTLIB::FLOOR_F64 : RTLIB::FLOOR_F32;
326   }
327   llvm_unreachable("Unknown libcall function");
328 }
329 
330 /// True if an instruction is in tail position in its caller. Intended for
331 /// legalizing libcalls as tail calls when possible.
332 static bool isLibCallInTailPosition(MachineInstr &MI) {
333   const Function &F = MI.getParent()->getParent()->getFunction();
334 
335   // Conservatively require the attributes of the call to match those of
336   // the return. Ignore NoAlias and NonNull because they don't affect the
337   // call sequence.
338   AttributeList CallerAttrs = F.getAttributes();
339   if (AttrBuilder(CallerAttrs, AttributeList::ReturnIndex)
340           .removeAttribute(Attribute::NoAlias)
341           .removeAttribute(Attribute::NonNull)
342           .hasAttributes())
343     return false;
344 
345   // It's not safe to eliminate the sign / zero extension of the return value.
346   if (CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::ZExt) ||
347       CallerAttrs.hasAttribute(AttributeList::ReturnIndex, Attribute::SExt))
348     return false;
349 
350   // Only tail call if the following instruction is a standard return.
351   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
352   MachineInstr *Next = MI.getNextNode();
353   if (!Next || TII.isTailCall(*Next) || !Next->isReturn())
354     return false;
355 
356   return true;
357 }
358 
359 LegalizerHelper::LegalizeResult
360 llvm::createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
361                     const CallLowering::ArgInfo &Result,
362                     ArrayRef<CallLowering::ArgInfo> Args) {
363   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
364   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
365   const char *Name = TLI.getLibcallName(Libcall);
366 
367   CallLowering::CallLoweringInfo Info;
368   Info.CallConv = TLI.getLibcallCallingConv(Libcall);
369   Info.Callee = MachineOperand::CreateES(Name);
370   Info.OrigRet = Result;
371   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
372   if (!CLI.lowerCall(MIRBuilder, Info))
373     return LegalizerHelper::UnableToLegalize;
374 
375   return LegalizerHelper::Legalized;
376 }
377 
378 // Useful for libcalls where all operands have the same type.
379 static LegalizerHelper::LegalizeResult
380 simpleLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, unsigned Size,
381               Type *OpType) {
382   auto Libcall = getRTLibDesc(MI.getOpcode(), Size);
383 
384   SmallVector<CallLowering::ArgInfo, 3> Args;
385   for (unsigned i = 1; i < MI.getNumOperands(); i++)
386     Args.push_back({MI.getOperand(i).getReg(), OpType});
387   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
388                        Args);
389 }
390 
391 LegalizerHelper::LegalizeResult
392 llvm::createMemLibcall(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
393                        MachineInstr &MI) {
394   assert(MI.getOpcode() == TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS);
395   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
396 
397   SmallVector<CallLowering::ArgInfo, 3> Args;
398   // Add all the args, except for the last which is an imm denoting 'tail'.
399   for (unsigned i = 1; i < MI.getNumOperands() - 1; i++) {
400     Register Reg = MI.getOperand(i).getReg();
401 
402     // Need derive an IR type for call lowering.
403     LLT OpLLT = MRI.getType(Reg);
404     Type *OpTy = nullptr;
405     if (OpLLT.isPointer())
406       OpTy = Type::getInt8PtrTy(Ctx, OpLLT.getAddressSpace());
407     else
408       OpTy = IntegerType::get(Ctx, OpLLT.getSizeInBits());
409     Args.push_back({Reg, OpTy});
410   }
411 
412   auto &CLI = *MIRBuilder.getMF().getSubtarget().getCallLowering();
413   auto &TLI = *MIRBuilder.getMF().getSubtarget().getTargetLowering();
414   Intrinsic::ID ID = MI.getOperand(0).getIntrinsicID();
415   RTLIB::Libcall RTLibcall;
416   switch (ID) {
417   case Intrinsic::memcpy:
418     RTLibcall = RTLIB::MEMCPY;
419     break;
420   case Intrinsic::memset:
421     RTLibcall = RTLIB::MEMSET;
422     break;
423   case Intrinsic::memmove:
424     RTLibcall = RTLIB::MEMMOVE;
425     break;
426   default:
427     return LegalizerHelper::UnableToLegalize;
428   }
429   const char *Name = TLI.getLibcallName(RTLibcall);
430 
431   MIRBuilder.setInstr(MI);
432 
433   CallLowering::CallLoweringInfo Info;
434   Info.CallConv = TLI.getLibcallCallingConv(RTLibcall);
435   Info.Callee = MachineOperand::CreateES(Name);
436   Info.OrigRet = CallLowering::ArgInfo({0}, Type::getVoidTy(Ctx));
437   Info.IsTailCall = MI.getOperand(MI.getNumOperands() - 1).getImm() == 1 &&
438                     isLibCallInTailPosition(MI);
439 
440   std::copy(Args.begin(), Args.end(), std::back_inserter(Info.OrigArgs));
441   if (!CLI.lowerCall(MIRBuilder, Info))
442     return LegalizerHelper::UnableToLegalize;
443 
444   if (Info.LoweredTailCall) {
445     assert(Info.IsTailCall && "Lowered tail call when it wasn't a tail call?");
446     // We must have a return following the call to get past
447     // isLibCallInTailPosition.
448     assert(MI.getNextNode() && MI.getNextNode()->isReturn() &&
449            "Expected instr following MI to be a return?");
450 
451     // We lowered a tail call, so the call is now the return from the block.
452     // Delete the old return.
453     MI.getNextNode()->eraseFromParent();
454   }
455 
456   return LegalizerHelper::Legalized;
457 }
458 
459 static RTLIB::Libcall getConvRTLibDesc(unsigned Opcode, Type *ToType,
460                                        Type *FromType) {
461   auto ToMVT = MVT::getVT(ToType);
462   auto FromMVT = MVT::getVT(FromType);
463 
464   switch (Opcode) {
465   case TargetOpcode::G_FPEXT:
466     return RTLIB::getFPEXT(FromMVT, ToMVT);
467   case TargetOpcode::G_FPTRUNC:
468     return RTLIB::getFPROUND(FromMVT, ToMVT);
469   case TargetOpcode::G_FPTOSI:
470     return RTLIB::getFPTOSINT(FromMVT, ToMVT);
471   case TargetOpcode::G_FPTOUI:
472     return RTLIB::getFPTOUINT(FromMVT, ToMVT);
473   case TargetOpcode::G_SITOFP:
474     return RTLIB::getSINTTOFP(FromMVT, ToMVT);
475   case TargetOpcode::G_UITOFP:
476     return RTLIB::getUINTTOFP(FromMVT, ToMVT);
477   }
478   llvm_unreachable("Unsupported libcall function");
479 }
480 
481 static LegalizerHelper::LegalizeResult
482 conversionLibcall(MachineInstr &MI, MachineIRBuilder &MIRBuilder, Type *ToType,
483                   Type *FromType) {
484   RTLIB::Libcall Libcall = getConvRTLibDesc(MI.getOpcode(), ToType, FromType);
485   return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
486                        {{MI.getOperand(1).getReg(), FromType}});
487 }
488 
489 LegalizerHelper::LegalizeResult
490 LegalizerHelper::libcall(MachineInstr &MI) {
491   LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
492   unsigned Size = LLTy.getSizeInBits();
493   auto &Ctx = MIRBuilder.getMF().getFunction().getContext();
494 
495   MIRBuilder.setInstr(MI);
496 
497   switch (MI.getOpcode()) {
498   default:
499     return UnableToLegalize;
500   case TargetOpcode::G_SDIV:
501   case TargetOpcode::G_UDIV:
502   case TargetOpcode::G_SREM:
503   case TargetOpcode::G_UREM:
504   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
505     Type *HLTy = IntegerType::get(Ctx, Size);
506     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
507     if (Status != Legalized)
508       return Status;
509     break;
510   }
511   case TargetOpcode::G_FADD:
512   case TargetOpcode::G_FSUB:
513   case TargetOpcode::G_FMUL:
514   case TargetOpcode::G_FDIV:
515   case TargetOpcode::G_FMA:
516   case TargetOpcode::G_FPOW:
517   case TargetOpcode::G_FREM:
518   case TargetOpcode::G_FCOS:
519   case TargetOpcode::G_FSIN:
520   case TargetOpcode::G_FLOG10:
521   case TargetOpcode::G_FLOG:
522   case TargetOpcode::G_FLOG2:
523   case TargetOpcode::G_FEXP:
524   case TargetOpcode::G_FEXP2:
525   case TargetOpcode::G_FCEIL:
526   case TargetOpcode::G_FFLOOR: {
527     if (Size > 64) {
528       LLVM_DEBUG(dbgs() << "Size " << Size << " too large to legalize.\n");
529       return UnableToLegalize;
530     }
531     Type *HLTy = Size == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx);
532     auto Status = simpleLibcall(MI, MIRBuilder, Size, HLTy);
533     if (Status != Legalized)
534       return Status;
535     break;
536   }
537   case TargetOpcode::G_FPEXT: {
538     // FIXME: Support other floating point types (half, fp128 etc)
539     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
540     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
541     if (ToSize != 64 || FromSize != 32)
542       return UnableToLegalize;
543     LegalizeResult Status = conversionLibcall(
544         MI, MIRBuilder, Type::getDoubleTy(Ctx), Type::getFloatTy(Ctx));
545     if (Status != Legalized)
546       return Status;
547     break;
548   }
549   case TargetOpcode::G_FPTRUNC: {
550     // FIXME: Support other floating point types (half, fp128 etc)
551     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
552     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
553     if (ToSize != 32 || FromSize != 64)
554       return UnableToLegalize;
555     LegalizeResult Status = conversionLibcall(
556         MI, MIRBuilder, Type::getFloatTy(Ctx), Type::getDoubleTy(Ctx));
557     if (Status != Legalized)
558       return Status;
559     break;
560   }
561   case TargetOpcode::G_FPTOSI:
562   case TargetOpcode::G_FPTOUI: {
563     // FIXME: Support other types
564     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
565     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
566     if ((ToSize != 32 && ToSize != 64) || (FromSize != 32 && FromSize != 64))
567       return UnableToLegalize;
568     LegalizeResult Status = conversionLibcall(
569         MI, MIRBuilder,
570         ToSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx),
571         FromSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx));
572     if (Status != Legalized)
573       return Status;
574     break;
575   }
576   case TargetOpcode::G_SITOFP:
577   case TargetOpcode::G_UITOFP: {
578     // FIXME: Support other types
579     unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
580     unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
581     if ((FromSize != 32 && FromSize != 64) || (ToSize != 32 && ToSize != 64))
582       return UnableToLegalize;
583     LegalizeResult Status = conversionLibcall(
584         MI, MIRBuilder,
585         ToSize == 64 ? Type::getDoubleTy(Ctx) : Type::getFloatTy(Ctx),
586         FromSize == 32 ? Type::getInt32Ty(Ctx) : Type::getInt64Ty(Ctx));
587     if (Status != Legalized)
588       return Status;
589     break;
590   }
591   }
592 
593   MI.eraseFromParent();
594   return Legalized;
595 }
596 
597 LegalizerHelper::LegalizeResult LegalizerHelper::narrowScalar(MachineInstr &MI,
598                                                               unsigned TypeIdx,
599                                                               LLT NarrowTy) {
600   MIRBuilder.setInstr(MI);
601 
602   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
603   uint64_t NarrowSize = NarrowTy.getSizeInBits();
604 
605   switch (MI.getOpcode()) {
606   default:
607     return UnableToLegalize;
608   case TargetOpcode::G_IMPLICIT_DEF: {
609     // FIXME: add support for when SizeOp0 isn't an exact multiple of
610     // NarrowSize.
611     if (SizeOp0 % NarrowSize != 0)
612       return UnableToLegalize;
613     int NumParts = SizeOp0 / NarrowSize;
614 
615     SmallVector<Register, 2> DstRegs;
616     for (int i = 0; i < NumParts; ++i)
617       DstRegs.push_back(
618           MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
619 
620     Register DstReg = MI.getOperand(0).getReg();
621     if(MRI.getType(DstReg).isVector())
622       MIRBuilder.buildBuildVector(DstReg, DstRegs);
623     else
624       MIRBuilder.buildMerge(DstReg, DstRegs);
625     MI.eraseFromParent();
626     return Legalized;
627   }
628   case TargetOpcode::G_CONSTANT: {
629     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
630     const APInt &Val = MI.getOperand(1).getCImm()->getValue();
631     unsigned TotalSize = Ty.getSizeInBits();
632     unsigned NarrowSize = NarrowTy.getSizeInBits();
633     int NumParts = TotalSize / NarrowSize;
634 
635     SmallVector<Register, 4> PartRegs;
636     for (int I = 0; I != NumParts; ++I) {
637       unsigned Offset = I * NarrowSize;
638       auto K = MIRBuilder.buildConstant(NarrowTy,
639                                         Val.lshr(Offset).trunc(NarrowSize));
640       PartRegs.push_back(K.getReg(0));
641     }
642 
643     LLT LeftoverTy;
644     unsigned LeftoverBits = TotalSize - NumParts * NarrowSize;
645     SmallVector<Register, 1> LeftoverRegs;
646     if (LeftoverBits != 0) {
647       LeftoverTy = LLT::scalar(LeftoverBits);
648       auto K = MIRBuilder.buildConstant(
649         LeftoverTy,
650         Val.lshr(NumParts * NarrowSize).trunc(LeftoverBits));
651       LeftoverRegs.push_back(K.getReg(0));
652     }
653 
654     insertParts(MI.getOperand(0).getReg(),
655                 Ty, NarrowTy, PartRegs, LeftoverTy, LeftoverRegs);
656 
657     MI.eraseFromParent();
658     return Legalized;
659   }
660   case TargetOpcode::G_SEXT: {
661     if (TypeIdx != 0)
662       return UnableToLegalize;
663 
664     Register SrcReg = MI.getOperand(1).getReg();
665     LLT SrcTy = MRI.getType(SrcReg);
666 
667     // FIXME: support the general case where the requested NarrowTy may not be
668     // the same as the source type. E.g. s128 = sext(s32)
669     if ((SrcTy.getSizeInBits() != SizeOp0 / 2) ||
670         SrcTy.getSizeInBits() != NarrowTy.getSizeInBits()) {
671       LLVM_DEBUG(dbgs() << "Can't narrow sext to type " << NarrowTy << "\n");
672       return UnableToLegalize;
673     }
674 
675     // Shift the sign bit of the low register through the high register.
676     auto ShiftAmt =
677         MIRBuilder.buildConstant(LLT::scalar(64), NarrowTy.getSizeInBits() - 1);
678     auto Shift = MIRBuilder.buildAShr(NarrowTy, SrcReg, ShiftAmt);
679     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)});
680     MI.eraseFromParent();
681     return Legalized;
682   }
683   case TargetOpcode::G_ZEXT:
684   case TargetOpcode::G_ANYEXT: {
685     if (TypeIdx != 0)
686       return UnableToLegalize;
687 
688     LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
689     uint64_t SizeOp1 = SrcTy.getSizeInBits();
690     if (SizeOp0 % SizeOp1 != 0)
691       return UnableToLegalize;
692 
693     Register PadReg;
694     if (MI.getOpcode() == TargetOpcode::G_ZEXT)
695       PadReg = MIRBuilder.buildConstant(SrcTy, 0).getReg(0);
696     else
697       PadReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
698 
699     // Generate a merge where the bottom bits are taken from the source, and
700     // zero/impdef everything else.
701     unsigned NumParts = SizeOp0 / SizeOp1;
702     SmallVector<Register, 4> Srcs = {MI.getOperand(1).getReg()};
703     for (unsigned Part = 1; Part < NumParts; ++Part)
704       Srcs.push_back(PadReg);
705     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs);
706     MI.eraseFromParent();
707     return Legalized;
708   }
709   case TargetOpcode::G_TRUNC: {
710     if (TypeIdx != 1)
711       return UnableToLegalize;
712 
713     uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
714     if (NarrowTy.getSizeInBits() * 2 != SizeOp1) {
715       LLVM_DEBUG(dbgs() << "Can't narrow trunc to type " << NarrowTy << "\n");
716       return UnableToLegalize;
717     }
718 
719     auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg());
720     MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0));
721     MI.eraseFromParent();
722     return Legalized;
723   }
724 
725   case TargetOpcode::G_ADD: {
726     // FIXME: add support for when SizeOp0 isn't an exact multiple of
727     // NarrowSize.
728     if (SizeOp0 % NarrowSize != 0)
729       return UnableToLegalize;
730     // Expand in terms of carry-setting/consuming G_ADDE instructions.
731     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
732 
733     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
734     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
735     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
736 
737     Register CarryIn;
738     for (int i = 0; i < NumParts; ++i) {
739       Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
740       Register CarryOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
741 
742       if (i == 0)
743         MIRBuilder.buildUAddo(DstReg, CarryOut, Src1Regs[i], Src2Regs[i]);
744       else {
745         MIRBuilder.buildUAdde(DstReg, CarryOut, Src1Regs[i],
746                               Src2Regs[i], CarryIn);
747       }
748 
749       DstRegs.push_back(DstReg);
750       CarryIn = CarryOut;
751     }
752     Register DstReg = MI.getOperand(0).getReg();
753     if(MRI.getType(DstReg).isVector())
754       MIRBuilder.buildBuildVector(DstReg, DstRegs);
755     else
756       MIRBuilder.buildMerge(DstReg, DstRegs);
757     MI.eraseFromParent();
758     return Legalized;
759   }
760   case TargetOpcode::G_SUB: {
761     // FIXME: add support for when SizeOp0 isn't an exact multiple of
762     // NarrowSize.
763     if (SizeOp0 % NarrowSize != 0)
764       return UnableToLegalize;
765 
766     int NumParts = SizeOp0 / NarrowTy.getSizeInBits();
767 
768     SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
769     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
770     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
771 
772     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
773     Register BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
774     MIRBuilder.buildInstr(TargetOpcode::G_USUBO, {DstReg, BorrowOut},
775                           {Src1Regs[0], Src2Regs[0]});
776     DstRegs.push_back(DstReg);
777     Register BorrowIn = BorrowOut;
778     for (int i = 1; i < NumParts; ++i) {
779       DstReg = MRI.createGenericVirtualRegister(NarrowTy);
780       BorrowOut = MRI.createGenericVirtualRegister(LLT::scalar(1));
781 
782       MIRBuilder.buildInstr(TargetOpcode::G_USUBE, {DstReg, BorrowOut},
783                             {Src1Regs[i], Src2Regs[i], BorrowIn});
784 
785       DstRegs.push_back(DstReg);
786       BorrowIn = BorrowOut;
787     }
788     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
789     MI.eraseFromParent();
790     return Legalized;
791   }
792   case TargetOpcode::G_MUL:
793   case TargetOpcode::G_UMULH:
794     return narrowScalarMul(MI, NarrowTy);
795   case TargetOpcode::G_EXTRACT:
796     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
797   case TargetOpcode::G_INSERT:
798     return narrowScalarInsert(MI, TypeIdx, NarrowTy);
799   case TargetOpcode::G_LOAD: {
800     const auto &MMO = **MI.memoperands_begin();
801     Register DstReg = MI.getOperand(0).getReg();
802     LLT DstTy = MRI.getType(DstReg);
803     if (DstTy.isVector())
804       return UnableToLegalize;
805 
806     if (8 * MMO.getSize() != DstTy.getSizeInBits()) {
807       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
808       auto &MMO = **MI.memoperands_begin();
809       MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
810       MIRBuilder.buildAnyExt(DstReg, TmpReg);
811       MI.eraseFromParent();
812       return Legalized;
813     }
814 
815     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
816   }
817   case TargetOpcode::G_ZEXTLOAD:
818   case TargetOpcode::G_SEXTLOAD: {
819     bool ZExt = MI.getOpcode() == TargetOpcode::G_ZEXTLOAD;
820     Register DstReg = MI.getOperand(0).getReg();
821     Register PtrReg = MI.getOperand(1).getReg();
822 
823     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
824     auto &MMO = **MI.memoperands_begin();
825     if (MMO.getSizeInBits() == NarrowSize) {
826       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
827     } else {
828       unsigned ExtLoad = ZExt ? TargetOpcode::G_ZEXTLOAD
829         : TargetOpcode::G_SEXTLOAD;
830       MIRBuilder.buildInstr(ExtLoad)
831         .addDef(TmpReg)
832         .addUse(PtrReg)
833         .addMemOperand(&MMO);
834     }
835 
836     if (ZExt)
837       MIRBuilder.buildZExt(DstReg, TmpReg);
838     else
839       MIRBuilder.buildSExt(DstReg, TmpReg);
840 
841     MI.eraseFromParent();
842     return Legalized;
843   }
844   case TargetOpcode::G_STORE: {
845     const auto &MMO = **MI.memoperands_begin();
846 
847     Register SrcReg = MI.getOperand(0).getReg();
848     LLT SrcTy = MRI.getType(SrcReg);
849     if (SrcTy.isVector())
850       return UnableToLegalize;
851 
852     int NumParts = SizeOp0 / NarrowSize;
853     unsigned HandledSize = NumParts * NarrowTy.getSizeInBits();
854     unsigned LeftoverBits = SrcTy.getSizeInBits() - HandledSize;
855     if (SrcTy.isVector() && LeftoverBits != 0)
856       return UnableToLegalize;
857 
858     if (8 * MMO.getSize() != SrcTy.getSizeInBits()) {
859       Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
860       auto &MMO = **MI.memoperands_begin();
861       MIRBuilder.buildTrunc(TmpReg, SrcReg);
862       MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
863       MI.eraseFromParent();
864       return Legalized;
865     }
866 
867     return reduceLoadStoreWidth(MI, 0, NarrowTy);
868   }
869   case TargetOpcode::G_SELECT:
870     return narrowScalarSelect(MI, TypeIdx, NarrowTy);
871   case TargetOpcode::G_AND:
872   case TargetOpcode::G_OR:
873   case TargetOpcode::G_XOR: {
874     // Legalize bitwise operation:
875     // A = BinOp<Ty> B, C
876     // into:
877     // B1, ..., BN = G_UNMERGE_VALUES B
878     // C1, ..., CN = G_UNMERGE_VALUES C
879     // A1 = BinOp<Ty/N> B1, C2
880     // ...
881     // AN = BinOp<Ty/N> BN, CN
882     // A = G_MERGE_VALUES A1, ..., AN
883     return narrowScalarBasic(MI, TypeIdx, NarrowTy);
884   }
885   case TargetOpcode::G_SHL:
886   case TargetOpcode::G_LSHR:
887   case TargetOpcode::G_ASHR:
888     return narrowScalarShift(MI, TypeIdx, NarrowTy);
889   case TargetOpcode::G_CTLZ:
890   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
891   case TargetOpcode::G_CTTZ:
892   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
893   case TargetOpcode::G_CTPOP:
894     if (TypeIdx != 0)
895       return UnableToLegalize; // TODO
896 
897     Observer.changingInstr(MI);
898     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
899     Observer.changedInstr(MI);
900     return Legalized;
901   case TargetOpcode::G_INTTOPTR:
902     if (TypeIdx != 1)
903       return UnableToLegalize;
904 
905     Observer.changingInstr(MI);
906     narrowScalarSrc(MI, NarrowTy, 1);
907     Observer.changedInstr(MI);
908     return Legalized;
909   case TargetOpcode::G_PTRTOINT:
910     if (TypeIdx != 0)
911       return UnableToLegalize;
912 
913     Observer.changingInstr(MI);
914     narrowScalarDst(MI, NarrowTy, 0, TargetOpcode::G_ZEXT);
915     Observer.changedInstr(MI);
916     return Legalized;
917   case TargetOpcode::G_PHI: {
918     unsigned NumParts = SizeOp0 / NarrowSize;
919     SmallVector<Register, 2> DstRegs;
920     SmallVector<SmallVector<Register, 2>, 2> SrcRegs;
921     DstRegs.resize(NumParts);
922     SrcRegs.resize(MI.getNumOperands() / 2);
923     Observer.changingInstr(MI);
924     for (unsigned i = 1; i < MI.getNumOperands(); i += 2) {
925       MachineBasicBlock &OpMBB = *MI.getOperand(i + 1).getMBB();
926       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
927       extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
928                    SrcRegs[i / 2]);
929     }
930     MachineBasicBlock &MBB = *MI.getParent();
931     MIRBuilder.setInsertPt(MBB, MI);
932     for (unsigned i = 0; i < NumParts; ++i) {
933       DstRegs[i] = MRI.createGenericVirtualRegister(NarrowTy);
934       MachineInstrBuilder MIB =
935           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
936       for (unsigned j = 1; j < MI.getNumOperands(); j += 2)
937         MIB.addUse(SrcRegs[j / 2][i]).add(MI.getOperand(j + 1));
938     }
939     MIRBuilder.setInsertPt(MBB, MBB.getFirstNonPHI());
940     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
941     Observer.changedInstr(MI);
942     MI.eraseFromParent();
943     return Legalized;
944   }
945   case TargetOpcode::G_EXTRACT_VECTOR_ELT:
946   case TargetOpcode::G_INSERT_VECTOR_ELT: {
947     if (TypeIdx != 2)
948       return UnableToLegalize;
949 
950     int OpIdx = MI.getOpcode() == TargetOpcode::G_EXTRACT_VECTOR_ELT ? 2 : 3;
951     Observer.changingInstr(MI);
952     narrowScalarSrc(MI, NarrowTy, OpIdx);
953     Observer.changedInstr(MI);
954     return Legalized;
955   }
956   case TargetOpcode::G_ICMP: {
957     uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
958     if (NarrowSize * 2 != SrcSize)
959       return UnableToLegalize;
960 
961     Observer.changingInstr(MI);
962     Register LHSL = MRI.createGenericVirtualRegister(NarrowTy);
963     Register LHSH = MRI.createGenericVirtualRegister(NarrowTy);
964     MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg());
965 
966     Register RHSL = MRI.createGenericVirtualRegister(NarrowTy);
967     Register RHSH = MRI.createGenericVirtualRegister(NarrowTy);
968     MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg());
969 
970     CmpInst::Predicate Pred =
971         static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
972     LLT ResTy = MRI.getType(MI.getOperand(0).getReg());
973 
974     if (Pred == CmpInst::ICMP_EQ || Pred == CmpInst::ICMP_NE) {
975       MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
976       MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
977       MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
978       MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
979       MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero);
980     } else {
981       MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
982       MachineInstrBuilder CmpHEQ =
983           MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, ResTy, LHSH, RHSH);
984       MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
985           ICmpInst::getUnsignedPredicate(Pred), ResTy, LHSL, RHSL);
986       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH);
987     }
988     Observer.changedInstr(MI);
989     MI.eraseFromParent();
990     return Legalized;
991   }
992   case TargetOpcode::G_SEXT_INREG: {
993     if (TypeIdx != 0)
994       return UnableToLegalize;
995 
996     if (!MI.getOperand(2).isImm())
997       return UnableToLegalize;
998     int64_t SizeInBits = MI.getOperand(2).getImm();
999 
1000     // So long as the new type has more bits than the bits we're extending we
1001     // don't need to break it apart.
1002     if (NarrowTy.getScalarSizeInBits() >= SizeInBits) {
1003       Observer.changingInstr(MI);
1004       // We don't lose any non-extension bits by truncating the src and
1005       // sign-extending the dst.
1006       MachineOperand &MO1 = MI.getOperand(1);
1007       auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1.getReg());
1008       MO1.setReg(TruncMIB->getOperand(0).getReg());
1009 
1010       MachineOperand &MO2 = MI.getOperand(0);
1011       Register DstExt = MRI.createGenericVirtualRegister(NarrowTy);
1012       MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1013       MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt});
1014       MO2.setReg(DstExt);
1015       Observer.changedInstr(MI);
1016       return Legalized;
1017     }
1018 
1019     // Break it apart. Components below the extension point are unmodified. The
1020     // component containing the extension point becomes a narrower SEXT_INREG.
1021     // Components above it are ashr'd from the component containing the
1022     // extension point.
1023     if (SizeOp0 % NarrowSize != 0)
1024       return UnableToLegalize;
1025     int NumParts = SizeOp0 / NarrowSize;
1026 
1027     // List the registers where the destination will be scattered.
1028     SmallVector<Register, 2> DstRegs;
1029     // List the registers where the source will be split.
1030     SmallVector<Register, 2> SrcRegs;
1031 
1032     // Create all the temporary registers.
1033     for (int i = 0; i < NumParts; ++i) {
1034       Register SrcReg = MRI.createGenericVirtualRegister(NarrowTy);
1035 
1036       SrcRegs.push_back(SrcReg);
1037     }
1038 
1039     // Explode the big arguments into smaller chunks.
1040     MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg());
1041 
1042     Register AshrCstReg =
1043         MIRBuilder.buildConstant(NarrowTy, NarrowTy.getScalarSizeInBits() - 1)
1044             ->getOperand(0)
1045             .getReg();
1046     Register FullExtensionReg = 0;
1047     Register PartialExtensionReg = 0;
1048 
1049     // Do the operation on each small part.
1050     for (int i = 0; i < NumParts; ++i) {
1051       if ((i + 1) * NarrowTy.getScalarSizeInBits() < SizeInBits)
1052         DstRegs.push_back(SrcRegs[i]);
1053       else if (i * NarrowTy.getScalarSizeInBits() > SizeInBits) {
1054         assert(PartialExtensionReg &&
1055                "Expected to visit partial extension before full");
1056         if (FullExtensionReg) {
1057           DstRegs.push_back(FullExtensionReg);
1058           continue;
1059         }
1060         DstRegs.push_back(MIRBuilder
1061                               .buildInstr(TargetOpcode::G_ASHR, {NarrowTy},
1062                                           {PartialExtensionReg, AshrCstReg})
1063                               ->getOperand(0)
1064                               .getReg());
1065         FullExtensionReg = DstRegs.back();
1066       } else {
1067         DstRegs.push_back(
1068             MIRBuilder
1069                 .buildInstr(
1070                     TargetOpcode::G_SEXT_INREG, {NarrowTy},
1071                     {SrcRegs[i], SizeInBits % NarrowTy.getScalarSizeInBits()})
1072                 ->getOperand(0)
1073                 .getReg());
1074         PartialExtensionReg = DstRegs.back();
1075       }
1076     }
1077 
1078     // Gather the destination registers into the final destination.
1079     Register DstReg = MI.getOperand(0).getReg();
1080     MIRBuilder.buildMerge(DstReg, DstRegs);
1081     MI.eraseFromParent();
1082     return Legalized;
1083   }
1084   case TargetOpcode::G_BSWAP:
1085   case TargetOpcode::G_BITREVERSE: {
1086     if (SizeOp0 % NarrowSize != 0)
1087       return UnableToLegalize;
1088 
1089     Observer.changingInstr(MI);
1090     SmallVector<Register, 2> SrcRegs, DstRegs;
1091     unsigned NumParts = SizeOp0 / NarrowSize;
1092     extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
1093 
1094     for (unsigned i = 0; i < NumParts; ++i) {
1095       auto DstPart = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
1096                                            {SrcRegs[NumParts - 1 - i]});
1097       DstRegs.push_back(DstPart.getReg(0));
1098     }
1099 
1100     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
1101 
1102     Observer.changedInstr(MI);
1103     MI.eraseFromParent();
1104     return Legalized;
1105   }
1106   }
1107 }
1108 
1109 void LegalizerHelper::widenScalarSrc(MachineInstr &MI, LLT WideTy,
1110                                      unsigned OpIdx, unsigned ExtOpcode) {
1111   MachineOperand &MO = MI.getOperand(OpIdx);
1112   auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
1113   MO.setReg(ExtB->getOperand(0).getReg());
1114 }
1115 
1116 void LegalizerHelper::narrowScalarSrc(MachineInstr &MI, LLT NarrowTy,
1117                                       unsigned OpIdx) {
1118   MachineOperand &MO = MI.getOperand(OpIdx);
1119   auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
1120                                     {MO.getReg()});
1121   MO.setReg(ExtB->getOperand(0).getReg());
1122 }
1123 
1124 void LegalizerHelper::widenScalarDst(MachineInstr &MI, LLT WideTy,
1125                                      unsigned OpIdx, unsigned TruncOpcode) {
1126   MachineOperand &MO = MI.getOperand(OpIdx);
1127   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1128   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1129   MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
1130   MO.setReg(DstExt);
1131 }
1132 
1133 void LegalizerHelper::narrowScalarDst(MachineInstr &MI, LLT NarrowTy,
1134                                       unsigned OpIdx, unsigned ExtOpcode) {
1135   MachineOperand &MO = MI.getOperand(OpIdx);
1136   Register DstTrunc = MRI.createGenericVirtualRegister(NarrowTy);
1137   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1138   MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
1139   MO.setReg(DstTrunc);
1140 }
1141 
1142 void LegalizerHelper::moreElementsVectorDst(MachineInstr &MI, LLT WideTy,
1143                                             unsigned OpIdx) {
1144   MachineOperand &MO = MI.getOperand(OpIdx);
1145   Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1146   MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1147   MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
1148   MO.setReg(DstExt);
1149 }
1150 
1151 void LegalizerHelper::moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy,
1152                                             unsigned OpIdx) {
1153   MachineOperand &MO = MI.getOperand(OpIdx);
1154 
1155   LLT OldTy = MRI.getType(MO.getReg());
1156   unsigned OldElts = OldTy.getNumElements();
1157   unsigned NewElts = MoreTy.getNumElements();
1158 
1159   unsigned NumParts = NewElts / OldElts;
1160 
1161   // Use concat_vectors if the result is a multiple of the number of elements.
1162   if (NumParts * OldElts == NewElts) {
1163     SmallVector<Register, 8> Parts;
1164     Parts.push_back(MO.getReg());
1165 
1166     Register ImpDef = MIRBuilder.buildUndef(OldTy).getReg(0);
1167     for (unsigned I = 1; I != NumParts; ++I)
1168       Parts.push_back(ImpDef);
1169 
1170     auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
1171     MO.setReg(Concat.getReg(0));
1172     return;
1173   }
1174 
1175   Register MoreReg = MRI.createGenericVirtualRegister(MoreTy);
1176   Register ImpDef = MIRBuilder.buildUndef(MoreTy).getReg(0);
1177   MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
1178   MO.setReg(MoreReg);
1179 }
1180 
1181 LegalizerHelper::LegalizeResult
1182 LegalizerHelper::widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx,
1183                                         LLT WideTy) {
1184   if (TypeIdx != 1)
1185     return UnableToLegalize;
1186 
1187   Register DstReg = MI.getOperand(0).getReg();
1188   LLT DstTy = MRI.getType(DstReg);
1189   if (DstTy.isVector())
1190     return UnableToLegalize;
1191 
1192   Register Src1 = MI.getOperand(1).getReg();
1193   LLT SrcTy = MRI.getType(Src1);
1194   const int DstSize = DstTy.getSizeInBits();
1195   const int SrcSize = SrcTy.getSizeInBits();
1196   const int WideSize = WideTy.getSizeInBits();
1197   const int NumMerge = (DstSize + WideSize - 1) / WideSize;
1198 
1199   unsigned NumOps = MI.getNumOperands();
1200   unsigned NumSrc = MI.getNumOperands() - 1;
1201   unsigned PartSize = DstTy.getSizeInBits() / NumSrc;
1202 
1203   if (WideSize >= DstSize) {
1204     // Directly pack the bits in the target type.
1205     Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1).getReg(0);
1206 
1207     for (unsigned I = 2; I != NumOps; ++I) {
1208       const unsigned Offset = (I - 1) * PartSize;
1209 
1210       Register SrcReg = MI.getOperand(I).getReg();
1211       assert(MRI.getType(SrcReg) == LLT::scalar(PartSize));
1212 
1213       auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
1214 
1215       Register NextResult = I + 1 == NumOps && WideTy == DstTy ? DstReg :
1216         MRI.createGenericVirtualRegister(WideTy);
1217 
1218       auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
1219       auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
1220       MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1221       ResultReg = NextResult;
1222     }
1223 
1224     if (WideSize > DstSize)
1225       MIRBuilder.buildTrunc(DstReg, ResultReg);
1226     else if (DstTy.isPointer())
1227       MIRBuilder.buildIntToPtr(DstReg, ResultReg);
1228 
1229     MI.eraseFromParent();
1230     return Legalized;
1231   }
1232 
1233   // Unmerge the original values to the GCD type, and recombine to the next
1234   // multiple greater than the original type.
1235   //
1236   // %3:_(s12) = G_MERGE_VALUES %0:_(s4), %1:_(s4), %2:_(s4) -> s6
1237   // %4:_(s2), %5:_(s2) = G_UNMERGE_VALUES %0
1238   // %6:_(s2), %7:_(s2) = G_UNMERGE_VALUES %1
1239   // %8:_(s2), %9:_(s2) = G_UNMERGE_VALUES %2
1240   // %10:_(s6) = G_MERGE_VALUES %4, %5, %6
1241   // %11:_(s6) = G_MERGE_VALUES %7, %8, %9
1242   // %12:_(s12) = G_MERGE_VALUES %10, %11
1243   //
1244   // Padding with undef if necessary:
1245   //
1246   // %2:_(s8) = G_MERGE_VALUES %0:_(s4), %1:_(s4) -> s6
1247   // %3:_(s2), %4:_(s2) = G_UNMERGE_VALUES %0
1248   // %5:_(s2), %6:_(s2) = G_UNMERGE_VALUES %1
1249   // %7:_(s2) = G_IMPLICIT_DEF
1250   // %8:_(s6) = G_MERGE_VALUES %3, %4, %5
1251   // %9:_(s6) = G_MERGE_VALUES %6, %7, %7
1252   // %10:_(s12) = G_MERGE_VALUES %8, %9
1253 
1254   const int GCD = greatestCommonDivisor(SrcSize, WideSize);
1255   LLT GCDTy = LLT::scalar(GCD);
1256 
1257   SmallVector<Register, 8> Parts;
1258   SmallVector<Register, 8> NewMergeRegs;
1259   SmallVector<Register, 8> Unmerges;
1260   LLT WideDstTy = LLT::scalar(NumMerge * WideSize);
1261 
1262   // Decompose the original operands if they don't evenly divide.
1263   for (int I = 1, E = MI.getNumOperands(); I != E; ++I) {
1264     Register SrcReg = MI.getOperand(I).getReg();
1265     if (GCD == SrcSize) {
1266       Unmerges.push_back(SrcReg);
1267     } else {
1268       auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
1269       for (int J = 0, JE = Unmerge->getNumOperands() - 1; J != JE; ++J)
1270         Unmerges.push_back(Unmerge.getReg(J));
1271     }
1272   }
1273 
1274   // Pad with undef to the next size that is a multiple of the requested size.
1275   if (static_cast<int>(Unmerges.size()) != NumMerge * WideSize) {
1276     Register UndefReg = MIRBuilder.buildUndef(GCDTy).getReg(0);
1277     for (int I = Unmerges.size(); I != NumMerge * WideSize; ++I)
1278       Unmerges.push_back(UndefReg);
1279   }
1280 
1281   const int PartsPerGCD = WideSize / GCD;
1282 
1283   // Build merges of each piece.
1284   ArrayRef<Register> Slicer(Unmerges);
1285   for (int I = 0; I != NumMerge; ++I, Slicer = Slicer.drop_front(PartsPerGCD)) {
1286     auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
1287     NewMergeRegs.push_back(Merge.getReg(0));
1288   }
1289 
1290   // A truncate may be necessary if the requested type doesn't evenly divide the
1291   // original result type.
1292   if (DstTy.getSizeInBits() == WideDstTy.getSizeInBits()) {
1293     MIRBuilder.buildMerge(DstReg, NewMergeRegs);
1294   } else {
1295     auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
1296     MIRBuilder.buildTrunc(DstReg, FinalMerge.getReg(0));
1297   }
1298 
1299   MI.eraseFromParent();
1300   return Legalized;
1301 }
1302 
1303 LegalizerHelper::LegalizeResult
1304 LegalizerHelper::widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx,
1305                                           LLT WideTy) {
1306   if (TypeIdx != 0)
1307     return UnableToLegalize;
1308 
1309   unsigned NumDst = MI.getNumOperands() - 1;
1310   Register SrcReg = MI.getOperand(NumDst).getReg();
1311   LLT SrcTy = MRI.getType(SrcReg);
1312   if (!SrcTy.isScalar())
1313     return UnableToLegalize;
1314 
1315   Register Dst0Reg = MI.getOperand(0).getReg();
1316   LLT DstTy = MRI.getType(Dst0Reg);
1317   if (!DstTy.isScalar())
1318     return UnableToLegalize;
1319 
1320   unsigned NewSrcSize = NumDst * WideTy.getSizeInBits();
1321   LLT NewSrcTy = LLT::scalar(NewSrcSize);
1322   unsigned SizeDiff = WideTy.getSizeInBits() - DstTy.getSizeInBits();
1323 
1324   auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
1325 
1326   for (unsigned I = 1; I != NumDst; ++I) {
1327     auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
1328     auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
1329     WideSrc = MIRBuilder.buildOr(NewSrcTy, WideSrc, Shl);
1330   }
1331 
1332   Observer.changingInstr(MI);
1333 
1334   MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
1335   for (unsigned I = 0; I != NumDst; ++I)
1336     widenScalarDst(MI, WideTy, I);
1337 
1338   Observer.changedInstr(MI);
1339 
1340   return Legalized;
1341 }
1342 
1343 LegalizerHelper::LegalizeResult
1344 LegalizerHelper::widenScalarExtract(MachineInstr &MI, unsigned TypeIdx,
1345                                     LLT WideTy) {
1346   Register DstReg = MI.getOperand(0).getReg();
1347   Register SrcReg = MI.getOperand(1).getReg();
1348   LLT SrcTy = MRI.getType(SrcReg);
1349 
1350   LLT DstTy = MRI.getType(DstReg);
1351   unsigned Offset = MI.getOperand(2).getImm();
1352 
1353   if (TypeIdx == 0) {
1354     if (SrcTy.isVector() || DstTy.isVector())
1355       return UnableToLegalize;
1356 
1357     SrcOp Src(SrcReg);
1358     if (SrcTy.isPointer()) {
1359       // Extracts from pointers can be handled only if they are really just
1360       // simple integers.
1361       const DataLayout &DL = MIRBuilder.getDataLayout();
1362       if (DL.isNonIntegralAddressSpace(SrcTy.getAddressSpace()))
1363         return UnableToLegalize;
1364 
1365       LLT SrcAsIntTy = LLT::scalar(SrcTy.getSizeInBits());
1366       Src = MIRBuilder.buildPtrToInt(SrcAsIntTy, Src);
1367       SrcTy = SrcAsIntTy;
1368     }
1369 
1370     if (DstTy.isPointer())
1371       return UnableToLegalize;
1372 
1373     if (Offset == 0) {
1374       // Avoid a shift in the degenerate case.
1375       MIRBuilder.buildTrunc(DstReg,
1376                             MIRBuilder.buildAnyExtOrTrunc(WideTy, Src));
1377       MI.eraseFromParent();
1378       return Legalized;
1379     }
1380 
1381     // Do a shift in the source type.
1382     LLT ShiftTy = SrcTy;
1383     if (WideTy.getSizeInBits() > SrcTy.getSizeInBits()) {
1384       Src = MIRBuilder.buildAnyExt(WideTy, Src);
1385       ShiftTy = WideTy;
1386     } else if (WideTy.getSizeInBits() > SrcTy.getSizeInBits())
1387       return UnableToLegalize;
1388 
1389     auto LShr = MIRBuilder.buildLShr(
1390       ShiftTy, Src, MIRBuilder.buildConstant(ShiftTy, Offset));
1391     MIRBuilder.buildTrunc(DstReg, LShr);
1392     MI.eraseFromParent();
1393     return Legalized;
1394   }
1395 
1396   if (SrcTy.isScalar()) {
1397     Observer.changingInstr(MI);
1398     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1399     Observer.changedInstr(MI);
1400     return Legalized;
1401   }
1402 
1403   if (!SrcTy.isVector())
1404     return UnableToLegalize;
1405 
1406   if (DstTy != SrcTy.getElementType())
1407     return UnableToLegalize;
1408 
1409   if (Offset % SrcTy.getScalarSizeInBits() != 0)
1410     return UnableToLegalize;
1411 
1412   Observer.changingInstr(MI);
1413   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1414 
1415   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *
1416                           Offset);
1417   widenScalarDst(MI, WideTy.getScalarType(), 0);
1418   Observer.changedInstr(MI);
1419   return Legalized;
1420 }
1421 
1422 LegalizerHelper::LegalizeResult
1423 LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
1424                                    LLT WideTy) {
1425   if (TypeIdx != 0)
1426     return UnableToLegalize;
1427   Observer.changingInstr(MI);
1428   widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1429   widenScalarDst(MI, WideTy);
1430   Observer.changedInstr(MI);
1431   return Legalized;
1432 }
1433 
1434 LegalizerHelper::LegalizeResult
1435 LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
1436   MIRBuilder.setInstr(MI);
1437 
1438   switch (MI.getOpcode()) {
1439   default:
1440     return UnableToLegalize;
1441   case TargetOpcode::G_EXTRACT:
1442     return widenScalarExtract(MI, TypeIdx, WideTy);
1443   case TargetOpcode::G_INSERT:
1444     return widenScalarInsert(MI, TypeIdx, WideTy);
1445   case TargetOpcode::G_MERGE_VALUES:
1446     return widenScalarMergeValues(MI, TypeIdx, WideTy);
1447   case TargetOpcode::G_UNMERGE_VALUES:
1448     return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
1449   case TargetOpcode::G_UADDO:
1450   case TargetOpcode::G_USUBO: {
1451     if (TypeIdx == 1)
1452       return UnableToLegalize; // TODO
1453     auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1454                                          {MI.getOperand(2).getReg()});
1455     auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1456                                          {MI.getOperand(3).getReg()});
1457     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1458                           ? TargetOpcode::G_ADD
1459                           : TargetOpcode::G_SUB;
1460     // Do the arithmetic in the larger type.
1461     auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1462     LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1463     APInt Mask = APInt::getAllOnesValue(OrigTy.getSizeInBits());
1464     auto AndOp = MIRBuilder.buildInstr(
1465         TargetOpcode::G_AND, {WideTy},
1466         {NewOp, MIRBuilder.buildConstant(WideTy, Mask.getZExtValue())});
1467     // There is no overflow if the AndOp is the same as NewOp.
1468     MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
1469                          AndOp);
1470     // Now trunc the NewOp to the original result.
1471     MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
1472     MI.eraseFromParent();
1473     return Legalized;
1474   }
1475   case TargetOpcode::G_CTTZ:
1476   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
1477   case TargetOpcode::G_CTLZ:
1478   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
1479   case TargetOpcode::G_CTPOP: {
1480     if (TypeIdx == 0) {
1481       Observer.changingInstr(MI);
1482       widenScalarDst(MI, WideTy, 0);
1483       Observer.changedInstr(MI);
1484       return Legalized;
1485     }
1486 
1487     Register SrcReg = MI.getOperand(1).getReg();
1488 
1489     // First ZEXT the input.
1490     auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1491     LLT CurTy = MRI.getType(SrcReg);
1492     if (MI.getOpcode() == TargetOpcode::G_CTTZ) {
1493       // The count is the same in the larger type except if the original
1494       // value was zero.  This can be handled by setting the bit just off
1495       // the top of the original type.
1496       auto TopBit =
1497           APInt::getOneBitSet(WideTy.getSizeInBits(), CurTy.getSizeInBits());
1498       MIBSrc = MIRBuilder.buildOr(
1499         WideTy, MIBSrc, MIRBuilder.buildConstant(WideTy, TopBit));
1500     }
1501 
1502     // Perform the operation at the larger size.
1503     auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1504     // This is already the correct result for CTPOP and CTTZs
1505     if (MI.getOpcode() == TargetOpcode::G_CTLZ ||
1506         MI.getOpcode() == TargetOpcode::G_CTLZ_ZERO_UNDEF) {
1507       // The correct result is NewOp - (Difference in widety and current ty).
1508       unsigned SizeDiff = WideTy.getSizeInBits() - CurTy.getSizeInBits();
1509       MIBNewOp = MIRBuilder.buildInstr(
1510           TargetOpcode::G_SUB, {WideTy},
1511           {MIBNewOp, MIRBuilder.buildConstant(WideTy, SizeDiff)});
1512     }
1513 
1514     MIRBuilder.buildZExtOrTrunc(MI.getOperand(0), MIBNewOp);
1515     MI.eraseFromParent();
1516     return Legalized;
1517   }
1518   case TargetOpcode::G_BSWAP: {
1519     Observer.changingInstr(MI);
1520     Register DstReg = MI.getOperand(0).getReg();
1521 
1522     Register ShrReg = MRI.createGenericVirtualRegister(WideTy);
1523     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1524     Register ShiftAmtReg = MRI.createGenericVirtualRegister(WideTy);
1525     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1526 
1527     MI.getOperand(0).setReg(DstExt);
1528 
1529     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1530 
1531     LLT Ty = MRI.getType(DstReg);
1532     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1533     MIRBuilder.buildConstant(ShiftAmtReg, DiffBits);
1534     MIRBuilder.buildInstr(TargetOpcode::G_LSHR)
1535       .addDef(ShrReg)
1536       .addUse(DstExt)
1537       .addUse(ShiftAmtReg);
1538 
1539     MIRBuilder.buildTrunc(DstReg, ShrReg);
1540     Observer.changedInstr(MI);
1541     return Legalized;
1542   }
1543   case TargetOpcode::G_BITREVERSE: {
1544     Observer.changingInstr(MI);
1545 
1546     Register DstReg = MI.getOperand(0).getReg();
1547     LLT Ty = MRI.getType(DstReg);
1548     unsigned DiffBits = WideTy.getScalarSizeInBits() - Ty.getScalarSizeInBits();
1549 
1550     Register DstExt = MRI.createGenericVirtualRegister(WideTy);
1551     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1552     MI.getOperand(0).setReg(DstExt);
1553     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), ++MIRBuilder.getInsertPt());
1554 
1555     auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
1556     auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt);
1557     MIRBuilder.buildTrunc(DstReg, Shift);
1558     Observer.changedInstr(MI);
1559     return Legalized;
1560   }
1561   case TargetOpcode::G_ADD:
1562   case TargetOpcode::G_AND:
1563   case TargetOpcode::G_MUL:
1564   case TargetOpcode::G_OR:
1565   case TargetOpcode::G_XOR:
1566   case TargetOpcode::G_SUB:
1567     // Perform operation at larger width (any extension is fines here, high bits
1568     // don't affect the result) and then truncate the result back to the
1569     // original type.
1570     Observer.changingInstr(MI);
1571     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1572     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1573     widenScalarDst(MI, WideTy);
1574     Observer.changedInstr(MI);
1575     return Legalized;
1576 
1577   case TargetOpcode::G_SHL:
1578     Observer.changingInstr(MI);
1579 
1580     if (TypeIdx == 0) {
1581       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1582       widenScalarDst(MI, WideTy);
1583     } else {
1584       assert(TypeIdx == 1);
1585       // The "number of bits to shift" operand must preserve its value as an
1586       // unsigned integer:
1587       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1588     }
1589 
1590     Observer.changedInstr(MI);
1591     return Legalized;
1592 
1593   case TargetOpcode::G_SDIV:
1594   case TargetOpcode::G_SREM:
1595   case TargetOpcode::G_SMIN:
1596   case TargetOpcode::G_SMAX:
1597     Observer.changingInstr(MI);
1598     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1599     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1600     widenScalarDst(MI, WideTy);
1601     Observer.changedInstr(MI);
1602     return Legalized;
1603 
1604   case TargetOpcode::G_ASHR:
1605   case TargetOpcode::G_LSHR:
1606     Observer.changingInstr(MI);
1607 
1608     if (TypeIdx == 0) {
1609       unsigned CvtOp = MI.getOpcode() == TargetOpcode::G_ASHR ?
1610         TargetOpcode::G_SEXT : TargetOpcode::G_ZEXT;
1611 
1612       widenScalarSrc(MI, WideTy, 1, CvtOp);
1613       widenScalarDst(MI, WideTy);
1614     } else {
1615       assert(TypeIdx == 1);
1616       // The "number of bits to shift" operand must preserve its value as an
1617       // unsigned integer:
1618       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1619     }
1620 
1621     Observer.changedInstr(MI);
1622     return Legalized;
1623   case TargetOpcode::G_UDIV:
1624   case TargetOpcode::G_UREM:
1625   case TargetOpcode::G_UMIN:
1626   case TargetOpcode::G_UMAX:
1627     Observer.changingInstr(MI);
1628     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1629     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ZEXT);
1630     widenScalarDst(MI, WideTy);
1631     Observer.changedInstr(MI);
1632     return Legalized;
1633 
1634   case TargetOpcode::G_SELECT:
1635     Observer.changingInstr(MI);
1636     if (TypeIdx == 0) {
1637       // Perform operation at larger width (any extension is fine here, high
1638       // bits don't affect the result) and then truncate the result back to the
1639       // original type.
1640       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1641       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_ANYEXT);
1642       widenScalarDst(MI, WideTy);
1643     } else {
1644       bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1645       // Explicit extension is required here since high bits affect the result.
1646       widenScalarSrc(MI, WideTy, 1, MIRBuilder.getBoolExtOp(IsVec, false));
1647     }
1648     Observer.changedInstr(MI);
1649     return Legalized;
1650 
1651   case TargetOpcode::G_FPTOSI:
1652   case TargetOpcode::G_FPTOUI:
1653     Observer.changingInstr(MI);
1654 
1655     if (TypeIdx == 0)
1656       widenScalarDst(MI, WideTy);
1657     else
1658       widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_FPEXT);
1659 
1660     Observer.changedInstr(MI);
1661     return Legalized;
1662   case TargetOpcode::G_SITOFP:
1663     if (TypeIdx != 1)
1664       return UnableToLegalize;
1665     Observer.changingInstr(MI);
1666     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_SEXT);
1667     Observer.changedInstr(MI);
1668     return Legalized;
1669 
1670   case TargetOpcode::G_UITOFP:
1671     if (TypeIdx != 1)
1672       return UnableToLegalize;
1673     Observer.changingInstr(MI);
1674     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1675     Observer.changedInstr(MI);
1676     return Legalized;
1677 
1678   case TargetOpcode::G_LOAD:
1679   case TargetOpcode::G_SEXTLOAD:
1680   case TargetOpcode::G_ZEXTLOAD:
1681     Observer.changingInstr(MI);
1682     widenScalarDst(MI, WideTy);
1683     Observer.changedInstr(MI);
1684     return Legalized;
1685 
1686   case TargetOpcode::G_STORE: {
1687     if (TypeIdx != 0)
1688       return UnableToLegalize;
1689 
1690     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1691     if (!isPowerOf2_32(Ty.getSizeInBits()))
1692       return UnableToLegalize;
1693 
1694     Observer.changingInstr(MI);
1695 
1696     unsigned ExtType = Ty.getScalarSizeInBits() == 1 ?
1697       TargetOpcode::G_ZEXT : TargetOpcode::G_ANYEXT;
1698     widenScalarSrc(MI, WideTy, 0, ExtType);
1699 
1700     Observer.changedInstr(MI);
1701     return Legalized;
1702   }
1703   case TargetOpcode::G_CONSTANT: {
1704     MachineOperand &SrcMO = MI.getOperand(1);
1705     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1706     unsigned ExtOpc = LI.getExtOpcodeForWideningConstant(
1707         MRI.getType(MI.getOperand(0).getReg()));
1708     assert((ExtOpc == TargetOpcode::G_ZEXT || ExtOpc == TargetOpcode::G_SEXT ||
1709             ExtOpc == TargetOpcode::G_ANYEXT) &&
1710            "Illegal Extend");
1711     const APInt &SrcVal = SrcMO.getCImm()->getValue();
1712     const APInt &Val = (ExtOpc == TargetOpcode::G_SEXT)
1713                            ? SrcVal.sext(WideTy.getSizeInBits())
1714                            : SrcVal.zext(WideTy.getSizeInBits());
1715     Observer.changingInstr(MI);
1716     SrcMO.setCImm(ConstantInt::get(Ctx, Val));
1717 
1718     widenScalarDst(MI, WideTy);
1719     Observer.changedInstr(MI);
1720     return Legalized;
1721   }
1722   case TargetOpcode::G_FCONSTANT: {
1723     MachineOperand &SrcMO = MI.getOperand(1);
1724     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
1725     APFloat Val = SrcMO.getFPImm()->getValueAPF();
1726     bool LosesInfo;
1727     switch (WideTy.getSizeInBits()) {
1728     case 32:
1729       Val.convert(APFloat::IEEEsingle(), APFloat::rmNearestTiesToEven,
1730                   &LosesInfo);
1731       break;
1732     case 64:
1733       Val.convert(APFloat::IEEEdouble(), APFloat::rmNearestTiesToEven,
1734                   &LosesInfo);
1735       break;
1736     default:
1737       return UnableToLegalize;
1738     }
1739 
1740     assert(!LosesInfo && "extend should always be lossless");
1741 
1742     Observer.changingInstr(MI);
1743     SrcMO.setFPImm(ConstantFP::get(Ctx, Val));
1744 
1745     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1746     Observer.changedInstr(MI);
1747     return Legalized;
1748   }
1749   case TargetOpcode::G_IMPLICIT_DEF: {
1750     Observer.changingInstr(MI);
1751     widenScalarDst(MI, WideTy);
1752     Observer.changedInstr(MI);
1753     return Legalized;
1754   }
1755   case TargetOpcode::G_BRCOND:
1756     Observer.changingInstr(MI);
1757     widenScalarSrc(MI, WideTy, 0, MIRBuilder.getBoolExtOp(false, false));
1758     Observer.changedInstr(MI);
1759     return Legalized;
1760 
1761   case TargetOpcode::G_FCMP:
1762     Observer.changingInstr(MI);
1763     if (TypeIdx == 0)
1764       widenScalarDst(MI, WideTy);
1765     else {
1766       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_FPEXT);
1767       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_FPEXT);
1768     }
1769     Observer.changedInstr(MI);
1770     return Legalized;
1771 
1772   case TargetOpcode::G_ICMP:
1773     Observer.changingInstr(MI);
1774     if (TypeIdx == 0)
1775       widenScalarDst(MI, WideTy);
1776     else {
1777       unsigned ExtOpcode = CmpInst::isSigned(static_cast<CmpInst::Predicate>(
1778                                MI.getOperand(1).getPredicate()))
1779                                ? TargetOpcode::G_SEXT
1780                                : TargetOpcode::G_ZEXT;
1781       widenScalarSrc(MI, WideTy, 2, ExtOpcode);
1782       widenScalarSrc(MI, WideTy, 3, ExtOpcode);
1783     }
1784     Observer.changedInstr(MI);
1785     return Legalized;
1786 
1787   case TargetOpcode::G_PTR_ADD:
1788     assert(TypeIdx == 1 && "unable to legalize pointer of G_PTR_ADD");
1789     Observer.changingInstr(MI);
1790     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1791     Observer.changedInstr(MI);
1792     return Legalized;
1793 
1794   case TargetOpcode::G_PHI: {
1795     assert(TypeIdx == 0 && "Expecting only Idx 0");
1796 
1797     Observer.changingInstr(MI);
1798     for (unsigned I = 1; I < MI.getNumOperands(); I += 2) {
1799       MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
1800       MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
1801       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_ANYEXT);
1802     }
1803 
1804     MachineBasicBlock &MBB = *MI.getParent();
1805     MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
1806     widenScalarDst(MI, WideTy);
1807     Observer.changedInstr(MI);
1808     return Legalized;
1809   }
1810   case TargetOpcode::G_EXTRACT_VECTOR_ELT: {
1811     if (TypeIdx == 0) {
1812       Register VecReg = MI.getOperand(1).getReg();
1813       LLT VecTy = MRI.getType(VecReg);
1814       Observer.changingInstr(MI);
1815 
1816       widenScalarSrc(MI, LLT::vector(VecTy.getNumElements(),
1817                                      WideTy.getSizeInBits()),
1818                      1, TargetOpcode::G_SEXT);
1819 
1820       widenScalarDst(MI, WideTy, 0);
1821       Observer.changedInstr(MI);
1822       return Legalized;
1823     }
1824 
1825     if (TypeIdx != 2)
1826       return UnableToLegalize;
1827     Observer.changingInstr(MI);
1828     // TODO: Probably should be zext
1829     widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_SEXT);
1830     Observer.changedInstr(MI);
1831     return Legalized;
1832   }
1833   case TargetOpcode::G_INSERT_VECTOR_ELT: {
1834     if (TypeIdx == 1) {
1835       Observer.changingInstr(MI);
1836 
1837       Register VecReg = MI.getOperand(1).getReg();
1838       LLT VecTy = MRI.getType(VecReg);
1839       LLT WideVecTy = LLT::vector(VecTy.getNumElements(), WideTy);
1840 
1841       widenScalarSrc(MI, WideVecTy, 1, TargetOpcode::G_ANYEXT);
1842       widenScalarSrc(MI, WideTy, 2, TargetOpcode::G_ANYEXT);
1843       widenScalarDst(MI, WideVecTy, 0);
1844       Observer.changedInstr(MI);
1845       return Legalized;
1846     }
1847 
1848     if (TypeIdx == 2) {
1849       Observer.changingInstr(MI);
1850       // TODO: Probably should be zext
1851       widenScalarSrc(MI, WideTy, 3, TargetOpcode::G_SEXT);
1852       Observer.changedInstr(MI);
1853     }
1854 
1855     return Legalized;
1856   }
1857   case TargetOpcode::G_FADD:
1858   case TargetOpcode::G_FMUL:
1859   case TargetOpcode::G_FSUB:
1860   case TargetOpcode::G_FMA:
1861   case TargetOpcode::G_FMAD:
1862   case TargetOpcode::G_FNEG:
1863   case TargetOpcode::G_FABS:
1864   case TargetOpcode::G_FCANONICALIZE:
1865   case TargetOpcode::G_FMINNUM:
1866   case TargetOpcode::G_FMAXNUM:
1867   case TargetOpcode::G_FMINNUM_IEEE:
1868   case TargetOpcode::G_FMAXNUM_IEEE:
1869   case TargetOpcode::G_FMINIMUM:
1870   case TargetOpcode::G_FMAXIMUM:
1871   case TargetOpcode::G_FDIV:
1872   case TargetOpcode::G_FREM:
1873   case TargetOpcode::G_FCEIL:
1874   case TargetOpcode::G_FFLOOR:
1875   case TargetOpcode::G_FCOS:
1876   case TargetOpcode::G_FSIN:
1877   case TargetOpcode::G_FLOG10:
1878   case TargetOpcode::G_FLOG:
1879   case TargetOpcode::G_FLOG2:
1880   case TargetOpcode::G_FRINT:
1881   case TargetOpcode::G_FNEARBYINT:
1882   case TargetOpcode::G_FSQRT:
1883   case TargetOpcode::G_FEXP:
1884   case TargetOpcode::G_FEXP2:
1885   case TargetOpcode::G_FPOW:
1886   case TargetOpcode::G_INTRINSIC_TRUNC:
1887   case TargetOpcode::G_INTRINSIC_ROUND:
1888     assert(TypeIdx == 0);
1889     Observer.changingInstr(MI);
1890 
1891     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
1892       widenScalarSrc(MI, WideTy, I, TargetOpcode::G_FPEXT);
1893 
1894     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_FPTRUNC);
1895     Observer.changedInstr(MI);
1896     return Legalized;
1897   case TargetOpcode::G_INTTOPTR:
1898     if (TypeIdx != 1)
1899       return UnableToLegalize;
1900 
1901     Observer.changingInstr(MI);
1902     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ZEXT);
1903     Observer.changedInstr(MI);
1904     return Legalized;
1905   case TargetOpcode::G_PTRTOINT:
1906     if (TypeIdx != 0)
1907       return UnableToLegalize;
1908 
1909     Observer.changingInstr(MI);
1910     widenScalarDst(MI, WideTy, 0);
1911     Observer.changedInstr(MI);
1912     return Legalized;
1913   case TargetOpcode::G_BUILD_VECTOR: {
1914     Observer.changingInstr(MI);
1915 
1916     const LLT WideEltTy = TypeIdx == 1 ? WideTy : WideTy.getElementType();
1917     for (int I = 1, E = MI.getNumOperands(); I != E; ++I)
1918       widenScalarSrc(MI, WideEltTy, I, TargetOpcode::G_ANYEXT);
1919 
1920     // Avoid changing the result vector type if the source element type was
1921     // requested.
1922     if (TypeIdx == 1) {
1923       auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
1924       MI.setDesc(TII.get(TargetOpcode::G_BUILD_VECTOR_TRUNC));
1925     } else {
1926       widenScalarDst(MI, WideTy, 0);
1927     }
1928 
1929     Observer.changedInstr(MI);
1930     return Legalized;
1931   }
1932   case TargetOpcode::G_SEXT_INREG:
1933     if (TypeIdx != 0)
1934       return UnableToLegalize;
1935 
1936     Observer.changingInstr(MI);
1937     widenScalarSrc(MI, WideTy, 1, TargetOpcode::G_ANYEXT);
1938     widenScalarDst(MI, WideTy, 0, TargetOpcode::G_TRUNC);
1939     Observer.changedInstr(MI);
1940     return Legalized;
1941   }
1942 }
1943 
1944 static void getUnmergePieces(SmallVectorImpl<Register> &Pieces,
1945                              MachineIRBuilder &B, Register Src, LLT Ty) {
1946   auto Unmerge = B.buildUnmerge(Ty, Src);
1947   for (int I = 0, E = Unmerge->getNumOperands() - 1; I != E; ++I)
1948     Pieces.push_back(Unmerge.getReg(I));
1949 }
1950 
1951 LegalizerHelper::LegalizeResult
1952 LegalizerHelper::lowerBitcast(MachineInstr &MI) {
1953   Register Dst = MI.getOperand(0).getReg();
1954   Register Src = MI.getOperand(1).getReg();
1955   LLT DstTy = MRI.getType(Dst);
1956   LLT SrcTy = MRI.getType(Src);
1957 
1958   if (SrcTy.isVector() && !DstTy.isVector()) {
1959     SmallVector<Register, 8> SrcRegs;
1960     getUnmergePieces(SrcRegs, MIRBuilder, Src, SrcTy.getElementType());
1961     MIRBuilder.buildMerge(Dst, SrcRegs);
1962     MI.eraseFromParent();
1963     return Legalized;
1964   }
1965 
1966   if (DstTy.isVector() && !SrcTy.isVector()) {
1967     SmallVector<Register, 8> SrcRegs;
1968     getUnmergePieces(SrcRegs, MIRBuilder, Src, DstTy.getElementType());
1969     MIRBuilder.buildMerge(Dst, SrcRegs);
1970     MI.eraseFromParent();
1971     return Legalized;
1972   }
1973 
1974   return UnableToLegalize;
1975 }
1976 
1977 LegalizerHelper::LegalizeResult
1978 LegalizerHelper::lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
1979   using namespace TargetOpcode;
1980   MIRBuilder.setInstr(MI);
1981 
1982   switch(MI.getOpcode()) {
1983   default:
1984     return UnableToLegalize;
1985   case TargetOpcode::G_BITCAST:
1986     return lowerBitcast(MI);
1987   case TargetOpcode::G_SREM:
1988   case TargetOpcode::G_UREM: {
1989     Register QuotReg = MRI.createGenericVirtualRegister(Ty);
1990     MIRBuilder.buildInstr(MI.getOpcode() == G_SREM ? G_SDIV : G_UDIV)
1991         .addDef(QuotReg)
1992         .addUse(MI.getOperand(1).getReg())
1993         .addUse(MI.getOperand(2).getReg());
1994 
1995     Register ProdReg = MRI.createGenericVirtualRegister(Ty);
1996     MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1997     MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1998                         ProdReg);
1999     MI.eraseFromParent();
2000     return Legalized;
2001   }
2002   case TargetOpcode::G_SADDO:
2003   case TargetOpcode::G_SSUBO:
2004     return lowerSADDO_SSUBO(MI);
2005   case TargetOpcode::G_SMULO:
2006   case TargetOpcode::G_UMULO: {
2007     // Generate G_UMULH/G_SMULH to check for overflow and a normal G_MUL for the
2008     // result.
2009     Register Res = MI.getOperand(0).getReg();
2010     Register Overflow = MI.getOperand(1).getReg();
2011     Register LHS = MI.getOperand(2).getReg();
2012     Register RHS = MI.getOperand(3).getReg();
2013 
2014     MIRBuilder.buildMul(Res, LHS, RHS);
2015 
2016     unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SMULO
2017                           ? TargetOpcode::G_SMULH
2018                           : TargetOpcode::G_UMULH;
2019 
2020     Register HiPart = MRI.createGenericVirtualRegister(Ty);
2021     MIRBuilder.buildInstr(Opcode)
2022       .addDef(HiPart)
2023       .addUse(LHS)
2024       .addUse(RHS);
2025 
2026     Register Zero = MRI.createGenericVirtualRegister(Ty);
2027     MIRBuilder.buildConstant(Zero, 0);
2028 
2029     // For *signed* multiply, overflow is detected by checking:
2030     // (hi != (lo >> bitwidth-1))
2031     if (Opcode == TargetOpcode::G_SMULH) {
2032       Register Shifted = MRI.createGenericVirtualRegister(Ty);
2033       Register ShiftAmt = MRI.createGenericVirtualRegister(Ty);
2034       MIRBuilder.buildConstant(ShiftAmt, Ty.getSizeInBits() - 1);
2035       MIRBuilder.buildInstr(TargetOpcode::G_ASHR)
2036         .addDef(Shifted)
2037         .addUse(Res)
2038         .addUse(ShiftAmt);
2039       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Shifted);
2040     } else {
2041       MIRBuilder.buildICmp(CmpInst::ICMP_NE, Overflow, HiPart, Zero);
2042     }
2043     MI.eraseFromParent();
2044     return Legalized;
2045   }
2046   case TargetOpcode::G_FNEG: {
2047     // TODO: Handle vector types once we are able to
2048     // represent them.
2049     if (Ty.isVector())
2050       return UnableToLegalize;
2051     Register Res = MI.getOperand(0).getReg();
2052     Type *ZeroTy;
2053     LLVMContext &Ctx = MIRBuilder.getMF().getFunction().getContext();
2054     switch (Ty.getSizeInBits()) {
2055     case 16:
2056       ZeroTy = Type::getHalfTy(Ctx);
2057       break;
2058     case 32:
2059       ZeroTy = Type::getFloatTy(Ctx);
2060       break;
2061     case 64:
2062       ZeroTy = Type::getDoubleTy(Ctx);
2063       break;
2064     case 128:
2065       ZeroTy = Type::getFP128Ty(Ctx);
2066       break;
2067     default:
2068       llvm_unreachable("unexpected floating-point type");
2069     }
2070     ConstantFP &ZeroForNegation =
2071         *cast<ConstantFP>(ConstantFP::getZeroValueForNegation(ZeroTy));
2072     auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
2073     Register SubByReg = MI.getOperand(1).getReg();
2074     Register ZeroReg = Zero->getOperand(0).getReg();
2075     MIRBuilder.buildInstr(TargetOpcode::G_FSUB, {Res}, {ZeroReg, SubByReg},
2076                           MI.getFlags());
2077     MI.eraseFromParent();
2078     return Legalized;
2079   }
2080   case TargetOpcode::G_FSUB: {
2081     // Lower (G_FSUB LHS, RHS) to (G_FADD LHS, (G_FNEG RHS)).
2082     // First, check if G_FNEG is marked as Lower. If so, we may
2083     // end up with an infinite loop as G_FSUB is used to legalize G_FNEG.
2084     if (LI.getAction({G_FNEG, {Ty}}).Action == Lower)
2085       return UnableToLegalize;
2086     Register Res = MI.getOperand(0).getReg();
2087     Register LHS = MI.getOperand(1).getReg();
2088     Register RHS = MI.getOperand(2).getReg();
2089     Register Neg = MRI.createGenericVirtualRegister(Ty);
2090     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
2091     MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Res}, {LHS, Neg}, MI.getFlags());
2092     MI.eraseFromParent();
2093     return Legalized;
2094   }
2095   case TargetOpcode::G_FMAD:
2096     return lowerFMad(MI);
2097   case TargetOpcode::G_INTRINSIC_ROUND:
2098     return lowerIntrinsicRound(MI);
2099   case TargetOpcode::G_ATOMIC_CMPXCHG_WITH_SUCCESS: {
2100     Register OldValRes = MI.getOperand(0).getReg();
2101     Register SuccessRes = MI.getOperand(1).getReg();
2102     Register Addr = MI.getOperand(2).getReg();
2103     Register CmpVal = MI.getOperand(3).getReg();
2104     Register NewVal = MI.getOperand(4).getReg();
2105     MIRBuilder.buildAtomicCmpXchg(OldValRes, Addr, CmpVal, NewVal,
2106                                   **MI.memoperands_begin());
2107     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, SuccessRes, OldValRes, CmpVal);
2108     MI.eraseFromParent();
2109     return Legalized;
2110   }
2111   case TargetOpcode::G_LOAD:
2112   case TargetOpcode::G_SEXTLOAD:
2113   case TargetOpcode::G_ZEXTLOAD: {
2114     // Lower to a memory-width G_LOAD and a G_SEXT/G_ZEXT/G_ANYEXT
2115     Register DstReg = MI.getOperand(0).getReg();
2116     Register PtrReg = MI.getOperand(1).getReg();
2117     LLT DstTy = MRI.getType(DstReg);
2118     auto &MMO = **MI.memoperands_begin();
2119 
2120     if (DstTy.getSizeInBits() == MMO.getSizeInBits()) {
2121       if (MI.getOpcode() == TargetOpcode::G_LOAD) {
2122         // This load needs splitting into power of 2 sized loads.
2123         if (DstTy.isVector())
2124           return UnableToLegalize;
2125         if (isPowerOf2_32(DstTy.getSizeInBits()))
2126           return UnableToLegalize; // Don't know what we're being asked to do.
2127 
2128         // Our strategy here is to generate anyextending loads for the smaller
2129         // types up to next power-2 result type, and then combine the two larger
2130         // result values together, before truncating back down to the non-pow-2
2131         // type.
2132         // E.g. v1 = i24 load =>
2133         // v2 = i32 load (2 byte)
2134         // v3 = i32 load (1 byte)
2135         // v4 = i32 shl v3, 16
2136         // v5 = i32 or v4, v2
2137         // v1 = i24 trunc v5
2138         // By doing this we generate the correct truncate which should get
2139         // combined away as an artifact with a matching extend.
2140         uint64_t LargeSplitSize = PowerOf2Floor(DstTy.getSizeInBits());
2141         uint64_t SmallSplitSize = DstTy.getSizeInBits() - LargeSplitSize;
2142 
2143         MachineFunction &MF = MIRBuilder.getMF();
2144         MachineMemOperand *LargeMMO =
2145             MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2146         MachineMemOperand *SmallMMO = MF.getMachineMemOperand(
2147             &MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2148 
2149         LLT PtrTy = MRI.getType(PtrReg);
2150         unsigned AnyExtSize = NextPowerOf2(DstTy.getSizeInBits());
2151         LLT AnyExtTy = LLT::scalar(AnyExtSize);
2152         Register LargeLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2153         Register SmallLdReg = MRI.createGenericVirtualRegister(AnyExtTy);
2154         auto LargeLoad =
2155             MIRBuilder.buildLoad(LargeLdReg, PtrReg, *LargeMMO);
2156 
2157         auto OffsetCst =
2158             MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2159         Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2160         auto SmallPtr =
2161             MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2162         auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
2163                                               *SmallMMO);
2164 
2165         auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
2166         auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt);
2167         auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
2168         MIRBuilder.buildTrunc(DstReg, {Or.getReg(0)});
2169         MI.eraseFromParent();
2170         return Legalized;
2171       }
2172       MIRBuilder.buildLoad(DstReg, PtrReg, MMO);
2173       MI.eraseFromParent();
2174       return Legalized;
2175     }
2176 
2177     if (DstTy.isScalar()) {
2178       Register TmpReg =
2179           MRI.createGenericVirtualRegister(LLT::scalar(MMO.getSizeInBits()));
2180       MIRBuilder.buildLoad(TmpReg, PtrReg, MMO);
2181       switch (MI.getOpcode()) {
2182       default:
2183         llvm_unreachable("Unexpected opcode");
2184       case TargetOpcode::G_LOAD:
2185         MIRBuilder.buildExtOrTrunc(TargetOpcode::G_ANYEXT, DstReg, TmpReg);
2186         break;
2187       case TargetOpcode::G_SEXTLOAD:
2188         MIRBuilder.buildSExt(DstReg, TmpReg);
2189         break;
2190       case TargetOpcode::G_ZEXTLOAD:
2191         MIRBuilder.buildZExt(DstReg, TmpReg);
2192         break;
2193       }
2194       MI.eraseFromParent();
2195       return Legalized;
2196     }
2197 
2198     return UnableToLegalize;
2199   }
2200   case TargetOpcode::G_STORE: {
2201     // Lower a non-power of 2 store into multiple pow-2 stores.
2202     // E.g. split an i24 store into an i16 store + i8 store.
2203     // We do this by first extending the stored value to the next largest power
2204     // of 2 type, and then using truncating stores to store the components.
2205     // By doing this, likewise with G_LOAD, generate an extend that can be
2206     // artifact-combined away instead of leaving behind extracts.
2207     Register SrcReg = MI.getOperand(0).getReg();
2208     Register PtrReg = MI.getOperand(1).getReg();
2209     LLT SrcTy = MRI.getType(SrcReg);
2210     MachineMemOperand &MMO = **MI.memoperands_begin();
2211     if (SrcTy.getSizeInBits() != MMO.getSizeInBits())
2212       return UnableToLegalize;
2213     if (SrcTy.isVector())
2214       return UnableToLegalize;
2215     if (isPowerOf2_32(SrcTy.getSizeInBits()))
2216       return UnableToLegalize; // Don't know what we're being asked to do.
2217 
2218     // Extend to the next pow-2.
2219     const LLT ExtendTy = LLT::scalar(NextPowerOf2(SrcTy.getSizeInBits()));
2220     auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg);
2221 
2222     // Obtain the smaller value by shifting away the larger value.
2223     uint64_t LargeSplitSize = PowerOf2Floor(SrcTy.getSizeInBits());
2224     uint64_t SmallSplitSize = SrcTy.getSizeInBits() - LargeSplitSize;
2225     auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize);
2226     auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt);
2227 
2228     // Generate the PtrAdd and truncating stores.
2229     LLT PtrTy = MRI.getType(PtrReg);
2230     auto OffsetCst =
2231         MIRBuilder.buildConstant(LLT::scalar(64), LargeSplitSize / 8);
2232     Register PtrAddReg = MRI.createGenericVirtualRegister(PtrTy);
2233     auto SmallPtr =
2234         MIRBuilder.buildPtrAdd(PtrAddReg, PtrReg, OffsetCst.getReg(0));
2235 
2236     MachineFunction &MF = MIRBuilder.getMF();
2237     MachineMemOperand *LargeMMO =
2238         MF.getMachineMemOperand(&MMO, 0, LargeSplitSize / 8);
2239     MachineMemOperand *SmallMMO =
2240         MF.getMachineMemOperand(&MMO, LargeSplitSize / 8, SmallSplitSize / 8);
2241     MIRBuilder.buildStore(ExtVal.getReg(0), PtrReg, *LargeMMO);
2242     MIRBuilder.buildStore(SmallVal.getReg(0), SmallPtr.getReg(0), *SmallMMO);
2243     MI.eraseFromParent();
2244     return Legalized;
2245   }
2246   case TargetOpcode::G_CTLZ_ZERO_UNDEF:
2247   case TargetOpcode::G_CTTZ_ZERO_UNDEF:
2248   case TargetOpcode::G_CTLZ:
2249   case TargetOpcode::G_CTTZ:
2250   case TargetOpcode::G_CTPOP:
2251     return lowerBitCount(MI, TypeIdx, Ty);
2252   case G_UADDO: {
2253     Register Res = MI.getOperand(0).getReg();
2254     Register CarryOut = MI.getOperand(1).getReg();
2255     Register LHS = MI.getOperand(2).getReg();
2256     Register RHS = MI.getOperand(3).getReg();
2257 
2258     MIRBuilder.buildAdd(Res, LHS, RHS);
2259     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, RHS);
2260 
2261     MI.eraseFromParent();
2262     return Legalized;
2263   }
2264   case G_UADDE: {
2265     Register Res = MI.getOperand(0).getReg();
2266     Register CarryOut = MI.getOperand(1).getReg();
2267     Register LHS = MI.getOperand(2).getReg();
2268     Register RHS = MI.getOperand(3).getReg();
2269     Register CarryIn = MI.getOperand(4).getReg();
2270 
2271     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2272     Register ZExtCarryIn = MRI.createGenericVirtualRegister(Ty);
2273 
2274     MIRBuilder.buildAdd(TmpRes, LHS, RHS);
2275     MIRBuilder.buildZExt(ZExtCarryIn, CarryIn);
2276     MIRBuilder.buildAdd(Res, TmpRes, ZExtCarryIn);
2277     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, CarryOut, Res, LHS);
2278 
2279     MI.eraseFromParent();
2280     return Legalized;
2281   }
2282   case G_USUBO: {
2283     Register Res = MI.getOperand(0).getReg();
2284     Register BorrowOut = MI.getOperand(1).getReg();
2285     Register LHS = MI.getOperand(2).getReg();
2286     Register RHS = MI.getOperand(3).getReg();
2287 
2288     MIRBuilder.buildSub(Res, LHS, RHS);
2289     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, BorrowOut, LHS, RHS);
2290 
2291     MI.eraseFromParent();
2292     return Legalized;
2293   }
2294   case G_USUBE: {
2295     Register Res = MI.getOperand(0).getReg();
2296     Register BorrowOut = MI.getOperand(1).getReg();
2297     Register LHS = MI.getOperand(2).getReg();
2298     Register RHS = MI.getOperand(3).getReg();
2299     Register BorrowIn = MI.getOperand(4).getReg();
2300 
2301     Register TmpRes = MRI.createGenericVirtualRegister(Ty);
2302     Register ZExtBorrowIn = MRI.createGenericVirtualRegister(Ty);
2303     Register LHS_EQ_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2304     Register LHS_ULT_RHS = MRI.createGenericVirtualRegister(LLT::scalar(1));
2305 
2306     MIRBuilder.buildSub(TmpRes, LHS, RHS);
2307     MIRBuilder.buildZExt(ZExtBorrowIn, BorrowIn);
2308     MIRBuilder.buildSub(Res, TmpRes, ZExtBorrowIn);
2309     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LHS_EQ_RHS, LHS, RHS);
2310     MIRBuilder.buildICmp(CmpInst::ICMP_ULT, LHS_ULT_RHS, LHS, RHS);
2311     MIRBuilder.buildSelect(BorrowOut, LHS_EQ_RHS, BorrowIn, LHS_ULT_RHS);
2312 
2313     MI.eraseFromParent();
2314     return Legalized;
2315   }
2316   case G_UITOFP:
2317     return lowerUITOFP(MI, TypeIdx, Ty);
2318   case G_SITOFP:
2319     return lowerSITOFP(MI, TypeIdx, Ty);
2320   case G_FPTOUI:
2321     return lowerFPTOUI(MI, TypeIdx, Ty);
2322   case G_SMIN:
2323   case G_SMAX:
2324   case G_UMIN:
2325   case G_UMAX:
2326     return lowerMinMax(MI, TypeIdx, Ty);
2327   case G_FCOPYSIGN:
2328     return lowerFCopySign(MI, TypeIdx, Ty);
2329   case G_FMINNUM:
2330   case G_FMAXNUM:
2331     return lowerFMinNumMaxNum(MI);
2332   case G_UNMERGE_VALUES:
2333     return lowerUnmergeValues(MI);
2334   case TargetOpcode::G_SEXT_INREG: {
2335     assert(MI.getOperand(2).isImm() && "Expected immediate");
2336     int64_t SizeInBits = MI.getOperand(2).getImm();
2337 
2338     Register DstReg = MI.getOperand(0).getReg();
2339     Register SrcReg = MI.getOperand(1).getReg();
2340     LLT DstTy = MRI.getType(DstReg);
2341     Register TmpRes = MRI.createGenericVirtualRegister(DstTy);
2342 
2343     auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
2344     MIRBuilder.buildInstr(TargetOpcode::G_SHL, {TmpRes}, {SrcReg, MIBSz->getOperand(0).getReg()});
2345     MIRBuilder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {TmpRes, MIBSz->getOperand(0).getReg()});
2346     MI.eraseFromParent();
2347     return Legalized;
2348   }
2349   case G_SHUFFLE_VECTOR:
2350     return lowerShuffleVector(MI);
2351   case G_DYN_STACKALLOC:
2352     return lowerDynStackAlloc(MI);
2353   case G_EXTRACT:
2354     return lowerExtract(MI);
2355   case G_INSERT:
2356     return lowerInsert(MI);
2357   case G_BSWAP:
2358     return lowerBswap(MI);
2359   case G_BITREVERSE:
2360     return lowerBitreverse(MI);
2361   case G_READ_REGISTER:
2362     return lowerReadRegister(MI);
2363   }
2364 }
2365 
2366 LegalizerHelper::LegalizeResult LegalizerHelper::fewerElementsVectorImplicitDef(
2367     MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy) {
2368   SmallVector<Register, 2> DstRegs;
2369 
2370   unsigned NarrowSize = NarrowTy.getSizeInBits();
2371   Register DstReg = MI.getOperand(0).getReg();
2372   unsigned Size = MRI.getType(DstReg).getSizeInBits();
2373   int NumParts = Size / NarrowSize;
2374   // FIXME: Don't know how to handle the situation where the small vectors
2375   // aren't all the same size yet.
2376   if (Size % NarrowSize != 0)
2377     return UnableToLegalize;
2378 
2379   for (int i = 0; i < NumParts; ++i) {
2380     Register TmpReg = MRI.createGenericVirtualRegister(NarrowTy);
2381     MIRBuilder.buildUndef(TmpReg);
2382     DstRegs.push_back(TmpReg);
2383   }
2384 
2385   if (NarrowTy.isVector())
2386     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2387   else
2388     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2389 
2390   MI.eraseFromParent();
2391   return Legalized;
2392 }
2393 
2394 LegalizerHelper::LegalizeResult
2395 LegalizerHelper::fewerElementsVectorBasic(MachineInstr &MI, unsigned TypeIdx,
2396                                           LLT NarrowTy) {
2397   const unsigned Opc = MI.getOpcode();
2398   const unsigned NumOps = MI.getNumOperands() - 1;
2399   const unsigned NarrowSize = NarrowTy.getSizeInBits();
2400   const Register DstReg = MI.getOperand(0).getReg();
2401   const unsigned Flags = MI.getFlags();
2402   const LLT DstTy = MRI.getType(DstReg);
2403   const unsigned Size = DstTy.getSizeInBits();
2404   const int NumParts = Size / NarrowSize;
2405   const LLT EltTy = DstTy.getElementType();
2406   const unsigned EltSize = EltTy.getSizeInBits();
2407   const unsigned BitsForNumParts = NarrowSize * NumParts;
2408 
2409   // Check if we have any leftovers. If we do, then only handle the case where
2410   // the leftover is one element.
2411   if (BitsForNumParts != Size && BitsForNumParts + EltSize != Size)
2412     return UnableToLegalize;
2413 
2414   if (BitsForNumParts != Size) {
2415     Register AccumDstReg = MRI.createGenericVirtualRegister(DstTy);
2416     MIRBuilder.buildUndef(AccumDstReg);
2417 
2418     // Handle the pieces which evenly divide into the requested type with
2419     // extract/op/insert sequence.
2420     for (unsigned Offset = 0; Offset < BitsForNumParts; Offset += NarrowSize) {
2421       SmallVector<SrcOp, 4> SrcOps;
2422       for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2423         Register PartOpReg = MRI.createGenericVirtualRegister(NarrowTy);
2424         MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
2425         SrcOps.push_back(PartOpReg);
2426       }
2427 
2428       Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy);
2429       MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2430 
2431       Register PartInsertReg = MRI.createGenericVirtualRegister(DstTy);
2432       MIRBuilder.buildInsert(PartInsertReg, AccumDstReg, PartDstReg, Offset);
2433       AccumDstReg = PartInsertReg;
2434     }
2435 
2436     // Handle the remaining element sized leftover piece.
2437     SmallVector<SrcOp, 4> SrcOps;
2438     for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2439       Register PartOpReg = MRI.createGenericVirtualRegister(EltTy);
2440       MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
2441                               BitsForNumParts);
2442       SrcOps.push_back(PartOpReg);
2443     }
2444 
2445     Register PartDstReg = MRI.createGenericVirtualRegister(EltTy);
2446     MIRBuilder.buildInstr(Opc, {PartDstReg}, SrcOps, Flags);
2447     MIRBuilder.buildInsert(DstReg, AccumDstReg, PartDstReg, BitsForNumParts);
2448     MI.eraseFromParent();
2449 
2450     return Legalized;
2451   }
2452 
2453   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2454 
2455   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
2456 
2457   if (NumOps >= 2)
2458     extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
2459 
2460   if (NumOps >= 3)
2461     extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
2462 
2463   for (int i = 0; i < NumParts; ++i) {
2464     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
2465 
2466     if (NumOps == 1)
2467       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i]}, Flags);
2468     else if (NumOps == 2) {
2469       MIRBuilder.buildInstr(Opc, {DstReg}, {Src0Regs[i], Src1Regs[i]}, Flags);
2470     } else if (NumOps == 3) {
2471       MIRBuilder.buildInstr(Opc, {DstReg},
2472                             {Src0Regs[i], Src1Regs[i], Src2Regs[i]}, Flags);
2473     }
2474 
2475     DstRegs.push_back(DstReg);
2476   }
2477 
2478   if (NarrowTy.isVector())
2479     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2480   else
2481     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2482 
2483   MI.eraseFromParent();
2484   return Legalized;
2485 }
2486 
2487 // Handle splitting vector operations which need to have the same number of
2488 // elements in each type index, but each type index may have a different element
2489 // type.
2490 //
2491 // e.g.  <4 x s64> = G_SHL <4 x s64>, <4 x s32> ->
2492 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2493 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2494 //
2495 // Also handles some irregular breakdown cases, e.g.
2496 // e.g.  <3 x s64> = G_SHL <3 x s64>, <3 x s32> ->
2497 //       <2 x s64> = G_SHL <2 x s64>, <2 x s32>
2498 //             s64 = G_SHL s64, s32
2499 LegalizerHelper::LegalizeResult
2500 LegalizerHelper::fewerElementsVectorMultiEltType(
2501   MachineInstr &MI, unsigned TypeIdx, LLT NarrowTyArg) {
2502   if (TypeIdx != 0)
2503     return UnableToLegalize;
2504 
2505   const LLT NarrowTy0 = NarrowTyArg;
2506   const unsigned NewNumElts =
2507       NarrowTy0.isVector() ? NarrowTy0.getNumElements() : 1;
2508 
2509   const Register DstReg = MI.getOperand(0).getReg();
2510   LLT DstTy = MRI.getType(DstReg);
2511   LLT LeftoverTy0;
2512 
2513   // All of the operands need to have the same number of elements, so if we can
2514   // determine a type breakdown for the result type, we can for all of the
2515   // source types.
2516   int NumParts = getNarrowTypeBreakDown(DstTy, NarrowTy0, LeftoverTy0).first;
2517   if (NumParts < 0)
2518     return UnableToLegalize;
2519 
2520   SmallVector<MachineInstrBuilder, 4> NewInsts;
2521 
2522   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2523   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2524 
2525   for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I) {
2526     LLT LeftoverTy;
2527     Register SrcReg = MI.getOperand(I).getReg();
2528     LLT SrcTyI = MRI.getType(SrcReg);
2529     LLT NarrowTyI = LLT::scalarOrVector(NewNumElts, SrcTyI.getScalarType());
2530     LLT LeftoverTyI;
2531 
2532     // Split this operand into the requested typed registers, and any leftover
2533     // required to reproduce the original type.
2534     if (!extractParts(SrcReg, SrcTyI, NarrowTyI, LeftoverTyI, PartRegs,
2535                       LeftoverRegs))
2536       return UnableToLegalize;
2537 
2538     if (I == 1) {
2539       // For the first operand, create an instruction for each part and setup
2540       // the result.
2541       for (Register PartReg : PartRegs) {
2542         Register PartDstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2543         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2544                                .addDef(PartDstReg)
2545                                .addUse(PartReg));
2546         DstRegs.push_back(PartDstReg);
2547       }
2548 
2549       for (Register LeftoverReg : LeftoverRegs) {
2550         Register PartDstReg = MRI.createGenericVirtualRegister(LeftoverTy0);
2551         NewInsts.push_back(MIRBuilder.buildInstrNoInsert(MI.getOpcode())
2552                                .addDef(PartDstReg)
2553                                .addUse(LeftoverReg));
2554         LeftoverDstRegs.push_back(PartDstReg);
2555       }
2556     } else {
2557       assert(NewInsts.size() == PartRegs.size() + LeftoverRegs.size());
2558 
2559       // Add the newly created operand splits to the existing instructions. The
2560       // odd-sized pieces are ordered after the requested NarrowTyArg sized
2561       // pieces.
2562       unsigned InstCount = 0;
2563       for (unsigned J = 0, JE = PartRegs.size(); J != JE; ++J)
2564         NewInsts[InstCount++].addUse(PartRegs[J]);
2565       for (unsigned J = 0, JE = LeftoverRegs.size(); J != JE; ++J)
2566         NewInsts[InstCount++].addUse(LeftoverRegs[J]);
2567     }
2568 
2569     PartRegs.clear();
2570     LeftoverRegs.clear();
2571   }
2572 
2573   // Insert the newly built operations and rebuild the result register.
2574   for (auto &MIB : NewInsts)
2575     MIRBuilder.insertInstr(MIB);
2576 
2577   insertParts(DstReg, DstTy, NarrowTy0, DstRegs, LeftoverTy0, LeftoverDstRegs);
2578 
2579   MI.eraseFromParent();
2580   return Legalized;
2581 }
2582 
2583 LegalizerHelper::LegalizeResult
2584 LegalizerHelper::fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
2585                                           LLT NarrowTy) {
2586   if (TypeIdx != 0)
2587     return UnableToLegalize;
2588 
2589   Register DstReg = MI.getOperand(0).getReg();
2590   Register SrcReg = MI.getOperand(1).getReg();
2591   LLT DstTy = MRI.getType(DstReg);
2592   LLT SrcTy = MRI.getType(SrcReg);
2593 
2594   LLT NarrowTy0 = NarrowTy;
2595   LLT NarrowTy1;
2596   unsigned NumParts;
2597 
2598   if (NarrowTy.isVector()) {
2599     // Uneven breakdown not handled.
2600     NumParts = DstTy.getNumElements() / NarrowTy.getNumElements();
2601     if (NumParts * NarrowTy.getNumElements() != DstTy.getNumElements())
2602       return UnableToLegalize;
2603 
2604     NarrowTy1 = LLT::vector(NumParts, SrcTy.getElementType().getSizeInBits());
2605   } else {
2606     NumParts = DstTy.getNumElements();
2607     NarrowTy1 = SrcTy.getElementType();
2608   }
2609 
2610   SmallVector<Register, 4> SrcRegs, DstRegs;
2611   extractParts(SrcReg, NarrowTy1, NumParts, SrcRegs);
2612 
2613   for (unsigned I = 0; I < NumParts; ++I) {
2614     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2615     MachineInstr *NewInst = MIRBuilder.buildInstr(MI.getOpcode())
2616       .addDef(DstReg)
2617       .addUse(SrcRegs[I]);
2618 
2619     NewInst->setFlags(MI.getFlags());
2620     DstRegs.push_back(DstReg);
2621   }
2622 
2623   if (NarrowTy.isVector())
2624     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2625   else
2626     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2627 
2628   MI.eraseFromParent();
2629   return Legalized;
2630 }
2631 
2632 LegalizerHelper::LegalizeResult
2633 LegalizerHelper::fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx,
2634                                         LLT NarrowTy) {
2635   Register DstReg = MI.getOperand(0).getReg();
2636   Register Src0Reg = MI.getOperand(2).getReg();
2637   LLT DstTy = MRI.getType(DstReg);
2638   LLT SrcTy = MRI.getType(Src0Reg);
2639 
2640   unsigned NumParts;
2641   LLT NarrowTy0, NarrowTy1;
2642 
2643   if (TypeIdx == 0) {
2644     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2645     unsigned OldElts = DstTy.getNumElements();
2646 
2647     NarrowTy0 = NarrowTy;
2648     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) : DstTy.getNumElements();
2649     NarrowTy1 = NarrowTy.isVector() ?
2650       LLT::vector(NarrowTy.getNumElements(), SrcTy.getScalarSizeInBits()) :
2651       SrcTy.getElementType();
2652 
2653   } else {
2654     unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
2655     unsigned OldElts = SrcTy.getNumElements();
2656 
2657     NumParts = NarrowTy.isVector() ? (OldElts / NewElts) :
2658       NarrowTy.getNumElements();
2659     NarrowTy0 = LLT::vector(NarrowTy.getNumElements(),
2660                             DstTy.getScalarSizeInBits());
2661     NarrowTy1 = NarrowTy;
2662   }
2663 
2664   // FIXME: Don't know how to handle the situation where the small vectors
2665   // aren't all the same size yet.
2666   if (NarrowTy1.isVector() &&
2667       NarrowTy1.getNumElements() * NumParts != DstTy.getNumElements())
2668     return UnableToLegalize;
2669 
2670   CmpInst::Predicate Pred
2671     = static_cast<CmpInst::Predicate>(MI.getOperand(1).getPredicate());
2672 
2673   SmallVector<Register, 2> Src1Regs, Src2Regs, DstRegs;
2674   extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
2675   extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
2676 
2677   for (unsigned I = 0; I < NumParts; ++I) {
2678     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2679     DstRegs.push_back(DstReg);
2680 
2681     if (MI.getOpcode() == TargetOpcode::G_ICMP)
2682       MIRBuilder.buildICmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2683     else {
2684       MachineInstr *NewCmp
2685         = MIRBuilder.buildFCmp(Pred, DstReg, Src1Regs[I], Src2Regs[I]);
2686       NewCmp->setFlags(MI.getFlags());
2687     }
2688   }
2689 
2690   if (NarrowTy1.isVector())
2691     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2692   else
2693     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2694 
2695   MI.eraseFromParent();
2696   return Legalized;
2697 }
2698 
2699 LegalizerHelper::LegalizeResult
2700 LegalizerHelper::fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx,
2701                                            LLT NarrowTy) {
2702   Register DstReg = MI.getOperand(0).getReg();
2703   Register CondReg = MI.getOperand(1).getReg();
2704 
2705   unsigned NumParts = 0;
2706   LLT NarrowTy0, NarrowTy1;
2707 
2708   LLT DstTy = MRI.getType(DstReg);
2709   LLT CondTy = MRI.getType(CondReg);
2710   unsigned Size = DstTy.getSizeInBits();
2711 
2712   assert(TypeIdx == 0 || CondTy.isVector());
2713 
2714   if (TypeIdx == 0) {
2715     NarrowTy0 = NarrowTy;
2716     NarrowTy1 = CondTy;
2717 
2718     unsigned NarrowSize = NarrowTy0.getSizeInBits();
2719     // FIXME: Don't know how to handle the situation where the small vectors
2720     // aren't all the same size yet.
2721     if (Size % NarrowSize != 0)
2722       return UnableToLegalize;
2723 
2724     NumParts = Size / NarrowSize;
2725 
2726     // Need to break down the condition type
2727     if (CondTy.isVector()) {
2728       if (CondTy.getNumElements() == NumParts)
2729         NarrowTy1 = CondTy.getElementType();
2730       else
2731         NarrowTy1 = LLT::vector(CondTy.getNumElements() / NumParts,
2732                                 CondTy.getScalarSizeInBits());
2733     }
2734   } else {
2735     NumParts = CondTy.getNumElements();
2736     if (NarrowTy.isVector()) {
2737       // TODO: Handle uneven breakdown.
2738       if (NumParts * NarrowTy.getNumElements() != CondTy.getNumElements())
2739         return UnableToLegalize;
2740 
2741       return UnableToLegalize;
2742     } else {
2743       NarrowTy0 = DstTy.getElementType();
2744       NarrowTy1 = NarrowTy;
2745     }
2746   }
2747 
2748   SmallVector<Register, 2> DstRegs, Src0Regs, Src1Regs, Src2Regs;
2749   if (CondTy.isVector())
2750     extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2751 
2752   extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2753   extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2754 
2755   for (unsigned i = 0; i < NumParts; ++i) {
2756     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy0);
2757     MIRBuilder.buildSelect(DstReg, CondTy.isVector() ? Src0Regs[i] : CondReg,
2758                            Src1Regs[i], Src2Regs[i]);
2759     DstRegs.push_back(DstReg);
2760   }
2761 
2762   if (NarrowTy0.isVector())
2763     MIRBuilder.buildConcatVectors(DstReg, DstRegs);
2764   else
2765     MIRBuilder.buildBuildVector(DstReg, DstRegs);
2766 
2767   MI.eraseFromParent();
2768   return Legalized;
2769 }
2770 
2771 LegalizerHelper::LegalizeResult
2772 LegalizerHelper::fewerElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
2773                                         LLT NarrowTy) {
2774   const Register DstReg = MI.getOperand(0).getReg();
2775   LLT PhiTy = MRI.getType(DstReg);
2776   LLT LeftoverTy;
2777 
2778   // All of the operands need to have the same number of elements, so if we can
2779   // determine a type breakdown for the result type, we can for all of the
2780   // source types.
2781   int NumParts, NumLeftover;
2782   std::tie(NumParts, NumLeftover)
2783     = getNarrowTypeBreakDown(PhiTy, NarrowTy, LeftoverTy);
2784   if (NumParts < 0)
2785     return UnableToLegalize;
2786 
2787   SmallVector<Register, 4> DstRegs, LeftoverDstRegs;
2788   SmallVector<MachineInstrBuilder, 4> NewInsts;
2789 
2790   const int TotalNumParts = NumParts + NumLeftover;
2791 
2792   // Insert the new phis in the result block first.
2793   for (int I = 0; I != TotalNumParts; ++I) {
2794     LLT Ty = I < NumParts ? NarrowTy : LeftoverTy;
2795     Register PartDstReg = MRI.createGenericVirtualRegister(Ty);
2796     NewInsts.push_back(MIRBuilder.buildInstr(TargetOpcode::G_PHI)
2797                        .addDef(PartDstReg));
2798     if (I < NumParts)
2799       DstRegs.push_back(PartDstReg);
2800     else
2801       LeftoverDstRegs.push_back(PartDstReg);
2802   }
2803 
2804   MachineBasicBlock *MBB = MI.getParent();
2805   MIRBuilder.setInsertPt(*MBB, MBB->getFirstNonPHI());
2806   insertParts(DstReg, PhiTy, NarrowTy, DstRegs, LeftoverTy, LeftoverDstRegs);
2807 
2808   SmallVector<Register, 4> PartRegs, LeftoverRegs;
2809 
2810   // Insert code to extract the incoming values in each predecessor block.
2811   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
2812     PartRegs.clear();
2813     LeftoverRegs.clear();
2814 
2815     Register SrcReg = MI.getOperand(I).getReg();
2816     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
2817     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
2818 
2819     LLT Unused;
2820     if (!extractParts(SrcReg, PhiTy, NarrowTy, Unused, PartRegs,
2821                       LeftoverRegs))
2822       return UnableToLegalize;
2823 
2824     // Add the newly created operand splits to the existing instructions. The
2825     // odd-sized pieces are ordered after the requested NarrowTyArg sized
2826     // pieces.
2827     for (int J = 0; J != TotalNumParts; ++J) {
2828       MachineInstrBuilder MIB = NewInsts[J];
2829       MIB.addUse(J < NumParts ? PartRegs[J] : LeftoverRegs[J - NumParts]);
2830       MIB.addMBB(&OpMBB);
2831     }
2832   }
2833 
2834   MI.eraseFromParent();
2835   return Legalized;
2836 }
2837 
2838 LegalizerHelper::LegalizeResult
2839 LegalizerHelper::fewerElementsVectorUnmergeValues(MachineInstr &MI,
2840                                                   unsigned TypeIdx,
2841                                                   LLT NarrowTy) {
2842   if (TypeIdx != 1)
2843     return UnableToLegalize;
2844 
2845   const int NumDst = MI.getNumOperands() - 1;
2846   const Register SrcReg = MI.getOperand(NumDst).getReg();
2847   LLT SrcTy = MRI.getType(SrcReg);
2848 
2849   LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2850 
2851   // TODO: Create sequence of extracts.
2852   if (DstTy == NarrowTy)
2853     return UnableToLegalize;
2854 
2855   LLT GCDTy = getGCDType(SrcTy, NarrowTy);
2856   if (DstTy == GCDTy) {
2857     // This would just be a copy of the same unmerge.
2858     // TODO: Create extracts, pad with undef and create intermediate merges.
2859     return UnableToLegalize;
2860   }
2861 
2862   auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
2863   const int NumUnmerge = Unmerge->getNumOperands() - 1;
2864   const int PartsPerUnmerge = NumDst / NumUnmerge;
2865 
2866   for (int I = 0; I != NumUnmerge; ++I) {
2867     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
2868 
2869     for (int J = 0; J != PartsPerUnmerge; ++J)
2870       MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg());
2871     MIB.addUse(Unmerge.getReg(I));
2872   }
2873 
2874   MI.eraseFromParent();
2875   return Legalized;
2876 }
2877 
2878 LegalizerHelper::LegalizeResult
2879 LegalizerHelper::fewerElementsVectorBuildVector(MachineInstr &MI,
2880                                                 unsigned TypeIdx,
2881                                                 LLT NarrowTy) {
2882   assert(TypeIdx == 0 && "not a vector type index");
2883   Register DstReg = MI.getOperand(0).getReg();
2884   LLT DstTy = MRI.getType(DstReg);
2885   LLT SrcTy = DstTy.getElementType();
2886 
2887   int DstNumElts = DstTy.getNumElements();
2888   int NarrowNumElts = NarrowTy.getNumElements();
2889   int NumConcat = (DstNumElts + NarrowNumElts - 1) / NarrowNumElts;
2890   LLT WidenedDstTy = LLT::vector(NarrowNumElts * NumConcat, SrcTy);
2891 
2892   SmallVector<Register, 8> ConcatOps;
2893   SmallVector<Register, 8> SubBuildVector;
2894 
2895   Register UndefReg;
2896   if (WidenedDstTy != DstTy)
2897     UndefReg = MIRBuilder.buildUndef(SrcTy).getReg(0);
2898 
2899   // Create a G_CONCAT_VECTORS of NarrowTy pieces, padding with undef as
2900   // necessary.
2901   //
2902   // %3:_(<3 x s16>) = G_BUILD_VECTOR %0, %1, %2
2903   //   -> <2 x s16>
2904   //
2905   // %4:_(s16) = G_IMPLICIT_DEF
2906   // %5:_(<2 x s16>) = G_BUILD_VECTOR %0, %1
2907   // %6:_(<2 x s16>) = G_BUILD_VECTOR %2, %4
2908   // %7:_(<4 x s16>) = G_CONCAT_VECTORS %5, %6
2909   // %3:_(<3 x s16>) = G_EXTRACT %7, 0
2910   for (int I = 0; I != NumConcat; ++I) {
2911     for (int J = 0; J != NarrowNumElts; ++J) {
2912       int SrcIdx = NarrowNumElts * I + J;
2913 
2914       if (SrcIdx < DstNumElts) {
2915         Register SrcReg = MI.getOperand(SrcIdx + 1).getReg();
2916         SubBuildVector.push_back(SrcReg);
2917       } else
2918         SubBuildVector.push_back(UndefReg);
2919     }
2920 
2921     auto BuildVec = MIRBuilder.buildBuildVector(NarrowTy, SubBuildVector);
2922     ConcatOps.push_back(BuildVec.getReg(0));
2923     SubBuildVector.clear();
2924   }
2925 
2926   if (DstTy == WidenedDstTy)
2927     MIRBuilder.buildConcatVectors(DstReg, ConcatOps);
2928   else {
2929     auto Concat = MIRBuilder.buildConcatVectors(WidenedDstTy, ConcatOps);
2930     MIRBuilder.buildExtract(DstReg, Concat, 0);
2931   }
2932 
2933   MI.eraseFromParent();
2934   return Legalized;
2935 }
2936 
2937 LegalizerHelper::LegalizeResult
2938 LegalizerHelper::reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx,
2939                                       LLT NarrowTy) {
2940   // FIXME: Don't know how to handle secondary types yet.
2941   if (TypeIdx != 0)
2942     return UnableToLegalize;
2943 
2944   MachineMemOperand *MMO = *MI.memoperands_begin();
2945 
2946   // This implementation doesn't work for atomics. Give up instead of doing
2947   // something invalid.
2948   if (MMO->getOrdering() != AtomicOrdering::NotAtomic ||
2949       MMO->getFailureOrdering() != AtomicOrdering::NotAtomic)
2950     return UnableToLegalize;
2951 
2952   bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD;
2953   Register ValReg = MI.getOperand(0).getReg();
2954   Register AddrReg = MI.getOperand(1).getReg();
2955   LLT ValTy = MRI.getType(ValReg);
2956 
2957   int NumParts = -1;
2958   int NumLeftover = -1;
2959   LLT LeftoverTy;
2960   SmallVector<Register, 8> NarrowRegs, NarrowLeftoverRegs;
2961   if (IsLoad) {
2962     std::tie(NumParts, NumLeftover) = getNarrowTypeBreakDown(ValTy, NarrowTy, LeftoverTy);
2963   } else {
2964     if (extractParts(ValReg, ValTy, NarrowTy, LeftoverTy, NarrowRegs,
2965                      NarrowLeftoverRegs)) {
2966       NumParts = NarrowRegs.size();
2967       NumLeftover = NarrowLeftoverRegs.size();
2968     }
2969   }
2970 
2971   if (NumParts == -1)
2972     return UnableToLegalize;
2973 
2974   const LLT OffsetTy = LLT::scalar(MRI.getType(AddrReg).getScalarSizeInBits());
2975 
2976   unsigned TotalSize = ValTy.getSizeInBits();
2977 
2978   // Split the load/store into PartTy sized pieces starting at Offset. If this
2979   // is a load, return the new registers in ValRegs. For a store, each elements
2980   // of ValRegs should be PartTy. Returns the next offset that needs to be
2981   // handled.
2982   auto splitTypePieces = [=](LLT PartTy, SmallVectorImpl<Register> &ValRegs,
2983                              unsigned Offset) -> unsigned {
2984     MachineFunction &MF = MIRBuilder.getMF();
2985     unsigned PartSize = PartTy.getSizeInBits();
2986     for (unsigned Idx = 0, E = NumParts; Idx != E && Offset < TotalSize;
2987          Offset += PartSize, ++Idx) {
2988       unsigned ByteSize = PartSize / 8;
2989       unsigned ByteOffset = Offset / 8;
2990       Register NewAddrReg;
2991 
2992       MIRBuilder.materializePtrAdd(NewAddrReg, AddrReg, OffsetTy, ByteOffset);
2993 
2994       MachineMemOperand *NewMMO =
2995         MF.getMachineMemOperand(MMO, ByteOffset, ByteSize);
2996 
2997       if (IsLoad) {
2998         Register Dst = MRI.createGenericVirtualRegister(PartTy);
2999         ValRegs.push_back(Dst);
3000         MIRBuilder.buildLoad(Dst, NewAddrReg, *NewMMO);
3001       } else {
3002         MIRBuilder.buildStore(ValRegs[Idx], NewAddrReg, *NewMMO);
3003       }
3004     }
3005 
3006     return Offset;
3007   };
3008 
3009   unsigned HandledOffset = splitTypePieces(NarrowTy, NarrowRegs, 0);
3010 
3011   // Handle the rest of the register if this isn't an even type breakdown.
3012   if (LeftoverTy.isValid())
3013     splitTypePieces(LeftoverTy, NarrowLeftoverRegs, HandledOffset);
3014 
3015   if (IsLoad) {
3016     insertParts(ValReg, ValTy, NarrowTy, NarrowRegs,
3017                 LeftoverTy, NarrowLeftoverRegs);
3018   }
3019 
3020   MI.eraseFromParent();
3021   return Legalized;
3022 }
3023 
3024 LegalizerHelper::LegalizeResult
3025 LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
3026                                      LLT NarrowTy) {
3027   using namespace TargetOpcode;
3028 
3029   MIRBuilder.setInstr(MI);
3030   switch (MI.getOpcode()) {
3031   case G_IMPLICIT_DEF:
3032     return fewerElementsVectorImplicitDef(MI, TypeIdx, NarrowTy);
3033   case G_AND:
3034   case G_OR:
3035   case G_XOR:
3036   case G_ADD:
3037   case G_SUB:
3038   case G_MUL:
3039   case G_SMULH:
3040   case G_UMULH:
3041   case G_FADD:
3042   case G_FMUL:
3043   case G_FSUB:
3044   case G_FNEG:
3045   case G_FABS:
3046   case G_FCANONICALIZE:
3047   case G_FDIV:
3048   case G_FREM:
3049   case G_FMA:
3050   case G_FMAD:
3051   case G_FPOW:
3052   case G_FEXP:
3053   case G_FEXP2:
3054   case G_FLOG:
3055   case G_FLOG2:
3056   case G_FLOG10:
3057   case G_FNEARBYINT:
3058   case G_FCEIL:
3059   case G_FFLOOR:
3060   case G_FRINT:
3061   case G_INTRINSIC_ROUND:
3062   case G_INTRINSIC_TRUNC:
3063   case G_FCOS:
3064   case G_FSIN:
3065   case G_FSQRT:
3066   case G_BSWAP:
3067   case G_BITREVERSE:
3068   case G_SDIV:
3069   case G_UDIV:
3070   case G_SREM:
3071   case G_UREM:
3072   case G_SMIN:
3073   case G_SMAX:
3074   case G_UMIN:
3075   case G_UMAX:
3076   case G_FMINNUM:
3077   case G_FMAXNUM:
3078   case G_FMINNUM_IEEE:
3079   case G_FMAXNUM_IEEE:
3080   case G_FMINIMUM:
3081   case G_FMAXIMUM:
3082     return fewerElementsVectorBasic(MI, TypeIdx, NarrowTy);
3083   case G_SHL:
3084   case G_LSHR:
3085   case G_ASHR:
3086   case G_CTLZ:
3087   case G_CTLZ_ZERO_UNDEF:
3088   case G_CTTZ:
3089   case G_CTTZ_ZERO_UNDEF:
3090   case G_CTPOP:
3091   case G_FCOPYSIGN:
3092     return fewerElementsVectorMultiEltType(MI, TypeIdx, NarrowTy);
3093   case G_ZEXT:
3094   case G_SEXT:
3095   case G_ANYEXT:
3096   case G_FPEXT:
3097   case G_FPTRUNC:
3098   case G_SITOFP:
3099   case G_UITOFP:
3100   case G_FPTOSI:
3101   case G_FPTOUI:
3102   case G_INTTOPTR:
3103   case G_PTRTOINT:
3104   case G_ADDRSPACE_CAST:
3105     return fewerElementsVectorCasts(MI, TypeIdx, NarrowTy);
3106   case G_ICMP:
3107   case G_FCMP:
3108     return fewerElementsVectorCmp(MI, TypeIdx, NarrowTy);
3109   case G_SELECT:
3110     return fewerElementsVectorSelect(MI, TypeIdx, NarrowTy);
3111   case G_PHI:
3112     return fewerElementsVectorPhi(MI, TypeIdx, NarrowTy);
3113   case G_UNMERGE_VALUES:
3114     return fewerElementsVectorUnmergeValues(MI, TypeIdx, NarrowTy);
3115   case G_BUILD_VECTOR:
3116     return fewerElementsVectorBuildVector(MI, TypeIdx, NarrowTy);
3117   case G_LOAD:
3118   case G_STORE:
3119     return reduceLoadStoreWidth(MI, TypeIdx, NarrowTy);
3120   default:
3121     return UnableToLegalize;
3122   }
3123 }
3124 
3125 LegalizerHelper::LegalizeResult
3126 LegalizerHelper::narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
3127                                              const LLT HalfTy, const LLT AmtTy) {
3128 
3129   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3130   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3131   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3132 
3133   if (Amt.isNullValue()) {
3134     MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
3135     MI.eraseFromParent();
3136     return Legalized;
3137   }
3138 
3139   LLT NVT = HalfTy;
3140   unsigned NVTBits = HalfTy.getSizeInBits();
3141   unsigned VTBits = 2 * NVTBits;
3142 
3143   SrcOp Lo(Register(0)), Hi(Register(0));
3144   if (MI.getOpcode() == TargetOpcode::G_SHL) {
3145     if (Amt.ugt(VTBits)) {
3146       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3147     } else if (Amt.ugt(NVTBits)) {
3148       Lo = MIRBuilder.buildConstant(NVT, 0);
3149       Hi = MIRBuilder.buildShl(NVT, InL,
3150                                MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3151     } else if (Amt == NVTBits) {
3152       Lo = MIRBuilder.buildConstant(NVT, 0);
3153       Hi = InL;
3154     } else {
3155       Lo = MIRBuilder.buildShl(NVT, InL, MIRBuilder.buildConstant(AmtTy, Amt));
3156       auto OrLHS =
3157           MIRBuilder.buildShl(NVT, InH, MIRBuilder.buildConstant(AmtTy, Amt));
3158       auto OrRHS = MIRBuilder.buildLShr(
3159           NVT, InL, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3160       Hi = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3161     }
3162   } else if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3163     if (Amt.ugt(VTBits)) {
3164       Lo = Hi = MIRBuilder.buildConstant(NVT, 0);
3165     } else if (Amt.ugt(NVTBits)) {
3166       Lo = MIRBuilder.buildLShr(NVT, InH,
3167                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3168       Hi = MIRBuilder.buildConstant(NVT, 0);
3169     } else if (Amt == NVTBits) {
3170       Lo = InH;
3171       Hi = MIRBuilder.buildConstant(NVT, 0);
3172     } else {
3173       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3174 
3175       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3176       auto OrRHS = MIRBuilder.buildShl(
3177           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3178 
3179       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3180       Hi = MIRBuilder.buildLShr(NVT, InH, ShiftAmtConst);
3181     }
3182   } else {
3183     if (Amt.ugt(VTBits)) {
3184       Hi = Lo = MIRBuilder.buildAShr(
3185           NVT, InH, MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3186     } else if (Amt.ugt(NVTBits)) {
3187       Lo = MIRBuilder.buildAShr(NVT, InH,
3188                                 MIRBuilder.buildConstant(AmtTy, Amt - NVTBits));
3189       Hi = MIRBuilder.buildAShr(NVT, InH,
3190                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3191     } else if (Amt == NVTBits) {
3192       Lo = InH;
3193       Hi = MIRBuilder.buildAShr(NVT, InH,
3194                                 MIRBuilder.buildConstant(AmtTy, NVTBits - 1));
3195     } else {
3196       auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3197 
3198       auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3199       auto OrRHS = MIRBuilder.buildShl(
3200           NVT, InH, MIRBuilder.buildConstant(AmtTy, -Amt + NVTBits));
3201 
3202       Lo = MIRBuilder.buildOr(NVT, OrLHS, OrRHS);
3203       Hi = MIRBuilder.buildAShr(NVT, InH, ShiftAmtConst);
3204     }
3205   }
3206 
3207   MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
3208   MI.eraseFromParent();
3209 
3210   return Legalized;
3211 }
3212 
3213 // TODO: Optimize if constant shift amount.
3214 LegalizerHelper::LegalizeResult
3215 LegalizerHelper::narrowScalarShift(MachineInstr &MI, unsigned TypeIdx,
3216                                    LLT RequestedTy) {
3217   if (TypeIdx == 1) {
3218     Observer.changingInstr(MI);
3219     narrowScalarSrc(MI, RequestedTy, 2);
3220     Observer.changedInstr(MI);
3221     return Legalized;
3222   }
3223 
3224   Register DstReg = MI.getOperand(0).getReg();
3225   LLT DstTy = MRI.getType(DstReg);
3226   if (DstTy.isVector())
3227     return UnableToLegalize;
3228 
3229   Register Amt = MI.getOperand(2).getReg();
3230   LLT ShiftAmtTy = MRI.getType(Amt);
3231   const unsigned DstEltSize = DstTy.getScalarSizeInBits();
3232   if (DstEltSize % 2 != 0)
3233     return UnableToLegalize;
3234 
3235   // Ignore the input type. We can only go to exactly half the size of the
3236   // input. If that isn't small enough, the resulting pieces will be further
3237   // legalized.
3238   const unsigned NewBitSize = DstEltSize / 2;
3239   const LLT HalfTy = LLT::scalar(NewBitSize);
3240   const LLT CondTy = LLT::scalar(1);
3241 
3242   if (const MachineInstr *KShiftAmt =
3243           getOpcodeDef(TargetOpcode::G_CONSTANT, Amt, MRI)) {
3244     return narrowScalarShiftByConstant(
3245         MI, KShiftAmt->getOperand(1).getCImm()->getValue(), HalfTy, ShiftAmtTy);
3246   }
3247 
3248   // TODO: Expand with known bits.
3249 
3250   // Handle the fully general expansion by an unknown amount.
3251   auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
3252 
3253   Register InL = MRI.createGenericVirtualRegister(HalfTy);
3254   Register InH = MRI.createGenericVirtualRegister(HalfTy);
3255   MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3256 
3257   auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
3258   auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
3259 
3260   auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
3261   auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
3262   auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
3263 
3264   Register ResultRegs[2];
3265   switch (MI.getOpcode()) {
3266   case TargetOpcode::G_SHL: {
3267     // Short: ShAmt < NewBitSize
3268     auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt);
3269 
3270     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
3271     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt);
3272     auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3273 
3274     // Long: ShAmt >= NewBitSize
3275     auto LoL = MIRBuilder.buildConstant(HalfTy, 0);         // Lo part is zero.
3276     auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
3277 
3278     auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
3279     auto Hi = MIRBuilder.buildSelect(
3280         HalfTy, IsZero, InH, MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL));
3281 
3282     ResultRegs[0] = Lo.getReg(0);
3283     ResultRegs[1] = Hi.getReg(0);
3284     break;
3285   }
3286   case TargetOpcode::G_LSHR:
3287   case TargetOpcode::G_ASHR: {
3288     // Short: ShAmt < NewBitSize
3289     auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt});
3290 
3291     auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt);
3292     auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
3293     auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3294 
3295     // Long: ShAmt >= NewBitSize
3296     MachineInstrBuilder HiL;
3297     if (MI.getOpcode() == TargetOpcode::G_LSHR) {
3298       HiL = MIRBuilder.buildConstant(HalfTy, 0);            // Hi part is zero.
3299     } else {
3300       auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1);
3301       HiL = MIRBuilder.buildAShr(HalfTy, InH, ShiftAmt);    // Sign of Hi part.
3302     }
3303     auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy},
3304                                      {InH, AmtExcess});     // Lo from Hi part.
3305 
3306     auto Lo = MIRBuilder.buildSelect(
3307         HalfTy, IsZero, InL, MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL));
3308 
3309     auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
3310 
3311     ResultRegs[0] = Lo.getReg(0);
3312     ResultRegs[1] = Hi.getReg(0);
3313     break;
3314   }
3315   default:
3316     llvm_unreachable("not a shift");
3317   }
3318 
3319   MIRBuilder.buildMerge(DstReg, ResultRegs);
3320   MI.eraseFromParent();
3321   return Legalized;
3322 }
3323 
3324 LegalizerHelper::LegalizeResult
3325 LegalizerHelper::moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
3326                                        LLT MoreTy) {
3327   assert(TypeIdx == 0 && "Expecting only Idx 0");
3328 
3329   Observer.changingInstr(MI);
3330   for (unsigned I = 1, E = MI.getNumOperands(); I != E; I += 2) {
3331     MachineBasicBlock &OpMBB = *MI.getOperand(I + 1).getMBB();
3332     MIRBuilder.setInsertPt(OpMBB, OpMBB.getFirstTerminator());
3333     moreElementsVectorSrc(MI, MoreTy, I);
3334   }
3335 
3336   MachineBasicBlock &MBB = *MI.getParent();
3337   MIRBuilder.setInsertPt(MBB, --MBB.getFirstNonPHI());
3338   moreElementsVectorDst(MI, MoreTy, 0);
3339   Observer.changedInstr(MI);
3340   return Legalized;
3341 }
3342 
3343 LegalizerHelper::LegalizeResult
3344 LegalizerHelper::moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
3345                                     LLT MoreTy) {
3346   MIRBuilder.setInstr(MI);
3347   unsigned Opc = MI.getOpcode();
3348   switch (Opc) {
3349   case TargetOpcode::G_IMPLICIT_DEF:
3350   case TargetOpcode::G_LOAD: {
3351     if (TypeIdx != 0)
3352       return UnableToLegalize;
3353     Observer.changingInstr(MI);
3354     moreElementsVectorDst(MI, MoreTy, 0);
3355     Observer.changedInstr(MI);
3356     return Legalized;
3357   }
3358   case TargetOpcode::G_STORE:
3359     if (TypeIdx != 0)
3360       return UnableToLegalize;
3361     Observer.changingInstr(MI);
3362     moreElementsVectorSrc(MI, MoreTy, 0);
3363     Observer.changedInstr(MI);
3364     return Legalized;
3365   case TargetOpcode::G_AND:
3366   case TargetOpcode::G_OR:
3367   case TargetOpcode::G_XOR:
3368   case TargetOpcode::G_SMIN:
3369   case TargetOpcode::G_SMAX:
3370   case TargetOpcode::G_UMIN:
3371   case TargetOpcode::G_UMAX:
3372   case TargetOpcode::G_FMINNUM:
3373   case TargetOpcode::G_FMAXNUM:
3374   case TargetOpcode::G_FMINNUM_IEEE:
3375   case TargetOpcode::G_FMAXNUM_IEEE:
3376   case TargetOpcode::G_FMINIMUM:
3377   case TargetOpcode::G_FMAXIMUM: {
3378     Observer.changingInstr(MI);
3379     moreElementsVectorSrc(MI, MoreTy, 1);
3380     moreElementsVectorSrc(MI, MoreTy, 2);
3381     moreElementsVectorDst(MI, MoreTy, 0);
3382     Observer.changedInstr(MI);
3383     return Legalized;
3384   }
3385   case TargetOpcode::G_EXTRACT:
3386     if (TypeIdx != 1)
3387       return UnableToLegalize;
3388     Observer.changingInstr(MI);
3389     moreElementsVectorSrc(MI, MoreTy, 1);
3390     Observer.changedInstr(MI);
3391     return Legalized;
3392   case TargetOpcode::G_INSERT:
3393     if (TypeIdx != 0)
3394       return UnableToLegalize;
3395     Observer.changingInstr(MI);
3396     moreElementsVectorSrc(MI, MoreTy, 1);
3397     moreElementsVectorDst(MI, MoreTy, 0);
3398     Observer.changedInstr(MI);
3399     return Legalized;
3400   case TargetOpcode::G_SELECT:
3401     if (TypeIdx != 0)
3402       return UnableToLegalize;
3403     if (MRI.getType(MI.getOperand(1).getReg()).isVector())
3404       return UnableToLegalize;
3405 
3406     Observer.changingInstr(MI);
3407     moreElementsVectorSrc(MI, MoreTy, 2);
3408     moreElementsVectorSrc(MI, MoreTy, 3);
3409     moreElementsVectorDst(MI, MoreTy, 0);
3410     Observer.changedInstr(MI);
3411     return Legalized;
3412   case TargetOpcode::G_UNMERGE_VALUES: {
3413     if (TypeIdx != 1)
3414       return UnableToLegalize;
3415 
3416     LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
3417     int NumDst = MI.getNumOperands() - 1;
3418     moreElementsVectorSrc(MI, MoreTy, NumDst);
3419 
3420     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
3421     for (int I = 0; I != NumDst; ++I)
3422       MIB.addDef(MI.getOperand(I).getReg());
3423 
3424     int NewNumDst = MoreTy.getSizeInBits() / DstTy.getSizeInBits();
3425     for (int I = NumDst; I != NewNumDst; ++I)
3426       MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
3427 
3428     MIB.addUse(MI.getOperand(NumDst).getReg());
3429     MI.eraseFromParent();
3430     return Legalized;
3431   }
3432   case TargetOpcode::G_PHI:
3433     return moreElementsVectorPhi(MI, TypeIdx, MoreTy);
3434   default:
3435     return UnableToLegalize;
3436   }
3437 }
3438 
3439 void LegalizerHelper::multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
3440                                         ArrayRef<Register> Src1Regs,
3441                                         ArrayRef<Register> Src2Regs,
3442                                         LLT NarrowTy) {
3443   MachineIRBuilder &B = MIRBuilder;
3444   unsigned SrcParts = Src1Regs.size();
3445   unsigned DstParts = DstRegs.size();
3446 
3447   unsigned DstIdx = 0; // Low bits of the result.
3448   Register FactorSum =
3449       B.buildMul(NarrowTy, Src1Regs[DstIdx], Src2Regs[DstIdx]).getReg(0);
3450   DstRegs[DstIdx] = FactorSum;
3451 
3452   unsigned CarrySumPrevDstIdx;
3453   SmallVector<Register, 4> Factors;
3454 
3455   for (DstIdx = 1; DstIdx < DstParts; DstIdx++) {
3456     // Collect low parts of muls for DstIdx.
3457     for (unsigned i = DstIdx + 1 < SrcParts ? 0 : DstIdx - SrcParts + 1;
3458          i <= std::min(DstIdx, SrcParts - 1); ++i) {
3459       MachineInstrBuilder Mul =
3460           B.buildMul(NarrowTy, Src1Regs[DstIdx - i], Src2Regs[i]);
3461       Factors.push_back(Mul.getReg(0));
3462     }
3463     // Collect high parts of muls from previous DstIdx.
3464     for (unsigned i = DstIdx < SrcParts ? 0 : DstIdx - SrcParts;
3465          i <= std::min(DstIdx - 1, SrcParts - 1); ++i) {
3466       MachineInstrBuilder Umulh =
3467           B.buildUMulH(NarrowTy, Src1Regs[DstIdx - 1 - i], Src2Regs[i]);
3468       Factors.push_back(Umulh.getReg(0));
3469     }
3470     // Add CarrySum from additions calculated for previous DstIdx.
3471     if (DstIdx != 1) {
3472       Factors.push_back(CarrySumPrevDstIdx);
3473     }
3474 
3475     Register CarrySum;
3476     // Add all factors and accumulate all carries into CarrySum.
3477     if (DstIdx != DstParts - 1) {
3478       MachineInstrBuilder Uaddo =
3479           B.buildUAddo(NarrowTy, LLT::scalar(1), Factors[0], Factors[1]);
3480       FactorSum = Uaddo.getReg(0);
3481       CarrySum = B.buildZExt(NarrowTy, Uaddo.getReg(1)).getReg(0);
3482       for (unsigned i = 2; i < Factors.size(); ++i) {
3483         MachineInstrBuilder Uaddo =
3484             B.buildUAddo(NarrowTy, LLT::scalar(1), FactorSum, Factors[i]);
3485         FactorSum = Uaddo.getReg(0);
3486         MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
3487         CarrySum = B.buildAdd(NarrowTy, CarrySum, Carry).getReg(0);
3488       }
3489     } else {
3490       // Since value for the next index is not calculated, neither is CarrySum.
3491       FactorSum = B.buildAdd(NarrowTy, Factors[0], Factors[1]).getReg(0);
3492       for (unsigned i = 2; i < Factors.size(); ++i)
3493         FactorSum = B.buildAdd(NarrowTy, FactorSum, Factors[i]).getReg(0);
3494     }
3495 
3496     CarrySumPrevDstIdx = CarrySum;
3497     DstRegs[DstIdx] = FactorSum;
3498     Factors.clear();
3499   }
3500 }
3501 
3502 LegalizerHelper::LegalizeResult
3503 LegalizerHelper::narrowScalarMul(MachineInstr &MI, LLT NarrowTy) {
3504   Register DstReg = MI.getOperand(0).getReg();
3505   Register Src1 = MI.getOperand(1).getReg();
3506   Register Src2 = MI.getOperand(2).getReg();
3507 
3508   LLT Ty = MRI.getType(DstReg);
3509   if (Ty.isVector())
3510     return UnableToLegalize;
3511 
3512   unsigned SrcSize = MRI.getType(Src1).getSizeInBits();
3513   unsigned DstSize = Ty.getSizeInBits();
3514   unsigned NarrowSize = NarrowTy.getSizeInBits();
3515   if (DstSize % NarrowSize != 0 || SrcSize % NarrowSize != 0)
3516     return UnableToLegalize;
3517 
3518   unsigned NumDstParts = DstSize / NarrowSize;
3519   unsigned NumSrcParts = SrcSize / NarrowSize;
3520   bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
3521   unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
3522 
3523   SmallVector<Register, 2> Src1Parts, Src2Parts, DstTmpRegs;
3524   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
3525   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
3526   DstTmpRegs.resize(DstTmpParts);
3527   multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
3528 
3529   // Take only high half of registers if this is high mul.
3530   ArrayRef<Register> DstRegs(
3531       IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
3532   MIRBuilder.buildMerge(DstReg, DstRegs);
3533   MI.eraseFromParent();
3534   return Legalized;
3535 }
3536 
3537 LegalizerHelper::LegalizeResult
3538 LegalizerHelper::narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx,
3539                                      LLT NarrowTy) {
3540   if (TypeIdx != 1)
3541     return UnableToLegalize;
3542 
3543   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3544 
3545   int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
3546   // FIXME: add support for when SizeOp1 isn't an exact multiple of
3547   // NarrowSize.
3548   if (SizeOp1 % NarrowSize != 0)
3549     return UnableToLegalize;
3550   int NumParts = SizeOp1 / NarrowSize;
3551 
3552   SmallVector<Register, 2> SrcRegs, DstRegs;
3553   SmallVector<uint64_t, 2> Indexes;
3554   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3555 
3556   Register OpReg = MI.getOperand(0).getReg();
3557   uint64_t OpStart = MI.getOperand(2).getImm();
3558   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3559   for (int i = 0; i < NumParts; ++i) {
3560     unsigned SrcStart = i * NarrowSize;
3561 
3562     if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) {
3563       // No part of the extract uses this subregister, ignore it.
3564       continue;
3565     } else if (SrcStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3566       // The entire subregister is extracted, forward the value.
3567       DstRegs.push_back(SrcRegs[i]);
3568       continue;
3569     }
3570 
3571     // OpSegStart is where this destination segment would start in OpReg if it
3572     // extended infinitely in both directions.
3573     int64_t ExtractOffset;
3574     uint64_t SegSize;
3575     if (OpStart < SrcStart) {
3576       ExtractOffset = 0;
3577       SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart);
3578     } else {
3579       ExtractOffset = OpStart - SrcStart;
3580       SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize);
3581     }
3582 
3583     Register SegReg = SrcRegs[i];
3584     if (ExtractOffset != 0 || SegSize != NarrowSize) {
3585       // A genuine extract is needed.
3586       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3587       MIRBuilder.buildExtract(SegReg, SrcRegs[i], ExtractOffset);
3588     }
3589 
3590     DstRegs.push_back(SegReg);
3591   }
3592 
3593   Register DstReg = MI.getOperand(0).getReg();
3594   if(MRI.getType(DstReg).isVector())
3595     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3596   else
3597     MIRBuilder.buildMerge(DstReg, DstRegs);
3598   MI.eraseFromParent();
3599   return Legalized;
3600 }
3601 
3602 LegalizerHelper::LegalizeResult
3603 LegalizerHelper::narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx,
3604                                     LLT NarrowTy) {
3605   // FIXME: Don't know how to handle secondary types yet.
3606   if (TypeIdx != 0)
3607     return UnableToLegalize;
3608 
3609   uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
3610   uint64_t NarrowSize = NarrowTy.getSizeInBits();
3611 
3612   // FIXME: add support for when SizeOp0 isn't an exact multiple of
3613   // NarrowSize.
3614   if (SizeOp0 % NarrowSize != 0)
3615     return UnableToLegalize;
3616 
3617   int NumParts = SizeOp0 / NarrowSize;
3618 
3619   SmallVector<Register, 2> SrcRegs, DstRegs;
3620   SmallVector<uint64_t, 2> Indexes;
3621   extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3622 
3623   Register OpReg = MI.getOperand(2).getReg();
3624   uint64_t OpStart = MI.getOperand(3).getImm();
3625   uint64_t OpSize = MRI.getType(OpReg).getSizeInBits();
3626   for (int i = 0; i < NumParts; ++i) {
3627     unsigned DstStart = i * NarrowSize;
3628 
3629     if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) {
3630       // No part of the insert affects this subregister, forward the original.
3631       DstRegs.push_back(SrcRegs[i]);
3632       continue;
3633     } else if (DstStart == OpStart && NarrowTy == MRI.getType(OpReg)) {
3634       // The entire subregister is defined by this insert, forward the new
3635       // value.
3636       DstRegs.push_back(OpReg);
3637       continue;
3638     }
3639 
3640     // OpSegStart is where this destination segment would start in OpReg if it
3641     // extended infinitely in both directions.
3642     int64_t ExtractOffset, InsertOffset;
3643     uint64_t SegSize;
3644     if (OpStart < DstStart) {
3645       InsertOffset = 0;
3646       ExtractOffset = DstStart - OpStart;
3647       SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart);
3648     } else {
3649       InsertOffset = OpStart - DstStart;
3650       ExtractOffset = 0;
3651       SegSize =
3652         std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart);
3653     }
3654 
3655     Register SegReg = OpReg;
3656     if (ExtractOffset != 0 || SegSize != OpSize) {
3657       // A genuine extract is needed.
3658       SegReg = MRI.createGenericVirtualRegister(LLT::scalar(SegSize));
3659       MIRBuilder.buildExtract(SegReg, OpReg, ExtractOffset);
3660     }
3661 
3662     Register DstReg = MRI.createGenericVirtualRegister(NarrowTy);
3663     MIRBuilder.buildInsert(DstReg, SrcRegs[i], SegReg, InsertOffset);
3664     DstRegs.push_back(DstReg);
3665   }
3666 
3667   assert(DstRegs.size() == (unsigned)NumParts && "not all parts covered");
3668   Register DstReg = MI.getOperand(0).getReg();
3669   if(MRI.getType(DstReg).isVector())
3670     MIRBuilder.buildBuildVector(DstReg, DstRegs);
3671   else
3672     MIRBuilder.buildMerge(DstReg, DstRegs);
3673   MI.eraseFromParent();
3674   return Legalized;
3675 }
3676 
3677 LegalizerHelper::LegalizeResult
3678 LegalizerHelper::narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx,
3679                                    LLT NarrowTy) {
3680   Register DstReg = MI.getOperand(0).getReg();
3681   LLT DstTy = MRI.getType(DstReg);
3682 
3683   assert(MI.getNumOperands() == 3 && TypeIdx == 0);
3684 
3685   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3686   SmallVector<Register, 4> Src0Regs, Src0LeftoverRegs;
3687   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3688   LLT LeftoverTy;
3689   if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
3690                     Src0Regs, Src0LeftoverRegs))
3691     return UnableToLegalize;
3692 
3693   LLT Unused;
3694   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
3695                     Src1Regs, Src1LeftoverRegs))
3696     llvm_unreachable("inconsistent extractParts result");
3697 
3698   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3699     auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
3700                                         {Src0Regs[I], Src1Regs[I]});
3701     DstRegs.push_back(Inst->getOperand(0).getReg());
3702   }
3703 
3704   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3705     auto Inst = MIRBuilder.buildInstr(
3706       MI.getOpcode(),
3707       {LeftoverTy}, {Src0LeftoverRegs[I], Src1LeftoverRegs[I]});
3708     DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
3709   }
3710 
3711   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3712               LeftoverTy, DstLeftoverRegs);
3713 
3714   MI.eraseFromParent();
3715   return Legalized;
3716 }
3717 
3718 LegalizerHelper::LegalizeResult
3719 LegalizerHelper::narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx,
3720                                     LLT NarrowTy) {
3721   if (TypeIdx != 0)
3722     return UnableToLegalize;
3723 
3724   Register CondReg = MI.getOperand(1).getReg();
3725   LLT CondTy = MRI.getType(CondReg);
3726   if (CondTy.isVector()) // TODO: Handle vselect
3727     return UnableToLegalize;
3728 
3729   Register DstReg = MI.getOperand(0).getReg();
3730   LLT DstTy = MRI.getType(DstReg);
3731 
3732   SmallVector<Register, 4> DstRegs, DstLeftoverRegs;
3733   SmallVector<Register, 4> Src1Regs, Src1LeftoverRegs;
3734   SmallVector<Register, 4> Src2Regs, Src2LeftoverRegs;
3735   LLT LeftoverTy;
3736   if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
3737                     Src1Regs, Src1LeftoverRegs))
3738     return UnableToLegalize;
3739 
3740   LLT Unused;
3741   if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
3742                     Src2Regs, Src2LeftoverRegs))
3743     llvm_unreachable("inconsistent extractParts result");
3744 
3745   for (unsigned I = 0, E = Src1Regs.size(); I != E; ++I) {
3746     auto Select = MIRBuilder.buildSelect(NarrowTy,
3747                                          CondReg, Src1Regs[I], Src2Regs[I]);
3748     DstRegs.push_back(Select->getOperand(0).getReg());
3749   }
3750 
3751   for (unsigned I = 0, E = Src1LeftoverRegs.size(); I != E; ++I) {
3752     auto Select = MIRBuilder.buildSelect(
3753       LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]);
3754     DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
3755   }
3756 
3757   insertParts(DstReg, DstTy, NarrowTy, DstRegs,
3758               LeftoverTy, DstLeftoverRegs);
3759 
3760   MI.eraseFromParent();
3761   return Legalized;
3762 }
3763 
3764 LegalizerHelper::LegalizeResult
3765 LegalizerHelper::lowerBitCount(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3766   unsigned Opc = MI.getOpcode();
3767   auto &TII = *MI.getMF()->getSubtarget().getInstrInfo();
3768   auto isSupported = [this](const LegalityQuery &Q) {
3769     auto QAction = LI.getAction(Q).Action;
3770     return QAction == Legal || QAction == Libcall || QAction == Custom;
3771   };
3772   switch (Opc) {
3773   default:
3774     return UnableToLegalize;
3775   case TargetOpcode::G_CTLZ_ZERO_UNDEF: {
3776     // This trivially expands to CTLZ.
3777     Observer.changingInstr(MI);
3778     MI.setDesc(TII.get(TargetOpcode::G_CTLZ));
3779     Observer.changedInstr(MI);
3780     return Legalized;
3781   }
3782   case TargetOpcode::G_CTLZ: {
3783     Register SrcReg = MI.getOperand(1).getReg();
3784     unsigned Len = Ty.getSizeInBits();
3785     if (isSupported({TargetOpcode::G_CTLZ_ZERO_UNDEF, {Ty, Ty}})) {
3786       // If CTLZ_ZERO_UNDEF is supported, emit that and a select for zero.
3787       auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
3788                                              {Ty}, {SrcReg});
3789       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3790       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3791       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3792                                           SrcReg, MIBZero);
3793       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3794                              MIBCtlzZU);
3795       MI.eraseFromParent();
3796       return Legalized;
3797     }
3798     // for now, we do this:
3799     // NewLen = NextPowerOf2(Len);
3800     // x = x | (x >> 1);
3801     // x = x | (x >> 2);
3802     // ...
3803     // x = x | (x >>16);
3804     // x = x | (x >>32); // for 64-bit input
3805     // Upto NewLen/2
3806     // return Len - popcount(x);
3807     //
3808     // Ref: "Hacker's Delight" by Henry Warren
3809     Register Op = SrcReg;
3810     unsigned NewLen = PowerOf2Ceil(Len);
3811     for (unsigned i = 0; (1U << i) <= (NewLen / 2); ++i) {
3812       auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
3813       auto MIBOp = MIRBuilder.buildInstr(
3814           TargetOpcode::G_OR, {Ty},
3815           {Op, MIRBuilder.buildInstr(TargetOpcode::G_LSHR, {Ty},
3816                                      {Op, MIBShiftAmt})});
3817       Op = MIBOp->getOperand(0).getReg();
3818     }
3819     auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
3820     MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3821                           {MIRBuilder.buildConstant(Ty, Len), MIBPop});
3822     MI.eraseFromParent();
3823     return Legalized;
3824   }
3825   case TargetOpcode::G_CTTZ_ZERO_UNDEF: {
3826     // This trivially expands to CTTZ.
3827     Observer.changingInstr(MI);
3828     MI.setDesc(TII.get(TargetOpcode::G_CTTZ));
3829     Observer.changedInstr(MI);
3830     return Legalized;
3831   }
3832   case TargetOpcode::G_CTTZ: {
3833     Register SrcReg = MI.getOperand(1).getReg();
3834     unsigned Len = Ty.getSizeInBits();
3835     if (isSupported({TargetOpcode::G_CTTZ_ZERO_UNDEF, {Ty, Ty}})) {
3836       // If CTTZ_ZERO_UNDEF is legal or custom, emit that and a select with
3837       // zero.
3838       auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
3839                                              {Ty}, {SrcReg});
3840       auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3841       auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3842       auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3843                                           SrcReg, MIBZero);
3844       MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3845                              MIBCttzZU);
3846       MI.eraseFromParent();
3847       return Legalized;
3848     }
3849     // for now, we use: { return popcount(~x & (x - 1)); }
3850     // unless the target has ctlz but not ctpop, in which case we use:
3851     // { return 32 - nlz(~x & (x-1)); }
3852     // Ref: "Hacker's Delight" by Henry Warren
3853     auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
3854     auto MIBNot =
3855         MIRBuilder.buildInstr(TargetOpcode::G_XOR, {Ty}, {SrcReg, MIBCstNeg1});
3856     auto MIBTmp = MIRBuilder.buildInstr(
3857         TargetOpcode::G_AND, {Ty},
3858         {MIBNot, MIRBuilder.buildInstr(TargetOpcode::G_ADD, {Ty},
3859                                        {SrcReg, MIBCstNeg1})});
3860     if (!isSupported({TargetOpcode::G_CTPOP, {Ty, Ty}}) &&
3861         isSupported({TargetOpcode::G_CTLZ, {Ty, Ty}})) {
3862       auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
3863       MIRBuilder.buildInstr(
3864           TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3865           {MIBCstLen,
3866            MIRBuilder.buildInstr(TargetOpcode::G_CTLZ, {Ty}, {MIBTmp})});
3867       MI.eraseFromParent();
3868       return Legalized;
3869     }
3870     MI.setDesc(TII.get(TargetOpcode::G_CTPOP));
3871     MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3872     return Legalized;
3873   }
3874   }
3875 }
3876 
3877 // Expand s32 = G_UITOFP s64 using bit operations to an IEEE float
3878 // representation.
3879 LegalizerHelper::LegalizeResult
3880 LegalizerHelper::lowerU64ToF32BitOps(MachineInstr &MI) {
3881   Register Dst = MI.getOperand(0).getReg();
3882   Register Src = MI.getOperand(1).getReg();
3883   const LLT S64 = LLT::scalar(64);
3884   const LLT S32 = LLT::scalar(32);
3885   const LLT S1 = LLT::scalar(1);
3886 
3887   assert(MRI.getType(Src) == S64 && MRI.getType(Dst) == S32);
3888 
3889   // unsigned cul2f(ulong u) {
3890   //   uint lz = clz(u);
3891   //   uint e = (u != 0) ? 127U + 63U - lz : 0;
3892   //   u = (u << lz) & 0x7fffffffffffffffUL;
3893   //   ulong t = u & 0xffffffffffUL;
3894   //   uint v = (e << 23) | (uint)(u >> 40);
3895   //   uint r = t > 0x8000000000UL ? 1U : (t == 0x8000000000UL ? v & 1U : 0U);
3896   //   return as_float(v + r);
3897   // }
3898 
3899   auto Zero32 = MIRBuilder.buildConstant(S32, 0);
3900   auto Zero64 = MIRBuilder.buildConstant(S64, 0);
3901 
3902   auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
3903 
3904   auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
3905   auto Sub = MIRBuilder.buildSub(S32, K, LZ);
3906 
3907   auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
3908   auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
3909 
3910   auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
3911   auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
3912 
3913   auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
3914 
3915   auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
3916   auto T = MIRBuilder.buildAnd(S64, U, Mask1);
3917 
3918   auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
3919   auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
3920   auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
3921 
3922   auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
3923   auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
3924   auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
3925   auto One = MIRBuilder.buildConstant(S32, 1);
3926 
3927   auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
3928   auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
3929   auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
3930   MIRBuilder.buildAdd(Dst, V, R);
3931 
3932   return Legalized;
3933 }
3934 
3935 LegalizerHelper::LegalizeResult
3936 LegalizerHelper::lowerUITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3937   Register Dst = MI.getOperand(0).getReg();
3938   Register Src = MI.getOperand(1).getReg();
3939   LLT DstTy = MRI.getType(Dst);
3940   LLT SrcTy = MRI.getType(Src);
3941 
3942   if (SrcTy == LLT::scalar(1)) {
3943     auto True = MIRBuilder.buildFConstant(DstTy, 1.0);
3944     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
3945     MIRBuilder.buildSelect(Dst, Src, True, False);
3946     MI.eraseFromParent();
3947     return Legalized;
3948   }
3949 
3950   if (SrcTy != LLT::scalar(64))
3951     return UnableToLegalize;
3952 
3953   if (DstTy == LLT::scalar(32)) {
3954     // TODO: SelectionDAG has several alternative expansions to port which may
3955     // be more reasonble depending on the available instructions. If a target
3956     // has sitofp, does not have CTLZ, or can efficiently use f64 as an
3957     // intermediate type, this is probably worse.
3958     return lowerU64ToF32BitOps(MI);
3959   }
3960 
3961   return UnableToLegalize;
3962 }
3963 
3964 LegalizerHelper::LegalizeResult
3965 LegalizerHelper::lowerSITOFP(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
3966   Register Dst = MI.getOperand(0).getReg();
3967   Register Src = MI.getOperand(1).getReg();
3968   LLT DstTy = MRI.getType(Dst);
3969   LLT SrcTy = MRI.getType(Src);
3970 
3971   const LLT S64 = LLT::scalar(64);
3972   const LLT S32 = LLT::scalar(32);
3973   const LLT S1 = LLT::scalar(1);
3974 
3975   if (SrcTy == S1) {
3976     auto True = MIRBuilder.buildFConstant(DstTy, -1.0);
3977     auto False = MIRBuilder.buildFConstant(DstTy, 0.0);
3978     MIRBuilder.buildSelect(Dst, Src, True, False);
3979     MI.eraseFromParent();
3980     return Legalized;
3981   }
3982 
3983   if (SrcTy != S64)
3984     return UnableToLegalize;
3985 
3986   if (DstTy == S32) {
3987     // signed cl2f(long l) {
3988     //   long s = l >> 63;
3989     //   float r = cul2f((l + s) ^ s);
3990     //   return s ? -r : r;
3991     // }
3992     Register L = Src;
3993     auto SignBit = MIRBuilder.buildConstant(S64, 63);
3994     auto S = MIRBuilder.buildAShr(S64, L, SignBit);
3995 
3996     auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
3997     auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
3998     auto R = MIRBuilder.buildUITOFP(S32, Xor);
3999 
4000     auto RNeg = MIRBuilder.buildFNeg(S32, R);
4001     auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
4002                                             MIRBuilder.buildConstant(S64, 0));
4003     MIRBuilder.buildSelect(Dst, SignNotZero, RNeg, R);
4004     return Legalized;
4005   }
4006 
4007   return UnableToLegalize;
4008 }
4009 
4010 LegalizerHelper::LegalizeResult
4011 LegalizerHelper::lowerFPTOUI(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4012   Register Dst = MI.getOperand(0).getReg();
4013   Register Src = MI.getOperand(1).getReg();
4014   LLT DstTy = MRI.getType(Dst);
4015   LLT SrcTy = MRI.getType(Src);
4016   const LLT S64 = LLT::scalar(64);
4017   const LLT S32 = LLT::scalar(32);
4018 
4019   if (SrcTy != S64 && SrcTy != S32)
4020     return UnableToLegalize;
4021   if (DstTy != S32 && DstTy != S64)
4022     return UnableToLegalize;
4023 
4024   // FPTOSI gives same result as FPTOUI for positive signed integers.
4025   // FPTOUI needs to deal with fp values that convert to unsigned integers
4026   // greater or equal to 2^31 for float or 2^63 for double. For brevity 2^Exp.
4027 
4028   APInt TwoPExpInt = APInt::getSignMask(DstTy.getSizeInBits());
4029   APFloat TwoPExpFP(SrcTy.getSizeInBits() == 32 ? APFloat::IEEEsingle()
4030                                                 : APFloat::IEEEdouble(),
4031                     APInt::getNullValue(SrcTy.getSizeInBits()));
4032   TwoPExpFP.convertFromAPInt(TwoPExpInt, false, APFloat::rmNearestTiesToEven);
4033 
4034   MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src);
4035 
4036   MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP);
4037   // For fp Value greater or equal to Threshold(2^Exp), we use FPTOSI on
4038   // (Value - 2^Exp) and add 2^Exp by setting highest bit in result to 1.
4039   MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold);
4040   MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub);
4041   MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt);
4042   MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit);
4043 
4044   const LLT S1 = LLT::scalar(1);
4045 
4046   MachineInstrBuilder FCMP =
4047       MIRBuilder.buildFCmp(CmpInst::FCMP_ULT, S1, Src, Threshold);
4048   MIRBuilder.buildSelect(Dst, FCMP, FPTOSI, Res);
4049 
4050   MI.eraseFromParent();
4051   return Legalized;
4052 }
4053 
4054 static CmpInst::Predicate minMaxToCompare(unsigned Opc) {
4055   switch (Opc) {
4056   case TargetOpcode::G_SMIN:
4057     return CmpInst::ICMP_SLT;
4058   case TargetOpcode::G_SMAX:
4059     return CmpInst::ICMP_SGT;
4060   case TargetOpcode::G_UMIN:
4061     return CmpInst::ICMP_ULT;
4062   case TargetOpcode::G_UMAX:
4063     return CmpInst::ICMP_UGT;
4064   default:
4065     llvm_unreachable("not in integer min/max");
4066   }
4067 }
4068 
4069 LegalizerHelper::LegalizeResult
4070 LegalizerHelper::lowerMinMax(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4071   Register Dst = MI.getOperand(0).getReg();
4072   Register Src0 = MI.getOperand(1).getReg();
4073   Register Src1 = MI.getOperand(2).getReg();
4074 
4075   const CmpInst::Predicate Pred = minMaxToCompare(MI.getOpcode());
4076   LLT CmpType = MRI.getType(Dst).changeElementSize(1);
4077 
4078   auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
4079   MIRBuilder.buildSelect(Dst, Cmp, Src0, Src1);
4080 
4081   MI.eraseFromParent();
4082   return Legalized;
4083 }
4084 
4085 LegalizerHelper::LegalizeResult
4086 LegalizerHelper::lowerFCopySign(MachineInstr &MI, unsigned TypeIdx, LLT Ty) {
4087   Register Dst = MI.getOperand(0).getReg();
4088   Register Src0 = MI.getOperand(1).getReg();
4089   Register Src1 = MI.getOperand(2).getReg();
4090 
4091   const LLT Src0Ty = MRI.getType(Src0);
4092   const LLT Src1Ty = MRI.getType(Src1);
4093 
4094   const int Src0Size = Src0Ty.getScalarSizeInBits();
4095   const int Src1Size = Src1Ty.getScalarSizeInBits();
4096 
4097   auto SignBitMask = MIRBuilder.buildConstant(
4098     Src0Ty, APInt::getSignMask(Src0Size));
4099 
4100   auto NotSignBitMask = MIRBuilder.buildConstant(
4101     Src0Ty, APInt::getLowBitsSet(Src0Size, Src0Size - 1));
4102 
4103   auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
4104   MachineInstr *Or;
4105 
4106   if (Src0Ty == Src1Ty) {
4107     auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
4108     Or = MIRBuilder.buildOr(Dst, And0, And1);
4109   } else if (Src0Size > Src1Size) {
4110     auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
4111     auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
4112     auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
4113     auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
4114     Or = MIRBuilder.buildOr(Dst, And0, And1);
4115   } else {
4116     auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
4117     auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
4118     auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
4119     auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
4120     Or = MIRBuilder.buildOr(Dst, And0, And1);
4121   }
4122 
4123   // Be careful about setting nsz/nnan/ninf on every instruction, since the
4124   // constants are a nan and -0.0, but the final result should preserve
4125   // everything.
4126   if (unsigned Flags = MI.getFlags())
4127     Or->setFlags(Flags);
4128 
4129   MI.eraseFromParent();
4130   return Legalized;
4131 }
4132 
4133 LegalizerHelper::LegalizeResult
4134 LegalizerHelper::lowerFMinNumMaxNum(MachineInstr &MI) {
4135   unsigned NewOp = MI.getOpcode() == TargetOpcode::G_FMINNUM ?
4136     TargetOpcode::G_FMINNUM_IEEE : TargetOpcode::G_FMAXNUM_IEEE;
4137 
4138   Register Dst = MI.getOperand(0).getReg();
4139   Register Src0 = MI.getOperand(1).getReg();
4140   Register Src1 = MI.getOperand(2).getReg();
4141   LLT Ty = MRI.getType(Dst);
4142 
4143   if (!MI.getFlag(MachineInstr::FmNoNans)) {
4144     // Insert canonicalizes if it's possible we need to quiet to get correct
4145     // sNaN behavior.
4146 
4147     // Note this must be done here, and not as an optimization combine in the
4148     // absence of a dedicate quiet-snan instruction as we're using an
4149     // omni-purpose G_FCANONICALIZE.
4150     if (!isKnownNeverSNaN(Src0, MRI))
4151       Src0 = MIRBuilder.buildFCanonicalize(Ty, Src0, MI.getFlags()).getReg(0);
4152 
4153     if (!isKnownNeverSNaN(Src1, MRI))
4154       Src1 = MIRBuilder.buildFCanonicalize(Ty, Src1, MI.getFlags()).getReg(0);
4155   }
4156 
4157   // If there are no nans, it's safe to simply replace this with the non-IEEE
4158   // version.
4159   MIRBuilder.buildInstr(NewOp, {Dst}, {Src0, Src1}, MI.getFlags());
4160   MI.eraseFromParent();
4161   return Legalized;
4162 }
4163 
4164 LegalizerHelper::LegalizeResult LegalizerHelper::lowerFMad(MachineInstr &MI) {
4165   // Expand G_FMAD a, b, c -> G_FADD (G_FMUL a, b), c
4166   Register DstReg = MI.getOperand(0).getReg();
4167   LLT Ty = MRI.getType(DstReg);
4168   unsigned Flags = MI.getFlags();
4169 
4170   auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2),
4171                                   Flags);
4172   MIRBuilder.buildFAdd(DstReg, Mul, MI.getOperand(3), Flags);
4173   MI.eraseFromParent();
4174   return Legalized;
4175 }
4176 
4177 LegalizerHelper::LegalizeResult
4178 LegalizerHelper::lowerIntrinsicRound(MachineInstr &MI) {
4179   Register DstReg = MI.getOperand(0).getReg();
4180   Register SrcReg = MI.getOperand(1).getReg();
4181   unsigned Flags = MI.getFlags();
4182   LLT Ty = MRI.getType(DstReg);
4183   const LLT CondTy = Ty.changeElementSize(1);
4184 
4185   // result = trunc(src);
4186   // if (src < 0.0 && src != result)
4187   //   result += -1.0.
4188 
4189   auto Zero = MIRBuilder.buildFConstant(Ty, 0.0);
4190   auto Trunc = MIRBuilder.buildIntrinsicTrunc(Ty, SrcReg, Flags);
4191 
4192   auto Lt0 = MIRBuilder.buildFCmp(CmpInst::FCMP_OLT, CondTy,
4193                                   SrcReg, Zero, Flags);
4194   auto NeTrunc = MIRBuilder.buildFCmp(CmpInst::FCMP_ONE, CondTy,
4195                                       SrcReg, Trunc, Flags);
4196   auto And = MIRBuilder.buildAnd(CondTy, Lt0, NeTrunc);
4197   auto AddVal = MIRBuilder.buildSITOFP(Ty, And);
4198 
4199   MIRBuilder.buildFAdd(DstReg, Trunc, AddVal);
4200   MI.eraseFromParent();
4201   return Legalized;
4202 }
4203 
4204 LegalizerHelper::LegalizeResult
4205 LegalizerHelper::lowerUnmergeValues(MachineInstr &MI) {
4206   const unsigned NumDst = MI.getNumOperands() - 1;
4207   const Register SrcReg = MI.getOperand(NumDst).getReg();
4208   LLT SrcTy = MRI.getType(SrcReg);
4209 
4210   Register Dst0Reg = MI.getOperand(0).getReg();
4211   LLT DstTy = MRI.getType(Dst0Reg);
4212 
4213 
4214   // Expand scalarizing unmerge as bitcast to integer and shift.
4215   if (!DstTy.isVector() && SrcTy.isVector() &&
4216       SrcTy.getElementType() == DstTy) {
4217     LLT IntTy = LLT::scalar(SrcTy.getSizeInBits());
4218     Register Cast = MIRBuilder.buildBitcast(IntTy, SrcReg).getReg(0);
4219 
4220     MIRBuilder.buildTrunc(Dst0Reg, Cast);
4221 
4222     const unsigned DstSize = DstTy.getSizeInBits();
4223     unsigned Offset = DstSize;
4224     for (unsigned I = 1; I != NumDst; ++I, Offset += DstSize) {
4225       auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
4226       auto Shift = MIRBuilder.buildLShr(IntTy, Cast, ShiftAmt);
4227       MIRBuilder.buildTrunc(MI.getOperand(I), Shift);
4228     }
4229 
4230     MI.eraseFromParent();
4231     return Legalized;
4232   }
4233 
4234   return UnableToLegalize;
4235 }
4236 
4237 LegalizerHelper::LegalizeResult
4238 LegalizerHelper::lowerShuffleVector(MachineInstr &MI) {
4239   Register DstReg = MI.getOperand(0).getReg();
4240   Register Src0Reg = MI.getOperand(1).getReg();
4241   Register Src1Reg = MI.getOperand(2).getReg();
4242   LLT Src0Ty = MRI.getType(Src0Reg);
4243   LLT DstTy = MRI.getType(DstReg);
4244   LLT IdxTy = LLT::scalar(32);
4245 
4246   ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();
4247 
4248   if (DstTy.isScalar()) {
4249     if (Src0Ty.isVector())
4250       return UnableToLegalize;
4251 
4252     // This is just a SELECT.
4253     assert(Mask.size() == 1 && "Expected a single mask element");
4254     Register Val;
4255     if (Mask[0] < 0 || Mask[0] > 1)
4256       Val = MIRBuilder.buildUndef(DstTy).getReg(0);
4257     else
4258       Val = Mask[0] == 0 ? Src0Reg : Src1Reg;
4259     MIRBuilder.buildCopy(DstReg, Val);
4260     MI.eraseFromParent();
4261     return Legalized;
4262   }
4263 
4264   Register Undef;
4265   SmallVector<Register, 32> BuildVec;
4266   LLT EltTy = DstTy.getElementType();
4267 
4268   for (int Idx : Mask) {
4269     if (Idx < 0) {
4270       if (!Undef.isValid())
4271         Undef = MIRBuilder.buildUndef(EltTy).getReg(0);
4272       BuildVec.push_back(Undef);
4273       continue;
4274     }
4275 
4276     if (Src0Ty.isScalar()) {
4277       BuildVec.push_back(Idx == 0 ? Src0Reg : Src1Reg);
4278     } else {
4279       int NumElts = Src0Ty.getNumElements();
4280       Register SrcVec = Idx < NumElts ? Src0Reg : Src1Reg;
4281       int ExtractIdx = Idx < NumElts ? Idx : Idx - NumElts;
4282       auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
4283       auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
4284       BuildVec.push_back(Extract.getReg(0));
4285     }
4286   }
4287 
4288   MIRBuilder.buildBuildVector(DstReg, BuildVec);
4289   MI.eraseFromParent();
4290   return Legalized;
4291 }
4292 
4293 LegalizerHelper::LegalizeResult
4294 LegalizerHelper::lowerDynStackAlloc(MachineInstr &MI) {
4295   Register Dst = MI.getOperand(0).getReg();
4296   Register AllocSize = MI.getOperand(1).getReg();
4297   unsigned Align = MI.getOperand(2).getImm();
4298 
4299   const auto &MF = *MI.getMF();
4300   const auto &TLI = *MF.getSubtarget().getTargetLowering();
4301 
4302   LLT PtrTy = MRI.getType(Dst);
4303   LLT IntPtrTy = LLT::scalar(PtrTy.getSizeInBits());
4304 
4305   Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
4306   auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg);
4307   SPTmp = MIRBuilder.buildCast(IntPtrTy, SPTmp);
4308 
4309   // Subtract the final alloc from the SP. We use G_PTRTOINT here so we don't
4310   // have to generate an extra instruction to negate the alloc and then use
4311   // G_PTR_ADD to add the negative offset.
4312   auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize);
4313   if (Align) {
4314     APInt AlignMask(IntPtrTy.getSizeInBits(), Align, true);
4315     AlignMask.negate();
4316     auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask);
4317     Alloc = MIRBuilder.buildAnd(IntPtrTy, Alloc, AlignCst);
4318   }
4319 
4320   SPTmp = MIRBuilder.buildCast(PtrTy, Alloc);
4321   MIRBuilder.buildCopy(SPReg, SPTmp);
4322   MIRBuilder.buildCopy(Dst, SPTmp);
4323 
4324   MI.eraseFromParent();
4325   return Legalized;
4326 }
4327 
4328 LegalizerHelper::LegalizeResult
4329 LegalizerHelper::lowerExtract(MachineInstr &MI) {
4330   Register Dst = MI.getOperand(0).getReg();
4331   Register Src = MI.getOperand(1).getReg();
4332   unsigned Offset = MI.getOperand(2).getImm();
4333 
4334   LLT DstTy = MRI.getType(Dst);
4335   LLT SrcTy = MRI.getType(Src);
4336 
4337   if (DstTy.isScalar() &&
4338       (SrcTy.isScalar() ||
4339        (SrcTy.isVector() && DstTy == SrcTy.getElementType()))) {
4340     LLT SrcIntTy = SrcTy;
4341     if (!SrcTy.isScalar()) {
4342       SrcIntTy = LLT::scalar(SrcTy.getSizeInBits());
4343       Src = MIRBuilder.buildBitcast(SrcIntTy, Src).getReg(0);
4344     }
4345 
4346     if (Offset == 0)
4347       MIRBuilder.buildTrunc(Dst, Src);
4348     else {
4349       auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset);
4350       auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt);
4351       MIRBuilder.buildTrunc(Dst, Shr);
4352     }
4353 
4354     MI.eraseFromParent();
4355     return Legalized;
4356   }
4357 
4358   return UnableToLegalize;
4359 }
4360 
4361 LegalizerHelper::LegalizeResult LegalizerHelper::lowerInsert(MachineInstr &MI) {
4362   Register Dst = MI.getOperand(0).getReg();
4363   Register Src = MI.getOperand(1).getReg();
4364   Register InsertSrc = MI.getOperand(2).getReg();
4365   uint64_t Offset = MI.getOperand(3).getImm();
4366 
4367   LLT DstTy = MRI.getType(Src);
4368   LLT InsertTy = MRI.getType(InsertSrc);
4369 
4370   if (InsertTy.isScalar() &&
4371       (DstTy.isScalar() ||
4372        (DstTy.isVector() && DstTy.getElementType() == InsertTy))) {
4373     LLT IntDstTy = DstTy;
4374     if (!DstTy.isScalar()) {
4375       IntDstTy = LLT::scalar(DstTy.getSizeInBits());
4376       Src = MIRBuilder.buildBitcast(IntDstTy, Src).getReg(0);
4377     }
4378 
4379     Register ExtInsSrc = MIRBuilder.buildZExt(IntDstTy, InsertSrc).getReg(0);
4380     if (Offset != 0) {
4381       auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset);
4382       ExtInsSrc = MIRBuilder.buildShl(IntDstTy, ExtInsSrc, ShiftAmt).getReg(0);
4383     }
4384 
4385     APInt MaskVal = ~APInt::getBitsSet(DstTy.getSizeInBits(), Offset,
4386                                        InsertTy.getSizeInBits());
4387 
4388     auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal);
4389     auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);
4390     auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc);
4391 
4392     MIRBuilder.buildBitcast(Dst, Or);
4393     MI.eraseFromParent();
4394     return Legalized;
4395   }
4396 
4397   return UnableToLegalize;
4398 }
4399 
4400 LegalizerHelper::LegalizeResult
4401 LegalizerHelper::lowerSADDO_SSUBO(MachineInstr &MI) {
4402   Register Dst0 = MI.getOperand(0).getReg();
4403   Register Dst1 = MI.getOperand(1).getReg();
4404   Register LHS = MI.getOperand(2).getReg();
4405   Register RHS = MI.getOperand(3).getReg();
4406   const bool IsAdd = MI.getOpcode() == TargetOpcode::G_SADDO;
4407 
4408   LLT Ty = MRI.getType(Dst0);
4409   LLT BoolTy = MRI.getType(Dst1);
4410 
4411   if (IsAdd)
4412     MIRBuilder.buildAdd(Dst0, LHS, RHS);
4413   else
4414     MIRBuilder.buildSub(Dst0, LHS, RHS);
4415 
4416   // TODO: If SADDSAT/SSUBSAT is legal, compare results to detect overflow.
4417 
4418   auto Zero = MIRBuilder.buildConstant(Ty, 0);
4419 
4420   // For an addition, the result should be less than one of the operands (LHS)
4421   // if and only if the other operand (RHS) is negative, otherwise there will
4422   // be overflow.
4423   // For a subtraction, the result should be less than one of the operands
4424   // (LHS) if and only if the other operand (RHS) is (non-zero) positive,
4425   // otherwise there will be overflow.
4426   auto ResultLowerThanLHS =
4427       MIRBuilder.buildICmp(CmpInst::ICMP_SLT, BoolTy, Dst0, LHS);
4428   auto ConditionRHS = MIRBuilder.buildICmp(
4429       IsAdd ? CmpInst::ICMP_SLT : CmpInst::ICMP_SGT, BoolTy, RHS, Zero);
4430 
4431   MIRBuilder.buildXor(Dst1, ConditionRHS, ResultLowerThanLHS);
4432   MI.eraseFromParent();
4433   return Legalized;
4434 }
4435 
4436 LegalizerHelper::LegalizeResult
4437 LegalizerHelper::lowerBswap(MachineInstr &MI) {
4438   Register Dst = MI.getOperand(0).getReg();
4439   Register Src = MI.getOperand(1).getReg();
4440   const LLT Ty = MRI.getType(Src);
4441   unsigned SizeInBytes = Ty.getSizeInBytes();
4442   unsigned BaseShiftAmt = (SizeInBytes - 1) * 8;
4443 
4444   // Swap most and least significant byte, set remaining bytes in Res to zero.
4445   auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt);
4446   auto LSByteShiftedLeft = MIRBuilder.buildShl(Ty, Src, ShiftAmt);
4447   auto MSByteShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
4448   auto Res = MIRBuilder.buildOr(Ty, MSByteShiftedRight, LSByteShiftedLeft);
4449 
4450   // Set i-th high/low byte in Res to i-th low/high byte from Src.
4451   for (unsigned i = 1; i < SizeInBytes / 2; ++i) {
4452     // AND with Mask leaves byte i unchanged and sets remaining bytes to 0.
4453     APInt APMask(SizeInBytes * 8, 0xFF << (i * 8));
4454     auto Mask = MIRBuilder.buildConstant(Ty, APMask);
4455     auto ShiftAmt = MIRBuilder.buildConstant(Ty, BaseShiftAmt - 16 * i);
4456     // Low byte shifted left to place of high byte: (Src & Mask) << ShiftAmt.
4457     auto LoByte = MIRBuilder.buildAnd(Ty, Src, Mask);
4458     auto LoShiftedLeft = MIRBuilder.buildShl(Ty, LoByte, ShiftAmt);
4459     Res = MIRBuilder.buildOr(Ty, Res, LoShiftedLeft);
4460     // High byte shifted right to place of low byte: (Src >> ShiftAmt) & Mask.
4461     auto SrcShiftedRight = MIRBuilder.buildLShr(Ty, Src, ShiftAmt);
4462     auto HiShiftedRight = MIRBuilder.buildAnd(Ty, SrcShiftedRight, Mask);
4463     Res = MIRBuilder.buildOr(Ty, Res, HiShiftedRight);
4464   }
4465   Res.getInstr()->getOperand(0).setReg(Dst);
4466 
4467   MI.eraseFromParent();
4468   return Legalized;
4469 }
4470 
4471 //{ (Src & Mask) >> N } | { (Src << N) & Mask }
4472 static MachineInstrBuilder SwapN(unsigned N, DstOp Dst, MachineIRBuilder &B,
4473                                  MachineInstrBuilder Src, APInt Mask) {
4474   const LLT Ty = Dst.getLLTTy(*B.getMRI());
4475   MachineInstrBuilder C_N = B.buildConstant(Ty, N);
4476   MachineInstrBuilder MaskLoNTo0 = B.buildConstant(Ty, Mask);
4477   auto LHS = B.buildLShr(Ty, B.buildAnd(Ty, Src, MaskLoNTo0), C_N);
4478   auto RHS = B.buildAnd(Ty, B.buildShl(Ty, Src, C_N), MaskLoNTo0);
4479   return B.buildOr(Dst, LHS, RHS);
4480 }
4481 
4482 LegalizerHelper::LegalizeResult
4483 LegalizerHelper::lowerBitreverse(MachineInstr &MI) {
4484   Register Dst = MI.getOperand(0).getReg();
4485   Register Src = MI.getOperand(1).getReg();
4486   const LLT Ty = MRI.getType(Src);
4487   unsigned Size = Ty.getSizeInBits();
4488 
4489   MachineInstrBuilder BSWAP =
4490       MIRBuilder.buildInstr(TargetOpcode::G_BSWAP, {Ty}, {Src});
4491 
4492   // swap high and low 4 bits in 8 bit blocks 7654|3210 -> 3210|7654
4493   //    [(val & 0xF0F0F0F0) >> 4] | [(val & 0x0F0F0F0F) << 4]
4494   // -> [(val & 0xF0F0F0F0) >> 4] | [(val << 4) & 0xF0F0F0F0]
4495   MachineInstrBuilder Swap4 =
4496       SwapN(4, Ty, MIRBuilder, BSWAP, APInt::getSplat(Size, APInt(8, 0xF0)));
4497 
4498   // swap high and low 2 bits in 4 bit blocks 32|10 76|54 -> 10|32 54|76
4499   //    [(val & 0xCCCCCCCC) >> 2] & [(val & 0x33333333) << 2]
4500   // -> [(val & 0xCCCCCCCC) >> 2] & [(val << 2) & 0xCCCCCCCC]
4501   MachineInstrBuilder Swap2 =
4502       SwapN(2, Ty, MIRBuilder, Swap4, APInt::getSplat(Size, APInt(8, 0xCC)));
4503 
4504   // swap high and low 1 bit in 2 bit blocks 1|0 3|2 5|4 7|6 -> 0|1 2|3 4|5 6|7
4505   //    [(val & 0xAAAAAAAA) >> 1] & [(val & 0x55555555) << 1]
4506   // -> [(val & 0xAAAAAAAA) >> 1] & [(val << 1) & 0xAAAAAAAA]
4507   SwapN(1, Dst, MIRBuilder, Swap2, APInt::getSplat(Size, APInt(8, 0xAA)));
4508 
4509   MI.eraseFromParent();
4510   return Legalized;
4511 }
4512 
4513 LegalizerHelper::LegalizeResult
4514 LegalizerHelper::lowerReadRegister(MachineInstr &MI) {
4515   Register Dst = MI.getOperand(0).getReg();
4516   const LLT Ty = MRI.getType(Dst);
4517   const MDString *RegStr = cast<MDString>(
4518     cast<MDNode>(MI.getOperand(1).getMetadata())->getOperand(0));
4519 
4520   MachineFunction &MF = MIRBuilder.getMF();
4521   const TargetSubtargetInfo &STI = MF.getSubtarget();
4522   const TargetLowering *TLI = STI.getTargetLowering();
4523   Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty, MF);
4524   if (!Reg.isValid())
4525     return UnableToLegalize;
4526 
4527   MIRBuilder.buildCopy(Dst, Reg);
4528   MI.eraseFromParent();
4529   return Legalized;
4530 }
4531