1 //===-- llvm/CodeGen/GlobalISel/Legalizer.cpp -----------------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 /// \file This file implements the LegalizerHelper class to legalize individual
11 /// instructions and the LegalizePass wrapper pass for the primary
12 /// legalization.
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
17 #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
18 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
19 #include "llvm/CodeGen/GlobalISel/Utils.h"
20 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetPassConfig.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
26 
27 #define DEBUG_TYPE "legalizer"
28 
29 using namespace llvm;
30 
31 char Legalizer::ID = 0;
32 INITIALIZE_PASS_BEGIN(Legalizer, DEBUG_TYPE,
33                       "Legalize the Machine IR a function's Machine IR", false,
34                       false)
35 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
36 INITIALIZE_PASS_END(Legalizer, DEBUG_TYPE,
37                     "Legalize the Machine IR a function's Machine IR", false,
38                     false)
39 
40 Legalizer::Legalizer() : MachineFunctionPass(ID) {
41   initializeLegalizerPass(*PassRegistry::getPassRegistry());
42 }
43 
44 void Legalizer::getAnalysisUsage(AnalysisUsage &AU) const {
45   AU.addRequired<TargetPassConfig>();
46   MachineFunctionPass::getAnalysisUsage(AU);
47 }
48 
49 void Legalizer::init(MachineFunction &MF) {
50 }
51 
52 bool Legalizer::combineExtracts(MachineInstr &MI, MachineRegisterInfo &MRI,
53                                 const TargetInstrInfo &TII) {
54   bool Changed = false;
55   if (MI.getOpcode() != TargetOpcode::G_EXTRACT)
56     return Changed;
57 
58   unsigned NumDefs = (MI.getNumOperands() - 1) / 2;
59   unsigned SrcReg = MI.getOperand(NumDefs).getReg();
60   MachineInstr &SeqI = *MRI.def_instr_begin(SrcReg);
61   if (SeqI.getOpcode() != TargetOpcode::G_SEQUENCE)
62       return Changed;
63 
64   unsigned NumSeqSrcs = (SeqI.getNumOperands() - 1) / 2;
65   bool AllDefsReplaced = true;
66 
67   // Try to match each register extracted with a corresponding insertion formed
68   // by the G_SEQUENCE.
69   for (unsigned Idx = 0, SeqIdx = 0; Idx < NumDefs; ++Idx) {
70     MachineOperand &ExtractMO = MI.getOperand(Idx);
71     assert(ExtractMO.isReg() && ExtractMO.isDef() &&
72            "unexpected extract operand");
73 
74     unsigned ExtractReg = ExtractMO.getReg();
75     unsigned ExtractPos = MI.getOperand(NumDefs + Idx + 1).getImm();
76 
77     while (SeqIdx < NumSeqSrcs &&
78            SeqI.getOperand(2 * SeqIdx + 2).getImm() < ExtractPos)
79       ++SeqIdx;
80 
81     if (SeqIdx == NumSeqSrcs) {
82       AllDefsReplaced = false;
83       continue;
84     }
85 
86     unsigned OrigReg = SeqI.getOperand(2 * SeqIdx + 1).getReg();
87     if (SeqI.getOperand(2 * SeqIdx + 2).getImm() != ExtractPos ||
88         MRI.getType(OrigReg) != MRI.getType(ExtractReg)) {
89       AllDefsReplaced = false;
90       continue;
91     }
92 
93     assert(!TargetRegisterInfo::isPhysicalRegister(OrigReg) &&
94            "unexpected physical register in G_SEQUENCE");
95 
96     // Finally we can replace the uses.
97     MRI.replaceRegWith(ExtractReg, OrigReg);
98   }
99 
100   if (AllDefsReplaced) {
101     // If SeqI was the next instruction in the BB and we removed it, we'd break
102     // the outer iteration.
103     assert(std::next(MachineBasicBlock::iterator(MI)) != SeqI &&
104            "G_SEQUENCE does not dominate G_EXTRACT");
105 
106     MI.eraseFromParent();
107 
108     if (MRI.use_empty(SrcReg))
109       SeqI.eraseFromParent();
110     Changed = true;
111   }
112 
113   return Changed;
114 }
115 
116 bool Legalizer::runOnMachineFunction(MachineFunction &MF) {
117   // If the ISel pipeline failed, do not bother running that pass.
118   if (MF.getProperties().hasProperty(
119           MachineFunctionProperties::Property::FailedISel))
120     return false;
121   DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n');
122   init(MF);
123   const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
124   const LegalizerInfo &LegalizerInfo = *MF.getSubtarget().getLegalizerInfo();
125   MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
126   LegalizerHelper Helper(MF);
127 
128   // FIXME: an instruction may need more than one pass before it is legal. For
129   // example on most architectures <3 x i3> is doubly-illegal. It would
130   // typically proceed along a path like: <3 x i3> -> <3 x i8> -> <8 x i8>. We
131   // probably want a worklist of instructions rather than naive iterate until
132   // convergence for performance reasons.
133   bool Changed = false;
134   MachineBasicBlock::iterator NextMI;
135   for (auto &MBB : MF)
136     for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) {
137       // Get the next Instruction before we try to legalize, because there's a
138       // good chance MI will be deleted.
139       NextMI = std::next(MI);
140 
141       // Only legalize pre-isel generic instructions: others don't have types
142       // and are assumed to be legal.
143       if (!isPreISelGenericOpcode(MI->getOpcode()))
144         continue;
145 
146       auto Res = Helper.legalizeInstr(*MI, LegalizerInfo);
147 
148       // Error out if we couldn't legalize this instruction. We may want to fall
149       // back to DAG ISel instead in the future.
150       if (Res == LegalizerHelper::UnableToLegalize) {
151         reportGISelFailure(MF, TPC, MORE, "gisel-legalize",
152                            "unable to legalize instruction", *MI);
153         return false;
154       }
155 
156       Changed |= Res == LegalizerHelper::Legalized;
157     }
158 
159 
160   MachineRegisterInfo &MRI = MF.getRegInfo();
161   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
162   for (auto &MBB : MF) {
163     for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) {
164       // Get the next Instruction before we try to legalize, because there's a
165       // good chance MI will be deleted.
166       NextMI = std::next(MI);
167 
168       Changed |= combineExtracts(*MI, MRI, TII);
169     }
170   }
171 
172   return Changed;
173 }
174