1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp -----------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the InstructionSelector class.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
14 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
15 #include "llvm/CodeGen/GlobalISel/Utils.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Constants.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 
22 #define DEBUG_TYPE "instructionselector"
23 
24 using namespace llvm;
25 
26 InstructionSelector::InstructionSelector() {}
27 
28 bool InstructionSelector::constrainOperandRegToRegClass(
29     MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
30     const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
31     const RegisterBankInfo &RBI) const {
32   MachineBasicBlock &MBB = *I.getParent();
33   MachineFunction &MF = *MBB.getParent();
34   MachineRegisterInfo &MRI = MF.getRegInfo();
35 
36   return llvm::constrainRegToClass(MRI, TII, RBI, I,
37                                    I.getOperand(OpIdx).getReg(), RC);
38 }
39 
40 bool InstructionSelector::constrainSelectedInstRegOperands(
41     MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
42     const RegisterBankInfo &RBI) const {
43   MachineBasicBlock &MBB = *I.getParent();
44   MachineFunction &MF = *MBB.getParent();
45   MachineRegisterInfo &MRI = MF.getRegInfo();
46 
47   for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
48     MachineOperand &MO = I.getOperand(OpI);
49 
50     // There's nothing to be done on non-register operands.
51     if (!MO.isReg())
52       continue;
53 
54     DEBUG(dbgs() << "Converting operand: " << MO << '\n');
55     assert(MO.isReg() && "Unsupported non-reg operand");
56 
57     unsigned Reg = MO.getReg();
58     // Physical registers don't need to be constrained.
59     if (TRI.isPhysicalRegister(Reg))
60       continue;
61 
62     // Register operands with a value of 0 (e.g. predicate operands) don't need
63     // to be constrained.
64     if (Reg == 0)
65       continue;
66 
67     // If the operand is a vreg, we should constrain its regclass, and only
68     // insert COPYs if that's impossible.
69     // constrainOperandRegClass does that for us.
70     MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
71                                        Reg, OpI));
72 
73     // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
74     // done.
75     if (MO.isUse()) {
76       int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
77       if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
78         I.tieOperands(DefIdx, OpI);
79     }
80   }
81   return true;
82 }
83 
84 bool InstructionSelector::isOperandImmEqual(
85     const MachineOperand &MO, int64_t Value,
86     const MachineRegisterInfo &MRI) const {
87 
88   if (MO.isReg() && MO.getReg())
89     if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
90       return *VRegVal == Value;
91   return false;
92 }
93 
94 bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI) const {
95   return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() &&
96          MI.implicit_operands().begin() == MI.implicit_operands().end();
97 }
98