1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp -----------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the InstructionSelector class.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
14 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
15 #include "llvm/CodeGen/GlobalISel/Utils.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
19 
20 #define DEBUG_TYPE "instructionselector"
21 
22 using namespace llvm;
23 
24 InstructionSelector::InstructionSelector() {}
25 
26 bool InstructionSelector::constrainSelectedInstRegOperands(
27     MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
28     const RegisterBankInfo &RBI) const {
29   MachineBasicBlock &MBB = *I.getParent();
30   MachineFunction &MF = *MBB.getParent();
31   MachineRegisterInfo &MRI = MF.getRegInfo();
32 
33   for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
34     MachineOperand &MO = I.getOperand(OpI);
35 
36     // There's nothing to be done on non-register operands.
37     if (!MO.isReg())
38       continue;
39 
40     DEBUG(dbgs() << "Converting operand: " << MO << '\n');
41     assert(MO.isReg() && "Unsupported non-reg operand");
42 
43     unsigned Reg = MO.getReg();
44     // Physical registers don't need to be constrained.
45     if (TRI.isPhysicalRegister(Reg))
46       continue;
47 
48     // Register operands with a value of 0 (e.g. predicate operands) don't need
49     // to be constrained.
50     if (Reg == 0)
51       continue;
52 
53     // If the operand is a vreg, we should constrain its regclass, and only
54     // insert COPYs if that's impossible.
55     // constrainOperandRegClass does that for us.
56     MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
57                                        Reg, OpI));
58   }
59   return true;
60 }
61