1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp -----------*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the InstructionSelector class.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
14 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
15 #include "llvm/CodeGen/GlobalISel/Utils.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/IR/Constants.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 
22 #define DEBUG_TYPE "instructionselector"
23 
24 using namespace llvm;
25 
26 InstructionSelector::InstructionSelector() {}
27 
28 bool InstructionSelector::constrainSelectedInstRegOperands(
29     MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
30     const RegisterBankInfo &RBI) const {
31   MachineBasicBlock &MBB = *I.getParent();
32   MachineFunction &MF = *MBB.getParent();
33   MachineRegisterInfo &MRI = MF.getRegInfo();
34 
35   for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
36     MachineOperand &MO = I.getOperand(OpI);
37 
38     // There's nothing to be done on non-register operands.
39     if (!MO.isReg())
40       continue;
41 
42     DEBUG(dbgs() << "Converting operand: " << MO << '\n');
43     assert(MO.isReg() && "Unsupported non-reg operand");
44 
45     unsigned Reg = MO.getReg();
46     // Physical registers don't need to be constrained.
47     if (TRI.isPhysicalRegister(Reg))
48       continue;
49 
50     // Register operands with a value of 0 (e.g. predicate operands) don't need
51     // to be constrained.
52     if (Reg == 0)
53       continue;
54 
55     // If the operand is a vreg, we should constrain its regclass, and only
56     // insert COPYs if that's impossible.
57     // constrainOperandRegClass does that for us.
58     MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
59                                        Reg, OpI));
60 
61     // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
62     // done.
63     if (MO.isUse()) {
64       int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
65       if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
66         I.tieOperands(DefIdx, OpI);
67     }
68   }
69   return true;
70 }
71 
72 bool InstructionSelector::isOperandImmEqual(
73     const MachineOperand &MO, int64_t Value,
74     const MachineRegisterInfo &MRI) const {
75 
76   if (MO.isReg() && MO.getReg())
77     if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
78       return *VRegVal == Value;
79   return false;
80 }
81 
82 bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI) const {
83   return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() &&
84          MI.implicit_operands().begin() == MI.implicit_operands().end();
85 }
86