1 //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the InstructionSelector class.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
14 #include "llvm/CodeGen/GlobalISel/Utils.h"
15 #include "llvm/CodeGen/MachineBasicBlock.h"
16 #include "llvm/CodeGen/MachineFunction.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineOperand.h"
19 #include "llvm/MC/MCInstrDesc.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetRegisterInfo.h"
23 #include <cassert>
24 
25 #define DEBUG_TYPE "instructionselector"
26 
27 using namespace llvm;
28 
29 InstructionSelector::InstructionSelector() = default;
30 
31 bool InstructionSelector::constrainOperandRegToRegClass(
32     MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
33     const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
34     const RegisterBankInfo &RBI) const {
35   MachineBasicBlock &MBB = *I.getParent();
36   MachineFunction &MF = *MBB.getParent();
37   MachineRegisterInfo &MRI = MF.getRegInfo();
38 
39   return
40       constrainRegToClass(MRI, TII, RBI, I, I.getOperand(OpIdx).getReg(), RC);
41 }
42 
43 bool InstructionSelector::constrainSelectedInstRegOperands(
44     MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
45     const RegisterBankInfo &RBI) const {
46   MachineBasicBlock &MBB = *I.getParent();
47   MachineFunction &MF = *MBB.getParent();
48   MachineRegisterInfo &MRI = MF.getRegInfo();
49 
50   for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) {
51     MachineOperand &MO = I.getOperand(OpI);
52 
53     // There's nothing to be done on non-register operands.
54     if (!MO.isReg())
55       continue;
56 
57     DEBUG(dbgs() << "Converting operand: " << MO << '\n');
58     assert(MO.isReg() && "Unsupported non-reg operand");
59 
60     unsigned Reg = MO.getReg();
61     // Physical registers don't need to be constrained.
62     if (TRI.isPhysicalRegister(Reg))
63       continue;
64 
65     // Register operands with a value of 0 (e.g. predicate operands) don't need
66     // to be constrained.
67     if (Reg == 0)
68       continue;
69 
70     // If the operand is a vreg, we should constrain its regclass, and only
71     // insert COPYs if that's impossible.
72     // constrainOperandRegClass does that for us.
73     MO.setReg(constrainOperandRegClass(MF, TRI, MRI, TII, RBI, I, I.getDesc(),
74                                        Reg, OpI));
75 
76     // Tie uses to defs as indicated in MCInstrDesc if this hasn't already been
77     // done.
78     if (MO.isUse()) {
79       int DefIdx = I.getDesc().getOperandConstraint(OpI, MCOI::TIED_TO);
80       if (DefIdx != -1 && !I.isRegTiedToUseOperand(DefIdx))
81         I.tieOperands(DefIdx, OpI);
82     }
83   }
84   return true;
85 }
86 
87 bool InstructionSelector::isOperandImmEqual(
88     const MachineOperand &MO, int64_t Value,
89     const MachineRegisterInfo &MRI) const {
90   if (MO.isReg() && MO.getReg())
91     if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
92       return *VRegVal == Value;
93   return false;
94 }
95 
96 bool InstructionSelector::isObviouslySafeToFold(MachineInstr &MI) const {
97   return !MI.mayLoadOrStore() && !MI.hasUnmodeledSideEffects() &&
98          MI.implicit_operands().begin() == MI.implicit_operands().end();
99 }
100