1 //===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the InstructionSelect class.
10 //===----------------------------------------------------------------------===//
11 
12 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
13 #include "llvm/ADT/PostOrderIterator.h"
14 #include "llvm/ADT/ScopeExit.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/Analysis/BlockFrequencyInfo.h"
17 #include "llvm/Analysis/LazyBlockFrequencyInfo.h"
18 #include "llvm/Analysis/ProfileSummaryInfo.h"
19 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
20 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
21 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
22 #include "llvm/CodeGen/GlobalISel/Utils.h"
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/TargetInstrInfo.h"
28 #include "llvm/CodeGen/TargetLowering.h"
29 #include "llvm/CodeGen/TargetPassConfig.h"
30 #include "llvm/CodeGen/TargetSubtargetInfo.h"
31 #include "llvm/Config/config.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/TargetRegistry.h"
37 #include "llvm/Target/TargetMachine.h"
38 
39 #define DEBUG_TYPE "instruction-select"
40 
41 using namespace llvm;
42 
43 #ifdef LLVM_GISEL_COV_PREFIX
44 static cl::opt<std::string>
45     CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
46                    cl::desc("Record GlobalISel rule coverage files of this "
47                             "prefix if instrumentation was generated"));
48 #else
49 static const std::string CoveragePrefix;
50 #endif
51 
52 char InstructionSelect::ID = 0;
53 INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE,
54                       "Select target instructions out of generic instructions",
55                       false, false)
56 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
57 INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
58 INITIALIZE_PASS_DEPENDENCY(ProfileSummaryInfoWrapperPass)
59 INITIALIZE_PASS_DEPENDENCY(LazyBlockFrequencyInfoPass)
60 INITIALIZE_PASS_END(InstructionSelect, DEBUG_TYPE,
61                     "Select target instructions out of generic instructions",
62                     false, false)
63 
64 InstructionSelect::InstructionSelect(CodeGenOpt::Level OL)
65     : MachineFunctionPass(ID), OptLevel(OL) {}
66 
67 // In order not to crash when calling getAnalysis during testing with -run-pass
68 // we use the default opt level here instead of None, so that the addRequired()
69 // calls are made in getAnalysisUsage().
70 InstructionSelect::InstructionSelect()
71     : MachineFunctionPass(ID), OptLevel(CodeGenOpt::Default) {}
72 
73 void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
74   AU.addRequired<TargetPassConfig>();
75   if (OptLevel != CodeGenOpt::None) {
76     AU.addRequired<GISelKnownBitsAnalysis>();
77     AU.addPreserved<GISelKnownBitsAnalysis>();
78     AU.addRequired<ProfileSummaryInfoWrapperPass>();
79     LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
80   }
81   getSelectionDAGFallbackAnalysisUsage(AU);
82   MachineFunctionPass::getAnalysisUsage(AU);
83 }
84 
85 bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
86   // If the ISel pipeline failed, do not bother running that pass.
87   if (MF.getProperties().hasProperty(
88           MachineFunctionProperties::Property::FailedISel))
89     return false;
90 
91   LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
92 
93   const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
94   InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
95 
96   CodeGenOpt::Level OldOptLevel = OptLevel;
97   auto RestoreOptLevel = make_scope_exit([=]() { OptLevel = OldOptLevel; });
98   OptLevel = MF.getFunction().hasOptNone() ? CodeGenOpt::None
99                                            : MF.getTarget().getOptLevel();
100 
101   GISelKnownBits *KB = nullptr;
102   if (OptLevel != CodeGenOpt::None) {
103     KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
104     PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
105     if (PSI && PSI->hasProfileSummary())
106       BFI = &getAnalysis<LazyBlockFrequencyInfoPass>().getBFI();
107   }
108 
109   CodeGenCoverage CoverageInfo;
110   assert(ISel && "Cannot work without InstructionSelector");
111   ISel->setupMF(MF, KB, CoverageInfo, PSI, BFI);
112 
113   // An optimization remark emitter. Used to report failures.
114   MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
115 
116   // FIXME: There are many other MF/MFI fields we need to initialize.
117 
118   MachineRegisterInfo &MRI = MF.getRegInfo();
119 #ifndef NDEBUG
120   // Check that our input is fully legal: we require the function to have the
121   // Legalized property, so it should be.
122   // FIXME: This should be in the MachineVerifier, as the RegBankSelected
123   // property check already is.
124   if (!DisableGISelLegalityCheck)
125     if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
126       reportGISelFailure(MF, TPC, MORE, "gisel-select",
127                          "instruction is not legal", *MI);
128       return false;
129     }
130   // FIXME: We could introduce new blocks and will need to fix the outer loop.
131   // Until then, keep track of the number of blocks to assert that we don't.
132   const size_t NumBlocks = MF.size();
133 #endif
134 
135   // Keep track of selected blocks, so we can delete unreachable ones later.
136   DenseSet<MachineBasicBlock *> SelectedBlocks;
137 
138   for (MachineBasicBlock *MBB : post_order(&MF)) {
139     ISel->CurMBB = MBB;
140     SelectedBlocks.insert(MBB);
141     if (MBB->empty())
142       continue;
143 
144     // Select instructions in reverse block order. We permit erasing so have
145     // to resort to manually iterating and recognizing the begin (rend) case.
146     bool ReachedBegin = false;
147     for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
148          !ReachedBegin;) {
149 #ifndef NDEBUG
150       // Keep track of the insertion range for debug printing.
151       const auto AfterIt = std::next(MII);
152 #endif
153       // Select this instruction.
154       MachineInstr &MI = *MII;
155 
156       // And have our iterator point to the next instruction, if there is one.
157       if (MII == Begin)
158         ReachedBegin = true;
159       else
160         --MII;
161 
162       LLVM_DEBUG(dbgs() << "Selecting: \n  " << MI);
163 
164       // We could have folded this instruction away already, making it dead.
165       // If so, erase it.
166       if (isTriviallyDead(MI, MRI)) {
167         LLVM_DEBUG(dbgs() << "Is dead; erasing.\n");
168         MI.eraseFromParentAndMarkDBGValuesForRemoval();
169         continue;
170       }
171 
172       // Eliminate hints.
173       if (isPreISelGenericOptimizationHint(MI.getOpcode())) {
174         Register DstReg = MI.getOperand(0).getReg();
175         Register SrcReg = MI.getOperand(1).getReg();
176 
177         // At this point, the destination register class of the hint may have
178         // been decided.
179         //
180         // Propagate that through to the source register.
181         const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
182         if (DstRC)
183           MRI.setRegClass(SrcReg, DstRC);
184         assert(canReplaceReg(DstReg, SrcReg, MRI) &&
185                "Must be able to replace dst with src!");
186         MI.eraseFromParent();
187         MRI.replaceRegWith(DstReg, SrcReg);
188         continue;
189       }
190 
191       if (!ISel->select(MI)) {
192         // FIXME: It would be nice to dump all inserted instructions.  It's
193         // not obvious how, esp. considering select() can insert after MI.
194         reportGISelFailure(MF, TPC, MORE, "gisel-select", "cannot select", MI);
195         return false;
196       }
197 
198       // Dump the range of instructions that MI expanded into.
199       LLVM_DEBUG({
200         auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII);
201         dbgs() << "Into:\n";
202         for (auto &InsertedMI : make_range(InsertedBegin, AfterIt))
203           dbgs() << "  " << InsertedMI;
204         dbgs() << '\n';
205       });
206     }
207   }
208 
209   SmallVector<MachineBasicBlock *> BlocksToDelete;
210   for (MachineBasicBlock &MBB : MF) {
211     if (MBB.empty())
212       continue;
213 
214     if (!SelectedBlocks.contains(&MBB)) {
215       // This is an unreachable block and therefore hasn't been selected, since
216       // the main selection loop above uses a postorder block traversal. Mark
217       // the block for deletion.
218       if (!MBB.hasAddressTaken())
219         BlocksToDelete.push_back(&MBB);
220       continue;
221     }
222 
223     // Try to find redundant copies b/w vregs of the same register class.
224     bool ReachedBegin = false;
225     for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
226       // Select this instruction.
227       MachineInstr &MI = *MII;
228 
229       // And have our iterator point to the next instruction, if there is one.
230       if (MII == Begin)
231         ReachedBegin = true;
232       else
233         --MII;
234       if (MI.getOpcode() != TargetOpcode::COPY)
235         continue;
236       Register SrcReg = MI.getOperand(1).getReg();
237       Register DstReg = MI.getOperand(0).getReg();
238       if (Register::isVirtualRegister(SrcReg) &&
239           Register::isVirtualRegister(DstReg)) {
240         auto SrcRC = MRI.getRegClass(SrcReg);
241         auto DstRC = MRI.getRegClass(DstReg);
242         if (SrcRC == DstRC) {
243           MRI.replaceRegWith(DstReg, SrcReg);
244           MI.eraseFromParent();
245         }
246       }
247     }
248   }
249 
250 #ifndef NDEBUG
251   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
252   // Now that selection is complete, there are no more generic vregs.  Verify
253   // that the size of the now-constrained vreg is unchanged and that it has a
254   // register class.
255   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
256     unsigned VReg = Register::index2VirtReg(I);
257 
258     MachineInstr *MI = nullptr;
259     if (!MRI.def_empty(VReg))
260       MI = &*MRI.def_instr_begin(VReg);
261     else if (!MRI.use_empty(VReg))
262       MI = &*MRI.use_instr_begin(VReg);
263     if (!MI)
264       continue;
265 
266     const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
267     if (!RC) {
268       reportGISelFailure(MF, TPC, MORE, "gisel-select",
269                          "VReg has no regclass after selection", *MI);
270       return false;
271     }
272 
273     const LLT Ty = MRI.getType(VReg);
274     if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
275       reportGISelFailure(
276           MF, TPC, MORE, "gisel-select",
277           "VReg's low-level type and register class have different sizes", *MI);
278       return false;
279     }
280   }
281 
282   if (MF.size() != NumBlocks) {
283     MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
284                                       MF.getFunction().getSubprogram(),
285                                       /*MBB=*/nullptr);
286     R << "inserting blocks is not supported yet";
287     reportGISelFailure(MF, TPC, MORE, R);
288     return false;
289   }
290 #endif
291   for (auto *MBB : BlocksToDelete)
292     MBB->eraseFromParent();
293 
294   // Determine if there are any calls in this machine function. Ported from
295   // SelectionDAG.
296   MachineFrameInfo &MFI = MF.getFrameInfo();
297   for (const auto &MBB : MF) {
298     if (MFI.hasCalls() && MF.hasInlineAsm())
299       break;
300 
301     for (const auto &MI : MBB) {
302       if ((MI.isCall() && !MI.isReturn()) || MI.isStackAligningInlineAsm())
303         MFI.setHasCalls(true);
304       if (MI.isInlineAsm())
305         MF.setHasInlineAsm(true);
306     }
307   }
308 
309   // FIXME: FinalizeISel pass calls finalizeLowering, so it's called twice.
310   auto &TLI = *MF.getSubtarget().getTargetLowering();
311   TLI.finalizeLowering(MF);
312 
313   LLVM_DEBUG({
314     dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
315     for (auto RuleID : CoverageInfo.covered())
316       dbgs() << " id" << RuleID;
317     dbgs() << "\n\n";
318   });
319   CoverageInfo.emit(CoveragePrefix,
320                     TLI.getTargetMachine().getTarget().getBackendName());
321 
322   // If we successfully selected the function nothing is going to use the vreg
323   // types after us (otherwise MIRPrinter would need them). Make sure the types
324   // disappear.
325   MRI.clearVirtRegTypes();
326 
327   // FIXME: Should we accurately track changes?
328   return true;
329 }
330