1 //===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 /// \file 10 /// This file implements the InstructionSelect class. 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 14 #include "llvm/ADT/PostOrderIterator.h" 15 #include "llvm/ADT/Twine.h" 16 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" 17 #include "llvm/CodeGen/MachineRegisterInfo.h" 18 #include "llvm/IR/Function.h" 19 #include "llvm/Support/CommandLine.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Target/TargetSubtargetInfo.h" 22 23 #define DEBUG_TYPE "instruction-select" 24 25 using namespace llvm; 26 27 char InstructionSelect::ID = 0; 28 INITIALIZE_PASS(InstructionSelect, DEBUG_TYPE, 29 "Select target instructions out of generic instructions", 30 false, false); 31 32 InstructionSelect::InstructionSelect() : MachineFunctionPass(ID) { 33 initializeInstructionSelectPass(*PassRegistry::getPassRegistry()); 34 } 35 36 static void reportSelectionError(const MachineInstr &MI, const Twine &Message) { 37 const MachineFunction &MF = *MI.getParent()->getParent(); 38 std::string ErrStorage; 39 raw_string_ostream Err(ErrStorage); 40 Err << Message << ":\nIn function: " << MF.getName() << '\n' << MI << '\n'; 41 report_fatal_error(Err.str()); 42 } 43 44 bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) { 45 DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n'); 46 47 const InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector(); 48 assert(ISel && "Cannot work without InstructionSelector"); 49 50 // FIXME: freezeReservedRegs is now done in IRTranslator, but there are many 51 // other MF/MFI fields we need to initialize. 52 53 #ifndef NDEBUG 54 // FIXME: We could introduce new blocks and will need to fix the outer loop. 55 // Until then, keep track of the number of blocks to assert that we don't. 56 const size_t NumBlocks = MF.size(); 57 #endif 58 59 for (MachineBasicBlock *MBB : post_order(&MF)) { 60 for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(), 61 End = MBB->rend(); 62 MII != End;) { 63 MachineInstr &MI = *MII++; 64 DEBUG(dbgs() << "Selecting: " << MI << '\n'); 65 if (!ISel->select(MI)) 66 reportSelectionError(MI, "Cannot select"); 67 // FIXME: It would be nice to dump all inserted instructions. It's not 68 // obvious how, esp. considering select() can insert after MI. 69 } 70 } 71 72 assert(MF.size() == NumBlocks && "Inserting blocks is not supported yet"); 73 74 // Check that we did select everything. Do this separately to make sure we 75 // didn't miss any newly inserted instructions. 76 // FIXME: This (and other checks) should move into a verifier, predicated on 77 // a "post-isel" MachineFunction property. That would also let us selectively 78 // enable it depending on build configuration. 79 for (MachineBasicBlock &MBB : MF) { 80 for (MachineInstr &MI : MBB) { 81 if (isPreISelGenericOpcode(MI.getOpcode())) { 82 reportSelectionError( 83 MI, "Generic instruction survived instruction selection"); 84 } 85 } 86 } 87 88 // Now that selection is complete, there are no more generic vregs. 89 // FIXME: We're still discussing what to do with the vreg->size map: 90 // it's somewhat redundant (with the def MIs type size), but having to 91 // examine MIs is also awkward. Another alternative is to track the type on 92 // the vreg instead, but that's not ideal either, because it's saying that 93 // vregs have types, which they really don't. But then again, LLT is just 94 // a size and a "shape": it's probably the same information as regbank info. 95 MF.getRegInfo().clearVirtRegSizes(); 96 97 // FIXME: Should we accurately track changes? 98 return true; 99 } 100