1 //===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the InstructionSelect class.
10 //===----------------------------------------------------------------------===//
11 
12 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
13 #include "llvm/ADT/PostOrderIterator.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
16 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
18 #include "llvm/CodeGen/GlobalISel/Utils.h"
19 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/CodeGen/TargetLowering.h"
24 #include "llvm/CodeGen/TargetPassConfig.h"
25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
26 #include "llvm/Config/config.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Target/TargetMachine.h"
33 
34 #define DEBUG_TYPE "instruction-select"
35 
36 using namespace llvm;
37 
38 #ifdef LLVM_GISEL_COV_PREFIX
39 static cl::opt<std::string>
40     CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
41                    cl::desc("Record GlobalISel rule coverage files of this "
42                             "prefix if instrumentation was generated"));
43 #else
44 static const std::string CoveragePrefix;
45 #endif
46 
47 char InstructionSelect::ID = 0;
48 INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE,
49                       "Select target instructions out of generic instructions",
50                       false, false)
51 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
52 INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
53 INITIALIZE_PASS_END(InstructionSelect, DEBUG_TYPE,
54                     "Select target instructions out of generic instructions",
55                     false, false)
56 
57 InstructionSelect::InstructionSelect() : MachineFunctionPass(ID) { }
58 
59 void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
60   AU.addRequired<TargetPassConfig>();
61   AU.addRequired<GISelKnownBitsAnalysis>();
62   AU.addPreserved<GISelKnownBitsAnalysis>();
63   getSelectionDAGFallbackAnalysisUsage(AU);
64   MachineFunctionPass::getAnalysisUsage(AU);
65 }
66 
67 bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
68   // If the ISel pipeline failed, do not bother running that pass.
69   if (MF.getProperties().hasProperty(
70           MachineFunctionProperties::Property::FailedISel))
71     return false;
72 
73   LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
74   GISelKnownBits &KB = getAnalysis<GISelKnownBitsAnalysis>().get(MF);
75 
76   const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
77   InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
78   CodeGenCoverage CoverageInfo;
79   assert(ISel && "Cannot work without InstructionSelector");
80   ISel->setupMF(MF, KB, CoverageInfo);
81 
82   // An optimization remark emitter. Used to report failures.
83   MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
84 
85   // FIXME: There are many other MF/MFI fields we need to initialize.
86 
87   MachineRegisterInfo &MRI = MF.getRegInfo();
88 #ifndef NDEBUG
89   // Check that our input is fully legal: we require the function to have the
90   // Legalized property, so it should be.
91   // FIXME: This should be in the MachineVerifier, as the RegBankSelected
92   // property check already is.
93   if (!DisableGISelLegalityCheck)
94     if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
95       reportGISelFailure(MF, TPC, MORE, "gisel-select",
96                          "instruction is not legal", *MI);
97       return false;
98     }
99   // FIXME: We could introduce new blocks and will need to fix the outer loop.
100   // Until then, keep track of the number of blocks to assert that we don't.
101   const size_t NumBlocks = MF.size();
102 #endif
103 
104   for (MachineBasicBlock *MBB : post_order(&MF)) {
105     if (MBB->empty())
106       continue;
107 
108     // Select instructions in reverse block order. We permit erasing so have
109     // to resort to manually iterating and recognizing the begin (rend) case.
110     bool ReachedBegin = false;
111     for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
112          !ReachedBegin;) {
113 #ifndef NDEBUG
114       // Keep track of the insertion range for debug printing.
115       const auto AfterIt = std::next(MII);
116 #endif
117       // Select this instruction.
118       MachineInstr &MI = *MII;
119 
120       // And have our iterator point to the next instruction, if there is one.
121       if (MII == Begin)
122         ReachedBegin = true;
123       else
124         --MII;
125 
126       LLVM_DEBUG(dbgs() << "Selecting: \n  " << MI);
127 
128       // We could have folded this instruction away already, making it dead.
129       // If so, erase it.
130       if (isTriviallyDead(MI, MRI)) {
131         LLVM_DEBUG(dbgs() << "Is dead; erasing.\n");
132         MI.eraseFromParentAndMarkDBGValuesForRemoval();
133         continue;
134       }
135 
136       // Eliminate hints.
137       if (isPreISelGenericOptimizationHint(MI.getOpcode())) {
138         Register DstReg = MI.getOperand(0).getReg();
139         Register SrcReg = MI.getOperand(1).getReg();
140         MI.eraseFromParent();
141         MRI.replaceRegWith(DstReg, SrcReg);
142         continue;
143       }
144 
145       if (!ISel->select(MI)) {
146         // FIXME: It would be nice to dump all inserted instructions.  It's
147         // not obvious how, esp. considering select() can insert after MI.
148         reportGISelFailure(MF, TPC, MORE, "gisel-select", "cannot select", MI);
149         return false;
150       }
151 
152       // Dump the range of instructions that MI expanded into.
153       LLVM_DEBUG({
154         auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII);
155         dbgs() << "Into:\n";
156         for (auto &InsertedMI : make_range(InsertedBegin, AfterIt))
157           dbgs() << "  " << InsertedMI;
158         dbgs() << '\n';
159       });
160     }
161   }
162 
163   for (MachineBasicBlock &MBB : MF) {
164     if (MBB.empty())
165       continue;
166 
167     // Try to find redundant copies b/w vregs of the same register class.
168     bool ReachedBegin = false;
169     for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
170       // Select this instruction.
171       MachineInstr &MI = *MII;
172 
173       // And have our iterator point to the next instruction, if there is one.
174       if (MII == Begin)
175         ReachedBegin = true;
176       else
177         --MII;
178       if (MI.getOpcode() != TargetOpcode::COPY)
179         continue;
180       Register SrcReg = MI.getOperand(1).getReg();
181       Register DstReg = MI.getOperand(0).getReg();
182       if (Register::isVirtualRegister(SrcReg) &&
183           Register::isVirtualRegister(DstReg)) {
184         auto SrcRC = MRI.getRegClass(SrcReg);
185         auto DstRC = MRI.getRegClass(DstReg);
186         if (SrcRC == DstRC) {
187           MRI.replaceRegWith(DstReg, SrcReg);
188           MI.eraseFromParent();
189         }
190       }
191     }
192   }
193 
194 #ifndef NDEBUG
195   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
196   // Now that selection is complete, there are no more generic vregs.  Verify
197   // that the size of the now-constrained vreg is unchanged and that it has a
198   // register class.
199   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
200     unsigned VReg = Register::index2VirtReg(I);
201 
202     MachineInstr *MI = nullptr;
203     if (!MRI.def_empty(VReg))
204       MI = &*MRI.def_instr_begin(VReg);
205     else if (!MRI.use_empty(VReg))
206       MI = &*MRI.use_instr_begin(VReg);
207     if (!MI)
208       continue;
209 
210     const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
211     if (!RC) {
212       reportGISelFailure(MF, TPC, MORE, "gisel-select",
213                          "VReg has no regclass after selection", *MI);
214       return false;
215     }
216 
217     const LLT Ty = MRI.getType(VReg);
218     if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
219       reportGISelFailure(
220           MF, TPC, MORE, "gisel-select",
221           "VReg's low-level type and register class have different sizes", *MI);
222       return false;
223     }
224   }
225 
226   if (MF.size() != NumBlocks) {
227     MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
228                                       MF.getFunction().getSubprogram(),
229                                       /*MBB=*/nullptr);
230     R << "inserting blocks is not supported yet";
231     reportGISelFailure(MF, TPC, MORE, R);
232     return false;
233   }
234 #endif
235   // Determine if there are any calls in this machine function. Ported from
236   // SelectionDAG.
237   MachineFrameInfo &MFI = MF.getFrameInfo();
238   for (const auto &MBB : MF) {
239     if (MFI.hasCalls() && MF.hasInlineAsm())
240       break;
241 
242     for (const auto &MI : MBB) {
243       if ((MI.isCall() && !MI.isReturn()) || MI.isStackAligningInlineAsm())
244         MFI.setHasCalls(true);
245       if (MI.isInlineAsm())
246         MF.setHasInlineAsm(true);
247     }
248   }
249 
250   // FIXME: FinalizeISel pass calls finalizeLowering, so it's called twice.
251   auto &TLI = *MF.getSubtarget().getTargetLowering();
252   TLI.finalizeLowering(MF);
253 
254   LLVM_DEBUG({
255     dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
256     for (auto RuleID : CoverageInfo.covered())
257       dbgs() << " id" << RuleID;
258     dbgs() << "\n\n";
259   });
260   CoverageInfo.emit(CoveragePrefix,
261                     TLI.getTargetMachine().getTarget().getBackendName());
262 
263   // If we successfully selected the function nothing is going to use the vreg
264   // types after us (otherwise MIRPrinter would need them). Make sure the types
265   // disappear.
266   MRI.clearVirtRegTypes();
267 
268   // FIXME: Should we accurately track changes?
269   return true;
270 }
271