1 //===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the InstructionSelect class.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
14 #include "llvm/ADT/PostOrderIterator.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
17 #include "llvm/CodeGen/GlobalISel/MachineLegalizer.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/CodeGen/TargetPassConfig.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Target/TargetSubtargetInfo.h"
24 
25 #define DEBUG_TYPE "instruction-select"
26 
27 using namespace llvm;
28 
29 char InstructionSelect::ID = 0;
30 INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE,
31                       "Select target instructions out of generic instructions",
32                       false, false)
33 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
34 INITIALIZE_PASS_END(InstructionSelect, DEBUG_TYPE,
35                     "Select target instructions out of generic instructions",
36                     false, false)
37 
38 InstructionSelect::InstructionSelect() : MachineFunctionPass(ID) {
39   initializeInstructionSelectPass(*PassRegistry::getPassRegistry());
40 }
41 
42 void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
43   AU.addRequired<TargetPassConfig>();
44   MachineFunctionPass::getAnalysisUsage(AU);
45 }
46 
47 static void reportSelectionError(const MachineInstr &MI, const Twine &Message) {
48   const MachineFunction &MF = *MI.getParent()->getParent();
49   std::string ErrStorage;
50   raw_string_ostream Err(ErrStorage);
51   Err << Message << ":\nIn function: " << MF.getName() << '\n' << MI << '\n';
52   report_fatal_error(Err.str());
53 }
54 
55 bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
56   // If the ISel pipeline failed, do not bother running that pass.
57   if (MF.getProperties().hasProperty(
58           MachineFunctionProperties::Property::FailedISel))
59     return false;
60 
61   DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
62 
63   const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
64   const InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
65   assert(ISel && "Cannot work without InstructionSelector");
66 
67   // FIXME: freezeReservedRegs is now done in IRTranslator, but there are many
68   // other MF/MFI fields we need to initialize.
69 
70 #ifndef NDEBUG
71   // Check that our input is fully legal: we require the function to have the
72   // Legalized property, so it should be.
73   // FIXME: This should be in the MachineVerifier, but it can't use the
74   // MachineLegalizer as it's currently in the separate GlobalISel library.
75   // The RegBankSelected property is already checked in the verifier. Note
76   // that it has the same layering problem, but we only use inline methods so
77   // end up not needing to link against the GlobalISel library.
78   const MachineRegisterInfo &MRI = MF.getRegInfo();
79   if (const MachineLegalizer *MLI = MF.getSubtarget().getMachineLegalizer())
80     for (const MachineBasicBlock &MBB : MF)
81       for (const MachineInstr &MI : MBB)
82         if (isPreISelGenericOpcode(MI.getOpcode()) && !MLI->isLegal(MI, MRI))
83           reportSelectionError(MI, "Instruction is not legal");
84 
85 #endif
86   // FIXME: We could introduce new blocks and will need to fix the outer loop.
87   // Until then, keep track of the number of blocks to assert that we don't.
88   const size_t NumBlocks = MF.size();
89 
90   bool Failed = false;
91   for (MachineBasicBlock *MBB : post_order(&MF)) {
92     for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
93                                              End = MBB->rend();
94          MII != End;) {
95       MachineInstr &MI = *MII++;
96       DEBUG(dbgs() << "Selecting: " << MI << '\n');
97       if (!ISel->select(MI)) {
98         if (TPC.isGlobalISelAbortEnabled())
99           // FIXME: It would be nice to dump all inserted instructions.  It's
100           // not
101           // obvious how, esp. considering select() can insert after MI.
102           reportSelectionError(MI, "Cannot select");
103         Failed = true;
104         break;
105       }
106     }
107   }
108 
109   if (!TPC.isGlobalISelAbortEnabled() && (Failed || MF.size() == NumBlocks)) {
110     MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
111     return false;
112   }
113   assert(MF.size() == NumBlocks && "Inserting blocks is not supported yet");
114 
115   // Now that selection is complete, there are no more generic vregs.
116   // FIXME: We're still discussing what to do with the vreg->size map:
117   // it's somewhat redundant (with the def MIs type size), but having to
118   // examine MIs is also awkward.  Another alternative is to track the type on
119   // the vreg instead, but that's not ideal either, because it's saying that
120   // vregs have types, which they really don't. But then again, LLT is just
121   // a size and a "shape": it's probably the same information as regbank info.
122   MF.getRegInfo().clearVirtRegTypes();
123 
124   // FIXME: Should we accurately track changes?
125   return true;
126 }
127