1 //===- llvm/CodeGen/GlobalISel/InstructionSelect.cpp - InstructionSelect ---==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the InstructionSelect class.
10 //===----------------------------------------------------------------------===//
11 
12 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
13 #include "llvm/ADT/PostOrderIterator.h"
14 #include "llvm/ADT/Twine.h"
15 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
16 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
17 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
18 #include "llvm/CodeGen/GlobalISel/Utils.h"
19 #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/CodeGen/TargetLowering.h"
24 #include "llvm/CodeGen/TargetPassConfig.h"
25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
26 #include "llvm/Config/config.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/Function.h"
29 #include "llvm/Support/CommandLine.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/TargetRegistry.h"
32 #include "llvm/Target/TargetMachine.h"
33 
34 #define DEBUG_TYPE "instruction-select"
35 
36 using namespace llvm;
37 
38 #ifdef LLVM_GISEL_COV_PREFIX
39 static cl::opt<std::string>
40     CoveragePrefix("gisel-coverage-prefix", cl::init(LLVM_GISEL_COV_PREFIX),
41                    cl::desc("Record GlobalISel rule coverage files of this "
42                             "prefix if instrumentation was generated"));
43 #else
44 static const std::string CoveragePrefix;
45 #endif
46 
47 char InstructionSelect::ID = 0;
48 INITIALIZE_PASS_BEGIN(InstructionSelect, DEBUG_TYPE,
49                       "Select target instructions out of generic instructions",
50                       false, false)
51 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
52 INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
53 INITIALIZE_PASS_END(InstructionSelect, DEBUG_TYPE,
54                     "Select target instructions out of generic instructions",
55                     false, false)
56 
57 InstructionSelect::InstructionSelect() : MachineFunctionPass(ID) { }
58 
59 void InstructionSelect::getAnalysisUsage(AnalysisUsage &AU) const {
60   AU.addRequired<TargetPassConfig>();
61   AU.addRequired<GISelKnownBitsAnalysis>();
62   AU.addPreserved<GISelKnownBitsAnalysis>();
63   getSelectionDAGFallbackAnalysisUsage(AU);
64   MachineFunctionPass::getAnalysisUsage(AU);
65 }
66 
67 bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
68   // If the ISel pipeline failed, do not bother running that pass.
69   if (MF.getProperties().hasProperty(
70           MachineFunctionProperties::Property::FailedISel))
71     return false;
72 
73   LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
74   GISelKnownBits &KB = getAnalysis<GISelKnownBitsAnalysis>().get(MF);
75 
76   const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
77   InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
78   CodeGenCoverage CoverageInfo;
79   assert(ISel && "Cannot work without InstructionSelector");
80   ISel->setupMF(MF, KB, CoverageInfo);
81 
82   // An optimization remark emitter. Used to report failures.
83   MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
84 
85   // FIXME: There are many other MF/MFI fields we need to initialize.
86 
87   MachineRegisterInfo &MRI = MF.getRegInfo();
88 #ifndef NDEBUG
89   // Check that our input is fully legal: we require the function to have the
90   // Legalized property, so it should be.
91   // FIXME: This should be in the MachineVerifier, as the RegBankSelected
92   // property check already is.
93   if (!DisableGISelLegalityCheck)
94     if (const MachineInstr *MI = machineFunctionIsIllegal(MF)) {
95       reportGISelFailure(MF, TPC, MORE, "gisel-select",
96                          "instruction is not legal", *MI);
97       return false;
98     }
99   // FIXME: We could introduce new blocks and will need to fix the outer loop.
100   // Until then, keep track of the number of blocks to assert that we don't.
101   const size_t NumBlocks = MF.size();
102 #endif
103 
104   for (MachineBasicBlock *MBB : post_order(&MF)) {
105     if (MBB->empty())
106       continue;
107 
108     // Select instructions in reverse block order. We permit erasing so have
109     // to resort to manually iterating and recognizing the begin (rend) case.
110     bool ReachedBegin = false;
111     for (auto MII = std::prev(MBB->end()), Begin = MBB->begin();
112          !ReachedBegin;) {
113 #ifndef NDEBUG
114       // Keep track of the insertion range for debug printing.
115       const auto AfterIt = std::next(MII);
116 #endif
117       // Select this instruction.
118       MachineInstr &MI = *MII;
119 
120       // And have our iterator point to the next instruction, if there is one.
121       if (MII == Begin)
122         ReachedBegin = true;
123       else
124         --MII;
125 
126       LLVM_DEBUG(dbgs() << "Selecting: \n  " << MI);
127 
128       // We could have folded this instruction away already, making it dead.
129       // If so, erase it.
130       if (isTriviallyDead(MI, MRI)) {
131         LLVM_DEBUG(dbgs() << "Is dead; erasing.\n");
132         MI.eraseFromParentAndMarkDBGValuesForRemoval();
133         continue;
134       }
135 
136       // Eliminate hints.
137       if (isPreISelGenericOptimizationHint(MI.getOpcode())) {
138         Register DstReg = MI.getOperand(0).getReg();
139         Register SrcReg = MI.getOperand(1).getReg();
140 
141         // At this point, the destination register class of the hint may have
142         // been decided.
143         //
144         // Propagate that through to the source register.
145         const TargetRegisterClass *DstRC = MRI.getRegClassOrNull(DstReg);
146         if (DstRC)
147           MRI.setRegClass(SrcReg, DstRC);
148         assert(canReplaceReg(DstReg, SrcReg, MRI) &&
149                "Must be able to replace dst with src!");
150         MI.eraseFromParent();
151         MRI.replaceRegWith(DstReg, SrcReg);
152         continue;
153       }
154 
155       if (!ISel->select(MI)) {
156         // FIXME: It would be nice to dump all inserted instructions.  It's
157         // not obvious how, esp. considering select() can insert after MI.
158         reportGISelFailure(MF, TPC, MORE, "gisel-select", "cannot select", MI);
159         return false;
160       }
161 
162       // Dump the range of instructions that MI expanded into.
163       LLVM_DEBUG({
164         auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII);
165         dbgs() << "Into:\n";
166         for (auto &InsertedMI : make_range(InsertedBegin, AfterIt))
167           dbgs() << "  " << InsertedMI;
168         dbgs() << '\n';
169       });
170     }
171   }
172 
173   for (MachineBasicBlock &MBB : MF) {
174     if (MBB.empty())
175       continue;
176 
177     // Try to find redundant copies b/w vregs of the same register class.
178     bool ReachedBegin = false;
179     for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
180       // Select this instruction.
181       MachineInstr &MI = *MII;
182 
183       // And have our iterator point to the next instruction, if there is one.
184       if (MII == Begin)
185         ReachedBegin = true;
186       else
187         --MII;
188       if (MI.getOpcode() != TargetOpcode::COPY)
189         continue;
190       Register SrcReg = MI.getOperand(1).getReg();
191       Register DstReg = MI.getOperand(0).getReg();
192       if (Register::isVirtualRegister(SrcReg) &&
193           Register::isVirtualRegister(DstReg)) {
194         auto SrcRC = MRI.getRegClass(SrcReg);
195         auto DstRC = MRI.getRegClass(DstReg);
196         if (SrcRC == DstRC) {
197           MRI.replaceRegWith(DstReg, SrcReg);
198           MI.eraseFromParent();
199         }
200       }
201     }
202   }
203 
204 #ifndef NDEBUG
205   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
206   // Now that selection is complete, there are no more generic vregs.  Verify
207   // that the size of the now-constrained vreg is unchanged and that it has a
208   // register class.
209   for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
210     unsigned VReg = Register::index2VirtReg(I);
211 
212     MachineInstr *MI = nullptr;
213     if (!MRI.def_empty(VReg))
214       MI = &*MRI.def_instr_begin(VReg);
215     else if (!MRI.use_empty(VReg))
216       MI = &*MRI.use_instr_begin(VReg);
217     if (!MI)
218       continue;
219 
220     const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
221     if (!RC) {
222       reportGISelFailure(MF, TPC, MORE, "gisel-select",
223                          "VReg has no regclass after selection", *MI);
224       return false;
225     }
226 
227     const LLT Ty = MRI.getType(VReg);
228     if (Ty.isValid() && Ty.getSizeInBits() > TRI.getRegSizeInBits(*RC)) {
229       reportGISelFailure(
230           MF, TPC, MORE, "gisel-select",
231           "VReg's low-level type and register class have different sizes", *MI);
232       return false;
233     }
234   }
235 
236   if (MF.size() != NumBlocks) {
237     MachineOptimizationRemarkMissed R("gisel-select", "GISelFailure",
238                                       MF.getFunction().getSubprogram(),
239                                       /*MBB=*/nullptr);
240     R << "inserting blocks is not supported yet";
241     reportGISelFailure(MF, TPC, MORE, R);
242     return false;
243   }
244 #endif
245   // Determine if there are any calls in this machine function. Ported from
246   // SelectionDAG.
247   MachineFrameInfo &MFI = MF.getFrameInfo();
248   for (const auto &MBB : MF) {
249     if (MFI.hasCalls() && MF.hasInlineAsm())
250       break;
251 
252     for (const auto &MI : MBB) {
253       if ((MI.isCall() && !MI.isReturn()) || MI.isStackAligningInlineAsm())
254         MFI.setHasCalls(true);
255       if (MI.isInlineAsm())
256         MF.setHasInlineAsm(true);
257     }
258   }
259 
260   // FIXME: FinalizeISel pass calls finalizeLowering, so it's called twice.
261   auto &TLI = *MF.getSubtarget().getTargetLowering();
262   TLI.finalizeLowering(MF);
263 
264   LLVM_DEBUG({
265     dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
266     for (auto RuleID : CoverageInfo.covered())
267       dbgs() << " id" << RuleID;
268     dbgs() << "\n\n";
269   });
270   CoverageInfo.emit(CoveragePrefix,
271                     TLI.getTargetMachine().getTarget().getBackendName());
272 
273   // If we successfully selected the function nothing is going to use the vreg
274   // types after us (otherwise MIRPrinter would need them). Make sure the types
275   // disappear.
276   MRI.clearVirtRegTypes();
277 
278   // FIXME: Should we accurately track changes?
279   return true;
280 }
281