1 //===-- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator --*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the IRTranslator class.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
14 
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/IR/Constant.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/Type.h"
23 #include "llvm/IR/Value.h"
24 #include "llvm/Target/TargetLowering.h"
25 
26 #define DEBUG_TYPE "irtranslator"
27 
28 using namespace llvm;
29 
30 char IRTranslator::ID = 0;
31 INITIALIZE_PASS(IRTranslator, "irtranslator", "IRTranslator LLVM IR -> MI",
32                 false, false);
33 
34 IRTranslator::IRTranslator() : MachineFunctionPass(ID), MRI(nullptr) {
35   initializeIRTranslatorPass(*PassRegistry::getPassRegistry());
36 }
37 
38 unsigned IRTranslator::getOrCreateVReg(const Value &Val) {
39   unsigned &ValReg = ValToVReg[&Val];
40   // Check if this is the first time we see Val.
41   if (!ValReg) {
42     // Fill ValRegsSequence with the sequence of registers
43     // we need to concat together to produce the value.
44     assert(Val.getType()->isSized() &&
45            "Don't know how to create an empty vreg");
46     assert(!Val.getType()->isAggregateType() && "Not yet implemented");
47     unsigned Size = DL->getTypeSizeInBits(Val.getType());
48     unsigned VReg = MRI->createGenericVirtualRegister(Size);
49     ValReg = VReg;
50     assert(!isa<Constant>(Val) && "Not yet implemented");
51   }
52   return ValReg;
53 }
54 
55 MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock &BB) {
56   MachineBasicBlock *&MBB = BBToMBB[&BB];
57   if (!MBB) {
58     MachineFunction &MF = MIRBuilder.getMF();
59     MBB = MF.CreateMachineBasicBlock();
60     MF.push_back(MBB);
61   }
62   return *MBB;
63 }
64 
65 bool IRTranslator::translateBinaryOp(unsigned Opcode, const Instruction &Inst) {
66   // Get or create a virtual register for each value.
67   // Unless the value is a Constant => loadimm cst?
68   // or inline constant each time?
69   // Creation of a virtual register needs to have a size.
70   unsigned Op0 = getOrCreateVReg(*Inst.getOperand(0));
71   unsigned Op1 = getOrCreateVReg(*Inst.getOperand(1));
72   unsigned Res = getOrCreateVReg(Inst);
73   MIRBuilder.buildInstr(Opcode, LLT{*Inst.getType()}, Res, Op0, Op1);
74   return true;
75 }
76 
77 bool IRTranslator::translateReturn(const Instruction &Inst) {
78   assert(isa<ReturnInst>(Inst) && "Return expected");
79   const Value *Ret = cast<ReturnInst>(Inst).getReturnValue();
80   // The target may mess up with the insertion point, but
81   // this is not important as a return is the last instruction
82   // of the block anyway.
83   return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
84 }
85 
86 bool IRTranslator::translateBr(const Instruction &Inst) {
87   assert(isa<BranchInst>(Inst) && "Branch expected");
88   const BranchInst &BrInst = *cast<BranchInst>(&Inst);
89   if (BrInst.isUnconditional()) {
90     const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getOperand(0));
91     MachineBasicBlock &TgtBB = getOrCreateBB(BrTgt);
92     MIRBuilder.buildInstr(TargetOpcode::G_BR, LLT{*BrTgt.getType()}, TgtBB);
93   } else {
94     assert(0 && "Not yet implemented");
95   }
96   // Link successors.
97   MachineBasicBlock &CurBB = MIRBuilder.getMBB();
98   for (const BasicBlock *Succ : BrInst.successors())
99     CurBB.addSuccessor(&getOrCreateBB(*Succ));
100   return true;
101 }
102 
103 bool IRTranslator::translateBitCast(const CastInst &CI) {
104   if (LLT{*CI.getDestTy()} == LLT{*CI.getSrcTy()}) {
105     MIRBuilder.buildInstr(TargetOpcode::COPY, getOrCreateVReg(CI),
106                           getOrCreateVReg(*CI.getOperand(0)));
107     return true;
108   }
109   return translateCast(TargetOpcode::G_BITCAST, CI);
110 }
111 
112 bool IRTranslator::translateCast(unsigned Opcode, const CastInst &CI) {
113   unsigned Op = getOrCreateVReg(*CI.getOperand(0));
114   unsigned Res = getOrCreateVReg(CI);
115   MIRBuilder.buildInstr(Opcode, {LLT{*CI.getDestTy()}, LLT{*CI.getSrcTy()}},
116                         Res, Op);
117   return true;
118 }
119 
120 bool IRTranslator::translateStaticAlloca(const AllocaInst &AI) {
121   assert(AI.isStaticAlloca() && "only handle static allocas now");
122   MachineFunction &MF = MIRBuilder.getMF();
123   unsigned ElementSize = DL->getTypeStoreSize(AI.getAllocatedType());
124   unsigned Size =
125       ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
126 
127   unsigned Alignment = AI.getAlignment();
128   if (!Alignment)
129     Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
130 
131   unsigned Res = getOrCreateVReg(AI);
132   int FI = MF.getFrameInfo()->CreateStackObject(Size, Alignment, false, &AI);
133   MIRBuilder.buildFrameIndex(LLT::pointer(0), Res, FI);
134   return true;
135 }
136 
137 bool IRTranslator::translate(const Instruction &Inst) {
138   MIRBuilder.setDebugLoc(Inst.getDebugLoc());
139   switch(Inst.getOpcode()) {
140   // Arithmetic operations.
141   case Instruction::Add:
142     return translateBinaryOp(TargetOpcode::G_ADD, Inst);
143   case Instruction::Sub:
144     return translateBinaryOp(TargetOpcode::G_SUB, Inst);
145 
146   // Bitwise operations.
147   case Instruction::And:
148     return translateBinaryOp(TargetOpcode::G_AND, Inst);
149   case Instruction::Or:
150     return translateBinaryOp(TargetOpcode::G_OR, Inst);
151 
152   // Branch operations.
153   case Instruction::Br:
154     return translateBr(Inst);
155   case Instruction::Ret:
156     return translateReturn(Inst);
157 
158   // Casts
159   case Instruction::BitCast:
160     return translateBitCast(cast<CastInst>(Inst));
161   case Instruction::IntToPtr:
162     return translateCast(TargetOpcode::G_INTTOPTR, cast<CastInst>(Inst));
163   case Instruction::PtrToInt:
164     return translateCast(TargetOpcode::G_PTRTOINT, cast<CastInst>(Inst));
165 
166   case Instruction::Alloca:
167     return translateStaticAlloca(cast<AllocaInst>(Inst));
168 
169   default:
170     llvm_unreachable("Opcode not supported");
171   }
172 }
173 
174 
175 void IRTranslator::finalize() {
176   // Release the memory used by the different maps we
177   // needed during the translation.
178   ValToVReg.clear();
179   Constants.clear();
180 }
181 
182 bool IRTranslator::runOnMachineFunction(MachineFunction &MF) {
183   const Function &F = *MF.getFunction();
184   if (F.empty())
185     return false;
186   CLI = MF.getSubtarget().getCallLowering();
187   MIRBuilder.setMF(MF);
188   MRI = &MF.getRegInfo();
189   DL = &F.getParent()->getDataLayout();
190 
191   // Setup the arguments.
192   MachineBasicBlock &MBB = getOrCreateBB(F.front());
193   MIRBuilder.setMBB(MBB);
194   SmallVector<unsigned, 8> VRegArgs;
195   for (const Argument &Arg: F.args())
196     VRegArgs.push_back(getOrCreateVReg(Arg));
197   bool Succeeded =
198       CLI->lowerFormalArguments(MIRBuilder, F.getArgumentList(), VRegArgs);
199   if (!Succeeded)
200     report_fatal_error("Unable to lower arguments");
201 
202   for (const BasicBlock &BB: F) {
203     MachineBasicBlock &MBB = getOrCreateBB(BB);
204     // Set the insertion point of all the following translations to
205     // the end of this basic block.
206     MIRBuilder.setMBB(MBB);
207     for (const Instruction &Inst: BB) {
208       bool Succeeded = translate(Inst);
209       if (!Succeeded) {
210         DEBUG(dbgs() << "Cannot translate: " << Inst << '\n');
211         report_fatal_error("Unable to translate instruction");
212       }
213     }
214   }
215 
216   // Now that the MachineFrameInfo has been configured, no further changes to
217   // the reserved registers are possible.
218   MRI->freezeReservedRegs(MF);
219 
220   return false;
221 }
222