1 //===- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator ---*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the IRTranslator class.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
14 #include "llvm/ADT/PostOrderIterator.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/ADT/ScopeExit.h"
17 #include "llvm/ADT/SmallSet.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/Analysis/OptimizationRemarkEmitter.h"
20 #include "llvm/CodeGen/Analysis.h"
21 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
22 #include "llvm/CodeGen/LowLevelType.h"
23 #include "llvm/CodeGen/MachineBasicBlock.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineMemOperand.h"
28 #include "llvm/CodeGen/MachineOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/StackProtector.h"
31 #include "llvm/CodeGen/TargetFrameLowering.h"
32 #include "llvm/CodeGen/TargetLowering.h"
33 #include "llvm/CodeGen/TargetPassConfig.h"
34 #include "llvm/CodeGen/TargetRegisterInfo.h"
35 #include "llvm/CodeGen/TargetSubtargetInfo.h"
36 #include "llvm/IR/BasicBlock.h"
37 #include "llvm/IR/CFG.h"
38 #include "llvm/IR/Constant.h"
39 #include "llvm/IR/Constants.h"
40 #include "llvm/IR/DataLayout.h"
41 #include "llvm/IR/DebugInfo.h"
42 #include "llvm/IR/DerivedTypes.h"
43 #include "llvm/IR/Function.h"
44 #include "llvm/IR/GetElementPtrTypeIterator.h"
45 #include "llvm/IR/InlineAsm.h"
46 #include "llvm/IR/InstrTypes.h"
47 #include "llvm/IR/Instructions.h"
48 #include "llvm/IR/IntrinsicInst.h"
49 #include "llvm/IR/Intrinsics.h"
50 #include "llvm/IR/LLVMContext.h"
51 #include "llvm/IR/Metadata.h"
52 #include "llvm/IR/Type.h"
53 #include "llvm/IR/User.h"
54 #include "llvm/IR/Value.h"
55 #include "llvm/MC/MCContext.h"
56 #include "llvm/Pass.h"
57 #include "llvm/Support/Casting.h"
58 #include "llvm/Support/CodeGen.h"
59 #include "llvm/Support/Debug.h"
60 #include "llvm/Support/ErrorHandling.h"
61 #include "llvm/Support/LowLevelTypeImpl.h"
62 #include "llvm/Support/MathExtras.h"
63 #include "llvm/Support/raw_ostream.h"
64 #include "llvm/Target/TargetIntrinsicInfo.h"
65 #include "llvm/Target/TargetMachine.h"
66 #include <algorithm>
67 #include <cassert>
68 #include <cstdint>
69 #include <iterator>
70 #include <string>
71 #include <utility>
72 #include <vector>
73 
74 #define DEBUG_TYPE "irtranslator"
75 
76 using namespace llvm;
77 
78 char IRTranslator::ID = 0;
79 
80 INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
81                 false, false)
82 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
83 INITIALIZE_PASS_END(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
84                 false, false)
85 
86 static void reportTranslationError(MachineFunction &MF,
87                                    const TargetPassConfig &TPC,
88                                    OptimizationRemarkEmitter &ORE,
89                                    OptimizationRemarkMissed &R) {
90   MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
91 
92   // Print the function name explicitly if we don't have a debug location (which
93   // makes the diagnostic less useful) or if we're going to emit a raw error.
94   if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
95     R << (" (in function: " + MF.getName() + ")").str();
96 
97   if (TPC.isGlobalISelAbortEnabled())
98     report_fatal_error(R.getMsg());
99   else
100     ORE.emit(R);
101 }
102 
103 IRTranslator::IRTranslator() : MachineFunctionPass(ID) {
104   initializeIRTranslatorPass(*PassRegistry::getPassRegistry());
105 }
106 
107 void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const {
108   AU.addRequired<StackProtector>();
109   AU.addRequired<TargetPassConfig>();
110   getSelectionDAGFallbackAnalysisUsage(AU);
111   MachineFunctionPass::getAnalysisUsage(AU);
112 }
113 
114 static void computeValueLLTs(const DataLayout &DL, Type &Ty,
115                              SmallVectorImpl<LLT> &ValueTys,
116                              SmallVectorImpl<uint64_t> *Offsets = nullptr,
117                              uint64_t StartingOffset = 0) {
118   // Given a struct type, recursively traverse the elements.
119   if (StructType *STy = dyn_cast<StructType>(&Ty)) {
120     const StructLayout *SL = DL.getStructLayout(STy);
121     for (unsigned I = 0, E = STy->getNumElements(); I != E; ++I)
122       computeValueLLTs(DL, *STy->getElementType(I), ValueTys, Offsets,
123                        StartingOffset + SL->getElementOffset(I));
124     return;
125   }
126   // Given an array type, recursively traverse the elements.
127   if (ArrayType *ATy = dyn_cast<ArrayType>(&Ty)) {
128     Type *EltTy = ATy->getElementType();
129     uint64_t EltSize = DL.getTypeAllocSize(EltTy);
130     for (unsigned i = 0, e = ATy->getNumElements(); i != e; ++i)
131       computeValueLLTs(DL, *EltTy, ValueTys, Offsets,
132                        StartingOffset + i * EltSize);
133     return;
134   }
135   // Interpret void as zero return values.
136   if (Ty.isVoidTy())
137     return;
138   // Base case: we can get an LLT for this LLVM IR type.
139   ValueTys.push_back(getLLTForType(Ty, DL));
140   if (Offsets != nullptr)
141     Offsets->push_back(StartingOffset * 8);
142 }
143 
144 IRTranslator::ValueToVRegInfo::VRegListT &
145 IRTranslator::allocateVRegs(const Value &Val) {
146   assert(!VMap.contains(Val) && "Value already allocated in VMap");
147   auto *Regs = VMap.getVRegs(Val);
148   auto *Offsets = VMap.getOffsets(Val);
149   SmallVector<LLT, 4> SplitTys;
150   computeValueLLTs(*DL, *Val.getType(), SplitTys,
151                    Offsets->empty() ? Offsets : nullptr);
152   for (unsigned i = 0; i < SplitTys.size(); ++i)
153     Regs->push_back(0);
154   return *Regs;
155 }
156 
157 ArrayRef<unsigned> IRTranslator::getOrCreateVRegs(const Value &Val) {
158   auto VRegsIt = VMap.findVRegs(Val);
159   if (VRegsIt != VMap.vregs_end())
160     return *VRegsIt->second;
161 
162   if (Val.getType()->isVoidTy())
163     return *VMap.getVRegs(Val);
164 
165   // Create entry for this type.
166   auto *VRegs = VMap.getVRegs(Val);
167   auto *Offsets = VMap.getOffsets(Val);
168 
169   assert(Val.getType()->isSized() &&
170          "Don't know how to create an empty vreg");
171 
172   SmallVector<LLT, 4> SplitTys;
173   computeValueLLTs(*DL, *Val.getType(), SplitTys,
174                    Offsets->empty() ? Offsets : nullptr);
175 
176   if (!isa<Constant>(Val)) {
177     for (auto Ty : SplitTys)
178       VRegs->push_back(MRI->createGenericVirtualRegister(Ty));
179     return *VRegs;
180   }
181 
182   if (Val.getType()->isAggregateType()) {
183     // UndefValue, ConstantAggregateZero
184     auto &C = cast<Constant>(Val);
185     unsigned Idx = 0;
186     while (auto Elt = C.getAggregateElement(Idx++)) {
187       auto EltRegs = getOrCreateVRegs(*Elt);
188       std::copy(EltRegs.begin(), EltRegs.end(), std::back_inserter(*VRegs));
189     }
190   } else {
191     assert(SplitTys.size() == 1 && "unexpectedly split LLT");
192     VRegs->push_back(MRI->createGenericVirtualRegister(SplitTys[0]));
193     bool Success = translate(cast<Constant>(Val), VRegs->front());
194     if (!Success) {
195       OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
196                                  MF->getFunction().getSubprogram(),
197                                  &MF->getFunction().getEntryBlock());
198       R << "unable to translate constant: " << ore::NV("Type", Val.getType());
199       reportTranslationError(*MF, *TPC, *ORE, R);
200       return *VRegs;
201     }
202   }
203 
204   return *VRegs;
205 }
206 
207 int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
208   if (FrameIndices.find(&AI) != FrameIndices.end())
209     return FrameIndices[&AI];
210 
211   unsigned ElementSize = DL->getTypeStoreSize(AI.getAllocatedType());
212   unsigned Size =
213       ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
214 
215   // Always allocate at least one byte.
216   Size = std::max(Size, 1u);
217 
218   unsigned Alignment = AI.getAlignment();
219   if (!Alignment)
220     Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
221 
222   int &FI = FrameIndices[&AI];
223   FI = MF->getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
224   return FI;
225 }
226 
227 unsigned IRTranslator::getMemOpAlignment(const Instruction &I) {
228   unsigned Alignment = 0;
229   Type *ValTy = nullptr;
230   if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) {
231     Alignment = SI->getAlignment();
232     ValTy = SI->getValueOperand()->getType();
233   } else if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) {
234     Alignment = LI->getAlignment();
235     ValTy = LI->getType();
236   } else if (const AtomicCmpXchgInst *AI = dyn_cast<AtomicCmpXchgInst>(&I)) {
237     // TODO(PR27168): This instruction has no alignment attribute, but unlike
238     // the default alignment for load/store, the default here is to assume
239     // it has NATURAL alignment, not DataLayout-specified alignment.
240     const DataLayout &DL = AI->getModule()->getDataLayout();
241     Alignment = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
242     ValTy = AI->getCompareOperand()->getType();
243   } else if (const AtomicRMWInst *AI = dyn_cast<AtomicRMWInst>(&I)) {
244     // TODO(PR27168): This instruction has no alignment attribute, but unlike
245     // the default alignment for load/store, the default here is to assume
246     // it has NATURAL alignment, not DataLayout-specified alignment.
247     const DataLayout &DL = AI->getModule()->getDataLayout();
248     Alignment = DL.getTypeStoreSize(AI->getValOperand()->getType());
249     ValTy = AI->getType();
250   } else {
251     OptimizationRemarkMissed R("gisel-irtranslator", "", &I);
252     R << "unable to translate memop: " << ore::NV("Opcode", &I);
253     reportTranslationError(*MF, *TPC, *ORE, R);
254     return 1;
255   }
256 
257   return Alignment ? Alignment : DL->getABITypeAlignment(ValTy);
258 }
259 
260 MachineBasicBlock &IRTranslator::getMBB(const BasicBlock &BB) {
261   MachineBasicBlock *&MBB = BBToMBB[&BB];
262   assert(MBB && "BasicBlock was not encountered before");
263   return *MBB;
264 }
265 
266 void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
267   assert(NewPred && "new predecessor must be a real MachineBasicBlock");
268   MachinePreds[Edge].push_back(NewPred);
269 }
270 
271 bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
272                                      MachineIRBuilder &MIRBuilder) {
273   // FIXME: handle signed/unsigned wrapping flags.
274 
275   // Get or create a virtual register for each value.
276   // Unless the value is a Constant => loadimm cst?
277   // or inline constant each time?
278   // Creation of a virtual register needs to have a size.
279   unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
280   unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
281   unsigned Res = getOrCreateVReg(U);
282   MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1);
283   return true;
284 }
285 
286 bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
287   // -0.0 - X --> G_FNEG
288   if (isa<Constant>(U.getOperand(0)) &&
289       U.getOperand(0) == ConstantFP::getZeroValueForNegation(U.getType())) {
290     MIRBuilder.buildInstr(TargetOpcode::G_FNEG)
291         .addDef(getOrCreateVReg(U))
292         .addUse(getOrCreateVReg(*U.getOperand(1)));
293     return true;
294   }
295   return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
296 }
297 
298 bool IRTranslator::translateCompare(const User &U,
299                                     MachineIRBuilder &MIRBuilder) {
300   const CmpInst *CI = dyn_cast<CmpInst>(&U);
301   unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
302   unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
303   unsigned Res = getOrCreateVReg(U);
304   CmpInst::Predicate Pred =
305       CI ? CI->getPredicate() : static_cast<CmpInst::Predicate>(
306                                     cast<ConstantExpr>(U).getPredicate());
307   if (CmpInst::isIntPredicate(Pred))
308     MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
309   else if (Pred == CmpInst::FCMP_FALSE)
310     MIRBuilder.buildCopy(
311         Res, getOrCreateVReg(*Constant::getNullValue(CI->getType())));
312   else if (Pred == CmpInst::FCMP_TRUE)
313     MIRBuilder.buildCopy(
314         Res, getOrCreateVReg(*Constant::getAllOnesValue(CI->getType())));
315   else
316     MIRBuilder.buildFCmp(Pred, Res, Op0, Op1);
317 
318   return true;
319 }
320 
321 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
322   const ReturnInst &RI = cast<ReturnInst>(U);
323   const Value *Ret = RI.getReturnValue();
324   if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
325     Ret = nullptr;
326 
327   ArrayRef<unsigned> VRegs;
328   if (Ret)
329     VRegs = getOrCreateVRegs(*Ret);
330 
331   // The target may mess up with the insertion point, but
332   // this is not important as a return is the last instruction
333   // of the block anyway.
334 
335   return CLI->lowerReturn(MIRBuilder, Ret, VRegs);
336 }
337 
338 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
339   const BranchInst &BrInst = cast<BranchInst>(U);
340   unsigned Succ = 0;
341   if (!BrInst.isUnconditional()) {
342     // We want a G_BRCOND to the true BB followed by an unconditional branch.
343     unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
344     const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
345     MachineBasicBlock &TrueBB = getMBB(TrueTgt);
346     MIRBuilder.buildBrCond(Tst, TrueBB);
347   }
348 
349   const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
350   MachineBasicBlock &TgtBB = getMBB(BrTgt);
351   MachineBasicBlock &CurBB = MIRBuilder.getMBB();
352 
353   // If the unconditional target is the layout successor, fallthrough.
354   if (!CurBB.isLayoutSuccessor(&TgtBB))
355     MIRBuilder.buildBr(TgtBB);
356 
357   // Link successors.
358   for (const BasicBlock *Succ : BrInst.successors())
359     CurBB.addSuccessor(&getMBB(*Succ));
360   return true;
361 }
362 
363 bool IRTranslator::translateSwitch(const User &U,
364                                    MachineIRBuilder &MIRBuilder) {
365   // For now, just translate as a chain of conditional branches.
366   // FIXME: could we share most of the logic/code in
367   // SelectionDAGBuilder::visitSwitch between SelectionDAG and GlobalISel?
368   // At first sight, it seems most of the logic in there is independent of
369   // SelectionDAG-specifics and a lot of work went in to optimize switch
370   // lowering in there.
371 
372   const SwitchInst &SwInst = cast<SwitchInst>(U);
373   const unsigned SwCondValue = getOrCreateVReg(*SwInst.getCondition());
374   const BasicBlock *OrigBB = SwInst.getParent();
375 
376   LLT LLTi1 = getLLTForType(*Type::getInt1Ty(U.getContext()), *DL);
377   for (auto &CaseIt : SwInst.cases()) {
378     const unsigned CaseValueReg = getOrCreateVReg(*CaseIt.getCaseValue());
379     const unsigned Tst = MRI->createGenericVirtualRegister(LLTi1);
380     MIRBuilder.buildICmp(CmpInst::ICMP_EQ, Tst, CaseValueReg, SwCondValue);
381     MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
382     const BasicBlock *TrueBB = CaseIt.getCaseSuccessor();
383     MachineBasicBlock &TrueMBB = getMBB(*TrueBB);
384 
385     MIRBuilder.buildBrCond(Tst, TrueMBB);
386     CurMBB.addSuccessor(&TrueMBB);
387     addMachineCFGPred({OrigBB, TrueBB}, &CurMBB);
388 
389     MachineBasicBlock *FalseMBB =
390         MF->CreateMachineBasicBlock(SwInst.getParent());
391     // Insert the comparison blocks one after the other.
392     MF->insert(std::next(CurMBB.getIterator()), FalseMBB);
393     MIRBuilder.buildBr(*FalseMBB);
394     CurMBB.addSuccessor(FalseMBB);
395 
396     MIRBuilder.setMBB(*FalseMBB);
397   }
398   // handle default case
399   const BasicBlock *DefaultBB = SwInst.getDefaultDest();
400   MachineBasicBlock &DefaultMBB = getMBB(*DefaultBB);
401   MIRBuilder.buildBr(DefaultMBB);
402   MachineBasicBlock &CurMBB = MIRBuilder.getMBB();
403   CurMBB.addSuccessor(&DefaultMBB);
404   addMachineCFGPred({OrigBB, DefaultBB}, &CurMBB);
405 
406   return true;
407 }
408 
409 bool IRTranslator::translateIndirectBr(const User &U,
410                                        MachineIRBuilder &MIRBuilder) {
411   const IndirectBrInst &BrInst = cast<IndirectBrInst>(U);
412 
413   const unsigned Tgt = getOrCreateVReg(*BrInst.getAddress());
414   MIRBuilder.buildBrIndirect(Tgt);
415 
416   // Link successors.
417   MachineBasicBlock &CurBB = MIRBuilder.getMBB();
418   for (const BasicBlock *Succ : BrInst.successors())
419     CurBB.addSuccessor(&getMBB(*Succ));
420 
421   return true;
422 }
423 
424 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
425   const LoadInst &LI = cast<LoadInst>(U);
426 
427   auto Flags = LI.isVolatile() ? MachineMemOperand::MOVolatile
428                                : MachineMemOperand::MONone;
429   Flags |= MachineMemOperand::MOLoad;
430 
431   if (DL->getTypeStoreSize(LI.getType()) == 0)
432     return true;
433 
434   ArrayRef<unsigned> Regs = getOrCreateVRegs(LI);
435   ArrayRef<uint64_t> Offsets = *VMap.getOffsets(LI);
436   unsigned Base = getOrCreateVReg(*LI.getPointerOperand());
437 
438   for (unsigned i = 0; i < Regs.size(); ++i) {
439     unsigned Addr = 0;
440     MIRBuilder.materializeGEP(Addr, Base, LLT::scalar(64), Offsets[i] / 8);
441 
442     MachinePointerInfo Ptr(LI.getPointerOperand(), Offsets[i] / 8);
443     unsigned BaseAlign = getMemOpAlignment(LI);
444     auto MMO = MF->getMachineMemOperand(
445         Ptr, Flags, (MRI->getType(Regs[i]).getSizeInBits() + 7) / 8,
446         MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), nullptr,
447         LI.getSyncScopeID(), LI.getOrdering());
448     MIRBuilder.buildLoad(Regs[i], Addr, *MMO);
449   }
450 
451   return true;
452 }
453 
454 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
455   const StoreInst &SI = cast<StoreInst>(U);
456   auto Flags = SI.isVolatile() ? MachineMemOperand::MOVolatile
457                                : MachineMemOperand::MONone;
458   Flags |= MachineMemOperand::MOStore;
459 
460   if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
461     return true;
462 
463   ArrayRef<unsigned> Vals = getOrCreateVRegs(*SI.getValueOperand());
464   ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*SI.getValueOperand());
465   unsigned Base = getOrCreateVReg(*SI.getPointerOperand());
466 
467   for (unsigned i = 0; i < Vals.size(); ++i) {
468     unsigned Addr = 0;
469     MIRBuilder.materializeGEP(Addr, Base, LLT::scalar(64), Offsets[i] / 8);
470 
471     MachinePointerInfo Ptr(SI.getPointerOperand(), Offsets[i] / 8);
472     unsigned BaseAlign = getMemOpAlignment(SI);
473     auto MMO = MF->getMachineMemOperand(
474         Ptr, Flags, (MRI->getType(Vals[i]).getSizeInBits() + 7) / 8,
475         MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), nullptr,
476         SI.getSyncScopeID(), SI.getOrdering());
477     MIRBuilder.buildStore(Vals[i], Addr, *MMO);
478   }
479   return true;
480 }
481 
482 static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL) {
483   const Value *Src = U.getOperand(0);
484   Type *Int32Ty = Type::getInt32Ty(U.getContext());
485 
486   // getIndexedOffsetInType is designed for GEPs, so the first index is the
487   // usual array element rather than looking into the actual aggregate.
488   SmallVector<Value *, 1> Indices;
489   Indices.push_back(ConstantInt::get(Int32Ty, 0));
490 
491   if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&U)) {
492     for (auto Idx : EVI->indices())
493       Indices.push_back(ConstantInt::get(Int32Ty, Idx));
494   } else if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(&U)) {
495     for (auto Idx : IVI->indices())
496       Indices.push_back(ConstantInt::get(Int32Ty, Idx));
497   } else {
498     for (unsigned i = 1; i < U.getNumOperands(); ++i)
499       Indices.push_back(U.getOperand(i));
500   }
501 
502   return 8 * static_cast<uint64_t>(
503                  DL.getIndexedOffsetInType(Src->getType(), Indices));
504 }
505 
506 bool IRTranslator::translateExtractValue(const User &U,
507                                          MachineIRBuilder &MIRBuilder) {
508   const Value *Src = U.getOperand(0);
509   uint64_t Offset = getOffsetFromIndices(U, *DL);
510   ArrayRef<unsigned> SrcRegs = getOrCreateVRegs(*Src);
511   ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*Src);
512   unsigned Idx = std::lower_bound(Offsets.begin(), Offsets.end(), Offset) -
513                  Offsets.begin();
514   auto &DstRegs = allocateVRegs(U);
515 
516   for (unsigned i = 0; i < DstRegs.size(); ++i)
517     DstRegs[i] = SrcRegs[Idx++];
518 
519   return true;
520 }
521 
522 bool IRTranslator::translateInsertValue(const User &U,
523                                         MachineIRBuilder &MIRBuilder) {
524   const Value *Src = U.getOperand(0);
525   uint64_t Offset = getOffsetFromIndices(U, *DL);
526   auto &DstRegs = allocateVRegs(U);
527   ArrayRef<uint64_t> DstOffsets = *VMap.getOffsets(U);
528   ArrayRef<unsigned> SrcRegs = getOrCreateVRegs(*Src);
529   ArrayRef<unsigned> InsertedRegs = getOrCreateVRegs(*U.getOperand(1));
530   auto InsertedIt = InsertedRegs.begin();
531 
532   for (unsigned i = 0; i < DstRegs.size(); ++i) {
533     if (DstOffsets[i] >= Offset && InsertedIt != InsertedRegs.end())
534       DstRegs[i] = *InsertedIt++;
535     else
536       DstRegs[i] = SrcRegs[i];
537   }
538 
539   return true;
540 }
541 
542 bool IRTranslator::translateSelect(const User &U,
543                                    MachineIRBuilder &MIRBuilder) {
544   unsigned Tst = getOrCreateVReg(*U.getOperand(0));
545   ArrayRef<unsigned> ResRegs = getOrCreateVRegs(U);
546   ArrayRef<unsigned> Op0Regs = getOrCreateVRegs(*U.getOperand(1));
547   ArrayRef<unsigned> Op1Regs = getOrCreateVRegs(*U.getOperand(2));
548 
549   for (unsigned i = 0; i < ResRegs.size(); ++i)
550     MIRBuilder.buildSelect(ResRegs[i], Tst, Op0Regs[i], Op1Regs[i]);
551 
552   return true;
553 }
554 
555 bool IRTranslator::translateBitCast(const User &U,
556                                     MachineIRBuilder &MIRBuilder) {
557   // If we're bitcasting to the source type, we can reuse the source vreg.
558   if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
559       getLLTForType(*U.getType(), *DL)) {
560     unsigned SrcReg = getOrCreateVReg(*U.getOperand(0));
561     auto &Regs = *VMap.getVRegs(U);
562     // If we already assigned a vreg for this bitcast, we can't change that.
563     // Emit a copy to satisfy the users we already emitted.
564     if (!Regs.empty())
565       MIRBuilder.buildCopy(Regs[0], SrcReg);
566     else {
567       Regs.push_back(SrcReg);
568       VMap.getOffsets(U)->push_back(0);
569     }
570     return true;
571   }
572   return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
573 }
574 
575 bool IRTranslator::translateCast(unsigned Opcode, const User &U,
576                                  MachineIRBuilder &MIRBuilder) {
577   unsigned Op = getOrCreateVReg(*U.getOperand(0));
578   unsigned Res = getOrCreateVReg(U);
579   MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op);
580   return true;
581 }
582 
583 bool IRTranslator::translateGetElementPtr(const User &U,
584                                           MachineIRBuilder &MIRBuilder) {
585   // FIXME: support vector GEPs.
586   if (U.getType()->isVectorTy())
587     return false;
588 
589   Value &Op0 = *U.getOperand(0);
590   unsigned BaseReg = getOrCreateVReg(Op0);
591   Type *PtrIRTy = Op0.getType();
592   LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
593   Type *OffsetIRTy = DL->getIntPtrType(PtrIRTy);
594   LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
595 
596   int64_t Offset = 0;
597   for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
598        GTI != E; ++GTI) {
599     const Value *Idx = GTI.getOperand();
600     if (StructType *StTy = GTI.getStructTypeOrNull()) {
601       unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
602       Offset += DL->getStructLayout(StTy)->getElementOffset(Field);
603       continue;
604     } else {
605       uint64_t ElementSize = DL->getTypeAllocSize(GTI.getIndexedType());
606 
607       // If this is a scalar constant or a splat vector of constants,
608       // handle it quickly.
609       if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
610         Offset += ElementSize * CI->getSExtValue();
611         continue;
612       }
613 
614       if (Offset != 0) {
615         unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
616         unsigned OffsetReg =
617             getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
618         MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
619 
620         BaseReg = NewBaseReg;
621         Offset = 0;
622       }
623 
624       unsigned IdxReg = getOrCreateVReg(*Idx);
625       if (MRI->getType(IdxReg) != OffsetTy) {
626         unsigned NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
627         MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
628         IdxReg = NewIdxReg;
629       }
630 
631       // N = N + Idx * ElementSize;
632       // Avoid doing it for ElementSize of 1.
633       unsigned GepOffsetReg;
634       if (ElementSize != 1) {
635         unsigned ElementSizeReg =
636             getOrCreateVReg(*ConstantInt::get(OffsetIRTy, ElementSize));
637 
638         GepOffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
639         MIRBuilder.buildMul(GepOffsetReg, ElementSizeReg, IdxReg);
640       } else
641         GepOffsetReg = IdxReg;
642 
643       unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
644       MIRBuilder.buildGEP(NewBaseReg, BaseReg, GepOffsetReg);
645       BaseReg = NewBaseReg;
646     }
647   }
648 
649   if (Offset != 0) {
650     unsigned OffsetReg = getOrCreateVReg(*ConstantInt::get(OffsetIRTy, Offset));
651     MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetReg);
652     return true;
653   }
654 
655   MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
656   return true;
657 }
658 
659 bool IRTranslator::translateMemfunc(const CallInst &CI,
660                                     MachineIRBuilder &MIRBuilder,
661                                     unsigned ID) {
662   LLT SizeTy = getLLTForType(*CI.getArgOperand(2)->getType(), *DL);
663   Type *DstTy = CI.getArgOperand(0)->getType();
664   if (cast<PointerType>(DstTy)->getAddressSpace() != 0 ||
665       SizeTy.getSizeInBits() != DL->getPointerSizeInBits(0))
666     return false;
667 
668   SmallVector<CallLowering::ArgInfo, 8> Args;
669   for (int i = 0; i < 3; ++i) {
670     const auto &Arg = CI.getArgOperand(i);
671     Args.emplace_back(getOrCreateVReg(*Arg), Arg->getType());
672   }
673 
674   const char *Callee;
675   switch (ID) {
676   case Intrinsic::memmove:
677   case Intrinsic::memcpy: {
678     Type *SrcTy = CI.getArgOperand(1)->getType();
679     if(cast<PointerType>(SrcTy)->getAddressSpace() != 0)
680       return false;
681     Callee = ID == Intrinsic::memcpy ? "memcpy" : "memmove";
682     break;
683   }
684   case Intrinsic::memset:
685     Callee = "memset";
686     break;
687   default:
688     return false;
689   }
690 
691   return CLI->lowerCall(MIRBuilder, CI.getCallingConv(),
692                         MachineOperand::CreateES(Callee),
693                         CallLowering::ArgInfo(0, CI.getType()), Args);
694 }
695 
696 void IRTranslator::getStackGuard(unsigned DstReg,
697                                  MachineIRBuilder &MIRBuilder) {
698   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
699   MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
700   auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
701   MIB.addDef(DstReg);
702 
703   auto &TLI = *MF->getSubtarget().getTargetLowering();
704   Value *Global = TLI.getSDagStackGuard(*MF->getFunction().getParent());
705   if (!Global)
706     return;
707 
708   MachinePointerInfo MPInfo(Global);
709   MachineInstr::mmo_iterator MemRefs = MF->allocateMemRefsArray(1);
710   auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
711                MachineMemOperand::MODereferenceable;
712   *MemRefs =
713       MF->getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8,
714                                DL->getPointerABIAlignment(0));
715   MIB.setMemRefs(MemRefs, MemRefs + 1);
716 }
717 
718 bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
719                                               MachineIRBuilder &MIRBuilder) {
720   ArrayRef<unsigned> ResRegs = getOrCreateVRegs(CI);
721   auto MIB = MIRBuilder.buildInstr(Op)
722                  .addDef(ResRegs[0])
723                  .addDef(ResRegs[1])
724                  .addUse(getOrCreateVReg(*CI.getOperand(0)))
725                  .addUse(getOrCreateVReg(*CI.getOperand(1)));
726 
727   if (Op == TargetOpcode::G_UADDE || Op == TargetOpcode::G_USUBE) {
728     unsigned Zero = getOrCreateVReg(
729         *Constant::getNullValue(Type::getInt1Ty(CI.getContext())));
730     MIB.addUse(Zero);
731   }
732 
733   return true;
734 }
735 
736 bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
737                                            MachineIRBuilder &MIRBuilder) {
738   switch (ID) {
739   default:
740     break;
741   case Intrinsic::lifetime_start:
742   case Intrinsic::lifetime_end:
743     // Stack coloring is not enabled in O0 (which we care about now) so we can
744     // drop these. Make sure someone notices when we start compiling at higher
745     // opts though.
746     if (MF->getTarget().getOptLevel() != CodeGenOpt::None)
747       return false;
748     return true;
749   case Intrinsic::dbg_declare: {
750     const DbgDeclareInst &DI = cast<DbgDeclareInst>(CI);
751     assert(DI.getVariable() && "Missing variable");
752 
753     const Value *Address = DI.getAddress();
754     if (!Address || isa<UndefValue>(Address)) {
755       LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
756       return true;
757     }
758 
759     assert(DI.getVariable()->isValidLocationForIntrinsic(
760                MIRBuilder.getDebugLoc()) &&
761            "Expected inlined-at fields to agree");
762     auto AI = dyn_cast<AllocaInst>(Address);
763     if (AI && AI->isStaticAlloca()) {
764       // Static allocas are tracked at the MF level, no need for DBG_VALUE
765       // instructions (in fact, they get ignored if they *do* exist).
766       MF->setVariableDbgInfo(DI.getVariable(), DI.getExpression(),
767                              getOrCreateFrameIndex(*AI), DI.getDebugLoc());
768     } else
769       MIRBuilder.buildDirectDbgValue(getOrCreateVReg(*Address),
770                                      DI.getVariable(), DI.getExpression());
771     return true;
772   }
773   case Intrinsic::vaend:
774     // No target I know of cares about va_end. Certainly no in-tree target
775     // does. Simplest intrinsic ever!
776     return true;
777   case Intrinsic::vastart: {
778     auto &TLI = *MF->getSubtarget().getTargetLowering();
779     Value *Ptr = CI.getArgOperand(0);
780     unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8;
781 
782     MIRBuilder.buildInstr(TargetOpcode::G_VASTART)
783         .addUse(getOrCreateVReg(*Ptr))
784         .addMemOperand(MF->getMachineMemOperand(
785             MachinePointerInfo(Ptr), MachineMemOperand::MOStore, ListSize, 0));
786     return true;
787   }
788   case Intrinsic::dbg_value: {
789     // This form of DBG_VALUE is target-independent.
790     const DbgValueInst &DI = cast<DbgValueInst>(CI);
791     const Value *V = DI.getValue();
792     assert(DI.getVariable()->isValidLocationForIntrinsic(
793                MIRBuilder.getDebugLoc()) &&
794            "Expected inlined-at fields to agree");
795     if (!V) {
796       // Currently the optimizer can produce this; insert an undef to
797       // help debugging.  Probably the optimizer should not do this.
798       MIRBuilder.buildIndirectDbgValue(0, DI.getVariable(), DI.getExpression());
799     } else if (const auto *CI = dyn_cast<Constant>(V)) {
800       MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression());
801     } else {
802       unsigned Reg = getOrCreateVReg(*V);
803       // FIXME: This does not handle register-indirect values at offset 0. The
804       // direct/indirect thing shouldn't really be handled by something as
805       // implicit as reg+noreg vs reg+imm in the first palce, but it seems
806       // pretty baked in right now.
807       MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression());
808     }
809     return true;
810   }
811   case Intrinsic::uadd_with_overflow:
812     return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDE, MIRBuilder);
813   case Intrinsic::sadd_with_overflow:
814     return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
815   case Intrinsic::usub_with_overflow:
816     return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBE, MIRBuilder);
817   case Intrinsic::ssub_with_overflow:
818     return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
819   case Intrinsic::umul_with_overflow:
820     return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
821   case Intrinsic::smul_with_overflow:
822     return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
823   case Intrinsic::pow:
824     MIRBuilder.buildInstr(TargetOpcode::G_FPOW)
825         .addDef(getOrCreateVReg(CI))
826         .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
827         .addUse(getOrCreateVReg(*CI.getArgOperand(1)));
828     return true;
829   case Intrinsic::exp:
830     MIRBuilder.buildInstr(TargetOpcode::G_FEXP)
831         .addDef(getOrCreateVReg(CI))
832         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
833     return true;
834   case Intrinsic::exp2:
835     MIRBuilder.buildInstr(TargetOpcode::G_FEXP2)
836         .addDef(getOrCreateVReg(CI))
837         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
838     return true;
839   case Intrinsic::log:
840     MIRBuilder.buildInstr(TargetOpcode::G_FLOG)
841         .addDef(getOrCreateVReg(CI))
842         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
843     return true;
844   case Intrinsic::log2:
845     MIRBuilder.buildInstr(TargetOpcode::G_FLOG2)
846         .addDef(getOrCreateVReg(CI))
847         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
848     return true;
849   case Intrinsic::fabs:
850     MIRBuilder.buildInstr(TargetOpcode::G_FABS)
851         .addDef(getOrCreateVReg(CI))
852         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
853     return true;
854   case Intrinsic::fma:
855     MIRBuilder.buildInstr(TargetOpcode::G_FMA)
856         .addDef(getOrCreateVReg(CI))
857         .addUse(getOrCreateVReg(*CI.getArgOperand(0)))
858         .addUse(getOrCreateVReg(*CI.getArgOperand(1)))
859         .addUse(getOrCreateVReg(*CI.getArgOperand(2)));
860     return true;
861   case Intrinsic::fmuladd: {
862     const TargetMachine &TM = MF->getTarget();
863     const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
864     unsigned Dst = getOrCreateVReg(CI);
865     unsigned Op0 = getOrCreateVReg(*CI.getArgOperand(0));
866     unsigned Op1 = getOrCreateVReg(*CI.getArgOperand(1));
867     unsigned Op2 = getOrCreateVReg(*CI.getArgOperand(2));
868     if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
869         TLI.isFMAFasterThanFMulAndFAdd(TLI.getValueType(*DL, CI.getType()))) {
870       // TODO: Revisit this to see if we should move this part of the
871       // lowering to the combiner.
872       MIRBuilder.buildInstr(TargetOpcode::G_FMA, Dst, Op0, Op1, Op2);
873     } else {
874       LLT Ty = getLLTForType(*CI.getType(), *DL);
875       auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, Ty, Op0, Op1);
876       MIRBuilder.buildInstr(TargetOpcode::G_FADD, Dst, FMul, Op2);
877     }
878     return true;
879   }
880   case Intrinsic::memcpy:
881   case Intrinsic::memmove:
882   case Intrinsic::memset:
883     return translateMemfunc(CI, MIRBuilder, ID);
884   case Intrinsic::eh_typeid_for: {
885     GlobalValue *GV = ExtractTypeInfo(CI.getArgOperand(0));
886     unsigned Reg = getOrCreateVReg(CI);
887     unsigned TypeID = MF->getTypeIDFor(GV);
888     MIRBuilder.buildConstant(Reg, TypeID);
889     return true;
890   }
891   case Intrinsic::objectsize: {
892     // If we don't know by now, we're never going to know.
893     const ConstantInt *Min = cast<ConstantInt>(CI.getArgOperand(1));
894 
895     MIRBuilder.buildConstant(getOrCreateVReg(CI), Min->isZero() ? -1ULL : 0);
896     return true;
897   }
898   case Intrinsic::stackguard:
899     getStackGuard(getOrCreateVReg(CI), MIRBuilder);
900     return true;
901   case Intrinsic::stackprotector: {
902     LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
903     unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
904     getStackGuard(GuardVal, MIRBuilder);
905 
906     AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
907     MIRBuilder.buildStore(
908         GuardVal, getOrCreateVReg(*Slot),
909         *MF->getMachineMemOperand(
910             MachinePointerInfo::getFixedStack(*MF,
911                                               getOrCreateFrameIndex(*Slot)),
912             MachineMemOperand::MOStore | MachineMemOperand::MOVolatile,
913             PtrTy.getSizeInBits() / 8, 8));
914     return true;
915   }
916   case Intrinsic::cttz:
917   case Intrinsic::ctlz: {
918     ConstantInt *Cst = cast<ConstantInt>(CI.getArgOperand(1));
919     bool isTrailing = ID == Intrinsic::cttz;
920     unsigned Opcode = isTrailing
921                           ? Cst->isZero() ? TargetOpcode::G_CTTZ
922                                           : TargetOpcode::G_CTTZ_ZERO_UNDEF
923                           : Cst->isZero() ? TargetOpcode::G_CTLZ
924                                           : TargetOpcode::G_CTLZ_ZERO_UNDEF;
925     MIRBuilder.buildInstr(Opcode)
926         .addDef(getOrCreateVReg(CI))
927         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
928     return true;
929   }
930   case Intrinsic::ctpop: {
931     MIRBuilder.buildInstr(TargetOpcode::G_CTPOP)
932         .addDef(getOrCreateVReg(CI))
933         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
934     return true;
935   }
936   }
937   return false;
938 }
939 
940 bool IRTranslator::translateInlineAsm(const CallInst &CI,
941                                       MachineIRBuilder &MIRBuilder) {
942   const InlineAsm &IA = cast<InlineAsm>(*CI.getCalledValue());
943   if (!IA.getConstraintString().empty())
944     return false;
945 
946   unsigned ExtraInfo = 0;
947   if (IA.hasSideEffects())
948     ExtraInfo |= InlineAsm::Extra_HasSideEffects;
949   if (IA.getDialect() == InlineAsm::AD_Intel)
950     ExtraInfo |= InlineAsm::Extra_AsmDialect;
951 
952   MIRBuilder.buildInstr(TargetOpcode::INLINEASM)
953     .addExternalSymbol(IA.getAsmString().c_str())
954     .addImm(ExtraInfo);
955 
956   return true;
957 }
958 
959 unsigned IRTranslator::packRegs(const Value &V,
960                                   MachineIRBuilder &MIRBuilder) {
961   ArrayRef<unsigned> Regs = getOrCreateVRegs(V);
962   ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);
963   LLT BigTy = getLLTForType(*V.getType(), *DL);
964 
965   if (Regs.size() == 1)
966     return Regs[0];
967 
968   unsigned Dst = MRI->createGenericVirtualRegister(BigTy);
969   MIRBuilder.buildUndef(Dst);
970   for (unsigned i = 0; i < Regs.size(); ++i) {
971     unsigned NewDst = MRI->createGenericVirtualRegister(BigTy);
972     MIRBuilder.buildInsert(NewDst, Dst, Regs[i], Offsets[i]);
973     Dst = NewDst;
974   }
975   return Dst;
976 }
977 
978 void IRTranslator::unpackRegs(const Value &V, unsigned Src,
979                                 MachineIRBuilder &MIRBuilder) {
980   ArrayRef<unsigned> Regs = getOrCreateVRegs(V);
981   ArrayRef<uint64_t> Offsets = *VMap.getOffsets(V);
982 
983   for (unsigned i = 0; i < Regs.size(); ++i)
984     MIRBuilder.buildExtract(Regs[i], Src, Offsets[i]);
985 }
986 
987 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
988   const CallInst &CI = cast<CallInst>(U);
989   auto TII = MF->getTarget().getIntrinsicInfo();
990   const Function *F = CI.getCalledFunction();
991 
992   // FIXME: support Windows dllimport function calls.
993   if (F && F->hasDLLImportStorageClass())
994     return false;
995 
996   if (CI.isInlineAsm())
997     return translateInlineAsm(CI, MIRBuilder);
998 
999   Intrinsic::ID ID = Intrinsic::not_intrinsic;
1000   if (F && F->isIntrinsic()) {
1001     ID = F->getIntrinsicID();
1002     if (TII && ID == Intrinsic::not_intrinsic)
1003       ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
1004   }
1005 
1006   bool IsSplitType = valueIsSplit(CI);
1007   if (!F || !F->isIntrinsic() || ID == Intrinsic::not_intrinsic) {
1008     unsigned Res = IsSplitType ? MRI->createGenericVirtualRegister(
1009                                      getLLTForType(*CI.getType(), *DL))
1010                                : getOrCreateVReg(CI);
1011 
1012     SmallVector<unsigned, 8> Args;
1013     for (auto &Arg: CI.arg_operands())
1014       Args.push_back(packRegs(*Arg, MIRBuilder));
1015 
1016     MF->getFrameInfo().setHasCalls(true);
1017     bool Success = CLI->lowerCall(MIRBuilder, &CI, Res, Args, [&]() {
1018       return getOrCreateVReg(*CI.getCalledValue());
1019     });
1020 
1021     if (IsSplitType)
1022       unpackRegs(CI, Res, MIRBuilder);
1023     return Success;
1024   }
1025 
1026   assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
1027 
1028   if (translateKnownIntrinsic(CI, ID, MIRBuilder))
1029     return true;
1030 
1031   unsigned Res = 0;
1032   if (!CI.getType()->isVoidTy()) {
1033     if (IsSplitType)
1034       Res =
1035           MRI->createGenericVirtualRegister(getLLTForType(*CI.getType(), *DL));
1036     else
1037       Res = getOrCreateVReg(CI);
1038   }
1039   MachineInstrBuilder MIB =
1040       MIRBuilder.buildIntrinsic(ID, Res, !CI.doesNotAccessMemory());
1041 
1042   for (auto &Arg : CI.arg_operands()) {
1043     // Some intrinsics take metadata parameters. Reject them.
1044     if (isa<MetadataAsValue>(Arg))
1045       return false;
1046     MIB.addUse(packRegs(*Arg, MIRBuilder));
1047   }
1048 
1049   if (IsSplitType)
1050     unpackRegs(CI, Res, MIRBuilder);
1051 
1052   // Add a MachineMemOperand if it is a target mem intrinsic.
1053   const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
1054   TargetLowering::IntrinsicInfo Info;
1055   // TODO: Add a GlobalISel version of getTgtMemIntrinsic.
1056   if (TLI.getTgtMemIntrinsic(Info, CI, *MF, ID)) {
1057     uint64_t Size = Info.memVT.getStoreSize();
1058     MIB.addMemOperand(MF->getMachineMemOperand(MachinePointerInfo(Info.ptrVal),
1059                                                Info.flags, Size, Info.align));
1060   }
1061 
1062   return true;
1063 }
1064 
1065 bool IRTranslator::translateInvoke(const User &U,
1066                                    MachineIRBuilder &MIRBuilder) {
1067   const InvokeInst &I = cast<InvokeInst>(U);
1068   MCContext &Context = MF->getContext();
1069 
1070   const BasicBlock *ReturnBB = I.getSuccessor(0);
1071   const BasicBlock *EHPadBB = I.getSuccessor(1);
1072 
1073   const Value *Callee = I.getCalledValue();
1074   const Function *Fn = dyn_cast<Function>(Callee);
1075   if (isa<InlineAsm>(Callee))
1076     return false;
1077 
1078   // FIXME: support invoking patchpoint and statepoint intrinsics.
1079   if (Fn && Fn->isIntrinsic())
1080     return false;
1081 
1082   // FIXME: support whatever these are.
1083   if (I.countOperandBundlesOfType(LLVMContext::OB_deopt))
1084     return false;
1085 
1086   // FIXME: support Windows exception handling.
1087   if (!isa<LandingPadInst>(EHPadBB->front()))
1088     return false;
1089 
1090   // Emit the actual call, bracketed by EH_LABELs so that the MF knows about
1091   // the region covered by the try.
1092   MCSymbol *BeginSymbol = Context.createTempSymbol();
1093   MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
1094 
1095   unsigned Res =
1096         MRI->createGenericVirtualRegister(getLLTForType(*I.getType(), *DL));
1097   SmallVector<unsigned, 8> Args;
1098   for (auto &Arg: I.arg_operands())
1099     Args.push_back(packRegs(*Arg, MIRBuilder));
1100 
1101   if (!CLI->lowerCall(MIRBuilder, &I, Res, Args,
1102                       [&]() { return getOrCreateVReg(*I.getCalledValue()); }))
1103     return false;
1104 
1105   unpackRegs(I, Res, MIRBuilder);
1106 
1107   MCSymbol *EndSymbol = Context.createTempSymbol();
1108   MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
1109 
1110   // FIXME: track probabilities.
1111   MachineBasicBlock &EHPadMBB = getMBB(*EHPadBB),
1112                     &ReturnMBB = getMBB(*ReturnBB);
1113   MF->addInvoke(&EHPadMBB, BeginSymbol, EndSymbol);
1114   MIRBuilder.getMBB().addSuccessor(&ReturnMBB);
1115   MIRBuilder.getMBB().addSuccessor(&EHPadMBB);
1116   MIRBuilder.buildBr(ReturnMBB);
1117 
1118   return true;
1119 }
1120 
1121 bool IRTranslator::translateLandingPad(const User &U,
1122                                        MachineIRBuilder &MIRBuilder) {
1123   const LandingPadInst &LP = cast<LandingPadInst>(U);
1124 
1125   MachineBasicBlock &MBB = MIRBuilder.getMBB();
1126   addLandingPadInfo(LP, MBB);
1127 
1128   MBB.setIsEHPad();
1129 
1130   // If there aren't registers to copy the values into (e.g., during SjLj
1131   // exceptions), then don't bother.
1132   auto &TLI = *MF->getSubtarget().getTargetLowering();
1133   const Constant *PersonalityFn = MF->getFunction().getPersonalityFn();
1134   if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
1135       TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
1136     return true;
1137 
1138   // If landingpad's return type is token type, we don't create DAG nodes
1139   // for its exception pointer and selector value. The extraction of exception
1140   // pointer or selector value from token type landingpads is not currently
1141   // supported.
1142   if (LP.getType()->isTokenTy())
1143     return true;
1144 
1145   // Add a label to mark the beginning of the landing pad.  Deletion of the
1146   // landing pad can thus be detected via the MachineModuleInfo.
1147   MIRBuilder.buildInstr(TargetOpcode::EH_LABEL)
1148     .addSym(MF->addLandingPad(&MBB));
1149 
1150   LLT Ty = getLLTForType(*LP.getType(), *DL);
1151   unsigned Undef = MRI->createGenericVirtualRegister(Ty);
1152   MIRBuilder.buildUndef(Undef);
1153 
1154   SmallVector<LLT, 2> Tys;
1155   for (Type *Ty : cast<StructType>(LP.getType())->elements())
1156     Tys.push_back(getLLTForType(*Ty, *DL));
1157   assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
1158 
1159   // Mark exception register as live in.
1160   unsigned ExceptionReg = TLI.getExceptionPointerRegister(PersonalityFn);
1161   if (!ExceptionReg)
1162     return false;
1163 
1164   MBB.addLiveIn(ExceptionReg);
1165   ArrayRef<unsigned> ResRegs = getOrCreateVRegs(LP);
1166   MIRBuilder.buildCopy(ResRegs[0], ExceptionReg);
1167 
1168   unsigned SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
1169   if (!SelectorReg)
1170     return false;
1171 
1172   MBB.addLiveIn(SelectorReg);
1173   unsigned PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
1174   MIRBuilder.buildCopy(PtrVReg, SelectorReg);
1175   MIRBuilder.buildCast(ResRegs[1], PtrVReg);
1176 
1177   return true;
1178 }
1179 
1180 bool IRTranslator::translateAlloca(const User &U,
1181                                    MachineIRBuilder &MIRBuilder) {
1182   auto &AI = cast<AllocaInst>(U);
1183 
1184   if (AI.isSwiftError())
1185     return false;
1186 
1187   if (AI.isStaticAlloca()) {
1188     unsigned Res = getOrCreateVReg(AI);
1189     int FI = getOrCreateFrameIndex(AI);
1190     MIRBuilder.buildFrameIndex(Res, FI);
1191     return true;
1192   }
1193 
1194   // FIXME: support stack probing for Windows.
1195   if (MF->getTarget().getTargetTriple().isOSWindows())
1196     return false;
1197 
1198   // Now we're in the harder dynamic case.
1199   Type *Ty = AI.getAllocatedType();
1200   unsigned Align =
1201       std::max((unsigned)DL->getPrefTypeAlignment(Ty), AI.getAlignment());
1202 
1203   unsigned NumElts = getOrCreateVReg(*AI.getArraySize());
1204 
1205   Type *IntPtrIRTy = DL->getIntPtrType(AI.getType());
1206   LLT IntPtrTy = getLLTForType(*IntPtrIRTy, *DL);
1207   if (MRI->getType(NumElts) != IntPtrTy) {
1208     unsigned ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
1209     MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
1210     NumElts = ExtElts;
1211   }
1212 
1213   unsigned AllocSize = MRI->createGenericVirtualRegister(IntPtrTy);
1214   unsigned TySize =
1215       getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, -DL->getTypeAllocSize(Ty)));
1216   MIRBuilder.buildMul(AllocSize, NumElts, TySize);
1217 
1218   LLT PtrTy = getLLTForType(*AI.getType(), *DL);
1219   auto &TLI = *MF->getSubtarget().getTargetLowering();
1220   unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore();
1221 
1222   unsigned SPTmp = MRI->createGenericVirtualRegister(PtrTy);
1223   MIRBuilder.buildCopy(SPTmp, SPReg);
1224 
1225   unsigned AllocTmp = MRI->createGenericVirtualRegister(PtrTy);
1226   MIRBuilder.buildGEP(AllocTmp, SPTmp, AllocSize);
1227 
1228   // Handle alignment. We have to realign if the allocation granule was smaller
1229   // than stack alignment, or the specific alloca requires more than stack
1230   // alignment.
1231   unsigned StackAlign =
1232       MF->getSubtarget().getFrameLowering()->getStackAlignment();
1233   Align = std::max(Align, StackAlign);
1234   if (Align > StackAlign || DL->getTypeAllocSize(Ty) % StackAlign != 0) {
1235     // Round the size of the allocation up to the stack alignment size
1236     // by add SA-1 to the size. This doesn't overflow because we're computing
1237     // an address inside an alloca.
1238     unsigned AlignedAlloc = MRI->createGenericVirtualRegister(PtrTy);
1239     MIRBuilder.buildPtrMask(AlignedAlloc, AllocTmp, Log2_32(Align));
1240     AllocTmp = AlignedAlloc;
1241   }
1242 
1243   MIRBuilder.buildCopy(SPReg, AllocTmp);
1244   MIRBuilder.buildCopy(getOrCreateVReg(AI), AllocTmp);
1245 
1246   MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, &AI);
1247   assert(MF->getFrameInfo().hasVarSizedObjects());
1248   return true;
1249 }
1250 
1251 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
1252   // FIXME: We may need more info about the type. Because of how LLT works,
1253   // we're completely discarding the i64/double distinction here (amongst
1254   // others). Fortunately the ABIs I know of where that matters don't use va_arg
1255   // anyway but that's not guaranteed.
1256   MIRBuilder.buildInstr(TargetOpcode::G_VAARG)
1257     .addDef(getOrCreateVReg(U))
1258     .addUse(getOrCreateVReg(*U.getOperand(0)))
1259     .addImm(DL->getABITypeAlignment(U.getType()));
1260   return true;
1261 }
1262 
1263 bool IRTranslator::translateInsertElement(const User &U,
1264                                           MachineIRBuilder &MIRBuilder) {
1265   // If it is a <1 x Ty> vector, use the scalar as it is
1266   // not a legal vector type in LLT.
1267   if (U.getType()->getVectorNumElements() == 1) {
1268     unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1269     auto &Regs = *VMap.getVRegs(U);
1270     if (Regs.empty()) {
1271       Regs.push_back(Elt);
1272       VMap.getOffsets(U)->push_back(0);
1273     } else {
1274       MIRBuilder.buildCopy(Regs[0], Elt);
1275     }
1276     return true;
1277   }
1278 
1279   unsigned Res = getOrCreateVReg(U);
1280   unsigned Val = getOrCreateVReg(*U.getOperand(0));
1281   unsigned Elt = getOrCreateVReg(*U.getOperand(1));
1282   unsigned Idx = getOrCreateVReg(*U.getOperand(2));
1283   MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
1284   return true;
1285 }
1286 
1287 bool IRTranslator::translateExtractElement(const User &U,
1288                                            MachineIRBuilder &MIRBuilder) {
1289   // If it is a <1 x Ty> vector, use the scalar as it is
1290   // not a legal vector type in LLT.
1291   if (U.getOperand(0)->getType()->getVectorNumElements() == 1) {
1292     unsigned Elt = getOrCreateVReg(*U.getOperand(0));
1293     auto &Regs = *VMap.getVRegs(U);
1294     if (Regs.empty()) {
1295       Regs.push_back(Elt);
1296       VMap.getOffsets(U)->push_back(0);
1297     } else {
1298       MIRBuilder.buildCopy(Regs[0], Elt);
1299     }
1300     return true;
1301   }
1302   unsigned Res = getOrCreateVReg(U);
1303   unsigned Val = getOrCreateVReg(*U.getOperand(0));
1304   unsigned Idx = getOrCreateVReg(*U.getOperand(1));
1305   MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
1306   return true;
1307 }
1308 
1309 bool IRTranslator::translateShuffleVector(const User &U,
1310                                           MachineIRBuilder &MIRBuilder) {
1311   MIRBuilder.buildInstr(TargetOpcode::G_SHUFFLE_VECTOR)
1312       .addDef(getOrCreateVReg(U))
1313       .addUse(getOrCreateVReg(*U.getOperand(0)))
1314       .addUse(getOrCreateVReg(*U.getOperand(1)))
1315       .addUse(getOrCreateVReg(*U.getOperand(2)));
1316   return true;
1317 }
1318 
1319 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
1320   const PHINode &PI = cast<PHINode>(U);
1321 
1322   SmallVector<MachineInstr *, 4> Insts;
1323   for (auto Reg : getOrCreateVRegs(PI)) {
1324     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, Reg);
1325     Insts.push_back(MIB.getInstr());
1326   }
1327 
1328   PendingPHIs.emplace_back(&PI, std::move(Insts));
1329   return true;
1330 }
1331 
1332 bool IRTranslator::translateAtomicCmpXchg(const User &U,
1333                                           MachineIRBuilder &MIRBuilder) {
1334   const AtomicCmpXchgInst &I = cast<AtomicCmpXchgInst>(U);
1335 
1336   if (I.isWeak())
1337     return false;
1338 
1339   auto Flags = I.isVolatile() ? MachineMemOperand::MOVolatile
1340                               : MachineMemOperand::MONone;
1341   Flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1342 
1343   Type *ResType = I.getType();
1344   Type *ValType = ResType->Type::getStructElementType(0);
1345 
1346   auto Res = getOrCreateVRegs(I);
1347   unsigned OldValRes = Res[0];
1348   unsigned SuccessRes = Res[1];
1349   unsigned Addr = getOrCreateVReg(*I.getPointerOperand());
1350   unsigned Cmp = getOrCreateVReg(*I.getCompareOperand());
1351   unsigned NewVal = getOrCreateVReg(*I.getNewValOperand());
1352 
1353   MIRBuilder.buildAtomicCmpXchgWithSuccess(
1354       OldValRes, SuccessRes, Addr, Cmp, NewVal,
1355       *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
1356                                 Flags, DL->getTypeStoreSize(ValType),
1357                                 getMemOpAlignment(I), AAMDNodes(), nullptr,
1358                                 I.getSyncScopeID(), I.getSuccessOrdering(),
1359                                 I.getFailureOrdering()));
1360   return true;
1361 }
1362 
1363 bool IRTranslator::translateAtomicRMW(const User &U,
1364                                       MachineIRBuilder &MIRBuilder) {
1365   const AtomicRMWInst &I = cast<AtomicRMWInst>(U);
1366 
1367   auto Flags = I.isVolatile() ? MachineMemOperand::MOVolatile
1368                               : MachineMemOperand::MONone;
1369   Flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1370 
1371   Type *ResType = I.getType();
1372 
1373   unsigned Res = getOrCreateVReg(I);
1374   unsigned Addr = getOrCreateVReg(*I.getPointerOperand());
1375   unsigned Val = getOrCreateVReg(*I.getValOperand());
1376 
1377   unsigned Opcode = 0;
1378   switch (I.getOperation()) {
1379   default:
1380     llvm_unreachable("Unknown atomicrmw op");
1381     return false;
1382   case AtomicRMWInst::Xchg:
1383     Opcode = TargetOpcode::G_ATOMICRMW_XCHG;
1384     break;
1385   case AtomicRMWInst::Add:
1386     Opcode = TargetOpcode::G_ATOMICRMW_ADD;
1387     break;
1388   case AtomicRMWInst::Sub:
1389     Opcode = TargetOpcode::G_ATOMICRMW_SUB;
1390     break;
1391   case AtomicRMWInst::And:
1392     Opcode = TargetOpcode::G_ATOMICRMW_AND;
1393     break;
1394   case AtomicRMWInst::Nand:
1395     Opcode = TargetOpcode::G_ATOMICRMW_NAND;
1396     break;
1397   case AtomicRMWInst::Or:
1398     Opcode = TargetOpcode::G_ATOMICRMW_OR;
1399     break;
1400   case AtomicRMWInst::Xor:
1401     Opcode = TargetOpcode::G_ATOMICRMW_XOR;
1402     break;
1403   case AtomicRMWInst::Max:
1404     Opcode = TargetOpcode::G_ATOMICRMW_MAX;
1405     break;
1406   case AtomicRMWInst::Min:
1407     Opcode = TargetOpcode::G_ATOMICRMW_MIN;
1408     break;
1409   case AtomicRMWInst::UMax:
1410     Opcode = TargetOpcode::G_ATOMICRMW_UMAX;
1411     break;
1412   case AtomicRMWInst::UMin:
1413     Opcode = TargetOpcode::G_ATOMICRMW_UMIN;
1414     break;
1415   }
1416 
1417   MIRBuilder.buildAtomicRMW(
1418       Opcode, Res, Addr, Val,
1419       *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
1420                                 Flags, DL->getTypeStoreSize(ResType),
1421                                 getMemOpAlignment(I), AAMDNodes(), nullptr,
1422                                 I.getSyncScopeID(), I.getOrdering()));
1423   return true;
1424 }
1425 
1426 void IRTranslator::finishPendingPhis() {
1427   for (auto &Phi : PendingPHIs) {
1428     const PHINode *PI = Phi.first;
1429     ArrayRef<MachineInstr *> ComponentPHIs = Phi.second;
1430 
1431     // All MachineBasicBlocks exist, add them to the PHI. We assume IRTranslator
1432     // won't create extra control flow here, otherwise we need to find the
1433     // dominating predecessor here (or perhaps force the weirder IRTranslators
1434     // to provide a simple boundary).
1435     SmallSet<const BasicBlock *, 4> HandledPreds;
1436 
1437     for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
1438       auto IRPred = PI->getIncomingBlock(i);
1439       if (HandledPreds.count(IRPred))
1440         continue;
1441 
1442       HandledPreds.insert(IRPred);
1443       ArrayRef<unsigned> ValRegs = getOrCreateVRegs(*PI->getIncomingValue(i));
1444       for (auto Pred : getMachinePredBBs({IRPred, PI->getParent()})) {
1445         assert(Pred->isSuccessor(ComponentPHIs[0]->getParent()) &&
1446                "incorrect CFG at MachineBasicBlock level");
1447         for (unsigned j = 0; j < ValRegs.size(); ++j) {
1448           MachineInstrBuilder MIB(*MF, ComponentPHIs[j]);
1449           MIB.addUse(ValRegs[j]);
1450           MIB.addMBB(Pred);
1451         }
1452       }
1453     }
1454   }
1455 }
1456 
1457 bool IRTranslator::valueIsSplit(const Value &V,
1458                                 SmallVectorImpl<uint64_t> *Offsets) {
1459   SmallVector<LLT, 4> SplitTys;
1460   computeValueLLTs(*DL, *V.getType(), SplitTys, Offsets);
1461   return SplitTys.size() > 1;
1462 }
1463 
1464 bool IRTranslator::translate(const Instruction &Inst) {
1465   CurBuilder.setDebugLoc(Inst.getDebugLoc());
1466   switch(Inst.getOpcode()) {
1467 #define HANDLE_INST(NUM, OPCODE, CLASS) \
1468     case Instruction::OPCODE: return translate##OPCODE(Inst, CurBuilder);
1469 #include "llvm/IR/Instruction.def"
1470   default:
1471     return false;
1472   }
1473 }
1474 
1475 bool IRTranslator::translate(const Constant &C, unsigned Reg) {
1476   if (auto CI = dyn_cast<ConstantInt>(&C))
1477     EntryBuilder.buildConstant(Reg, *CI);
1478   else if (auto CF = dyn_cast<ConstantFP>(&C))
1479     EntryBuilder.buildFConstant(Reg, *CF);
1480   else if (isa<UndefValue>(C))
1481     EntryBuilder.buildUndef(Reg);
1482   else if (isa<ConstantPointerNull>(C)) {
1483     // As we are trying to build a constant val of 0 into a pointer,
1484     // insert a cast to make them correct with respect to types.
1485     unsigned NullSize = DL->getTypeSizeInBits(C.getType());
1486     auto *ZeroTy = Type::getIntNTy(C.getContext(), NullSize);
1487     auto *ZeroVal = ConstantInt::get(ZeroTy, 0);
1488     unsigned ZeroReg = getOrCreateVReg(*ZeroVal);
1489     EntryBuilder.buildCast(Reg, ZeroReg);
1490   } else if (auto GV = dyn_cast<GlobalValue>(&C))
1491     EntryBuilder.buildGlobalValue(Reg, GV);
1492   else if (auto CAZ = dyn_cast<ConstantAggregateZero>(&C)) {
1493     if (!CAZ->getType()->isVectorTy())
1494       return false;
1495     // Return the scalar if it is a <1 x Ty> vector.
1496     if (CAZ->getNumElements() == 1)
1497       return translate(*CAZ->getElementValue(0u), Reg);
1498     std::vector<unsigned> Ops;
1499     for (unsigned i = 0; i < CAZ->getNumElements(); ++i) {
1500       Constant &Elt = *CAZ->getElementValue(i);
1501       Ops.push_back(getOrCreateVReg(Elt));
1502     }
1503     EntryBuilder.buildMerge(Reg, Ops);
1504   } else if (auto CV = dyn_cast<ConstantDataVector>(&C)) {
1505     // Return the scalar if it is a <1 x Ty> vector.
1506     if (CV->getNumElements() == 1)
1507       return translate(*CV->getElementAsConstant(0), Reg);
1508     std::vector<unsigned> Ops;
1509     for (unsigned i = 0; i < CV->getNumElements(); ++i) {
1510       Constant &Elt = *CV->getElementAsConstant(i);
1511       Ops.push_back(getOrCreateVReg(Elt));
1512     }
1513     EntryBuilder.buildMerge(Reg, Ops);
1514   } else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
1515     switch(CE->getOpcode()) {
1516 #define HANDLE_INST(NUM, OPCODE, CLASS)                         \
1517       case Instruction::OPCODE: return translate##OPCODE(*CE, EntryBuilder);
1518 #include "llvm/IR/Instruction.def"
1519     default:
1520       return false;
1521     }
1522   } else if (auto CV = dyn_cast<ConstantVector>(&C)) {
1523     if (CV->getNumOperands() == 1)
1524       return translate(*CV->getOperand(0), Reg);
1525     SmallVector<unsigned, 4> Ops;
1526     for (unsigned i = 0; i < CV->getNumOperands(); ++i) {
1527       Ops.push_back(getOrCreateVReg(*CV->getOperand(i)));
1528     }
1529     EntryBuilder.buildMerge(Reg, Ops);
1530   } else if (auto *BA = dyn_cast<BlockAddress>(&C)) {
1531     EntryBuilder.buildBlockAddress(Reg, BA);
1532   } else
1533     return false;
1534 
1535   return true;
1536 }
1537 
1538 void IRTranslator::finalizeFunction() {
1539   // Release the memory used by the different maps we
1540   // needed during the translation.
1541   PendingPHIs.clear();
1542   VMap.reset();
1543   FrameIndices.clear();
1544   MachinePreds.clear();
1545   // MachineIRBuilder::DebugLoc can outlive the DILocation it holds. Clear it
1546   // to avoid accessing free’d memory (in runOnMachineFunction) and to avoid
1547   // destroying it twice (in ~IRTranslator() and ~LLVMContext())
1548   EntryBuilder = MachineIRBuilder();
1549   CurBuilder = MachineIRBuilder();
1550 }
1551 
1552 bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
1553   MF = &CurMF;
1554   const Function &F = MF->getFunction();
1555   if (F.empty())
1556     return false;
1557   CLI = MF->getSubtarget().getCallLowering();
1558   CurBuilder.setMF(*MF);
1559   EntryBuilder.setMF(*MF);
1560   MRI = &MF->getRegInfo();
1561   DL = &F.getParent()->getDataLayout();
1562   TPC = &getAnalysis<TargetPassConfig>();
1563   ORE = llvm::make_unique<OptimizationRemarkEmitter>(&F);
1564 
1565   assert(PendingPHIs.empty() && "stale PHIs");
1566 
1567   if (!DL->isLittleEndian()) {
1568     // Currently we don't properly handle big endian code.
1569     OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1570                                F.getSubprogram(), &F.getEntryBlock());
1571     R << "unable to translate in big endian mode";
1572     reportTranslationError(*MF, *TPC, *ORE, R);
1573   }
1574 
1575   // Release the per-function state when we return, whether we succeeded or not.
1576   auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
1577 
1578   // Setup a separate basic-block for the arguments and constants
1579   MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
1580   MF->push_back(EntryBB);
1581   EntryBuilder.setMBB(*EntryBB);
1582 
1583   // Create all blocks, in IR order, to preserve the layout.
1584   for (const BasicBlock &BB: F) {
1585     auto *&MBB = BBToMBB[&BB];
1586 
1587     MBB = MF->CreateMachineBasicBlock(&BB);
1588     MF->push_back(MBB);
1589 
1590     if (BB.hasAddressTaken())
1591       MBB->setHasAddressTaken();
1592   }
1593 
1594   // Make our arguments/constants entry block fallthrough to the IR entry block.
1595   EntryBB->addSuccessor(&getMBB(F.front()));
1596 
1597   // Lower the actual args into this basic block.
1598   SmallVector<unsigned, 8> VRegArgs;
1599   for (const Argument &Arg: F.args()) {
1600     if (DL->getTypeStoreSize(Arg.getType()) == 0)
1601       continue; // Don't handle zero sized types.
1602     VRegArgs.push_back(
1603         MRI->createGenericVirtualRegister(getLLTForType(*Arg.getType(), *DL)));
1604   }
1605 
1606   // We don't currently support translating swifterror or swiftself functions.
1607   for (auto &Arg : F.args()) {
1608     if (Arg.hasSwiftErrorAttr() || Arg.hasSwiftSelfAttr()) {
1609       OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1610                                  F.getSubprogram(), &F.getEntryBlock());
1611       R << "unable to lower arguments due to swifterror/swiftself: "
1612         << ore::NV("Prototype", F.getType());
1613       reportTranslationError(*MF, *TPC, *ORE, R);
1614       return false;
1615     }
1616   }
1617 
1618   if (!CLI->lowerFormalArguments(EntryBuilder, F, VRegArgs)) {
1619     OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1620                                F.getSubprogram(), &F.getEntryBlock());
1621     R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
1622     reportTranslationError(*MF, *TPC, *ORE, R);
1623     return false;
1624   }
1625 
1626   auto ArgIt = F.arg_begin();
1627   for (auto &VArg : VRegArgs) {
1628     // If the argument is an unsplit scalar then don't use unpackRegs to avoid
1629     // creating redundant copies.
1630     if (!valueIsSplit(*ArgIt, VMap.getOffsets(*ArgIt))) {
1631       auto &VRegs = *VMap.getVRegs(cast<Value>(*ArgIt));
1632       assert(VRegs.empty() && "VRegs already populated?");
1633       VRegs.push_back(VArg);
1634     } else {
1635       unpackRegs(*ArgIt, VArg, EntryBuilder);
1636     }
1637     ArgIt++;
1638   }
1639 
1640   // Need to visit defs before uses when translating instructions.
1641   ReversePostOrderTraversal<const Function *> RPOT(&F);
1642   for (const BasicBlock *BB : RPOT) {
1643     MachineBasicBlock &MBB = getMBB(*BB);
1644     // Set the insertion point of all the following translations to
1645     // the end of this basic block.
1646     CurBuilder.setMBB(MBB);
1647 
1648     for (const Instruction &Inst : *BB) {
1649       if (translate(Inst))
1650         continue;
1651 
1652       OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
1653                                  Inst.getDebugLoc(), BB);
1654       R << "unable to translate instruction: " << ore::NV("Opcode", &Inst);
1655 
1656       if (ORE->allowExtraAnalysis("gisel-irtranslator")) {
1657         std::string InstStrStorage;
1658         raw_string_ostream InstStr(InstStrStorage);
1659         InstStr << Inst;
1660 
1661         R << ": '" << InstStr.str() << "'";
1662       }
1663 
1664       reportTranslationError(*MF, *TPC, *ORE, R);
1665       return false;
1666     }
1667   }
1668 
1669   finishPendingPhis();
1670 
1671   // Merge the argument lowering and constants block with its single
1672   // successor, the LLVM-IR entry block.  We want the basic block to
1673   // be maximal.
1674   assert(EntryBB->succ_size() == 1 &&
1675          "Custom BB used for lowering should have only one successor");
1676   // Get the successor of the current entry block.
1677   MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
1678   assert(NewEntryBB.pred_size() == 1 &&
1679          "LLVM-IR entry block has a predecessor!?");
1680   // Move all the instruction from the current entry block to the
1681   // new entry block.
1682   NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
1683                     EntryBB->end());
1684 
1685   // Update the live-in information for the new entry block.
1686   for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
1687     NewEntryBB.addLiveIn(LiveIn);
1688   NewEntryBB.sortUniqueLiveIns();
1689 
1690   // Get rid of the now empty basic block.
1691   EntryBB->removeSuccessor(&NewEntryBB);
1692   MF->remove(EntryBB);
1693   MF->DeleteMachineBasicBlock(EntryBB);
1694 
1695   assert(&MF->front() == &NewEntryBB &&
1696          "New entry wasn't next in the list of basic block!");
1697 
1698   // Initialize stack protector information.
1699   StackProtector &SP = getAnalysis<StackProtector>();
1700   SP.copyToMachineFrameInfo(MF->getFrameInfo());
1701 
1702   return false;
1703 }
1704