1 //===-- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator --*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the IRTranslator class.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
14 
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/CodeGen/TargetPassConfig.h"
21 #include "llvm/IR/Constant.h"
22 #include "llvm/IR/Function.h"
23 #include "llvm/IR/GetElementPtrTypeIterator.h"
24 #include "llvm/IR/IntrinsicInst.h"
25 #include "llvm/IR/Type.h"
26 #include "llvm/IR/Value.h"
27 #include "llvm/Target/TargetIntrinsicInfo.h"
28 #include "llvm/Target/TargetLowering.h"
29 
30 #define DEBUG_TYPE "irtranslator"
31 
32 using namespace llvm;
33 
34 char IRTranslator::ID = 0;
35 INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
36                 false, false)
37 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
38 INITIALIZE_PASS_END(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
39                 false, false)
40 
41 IRTranslator::IRTranslator() : MachineFunctionPass(ID), MRI(nullptr) {
42   initializeIRTranslatorPass(*PassRegistry::getPassRegistry());
43 }
44 
45 void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const {
46   AU.addRequired<TargetPassConfig>();
47   MachineFunctionPass::getAnalysisUsage(AU);
48 }
49 
50 
51 unsigned IRTranslator::getOrCreateVReg(const Value &Val) {
52   unsigned &ValReg = ValToVReg[&Val];
53   // Check if this is the first time we see Val.
54   if (!ValReg) {
55     // Fill ValRegsSequence with the sequence of registers
56     // we need to concat together to produce the value.
57     assert(Val.getType()->isSized() &&
58            "Don't know how to create an empty vreg");
59     unsigned VReg = MRI->createGenericVirtualRegister(LLT{*Val.getType(), *DL});
60     ValReg = VReg;
61 
62     if (auto CV = dyn_cast<Constant>(&Val)) {
63       bool Success = translate(*CV, VReg);
64       if (!Success) {
65         if (!TPC->isGlobalISelAbortEnabled()) {
66           MIRBuilder.getMF().getProperties().set(
67               MachineFunctionProperties::Property::FailedISel);
68           return 0;
69         }
70         report_fatal_error("unable to translate constant");
71       }
72     }
73   }
74   return ValReg;
75 }
76 
77 int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
78   if (FrameIndices.find(&AI) != FrameIndices.end())
79     return FrameIndices[&AI];
80 
81   MachineFunction &MF = MIRBuilder.getMF();
82   unsigned ElementSize = DL->getTypeStoreSize(AI.getAllocatedType());
83   unsigned Size =
84       ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
85 
86   // Always allocate at least one byte.
87   Size = std::max(Size, 1u);
88 
89   unsigned Alignment = AI.getAlignment();
90   if (!Alignment)
91     Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
92 
93   int &FI = FrameIndices[&AI];
94   FI = MF.getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
95   return FI;
96 }
97 
98 unsigned IRTranslator::getMemOpAlignment(const Instruction &I) {
99   unsigned Alignment = 0;
100   Type *ValTy = nullptr;
101   if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) {
102     Alignment = SI->getAlignment();
103     ValTy = SI->getValueOperand()->getType();
104   } else if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) {
105     Alignment = LI->getAlignment();
106     ValTy = LI->getType();
107   } else if (!TPC->isGlobalISelAbortEnabled()) {
108     MIRBuilder.getMF().getProperties().set(
109         MachineFunctionProperties::Property::FailedISel);
110     return 1;
111   } else
112     llvm_unreachable("unhandled memory instruction");
113 
114   return Alignment ? Alignment : DL->getABITypeAlignment(ValTy);
115 }
116 
117 MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock &BB) {
118   MachineBasicBlock *&MBB = BBToMBB[&BB];
119   if (!MBB) {
120     MachineFunction &MF = MIRBuilder.getMF();
121     MBB = MF.CreateMachineBasicBlock();
122     MF.push_back(MBB);
123   }
124   return *MBB;
125 }
126 
127 bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U) {
128   // FIXME: handle signed/unsigned wrapping flags.
129 
130   // Get or create a virtual register for each value.
131   // Unless the value is a Constant => loadimm cst?
132   // or inline constant each time?
133   // Creation of a virtual register needs to have a size.
134   unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
135   unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
136   unsigned Res = getOrCreateVReg(U);
137   MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1);
138   return true;
139 }
140 
141 bool IRTranslator::translateCompare(const User &U) {
142   const CmpInst *CI = dyn_cast<CmpInst>(&U);
143   unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
144   unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
145   unsigned Res = getOrCreateVReg(U);
146   CmpInst::Predicate Pred =
147       CI ? CI->getPredicate() : static_cast<CmpInst::Predicate>(
148                                     cast<ConstantExpr>(U).getPredicate());
149 
150   if (CmpInst::isIntPredicate(Pred))
151     MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
152   else
153     MIRBuilder.buildFCmp(Pred, Res, Op0, Op1);
154 
155   return true;
156 }
157 
158 bool IRTranslator::translateRet(const User &U) {
159   const ReturnInst &RI = cast<ReturnInst>(U);
160   const Value *Ret = RI.getReturnValue();
161   // The target may mess up with the insertion point, but
162   // this is not important as a return is the last instruction
163   // of the block anyway.
164   return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
165 }
166 
167 bool IRTranslator::translateBr(const User &U) {
168   const BranchInst &BrInst = cast<BranchInst>(U);
169   unsigned Succ = 0;
170   if (!BrInst.isUnconditional()) {
171     // We want a G_BRCOND to the true BB followed by an unconditional branch.
172     unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
173     const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
174     MachineBasicBlock &TrueBB = getOrCreateBB(TrueTgt);
175     MIRBuilder.buildBrCond(Tst, TrueBB);
176   }
177 
178   const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
179   MachineBasicBlock &TgtBB = getOrCreateBB(BrTgt);
180   MIRBuilder.buildBr(TgtBB);
181 
182   // Link successors.
183   MachineBasicBlock &CurBB = MIRBuilder.getMBB();
184   for (const BasicBlock *Succ : BrInst.successors())
185     CurBB.addSuccessor(&getOrCreateBB(*Succ));
186   return true;
187 }
188 
189 bool IRTranslator::translateLoad(const User &U) {
190   const LoadInst &LI = cast<LoadInst>(U);
191 
192   if (!TPC->isGlobalISelAbortEnabled() && LI.isAtomic())
193     return false;
194 
195   assert(!LI.isAtomic() && "only non-atomic loads are supported at the moment");
196   auto Flags = LI.isVolatile() ? MachineMemOperand::MOVolatile
197                                : MachineMemOperand::MONone;
198   Flags |= MachineMemOperand::MOLoad;
199 
200   MachineFunction &MF = MIRBuilder.getMF();
201   unsigned Res = getOrCreateVReg(LI);
202   unsigned Addr = getOrCreateVReg(*LI.getPointerOperand());
203   LLT VTy{*LI.getType(), *DL}, PTy{*LI.getPointerOperand()->getType(), *DL};
204   MIRBuilder.buildLoad(
205       Res, Addr,
206       *MF.getMachineMemOperand(MachinePointerInfo(LI.getPointerOperand()),
207                                Flags, DL->getTypeStoreSize(LI.getType()),
208                                getMemOpAlignment(LI)));
209   return true;
210 }
211 
212 bool IRTranslator::translateStore(const User &U) {
213   const StoreInst &SI = cast<StoreInst>(U);
214 
215   if (!TPC->isGlobalISelAbortEnabled() && SI.isAtomic())
216     return false;
217 
218   assert(!SI.isAtomic() && "only non-atomic stores supported at the moment");
219   auto Flags = SI.isVolatile() ? MachineMemOperand::MOVolatile
220                                : MachineMemOperand::MONone;
221   Flags |= MachineMemOperand::MOStore;
222 
223   MachineFunction &MF = MIRBuilder.getMF();
224   unsigned Val = getOrCreateVReg(*SI.getValueOperand());
225   unsigned Addr = getOrCreateVReg(*SI.getPointerOperand());
226   LLT VTy{*SI.getValueOperand()->getType(), *DL},
227       PTy{*SI.getPointerOperand()->getType(), *DL};
228 
229   MIRBuilder.buildStore(
230       Val, Addr, *MF.getMachineMemOperand(
231                      MachinePointerInfo(SI.getPointerOperand()), Flags,
232                      DL->getTypeStoreSize(SI.getValueOperand()->getType()),
233                      getMemOpAlignment(SI)));
234   return true;
235 }
236 
237 bool IRTranslator::translateExtractValue(const User &U) {
238   const Value *Src = U.getOperand(0);
239   Type *Int32Ty = Type::getInt32Ty(U.getContext());
240   SmallVector<Value *, 1> Indices;
241 
242   // getIndexedOffsetInType is designed for GEPs, so the first index is the
243   // usual array element rather than looking into the actual aggregate.
244   Indices.push_back(ConstantInt::get(Int32Ty, 0));
245 
246   if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&U)) {
247     for (auto Idx : EVI->indices())
248       Indices.push_back(ConstantInt::get(Int32Ty, Idx));
249   } else {
250     for (unsigned i = 1; i < U.getNumOperands(); ++i)
251       Indices.push_back(U.getOperand(i));
252   }
253 
254   uint64_t Offset = 8 * DL->getIndexedOffsetInType(Src->getType(), Indices);
255 
256   unsigned Res = getOrCreateVReg(U);
257   MIRBuilder.buildExtract(Res, Offset, getOrCreateVReg(*Src));
258 
259   return true;
260 }
261 
262 bool IRTranslator::translateInsertValue(const User &U) {
263   const Value *Src = U.getOperand(0);
264   Type *Int32Ty = Type::getInt32Ty(U.getContext());
265   SmallVector<Value *, 1> Indices;
266 
267   // getIndexedOffsetInType is designed for GEPs, so the first index is the
268   // usual array element rather than looking into the actual aggregate.
269   Indices.push_back(ConstantInt::get(Int32Ty, 0));
270 
271   if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(&U)) {
272     for (auto Idx : IVI->indices())
273       Indices.push_back(ConstantInt::get(Int32Ty, Idx));
274   } else {
275     for (unsigned i = 2; i < U.getNumOperands(); ++i)
276       Indices.push_back(U.getOperand(i));
277   }
278 
279   uint64_t Offset = 8 * DL->getIndexedOffsetInType(Src->getType(), Indices);
280 
281   unsigned Res = getOrCreateVReg(U);
282   const Value &Inserted = *U.getOperand(1);
283   MIRBuilder.buildInsert(Res, getOrCreateVReg(*Src), getOrCreateVReg(Inserted),
284                          Offset);
285 
286   return true;
287 }
288 
289 bool IRTranslator::translateSelect(const User &U) {
290   MIRBuilder.buildSelect(getOrCreateVReg(U), getOrCreateVReg(*U.getOperand(0)),
291                          getOrCreateVReg(*U.getOperand(1)),
292                          getOrCreateVReg(*U.getOperand(2)));
293   return true;
294 }
295 
296 bool IRTranslator::translateBitCast(const User &U) {
297   if (LLT{*U.getOperand(0)->getType(), *DL} == LLT{*U.getType(), *DL}) {
298     unsigned &Reg = ValToVReg[&U];
299     if (Reg)
300       MIRBuilder.buildCopy(Reg, getOrCreateVReg(*U.getOperand(0)));
301     else
302       Reg = getOrCreateVReg(*U.getOperand(0));
303     return true;
304   }
305   return translateCast(TargetOpcode::G_BITCAST, U);
306 }
307 
308 bool IRTranslator::translateCast(unsigned Opcode, const User &U) {
309   unsigned Op = getOrCreateVReg(*U.getOperand(0));
310   unsigned Res = getOrCreateVReg(U);
311   MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op);
312   return true;
313 }
314 
315 bool IRTranslator::translateGetElementPtr(const User &U) {
316   // FIXME: support vector GEPs.
317   if (U.getType()->isVectorTy())
318     return false;
319 
320   Value &Op0 = *U.getOperand(0);
321   unsigned BaseReg = getOrCreateVReg(Op0);
322   LLT PtrTy{*Op0.getType(), *DL};
323   unsigned PtrSize = DL->getPointerSizeInBits(PtrTy.getAddressSpace());
324   LLT OffsetTy = LLT::scalar(PtrSize);
325 
326   int64_t Offset = 0;
327   for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
328        GTI != E; ++GTI) {
329     const Value *Idx = GTI.getOperand();
330     if (StructType *StTy = dyn_cast<StructType>(*GTI)) {
331       unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
332       Offset += DL->getStructLayout(StTy)->getElementOffset(Field);
333       continue;
334     } else {
335       uint64_t ElementSize = DL->getTypeAllocSize(GTI.getIndexedType());
336 
337       // If this is a scalar constant or a splat vector of constants,
338       // handle it quickly.
339       if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
340         Offset += ElementSize * CI->getSExtValue();
341         continue;
342       }
343 
344       if (Offset != 0) {
345         unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
346         unsigned OffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
347         MIRBuilder.buildConstant(OffsetReg, Offset);
348         MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
349 
350         BaseReg = NewBaseReg;
351         Offset = 0;
352       }
353 
354       // N = N + Idx * ElementSize;
355       unsigned ElementSizeReg = MRI->createGenericVirtualRegister(OffsetTy);
356       MIRBuilder.buildConstant(ElementSizeReg, ElementSize);
357 
358       unsigned IdxReg = getOrCreateVReg(*Idx);
359       if (MRI->getType(IdxReg) != OffsetTy) {
360         unsigned NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
361         MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
362         IdxReg = NewIdxReg;
363       }
364 
365       unsigned OffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
366       MIRBuilder.buildMul(OffsetReg, ElementSizeReg, IdxReg);
367 
368       unsigned NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
369       MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetReg);
370       BaseReg = NewBaseReg;
371     }
372   }
373 
374   if (Offset != 0) {
375     unsigned OffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
376     MIRBuilder.buildConstant(OffsetReg, Offset);
377     MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetReg);
378     return true;
379   }
380 
381   MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
382   return true;
383 }
384 
385 bool IRTranslator::translateMemcpy(const CallInst &CI) {
386   LLT SizeTy{*CI.getArgOperand(2)->getType(), *DL};
387   if (cast<PointerType>(CI.getArgOperand(0)->getType())->getAddressSpace() !=
388           0 ||
389       cast<PointerType>(CI.getArgOperand(1)->getType())->getAddressSpace() !=
390           0 ||
391       SizeTy.getSizeInBits() != DL->getPointerSizeInBits(0))
392     return false;
393 
394   SmallVector<CallLowering::ArgInfo, 8> Args;
395   for (int i = 0; i < 3; ++i) {
396     const auto &Arg = CI.getArgOperand(i);
397     Args.emplace_back(getOrCreateVReg(*Arg), Arg->getType());
398   }
399 
400   MachineOperand Callee = MachineOperand::CreateES("memcpy");
401 
402   return CLI->lowerCall(MIRBuilder, Callee,
403                         CallLowering::ArgInfo(0, CI.getType()), Args);
404 }
405 
406 void IRTranslator::getStackGuard(unsigned DstReg) {
407   auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
408   MIB.addDef(DstReg);
409 
410   auto &MF = MIRBuilder.getMF();
411   auto &TLI = *MF.getSubtarget().getTargetLowering();
412   Value *Global = TLI.getSDagStackGuard(*MF.getFunction()->getParent());
413   if (!Global)
414     return;
415 
416   MachinePointerInfo MPInfo(Global);
417   MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(1);
418   auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
419                MachineMemOperand::MODereferenceable;
420   *MemRefs =
421       MF.getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8,
422                               DL->getPointerABIAlignment());
423   MIB.setMemRefs(MemRefs, MemRefs + 1);
424 }
425 
426 bool IRTranslator::translateKnownIntrinsic(const CallInst &CI,
427                                            Intrinsic::ID ID) {
428   unsigned Op = 0;
429   switch (ID) {
430   default: return false;
431   case Intrinsic::uadd_with_overflow: Op = TargetOpcode::G_UADDE; break;
432   case Intrinsic::sadd_with_overflow: Op = TargetOpcode::G_SADDO; break;
433   case Intrinsic::usub_with_overflow: Op = TargetOpcode::G_USUBE; break;
434   case Intrinsic::ssub_with_overflow: Op = TargetOpcode::G_SSUBO; break;
435   case Intrinsic::umul_with_overflow: Op = TargetOpcode::G_UMULO; break;
436   case Intrinsic::smul_with_overflow: Op = TargetOpcode::G_SMULO; break;
437   case Intrinsic::memcpy:
438     return translateMemcpy(CI);
439   case Intrinsic::objectsize: {
440     // If we don't know by now, we're never going to know.
441     const ConstantInt *Min = cast<ConstantInt>(CI.getArgOperand(1));
442 
443     MIRBuilder.buildConstant(getOrCreateVReg(CI), Min->isZero() ? -1ULL : 0);
444     return true;
445   }
446   case Intrinsic::stackguard:
447     getStackGuard(getOrCreateVReg(CI));
448     return true;
449   case Intrinsic::stackprotector: {
450     MachineFunction &MF = MIRBuilder.getMF();
451     LLT PtrTy{*CI.getArgOperand(0)->getType(), *DL};
452     unsigned GuardVal = MRI->createGenericVirtualRegister(PtrTy);
453     getStackGuard(GuardVal);
454 
455     AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
456     MIRBuilder.buildStore(
457         GuardVal, getOrCreateVReg(*Slot),
458         *MF.getMachineMemOperand(
459             MachinePointerInfo::getFixedStack(MF, getOrCreateFrameIndex(*Slot)),
460             MachineMemOperand::MOStore | MachineMemOperand::MOVolatile,
461             PtrTy.getSizeInBits() / 8, 8));
462     return true;
463   }
464   }
465 
466   LLT Ty{*CI.getOperand(0)->getType(), *DL};
467   LLT s1 = LLT::scalar(1);
468   unsigned Width = Ty.getSizeInBits();
469   unsigned Res = MRI->createGenericVirtualRegister(Ty);
470   unsigned Overflow = MRI->createGenericVirtualRegister(s1);
471   auto MIB = MIRBuilder.buildInstr(Op)
472                  .addDef(Res)
473                  .addDef(Overflow)
474                  .addUse(getOrCreateVReg(*CI.getOperand(0)))
475                  .addUse(getOrCreateVReg(*CI.getOperand(1)));
476 
477   if (Op == TargetOpcode::G_UADDE || Op == TargetOpcode::G_USUBE) {
478     unsigned Zero = MRI->createGenericVirtualRegister(s1);
479     EntryBuilder.buildConstant(Zero, 0);
480     MIB.addUse(Zero);
481   }
482 
483   MIRBuilder.buildSequence(getOrCreateVReg(CI), Res, 0, Overflow, Width);
484   return true;
485 }
486 
487 bool IRTranslator::translateCall(const User &U) {
488   const CallInst &CI = cast<CallInst>(U);
489   auto TII = MIRBuilder.getMF().getTarget().getIntrinsicInfo();
490   const Function *F = CI.getCalledFunction();
491 
492   if (!F || !F->isIntrinsic()) {
493     unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
494     SmallVector<unsigned, 8> Args;
495     for (auto &Arg: CI.arg_operands())
496       Args.push_back(getOrCreateVReg(*Arg));
497 
498     return CLI->lowerCall(MIRBuilder, CI, Res, Args, [&]() {
499       return getOrCreateVReg(*CI.getCalledValue());
500     });
501   }
502 
503   Intrinsic::ID ID = F->getIntrinsicID();
504   if (TII && ID == Intrinsic::not_intrinsic)
505     ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
506 
507   assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
508 
509   if (translateKnownIntrinsic(CI, ID))
510     return true;
511 
512   unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
513   MachineInstrBuilder MIB =
514       MIRBuilder.buildIntrinsic(ID, Res, !CI.doesNotAccessMemory());
515 
516   for (auto &Arg : CI.arg_operands()) {
517     if (ConstantInt *CI = dyn_cast<ConstantInt>(Arg))
518       MIB.addImm(CI->getSExtValue());
519     else
520       MIB.addUse(getOrCreateVReg(*Arg));
521   }
522   return true;
523 }
524 
525 bool IRTranslator::translateStaticAlloca(const AllocaInst &AI) {
526   if (!TPC->isGlobalISelAbortEnabled() && !AI.isStaticAlloca())
527     return false;
528 
529   assert(AI.isStaticAlloca() && "only handle static allocas now");
530   unsigned Res = getOrCreateVReg(AI);
531   int FI = getOrCreateFrameIndex(AI);
532   MIRBuilder.buildFrameIndex(Res, FI);
533   return true;
534 }
535 
536 bool IRTranslator::translatePHI(const User &U) {
537   const PHINode &PI = cast<PHINode>(U);
538   auto MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
539   MIB.addDef(getOrCreateVReg(PI));
540 
541   PendingPHIs.emplace_back(&PI, MIB.getInstr());
542   return true;
543 }
544 
545 void IRTranslator::finishPendingPhis() {
546   for (std::pair<const PHINode *, MachineInstr *> &Phi : PendingPHIs) {
547     const PHINode *PI = Phi.first;
548     MachineInstrBuilder MIB(MIRBuilder.getMF(), Phi.second);
549 
550     // All MachineBasicBlocks exist, add them to the PHI. We assume IRTranslator
551     // won't create extra control flow here, otherwise we need to find the
552     // dominating predecessor here (or perhaps force the weirder IRTranslators
553     // to provide a simple boundary).
554     for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
555       assert(BBToMBB[PI->getIncomingBlock(i)]->isSuccessor(MIB->getParent()) &&
556              "I appear to have misunderstood Machine PHIs");
557       MIB.addUse(getOrCreateVReg(*PI->getIncomingValue(i)));
558       MIB.addMBB(BBToMBB[PI->getIncomingBlock(i)]);
559     }
560   }
561 
562   PendingPHIs.clear();
563 }
564 
565 bool IRTranslator::translate(const Instruction &Inst) {
566   MIRBuilder.setDebugLoc(Inst.getDebugLoc());
567   switch(Inst.getOpcode()) {
568 #define HANDLE_INST(NUM, OPCODE, CLASS) \
569     case Instruction::OPCODE: return translate##OPCODE(Inst);
570 #include "llvm/IR/Instruction.def"
571   default:
572     if (!TPC->isGlobalISelAbortEnabled())
573       return false;
574     llvm_unreachable("unknown opcode");
575   }
576 }
577 
578 bool IRTranslator::translate(const Constant &C, unsigned Reg) {
579   if (auto CI = dyn_cast<ConstantInt>(&C))
580     EntryBuilder.buildConstant(Reg, CI->getZExtValue());
581   else if (auto CF = dyn_cast<ConstantFP>(&C))
582     EntryBuilder.buildFConstant(Reg, *CF);
583   else if (isa<UndefValue>(C))
584     EntryBuilder.buildInstr(TargetOpcode::IMPLICIT_DEF).addDef(Reg);
585   else if (isa<ConstantPointerNull>(C))
586     EntryBuilder.buildInstr(TargetOpcode::G_CONSTANT)
587         .addDef(Reg)
588         .addImm(0);
589   else if (auto GV = dyn_cast<GlobalValue>(&C))
590     EntryBuilder.buildGlobalValue(Reg, GV);
591   else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
592     switch(CE->getOpcode()) {
593 #define HANDLE_INST(NUM, OPCODE, CLASS)                         \
594       case Instruction::OPCODE: return translate##OPCODE(*CE);
595 #include "llvm/IR/Instruction.def"
596     default:
597       if (!TPC->isGlobalISelAbortEnabled())
598         return false;
599       llvm_unreachable("unknown opcode");
600     }
601   } else if (!TPC->isGlobalISelAbortEnabled())
602     return false;
603   else
604     llvm_unreachable("unhandled constant kind");
605 
606   return true;
607 }
608 
609 
610 void IRTranslator::finalizeFunction() {
611   finishPendingPhis();
612 
613   // Release the memory used by the different maps we
614   // needed during the translation.
615   ValToVReg.clear();
616   FrameIndices.clear();
617   Constants.clear();
618 }
619 
620 bool IRTranslator::runOnMachineFunction(MachineFunction &MF) {
621   const Function &F = *MF.getFunction();
622   if (F.empty())
623     return false;
624   CLI = MF.getSubtarget().getCallLowering();
625   MIRBuilder.setMF(MF);
626   EntryBuilder.setMF(MF);
627   MRI = &MF.getRegInfo();
628   DL = &F.getParent()->getDataLayout();
629   TPC = &getAnalysis<TargetPassConfig>();
630 
631   assert(PendingPHIs.empty() && "stale PHIs");
632 
633   // Setup the arguments.
634   MachineBasicBlock &MBB = getOrCreateBB(F.front());
635   MIRBuilder.setMBB(MBB);
636   SmallVector<unsigned, 8> VRegArgs;
637   for (const Argument &Arg: F.args())
638     VRegArgs.push_back(getOrCreateVReg(Arg));
639   bool Succeeded = CLI->lowerFormalArguments(MIRBuilder, F, VRegArgs);
640   if (!Succeeded) {
641     if (!TPC->isGlobalISelAbortEnabled()) {
642       MIRBuilder.getMF().getProperties().set(
643           MachineFunctionProperties::Property::FailedISel);
644       return false;
645     }
646     report_fatal_error("Unable to lower arguments");
647   }
648 
649   // Now that we've got the ABI handling code, it's safe to set a location for
650   // any Constants we find in the IR.
651   if (MBB.empty())
652     EntryBuilder.setMBB(MBB);
653   else
654     EntryBuilder.setInstr(MBB.back(), /* Before */ false);
655 
656   for (const BasicBlock &BB: F) {
657     MachineBasicBlock &MBB = getOrCreateBB(BB);
658     // Set the insertion point of all the following translations to
659     // the end of this basic block.
660     MIRBuilder.setMBB(MBB);
661     for (const Instruction &Inst: BB) {
662       bool Succeeded = translate(Inst);
663       if (!Succeeded) {
664         DEBUG(dbgs() << "Cannot translate: " << Inst << '\n');
665         if (TPC->isGlobalISelAbortEnabled())
666           report_fatal_error("Unable to translate instruction");
667         MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
668         break;
669       }
670     }
671   }
672 
673   finalizeFunction();
674 
675   // Now that the MachineFrameInfo has been configured, no further changes to
676   // the reserved registers are possible.
677   MRI->freezeReservedRegs(MF);
678 
679   return false;
680 }
681