1 //===-- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator --*- C++ -*-==//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 /// \file
10 /// This file implements the IRTranslator class.
11 //===----------------------------------------------------------------------===//
12 
13 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
14 
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/IR/Constant.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/IR/Type.h"
22 #include "llvm/IR/Value.h"
23 #include "llvm/Target/TargetLowering.h"
24 
25 #define DEBUG_TYPE "irtranslator"
26 
27 using namespace llvm;
28 
29 char IRTranslator::ID = 0;
30 
31 IRTranslator::IRTranslator() : MachineFunctionPass(ID), MRI(nullptr) {
32 }
33 
34 unsigned IRTranslator::getOrCreateVReg(const Value *Val) {
35   unsigned &ValReg = ValToVReg[Val];
36   // Check if this is the first time we see Val.
37   if (!ValReg) {
38     // Fill ValRegsSequence with the sequence of registers
39     // we need to concat together to produce the value.
40     assert(Val->getType()->isSized() &&
41            "Don't know how to create an empty vreg");
42     assert(!Val->getType()->isAggregateType() && "Not yet implemented");
43     unsigned Size = Val->getType()->getPrimitiveSizeInBits();
44     unsigned VReg = MRI->createGenericVirtualRegister(Size);
45     ValReg = VReg;
46     assert(!isa<Constant>(Val) && "Not yet implemented");
47   }
48   return ValReg;
49 }
50 
51 MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock *BB) {
52   MachineBasicBlock *&MBB = BBToMBB[BB];
53   if (!MBB) {
54     MachineFunction &MF = MIRBuilder.getMF();
55     MBB = MF.CreateMachineBasicBlock();
56     MF.push_back(MBB);
57   }
58   return *MBB;
59 }
60 
61 bool IRTranslator::translateADD(const Instruction &Inst) {
62   // Get or create a virtual register for each value.
63   // Unless the value is a Constant => loadimm cst?
64   // or inline constant each time?
65   // Creation of a virtual register needs to have a size.
66   unsigned Op0 = getOrCreateVReg(Inst.getOperand(0));
67   unsigned Op1 = getOrCreateVReg(Inst.getOperand(1));
68   unsigned Res = getOrCreateVReg(&Inst);
69   MIRBuilder.buildInstr(TargetOpcode::G_ADD, Inst.getType(), Res, Op0, Op1);
70   return true;
71 }
72 
73 bool IRTranslator::translateReturn(const Instruction &Inst) {
74   assert(isa<ReturnInst>(Inst) && "Return expected");
75   const Value *Ret = cast<ReturnInst>(Inst).getReturnValue();
76   // The target may mess up with the insertion point, but
77   // this is not important as a return is the last instruction
78   // of the block anyway.
79   return CLI->LowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(Ret));
80 }
81 
82 bool IRTranslator::translate(const Instruction &Inst) {
83   MIRBuilder.setDebugLoc(Inst.getDebugLoc());
84   switch(Inst.getOpcode()) {
85   case Instruction::Add:
86     return translateADD(Inst);
87   case Instruction::Ret:
88     return translateReturn(Inst);
89 
90   default:
91     llvm_unreachable("Opcode not supported");
92   }
93 }
94 
95 
96 void IRTranslator::finalize() {
97   // Release the memory used by the different maps we
98   // needed during the translation.
99   ValToVReg.clear();
100   Constants.clear();
101 }
102 
103 bool IRTranslator::runOnMachineFunction(MachineFunction &MF) {
104   const Function &F = *MF.getFunction();
105   if (F.empty())
106     return false;
107   CLI = MF.getSubtarget().getCallLowering();
108   MIRBuilder.setFunction(MF);
109   MRI = &MF.getRegInfo();
110   // Setup the arguments.
111   MachineBasicBlock &MBB = getOrCreateBB(&F.front());
112   MIRBuilder.setBasicBlock(MBB);
113   SmallVector<unsigned, 8> VRegArgs;
114   for (const Argument &Arg: F.args())
115     VRegArgs.push_back(getOrCreateVReg(&Arg));
116   bool Succeeded =
117       CLI->LowerFormalArguments(MIRBuilder, F.getArgumentList(), VRegArgs);
118   if (!Succeeded)
119     report_fatal_error("Unable to lower arguments");
120 
121   for (const BasicBlock &BB: F) {
122     MachineBasicBlock &MBB = getOrCreateBB(&BB);
123     MIRBuilder.setBasicBlock(MBB);
124     for (const Instruction &Inst: BB) {
125       bool Succeeded = translate(Inst);
126       if (!Succeeded) {
127         DEBUG(dbgs() << "Cannot translate: " << Inst << '\n');
128         report_fatal_error("Unable to translate instruction");
129       }
130     }
131   }
132   return false;
133 }
134