1 //===- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator ---*- C++ -*-==//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file implements the IRTranslator class.
10 //===----------------------------------------------------------------------===//
11 
12 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
13 #include "llvm/ADT/PostOrderIterator.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/ScopeExit.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/Analysis/BranchProbabilityInfo.h"
19 #include "llvm/Analysis/OptimizationRemarkEmitter.h"
20 #include "llvm/Analysis/ValueTracking.h"
21 #include "llvm/CodeGen/Analysis.h"
22 #include "llvm/CodeGen/FunctionLoweringInfo.h"
23 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
24 #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
25 #include "llvm/CodeGen/LowLevelType.h"
26 #include "llvm/CodeGen/MachineBasicBlock.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineMemOperand.h"
31 #include "llvm/CodeGen/MachineOperand.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/StackProtector.h"
34 #include "llvm/CodeGen/TargetFrameLowering.h"
35 #include "llvm/CodeGen/TargetLowering.h"
36 #include "llvm/CodeGen/TargetPassConfig.h"
37 #include "llvm/CodeGen/TargetRegisterInfo.h"
38 #include "llvm/CodeGen/TargetSubtargetInfo.h"
39 #include "llvm/IR/BasicBlock.h"
40 #include "llvm/IR/CFG.h"
41 #include "llvm/IR/Constant.h"
42 #include "llvm/IR/Constants.h"
43 #include "llvm/IR/DataLayout.h"
44 #include "llvm/IR/DebugInfo.h"
45 #include "llvm/IR/DerivedTypes.h"
46 #include "llvm/IR/Function.h"
47 #include "llvm/IR/GetElementPtrTypeIterator.h"
48 #include "llvm/IR/InlineAsm.h"
49 #include "llvm/IR/InstrTypes.h"
50 #include "llvm/IR/Instructions.h"
51 #include "llvm/IR/IntrinsicInst.h"
52 #include "llvm/IR/Intrinsics.h"
53 #include "llvm/IR/LLVMContext.h"
54 #include "llvm/IR/Metadata.h"
55 #include "llvm/IR/Type.h"
56 #include "llvm/IR/User.h"
57 #include "llvm/IR/Value.h"
58 #include "llvm/MC/MCContext.h"
59 #include "llvm/Pass.h"
60 #include "llvm/Support/Casting.h"
61 #include "llvm/Support/CodeGen.h"
62 #include "llvm/Support/Debug.h"
63 #include "llvm/Support/ErrorHandling.h"
64 #include "llvm/Support/LowLevelTypeImpl.h"
65 #include "llvm/Support/MathExtras.h"
66 #include "llvm/Support/raw_ostream.h"
67 #include "llvm/Target/TargetIntrinsicInfo.h"
68 #include "llvm/Target/TargetMachine.h"
69 #include <algorithm>
70 #include <cassert>
71 #include <cstdint>
72 #include <iterator>
73 #include <string>
74 #include <utility>
75 #include <vector>
76 
77 #define DEBUG_TYPE "irtranslator"
78 
79 using namespace llvm;
80 
81 static cl::opt<bool>
82     EnableCSEInIRTranslator("enable-cse-in-irtranslator",
83                             cl::desc("Should enable CSE in irtranslator"),
84                             cl::Optional, cl::init(false));
85 char IRTranslator::ID = 0;
86 
87 INITIALIZE_PASS_BEGIN(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
88                 false, false)
89 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
90 INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
91 INITIALIZE_PASS_END(IRTranslator, DEBUG_TYPE, "IRTranslator LLVM IR -> MI",
92                 false, false)
93 
94 static void reportTranslationError(MachineFunction &MF,
95                                    const TargetPassConfig &TPC,
96                                    OptimizationRemarkEmitter &ORE,
97                                    OptimizationRemarkMissed &R) {
98   MF.getProperties().set(MachineFunctionProperties::Property::FailedISel);
99 
100   // Print the function name explicitly if we don't have a debug location (which
101   // makes the diagnostic less useful) or if we're going to emit a raw error.
102   if (!R.getLocation().isValid() || TPC.isGlobalISelAbortEnabled())
103     R << (" (in function: " + MF.getName() + ")").str();
104 
105   if (TPC.isGlobalISelAbortEnabled())
106     report_fatal_error(R.getMsg());
107   else
108     ORE.emit(R);
109 }
110 
111 IRTranslator::IRTranslator() : MachineFunctionPass(ID) { }
112 
113 #ifndef NDEBUG
114 namespace {
115 /// Verify that every instruction created has the same DILocation as the
116 /// instruction being translated.
117 class DILocationVerifier : public GISelChangeObserver {
118   const Instruction *CurrInst = nullptr;
119 
120 public:
121   DILocationVerifier() = default;
122   ~DILocationVerifier() = default;
123 
124   const Instruction *getCurrentInst() const { return CurrInst; }
125   void setCurrentInst(const Instruction *Inst) { CurrInst = Inst; }
126 
127   void erasingInstr(MachineInstr &MI) override {}
128   void changingInstr(MachineInstr &MI) override {}
129   void changedInstr(MachineInstr &MI) override {}
130 
131   void createdInstr(MachineInstr &MI) override {
132     assert(getCurrentInst() && "Inserted instruction without a current MI");
133 
134     // Only print the check message if we're actually checking it.
135 #ifndef NDEBUG
136     LLVM_DEBUG(dbgs() << "Checking DILocation from " << *CurrInst
137                       << " was copied to " << MI);
138 #endif
139     // We allow insts in the entry block to have a debug loc line of 0 because
140     // they could have originated from constants, and we don't want a jumpy
141     // debug experience.
142     assert((CurrInst->getDebugLoc() == MI.getDebugLoc() ||
143             MI.getDebugLoc().getLine() == 0) &&
144            "Line info was not transferred to all instructions");
145   }
146 };
147 } // namespace
148 #endif // ifndef NDEBUG
149 
150 
151 void IRTranslator::getAnalysisUsage(AnalysisUsage &AU) const {
152   AU.addRequired<StackProtector>();
153   AU.addRequired<TargetPassConfig>();
154   AU.addRequired<GISelCSEAnalysisWrapperPass>();
155   getSelectionDAGFallbackAnalysisUsage(AU);
156   MachineFunctionPass::getAnalysisUsage(AU);
157 }
158 
159 IRTranslator::ValueToVRegInfo::VRegListT &
160 IRTranslator::allocateVRegs(const Value &Val) {
161   assert(!VMap.contains(Val) && "Value already allocated in VMap");
162   auto *Regs = VMap.getVRegs(Val);
163   auto *Offsets = VMap.getOffsets(Val);
164   SmallVector<LLT, 4> SplitTys;
165   computeValueLLTs(*DL, *Val.getType(), SplitTys,
166                    Offsets->empty() ? Offsets : nullptr);
167   for (unsigned i = 0; i < SplitTys.size(); ++i)
168     Regs->push_back(0);
169   return *Regs;
170 }
171 
172 ArrayRef<Register> IRTranslator::getOrCreateVRegs(const Value &Val) {
173   auto VRegsIt = VMap.findVRegs(Val);
174   if (VRegsIt != VMap.vregs_end())
175     return *VRegsIt->second;
176 
177   if (Val.getType()->isVoidTy())
178     return *VMap.getVRegs(Val);
179 
180   // Create entry for this type.
181   auto *VRegs = VMap.getVRegs(Val);
182   auto *Offsets = VMap.getOffsets(Val);
183 
184   assert(Val.getType()->isSized() &&
185          "Don't know how to create an empty vreg");
186 
187   SmallVector<LLT, 4> SplitTys;
188   computeValueLLTs(*DL, *Val.getType(), SplitTys,
189                    Offsets->empty() ? Offsets : nullptr);
190 
191   if (!isa<Constant>(Val)) {
192     for (auto Ty : SplitTys)
193       VRegs->push_back(MRI->createGenericVirtualRegister(Ty));
194     return *VRegs;
195   }
196 
197   if (Val.getType()->isAggregateType()) {
198     // UndefValue, ConstantAggregateZero
199     auto &C = cast<Constant>(Val);
200     unsigned Idx = 0;
201     while (auto Elt = C.getAggregateElement(Idx++)) {
202       auto EltRegs = getOrCreateVRegs(*Elt);
203       llvm::copy(EltRegs, std::back_inserter(*VRegs));
204     }
205   } else {
206     assert(SplitTys.size() == 1 && "unexpectedly split LLT");
207     VRegs->push_back(MRI->createGenericVirtualRegister(SplitTys[0]));
208     bool Success = translate(cast<Constant>(Val), VRegs->front());
209     if (!Success) {
210       OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
211                                  MF->getFunction().getSubprogram(),
212                                  &MF->getFunction().getEntryBlock());
213       R << "unable to translate constant: " << ore::NV("Type", Val.getType());
214       reportTranslationError(*MF, *TPC, *ORE, R);
215       return *VRegs;
216     }
217   }
218 
219   return *VRegs;
220 }
221 
222 int IRTranslator::getOrCreateFrameIndex(const AllocaInst &AI) {
223   if (FrameIndices.find(&AI) != FrameIndices.end())
224     return FrameIndices[&AI];
225 
226   unsigned ElementSize = DL->getTypeAllocSize(AI.getAllocatedType());
227   unsigned Size =
228       ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
229 
230   // Always allocate at least one byte.
231   Size = std::max(Size, 1u);
232 
233   unsigned Alignment = AI.getAlignment();
234   if (!Alignment)
235     Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
236 
237   int &FI = FrameIndices[&AI];
238   FI = MF->getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
239   return FI;
240 }
241 
242 unsigned IRTranslator::getMemOpAlignment(const Instruction &I) {
243   unsigned Alignment = 0;
244   Type *ValTy = nullptr;
245   if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) {
246     Alignment = SI->getAlignment();
247     ValTy = SI->getValueOperand()->getType();
248   } else if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) {
249     Alignment = LI->getAlignment();
250     ValTy = LI->getType();
251   } else if (const AtomicCmpXchgInst *AI = dyn_cast<AtomicCmpXchgInst>(&I)) {
252     // TODO(PR27168): This instruction has no alignment attribute, but unlike
253     // the default alignment for load/store, the default here is to assume
254     // it has NATURAL alignment, not DataLayout-specified alignment.
255     const DataLayout &DL = AI->getModule()->getDataLayout();
256     Alignment = DL.getTypeStoreSize(AI->getCompareOperand()->getType());
257     ValTy = AI->getCompareOperand()->getType();
258   } else if (const AtomicRMWInst *AI = dyn_cast<AtomicRMWInst>(&I)) {
259     // TODO(PR27168): This instruction has no alignment attribute, but unlike
260     // the default alignment for load/store, the default here is to assume
261     // it has NATURAL alignment, not DataLayout-specified alignment.
262     const DataLayout &DL = AI->getModule()->getDataLayout();
263     Alignment = DL.getTypeStoreSize(AI->getValOperand()->getType());
264     ValTy = AI->getType();
265   } else {
266     OptimizationRemarkMissed R("gisel-irtranslator", "", &I);
267     R << "unable to translate memop: " << ore::NV("Opcode", &I);
268     reportTranslationError(*MF, *TPC, *ORE, R);
269     return 1;
270   }
271 
272   return Alignment ? Alignment : DL->getABITypeAlignment(ValTy);
273 }
274 
275 MachineBasicBlock &IRTranslator::getMBB(const BasicBlock &BB) {
276   MachineBasicBlock *&MBB = BBToMBB[&BB];
277   assert(MBB && "BasicBlock was not encountered before");
278   return *MBB;
279 }
280 
281 void IRTranslator::addMachineCFGPred(CFGEdge Edge, MachineBasicBlock *NewPred) {
282   assert(NewPred && "new predecessor must be a real MachineBasicBlock");
283   MachinePreds[Edge].push_back(NewPred);
284 }
285 
286 bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U,
287                                      MachineIRBuilder &MIRBuilder) {
288   // Get or create a virtual register for each value.
289   // Unless the value is a Constant => loadimm cst?
290   // or inline constant each time?
291   // Creation of a virtual register needs to have a size.
292   Register Op0 = getOrCreateVReg(*U.getOperand(0));
293   Register Op1 = getOrCreateVReg(*U.getOperand(1));
294   Register Res = getOrCreateVReg(U);
295   uint16_t Flags = 0;
296   if (isa<Instruction>(U)) {
297     const Instruction &I = cast<Instruction>(U);
298     Flags = MachineInstr::copyFlagsFromInstruction(I);
299   }
300 
301   MIRBuilder.buildInstr(Opcode, {Res}, {Op0, Op1}, Flags);
302   return true;
303 }
304 
305 bool IRTranslator::translateFSub(const User &U, MachineIRBuilder &MIRBuilder) {
306   // -0.0 - X --> G_FNEG
307   if (isa<Constant>(U.getOperand(0)) &&
308       U.getOperand(0) == ConstantFP::getZeroValueForNegation(U.getType())) {
309     Register Op1 = getOrCreateVReg(*U.getOperand(1));
310     Register Res = getOrCreateVReg(U);
311     uint16_t Flags = 0;
312     if (isa<Instruction>(U)) {
313       const Instruction &I = cast<Instruction>(U);
314       Flags = MachineInstr::copyFlagsFromInstruction(I);
315     }
316     // Negate the last operand of the FSUB
317     MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op1}, Flags);
318     return true;
319   }
320   return translateBinaryOp(TargetOpcode::G_FSUB, U, MIRBuilder);
321 }
322 
323 bool IRTranslator::translateFNeg(const User &U, MachineIRBuilder &MIRBuilder) {
324   Register Op0 = getOrCreateVReg(*U.getOperand(0));
325   Register Res = getOrCreateVReg(U);
326   uint16_t Flags = 0;
327   if (isa<Instruction>(U)) {
328     const Instruction &I = cast<Instruction>(U);
329     Flags = MachineInstr::copyFlagsFromInstruction(I);
330   }
331   MIRBuilder.buildInstr(TargetOpcode::G_FNEG, {Res}, {Op0}, Flags);
332   return true;
333 }
334 
335 bool IRTranslator::translateCompare(const User &U,
336                                     MachineIRBuilder &MIRBuilder) {
337   const CmpInst *CI = dyn_cast<CmpInst>(&U);
338   Register Op0 = getOrCreateVReg(*U.getOperand(0));
339   Register Op1 = getOrCreateVReg(*U.getOperand(1));
340   Register Res = getOrCreateVReg(U);
341   CmpInst::Predicate Pred =
342       CI ? CI->getPredicate() : static_cast<CmpInst::Predicate>(
343                                     cast<ConstantExpr>(U).getPredicate());
344   if (CmpInst::isIntPredicate(Pred))
345     MIRBuilder.buildICmp(Pred, Res, Op0, Op1);
346   else if (Pred == CmpInst::FCMP_FALSE)
347     MIRBuilder.buildCopy(
348         Res, getOrCreateVReg(*Constant::getNullValue(CI->getType())));
349   else if (Pred == CmpInst::FCMP_TRUE)
350     MIRBuilder.buildCopy(
351         Res, getOrCreateVReg(*Constant::getAllOnesValue(CI->getType())));
352   else {
353     MIRBuilder.buildInstr(TargetOpcode::G_FCMP, {Res}, {Pred, Op0, Op1},
354                           MachineInstr::copyFlagsFromInstruction(*CI));
355   }
356 
357   return true;
358 }
359 
360 bool IRTranslator::translateRet(const User &U, MachineIRBuilder &MIRBuilder) {
361   const ReturnInst &RI = cast<ReturnInst>(U);
362   const Value *Ret = RI.getReturnValue();
363   if (Ret && DL->getTypeStoreSize(Ret->getType()) == 0)
364     Ret = nullptr;
365 
366   ArrayRef<Register> VRegs;
367   if (Ret)
368     VRegs = getOrCreateVRegs(*Ret);
369 
370   Register SwiftErrorVReg = 0;
371   if (CLI->supportSwiftError() && SwiftError.getFunctionArg()) {
372     SwiftErrorVReg = SwiftError.getOrCreateVRegUseAt(
373         &RI, &MIRBuilder.getMBB(), SwiftError.getFunctionArg());
374   }
375 
376   // The target may mess up with the insertion point, but
377   // this is not important as a return is the last instruction
378   // of the block anyway.
379   return CLI->lowerReturn(MIRBuilder, Ret, VRegs, SwiftErrorVReg);
380 }
381 
382 bool IRTranslator::translateBr(const User &U, MachineIRBuilder &MIRBuilder) {
383   const BranchInst &BrInst = cast<BranchInst>(U);
384   unsigned Succ = 0;
385   if (!BrInst.isUnconditional()) {
386     // We want a G_BRCOND to the true BB followed by an unconditional branch.
387     Register Tst = getOrCreateVReg(*BrInst.getCondition());
388     const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
389     MachineBasicBlock &TrueBB = getMBB(TrueTgt);
390     MIRBuilder.buildBrCond(Tst, TrueBB);
391   }
392 
393   const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
394   MachineBasicBlock &TgtBB = getMBB(BrTgt);
395   MachineBasicBlock &CurBB = MIRBuilder.getMBB();
396 
397   // If the unconditional target is the layout successor, fallthrough.
398   if (!CurBB.isLayoutSuccessor(&TgtBB))
399     MIRBuilder.buildBr(TgtBB);
400 
401   // Link successors.
402   for (const BasicBlock *Succ : successors(&BrInst))
403     CurBB.addSuccessor(&getMBB(*Succ));
404   return true;
405 }
406 
407 void IRTranslator::addSuccessorWithProb(MachineBasicBlock *Src,
408                                         MachineBasicBlock *Dst,
409                                         BranchProbability Prob) {
410   if (!FuncInfo.BPI) {
411     Src->addSuccessorWithoutProb(Dst);
412     return;
413   }
414   if (Prob.isUnknown())
415     Prob = getEdgeProbability(Src, Dst);
416   Src->addSuccessor(Dst, Prob);
417 }
418 
419 BranchProbability
420 IRTranslator::getEdgeProbability(const MachineBasicBlock *Src,
421                                  const MachineBasicBlock *Dst) const {
422   const BasicBlock *SrcBB = Src->getBasicBlock();
423   const BasicBlock *DstBB = Dst->getBasicBlock();
424   if (!FuncInfo.BPI) {
425     // If BPI is not available, set the default probability as 1 / N, where N is
426     // the number of successors.
427     auto SuccSize = std::max<uint32_t>(succ_size(SrcBB), 1);
428     return BranchProbability(1, SuccSize);
429   }
430   return FuncInfo.BPI->getEdgeProbability(SrcBB, DstBB);
431 }
432 
433 bool IRTranslator::translateSwitch(const User &U, MachineIRBuilder &MIB) {
434   using namespace SwitchCG;
435   // Extract cases from the switch.
436   const SwitchInst &SI = cast<SwitchInst>(U);
437   BranchProbabilityInfo *BPI = FuncInfo.BPI;
438   CaseClusterVector Clusters;
439   Clusters.reserve(SI.getNumCases());
440   for (auto &I : SI.cases()) {
441     MachineBasicBlock *Succ = &getMBB(*I.getCaseSuccessor());
442     assert(Succ && "Could not find successor mbb in mapping");
443     const ConstantInt *CaseVal = I.getCaseValue();
444     BranchProbability Prob =
445         BPI ? BPI->getEdgeProbability(SI.getParent(), I.getSuccessorIndex())
446             : BranchProbability(1, SI.getNumCases() + 1);
447     Clusters.push_back(CaseCluster::range(CaseVal, CaseVal, Succ, Prob));
448   }
449 
450   MachineBasicBlock *DefaultMBB = &getMBB(*SI.getDefaultDest());
451 
452   // Cluster adjacent cases with the same destination. We do this at all
453   // optimization levels because it's cheap to do and will make codegen faster
454   // if there are many clusters.
455   sortAndRangeify(Clusters);
456 
457   MachineBasicBlock *SwitchMBB = &getMBB(*SI.getParent());
458 
459   // If there is only the default destination, jump there directly.
460   if (Clusters.empty()) {
461     SwitchMBB->addSuccessor(DefaultMBB);
462     if (DefaultMBB != SwitchMBB->getNextNode())
463       MIB.buildBr(*DefaultMBB);
464     return true;
465   }
466 
467   SL->findJumpTables(Clusters, &SI, DefaultMBB);
468 
469   LLVM_DEBUG({
470     dbgs() << "Case clusters: ";
471     for (const CaseCluster &C : Clusters) {
472       if (C.Kind == CC_JumpTable)
473         dbgs() << "JT:";
474       if (C.Kind == CC_BitTests)
475         dbgs() << "BT:";
476 
477       C.Low->getValue().print(dbgs(), true);
478       if (C.Low != C.High) {
479         dbgs() << '-';
480         C.High->getValue().print(dbgs(), true);
481       }
482       dbgs() << ' ';
483     }
484     dbgs() << '\n';
485   });
486 
487   assert(!Clusters.empty());
488   SwitchWorkList WorkList;
489   CaseClusterIt First = Clusters.begin();
490   CaseClusterIt Last = Clusters.end() - 1;
491   auto DefaultProb = getEdgeProbability(SwitchMBB, DefaultMBB);
492   WorkList.push_back({SwitchMBB, First, Last, nullptr, nullptr, DefaultProb});
493 
494   // FIXME: At the moment we don't do any splitting optimizations here like
495   // SelectionDAG does, so this worklist only has one entry.
496   while (!WorkList.empty()) {
497     SwitchWorkListItem W = WorkList.back();
498     WorkList.pop_back();
499     if (!lowerSwitchWorkItem(W, SI.getCondition(), SwitchMBB, DefaultMBB, MIB))
500       return false;
501   }
502   return true;
503 }
504 
505 void IRTranslator::emitJumpTable(SwitchCG::JumpTable &JT,
506                                  MachineBasicBlock *MBB) {
507   // Emit the code for the jump table
508   assert(JT.Reg != -1U && "Should lower JT Header first!");
509   MachineIRBuilder MIB(*MBB->getParent());
510   MIB.setMBB(*MBB);
511   MIB.setDebugLoc(CurBuilder->getDebugLoc());
512 
513   Type *PtrIRTy = Type::getInt8PtrTy(MF->getFunction().getContext());
514   const LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
515 
516   auto Table = MIB.buildJumpTable(PtrTy, JT.JTI);
517   MIB.buildBrJT(Table.getReg(0), JT.JTI, JT.Reg);
518 }
519 
520 bool IRTranslator::emitJumpTableHeader(SwitchCG::JumpTable &JT,
521                                        SwitchCG::JumpTableHeader &JTH,
522                                        MachineBasicBlock *HeaderBB) {
523   MachineIRBuilder MIB(*HeaderBB->getParent());
524   MIB.setMBB(*HeaderBB);
525   MIB.setDebugLoc(CurBuilder->getDebugLoc());
526 
527   const Value &SValue = *JTH.SValue;
528   // Subtract the lowest switch case value from the value being switched on.
529   const LLT SwitchTy = getLLTForType(*SValue.getType(), *DL);
530   Register SwitchOpReg = getOrCreateVReg(SValue);
531   auto FirstCst = MIB.buildConstant(SwitchTy, JTH.First);
532   auto Sub = MIB.buildSub({SwitchTy}, SwitchOpReg, FirstCst);
533 
534   // This value may be smaller or larger than the target's pointer type, and
535   // therefore require extension or truncating.
536   Type *PtrIRTy = SValue.getType()->getPointerTo();
537   const LLT PtrScalarTy = LLT::scalar(DL->getTypeSizeInBits(PtrIRTy));
538   Sub = MIB.buildZExtOrTrunc(PtrScalarTy, Sub);
539 
540   JT.Reg = Sub.getReg(0);
541 
542   if (JTH.OmitRangeCheck) {
543     if (JT.MBB != HeaderBB->getNextNode())
544       MIB.buildBr(*JT.MBB);
545     return true;
546   }
547 
548   // Emit the range check for the jump table, and branch to the default block
549   // for the switch statement if the value being switched on exceeds the
550   // largest case in the switch.
551   auto Cst = getOrCreateVReg(
552       *ConstantInt::get(SValue.getType(), JTH.Last - JTH.First));
553   Cst = MIB.buildZExtOrTrunc(PtrScalarTy, Cst).getReg(0);
554   auto Cmp = MIB.buildICmp(CmpInst::ICMP_UGT, LLT::scalar(1), Sub, Cst);
555 
556   auto BrCond = MIB.buildBrCond(Cmp.getReg(0), *JT.Default);
557 
558   // Avoid emitting unnecessary branches to the next block.
559   if (JT.MBB != HeaderBB->getNextNode())
560     BrCond = MIB.buildBr(*JT.MBB);
561   return true;
562 }
563 
564 void IRTranslator::emitSwitchCase(SwitchCG::CaseBlock &CB,
565                                   MachineBasicBlock *SwitchBB,
566                                   MachineIRBuilder &MIB) {
567   Register CondLHS = getOrCreateVReg(*CB.CmpLHS);
568   Register Cond;
569   DebugLoc OldDbgLoc = MIB.getDebugLoc();
570   MIB.setDebugLoc(CB.DbgLoc);
571   MIB.setMBB(*CB.ThisBB);
572 
573   if (CB.PredInfo.NoCmp) {
574     // Branch or fall through to TrueBB.
575     addSuccessorWithProb(CB.ThisBB, CB.TrueBB, CB.TrueProb);
576     addMachineCFGPred({SwitchBB->getBasicBlock(), CB.TrueBB->getBasicBlock()},
577                       CB.ThisBB);
578     CB.ThisBB->normalizeSuccProbs();
579     if (CB.TrueBB != CB.ThisBB->getNextNode())
580       MIB.buildBr(*CB.TrueBB);
581     MIB.setDebugLoc(OldDbgLoc);
582     return;
583   }
584 
585   const LLT i1Ty = LLT::scalar(1);
586   // Build the compare.
587   if (!CB.CmpMHS) {
588     Register CondRHS = getOrCreateVReg(*CB.CmpRHS);
589     Cond = MIB.buildICmp(CB.PredInfo.Pred, i1Ty, CondLHS, CondRHS).getReg(0);
590   } else {
591     assert(CB.PredInfo.Pred == CmpInst::ICMP_ULE &&
592            "Can only handle ULE ranges");
593 
594     const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue();
595     const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
596 
597     Register CmpOpReg = getOrCreateVReg(*CB.CmpMHS);
598     if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
599       Register CondRHS = getOrCreateVReg(*CB.CmpRHS);
600       Cond =
601           MIB.buildICmp(CmpInst::ICMP_ULE, i1Ty, CmpOpReg, CondRHS).getReg(0);
602     } else {
603       const LLT &CmpTy = MRI->getType(CmpOpReg);
604       auto Sub = MIB.buildSub({CmpTy}, CmpOpReg, CondLHS);
605       auto Diff = MIB.buildConstant(CmpTy, High - Low);
606       Cond = MIB.buildICmp(CmpInst::ICMP_ULE, i1Ty, Sub, Diff).getReg(0);
607     }
608   }
609 
610   // Update successor info
611   addSuccessorWithProb(CB.ThisBB, CB.TrueBB, CB.TrueProb);
612 
613   addMachineCFGPred({SwitchBB->getBasicBlock(), CB.TrueBB->getBasicBlock()},
614                     CB.ThisBB);
615 
616   // TrueBB and FalseBB are always different unless the incoming IR is
617   // degenerate. This only happens when running llc on weird IR.
618   if (CB.TrueBB != CB.FalseBB)
619     addSuccessorWithProb(CB.ThisBB, CB.FalseBB, CB.FalseProb);
620   CB.ThisBB->normalizeSuccProbs();
621 
622   //  if (SwitchBB->getBasicBlock() != CB.FalseBB->getBasicBlock())
623     addMachineCFGPred({SwitchBB->getBasicBlock(), CB.FalseBB->getBasicBlock()},
624                       CB.ThisBB);
625 
626   // If the lhs block is the next block, invert the condition so that we can
627   // fall through to the lhs instead of the rhs block.
628   if (CB.TrueBB == CB.ThisBB->getNextNode()) {
629     std::swap(CB.TrueBB, CB.FalseBB);
630     auto True = MIB.buildConstant(i1Ty, 1);
631     Cond = MIB.buildInstr(TargetOpcode::G_XOR, {i1Ty}, {Cond, True}, None)
632                .getReg(0);
633   }
634 
635   MIB.buildBrCond(Cond, *CB.TrueBB);
636   MIB.buildBr(*CB.FalseBB);
637   MIB.setDebugLoc(OldDbgLoc);
638 }
639 
640 bool IRTranslator::lowerJumpTableWorkItem(SwitchCG::SwitchWorkListItem W,
641                                           MachineBasicBlock *SwitchMBB,
642                                           MachineBasicBlock *CurMBB,
643                                           MachineBasicBlock *DefaultMBB,
644                                           MachineIRBuilder &MIB,
645                                           MachineFunction::iterator BBI,
646                                           BranchProbability UnhandledProbs,
647                                           SwitchCG::CaseClusterIt I,
648                                           MachineBasicBlock *Fallthrough,
649                                           bool FallthroughUnreachable) {
650   using namespace SwitchCG;
651   MachineFunction *CurMF = SwitchMBB->getParent();
652   // FIXME: Optimize away range check based on pivot comparisons.
653   JumpTableHeader *JTH = &SL->JTCases[I->JTCasesIndex].first;
654   SwitchCG::JumpTable *JT = &SL->JTCases[I->JTCasesIndex].second;
655   BranchProbability DefaultProb = W.DefaultProb;
656 
657   // The jump block hasn't been inserted yet; insert it here.
658   MachineBasicBlock *JumpMBB = JT->MBB;
659   CurMF->insert(BBI, JumpMBB);
660 
661   // Since the jump table block is separate from the switch block, we need
662   // to keep track of it as a machine predecessor to the default block,
663   // otherwise we lose the phi edges.
664   addMachineCFGPred({SwitchMBB->getBasicBlock(), DefaultMBB->getBasicBlock()},
665                     CurMBB);
666   addMachineCFGPred({SwitchMBB->getBasicBlock(), DefaultMBB->getBasicBlock()},
667                     JumpMBB);
668 
669   auto JumpProb = I->Prob;
670   auto FallthroughProb = UnhandledProbs;
671 
672   // If the default statement is a target of the jump table, we evenly
673   // distribute the default probability to successors of CurMBB. Also
674   // update the probability on the edge from JumpMBB to Fallthrough.
675   for (MachineBasicBlock::succ_iterator SI = JumpMBB->succ_begin(),
676                                         SE = JumpMBB->succ_end();
677        SI != SE; ++SI) {
678     if (*SI == DefaultMBB) {
679       JumpProb += DefaultProb / 2;
680       FallthroughProb -= DefaultProb / 2;
681       JumpMBB->setSuccProbability(SI, DefaultProb / 2);
682       JumpMBB->normalizeSuccProbs();
683     } else {
684       // Also record edges from the jump table block to it's successors.
685       addMachineCFGPred({SwitchMBB->getBasicBlock(), (*SI)->getBasicBlock()},
686                         JumpMBB);
687     }
688   }
689 
690   // Skip the range check if the fallthrough block is unreachable.
691   if (FallthroughUnreachable)
692     JTH->OmitRangeCheck = true;
693 
694   if (!JTH->OmitRangeCheck)
695     addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);
696   addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);
697   CurMBB->normalizeSuccProbs();
698 
699   // The jump table header will be inserted in our current block, do the
700   // range check, and fall through to our fallthrough block.
701   JTH->HeaderBB = CurMBB;
702   JT->Default = Fallthrough; // FIXME: Move Default to JumpTableHeader.
703 
704   // If we're in the right place, emit the jump table header right now.
705   if (CurMBB == SwitchMBB) {
706     if (!emitJumpTableHeader(*JT, *JTH, CurMBB))
707       return false;
708     JTH->Emitted = true;
709   }
710   return true;
711 }
712 bool IRTranslator::lowerSwitchRangeWorkItem(SwitchCG::CaseClusterIt I,
713                                             Value *Cond,
714                                             MachineBasicBlock *Fallthrough,
715                                             bool FallthroughUnreachable,
716                                             BranchProbability UnhandledProbs,
717                                             MachineBasicBlock *CurMBB,
718                                             MachineIRBuilder &MIB,
719                                             MachineBasicBlock *SwitchMBB) {
720   using namespace SwitchCG;
721   const Value *RHS, *LHS, *MHS;
722   CmpInst::Predicate Pred;
723   if (I->Low == I->High) {
724     // Check Cond == I->Low.
725     Pred = CmpInst::ICMP_EQ;
726     LHS = Cond;
727     RHS = I->Low;
728     MHS = nullptr;
729   } else {
730     // Check I->Low <= Cond <= I->High.
731     Pred = CmpInst::ICMP_ULE;
732     LHS = I->Low;
733     MHS = Cond;
734     RHS = I->High;
735   }
736 
737   // If Fallthrough is unreachable, fold away the comparison.
738   // The false probability is the sum of all unhandled cases.
739   CaseBlock CB(Pred, FallthroughUnreachable, LHS, RHS, MHS, I->MBB, Fallthrough,
740                CurMBB, MIB.getDebugLoc(), I->Prob, UnhandledProbs);
741 
742   emitSwitchCase(CB, SwitchMBB, MIB);
743   return true;
744 }
745 
746 bool IRTranslator::lowerSwitchWorkItem(SwitchCG::SwitchWorkListItem W,
747                                        Value *Cond,
748                                        MachineBasicBlock *SwitchMBB,
749                                        MachineBasicBlock *DefaultMBB,
750                                        MachineIRBuilder &MIB) {
751   using namespace SwitchCG;
752   MachineFunction *CurMF = FuncInfo.MF;
753   MachineBasicBlock *NextMBB = nullptr;
754   MachineFunction::iterator BBI(W.MBB);
755   if (++BBI != FuncInfo.MF->end())
756     NextMBB = &*BBI;
757 
758   if (EnableOpts) {
759     // Here, we order cases by probability so the most likely case will be
760     // checked first. However, two clusters can have the same probability in
761     // which case their relative ordering is non-deterministic. So we use Low
762     // as a tie-breaker as clusters are guaranteed to never overlap.
763     llvm::sort(W.FirstCluster, W.LastCluster + 1,
764                [](const CaseCluster &a, const CaseCluster &b) {
765                  return a.Prob != b.Prob
766                             ? a.Prob > b.Prob
767                             : a.Low->getValue().slt(b.Low->getValue());
768                });
769 
770     // Rearrange the case blocks so that the last one falls through if possible
771     // without changing the order of probabilities.
772     for (CaseClusterIt I = W.LastCluster; I > W.FirstCluster;) {
773       --I;
774       if (I->Prob > W.LastCluster->Prob)
775         break;
776       if (I->Kind == CC_Range && I->MBB == NextMBB) {
777         std::swap(*I, *W.LastCluster);
778         break;
779       }
780     }
781   }
782 
783   // Compute total probability.
784   BranchProbability DefaultProb = W.DefaultProb;
785   BranchProbability UnhandledProbs = DefaultProb;
786   for (CaseClusterIt I = W.FirstCluster; I <= W.LastCluster; ++I)
787     UnhandledProbs += I->Prob;
788 
789   MachineBasicBlock *CurMBB = W.MBB;
790   for (CaseClusterIt I = W.FirstCluster, E = W.LastCluster; I <= E; ++I) {
791     bool FallthroughUnreachable = false;
792     MachineBasicBlock *Fallthrough;
793     if (I == W.LastCluster) {
794       // For the last cluster, fall through to the default destination.
795       Fallthrough = DefaultMBB;
796       FallthroughUnreachable = isa<UnreachableInst>(
797           DefaultMBB->getBasicBlock()->getFirstNonPHIOrDbg());
798     } else {
799       Fallthrough = CurMF->CreateMachineBasicBlock(CurMBB->getBasicBlock());
800       CurMF->insert(BBI, Fallthrough);
801     }
802     UnhandledProbs -= I->Prob;
803 
804     switch (I->Kind) {
805     case CC_BitTests: {
806       LLVM_DEBUG(dbgs() << "Switch to bit test optimization unimplemented");
807       return false; // Bit tests currently unimplemented.
808     }
809     case CC_JumpTable: {
810       if (!lowerJumpTableWorkItem(W, SwitchMBB, CurMBB, DefaultMBB, MIB, BBI,
811                                   UnhandledProbs, I, Fallthrough,
812                                   FallthroughUnreachable)) {
813         LLVM_DEBUG(dbgs() << "Failed to lower jump table");
814         return false;
815       }
816       break;
817     }
818     case CC_Range: {
819       if (!lowerSwitchRangeWorkItem(I, Cond, Fallthrough,
820                                     FallthroughUnreachable, UnhandledProbs,
821                                     CurMBB, MIB, SwitchMBB)) {
822         LLVM_DEBUG(dbgs() << "Failed to lower switch range");
823         return false;
824       }
825       break;
826     }
827     }
828     CurMBB = Fallthrough;
829   }
830 
831   return true;
832 }
833 
834 bool IRTranslator::translateIndirectBr(const User &U,
835                                        MachineIRBuilder &MIRBuilder) {
836   const IndirectBrInst &BrInst = cast<IndirectBrInst>(U);
837 
838   const Register Tgt = getOrCreateVReg(*BrInst.getAddress());
839   MIRBuilder.buildBrIndirect(Tgt);
840 
841   // Link successors.
842   MachineBasicBlock &CurBB = MIRBuilder.getMBB();
843   for (const BasicBlock *Succ : successors(&BrInst))
844     CurBB.addSuccessor(&getMBB(*Succ));
845 
846   return true;
847 }
848 
849 static bool isSwiftError(const Value *V) {
850   if (auto Arg = dyn_cast<Argument>(V))
851     return Arg->hasSwiftErrorAttr();
852   if (auto AI = dyn_cast<AllocaInst>(V))
853     return AI->isSwiftError();
854   return false;
855 }
856 
857 bool IRTranslator::translateLoad(const User &U, MachineIRBuilder &MIRBuilder) {
858   const LoadInst &LI = cast<LoadInst>(U);
859 
860   auto Flags = LI.isVolatile() ? MachineMemOperand::MOVolatile
861                                : MachineMemOperand::MONone;
862   Flags |= MachineMemOperand::MOLoad;
863 
864   if (DL->getTypeStoreSize(LI.getType()) == 0)
865     return true;
866 
867   ArrayRef<Register> Regs = getOrCreateVRegs(LI);
868   ArrayRef<uint64_t> Offsets = *VMap.getOffsets(LI);
869   Register Base = getOrCreateVReg(*LI.getPointerOperand());
870 
871   Type *OffsetIRTy = DL->getIntPtrType(LI.getPointerOperandType());
872   LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
873 
874   if (CLI->supportSwiftError() && isSwiftError(LI.getPointerOperand())) {
875     assert(Regs.size() == 1 && "swifterror should be single pointer");
876     Register VReg = SwiftError.getOrCreateVRegUseAt(&LI, &MIRBuilder.getMBB(),
877                                                     LI.getPointerOperand());
878     MIRBuilder.buildCopy(Regs[0], VReg);
879     return true;
880   }
881 
882   const MDNode *Ranges =
883       Regs.size() == 1 ? LI.getMetadata(LLVMContext::MD_range) : nullptr;
884   for (unsigned i = 0; i < Regs.size(); ++i) {
885     Register Addr;
886     MIRBuilder.materializeGEP(Addr, Base, OffsetTy, Offsets[i] / 8);
887 
888     MachinePointerInfo Ptr(LI.getPointerOperand(), Offsets[i] / 8);
889     unsigned BaseAlign = getMemOpAlignment(LI);
890     auto MMO = MF->getMachineMemOperand(
891         Ptr, Flags, (MRI->getType(Regs[i]).getSizeInBits() + 7) / 8,
892         MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), Ranges,
893         LI.getSyncScopeID(), LI.getOrdering());
894     MIRBuilder.buildLoad(Regs[i], Addr, *MMO);
895   }
896 
897   return true;
898 }
899 
900 bool IRTranslator::translateStore(const User &U, MachineIRBuilder &MIRBuilder) {
901   const StoreInst &SI = cast<StoreInst>(U);
902   auto Flags = SI.isVolatile() ? MachineMemOperand::MOVolatile
903                                : MachineMemOperand::MONone;
904   Flags |= MachineMemOperand::MOStore;
905 
906   if (DL->getTypeStoreSize(SI.getValueOperand()->getType()) == 0)
907     return true;
908 
909   ArrayRef<Register> Vals = getOrCreateVRegs(*SI.getValueOperand());
910   ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*SI.getValueOperand());
911   Register Base = getOrCreateVReg(*SI.getPointerOperand());
912 
913   Type *OffsetIRTy = DL->getIntPtrType(SI.getPointerOperandType());
914   LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
915 
916   if (CLI->supportSwiftError() && isSwiftError(SI.getPointerOperand())) {
917     assert(Vals.size() == 1 && "swifterror should be single pointer");
918 
919     Register VReg = SwiftError.getOrCreateVRegDefAt(&SI, &MIRBuilder.getMBB(),
920                                                     SI.getPointerOperand());
921     MIRBuilder.buildCopy(VReg, Vals[0]);
922     return true;
923   }
924 
925   for (unsigned i = 0; i < Vals.size(); ++i) {
926     Register Addr;
927     MIRBuilder.materializeGEP(Addr, Base, OffsetTy, Offsets[i] / 8);
928 
929     MachinePointerInfo Ptr(SI.getPointerOperand(), Offsets[i] / 8);
930     unsigned BaseAlign = getMemOpAlignment(SI);
931     auto MMO = MF->getMachineMemOperand(
932         Ptr, Flags, (MRI->getType(Vals[i]).getSizeInBits() + 7) / 8,
933         MinAlign(BaseAlign, Offsets[i] / 8), AAMDNodes(), nullptr,
934         SI.getSyncScopeID(), SI.getOrdering());
935     MIRBuilder.buildStore(Vals[i], Addr, *MMO);
936   }
937   return true;
938 }
939 
940 static uint64_t getOffsetFromIndices(const User &U, const DataLayout &DL) {
941   const Value *Src = U.getOperand(0);
942   Type *Int32Ty = Type::getInt32Ty(U.getContext());
943 
944   // getIndexedOffsetInType is designed for GEPs, so the first index is the
945   // usual array element rather than looking into the actual aggregate.
946   SmallVector<Value *, 1> Indices;
947   Indices.push_back(ConstantInt::get(Int32Ty, 0));
948 
949   if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&U)) {
950     for (auto Idx : EVI->indices())
951       Indices.push_back(ConstantInt::get(Int32Ty, Idx));
952   } else if (const InsertValueInst *IVI = dyn_cast<InsertValueInst>(&U)) {
953     for (auto Idx : IVI->indices())
954       Indices.push_back(ConstantInt::get(Int32Ty, Idx));
955   } else {
956     for (unsigned i = 1; i < U.getNumOperands(); ++i)
957       Indices.push_back(U.getOperand(i));
958   }
959 
960   return 8 * static_cast<uint64_t>(
961                  DL.getIndexedOffsetInType(Src->getType(), Indices));
962 }
963 
964 bool IRTranslator::translateExtractValue(const User &U,
965                                          MachineIRBuilder &MIRBuilder) {
966   const Value *Src = U.getOperand(0);
967   uint64_t Offset = getOffsetFromIndices(U, *DL);
968   ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src);
969   ArrayRef<uint64_t> Offsets = *VMap.getOffsets(*Src);
970   unsigned Idx = llvm::lower_bound(Offsets, Offset) - Offsets.begin();
971   auto &DstRegs = allocateVRegs(U);
972 
973   for (unsigned i = 0; i < DstRegs.size(); ++i)
974     DstRegs[i] = SrcRegs[Idx++];
975 
976   return true;
977 }
978 
979 bool IRTranslator::translateInsertValue(const User &U,
980                                         MachineIRBuilder &MIRBuilder) {
981   const Value *Src = U.getOperand(0);
982   uint64_t Offset = getOffsetFromIndices(U, *DL);
983   auto &DstRegs = allocateVRegs(U);
984   ArrayRef<uint64_t> DstOffsets = *VMap.getOffsets(U);
985   ArrayRef<Register> SrcRegs = getOrCreateVRegs(*Src);
986   ArrayRef<Register> InsertedRegs = getOrCreateVRegs(*U.getOperand(1));
987   auto InsertedIt = InsertedRegs.begin();
988 
989   for (unsigned i = 0; i < DstRegs.size(); ++i) {
990     if (DstOffsets[i] >= Offset && InsertedIt != InsertedRegs.end())
991       DstRegs[i] = *InsertedIt++;
992     else
993       DstRegs[i] = SrcRegs[i];
994   }
995 
996   return true;
997 }
998 
999 bool IRTranslator::translateSelect(const User &U,
1000                                    MachineIRBuilder &MIRBuilder) {
1001   Register Tst = getOrCreateVReg(*U.getOperand(0));
1002   ArrayRef<Register> ResRegs = getOrCreateVRegs(U);
1003   ArrayRef<Register> Op0Regs = getOrCreateVRegs(*U.getOperand(1));
1004   ArrayRef<Register> Op1Regs = getOrCreateVRegs(*U.getOperand(2));
1005 
1006   const SelectInst &SI = cast<SelectInst>(U);
1007   uint16_t Flags = 0;
1008   if (const CmpInst *Cmp = dyn_cast<CmpInst>(SI.getCondition()))
1009     Flags = MachineInstr::copyFlagsFromInstruction(*Cmp);
1010 
1011   for (unsigned i = 0; i < ResRegs.size(); ++i) {
1012     MIRBuilder.buildInstr(TargetOpcode::G_SELECT, {ResRegs[i]},
1013                           {Tst, Op0Regs[i], Op1Regs[i]}, Flags);
1014   }
1015 
1016   return true;
1017 }
1018 
1019 bool IRTranslator::translateBitCast(const User &U,
1020                                     MachineIRBuilder &MIRBuilder) {
1021   // If we're bitcasting to the source type, we can reuse the source vreg.
1022   if (getLLTForType(*U.getOperand(0)->getType(), *DL) ==
1023       getLLTForType(*U.getType(), *DL)) {
1024     Register SrcReg = getOrCreateVReg(*U.getOperand(0));
1025     auto &Regs = *VMap.getVRegs(U);
1026     // If we already assigned a vreg for this bitcast, we can't change that.
1027     // Emit a copy to satisfy the users we already emitted.
1028     if (!Regs.empty())
1029       MIRBuilder.buildCopy(Regs[0], SrcReg);
1030     else {
1031       Regs.push_back(SrcReg);
1032       VMap.getOffsets(U)->push_back(0);
1033     }
1034     return true;
1035   }
1036   return translateCast(TargetOpcode::G_BITCAST, U, MIRBuilder);
1037 }
1038 
1039 bool IRTranslator::translateCast(unsigned Opcode, const User &U,
1040                                  MachineIRBuilder &MIRBuilder) {
1041   Register Op = getOrCreateVReg(*U.getOperand(0));
1042   Register Res = getOrCreateVReg(U);
1043   MIRBuilder.buildInstr(Opcode, {Res}, {Op});
1044   return true;
1045 }
1046 
1047 bool IRTranslator::translateGetElementPtr(const User &U,
1048                                           MachineIRBuilder &MIRBuilder) {
1049   // FIXME: support vector GEPs.
1050   if (U.getType()->isVectorTy())
1051     return false;
1052 
1053   Value &Op0 = *U.getOperand(0);
1054   Register BaseReg = getOrCreateVReg(Op0);
1055   Type *PtrIRTy = Op0.getType();
1056   LLT PtrTy = getLLTForType(*PtrIRTy, *DL);
1057   Type *OffsetIRTy = DL->getIntPtrType(PtrIRTy);
1058   LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
1059 
1060   int64_t Offset = 0;
1061   for (gep_type_iterator GTI = gep_type_begin(&U), E = gep_type_end(&U);
1062        GTI != E; ++GTI) {
1063     const Value *Idx = GTI.getOperand();
1064     if (StructType *StTy = GTI.getStructTypeOrNull()) {
1065       unsigned Field = cast<Constant>(Idx)->getUniqueInteger().getZExtValue();
1066       Offset += DL->getStructLayout(StTy)->getElementOffset(Field);
1067       continue;
1068     } else {
1069       uint64_t ElementSize = DL->getTypeAllocSize(GTI.getIndexedType());
1070 
1071       // If this is a scalar constant or a splat vector of constants,
1072       // handle it quickly.
1073       if (const auto *CI = dyn_cast<ConstantInt>(Idx)) {
1074         Offset += ElementSize * CI->getSExtValue();
1075         continue;
1076       }
1077 
1078       if (Offset != 0) {
1079         Register NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
1080         LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
1081         auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset);
1082         MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetMIB.getReg(0));
1083 
1084         BaseReg = NewBaseReg;
1085         Offset = 0;
1086       }
1087 
1088       Register IdxReg = getOrCreateVReg(*Idx);
1089       if (MRI->getType(IdxReg) != OffsetTy) {
1090         Register NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
1091         MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
1092         IdxReg = NewIdxReg;
1093       }
1094 
1095       // N = N + Idx * ElementSize;
1096       // Avoid doing it for ElementSize of 1.
1097       Register GepOffsetReg;
1098       if (ElementSize != 1) {
1099         GepOffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
1100         auto ElementSizeMIB = MIRBuilder.buildConstant(
1101             getLLTForType(*OffsetIRTy, *DL), ElementSize);
1102         MIRBuilder.buildMul(GepOffsetReg, ElementSizeMIB.getReg(0), IdxReg);
1103       } else
1104         GepOffsetReg = IdxReg;
1105 
1106       Register NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
1107       MIRBuilder.buildGEP(NewBaseReg, BaseReg, GepOffsetReg);
1108       BaseReg = NewBaseReg;
1109     }
1110   }
1111 
1112   if (Offset != 0) {
1113     auto OffsetMIB =
1114         MIRBuilder.buildConstant(getLLTForType(*OffsetIRTy, *DL), Offset);
1115     MIRBuilder.buildGEP(getOrCreateVReg(U), BaseReg, OffsetMIB.getReg(0));
1116     return true;
1117   }
1118 
1119   MIRBuilder.buildCopy(getOrCreateVReg(U), BaseReg);
1120   return true;
1121 }
1122 
1123 bool IRTranslator::translateMemFunc(const CallInst &CI,
1124                                     MachineIRBuilder &MIRBuilder,
1125                                     Intrinsic::ID ID) {
1126 
1127   // If the source is undef, then just emit a nop.
1128   if (isa<UndefValue>(CI.getArgOperand(1)))
1129     return true;
1130 
1131   ArrayRef<Register> Res;
1132   auto ICall = MIRBuilder.buildIntrinsic(ID, Res, true);
1133   for (auto AI = CI.arg_begin(), AE = CI.arg_end(); std::next(AI) != AE; ++AI)
1134     ICall.addUse(getOrCreateVReg(**AI));
1135 
1136   unsigned DstAlign = 0, SrcAlign = 0;
1137   unsigned IsVol =
1138       cast<ConstantInt>(CI.getArgOperand(CI.getNumArgOperands() - 1))
1139           ->getZExtValue();
1140 
1141   if (auto *MCI = dyn_cast<MemCpyInst>(&CI)) {
1142     DstAlign = std::max<unsigned>(MCI->getDestAlignment(), 1);
1143     SrcAlign = std::max<unsigned>(MCI->getSourceAlignment(), 1);
1144   } else if (auto *MMI = dyn_cast<MemMoveInst>(&CI)) {
1145     DstAlign = std::max<unsigned>(MMI->getDestAlignment(), 1);
1146     SrcAlign = std::max<unsigned>(MMI->getSourceAlignment(), 1);
1147   } else {
1148     auto *MSI = cast<MemSetInst>(&CI);
1149     DstAlign = std::max<unsigned>(MSI->getDestAlignment(), 1);
1150   }
1151 
1152   // Create mem operands to store the alignment and volatile info.
1153   auto VolFlag = IsVol ? MachineMemOperand::MOVolatile : MachineMemOperand::MONone;
1154   ICall.addMemOperand(MF->getMachineMemOperand(
1155       MachinePointerInfo(CI.getArgOperand(0)),
1156       MachineMemOperand::MOStore | VolFlag, 1, DstAlign));
1157   if (ID != Intrinsic::memset)
1158     ICall.addMemOperand(MF->getMachineMemOperand(
1159         MachinePointerInfo(CI.getArgOperand(1)),
1160         MachineMemOperand::MOLoad | VolFlag, 1, SrcAlign));
1161 
1162   return true;
1163 }
1164 
1165 void IRTranslator::getStackGuard(Register DstReg,
1166                                  MachineIRBuilder &MIRBuilder) {
1167   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1168   MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF));
1169   auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
1170   MIB.addDef(DstReg);
1171 
1172   auto &TLI = *MF->getSubtarget().getTargetLowering();
1173   Value *Global = TLI.getSDagStackGuard(*MF->getFunction().getParent());
1174   if (!Global)
1175     return;
1176 
1177   MachinePointerInfo MPInfo(Global);
1178   auto Flags = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant |
1179                MachineMemOperand::MODereferenceable;
1180   MachineMemOperand *MemRef =
1181       MF->getMachineMemOperand(MPInfo, Flags, DL->getPointerSizeInBits() / 8,
1182                                DL->getPointerABIAlignment(0));
1183   MIB.setMemRefs({MemRef});
1184 }
1185 
1186 bool IRTranslator::translateOverflowIntrinsic(const CallInst &CI, unsigned Op,
1187                                               MachineIRBuilder &MIRBuilder) {
1188   ArrayRef<Register> ResRegs = getOrCreateVRegs(CI);
1189   MIRBuilder.buildInstr(Op)
1190       .addDef(ResRegs[0])
1191       .addDef(ResRegs[1])
1192       .addUse(getOrCreateVReg(*CI.getOperand(0)))
1193       .addUse(getOrCreateVReg(*CI.getOperand(1)));
1194 
1195   return true;
1196 }
1197 
1198 unsigned IRTranslator::getSimpleIntrinsicOpcode(Intrinsic::ID ID) {
1199   switch (ID) {
1200     default:
1201       break;
1202     case Intrinsic::bswap:
1203       return TargetOpcode::G_BSWAP;
1204     case Intrinsic::ceil:
1205       return TargetOpcode::G_FCEIL;
1206     case Intrinsic::cos:
1207       return TargetOpcode::G_FCOS;
1208     case Intrinsic::ctpop:
1209       return TargetOpcode::G_CTPOP;
1210     case Intrinsic::exp:
1211       return TargetOpcode::G_FEXP;
1212     case Intrinsic::exp2:
1213       return TargetOpcode::G_FEXP2;
1214     case Intrinsic::fabs:
1215       return TargetOpcode::G_FABS;
1216     case Intrinsic::copysign:
1217       return TargetOpcode::G_FCOPYSIGN;
1218     case Intrinsic::minnum:
1219       return TargetOpcode::G_FMINNUM;
1220     case Intrinsic::maxnum:
1221       return TargetOpcode::G_FMAXNUM;
1222     case Intrinsic::minimum:
1223       return TargetOpcode::G_FMINIMUM;
1224     case Intrinsic::maximum:
1225       return TargetOpcode::G_FMAXIMUM;
1226     case Intrinsic::canonicalize:
1227       return TargetOpcode::G_FCANONICALIZE;
1228     case Intrinsic::floor:
1229       return TargetOpcode::G_FFLOOR;
1230     case Intrinsic::fma:
1231       return TargetOpcode::G_FMA;
1232     case Intrinsic::log:
1233       return TargetOpcode::G_FLOG;
1234     case Intrinsic::log2:
1235       return TargetOpcode::G_FLOG2;
1236     case Intrinsic::log10:
1237       return TargetOpcode::G_FLOG10;
1238     case Intrinsic::nearbyint:
1239       return TargetOpcode::G_FNEARBYINT;
1240     case Intrinsic::pow:
1241       return TargetOpcode::G_FPOW;
1242     case Intrinsic::rint:
1243       return TargetOpcode::G_FRINT;
1244     case Intrinsic::round:
1245       return TargetOpcode::G_INTRINSIC_ROUND;
1246     case Intrinsic::sin:
1247       return TargetOpcode::G_FSIN;
1248     case Intrinsic::sqrt:
1249       return TargetOpcode::G_FSQRT;
1250     case Intrinsic::trunc:
1251       return TargetOpcode::G_INTRINSIC_TRUNC;
1252   }
1253   return Intrinsic::not_intrinsic;
1254 }
1255 
1256 bool IRTranslator::translateSimpleIntrinsic(const CallInst &CI,
1257                                             Intrinsic::ID ID,
1258                                             MachineIRBuilder &MIRBuilder) {
1259 
1260   unsigned Op = getSimpleIntrinsicOpcode(ID);
1261 
1262   // Is this a simple intrinsic?
1263   if (Op == Intrinsic::not_intrinsic)
1264     return false;
1265 
1266   // Yes. Let's translate it.
1267   SmallVector<llvm::SrcOp, 4> VRegs;
1268   for (auto &Arg : CI.arg_operands())
1269     VRegs.push_back(getOrCreateVReg(*Arg));
1270 
1271   MIRBuilder.buildInstr(Op, {getOrCreateVReg(CI)}, VRegs,
1272                         MachineInstr::copyFlagsFromInstruction(CI));
1273   return true;
1274 }
1275 
1276 bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
1277                                            MachineIRBuilder &MIRBuilder) {
1278 
1279   // If this is a simple intrinsic (that is, we just need to add a def of
1280   // a vreg, and uses for each arg operand, then translate it.
1281   if (translateSimpleIntrinsic(CI, ID, MIRBuilder))
1282     return true;
1283 
1284   switch (ID) {
1285   default:
1286     break;
1287   case Intrinsic::lifetime_start:
1288   case Intrinsic::lifetime_end: {
1289     // No stack colouring in O0, discard region information.
1290     if (MF->getTarget().getOptLevel() == CodeGenOpt::None)
1291       return true;
1292 
1293     unsigned Op = ID == Intrinsic::lifetime_start ? TargetOpcode::LIFETIME_START
1294                                                   : TargetOpcode::LIFETIME_END;
1295 
1296     // Get the underlying objects for the location passed on the lifetime
1297     // marker.
1298     SmallVector<const Value *, 4> Allocas;
1299     GetUnderlyingObjects(CI.getArgOperand(1), Allocas, *DL);
1300 
1301     // Iterate over each underlying object, creating lifetime markers for each
1302     // static alloca. Quit if we find a non-static alloca.
1303     for (const Value *V : Allocas) {
1304       const AllocaInst *AI = dyn_cast<AllocaInst>(V);
1305       if (!AI)
1306         continue;
1307 
1308       if (!AI->isStaticAlloca())
1309         return true;
1310 
1311       MIRBuilder.buildInstr(Op).addFrameIndex(getOrCreateFrameIndex(*AI));
1312     }
1313     return true;
1314   }
1315   case Intrinsic::dbg_declare: {
1316     const DbgDeclareInst &DI = cast<DbgDeclareInst>(CI);
1317     assert(DI.getVariable() && "Missing variable");
1318 
1319     const Value *Address = DI.getAddress();
1320     if (!Address || isa<UndefValue>(Address)) {
1321       LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
1322       return true;
1323     }
1324 
1325     assert(DI.getVariable()->isValidLocationForIntrinsic(
1326                MIRBuilder.getDebugLoc()) &&
1327            "Expected inlined-at fields to agree");
1328     auto AI = dyn_cast<AllocaInst>(Address);
1329     if (AI && AI->isStaticAlloca()) {
1330       // Static allocas are tracked at the MF level, no need for DBG_VALUE
1331       // instructions (in fact, they get ignored if they *do* exist).
1332       MF->setVariableDbgInfo(DI.getVariable(), DI.getExpression(),
1333                              getOrCreateFrameIndex(*AI), DI.getDebugLoc());
1334     } else {
1335       // A dbg.declare describes the address of a source variable, so lower it
1336       // into an indirect DBG_VALUE.
1337       MIRBuilder.buildIndirectDbgValue(getOrCreateVReg(*Address),
1338                                        DI.getVariable(), DI.getExpression());
1339     }
1340     return true;
1341   }
1342   case Intrinsic::dbg_label: {
1343     const DbgLabelInst &DI = cast<DbgLabelInst>(CI);
1344     assert(DI.getLabel() && "Missing label");
1345 
1346     assert(DI.getLabel()->isValidLocationForIntrinsic(
1347                MIRBuilder.getDebugLoc()) &&
1348            "Expected inlined-at fields to agree");
1349 
1350     MIRBuilder.buildDbgLabel(DI.getLabel());
1351     return true;
1352   }
1353   case Intrinsic::vaend:
1354     // No target I know of cares about va_end. Certainly no in-tree target
1355     // does. Simplest intrinsic ever!
1356     return true;
1357   case Intrinsic::vastart: {
1358     auto &TLI = *MF->getSubtarget().getTargetLowering();
1359     Value *Ptr = CI.getArgOperand(0);
1360     unsigned ListSize = TLI.getVaListSizeInBits(*DL) / 8;
1361 
1362     // FIXME: Get alignment
1363     MIRBuilder.buildInstr(TargetOpcode::G_VASTART)
1364         .addUse(getOrCreateVReg(*Ptr))
1365         .addMemOperand(MF->getMachineMemOperand(
1366             MachinePointerInfo(Ptr), MachineMemOperand::MOStore, ListSize, 1));
1367     return true;
1368   }
1369   case Intrinsic::dbg_value: {
1370     // This form of DBG_VALUE is target-independent.
1371     const DbgValueInst &DI = cast<DbgValueInst>(CI);
1372     const Value *V = DI.getValue();
1373     assert(DI.getVariable()->isValidLocationForIntrinsic(
1374                MIRBuilder.getDebugLoc()) &&
1375            "Expected inlined-at fields to agree");
1376     if (!V) {
1377       // Currently the optimizer can produce this; insert an undef to
1378       // help debugging.  Probably the optimizer should not do this.
1379       MIRBuilder.buildIndirectDbgValue(0, DI.getVariable(), DI.getExpression());
1380     } else if (const auto *CI = dyn_cast<Constant>(V)) {
1381       MIRBuilder.buildConstDbgValue(*CI, DI.getVariable(), DI.getExpression());
1382     } else {
1383       Register Reg = getOrCreateVReg(*V);
1384       // FIXME: This does not handle register-indirect values at offset 0. The
1385       // direct/indirect thing shouldn't really be handled by something as
1386       // implicit as reg+noreg vs reg+imm in the first palce, but it seems
1387       // pretty baked in right now.
1388       MIRBuilder.buildDirectDbgValue(Reg, DI.getVariable(), DI.getExpression());
1389     }
1390     return true;
1391   }
1392   case Intrinsic::uadd_with_overflow:
1393     return translateOverflowIntrinsic(CI, TargetOpcode::G_UADDO, MIRBuilder);
1394   case Intrinsic::sadd_with_overflow:
1395     return translateOverflowIntrinsic(CI, TargetOpcode::G_SADDO, MIRBuilder);
1396   case Intrinsic::usub_with_overflow:
1397     return translateOverflowIntrinsic(CI, TargetOpcode::G_USUBO, MIRBuilder);
1398   case Intrinsic::ssub_with_overflow:
1399     return translateOverflowIntrinsic(CI, TargetOpcode::G_SSUBO, MIRBuilder);
1400   case Intrinsic::umul_with_overflow:
1401     return translateOverflowIntrinsic(CI, TargetOpcode::G_UMULO, MIRBuilder);
1402   case Intrinsic::smul_with_overflow:
1403     return translateOverflowIntrinsic(CI, TargetOpcode::G_SMULO, MIRBuilder);
1404   case Intrinsic::fmuladd: {
1405     const TargetMachine &TM = MF->getTarget();
1406     const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
1407     Register Dst = getOrCreateVReg(CI);
1408     Register Op0 = getOrCreateVReg(*CI.getArgOperand(0));
1409     Register Op1 = getOrCreateVReg(*CI.getArgOperand(1));
1410     Register Op2 = getOrCreateVReg(*CI.getArgOperand(2));
1411     if (TM.Options.AllowFPOpFusion != FPOpFusion::Strict &&
1412         TLI.isFMAFasterThanFMulAndFAdd(TLI.getValueType(*DL, CI.getType()))) {
1413       // TODO: Revisit this to see if we should move this part of the
1414       // lowering to the combiner.
1415       MIRBuilder.buildInstr(TargetOpcode::G_FMA, {Dst}, {Op0, Op1, Op2},
1416                             MachineInstr::copyFlagsFromInstruction(CI));
1417     } else {
1418       LLT Ty = getLLTForType(*CI.getType(), *DL);
1419       auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, {Ty}, {Op0, Op1},
1420                                         MachineInstr::copyFlagsFromInstruction(CI));
1421       MIRBuilder.buildInstr(TargetOpcode::G_FADD, {Dst}, {FMul, Op2},
1422                             MachineInstr::copyFlagsFromInstruction(CI));
1423     }
1424     return true;
1425   }
1426   case Intrinsic::memcpy:
1427   case Intrinsic::memmove:
1428   case Intrinsic::memset:
1429     return translateMemFunc(CI, MIRBuilder, ID);
1430   case Intrinsic::eh_typeid_for: {
1431     GlobalValue *GV = ExtractTypeInfo(CI.getArgOperand(0));
1432     Register Reg = getOrCreateVReg(CI);
1433     unsigned TypeID = MF->getTypeIDFor(GV);
1434     MIRBuilder.buildConstant(Reg, TypeID);
1435     return true;
1436   }
1437   case Intrinsic::objectsize: {
1438     // If we don't know by now, we're never going to know.
1439     const ConstantInt *Min = cast<ConstantInt>(CI.getArgOperand(1));
1440 
1441     MIRBuilder.buildConstant(getOrCreateVReg(CI), Min->isZero() ? -1ULL : 0);
1442     return true;
1443   }
1444   case Intrinsic::is_constant:
1445     // If this wasn't constant-folded away by now, then it's not a
1446     // constant.
1447     MIRBuilder.buildConstant(getOrCreateVReg(CI), 0);
1448     return true;
1449   case Intrinsic::stackguard:
1450     getStackGuard(getOrCreateVReg(CI), MIRBuilder);
1451     return true;
1452   case Intrinsic::stackprotector: {
1453     LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
1454     Register GuardVal = MRI->createGenericVirtualRegister(PtrTy);
1455     getStackGuard(GuardVal, MIRBuilder);
1456 
1457     AllocaInst *Slot = cast<AllocaInst>(CI.getArgOperand(1));
1458     int FI = getOrCreateFrameIndex(*Slot);
1459     MF->getFrameInfo().setStackProtectorIndex(FI);
1460 
1461     MIRBuilder.buildStore(
1462         GuardVal, getOrCreateVReg(*Slot),
1463         *MF->getMachineMemOperand(MachinePointerInfo::getFixedStack(*MF, FI),
1464                                   MachineMemOperand::MOStore |
1465                                       MachineMemOperand::MOVolatile,
1466                                   PtrTy.getSizeInBits() / 8, 8));
1467     return true;
1468   }
1469   case Intrinsic::stacksave: {
1470     // Save the stack pointer to the location provided by the intrinsic.
1471     Register Reg = getOrCreateVReg(CI);
1472     Register StackPtr = MF->getSubtarget()
1473                             .getTargetLowering()
1474                             ->getStackPointerRegisterToSaveRestore();
1475 
1476     // If the target doesn't specify a stack pointer, then fall back.
1477     if (!StackPtr)
1478       return false;
1479 
1480     MIRBuilder.buildCopy(Reg, StackPtr);
1481     return true;
1482   }
1483   case Intrinsic::stackrestore: {
1484     // Restore the stack pointer from the location provided by the intrinsic.
1485     Register Reg = getOrCreateVReg(*CI.getArgOperand(0));
1486     Register StackPtr = MF->getSubtarget()
1487                             .getTargetLowering()
1488                             ->getStackPointerRegisterToSaveRestore();
1489 
1490     // If the target doesn't specify a stack pointer, then fall back.
1491     if (!StackPtr)
1492       return false;
1493 
1494     MIRBuilder.buildCopy(StackPtr, Reg);
1495     return true;
1496   }
1497   case Intrinsic::cttz:
1498   case Intrinsic::ctlz: {
1499     ConstantInt *Cst = cast<ConstantInt>(CI.getArgOperand(1));
1500     bool isTrailing = ID == Intrinsic::cttz;
1501     unsigned Opcode = isTrailing
1502                           ? Cst->isZero() ? TargetOpcode::G_CTTZ
1503                                           : TargetOpcode::G_CTTZ_ZERO_UNDEF
1504                           : Cst->isZero() ? TargetOpcode::G_CTLZ
1505                                           : TargetOpcode::G_CTLZ_ZERO_UNDEF;
1506     MIRBuilder.buildInstr(Opcode)
1507         .addDef(getOrCreateVReg(CI))
1508         .addUse(getOrCreateVReg(*CI.getArgOperand(0)));
1509     return true;
1510   }
1511   case Intrinsic::invariant_start: {
1512     LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
1513     Register Undef = MRI->createGenericVirtualRegister(PtrTy);
1514     MIRBuilder.buildUndef(Undef);
1515     return true;
1516   }
1517   case Intrinsic::invariant_end:
1518     return true;
1519   case Intrinsic::assume:
1520   case Intrinsic::var_annotation:
1521   case Intrinsic::sideeffect:
1522     // Discard annotate attributes, assumptions, and artificial side-effects.
1523     return true;
1524   }
1525   return false;
1526 }
1527 
1528 bool IRTranslator::translateInlineAsm(const CallInst &CI,
1529                                       MachineIRBuilder &MIRBuilder) {
1530   const InlineAsm &IA = cast<InlineAsm>(*CI.getCalledValue());
1531   if (!IA.getConstraintString().empty())
1532     return false;
1533 
1534   unsigned ExtraInfo = 0;
1535   if (IA.hasSideEffects())
1536     ExtraInfo |= InlineAsm::Extra_HasSideEffects;
1537   if (IA.getDialect() == InlineAsm::AD_Intel)
1538     ExtraInfo |= InlineAsm::Extra_AsmDialect;
1539 
1540   MIRBuilder.buildInstr(TargetOpcode::INLINEASM)
1541     .addExternalSymbol(IA.getAsmString().c_str())
1542     .addImm(ExtraInfo);
1543 
1544   return true;
1545 }
1546 
1547 bool IRTranslator::translateCallSite(const ImmutableCallSite &CS,
1548                                      MachineIRBuilder &MIRBuilder) {
1549   const Instruction &I = *CS.getInstruction();
1550   ArrayRef<Register> Res = getOrCreateVRegs(I);
1551 
1552   SmallVector<ArrayRef<Register>, 8> Args;
1553   Register SwiftInVReg = 0;
1554   Register SwiftErrorVReg = 0;
1555   for (auto &Arg : CS.args()) {
1556     if (CLI->supportSwiftError() && isSwiftError(Arg)) {
1557       assert(SwiftInVReg == 0 && "Expected only one swift error argument");
1558       LLT Ty = getLLTForType(*Arg->getType(), *DL);
1559       SwiftInVReg = MRI->createGenericVirtualRegister(Ty);
1560       MIRBuilder.buildCopy(SwiftInVReg, SwiftError.getOrCreateVRegUseAt(
1561                                             &I, &MIRBuilder.getMBB(), Arg));
1562       Args.emplace_back(makeArrayRef(SwiftInVReg));
1563       SwiftErrorVReg =
1564           SwiftError.getOrCreateVRegDefAt(&I, &MIRBuilder.getMBB(), Arg);
1565       continue;
1566     }
1567     Args.push_back(getOrCreateVRegs(*Arg));
1568   }
1569 
1570   MF->getFrameInfo().setHasCalls(true);
1571   bool Success =
1572       CLI->lowerCall(MIRBuilder, CS, Res, Args, SwiftErrorVReg,
1573                      [&]() { return getOrCreateVReg(*CS.getCalledValue()); });
1574 
1575   return Success;
1576 }
1577 
1578 bool IRTranslator::translateCall(const User &U, MachineIRBuilder &MIRBuilder) {
1579   const CallInst &CI = cast<CallInst>(U);
1580   auto TII = MF->getTarget().getIntrinsicInfo();
1581   const Function *F = CI.getCalledFunction();
1582 
1583   // FIXME: support Windows dllimport function calls.
1584   if (F && F->hasDLLImportStorageClass())
1585     return false;
1586 
1587   if (CI.isInlineAsm())
1588     return translateInlineAsm(CI, MIRBuilder);
1589 
1590   Intrinsic::ID ID = Intrinsic::not_intrinsic;
1591   if (F && F->isIntrinsic()) {
1592     ID = F->getIntrinsicID();
1593     if (TII && ID == Intrinsic::not_intrinsic)
1594       ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
1595   }
1596 
1597   if (!F || !F->isIntrinsic() || ID == Intrinsic::not_intrinsic)
1598     return translateCallSite(&CI, MIRBuilder);
1599 
1600   assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
1601 
1602   if (translateKnownIntrinsic(CI, ID, MIRBuilder))
1603     return true;
1604 
1605   ArrayRef<Register> ResultRegs;
1606   if (!CI.getType()->isVoidTy())
1607     ResultRegs = getOrCreateVRegs(CI);
1608 
1609   // Ignore the callsite attributes. Backend code is most likely not expecting
1610   // an intrinsic to sometimes have side effects and sometimes not.
1611   MachineInstrBuilder MIB =
1612       MIRBuilder.buildIntrinsic(ID, ResultRegs, !F->doesNotAccessMemory());
1613   if (isa<FPMathOperator>(CI))
1614     MIB->copyIRFlags(CI);
1615 
1616   for (auto &Arg : CI.arg_operands()) {
1617     // Some intrinsics take metadata parameters. Reject them.
1618     if (isa<MetadataAsValue>(Arg))
1619       return false;
1620     ArrayRef<Register> VRegs = getOrCreateVRegs(*Arg);
1621     if (VRegs.size() > 1)
1622       return false;
1623     MIB.addUse(VRegs[0]);
1624   }
1625 
1626   // Add a MachineMemOperand if it is a target mem intrinsic.
1627   const TargetLowering &TLI = *MF->getSubtarget().getTargetLowering();
1628   TargetLowering::IntrinsicInfo Info;
1629   // TODO: Add a GlobalISel version of getTgtMemIntrinsic.
1630   if (TLI.getTgtMemIntrinsic(Info, CI, *MF, ID)) {
1631     MaybeAlign Align = Info.align;
1632     if (!Align)
1633       Align = MaybeAlign(
1634           DL->getABITypeAlignment(Info.memVT.getTypeForEVT(F->getContext())));
1635 
1636     uint64_t Size = Info.memVT.getStoreSize();
1637     MIB.addMemOperand(MF->getMachineMemOperand(
1638         MachinePointerInfo(Info.ptrVal), Info.flags, Size, Align->value()));
1639   }
1640 
1641   return true;
1642 }
1643 
1644 bool IRTranslator::translateInvoke(const User &U,
1645                                    MachineIRBuilder &MIRBuilder) {
1646   const InvokeInst &I = cast<InvokeInst>(U);
1647   MCContext &Context = MF->getContext();
1648 
1649   const BasicBlock *ReturnBB = I.getSuccessor(0);
1650   const BasicBlock *EHPadBB = I.getSuccessor(1);
1651 
1652   const Value *Callee = I.getCalledValue();
1653   const Function *Fn = dyn_cast<Function>(Callee);
1654   if (isa<InlineAsm>(Callee))
1655     return false;
1656 
1657   // FIXME: support invoking patchpoint and statepoint intrinsics.
1658   if (Fn && Fn->isIntrinsic())
1659     return false;
1660 
1661   // FIXME: support whatever these are.
1662   if (I.countOperandBundlesOfType(LLVMContext::OB_deopt))
1663     return false;
1664 
1665   // FIXME: support Windows exception handling.
1666   if (!isa<LandingPadInst>(EHPadBB->front()))
1667     return false;
1668 
1669   // Emit the actual call, bracketed by EH_LABELs so that the MF knows about
1670   // the region covered by the try.
1671   MCSymbol *BeginSymbol = Context.createTempSymbol();
1672   MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(BeginSymbol);
1673 
1674   if (!translateCallSite(&I, MIRBuilder))
1675     return false;
1676 
1677   MCSymbol *EndSymbol = Context.createTempSymbol();
1678   MIRBuilder.buildInstr(TargetOpcode::EH_LABEL).addSym(EndSymbol);
1679 
1680   // FIXME: track probabilities.
1681   MachineBasicBlock &EHPadMBB = getMBB(*EHPadBB),
1682                     &ReturnMBB = getMBB(*ReturnBB);
1683   MF->addInvoke(&EHPadMBB, BeginSymbol, EndSymbol);
1684   MIRBuilder.getMBB().addSuccessor(&ReturnMBB);
1685   MIRBuilder.getMBB().addSuccessor(&EHPadMBB);
1686   MIRBuilder.buildBr(ReturnMBB);
1687 
1688   return true;
1689 }
1690 
1691 bool IRTranslator::translateCallBr(const User &U,
1692                                    MachineIRBuilder &MIRBuilder) {
1693   // FIXME: Implement this.
1694   return false;
1695 }
1696 
1697 bool IRTranslator::translateLandingPad(const User &U,
1698                                        MachineIRBuilder &MIRBuilder) {
1699   const LandingPadInst &LP = cast<LandingPadInst>(U);
1700 
1701   MachineBasicBlock &MBB = MIRBuilder.getMBB();
1702 
1703   MBB.setIsEHPad();
1704 
1705   // If there aren't registers to copy the values into (e.g., during SjLj
1706   // exceptions), then don't bother.
1707   auto &TLI = *MF->getSubtarget().getTargetLowering();
1708   const Constant *PersonalityFn = MF->getFunction().getPersonalityFn();
1709   if (TLI.getExceptionPointerRegister(PersonalityFn) == 0 &&
1710       TLI.getExceptionSelectorRegister(PersonalityFn) == 0)
1711     return true;
1712 
1713   // If landingpad's return type is token type, we don't create DAG nodes
1714   // for its exception pointer and selector value. The extraction of exception
1715   // pointer or selector value from token type landingpads is not currently
1716   // supported.
1717   if (LP.getType()->isTokenTy())
1718     return true;
1719 
1720   // Add a label to mark the beginning of the landing pad.  Deletion of the
1721   // landing pad can thus be detected via the MachineModuleInfo.
1722   MIRBuilder.buildInstr(TargetOpcode::EH_LABEL)
1723     .addSym(MF->addLandingPad(&MBB));
1724 
1725   LLT Ty = getLLTForType(*LP.getType(), *DL);
1726   Register Undef = MRI->createGenericVirtualRegister(Ty);
1727   MIRBuilder.buildUndef(Undef);
1728 
1729   SmallVector<LLT, 2> Tys;
1730   for (Type *Ty : cast<StructType>(LP.getType())->elements())
1731     Tys.push_back(getLLTForType(*Ty, *DL));
1732   assert(Tys.size() == 2 && "Only two-valued landingpads are supported");
1733 
1734   // Mark exception register as live in.
1735   Register ExceptionReg = TLI.getExceptionPointerRegister(PersonalityFn);
1736   if (!ExceptionReg)
1737     return false;
1738 
1739   MBB.addLiveIn(ExceptionReg);
1740   ArrayRef<Register> ResRegs = getOrCreateVRegs(LP);
1741   MIRBuilder.buildCopy(ResRegs[0], ExceptionReg);
1742 
1743   Register SelectorReg = TLI.getExceptionSelectorRegister(PersonalityFn);
1744   if (!SelectorReg)
1745     return false;
1746 
1747   MBB.addLiveIn(SelectorReg);
1748   Register PtrVReg = MRI->createGenericVirtualRegister(Tys[0]);
1749   MIRBuilder.buildCopy(PtrVReg, SelectorReg);
1750   MIRBuilder.buildCast(ResRegs[1], PtrVReg);
1751 
1752   return true;
1753 }
1754 
1755 bool IRTranslator::translateAlloca(const User &U,
1756                                    MachineIRBuilder &MIRBuilder) {
1757   auto &AI = cast<AllocaInst>(U);
1758 
1759   if (AI.isSwiftError())
1760     return true;
1761 
1762   if (AI.isStaticAlloca()) {
1763     Register Res = getOrCreateVReg(AI);
1764     int FI = getOrCreateFrameIndex(AI);
1765     MIRBuilder.buildFrameIndex(Res, FI);
1766     return true;
1767   }
1768 
1769   // FIXME: support stack probing for Windows.
1770   if (MF->getTarget().getTargetTriple().isOSWindows())
1771     return false;
1772 
1773   // Now we're in the harder dynamic case.
1774   Type *Ty = AI.getAllocatedType();
1775   unsigned Align =
1776       std::max((unsigned)DL->getPrefTypeAlignment(Ty), AI.getAlignment());
1777 
1778   Register NumElts = getOrCreateVReg(*AI.getArraySize());
1779 
1780   Type *IntPtrIRTy = DL->getIntPtrType(AI.getType());
1781   LLT IntPtrTy = getLLTForType(*IntPtrIRTy, *DL);
1782   if (MRI->getType(NumElts) != IntPtrTy) {
1783     Register ExtElts = MRI->createGenericVirtualRegister(IntPtrTy);
1784     MIRBuilder.buildZExtOrTrunc(ExtElts, NumElts);
1785     NumElts = ExtElts;
1786   }
1787 
1788   Register AllocSize = MRI->createGenericVirtualRegister(IntPtrTy);
1789   Register TySize =
1790       getOrCreateVReg(*ConstantInt::get(IntPtrIRTy, -DL->getTypeAllocSize(Ty)));
1791   MIRBuilder.buildMul(AllocSize, NumElts, TySize);
1792 
1793   LLT PtrTy = getLLTForType(*AI.getType(), *DL);
1794   auto &TLI = *MF->getSubtarget().getTargetLowering();
1795   Register SPReg = TLI.getStackPointerRegisterToSaveRestore();
1796 
1797   Register SPTmp = MRI->createGenericVirtualRegister(PtrTy);
1798   MIRBuilder.buildCopy(SPTmp, SPReg);
1799 
1800   Register AllocTmp = MRI->createGenericVirtualRegister(PtrTy);
1801   MIRBuilder.buildGEP(AllocTmp, SPTmp, AllocSize);
1802 
1803   // Handle alignment. We have to realign if the allocation granule was smaller
1804   // than stack alignment, or the specific alloca requires more than stack
1805   // alignment.
1806   unsigned StackAlign =
1807       MF->getSubtarget().getFrameLowering()->getStackAlignment();
1808   Align = std::max(Align, StackAlign);
1809   if (Align > StackAlign || DL->getTypeAllocSize(Ty) % StackAlign != 0) {
1810     // Round the size of the allocation up to the stack alignment size
1811     // by add SA-1 to the size. This doesn't overflow because we're computing
1812     // an address inside an alloca.
1813     Register AlignedAlloc = MRI->createGenericVirtualRegister(PtrTy);
1814     MIRBuilder.buildPtrMask(AlignedAlloc, AllocTmp, Log2_32(Align));
1815     AllocTmp = AlignedAlloc;
1816   }
1817 
1818   MIRBuilder.buildCopy(SPReg, AllocTmp);
1819   MIRBuilder.buildCopy(getOrCreateVReg(AI), AllocTmp);
1820 
1821   MF->getFrameInfo().CreateVariableSizedObject(Align ? Align : 1, &AI);
1822   assert(MF->getFrameInfo().hasVarSizedObjects());
1823   return true;
1824 }
1825 
1826 bool IRTranslator::translateVAArg(const User &U, MachineIRBuilder &MIRBuilder) {
1827   // FIXME: We may need more info about the type. Because of how LLT works,
1828   // we're completely discarding the i64/double distinction here (amongst
1829   // others). Fortunately the ABIs I know of where that matters don't use va_arg
1830   // anyway but that's not guaranteed.
1831   MIRBuilder.buildInstr(TargetOpcode::G_VAARG)
1832     .addDef(getOrCreateVReg(U))
1833     .addUse(getOrCreateVReg(*U.getOperand(0)))
1834     .addImm(DL->getABITypeAlignment(U.getType()));
1835   return true;
1836 }
1837 
1838 bool IRTranslator::translateInsertElement(const User &U,
1839                                           MachineIRBuilder &MIRBuilder) {
1840   // If it is a <1 x Ty> vector, use the scalar as it is
1841   // not a legal vector type in LLT.
1842   if (U.getType()->getVectorNumElements() == 1) {
1843     Register Elt = getOrCreateVReg(*U.getOperand(1));
1844     auto &Regs = *VMap.getVRegs(U);
1845     if (Regs.empty()) {
1846       Regs.push_back(Elt);
1847       VMap.getOffsets(U)->push_back(0);
1848     } else {
1849       MIRBuilder.buildCopy(Regs[0], Elt);
1850     }
1851     return true;
1852   }
1853 
1854   Register Res = getOrCreateVReg(U);
1855   Register Val = getOrCreateVReg(*U.getOperand(0));
1856   Register Elt = getOrCreateVReg(*U.getOperand(1));
1857   Register Idx = getOrCreateVReg(*U.getOperand(2));
1858   MIRBuilder.buildInsertVectorElement(Res, Val, Elt, Idx);
1859   return true;
1860 }
1861 
1862 bool IRTranslator::translateExtractElement(const User &U,
1863                                            MachineIRBuilder &MIRBuilder) {
1864   // If it is a <1 x Ty> vector, use the scalar as it is
1865   // not a legal vector type in LLT.
1866   if (U.getOperand(0)->getType()->getVectorNumElements() == 1) {
1867     Register Elt = getOrCreateVReg(*U.getOperand(0));
1868     auto &Regs = *VMap.getVRegs(U);
1869     if (Regs.empty()) {
1870       Regs.push_back(Elt);
1871       VMap.getOffsets(U)->push_back(0);
1872     } else {
1873       MIRBuilder.buildCopy(Regs[0], Elt);
1874     }
1875     return true;
1876   }
1877   Register Res = getOrCreateVReg(U);
1878   Register Val = getOrCreateVReg(*U.getOperand(0));
1879   const auto &TLI = *MF->getSubtarget().getTargetLowering();
1880   unsigned PreferredVecIdxWidth = TLI.getVectorIdxTy(*DL).getSizeInBits();
1881   Register Idx;
1882   if (auto *CI = dyn_cast<ConstantInt>(U.getOperand(1))) {
1883     if (CI->getBitWidth() != PreferredVecIdxWidth) {
1884       APInt NewIdx = CI->getValue().sextOrTrunc(PreferredVecIdxWidth);
1885       auto *NewIdxCI = ConstantInt::get(CI->getContext(), NewIdx);
1886       Idx = getOrCreateVReg(*NewIdxCI);
1887     }
1888   }
1889   if (!Idx)
1890     Idx = getOrCreateVReg(*U.getOperand(1));
1891   if (MRI->getType(Idx).getSizeInBits() != PreferredVecIdxWidth) {
1892     const LLT &VecIdxTy = LLT::scalar(PreferredVecIdxWidth);
1893     Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx)->getOperand(0).getReg();
1894   }
1895   MIRBuilder.buildExtractVectorElement(Res, Val, Idx);
1896   return true;
1897 }
1898 
1899 bool IRTranslator::translateShuffleVector(const User &U,
1900                                           MachineIRBuilder &MIRBuilder) {
1901   MIRBuilder.buildInstr(TargetOpcode::G_SHUFFLE_VECTOR)
1902       .addDef(getOrCreateVReg(U))
1903       .addUse(getOrCreateVReg(*U.getOperand(0)))
1904       .addUse(getOrCreateVReg(*U.getOperand(1)))
1905       .addShuffleMask(cast<Constant>(U.getOperand(2)));
1906   return true;
1907 }
1908 
1909 bool IRTranslator::translatePHI(const User &U, MachineIRBuilder &MIRBuilder) {
1910   const PHINode &PI = cast<PHINode>(U);
1911 
1912   SmallVector<MachineInstr *, 4> Insts;
1913   for (auto Reg : getOrCreateVRegs(PI)) {
1914     auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, {Reg}, {});
1915     Insts.push_back(MIB.getInstr());
1916   }
1917 
1918   PendingPHIs.emplace_back(&PI, std::move(Insts));
1919   return true;
1920 }
1921 
1922 bool IRTranslator::translateAtomicCmpXchg(const User &U,
1923                                           MachineIRBuilder &MIRBuilder) {
1924   const AtomicCmpXchgInst &I = cast<AtomicCmpXchgInst>(U);
1925 
1926   if (I.isWeak())
1927     return false;
1928 
1929   auto Flags = I.isVolatile() ? MachineMemOperand::MOVolatile
1930                               : MachineMemOperand::MONone;
1931   Flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1932 
1933   Type *ResType = I.getType();
1934   Type *ValType = ResType->Type::getStructElementType(0);
1935 
1936   auto Res = getOrCreateVRegs(I);
1937   Register OldValRes = Res[0];
1938   Register SuccessRes = Res[1];
1939   Register Addr = getOrCreateVReg(*I.getPointerOperand());
1940   Register Cmp = getOrCreateVReg(*I.getCompareOperand());
1941   Register NewVal = getOrCreateVReg(*I.getNewValOperand());
1942 
1943   MIRBuilder.buildAtomicCmpXchgWithSuccess(
1944       OldValRes, SuccessRes, Addr, Cmp, NewVal,
1945       *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
1946                                 Flags, DL->getTypeStoreSize(ValType),
1947                                 getMemOpAlignment(I), AAMDNodes(), nullptr,
1948                                 I.getSyncScopeID(), I.getSuccessOrdering(),
1949                                 I.getFailureOrdering()));
1950   return true;
1951 }
1952 
1953 bool IRTranslator::translateAtomicRMW(const User &U,
1954                                       MachineIRBuilder &MIRBuilder) {
1955   const AtomicRMWInst &I = cast<AtomicRMWInst>(U);
1956 
1957   auto Flags = I.isVolatile() ? MachineMemOperand::MOVolatile
1958                               : MachineMemOperand::MONone;
1959   Flags |= MachineMemOperand::MOLoad | MachineMemOperand::MOStore;
1960 
1961   Type *ResType = I.getType();
1962 
1963   Register Res = getOrCreateVReg(I);
1964   Register Addr = getOrCreateVReg(*I.getPointerOperand());
1965   Register Val = getOrCreateVReg(*I.getValOperand());
1966 
1967   unsigned Opcode = 0;
1968   switch (I.getOperation()) {
1969   default:
1970     return false;
1971   case AtomicRMWInst::Xchg:
1972     Opcode = TargetOpcode::G_ATOMICRMW_XCHG;
1973     break;
1974   case AtomicRMWInst::Add:
1975     Opcode = TargetOpcode::G_ATOMICRMW_ADD;
1976     break;
1977   case AtomicRMWInst::Sub:
1978     Opcode = TargetOpcode::G_ATOMICRMW_SUB;
1979     break;
1980   case AtomicRMWInst::And:
1981     Opcode = TargetOpcode::G_ATOMICRMW_AND;
1982     break;
1983   case AtomicRMWInst::Nand:
1984     Opcode = TargetOpcode::G_ATOMICRMW_NAND;
1985     break;
1986   case AtomicRMWInst::Or:
1987     Opcode = TargetOpcode::G_ATOMICRMW_OR;
1988     break;
1989   case AtomicRMWInst::Xor:
1990     Opcode = TargetOpcode::G_ATOMICRMW_XOR;
1991     break;
1992   case AtomicRMWInst::Max:
1993     Opcode = TargetOpcode::G_ATOMICRMW_MAX;
1994     break;
1995   case AtomicRMWInst::Min:
1996     Opcode = TargetOpcode::G_ATOMICRMW_MIN;
1997     break;
1998   case AtomicRMWInst::UMax:
1999     Opcode = TargetOpcode::G_ATOMICRMW_UMAX;
2000     break;
2001   case AtomicRMWInst::UMin:
2002     Opcode = TargetOpcode::G_ATOMICRMW_UMIN;
2003     break;
2004   case AtomicRMWInst::FAdd:
2005     Opcode = TargetOpcode::G_ATOMICRMW_FADD;
2006     break;
2007   case AtomicRMWInst::FSub:
2008     Opcode = TargetOpcode::G_ATOMICRMW_FSUB;
2009     break;
2010   }
2011 
2012   MIRBuilder.buildAtomicRMW(
2013       Opcode, Res, Addr, Val,
2014       *MF->getMachineMemOperand(MachinePointerInfo(I.getPointerOperand()),
2015                                 Flags, DL->getTypeStoreSize(ResType),
2016                                 getMemOpAlignment(I), AAMDNodes(), nullptr,
2017                                 I.getSyncScopeID(), I.getOrdering()));
2018   return true;
2019 }
2020 
2021 bool IRTranslator::translateFence(const User &U,
2022                                   MachineIRBuilder &MIRBuilder) {
2023   const FenceInst &Fence = cast<FenceInst>(U);
2024   MIRBuilder.buildFence(static_cast<unsigned>(Fence.getOrdering()),
2025                         Fence.getSyncScopeID());
2026   return true;
2027 }
2028 
2029 void IRTranslator::finishPendingPhis() {
2030 #ifndef NDEBUG
2031   DILocationVerifier Verifier;
2032   GISelObserverWrapper WrapperObserver(&Verifier);
2033   RAIIDelegateInstaller DelInstall(*MF, &WrapperObserver);
2034 #endif // ifndef NDEBUG
2035   for (auto &Phi : PendingPHIs) {
2036     const PHINode *PI = Phi.first;
2037     ArrayRef<MachineInstr *> ComponentPHIs = Phi.second;
2038     MachineBasicBlock *PhiMBB = ComponentPHIs[0]->getParent();
2039     EntryBuilder->setDebugLoc(PI->getDebugLoc());
2040 #ifndef NDEBUG
2041     Verifier.setCurrentInst(PI);
2042 #endif // ifndef NDEBUG
2043 
2044     SmallSet<const MachineBasicBlock *, 16> SeenPreds;
2045     for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
2046       auto IRPred = PI->getIncomingBlock(i);
2047       ArrayRef<Register> ValRegs = getOrCreateVRegs(*PI->getIncomingValue(i));
2048       for (auto Pred : getMachinePredBBs({IRPred, PI->getParent()})) {
2049         if (SeenPreds.count(Pred) || !PhiMBB->isPredecessor(Pred))
2050           continue;
2051         SeenPreds.insert(Pred);
2052         for (unsigned j = 0; j < ValRegs.size(); ++j) {
2053           MachineInstrBuilder MIB(*MF, ComponentPHIs[j]);
2054           MIB.addUse(ValRegs[j]);
2055           MIB.addMBB(Pred);
2056         }
2057       }
2058     }
2059   }
2060 }
2061 
2062 bool IRTranslator::valueIsSplit(const Value &V,
2063                                 SmallVectorImpl<uint64_t> *Offsets) {
2064   SmallVector<LLT, 4> SplitTys;
2065   if (Offsets && !Offsets->empty())
2066     Offsets->clear();
2067   computeValueLLTs(*DL, *V.getType(), SplitTys, Offsets);
2068   return SplitTys.size() > 1;
2069 }
2070 
2071 bool IRTranslator::translate(const Instruction &Inst) {
2072   CurBuilder->setDebugLoc(Inst.getDebugLoc());
2073   // We only emit constants into the entry block from here. To prevent jumpy
2074   // debug behaviour set the line to 0.
2075   if (const DebugLoc &DL = Inst.getDebugLoc())
2076     EntryBuilder->setDebugLoc(
2077         DebugLoc::get(0, 0, DL.getScope(), DL.getInlinedAt()));
2078   else
2079     EntryBuilder->setDebugLoc(DebugLoc());
2080 
2081   switch (Inst.getOpcode()) {
2082 #define HANDLE_INST(NUM, OPCODE, CLASS)                                        \
2083   case Instruction::OPCODE:                                                    \
2084     return translate##OPCODE(Inst, *CurBuilder.get());
2085 #include "llvm/IR/Instruction.def"
2086   default:
2087     return false;
2088   }
2089 }
2090 
2091 bool IRTranslator::translate(const Constant &C, Register Reg) {
2092   if (auto CI = dyn_cast<ConstantInt>(&C))
2093     EntryBuilder->buildConstant(Reg, *CI);
2094   else if (auto CF = dyn_cast<ConstantFP>(&C))
2095     EntryBuilder->buildFConstant(Reg, *CF);
2096   else if (isa<UndefValue>(C))
2097     EntryBuilder->buildUndef(Reg);
2098   else if (isa<ConstantPointerNull>(C)) {
2099     // As we are trying to build a constant val of 0 into a pointer,
2100     // insert a cast to make them correct with respect to types.
2101     unsigned NullSize = DL->getTypeSizeInBits(C.getType());
2102     auto *ZeroTy = Type::getIntNTy(C.getContext(), NullSize);
2103     auto *ZeroVal = ConstantInt::get(ZeroTy, 0);
2104     Register ZeroReg = getOrCreateVReg(*ZeroVal);
2105     EntryBuilder->buildCast(Reg, ZeroReg);
2106   } else if (auto GV = dyn_cast<GlobalValue>(&C))
2107     EntryBuilder->buildGlobalValue(Reg, GV);
2108   else if (auto CAZ = dyn_cast<ConstantAggregateZero>(&C)) {
2109     if (!CAZ->getType()->isVectorTy())
2110       return false;
2111     // Return the scalar if it is a <1 x Ty> vector.
2112     if (CAZ->getNumElements() == 1)
2113       return translate(*CAZ->getElementValue(0u), Reg);
2114     SmallVector<Register, 4> Ops;
2115     for (unsigned i = 0; i < CAZ->getNumElements(); ++i) {
2116       Constant &Elt = *CAZ->getElementValue(i);
2117       Ops.push_back(getOrCreateVReg(Elt));
2118     }
2119     EntryBuilder->buildBuildVector(Reg, Ops);
2120   } else if (auto CV = dyn_cast<ConstantDataVector>(&C)) {
2121     // Return the scalar if it is a <1 x Ty> vector.
2122     if (CV->getNumElements() == 1)
2123       return translate(*CV->getElementAsConstant(0), Reg);
2124     SmallVector<Register, 4> Ops;
2125     for (unsigned i = 0; i < CV->getNumElements(); ++i) {
2126       Constant &Elt = *CV->getElementAsConstant(i);
2127       Ops.push_back(getOrCreateVReg(Elt));
2128     }
2129     EntryBuilder->buildBuildVector(Reg, Ops);
2130   } else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
2131     switch(CE->getOpcode()) {
2132 #define HANDLE_INST(NUM, OPCODE, CLASS)                                        \
2133   case Instruction::OPCODE:                                                    \
2134     return translate##OPCODE(*CE, *EntryBuilder.get());
2135 #include "llvm/IR/Instruction.def"
2136     default:
2137       return false;
2138     }
2139   } else if (auto CV = dyn_cast<ConstantVector>(&C)) {
2140     if (CV->getNumOperands() == 1)
2141       return translate(*CV->getOperand(0), Reg);
2142     SmallVector<Register, 4> Ops;
2143     for (unsigned i = 0; i < CV->getNumOperands(); ++i) {
2144       Ops.push_back(getOrCreateVReg(*CV->getOperand(i)));
2145     }
2146     EntryBuilder->buildBuildVector(Reg, Ops);
2147   } else if (auto *BA = dyn_cast<BlockAddress>(&C)) {
2148     EntryBuilder->buildBlockAddress(Reg, BA);
2149   } else
2150     return false;
2151 
2152   return true;
2153 }
2154 
2155 void IRTranslator::finalizeBasicBlock() {
2156   for (auto &JTCase : SL->JTCases) {
2157     // Emit header first, if it wasn't already emitted.
2158     if (!JTCase.first.Emitted)
2159       emitJumpTableHeader(JTCase.second, JTCase.first, JTCase.first.HeaderBB);
2160 
2161     emitJumpTable(JTCase.second, JTCase.second.MBB);
2162   }
2163   SL->JTCases.clear();
2164 }
2165 
2166 void IRTranslator::finalizeFunction() {
2167   // Release the memory used by the different maps we
2168   // needed during the translation.
2169   PendingPHIs.clear();
2170   VMap.reset();
2171   FrameIndices.clear();
2172   MachinePreds.clear();
2173   // MachineIRBuilder::DebugLoc can outlive the DILocation it holds. Clear it
2174   // to avoid accessing free’d memory (in runOnMachineFunction) and to avoid
2175   // destroying it twice (in ~IRTranslator() and ~LLVMContext())
2176   EntryBuilder.reset();
2177   CurBuilder.reset();
2178   FuncInfo.clear();
2179 }
2180 
2181 bool IRTranslator::runOnMachineFunction(MachineFunction &CurMF) {
2182   MF = &CurMF;
2183   const Function &F = MF->getFunction();
2184   if (F.empty())
2185     return false;
2186   GISelCSEAnalysisWrapper &Wrapper =
2187       getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
2188   // Set the CSEConfig and run the analysis.
2189   GISelCSEInfo *CSEInfo = nullptr;
2190   TPC = &getAnalysis<TargetPassConfig>();
2191   bool EnableCSE = EnableCSEInIRTranslator.getNumOccurrences()
2192                        ? EnableCSEInIRTranslator
2193                        : TPC->isGISelCSEEnabled();
2194 
2195   if (EnableCSE) {
2196     EntryBuilder = make_unique<CSEMIRBuilder>(CurMF);
2197     CSEInfo = &Wrapper.get(TPC->getCSEConfig());
2198     EntryBuilder->setCSEInfo(CSEInfo);
2199     CurBuilder = make_unique<CSEMIRBuilder>(CurMF);
2200     CurBuilder->setCSEInfo(CSEInfo);
2201   } else {
2202     EntryBuilder = make_unique<MachineIRBuilder>();
2203     CurBuilder = make_unique<MachineIRBuilder>();
2204   }
2205   CLI = MF->getSubtarget().getCallLowering();
2206   CurBuilder->setMF(*MF);
2207   EntryBuilder->setMF(*MF);
2208   MRI = &MF->getRegInfo();
2209   DL = &F.getParent()->getDataLayout();
2210   ORE = llvm::make_unique<OptimizationRemarkEmitter>(&F);
2211   FuncInfo.MF = MF;
2212   FuncInfo.BPI = nullptr;
2213   const auto &TLI = *MF->getSubtarget().getTargetLowering();
2214   const TargetMachine &TM = MF->getTarget();
2215   SL = make_unique<GISelSwitchLowering>(this, FuncInfo);
2216   SL->init(TLI, TM, *DL);
2217 
2218   EnableOpts = TM.getOptLevel() != CodeGenOpt::None && !skipFunction(F);
2219 
2220   assert(PendingPHIs.empty() && "stale PHIs");
2221 
2222   if (!DL->isLittleEndian()) {
2223     // Currently we don't properly handle big endian code.
2224     OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
2225                                F.getSubprogram(), &F.getEntryBlock());
2226     R << "unable to translate in big endian mode";
2227     reportTranslationError(*MF, *TPC, *ORE, R);
2228   }
2229 
2230   // Release the per-function state when we return, whether we succeeded or not.
2231   auto FinalizeOnReturn = make_scope_exit([this]() { finalizeFunction(); });
2232 
2233   // Setup a separate basic-block for the arguments and constants
2234   MachineBasicBlock *EntryBB = MF->CreateMachineBasicBlock();
2235   MF->push_back(EntryBB);
2236   EntryBuilder->setMBB(*EntryBB);
2237 
2238   DebugLoc DbgLoc = F.getEntryBlock().getFirstNonPHI()->getDebugLoc();
2239   SwiftError.setFunction(CurMF);
2240   SwiftError.createEntriesInEntryBlock(DbgLoc);
2241 
2242   // Create all blocks, in IR order, to preserve the layout.
2243   for (const BasicBlock &BB: F) {
2244     auto *&MBB = BBToMBB[&BB];
2245 
2246     MBB = MF->CreateMachineBasicBlock(&BB);
2247     MF->push_back(MBB);
2248 
2249     if (BB.hasAddressTaken())
2250       MBB->setHasAddressTaken();
2251   }
2252 
2253   // Make our arguments/constants entry block fallthrough to the IR entry block.
2254   EntryBB->addSuccessor(&getMBB(F.front()));
2255 
2256   // Lower the actual args into this basic block.
2257   SmallVector<ArrayRef<Register>, 8> VRegArgs;
2258   for (const Argument &Arg: F.args()) {
2259     if (DL->getTypeStoreSize(Arg.getType()) == 0)
2260       continue; // Don't handle zero sized types.
2261     ArrayRef<Register> VRegs = getOrCreateVRegs(Arg);
2262     VRegArgs.push_back(VRegs);
2263 
2264     if (Arg.hasSwiftErrorAttr()) {
2265       assert(VRegs.size() == 1 && "Too many vregs for Swift error");
2266       SwiftError.setCurrentVReg(EntryBB, SwiftError.getFunctionArg(), VRegs[0]);
2267     }
2268   }
2269 
2270   if (!CLI->lowerFormalArguments(*EntryBuilder.get(), F, VRegArgs)) {
2271     OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
2272                                F.getSubprogram(), &F.getEntryBlock());
2273     R << "unable to lower arguments: " << ore::NV("Prototype", F.getType());
2274     reportTranslationError(*MF, *TPC, *ORE, R);
2275     return false;
2276   }
2277 
2278   // Need to visit defs before uses when translating instructions.
2279   GISelObserverWrapper WrapperObserver;
2280   if (EnableCSE && CSEInfo)
2281     WrapperObserver.addObserver(CSEInfo);
2282   {
2283     ReversePostOrderTraversal<const Function *> RPOT(&F);
2284 #ifndef NDEBUG
2285     DILocationVerifier Verifier;
2286     WrapperObserver.addObserver(&Verifier);
2287 #endif // ifndef NDEBUG
2288     RAIIDelegateInstaller DelInstall(*MF, &WrapperObserver);
2289     for (const BasicBlock *BB : RPOT) {
2290       MachineBasicBlock &MBB = getMBB(*BB);
2291       // Set the insertion point of all the following translations to
2292       // the end of this basic block.
2293       CurBuilder->setMBB(MBB);
2294 
2295       for (const Instruction &Inst : *BB) {
2296 #ifndef NDEBUG
2297         Verifier.setCurrentInst(&Inst);
2298 #endif // ifndef NDEBUG
2299         if (translate(Inst))
2300           continue;
2301 
2302         OptimizationRemarkMissed R("gisel-irtranslator", "GISelFailure",
2303                                    Inst.getDebugLoc(), BB);
2304         R << "unable to translate instruction: " << ore::NV("Opcode", &Inst);
2305 
2306         if (ORE->allowExtraAnalysis("gisel-irtranslator")) {
2307           std::string InstStrStorage;
2308           raw_string_ostream InstStr(InstStrStorage);
2309           InstStr << Inst;
2310 
2311           R << ": '" << InstStr.str() << "'";
2312         }
2313 
2314         reportTranslationError(*MF, *TPC, *ORE, R);
2315         return false;
2316       }
2317 
2318       finalizeBasicBlock();
2319     }
2320 #ifndef NDEBUG
2321     WrapperObserver.removeObserver(&Verifier);
2322 #endif
2323   }
2324 
2325   finishPendingPhis();
2326 
2327   SwiftError.propagateVRegs();
2328 
2329   // Merge the argument lowering and constants block with its single
2330   // successor, the LLVM-IR entry block.  We want the basic block to
2331   // be maximal.
2332   assert(EntryBB->succ_size() == 1 &&
2333          "Custom BB used for lowering should have only one successor");
2334   // Get the successor of the current entry block.
2335   MachineBasicBlock &NewEntryBB = **EntryBB->succ_begin();
2336   assert(NewEntryBB.pred_size() == 1 &&
2337          "LLVM-IR entry block has a predecessor!?");
2338   // Move all the instruction from the current entry block to the
2339   // new entry block.
2340   NewEntryBB.splice(NewEntryBB.begin(), EntryBB, EntryBB->begin(),
2341                     EntryBB->end());
2342 
2343   // Update the live-in information for the new entry block.
2344   for (const MachineBasicBlock::RegisterMaskPair &LiveIn : EntryBB->liveins())
2345     NewEntryBB.addLiveIn(LiveIn);
2346   NewEntryBB.sortUniqueLiveIns();
2347 
2348   // Get rid of the now empty basic block.
2349   EntryBB->removeSuccessor(&NewEntryBB);
2350   MF->remove(EntryBB);
2351   MF->DeleteMachineBasicBlock(EntryBB);
2352 
2353   assert(&MF->front() == &NewEntryBB &&
2354          "New entry wasn't next in the list of basic block!");
2355 
2356   // Initialize stack protector information.
2357   StackProtector &SP = getAnalysis<StackProtector>();
2358   SP.copyToMachineFrameInfo(MF->getFrameInfo());
2359 
2360   return false;
2361 }
2362