1 //===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This is an extremely simple MachineInstr-level dead-code-elimination pass.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "llvm/CodeGen/Passes.h"
15 #include "llvm/Pass.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/CodeGen/MachineRegisterInfo.h"
18 #include "llvm/Support/Debug.h"
19 #include "llvm/Support/raw_ostream.h"
20 #include "llvm/Target/TargetInstrInfo.h"
21 #include "llvm/Target/TargetMachine.h"
22 using namespace llvm;
23 
24 namespace {
25   class DeadMachineInstructionElim : public MachineFunctionPass {
26     virtual bool runOnMachineFunction(MachineFunction &MF);
27 
28     const TargetRegisterInfo *TRI;
29     const MachineRegisterInfo *MRI;
30     const TargetInstrInfo *TII;
31     BitVector LivePhysRegs;
32 
33   public:
34     static char ID; // Pass identification, replacement for typeid
35     DeadMachineInstructionElim() : MachineFunctionPass(&ID) {}
36 
37   private:
38     bool isDead(const MachineInstr *MI) const;
39   };
40 }
41 char DeadMachineInstructionElim::ID = 0;
42 
43 static RegisterPass<DeadMachineInstructionElim>
44 Y("dead-mi-elimination",
45   "Remove dead machine instructions");
46 
47 FunctionPass *llvm::createDeadMachineInstructionElimPass() {
48   return new DeadMachineInstructionElim();
49 }
50 
51 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
52   // Don't delete instructions with side effects.
53   bool SawStore = false;
54   if (!MI->isSafeToMove(TII, SawStore, 0))
55     return false;
56 
57   // Examine each operand.
58   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
59     const MachineOperand &MO = MI->getOperand(i);
60     if (MO.isReg() && MO.isDef()) {
61       unsigned Reg = MO.getReg();
62       if (TargetRegisterInfo::isPhysicalRegister(Reg) ?
63           LivePhysRegs[Reg] : !MRI->use_empty(Reg)) {
64         // This def has a use. Don't delete the instruction!
65         return false;
66       }
67     }
68   }
69 
70   // If there are no defs with uses, the instruction is dead.
71   return true;
72 }
73 
74 bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
75   bool AnyChanges = false;
76   MRI = &MF.getRegInfo();
77   TRI = MF.getTarget().getRegisterInfo();
78   TII = MF.getTarget().getInstrInfo();
79 
80   // Compute a bitvector to represent all non-allocatable physregs.
81   BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF);
82   NonAllocatableRegs.flip();
83 
84   // Loop over all instructions in all blocks, from bottom to top, so that it's
85   // more likely that chains of dependent but ultimately dead instructions will
86   // be cleaned up.
87   for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
88        I != E; ++I) {
89     MachineBasicBlock *MBB = &*I;
90 
91     // Start out assuming that all non-allocatable registers are live
92     // out of this block.
93     LivePhysRegs = NonAllocatableRegs;
94 
95     // Also add any explicit live-out physregs for this block.
96     if (!MBB->empty() && MBB->back().getDesc().isReturn())
97       for (MachineRegisterInfo::liveout_iterator LOI = MRI->liveout_begin(),
98            LOE = MRI->liveout_end(); LOI != LOE; ++LOI) {
99         unsigned Reg = *LOI;
100         if (TargetRegisterInfo::isPhysicalRegister(Reg))
101           LivePhysRegs.set(Reg);
102       }
103 
104     // Now scan the instructions and delete dead ones, tracking physreg
105     // liveness as we go.
106     for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
107          MIE = MBB->rend(); MII != MIE; ) {
108       MachineInstr *MI = &*MII;
109 
110       if (MI->getOpcode()==TargetInstrInfo::DEBUG_VALUE) {
111         // Don't delete the DEBUG_VALUE itself, but if its Value operand is
112         // a vreg and this is the only use, substitute an undef operand;
113         // the former operand will then be deleted normally.
114         if (MI->getNumOperands()==3 && MI->getOperand(0).isReg()) {
115           unsigned Reg = MI->getOperand(0).getReg();
116           MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg);
117           assert(I != MRI->use_end());
118           if (++I == MRI->use_end())
119             // only one use, which must be this DEBUG_VALUE.
120             MI->getOperand(0).setReg(0U);
121         }
122       }
123 
124       // If the instruction is dead, delete it!
125       if (isDead(MI)) {
126         DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
127         AnyChanges = true;
128         MI->eraseFromParent();
129         MIE = MBB->rend();
130         // MII is now pointing to the next instruction to process,
131         // so don't increment it.
132         continue;
133       }
134 
135       // Record the physreg defs.
136       for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
137         const MachineOperand &MO = MI->getOperand(i);
138         if (MO.isReg() && MO.isDef()) {
139           unsigned Reg = MO.getReg();
140           if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
141             LivePhysRegs.reset(Reg);
142             // Check the subreg set, not the alias set, because a def
143             // of a super-register may still be partially live after
144             // this def.
145             for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
146                  *SubRegs; ++SubRegs)
147               LivePhysRegs.reset(*SubRegs);
148           }
149         }
150       }
151       // Record the physreg uses, after the defs, in case a physreg is
152       // both defined and used in the same instruction.
153       for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
154         const MachineOperand &MO = MI->getOperand(i);
155         if (MO.isReg() && MO.isUse()) {
156           unsigned Reg = MO.getReg();
157           if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
158             LivePhysRegs.set(Reg);
159             for (const unsigned *AliasSet = TRI->getAliasSet(Reg);
160                  *AliasSet; ++AliasSet)
161               LivePhysRegs.set(*AliasSet);
162           }
163         }
164       }
165 
166       // We didn't delete the current instruction, so increment MII to
167       // the next one.
168       ++MII;
169     }
170   }
171 
172   LivePhysRegs.clear();
173   return AnyChanges;
174 }
175