1 //===- DeadMachineInstructionElim.cpp - Remove dead machine instructions --===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This is an extremely simple MachineInstr-level dead-code-elimination pass.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "codegen-dce"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Pass.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Target/TargetMachine.h"
23 #include "llvm/ADT/Statistic.h"
24 using namespace llvm;
25 
26 STATISTIC(NumDeletes,          "Number of dead instructions deleted");
27 
28 namespace {
29   class DeadMachineInstructionElim : public MachineFunctionPass {
30     virtual bool runOnMachineFunction(MachineFunction &MF);
31 
32     const TargetRegisterInfo *TRI;
33     const MachineRegisterInfo *MRI;
34     const TargetInstrInfo *TII;
35     BitVector LivePhysRegs;
36 
37   public:
38     static char ID; // Pass identification, replacement for typeid
39     DeadMachineInstructionElim() : MachineFunctionPass(&ID) {}
40 
41   private:
42     bool isDead(const MachineInstr *MI) const;
43   };
44 }
45 char DeadMachineInstructionElim::ID = 0;
46 
47 static RegisterPass<DeadMachineInstructionElim>
48 Y("dead-mi-elimination",
49   "Remove dead machine instructions");
50 
51 FunctionPass *llvm::createDeadMachineInstructionElimPass() {
52   return new DeadMachineInstructionElim();
53 }
54 
55 bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const {
56   // Don't delete instructions with side effects.
57   bool SawStore = false;
58   if (!MI->isSafeToMove(TII, 0, SawStore) && !MI->isPHI())
59     return false;
60 
61   // Examine each operand.
62   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
63     const MachineOperand &MO = MI->getOperand(i);
64     if (MO.isReg() && MO.isDef()) {
65       unsigned Reg = MO.getReg();
66       if (TargetRegisterInfo::isPhysicalRegister(Reg) ?
67           LivePhysRegs[Reg] : !MRI->use_nodbg_empty(Reg)) {
68         // This def has a non-debug use. Don't delete the instruction!
69         return false;
70       }
71     }
72   }
73 
74   // If there are no defs with uses, the instruction is dead.
75   return true;
76 }
77 
78 bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
79   bool AnyChanges = false;
80   MRI = &MF.getRegInfo();
81   TRI = MF.getTarget().getRegisterInfo();
82   TII = MF.getTarget().getInstrInfo();
83 
84   // Compute a bitvector to represent all non-allocatable physregs.
85   BitVector NonAllocatableRegs = TRI->getAllocatableSet(MF);
86   NonAllocatableRegs.flip();
87 
88   // Loop over all instructions in all blocks, from bottom to top, so that it's
89   // more likely that chains of dependent but ultimately dead instructions will
90   // be cleaned up.
91   for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
92        I != E; ++I) {
93     MachineBasicBlock *MBB = &*I;
94 
95     // Start out assuming that all non-allocatable registers are live
96     // out of this block.
97     LivePhysRegs = NonAllocatableRegs;
98 
99     // Also add any explicit live-out physregs for this block.
100     if (!MBB->empty() && MBB->back().getDesc().isReturn())
101       for (MachineRegisterInfo::liveout_iterator LOI = MRI->liveout_begin(),
102            LOE = MRI->liveout_end(); LOI != LOE; ++LOI) {
103         unsigned Reg = *LOI;
104         if (TargetRegisterInfo::isPhysicalRegister(Reg))
105           LivePhysRegs.set(Reg);
106       }
107 
108     // Now scan the instructions and delete dead ones, tracking physreg
109     // liveness as we go.
110     for (MachineBasicBlock::reverse_iterator MII = MBB->rbegin(),
111          MIE = MBB->rend(); MII != MIE; ) {
112       MachineInstr *MI = &*MII;
113 
114       // If the instruction is dead, delete it!
115       if (isDead(MI)) {
116         DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
117         // It is possible that some DBG_VALUE instructions refer to this
118         // instruction.  Examine each def operand for such references;
119         // if found, mark the DBG_VALUE as undef (but don't delete it).
120         for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
121           const MachineOperand &MO = MI->getOperand(i);
122           if (!MO.isReg() || !MO.isDef())
123             continue;
124           unsigned Reg = MO.getReg();
125           if (!TargetRegisterInfo::isVirtualRegister(Reg))
126             continue;
127           MachineRegisterInfo::use_iterator nextI;
128           for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg),
129                E = MRI->use_end(); I!=E; I=nextI) {
130             nextI = llvm::next(I);  // I is invalidated by the setReg
131             MachineOperand& Use = I.getOperand();
132             MachineInstr *UseMI = Use.getParent();
133             if (UseMI==MI)
134               continue;
135             assert(Use.isDebug());
136             UseMI->getOperand(0).setReg(0U);
137           }
138         }
139         AnyChanges = true;
140         MI->eraseFromParent();
141         ++NumDeletes;
142         MIE = MBB->rend();
143         // MII is now pointing to the next instruction to process,
144         // so don't increment it.
145         continue;
146       }
147 
148       // Record the physreg defs.
149       for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
150         const MachineOperand &MO = MI->getOperand(i);
151         if (MO.isReg() && MO.isDef()) {
152           unsigned Reg = MO.getReg();
153           if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
154             LivePhysRegs.reset(Reg);
155             // Check the subreg set, not the alias set, because a def
156             // of a super-register may still be partially live after
157             // this def.
158             for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
159                  *SubRegs; ++SubRegs)
160               LivePhysRegs.reset(*SubRegs);
161           }
162         }
163       }
164       // Record the physreg uses, after the defs, in case a physreg is
165       // both defined and used in the same instruction.
166       for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
167         const MachineOperand &MO = MI->getOperand(i);
168         if (MO.isReg() && MO.isUse()) {
169           unsigned Reg = MO.getReg();
170           if (Reg != 0 && TargetRegisterInfo::isPhysicalRegister(Reg)) {
171             LivePhysRegs.set(Reg);
172             for (const unsigned *AliasSet = TRI->getAliasSet(Reg);
173                  *AliasSet; ++AliasSet)
174               LivePhysRegs.set(*AliasSet);
175           }
176         }
177       }
178 
179       // We didn't delete the current instruction, so increment MII to
180       // the next one.
181       ++MII;
182     }
183   }
184 
185   LivePhysRegs.clear();
186   return AnyChanges;
187 }
188