1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains support for writing dwarf debug info into asm files.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "DwarfExpression.h"
15 #include "DwarfDebug.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/CodeGen/AsmPrinter.h"
18 #include "llvm/Support/Dwarf.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Target/TargetSubtargetInfo.h"
22 
23 using namespace llvm;
24 
25 void DwarfExpression::AddReg(int DwarfReg, const char *Comment) {
26   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
27   if (DwarfReg < 32) {
28     EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
29   } else {
30     EmitOp(dwarf::DW_OP_regx, Comment);
31     EmitUnsigned(DwarfReg);
32   }
33 }
34 
35 void DwarfExpression::AddRegIndirect(int DwarfReg, int Offset, bool Deref) {
36   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
37   if (DwarfReg < 32) {
38     EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
39   } else {
40     EmitOp(dwarf::DW_OP_bregx);
41     EmitUnsigned(DwarfReg);
42   }
43   EmitSigned(Offset);
44   if (Deref)
45     EmitOp(dwarf::DW_OP_deref);
46 }
47 
48 void DwarfExpression::AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
49   assert(SizeInBits > 0 && "piece has size zero");
50   const unsigned SizeOfByte = 8;
51   if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
52     EmitOp(dwarf::DW_OP_bit_piece);
53     EmitUnsigned(SizeInBits);
54     EmitUnsigned(OffsetInBits);
55   } else {
56     EmitOp(dwarf::DW_OP_piece);
57     unsigned ByteSize = SizeInBits / SizeOfByte;
58     EmitUnsigned(ByteSize);
59   }
60 }
61 
62 void DwarfExpression::AddShr(unsigned ShiftBy) {
63   EmitOp(dwarf::DW_OP_constu);
64   EmitUnsigned(ShiftBy);
65   EmitOp(dwarf::DW_OP_shr);
66 }
67 
68 bool DwarfExpression::AddMachineRegIndirect(unsigned MachineReg, int Offset) {
69   int DwarfReg = TRI.getDwarfRegNum(MachineReg, false);
70   if (DwarfReg < 0)
71     return false;
72 
73   if (isFrameRegister(MachineReg)) {
74     // If variable offset is based in frame register then use fbreg.
75     EmitOp(dwarf::DW_OP_fbreg);
76     EmitSigned(Offset);
77   } else {
78     AddRegIndirect(DwarfReg, Offset);
79   }
80   return true;
81 }
82 
83 bool DwarfExpression::AddMachineRegPiece(unsigned MachineReg,
84                                          unsigned PieceSizeInBits,
85                                          unsigned PieceOffsetInBits) {
86   if (!TRI.isPhysicalRegister(MachineReg))
87     return false;
88 
89   int Reg = TRI.getDwarfRegNum(MachineReg, false);
90 
91   // If this is a valid register number, emit it.
92   if (Reg >= 0) {
93     AddReg(Reg);
94     if (PieceSizeInBits)
95       AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
96     return true;
97   }
98 
99   // Walk up the super-register chain until we find a valid number.
100   // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
101   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
102     Reg = TRI.getDwarfRegNum(*SR, false);
103     if (Reg >= 0) {
104       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
105       unsigned Size = TRI.getSubRegIdxSize(Idx);
106       unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
107       AddReg(Reg, "super-register");
108       if (PieceOffsetInBits == RegOffset) {
109         AddOpPiece(Size, RegOffset);
110       } else {
111         // If this is part of a variable in a sub-register at a
112         // non-zero offset, we need to manually shift the value into
113         // place, since the DW_OP_piece describes the part of the
114         // variable, not the position of the subregister.
115         if (RegOffset)
116           AddShr(RegOffset);
117         AddOpPiece(Size, PieceOffsetInBits);
118       }
119       return true;
120     }
121   }
122 
123   // Otherwise, attempt to find a covering set of sub-register numbers.
124   // For example, Q0 on ARM is a composition of D0+D1.
125   //
126   // Keep track of the current position so we can emit the more
127   // efficient DW_OP_piece.
128   unsigned CurPos = PieceOffsetInBits;
129   // The size of the register in bits, assuming 8 bits per byte.
130   unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
131   // Keep track of the bits in the register we already emitted, so we
132   // can avoid emitting redundant aliasing subregs.
133   SmallBitVector Coverage(RegSize, false);
134   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
135     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
136     unsigned Size = TRI.getSubRegIdxSize(Idx);
137     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
138     Reg = TRI.getDwarfRegNum(*SR, false);
139 
140     // Intersection between the bits we already emitted and the bits
141     // covered by this subregister.
142     SmallBitVector Intersection(RegSize, false);
143     Intersection.set(Offset, Offset + Size);
144     Intersection ^= Coverage;
145 
146     // If this sub-register has a DWARF number and we haven't covered
147     // its range, emit a DWARF piece for it.
148     if (Reg >= 0 && Intersection.any()) {
149       AddReg(Reg, "sub-register");
150       AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
151       CurPos = Offset + Size;
152 
153       // Mark it as emitted.
154       Coverage.set(Offset, Offset + Size);
155     }
156   }
157 
158   return CurPos > PieceOffsetInBits;
159 }
160 
161 void DwarfExpression::AddSignedConstant(int Value) {
162   EmitOp(dwarf::DW_OP_consts);
163   EmitSigned(Value);
164   // The proper way to describe a constant value is
165   // DW_OP_constu <const>, DW_OP_stack_value.
166   // Unfortunately, DW_OP_stack_value was not available until DWARF-4,
167   // so we will continue to generate DW_OP_constu <const> for DWARF-2
168   // and DWARF-3. Technically, this is incorrect since DW_OP_const <const>
169   // actually describes a value at a constant addess, not a constant value.
170   // However, in the past there was no better way  to describe a constant
171   // value, so the producers and consumers started to rely on heuristics
172   // to disambiguate the value vs. location status of the expression.
173   // See PR21176 for more details.
174   if (DwarfVersion >= 4)
175     EmitOp(dwarf::DW_OP_stack_value);
176 }
177 
178 void DwarfExpression::AddUnsignedConstant(unsigned Value) {
179   EmitOp(dwarf::DW_OP_constu);
180   EmitUnsigned(Value);
181   // cf. comment in DwarfExpression::AddSignedConstant().
182   if (DwarfVersion >= 4)
183     EmitOp(dwarf::DW_OP_stack_value);
184 }
185 
186 static unsigned getOffsetOrZero(unsigned OffsetInBits,
187                                 unsigned PieceOffsetInBits) {
188   if (OffsetInBits == PieceOffsetInBits)
189     return 0;
190   assert(OffsetInBits >= PieceOffsetInBits && "overlapping pieces");
191   return OffsetInBits;
192 }
193 
194 bool DwarfExpression::AddMachineRegExpression(DIExpression Expr,
195                                               unsigned MachineReg,
196                                               unsigned PieceOffsetInBits) {
197   auto I = Expr.begin();
198   // Pattern-match combinations for which more efficient representations exist
199   // first.
200   if (I == Expr.end())
201     return AddMachineRegPiece(MachineReg);
202 
203   bool ValidReg = false;
204   switch (*I) {
205   case dwarf::DW_OP_bit_piece: {
206     unsigned OffsetInBits = I->getArg(1);
207     unsigned SizeInBits   = I->getArg(2);
208     // Piece always comes at the end of the expression.
209     return AddMachineRegPiece(MachineReg, SizeInBits,
210                getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
211   }
212   case dwarf::DW_OP_plus:
213     // [DW_OP_reg,Offset,DW_OP_plus,DW_OP_deref] --> [DW_OP_breg,Offset].
214     if (I->getNext() == dwarf::DW_OP_deref) {
215       unsigned Offset = I->getArg(1);
216       ValidReg = AddMachineRegIndirect(MachineReg, Offset);
217       std::advance(I, 2);
218       break;
219     } else
220       ValidReg = AddMachineRegPiece(MachineReg);
221   case dwarf::DW_OP_deref:
222     // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
223     ValidReg = AddMachineRegIndirect(MachineReg);
224     ++I;
225     break;
226   default:
227     llvm_unreachable("unsupported operand");
228   }
229 
230   if (!ValidReg)
231     return false;
232 
233   // Emit remaining elements of the expression.
234   AddExpression(I, Expr.end(), PieceOffsetInBits);
235   return true;
236 }
237 
238 void DwarfExpression::AddExpression(DIExpression::iterator I,
239                                     DIExpression::iterator E,
240                                     unsigned PieceOffsetInBits) {
241   for (; I != E; ++I) {
242     switch (*I) {
243     case dwarf::DW_OP_bit_piece: {
244       unsigned OffsetInBits = I->getArg(1);
245       unsigned SizeInBits   = I->getArg(2);
246       AddOpPiece(SizeInBits, getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
247       break;
248     }
249     case dwarf::DW_OP_plus:
250       EmitOp(dwarf::DW_OP_plus_uconst);
251       EmitUnsigned(I->getArg(1));
252       break;
253     case dwarf::DW_OP_deref:
254       EmitOp(dwarf::DW_OP_deref);
255       break;
256     default:
257       llvm_unreachable("unhandled opcode found in DIExpression");
258     }
259   }
260 }
261