1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains support for writing dwarf debug info into asm files.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "DwarfExpression.h"
14 #include "DwarfCompileUnit.h"
15 #include "llvm/ADT/APInt.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/BinaryFormat/Dwarf.h"
18 #include "llvm/CodeGen/Register.h"
19 #include "llvm/CodeGen/TargetRegisterInfo.h"
20 #include "llvm/IR/DebugInfoMetadata.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include <algorithm>
23 #include <cassert>
24 #include <cstdint>
25 
26 using namespace llvm;
27 
28 void DwarfExpression::emitConstu(uint64_t Value) {
29   if (Value < 32)
30     emitOp(dwarf::DW_OP_lit0 + Value);
31   else if (Value == std::numeric_limits<uint64_t>::max()) {
32     // Only do this for 64-bit values as the DWARF expression stack uses
33     // target-address-size values.
34     emitOp(dwarf::DW_OP_lit0);
35     emitOp(dwarf::DW_OP_not);
36   } else {
37     emitOp(dwarf::DW_OP_constu);
38     emitUnsigned(Value);
39   }
40 }
41 
42 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
43  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
44  assert((isUnknownLocation() || isRegisterLocation()) &&
45         "location description already locked down");
46  LocationKind = Register;
47  if (DwarfReg < 32) {
48    emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
49   } else {
50     emitOp(dwarf::DW_OP_regx, Comment);
51     emitUnsigned(DwarfReg);
52   }
53 }
54 
55 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
56   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
57   assert(!isRegisterLocation() && "location description already locked down");
58   if (DwarfReg < 32) {
59     emitOp(dwarf::DW_OP_breg0 + DwarfReg);
60   } else {
61     emitOp(dwarf::DW_OP_bregx);
62     emitUnsigned(DwarfReg);
63   }
64   emitSigned(Offset);
65 }
66 
67 void DwarfExpression::addFBReg(int Offset) {
68   emitOp(dwarf::DW_OP_fbreg);
69   emitSigned(Offset);
70 }
71 
72 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
73   if (!SizeInBits)
74     return;
75 
76   const unsigned SizeOfByte = 8;
77   if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
78     emitOp(dwarf::DW_OP_bit_piece);
79     emitUnsigned(SizeInBits);
80     emitUnsigned(OffsetInBits);
81   } else {
82     emitOp(dwarf::DW_OP_piece);
83     unsigned ByteSize = SizeInBits / SizeOfByte;
84     emitUnsigned(ByteSize);
85   }
86   this->OffsetInBits += SizeInBits;
87 }
88 
89 void DwarfExpression::addShr(unsigned ShiftBy) {
90   emitConstu(ShiftBy);
91   emitOp(dwarf::DW_OP_shr);
92 }
93 
94 void DwarfExpression::addAnd(unsigned Mask) {
95   emitConstu(Mask);
96   emitOp(dwarf::DW_OP_and);
97 }
98 
99 bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
100                                     unsigned MachineReg, unsigned MaxSize) {
101   if (!llvm::Register::isPhysicalRegister(MachineReg)) {
102     if (isFrameRegister(TRI, MachineReg)) {
103       DwarfRegs.push_back({-1, 0, nullptr});
104       return true;
105     }
106     return false;
107   }
108 
109   int Reg = TRI.getDwarfRegNum(MachineReg, false);
110 
111   // If this is a valid register number, emit it.
112   if (Reg >= 0) {
113     DwarfRegs.push_back({Reg, 0, nullptr});
114     return true;
115   }
116 
117   // Walk up the super-register chain until we find a valid number.
118   // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
119   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
120     Reg = TRI.getDwarfRegNum(*SR, false);
121     if (Reg >= 0) {
122       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
123       unsigned Size = TRI.getSubRegIdxSize(Idx);
124       unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
125       DwarfRegs.push_back({Reg, 0, "super-register"});
126       // Use a DW_OP_bit_piece to describe the sub-register.
127       setSubRegisterPiece(Size, RegOffset);
128       return true;
129     }
130   }
131 
132   // Otherwise, attempt to find a covering set of sub-register numbers.
133   // For example, Q0 on ARM is a composition of D0+D1.
134   unsigned CurPos = 0;
135   // The size of the register in bits.
136   const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
137   unsigned RegSize = TRI.getRegSizeInBits(*RC);
138   // Keep track of the bits in the register we already emitted, so we
139   // can avoid emitting redundant aliasing subregs. Because this is
140   // just doing a greedy scan of all subregisters, it is possible that
141   // this doesn't find a combination of subregisters that fully cover
142   // the register (even though one may exist).
143   SmallBitVector Coverage(RegSize, false);
144   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
145     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
146     unsigned Size = TRI.getSubRegIdxSize(Idx);
147     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
148     Reg = TRI.getDwarfRegNum(*SR, false);
149     if (Reg < 0)
150       continue;
151 
152     // Intersection between the bits we already emitted and the bits
153     // covered by this subregister.
154     SmallBitVector CurSubReg(RegSize, false);
155     CurSubReg.set(Offset, Offset + Size);
156 
157     // If this sub-register has a DWARF number and we haven't covered
158     // its range, emit a DWARF piece for it.
159     if (CurSubReg.test(Coverage)) {
160       // Emit a piece for any gap in the coverage.
161       if (Offset > CurPos)
162         DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"});
163       DwarfRegs.push_back(
164           {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
165       if (Offset >= MaxSize)
166         break;
167 
168       // Mark it as emitted.
169       Coverage.set(Offset, Offset + Size);
170       CurPos = Offset + Size;
171     }
172   }
173   // Failed to find any DWARF encoding.
174   if (CurPos == 0)
175     return false;
176   // Found a partial or complete DWARF encoding.
177   if (CurPos < RegSize)
178     DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
179   return true;
180 }
181 
182 void DwarfExpression::addStackValue() {
183   if (DwarfVersion >= 4)
184     emitOp(dwarf::DW_OP_stack_value);
185 }
186 
187 void DwarfExpression::addSignedConstant(int64_t Value) {
188   assert(isImplicitLocation() || isUnknownLocation());
189   LocationKind = Implicit;
190   emitOp(dwarf::DW_OP_consts);
191   emitSigned(Value);
192 }
193 
194 void DwarfExpression::addUnsignedConstant(uint64_t Value) {
195   assert(isImplicitLocation() || isUnknownLocation());
196   LocationKind = Implicit;
197   emitConstu(Value);
198 }
199 
200 void DwarfExpression::addUnsignedConstant(const APInt &Value) {
201   assert(isImplicitLocation() || isUnknownLocation());
202   LocationKind = Implicit;
203 
204   unsigned Size = Value.getBitWidth();
205   const uint64_t *Data = Value.getRawData();
206 
207   // Chop it up into 64-bit pieces, because that's the maximum that
208   // addUnsignedConstant takes.
209   unsigned Offset = 0;
210   while (Offset < Size) {
211     addUnsignedConstant(*Data++);
212     if (Offset == 0 && Size <= 64)
213       break;
214     addStackValue();
215     addOpPiece(std::min(Size - Offset, 64u), Offset);
216     Offset += 64;
217   }
218 }
219 
220 bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
221                                               DIExpressionCursor &ExprCursor,
222                                               unsigned MachineReg,
223                                               unsigned FragmentOffsetInBits) {
224   auto Fragment = ExprCursor.getFragmentInfo();
225   if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
226     LocationKind = Unknown;
227     return false;
228   }
229 
230   bool HasComplexExpression = false;
231   auto Op = ExprCursor.peek();
232   if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
233     HasComplexExpression = true;
234 
235   // If the register can only be described by a complex expression (i.e.,
236   // multiple subregisters) it doesn't safely compose with another complex
237   // expression. For example, it is not possible to apply a DW_OP_deref
238   // operation to multiple DW_OP_pieces.
239   if (HasComplexExpression && DwarfRegs.size() > 1) {
240     DwarfRegs.clear();
241     LocationKind = Unknown;
242     return false;
243   }
244 
245   // Handle simple register locations. If we are supposed to emit
246   // a call site parameter expression and if that expression is just a register
247   // location, emit it with addBReg and offset 0, because we should emit a DWARF
248   // expression representing a value, rather than a location.
249   if (!isMemoryLocation() && !HasComplexExpression && (!isParameterValue() ||
250                                                        isEntryValue())) {
251     for (auto &Reg : DwarfRegs) {
252       if (Reg.DwarfRegNo >= 0)
253         addReg(Reg.DwarfRegNo, Reg.Comment);
254       addOpPiece(Reg.Size);
255     }
256 
257     if (isEntryValue())
258       finalizeEntryValue();
259 
260     if (isEntryValue() && !isParameterValue() && DwarfVersion >= 4)
261       emitOp(dwarf::DW_OP_stack_value);
262 
263     DwarfRegs.clear();
264     return true;
265   }
266 
267   // Don't emit locations that cannot be expressed without DW_OP_stack_value.
268   if (DwarfVersion < 4)
269     if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
270           return Op.getOp() == dwarf::DW_OP_stack_value;
271         })) {
272       DwarfRegs.clear();
273       LocationKind = Unknown;
274       return false;
275     }
276 
277   assert(DwarfRegs.size() == 1);
278   auto Reg = DwarfRegs[0];
279   bool FBReg = isFrameRegister(TRI, MachineReg);
280   int SignedOffset = 0;
281   assert(Reg.Size == 0 && "subregister has same size as superregister");
282 
283   // Pattern-match combinations for which more efficient representations exist.
284   // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
285   if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
286     uint64_t Offset = Op->getArg(0);
287     uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
288     if (Offset <= IntMax) {
289       SignedOffset = Offset;
290       ExprCursor.take();
291     }
292   }
293 
294   // [Reg, DW_OP_constu, Offset, DW_OP_plus]  --> [DW_OP_breg, Offset]
295   // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
296   // If Reg is a subregister we need to mask it out before subtracting.
297   if (Op && Op->getOp() == dwarf::DW_OP_constu) {
298     uint64_t Offset = Op->getArg(0);
299     uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
300     auto N = ExprCursor.peekNext();
301     if (N && N->getOp() == dwarf::DW_OP_plus && Offset <= IntMax) {
302       SignedOffset = Offset;
303       ExprCursor.consume(2);
304     } else if (N && N->getOp() == dwarf::DW_OP_minus &&
305                !SubRegisterSizeInBits && Offset <= IntMax + 1) {
306       SignedOffset = -static_cast<int64_t>(Offset);
307       ExprCursor.consume(2);
308     }
309   }
310 
311   if (FBReg)
312     addFBReg(SignedOffset);
313   else
314     addBReg(Reg.DwarfRegNo, SignedOffset);
315   DwarfRegs.clear();
316   return true;
317 }
318 
319 void DwarfExpression::beginEntryValueExpression(
320     DIExpressionCursor &ExprCursor) {
321   auto Op = ExprCursor.take();
322   (void)Op;
323   assert(Op && Op->getOp() == dwarf::DW_OP_LLVM_entry_value);
324   assert(!isMemoryLocation() &&
325          "We don't support entry values of memory locations yet");
326   assert(!IsEmittingEntryValue && "Already emitting entry value?");
327   assert(Op->getArg(0) == 1 &&
328          "Can currently only emit entry values covering a single operation");
329 
330   emitOp(CU.getDwarf5OrGNULocationAtom(dwarf::DW_OP_entry_value));
331   IsEmittingEntryValue = true;
332   enableTemporaryBuffer();
333 }
334 
335 void DwarfExpression::finalizeEntryValue() {
336   assert(IsEmittingEntryValue && "Entry value not open?");
337   disableTemporaryBuffer();
338 
339   // Emit the entry value's size operand.
340   unsigned Size = getTemporaryBufferSize();
341   emitUnsigned(Size);
342 
343   // Emit the entry value's DWARF block operand.
344   commitTemporaryBuffer();
345 
346   IsEmittingEntryValue = false;
347 }
348 
349 /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
350 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
351   while (ExprCursor) {
352     auto Op = ExprCursor.take();
353     switch (Op->getOp()) {
354     case dwarf::DW_OP_deref:
355     case dwarf::DW_OP_LLVM_fragment:
356       break;
357     default:
358       return false;
359     }
360   }
361   return true;
362 }
363 
364 void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
365                                     unsigned FragmentOffsetInBits) {
366   // If we need to mask out a subregister, do it now, unless the next
367   // operation would emit an OpPiece anyway.
368   auto N = ExprCursor.peek();
369   if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
370     maskSubRegister();
371 
372   Optional<DIExpression::ExprOperand> PrevConvertOp = None;
373 
374   while (ExprCursor) {
375     auto Op = ExprCursor.take();
376     uint64_t OpNum = Op->getOp();
377 
378     if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) {
379       emitOp(OpNum);
380       continue;
381     } else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) {
382       addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0));
383       continue;
384     }
385 
386     switch (OpNum) {
387     case dwarf::DW_OP_LLVM_fragment: {
388       unsigned SizeInBits = Op->getArg(1);
389       unsigned FragmentOffset = Op->getArg(0);
390       // The fragment offset must have already been adjusted by emitting an
391       // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
392       // location.
393       assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
394 
395       // If addMachineReg already emitted DW_OP_piece operations to represent
396       // a super-register by splicing together sub-registers, subtract the size
397       // of the pieces that was already emitted.
398       SizeInBits -= OffsetInBits - FragmentOffset;
399 
400       // If addMachineReg requested a DW_OP_bit_piece to stencil out a
401       // sub-register that is smaller than the current fragment's size, use it.
402       if (SubRegisterSizeInBits)
403         SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
404 
405       // Emit a DW_OP_stack_value for implicit location descriptions.
406       if (isImplicitLocation())
407         addStackValue();
408 
409       // Emit the DW_OP_piece.
410       addOpPiece(SizeInBits, SubRegisterOffsetInBits);
411       setSubRegisterPiece(0, 0);
412       // Reset the location description kind.
413       LocationKind = Unknown;
414       return;
415     }
416     case dwarf::DW_OP_plus_uconst:
417       assert(!isRegisterLocation());
418       emitOp(dwarf::DW_OP_plus_uconst);
419       emitUnsigned(Op->getArg(0));
420       break;
421     case dwarf::DW_OP_plus:
422     case dwarf::DW_OP_minus:
423     case dwarf::DW_OP_mul:
424     case dwarf::DW_OP_div:
425     case dwarf::DW_OP_mod:
426     case dwarf::DW_OP_or:
427     case dwarf::DW_OP_and:
428     case dwarf::DW_OP_xor:
429     case dwarf::DW_OP_shl:
430     case dwarf::DW_OP_shr:
431     case dwarf::DW_OP_shra:
432     case dwarf::DW_OP_lit0:
433     case dwarf::DW_OP_not:
434     case dwarf::DW_OP_dup:
435       emitOp(OpNum);
436       break;
437     case dwarf::DW_OP_deref:
438       assert(!isRegisterLocation());
439       if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor))
440         // Turning this into a memory location description makes the deref
441         // implicit.
442         LocationKind = Memory;
443       else
444         emitOp(dwarf::DW_OP_deref);
445       break;
446     case dwarf::DW_OP_constu:
447       assert(!isRegisterLocation());
448       emitConstu(Op->getArg(0));
449       break;
450     case dwarf::DW_OP_LLVM_convert: {
451       unsigned BitSize = Op->getArg(0);
452       dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
453       if (DwarfVersion >= 5) {
454         emitOp(dwarf::DW_OP_convert);
455         // Reuse the base_type if we already have one in this CU otherwise we
456         // create a new one.
457         unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
458         for (; I != E; ++I)
459           if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
460               CU.ExprRefedBaseTypes[I].Encoding == Encoding)
461             break;
462 
463         if (I == E)
464           CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
465 
466         // If targeting a location-list; simply emit the index into the raw
467         // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
468         // fitted with means to extract it later.
469         // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
470         // (containing the index and a resolve mechanism during emit) into the
471         // DIE value list.
472         emitBaseTypeRef(I);
473       } else {
474         if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
475           if (Encoding == dwarf::DW_ATE_signed)
476             emitLegacySExt(PrevConvertOp->getArg(0));
477           else if (Encoding == dwarf::DW_ATE_unsigned)
478             emitLegacyZExt(PrevConvertOp->getArg(0));
479           PrevConvertOp = None;
480         } else {
481           PrevConvertOp = Op;
482         }
483       }
484       break;
485     }
486     case dwarf::DW_OP_stack_value:
487       LocationKind = Implicit;
488       break;
489     case dwarf::DW_OP_swap:
490       assert(!isRegisterLocation());
491       emitOp(dwarf::DW_OP_swap);
492       break;
493     case dwarf::DW_OP_xderef:
494       assert(!isRegisterLocation());
495       emitOp(dwarf::DW_OP_xderef);
496       break;
497     case dwarf::DW_OP_deref_size:
498       emitOp(dwarf::DW_OP_deref_size);
499       emitData1(Op->getArg(0));
500       break;
501     case dwarf::DW_OP_LLVM_tag_offset:
502       TagOffset = Op->getArg(0);
503       break;
504     case dwarf::DW_OP_regx:
505       emitOp(dwarf::DW_OP_regx);
506       emitUnsigned(Op->getArg(0));
507       break;
508     case dwarf::DW_OP_bregx:
509       emitOp(dwarf::DW_OP_bregx);
510       emitUnsigned(Op->getArg(0));
511       emitSigned(Op->getArg(1));
512       break;
513     default:
514       llvm_unreachable("unhandled opcode found in expression");
515     }
516   }
517 
518   if (isImplicitLocation() && !isParameterValue())
519     // Turn this into an implicit location description.
520     addStackValue();
521 }
522 
523 /// add masking operations to stencil out a subregister.
524 void DwarfExpression::maskSubRegister() {
525   assert(SubRegisterSizeInBits && "no subregister was registered");
526   if (SubRegisterOffsetInBits > 0)
527     addShr(SubRegisterOffsetInBits);
528   uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
529   addAnd(Mask);
530 }
531 
532 void DwarfExpression::finalize() {
533   assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
534   // Emit any outstanding DW_OP_piece operations to mask out subregisters.
535   if (SubRegisterSizeInBits == 0)
536     return;
537   // Don't emit a DW_OP_piece for a subregister at offset 0.
538   if (SubRegisterOffsetInBits == 0)
539     return;
540   addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
541 }
542 
543 void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
544   if (!Expr || !Expr->isFragment())
545     return;
546 
547   uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
548   assert(FragmentOffset >= OffsetInBits &&
549          "overlapping or duplicate fragments");
550   if (FragmentOffset > OffsetInBits)
551     addOpPiece(FragmentOffset - OffsetInBits);
552   OffsetInBits = FragmentOffset;
553 }
554 
555 void DwarfExpression::emitLegacySExt(unsigned FromBits) {
556   // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
557   emitOp(dwarf::DW_OP_dup);
558   emitOp(dwarf::DW_OP_constu);
559   emitUnsigned(FromBits - 1);
560   emitOp(dwarf::DW_OP_shr);
561   emitOp(dwarf::DW_OP_lit0);
562   emitOp(dwarf::DW_OP_not);
563   emitOp(dwarf::DW_OP_mul);
564   emitOp(dwarf::DW_OP_constu);
565   emitUnsigned(FromBits);
566   emitOp(dwarf::DW_OP_shl);
567   emitOp(dwarf::DW_OP_or);
568 }
569 
570 void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
571   // (X & (1 << FromBits - 1))
572   emitOp(dwarf::DW_OP_constu);
573   emitUnsigned((1ULL << FromBits) - 1);
574   emitOp(dwarf::DW_OP_and);
575 }
576