1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains support for writing dwarf debug info into asm files.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "DwarfExpression.h"
14 #include "DwarfCompileUnit.h"
15 #include "llvm/ADT/APInt.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/BinaryFormat/Dwarf.h"
18 #include "llvm/CodeGen/TargetRegisterInfo.h"
19 #include "llvm/IR/DebugInfoMetadata.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include <algorithm>
22 #include <cassert>
23 #include <cstdint>
24 
25 using namespace llvm;
26 
27 void DwarfExpression::emitConstu(uint64_t Value) {
28   if (Value < 32)
29     emitOp(dwarf::DW_OP_lit0 + Value);
30   else if (Value == std::numeric_limits<uint64_t>::max()) {
31     // Only do this for 64-bit values as the DWARF expression stack uses
32     // target-address-size values.
33     emitOp(dwarf::DW_OP_lit0);
34     emitOp(dwarf::DW_OP_not);
35   } else {
36     emitOp(dwarf::DW_OP_constu);
37     emitUnsigned(Value);
38   }
39 }
40 
41 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
42  assert(DwarfReg >= 0 && "invalid negative dwarf register number");
43  assert((isUnknownLocation() || isRegisterLocation()) &&
44         "location description already locked down");
45  LocationKind = Register;
46  if (DwarfReg < 32) {
47    emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
48   } else {
49     emitOp(dwarf::DW_OP_regx, Comment);
50     emitUnsigned(DwarfReg);
51   }
52 }
53 
54 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
55   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
56   assert(!isRegisterLocation() && "location description already locked down");
57   if (DwarfReg < 32) {
58     emitOp(dwarf::DW_OP_breg0 + DwarfReg);
59   } else {
60     emitOp(dwarf::DW_OP_bregx);
61     emitUnsigned(DwarfReg);
62   }
63   emitSigned(Offset);
64 }
65 
66 void DwarfExpression::addFBReg(int Offset) {
67   emitOp(dwarf::DW_OP_fbreg);
68   emitSigned(Offset);
69 }
70 
71 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
72   if (!SizeInBits)
73     return;
74 
75   const unsigned SizeOfByte = 8;
76   if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
77     emitOp(dwarf::DW_OP_bit_piece);
78     emitUnsigned(SizeInBits);
79     emitUnsigned(OffsetInBits);
80   } else {
81     emitOp(dwarf::DW_OP_piece);
82     unsigned ByteSize = SizeInBits / SizeOfByte;
83     emitUnsigned(ByteSize);
84   }
85   this->OffsetInBits += SizeInBits;
86 }
87 
88 void DwarfExpression::addShr(unsigned ShiftBy) {
89   emitConstu(ShiftBy);
90   emitOp(dwarf::DW_OP_shr);
91 }
92 
93 void DwarfExpression::addAnd(unsigned Mask) {
94   emitConstu(Mask);
95   emitOp(dwarf::DW_OP_and);
96 }
97 
98 bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
99                                     unsigned MachineReg, unsigned MaxSize) {
100   if (!TRI.isPhysicalRegister(MachineReg)) {
101     if (isFrameRegister(TRI, MachineReg)) {
102       DwarfRegs.push_back({-1, 0, nullptr});
103       return true;
104     }
105     return false;
106   }
107 
108   int Reg = TRI.getDwarfRegNum(MachineReg, false);
109 
110   // If this is a valid register number, emit it.
111   if (Reg >= 0) {
112     DwarfRegs.push_back({Reg, 0, nullptr});
113     return true;
114   }
115 
116   // Walk up the super-register chain until we find a valid number.
117   // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
118   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
119     Reg = TRI.getDwarfRegNum(*SR, false);
120     if (Reg >= 0) {
121       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
122       unsigned Size = TRI.getSubRegIdxSize(Idx);
123       unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
124       DwarfRegs.push_back({Reg, 0, "super-register"});
125       // Use a DW_OP_bit_piece to describe the sub-register.
126       setSubRegisterPiece(Size, RegOffset);
127       return true;
128     }
129   }
130 
131   // Otherwise, attempt to find a covering set of sub-register numbers.
132   // For example, Q0 on ARM is a composition of D0+D1.
133   unsigned CurPos = 0;
134   // The size of the register in bits.
135   const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
136   unsigned RegSize = TRI.getRegSizeInBits(*RC);
137   // Keep track of the bits in the register we already emitted, so we
138   // can avoid emitting redundant aliasing subregs. Because this is
139   // just doing a greedy scan of all subregisters, it is possible that
140   // this doesn't find a combination of subregisters that fully cover
141   // the register (even though one may exist).
142   SmallBitVector Coverage(RegSize, false);
143   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
144     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
145     unsigned Size = TRI.getSubRegIdxSize(Idx);
146     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
147     Reg = TRI.getDwarfRegNum(*SR, false);
148     if (Reg < 0)
149       continue;
150 
151     // Intersection between the bits we already emitted and the bits
152     // covered by this subregister.
153     SmallBitVector CurSubReg(RegSize, false);
154     CurSubReg.set(Offset, Offset + Size);
155 
156     // If this sub-register has a DWARF number and we haven't covered
157     // its range, emit a DWARF piece for it.
158     if (CurSubReg.test(Coverage)) {
159       // Emit a piece for any gap in the coverage.
160       if (Offset > CurPos)
161         DwarfRegs.push_back({-1, Offset - CurPos, "no DWARF register encoding"});
162       DwarfRegs.push_back(
163           {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
164       if (Offset >= MaxSize)
165         break;
166 
167       // Mark it as emitted.
168       Coverage.set(Offset, Offset + Size);
169       CurPos = Offset + Size;
170     }
171   }
172   // Failed to find any DWARF encoding.
173   if (CurPos == 0)
174     return false;
175   // Found a partial or complete DWARF encoding.
176   if (CurPos < RegSize)
177     DwarfRegs.push_back({-1, RegSize - CurPos, "no DWARF register encoding"});
178   return true;
179 }
180 
181 void DwarfExpression::addStackValue() {
182   if (DwarfVersion >= 4)
183     emitOp(dwarf::DW_OP_stack_value);
184 }
185 
186 void DwarfExpression::addSignedConstant(int64_t Value) {
187   assert(isImplicitLocation() || isUnknownLocation());
188   LocationKind = Implicit;
189   emitOp(dwarf::DW_OP_consts);
190   emitSigned(Value);
191 }
192 
193 void DwarfExpression::addUnsignedConstant(uint64_t Value) {
194   assert(isImplicitLocation() || isUnknownLocation());
195   LocationKind = Implicit;
196   emitConstu(Value);
197 }
198 
199 void DwarfExpression::addUnsignedConstant(const APInt &Value) {
200   assert(isImplicitLocation() || isUnknownLocation());
201   LocationKind = Implicit;
202 
203   unsigned Size = Value.getBitWidth();
204   const uint64_t *Data = Value.getRawData();
205 
206   // Chop it up into 64-bit pieces, because that's the maximum that
207   // addUnsignedConstant takes.
208   unsigned Offset = 0;
209   while (Offset < Size) {
210     addUnsignedConstant(*Data++);
211     if (Offset == 0 && Size <= 64)
212       break;
213     addStackValue();
214     addOpPiece(std::min(Size - Offset, 64u), Offset);
215     Offset += 64;
216   }
217 }
218 
219 bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
220                                               DIExpressionCursor &ExprCursor,
221                                               unsigned MachineReg,
222                                               unsigned FragmentOffsetInBits) {
223   auto Fragment = ExprCursor.getFragmentInfo();
224   if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
225     LocationKind = Unknown;
226     return false;
227   }
228 
229   bool HasComplexExpression = false;
230   auto Op = ExprCursor.peek();
231   if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
232     HasComplexExpression = true;
233 
234   // If the register can only be described by a complex expression (i.e.,
235   // multiple subregisters) it doesn't safely compose with another complex
236   // expression. For example, it is not possible to apply a DW_OP_deref
237   // operation to multiple DW_OP_pieces.
238   if (HasComplexExpression && DwarfRegs.size() > 1) {
239     DwarfRegs.clear();
240     LocationKind = Unknown;
241     return false;
242   }
243 
244   // Handle simple register locations. If we are supposed to emit
245   // a call site parameter expression and if that expression is just a register
246   // location, emit it with addBReg and offset 0, because we should emit a DWARF
247   // expression representing a value, rather than a location.
248   if (!isMemoryLocation() && !HasComplexExpression && (!isParameterValue() ||
249                                                        isEntryValue())) {
250     for (auto &Reg : DwarfRegs) {
251       if (Reg.DwarfRegNo >= 0)
252         addReg(Reg.DwarfRegNo, Reg.Comment);
253       addOpPiece(Reg.Size);
254     }
255 
256     if (isEntryValue() && !isParameterValue() && DwarfVersion >= 4)
257       emitOp(dwarf::DW_OP_stack_value);
258 
259     DwarfRegs.clear();
260     return true;
261   }
262 
263   // Don't emit locations that cannot be expressed without DW_OP_stack_value.
264   if (DwarfVersion < 4)
265     if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
266           return Op.getOp() == dwarf::DW_OP_stack_value;
267         })) {
268       DwarfRegs.clear();
269       LocationKind = Unknown;
270       return false;
271     }
272 
273   assert(DwarfRegs.size() == 1);
274   auto Reg = DwarfRegs[0];
275   bool FBReg = isFrameRegister(TRI, MachineReg);
276   int SignedOffset = 0;
277   assert(Reg.Size == 0 && "subregister has same size as superregister");
278 
279   // Pattern-match combinations for which more efficient representations exist.
280   // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
281   if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
282     SignedOffset = Op->getArg(0);
283     ExprCursor.take();
284   }
285 
286   // [Reg, DW_OP_constu, Offset, DW_OP_plus]  --> [DW_OP_breg, Offset]
287   // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
288   // If Reg is a subregister we need to mask it out before subtracting.
289   if (Op && Op->getOp() == dwarf::DW_OP_constu) {
290     auto N = ExprCursor.peekNext();
291     if (N && (N->getOp() == dwarf::DW_OP_plus ||
292              (N->getOp() == dwarf::DW_OP_minus && !SubRegisterSizeInBits))) {
293       int Offset = Op->getArg(0);
294       SignedOffset = (N->getOp() == dwarf::DW_OP_minus) ? -Offset : Offset;
295       ExprCursor.consume(2);
296     }
297   }
298 
299   if (FBReg)
300     addFBReg(SignedOffset);
301   else
302     addBReg(Reg.DwarfRegNo, SignedOffset);
303   DwarfRegs.clear();
304   return true;
305 }
306 
307 void DwarfExpression::addEntryValueExpression(DIExpressionCursor &ExprCursor) {
308   auto Op = ExprCursor.take();
309   assert(Op && Op->getOp() == dwarf::DW_OP_entry_value);
310   assert(!isMemoryLocation() &&
311          "We don't support entry values of memory locations yet");
312 
313   if (DwarfVersion >= 5)
314     emitOp(dwarf::DW_OP_entry_value);
315   else
316     emitOp(dwarf::DW_OP_GNU_entry_value);
317   emitUnsigned(Op->getArg(0));
318 }
319 
320 /// Assuming a well-formed expression, match "DW_OP_deref* DW_OP_LLVM_fragment?".
321 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
322   while (ExprCursor) {
323     auto Op = ExprCursor.take();
324     switch (Op->getOp()) {
325     case dwarf::DW_OP_deref:
326     case dwarf::DW_OP_LLVM_fragment:
327       break;
328     default:
329       return false;
330     }
331   }
332   return true;
333 }
334 
335 void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
336                                     unsigned FragmentOffsetInBits) {
337   // If we need to mask out a subregister, do it now, unless the next
338   // operation would emit an OpPiece anyway.
339   auto N = ExprCursor.peek();
340   if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
341     maskSubRegister();
342 
343   Optional<DIExpression::ExprOperand> PrevConvertOp = None;
344 
345   while (ExprCursor) {
346     auto Op = ExprCursor.take();
347     uint64_t OpNum = Op->getOp();
348 
349     if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) {
350       emitOp(OpNum);
351       continue;
352     } else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) {
353       addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0));
354       continue;
355     }
356 
357     switch (OpNum) {
358     case dwarf::DW_OP_LLVM_fragment: {
359       unsigned SizeInBits = Op->getArg(1);
360       unsigned FragmentOffset = Op->getArg(0);
361       // The fragment offset must have already been adjusted by emitting an
362       // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
363       // location.
364       assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
365 
366       // If addMachineReg already emitted DW_OP_piece operations to represent
367       // a super-register by splicing together sub-registers, subtract the size
368       // of the pieces that was already emitted.
369       SizeInBits -= OffsetInBits - FragmentOffset;
370 
371       // If addMachineReg requested a DW_OP_bit_piece to stencil out a
372       // sub-register that is smaller than the current fragment's size, use it.
373       if (SubRegisterSizeInBits)
374         SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
375 
376       // Emit a DW_OP_stack_value for implicit location descriptions.
377       if (isImplicitLocation())
378         addStackValue();
379 
380       // Emit the DW_OP_piece.
381       addOpPiece(SizeInBits, SubRegisterOffsetInBits);
382       setSubRegisterPiece(0, 0);
383       // Reset the location description kind.
384       LocationKind = Unknown;
385       return;
386     }
387     case dwarf::DW_OP_plus_uconst:
388       assert(!isRegisterLocation());
389       emitOp(dwarf::DW_OP_plus_uconst);
390       emitUnsigned(Op->getArg(0));
391       break;
392     case dwarf::DW_OP_plus:
393     case dwarf::DW_OP_minus:
394     case dwarf::DW_OP_mul:
395     case dwarf::DW_OP_div:
396     case dwarf::DW_OP_mod:
397     case dwarf::DW_OP_or:
398     case dwarf::DW_OP_and:
399     case dwarf::DW_OP_xor:
400     case dwarf::DW_OP_shl:
401     case dwarf::DW_OP_shr:
402     case dwarf::DW_OP_shra:
403     case dwarf::DW_OP_lit0:
404     case dwarf::DW_OP_not:
405     case dwarf::DW_OP_dup:
406       emitOp(OpNum);
407       break;
408     case dwarf::DW_OP_deref:
409       assert(!isRegisterLocation());
410       if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor))
411         // Turning this into a memory location description makes the deref
412         // implicit.
413         LocationKind = Memory;
414       else
415         emitOp(dwarf::DW_OP_deref);
416       break;
417     case dwarf::DW_OP_constu:
418       assert(!isRegisterLocation());
419       emitConstu(Op->getArg(0));
420       break;
421     case dwarf::DW_OP_LLVM_convert: {
422       unsigned BitSize = Op->getArg(0);
423       dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
424       if (DwarfVersion >= 5) {
425         emitOp(dwarf::DW_OP_convert);
426         // Reuse the base_type if we already have one in this CU otherwise we
427         // create a new one.
428         unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
429         for (; I != E; ++I)
430           if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
431               CU.ExprRefedBaseTypes[I].Encoding == Encoding)
432             break;
433 
434         if (I == E)
435           CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
436 
437         // If targeting a location-list; simply emit the index into the raw
438         // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
439         // fitted with means to extract it later.
440         // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
441         // (containing the index and a resolve mechanism during emit) into the
442         // DIE value list.
443         emitBaseTypeRef(I);
444       } else {
445         if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
446           if (Encoding == dwarf::DW_ATE_signed)
447             emitLegacySExt(PrevConvertOp->getArg(0));
448           else if (Encoding == dwarf::DW_ATE_unsigned)
449             emitLegacyZExt(PrevConvertOp->getArg(0));
450           PrevConvertOp = None;
451         } else {
452           PrevConvertOp = Op;
453         }
454       }
455       break;
456     }
457     case dwarf::DW_OP_stack_value:
458       LocationKind = Implicit;
459       break;
460     case dwarf::DW_OP_swap:
461       assert(!isRegisterLocation());
462       emitOp(dwarf::DW_OP_swap);
463       break;
464     case dwarf::DW_OP_xderef:
465       assert(!isRegisterLocation());
466       emitOp(dwarf::DW_OP_xderef);
467       break;
468     case dwarf::DW_OP_deref_size:
469       emitOp(dwarf::DW_OP_deref_size);
470       emitData1(Op->getArg(0));
471       break;
472     case dwarf::DW_OP_LLVM_tag_offset:
473       TagOffset = Op->getArg(0);
474       break;
475     case dwarf::DW_OP_regx:
476       emitOp(dwarf::DW_OP_regx);
477       emitUnsigned(Op->getArg(0));
478       break;
479     case dwarf::DW_OP_bregx:
480       emitOp(dwarf::DW_OP_bregx);
481       emitUnsigned(Op->getArg(0));
482       emitSigned(Op->getArg(1));
483       break;
484     default:
485       llvm_unreachable("unhandled opcode found in expression");
486     }
487   }
488 
489   if (isImplicitLocation() && !isParameterValue())
490     // Turn this into an implicit location description.
491     addStackValue();
492 }
493 
494 /// add masking operations to stencil out a subregister.
495 void DwarfExpression::maskSubRegister() {
496   assert(SubRegisterSizeInBits && "no subregister was registered");
497   if (SubRegisterOffsetInBits > 0)
498     addShr(SubRegisterOffsetInBits);
499   uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
500   addAnd(Mask);
501 }
502 
503 void DwarfExpression::finalize() {
504   assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
505   // Emit any outstanding DW_OP_piece operations to mask out subregisters.
506   if (SubRegisterSizeInBits == 0)
507     return;
508   // Don't emit a DW_OP_piece for a subregister at offset 0.
509   if (SubRegisterOffsetInBits == 0)
510     return;
511   addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
512 }
513 
514 void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
515   if (!Expr || !Expr->isFragment())
516     return;
517 
518   uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
519   assert(FragmentOffset >= OffsetInBits &&
520          "overlapping or duplicate fragments");
521   if (FragmentOffset > OffsetInBits)
522     addOpPiece(FragmentOffset - OffsetInBits);
523   OffsetInBits = FragmentOffset;
524 }
525 
526 void DwarfExpression::emitLegacySExt(unsigned FromBits) {
527   // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
528   emitOp(dwarf::DW_OP_dup);
529   emitOp(dwarf::DW_OP_constu);
530   emitUnsigned(FromBits - 1);
531   emitOp(dwarf::DW_OP_shr);
532   emitOp(dwarf::DW_OP_lit0);
533   emitOp(dwarf::DW_OP_not);
534   emitOp(dwarf::DW_OP_mul);
535   emitOp(dwarf::DW_OP_constu);
536   emitUnsigned(FromBits);
537   emitOp(dwarf::DW_OP_shl);
538   emitOp(dwarf::DW_OP_or);
539 }
540 
541 void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
542   // (X & (1 << FromBits - 1))
543   emitOp(dwarf::DW_OP_constu);
544   emitUnsigned((1ULL << FromBits) - 1);
545   emitOp(dwarf::DW_OP_and);
546 }
547