1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains support for writing dwarf debug info into asm files.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "DwarfExpression.h"
14 #include "DwarfCompileUnit.h"
15 #include "llvm/ADT/APInt.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/BinaryFormat/Dwarf.h"
18 #include "llvm/CodeGen/Register.h"
19 #include "llvm/CodeGen/TargetRegisterInfo.h"
20 #include "llvm/IR/DebugInfoMetadata.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include <algorithm>
23 #include <cassert>
24 #include <cstdint>
25 
26 using namespace llvm;
27 
28 void DwarfExpression::emitConstu(uint64_t Value) {
29   if (Value < 32)
30     emitOp(dwarf::DW_OP_lit0 + Value);
31   else if (Value == std::numeric_limits<uint64_t>::max()) {
32     // Only do this for 64-bit values as the DWARF expression stack uses
33     // target-address-size values.
34     emitOp(dwarf::DW_OP_lit0);
35     emitOp(dwarf::DW_OP_not);
36   } else {
37     emitOp(dwarf::DW_OP_constu);
38     emitUnsigned(Value);
39   }
40 }
41 
42 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
43   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
44   assert((isUnknownLocation() || isRegisterLocation()) &&
45          "location description already locked down");
46   LocationKind = Register;
47   if (DwarfReg < 32) {
48     emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
49   } else {
50     emitOp(dwarf::DW_OP_regx, Comment);
51     emitUnsigned(DwarfReg);
52   }
53 }
54 
55 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
56   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
57   assert(!isRegisterLocation() && "location description already locked down");
58   if (DwarfReg < 32) {
59     emitOp(dwarf::DW_OP_breg0 + DwarfReg);
60   } else {
61     emitOp(dwarf::DW_OP_bregx);
62     emitUnsigned(DwarfReg);
63   }
64   emitSigned(Offset);
65 }
66 
67 void DwarfExpression::addFBReg(int Offset) {
68   emitOp(dwarf::DW_OP_fbreg);
69   emitSigned(Offset);
70 }
71 
72 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
73   if (!SizeInBits)
74     return;
75 
76   const unsigned SizeOfByte = 8;
77   if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
78     emitOp(dwarf::DW_OP_bit_piece);
79     emitUnsigned(SizeInBits);
80     emitUnsigned(OffsetInBits);
81   } else {
82     emitOp(dwarf::DW_OP_piece);
83     unsigned ByteSize = SizeInBits / SizeOfByte;
84     emitUnsigned(ByteSize);
85   }
86   this->OffsetInBits += SizeInBits;
87 }
88 
89 void DwarfExpression::addShr(unsigned ShiftBy) {
90   emitConstu(ShiftBy);
91   emitOp(dwarf::DW_OP_shr);
92 }
93 
94 void DwarfExpression::addAnd(unsigned Mask) {
95   emitConstu(Mask);
96   emitOp(dwarf::DW_OP_and);
97 }
98 
99 bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
100                                     unsigned MachineReg, unsigned MaxSize) {
101   if (!llvm::Register::isPhysicalRegister(MachineReg)) {
102     if (isFrameRegister(TRI, MachineReg)) {
103       DwarfRegs.push_back(Register::createRegister(-1, nullptr));
104       return true;
105     }
106     return false;
107   }
108 
109   int Reg = TRI.getDwarfRegNum(MachineReg, false);
110 
111   // If this is a valid register number, emit it.
112   if (Reg >= 0) {
113     DwarfRegs.push_back(Register::createRegister(Reg, nullptr));
114     return true;
115   }
116 
117   // Walk up the super-register chain until we find a valid number.
118   // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
119   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
120     Reg = TRI.getDwarfRegNum(*SR, false);
121     if (Reg >= 0) {
122       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
123       unsigned Size = TRI.getSubRegIdxSize(Idx);
124       unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
125       DwarfRegs.push_back(Register::createRegister(Reg, "super-register"));
126       // Use a DW_OP_bit_piece to describe the sub-register.
127       setSubRegisterPiece(Size, RegOffset);
128       return true;
129     }
130   }
131 
132   // Otherwise, attempt to find a covering set of sub-register numbers.
133   // For example, Q0 on ARM is a composition of D0+D1.
134   unsigned CurPos = 0;
135   // The size of the register in bits.
136   const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
137   unsigned RegSize = TRI.getRegSizeInBits(*RC);
138   // Keep track of the bits in the register we already emitted, so we
139   // can avoid emitting redundant aliasing subregs. Because this is
140   // just doing a greedy scan of all subregisters, it is possible that
141   // this doesn't find a combination of subregisters that fully cover
142   // the register (even though one may exist).
143   SmallBitVector Coverage(RegSize, false);
144   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
145     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
146     unsigned Size = TRI.getSubRegIdxSize(Idx);
147     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
148     Reg = TRI.getDwarfRegNum(*SR, false);
149     if (Reg < 0)
150       continue;
151 
152     // Used to build the intersection between the bits we already
153     // emitted and the bits covered by this subregister.
154     SmallBitVector CurSubReg(RegSize, false);
155     CurSubReg.set(Offset, Offset + Size);
156 
157     // If this sub-register has a DWARF number and we haven't covered
158     // its range, and its range covers the value, emit a DWARF piece for it.
159     if (Offset < MaxSize && CurSubReg.test(Coverage)) {
160       // Emit a piece for any gap in the coverage.
161       if (Offset > CurPos)
162         DwarfRegs.push_back(Register::createSubRegister(
163             -1, Offset - CurPos, "no DWARF register encoding"));
164       if (Offset == 0 && Size >= MaxSize)
165         DwarfRegs.push_back(Register::createRegister(Reg, "sub-register"));
166       else
167         DwarfRegs.push_back(Register::createSubRegister(
168             Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"));
169     }
170     // Mark it as emitted.
171     Coverage.set(Offset, Offset + Size);
172     CurPos = Offset + Size;
173   }
174   // Failed to find any DWARF encoding.
175   if (CurPos == 0)
176     return false;
177   // Found a partial or complete DWARF encoding.
178   if (CurPos < RegSize)
179     DwarfRegs.push_back(Register::createSubRegister(
180         -1, RegSize - CurPos, "no DWARF register encoding"));
181   return true;
182 }
183 
184 void DwarfExpression::addStackValue() {
185   if (DwarfVersion >= 4)
186     emitOp(dwarf::DW_OP_stack_value);
187 }
188 
189 void DwarfExpression::addSignedConstant(int64_t Value) {
190   assert(isImplicitLocation() || isUnknownLocation());
191   LocationKind = Implicit;
192   emitOp(dwarf::DW_OP_consts);
193   emitSigned(Value);
194 }
195 
196 void DwarfExpression::addUnsignedConstant(uint64_t Value) {
197   assert(isImplicitLocation() || isUnknownLocation());
198   LocationKind = Implicit;
199   emitConstu(Value);
200 }
201 
202 void DwarfExpression::addUnsignedConstant(const APInt &Value) {
203   assert(isImplicitLocation() || isUnknownLocation());
204   LocationKind = Implicit;
205 
206   unsigned Size = Value.getBitWidth();
207   const uint64_t *Data = Value.getRawData();
208 
209   // Chop it up into 64-bit pieces, because that's the maximum that
210   // addUnsignedConstant takes.
211   unsigned Offset = 0;
212   while (Offset < Size) {
213     addUnsignedConstant(*Data++);
214     if (Offset == 0 && Size <= 64)
215       break;
216     addStackValue();
217     addOpPiece(std::min(Size - Offset, 64u), Offset);
218     Offset += 64;
219   }
220 }
221 
222 bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
223                                               DIExpressionCursor &ExprCursor,
224                                               unsigned MachineReg,
225                                               unsigned FragmentOffsetInBits) {
226   auto Fragment = ExprCursor.getFragmentInfo();
227   if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
228     LocationKind = Unknown;
229     return false;
230   }
231 
232   bool HasComplexExpression = false;
233   auto Op = ExprCursor.peek();
234   if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
235     HasComplexExpression = true;
236 
237   // If the register can only be described by a complex expression (i.e.,
238   // multiple subregisters) it doesn't safely compose with another complex
239   // expression. For example, it is not possible to apply a DW_OP_deref
240   // operation to multiple DW_OP_pieces.
241   if (HasComplexExpression && DwarfRegs.size() > 1) {
242     DwarfRegs.clear();
243     LocationKind = Unknown;
244     return false;
245   }
246 
247   // Handle simple register locations. If we are supposed to emit
248   // a call site parameter expression and if that expression is just a register
249   // location, emit it with addBReg and offset 0, because we should emit a DWARF
250   // expression representing a value, rather than a location.
251   if (!isMemoryLocation() && !HasComplexExpression &&
252       (!isParameterValue() || isEntryValue())) {
253     for (auto &Reg : DwarfRegs) {
254       if (Reg.DwarfRegNo >= 0)
255         addReg(Reg.DwarfRegNo, Reg.Comment);
256       addOpPiece(Reg.SubRegSize);
257     }
258 
259     if (isEntryValue())
260       finalizeEntryValue();
261 
262     if (isEntryValue() && !isParameterValue() && DwarfVersion >= 4)
263       emitOp(dwarf::DW_OP_stack_value);
264 
265     DwarfRegs.clear();
266     return true;
267   }
268 
269   // Don't emit locations that cannot be expressed without DW_OP_stack_value.
270   if (DwarfVersion < 4)
271     if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
272           return Op.getOp() == dwarf::DW_OP_stack_value;
273         })) {
274       DwarfRegs.clear();
275       LocationKind = Unknown;
276       return false;
277     }
278 
279   assert(DwarfRegs.size() == 1);
280   auto Reg = DwarfRegs[0];
281   bool FBReg = isFrameRegister(TRI, MachineReg);
282   int SignedOffset = 0;
283   assert(!Reg.isSubRegister() && "full register expected");
284 
285   // Pattern-match combinations for which more efficient representations exist.
286   // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
287   if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
288     uint64_t Offset = Op->getArg(0);
289     uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
290     if (Offset <= IntMax) {
291       SignedOffset = Offset;
292       ExprCursor.take();
293     }
294   }
295 
296   // [Reg, DW_OP_constu, Offset, DW_OP_plus]  --> [DW_OP_breg, Offset]
297   // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
298   // If Reg is a subregister we need to mask it out before subtracting.
299   if (Op && Op->getOp() == dwarf::DW_OP_constu) {
300     uint64_t Offset = Op->getArg(0);
301     uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
302     auto N = ExprCursor.peekNext();
303     if (N && N->getOp() == dwarf::DW_OP_plus && Offset <= IntMax) {
304       SignedOffset = Offset;
305       ExprCursor.consume(2);
306     } else if (N && N->getOp() == dwarf::DW_OP_minus &&
307                !SubRegisterSizeInBits && Offset <= IntMax + 1) {
308       SignedOffset = -static_cast<int64_t>(Offset);
309       ExprCursor.consume(2);
310     }
311   }
312 
313   if (FBReg)
314     addFBReg(SignedOffset);
315   else
316     addBReg(Reg.DwarfRegNo, SignedOffset);
317   DwarfRegs.clear();
318   return true;
319 }
320 
321 void DwarfExpression::beginEntryValueExpression(
322     DIExpressionCursor &ExprCursor) {
323   auto Op = ExprCursor.take();
324   (void)Op;
325   assert(Op && Op->getOp() == dwarf::DW_OP_LLVM_entry_value);
326   assert(!isMemoryLocation() &&
327          "We don't support entry values of memory locations yet");
328   assert(!IsEmittingEntryValue && "Already emitting entry value?");
329   assert(Op->getArg(0) == 1 &&
330          "Can currently only emit entry values covering a single operation");
331 
332   emitOp(CU.getDwarf5OrGNULocationAtom(dwarf::DW_OP_entry_value));
333   IsEmittingEntryValue = true;
334   enableTemporaryBuffer();
335 }
336 
337 void DwarfExpression::finalizeEntryValue() {
338   assert(IsEmittingEntryValue && "Entry value not open?");
339   disableTemporaryBuffer();
340 
341   // Emit the entry value's size operand.
342   unsigned Size = getTemporaryBufferSize();
343   emitUnsigned(Size);
344 
345   // Emit the entry value's DWARF block operand.
346   commitTemporaryBuffer();
347 
348   IsEmittingEntryValue = false;
349 }
350 
351 unsigned DwarfExpression::getOrCreateBaseType(unsigned BitSize,
352                                               dwarf::TypeKind Encoding) {
353   // Reuse the base_type if we already have one in this CU otherwise we
354   // create a new one.
355   unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
356   for (; I != E; ++I)
357     if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
358         CU.ExprRefedBaseTypes[I].Encoding == Encoding)
359       break;
360 
361   if (I == E)
362     CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
363   return I;
364 }
365 
366 /// Assuming a well-formed expression, match "DW_OP_deref*
367 /// DW_OP_LLVM_fragment?".
368 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
369   while (ExprCursor) {
370     auto Op = ExprCursor.take();
371     switch (Op->getOp()) {
372     case dwarf::DW_OP_deref:
373     case dwarf::DW_OP_LLVM_fragment:
374       break;
375     default:
376       return false;
377     }
378   }
379   return true;
380 }
381 
382 void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
383                                     unsigned FragmentOffsetInBits) {
384   // If we need to mask out a subregister, do it now, unless the next
385   // operation would emit an OpPiece anyway.
386   auto N = ExprCursor.peek();
387   if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
388     maskSubRegister();
389 
390   Optional<DIExpression::ExprOperand> PrevConvertOp = None;
391 
392   while (ExprCursor) {
393     auto Op = ExprCursor.take();
394     uint64_t OpNum = Op->getOp();
395 
396     if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) {
397       emitOp(OpNum);
398       continue;
399     } else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) {
400       addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0));
401       continue;
402     }
403 
404     switch (OpNum) {
405     case dwarf::DW_OP_LLVM_fragment: {
406       unsigned SizeInBits = Op->getArg(1);
407       unsigned FragmentOffset = Op->getArg(0);
408       // The fragment offset must have already been adjusted by emitting an
409       // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
410       // location.
411       assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
412       assert(SizeInBits >= OffsetInBits - FragmentOffset && "size underflow");
413 
414       // If addMachineReg already emitted DW_OP_piece operations to represent
415       // a super-register by splicing together sub-registers, subtract the size
416       // of the pieces that was already emitted.
417       SizeInBits -= OffsetInBits - FragmentOffset;
418 
419       // If addMachineReg requested a DW_OP_bit_piece to stencil out a
420       // sub-register that is smaller than the current fragment's size, use it.
421       if (SubRegisterSizeInBits)
422         SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
423 
424       // Emit a DW_OP_stack_value for implicit location descriptions.
425       if (isImplicitLocation())
426         addStackValue();
427 
428       // Emit the DW_OP_piece.
429       addOpPiece(SizeInBits, SubRegisterOffsetInBits);
430       setSubRegisterPiece(0, 0);
431       // Reset the location description kind.
432       LocationKind = Unknown;
433       return;
434     }
435     case dwarf::DW_OP_plus_uconst:
436       assert(!isRegisterLocation());
437       emitOp(dwarf::DW_OP_plus_uconst);
438       emitUnsigned(Op->getArg(0));
439       break;
440     case dwarf::DW_OP_plus:
441     case dwarf::DW_OP_minus:
442     case dwarf::DW_OP_mul:
443     case dwarf::DW_OP_div:
444     case dwarf::DW_OP_mod:
445     case dwarf::DW_OP_or:
446     case dwarf::DW_OP_and:
447     case dwarf::DW_OP_xor:
448     case dwarf::DW_OP_shl:
449     case dwarf::DW_OP_shr:
450     case dwarf::DW_OP_shra:
451     case dwarf::DW_OP_lit0:
452     case dwarf::DW_OP_not:
453     case dwarf::DW_OP_dup:
454     case dwarf::DW_OP_push_object_address:
455       emitOp(OpNum);
456       break;
457     case dwarf::DW_OP_deref:
458       assert(!isRegisterLocation());
459       if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor))
460         // Turning this into a memory location description makes the deref
461         // implicit.
462         LocationKind = Memory;
463       else
464         emitOp(dwarf::DW_OP_deref);
465       break;
466     case dwarf::DW_OP_constu:
467       assert(!isRegisterLocation());
468       emitConstu(Op->getArg(0));
469       break;
470     case dwarf::DW_OP_LLVM_convert: {
471       unsigned BitSize = Op->getArg(0);
472       dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
473       if (DwarfVersion >= 5) {
474         emitOp(dwarf::DW_OP_convert);
475         // If targeting a location-list; simply emit the index into the raw
476         // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
477         // fitted with means to extract it later.
478         // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
479         // (containing the index and a resolve mechanism during emit) into the
480         // DIE value list.
481         emitBaseTypeRef(getOrCreateBaseType(BitSize, Encoding));
482       } else {
483         if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
484           if (Encoding == dwarf::DW_ATE_signed)
485             emitLegacySExt(PrevConvertOp->getArg(0));
486           else if (Encoding == dwarf::DW_ATE_unsigned)
487             emitLegacyZExt(PrevConvertOp->getArg(0));
488           PrevConvertOp = None;
489         } else {
490           PrevConvertOp = Op;
491         }
492       }
493       break;
494     }
495     case dwarf::DW_OP_stack_value:
496       LocationKind = Implicit;
497       break;
498     case dwarf::DW_OP_swap:
499       assert(!isRegisterLocation());
500       emitOp(dwarf::DW_OP_swap);
501       break;
502     case dwarf::DW_OP_xderef:
503       assert(!isRegisterLocation());
504       emitOp(dwarf::DW_OP_xderef);
505       break;
506     case dwarf::DW_OP_deref_size:
507       emitOp(dwarf::DW_OP_deref_size);
508       emitData1(Op->getArg(0));
509       break;
510     case dwarf::DW_OP_LLVM_tag_offset:
511       TagOffset = Op->getArg(0);
512       break;
513     case dwarf::DW_OP_regx:
514       emitOp(dwarf::DW_OP_regx);
515       emitUnsigned(Op->getArg(0));
516       break;
517     case dwarf::DW_OP_bregx:
518       emitOp(dwarf::DW_OP_bregx);
519       emitUnsigned(Op->getArg(0));
520       emitSigned(Op->getArg(1));
521       break;
522     default:
523       llvm_unreachable("unhandled opcode found in expression");
524     }
525   }
526 
527   if (isImplicitLocation() && !isParameterValue())
528     // Turn this into an implicit location description.
529     addStackValue();
530 }
531 
532 /// add masking operations to stencil out a subregister.
533 void DwarfExpression::maskSubRegister() {
534   assert(SubRegisterSizeInBits && "no subregister was registered");
535   if (SubRegisterOffsetInBits > 0)
536     addShr(SubRegisterOffsetInBits);
537   uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
538   addAnd(Mask);
539 }
540 
541 void DwarfExpression::finalize() {
542   assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
543   // Emit any outstanding DW_OP_piece operations to mask out subregisters.
544   if (SubRegisterSizeInBits == 0)
545     return;
546   // Don't emit a DW_OP_piece for a subregister at offset 0.
547   if (SubRegisterOffsetInBits == 0)
548     return;
549   addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
550 }
551 
552 void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
553   if (!Expr || !Expr->isFragment())
554     return;
555 
556   uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
557   assert(FragmentOffset >= OffsetInBits &&
558          "overlapping or duplicate fragments");
559   if (FragmentOffset > OffsetInBits)
560     addOpPiece(FragmentOffset - OffsetInBits);
561   OffsetInBits = FragmentOffset;
562 }
563 
564 void DwarfExpression::emitLegacySExt(unsigned FromBits) {
565   // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
566   emitOp(dwarf::DW_OP_dup);
567   emitOp(dwarf::DW_OP_constu);
568   emitUnsigned(FromBits - 1);
569   emitOp(dwarf::DW_OP_shr);
570   emitOp(dwarf::DW_OP_lit0);
571   emitOp(dwarf::DW_OP_not);
572   emitOp(dwarf::DW_OP_mul);
573   emitOp(dwarf::DW_OP_constu);
574   emitUnsigned(FromBits);
575   emitOp(dwarf::DW_OP_shl);
576   emitOp(dwarf::DW_OP_or);
577 }
578 
579 void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
580   // (X & (1 << FromBits - 1))
581   emitOp(dwarf::DW_OP_constu);
582   emitUnsigned((1ULL << FromBits) - 1);
583   emitOp(dwarf::DW_OP_and);
584 }
585 
586 void DwarfExpression::addWasmLocation(unsigned Index, uint64_t Offset) {
587   assert(LocationKind == Implicit || LocationKind == Unknown);
588   LocationKind = Implicit;
589   emitOp(dwarf::DW_OP_WASM_location);
590   emitUnsigned(Index);
591   emitUnsigned(Offset);
592 }
593