1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains support for writing dwarf debug info into asm files.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "DwarfExpression.h"
15 #include "DwarfDebug.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/CodeGen/AsmPrinter.h"
18 #include "llvm/Support/Dwarf.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Target/TargetSubtargetInfo.h"
22 
23 using namespace llvm;
24 
25 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
26   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
27   if (DwarfReg < 32) {
28     emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
29   } else {
30     emitOp(dwarf::DW_OP_regx, Comment);
31     emitUnsigned(DwarfReg);
32   }
33 }
34 
35 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
36   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
37   if (DwarfReg < 32) {
38     emitOp(dwarf::DW_OP_breg0 + DwarfReg);
39   } else {
40     emitOp(dwarf::DW_OP_bregx);
41     emitUnsigned(DwarfReg);
42   }
43   emitSigned(Offset);
44 }
45 
46 void DwarfExpression::addFBReg(int Offset) {
47   emitOp(dwarf::DW_OP_fbreg);
48   emitSigned(Offset);
49 }
50 
51 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
52   if (!SizeInBits)
53     return;
54 
55   const unsigned SizeOfByte = 8;
56   if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
57     emitOp(dwarf::DW_OP_bit_piece);
58     emitUnsigned(SizeInBits);
59     emitUnsigned(OffsetInBits);
60   } else {
61     emitOp(dwarf::DW_OP_piece);
62     unsigned ByteSize = SizeInBits / SizeOfByte;
63     emitUnsigned(ByteSize);
64   }
65   this->OffsetInBits += SizeInBits;
66 }
67 
68 void DwarfExpression::addShr(unsigned ShiftBy) {
69   emitOp(dwarf::DW_OP_constu);
70   emitUnsigned(ShiftBy);
71   emitOp(dwarf::DW_OP_shr);
72 }
73 
74 void DwarfExpression::addAnd(unsigned Mask) {
75   emitOp(dwarf::DW_OP_constu);
76   emitUnsigned(Mask);
77   emitOp(dwarf::DW_OP_and);
78 }
79 
80 bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
81                                     unsigned MachineReg, unsigned MaxSize) {
82   if (!TRI.isPhysicalRegister(MachineReg)) {
83     if (isFrameRegister(TRI, MachineReg)) {
84       DwarfRegs.push_back({-1, 0, nullptr});
85       return true;
86     }
87     return false;
88   }
89 
90   int Reg = TRI.getDwarfRegNum(MachineReg, false);
91 
92   // If this is a valid register number, emit it.
93   if (Reg >= 0) {
94     DwarfRegs.push_back({Reg, 0, nullptr});
95     return true;
96   }
97 
98   // Walk up the super-register chain until we find a valid number.
99   // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
100   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
101     Reg = TRI.getDwarfRegNum(*SR, false);
102     if (Reg >= 0) {
103       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
104       unsigned Size = TRI.getSubRegIdxSize(Idx);
105       unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
106       DwarfRegs.push_back({Reg, 0, "super-register"});
107       // Use a DW_OP_bit_piece to describe the sub-register.
108       setSubRegisterPiece(Size, RegOffset);
109       return true;
110     }
111   }
112 
113   // Otherwise, attempt to find a covering set of sub-register numbers.
114   // For example, Q0 on ARM is a composition of D0+D1.
115   unsigned CurPos = 0;
116   // The size of the register in bits, assuming 8 bits per byte.
117   unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
118   // Keep track of the bits in the register we already emitted, so we
119   // can avoid emitting redundant aliasing subregs.
120   SmallBitVector Coverage(RegSize, false);
121   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
122     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
123     unsigned Size = TRI.getSubRegIdxSize(Idx);
124     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
125     Reg = TRI.getDwarfRegNum(*SR, false);
126 
127     // Intersection between the bits we already emitted and the bits
128     // covered by this subregister.
129     SmallBitVector Intersection(RegSize, false);
130     Intersection.set(Offset, Offset + Size);
131     Intersection ^= Coverage;
132 
133     // If this sub-register has a DWARF number and we haven't covered
134     // its range, emit a DWARF piece for it.
135     if (Reg >= 0 && Intersection.any()) {
136       // Emit a piece for any gap in the coverage.
137       if (Offset > CurPos)
138         DwarfRegs.push_back({-1, Offset - CurPos, nullptr});
139       DwarfRegs.push_back(
140           {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
141       if (Offset >= MaxSize)
142 	break;
143 
144       // Mark it as emitted.
145       Coverage.set(Offset, Offset + Size);
146       CurPos = Offset + Size;
147     }
148   }
149 
150   return CurPos;
151 }
152 
153 void DwarfExpression::addStackValue() {
154   if (DwarfVersion >= 4)
155     emitOp(dwarf::DW_OP_stack_value);
156 }
157 
158 void DwarfExpression::addSignedConstant(int64_t Value) {
159   emitOp(dwarf::DW_OP_consts);
160   emitSigned(Value);
161   addStackValue();
162 }
163 
164 void DwarfExpression::addUnsignedConstant(uint64_t Value) {
165   emitOp(dwarf::DW_OP_constu);
166   emitUnsigned(Value);
167   addStackValue();
168 }
169 
170 void DwarfExpression::addUnsignedConstant(const APInt &Value) {
171   unsigned Size = Value.getBitWidth();
172   const uint64_t *Data = Value.getRawData();
173 
174   // Chop it up into 64-bit pieces, because that's the maximum that
175   // addUnsignedConstant takes.
176   unsigned Offset = 0;
177   while (Offset < Size) {
178     addUnsignedConstant(*Data++);
179     if (Offset == 0 && Size <= 64)
180       break;
181     addOpPiece(std::min(Size-Offset, 64u), Offset);
182     Offset += 64;
183   }
184 }
185 
186 bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
187                                               DIExpressionCursor &ExprCursor,
188                                               unsigned MachineReg,
189                                               unsigned FragmentOffsetInBits) {
190   auto Fragment = ExprCursor.getFragmentInfo();
191   if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U))
192     return false;
193 
194   bool HasComplexExpression = false;
195   auto Op = ExprCursor.peek();
196   if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
197     HasComplexExpression = true;
198 
199   // If the register can only be described by a complex expression (i.e.,
200   // multiple subregisters) it doesn't safely compose with another complex
201   // expression. For example, it is not possible to apply a DW_OP_deref
202   // operation to multiple DW_OP_pieces.
203   if (HasComplexExpression && DwarfRegs.size() > 1) {
204     DwarfRegs.clear();
205     return false;
206   }
207 
208   // Handle simple register locations.
209   if (!HasComplexExpression) {
210     for (auto &Reg : DwarfRegs) {
211       if (Reg.DwarfRegNo >= 0)
212         addReg(Reg.DwarfRegNo, Reg.Comment);
213       addOpPiece(Reg.Size);
214     }
215     DwarfRegs.clear();
216     return true;
217   }
218 
219   assert(DwarfRegs.size() == 1);
220   auto Reg = DwarfRegs[0];
221   bool FBReg = isFrameRegister(TRI, MachineReg);
222   assert(Reg.Size == 0 && "subregister has same size as superregister");
223 
224   // Pattern-match combinations for which more efficient representations exist.
225   switch (Op->getOp()) {
226   default: {
227     if (FBReg)
228       addFBReg(0);
229     else
230       addReg(Reg.DwarfRegNo, 0);
231     break;
232   }
233   case dwarf::DW_OP_plus:
234   case dwarf::DW_OP_minus: {
235     // [DW_OP_reg,Offset,DW_OP_plus, DW_OP_deref] --> [DW_OP_breg, Offset].
236     // [DW_OP_reg,Offset,DW_OP_minus,DW_OP_deref] --> [DW_OP_breg,-Offset].
237     auto N = ExprCursor.peekNext();
238     if (N && N->getOp() == dwarf::DW_OP_deref) {
239       int Offset = Op->getArg(0);
240       int SignedOffset = (Op->getOp() == dwarf::DW_OP_plus) ? Offset : -Offset;
241       if (FBReg)
242         addFBReg(SignedOffset);
243       else
244         addBReg(Reg.DwarfRegNo, SignedOffset);
245 
246       ExprCursor.consume(2);
247       break;
248     }
249     addReg(Reg.DwarfRegNo, 0);
250     break;
251   }
252   case dwarf::DW_OP_deref:
253     // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
254     if (FBReg)
255       addFBReg(0);
256     else
257       addBReg(Reg.DwarfRegNo, 0);
258     ExprCursor.take();
259     break;
260   }
261   DwarfRegs.clear();
262   return true;
263 }
264 
265 void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
266                                     unsigned FragmentOffsetInBits) {
267   while (ExprCursor) {
268     auto Op = ExprCursor.take();
269 
270     // If we need to mask out a subregister, do it now, unless the next
271     // operation would emit an OpPiece anyway.
272     if (SubRegisterSizeInBits && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
273       maskSubRegister();
274 
275     switch (Op->getOp()) {
276     case dwarf::DW_OP_LLVM_fragment: {
277       unsigned SizeInBits = Op->getArg(1);
278       unsigned FragmentOffset = Op->getArg(0);
279       // The fragment offset must have already been adjusted by emitting an
280       // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
281       // location.
282       assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
283 
284       // If \a addMachineReg already emitted DW_OP_piece operations to represent
285       // a super-register by splicing together sub-registers, subtract the size
286       // of the pieces that was already emitted.
287       SizeInBits -= OffsetInBits - FragmentOffset;
288 
289       // If \a addMachineReg requested a DW_OP_bit_piece to stencil out a
290       // sub-register that is smaller than the current fragment's size, use it.
291       if (SubRegisterSizeInBits)
292         SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
293 
294       addOpPiece(SizeInBits, SubRegisterOffsetInBits);
295       setSubRegisterPiece(0, 0);
296       break;
297     }
298     case dwarf::DW_OP_plus:
299       emitOp(dwarf::DW_OP_plus_uconst);
300       emitUnsigned(Op->getArg(0));
301       break;
302     case dwarf::DW_OP_minus:
303       // There is no OP_minus_uconst.
304       emitOp(dwarf::DW_OP_constu);
305       emitUnsigned(Op->getArg(0));
306       emitOp(dwarf::DW_OP_minus);
307       break;
308     case dwarf::DW_OP_deref:
309       emitOp(dwarf::DW_OP_deref);
310       break;
311     case dwarf::DW_OP_constu:
312       emitOp(dwarf::DW_OP_constu);
313       emitUnsigned(Op->getArg(0));
314       break;
315     case dwarf::DW_OP_stack_value:
316       addStackValue();
317       break;
318     case dwarf::DW_OP_swap:
319       emitOp(dwarf::DW_OP_swap);
320       break;
321     case dwarf::DW_OP_xderef:
322       emitOp(dwarf::DW_OP_xderef);
323       break;
324     default:
325       llvm_unreachable("unhandled opcode found in expression");
326     }
327   }
328 }
329 
330 /// add masking operations to stencil out a subregister.
331 void DwarfExpression::maskSubRegister() {
332   assert(SubRegisterSizeInBits && "no subregister was registered");
333   if (SubRegisterOffsetInBits > 0)
334     addShr(SubRegisterOffsetInBits);
335   uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
336   addAnd(Mask);
337 }
338 
339 
340 void DwarfExpression::finalize() {
341   assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
342   // Emit any outstanding DW_OP_piece operations to mask out subregisters.
343   if (SubRegisterSizeInBits == 0)
344     return;
345   // Don't emit a DW_OP_piece for a subregister at offset 0.
346   if (SubRegisterOffsetInBits == 0)
347     return;
348   addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
349 }
350 
351 void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
352   if (!Expr || !Expr->isFragment())
353     return;
354 
355   uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
356   assert(FragmentOffset >= OffsetInBits &&
357          "overlapping or duplicate fragments");
358   if (FragmentOffset > OffsetInBits)
359     addOpPiece(FragmentOffset - OffsetInBits);
360   OffsetInBits = FragmentOffset;
361 }
362