1 //===- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains support for writing dwarf debug info into asm files.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "DwarfExpression.h"
14 #include "DwarfCompileUnit.h"
15 #include "llvm/ADT/APInt.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/BinaryFormat/Dwarf.h"
18 #include "llvm/CodeGen/Register.h"
19 #include "llvm/CodeGen/TargetRegisterInfo.h"
20 #include "llvm/IR/DebugInfoMetadata.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include <algorithm>
23 #include <cassert>
24 #include <cstdint>
25 
26 using namespace llvm;
27 
28 void DwarfExpression::emitConstu(uint64_t Value) {
29   if (Value < 32)
30     emitOp(dwarf::DW_OP_lit0 + Value);
31   else if (Value == std::numeric_limits<uint64_t>::max()) {
32     // Only do this for 64-bit values as the DWARF expression stack uses
33     // target-address-size values.
34     emitOp(dwarf::DW_OP_lit0);
35     emitOp(dwarf::DW_OP_not);
36   } else {
37     emitOp(dwarf::DW_OP_constu);
38     emitUnsigned(Value);
39   }
40 }
41 
42 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
43   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
44   assert((isUnknownLocation() || isRegisterLocation()) &&
45          "location description already locked down");
46   LocationKind = Register;
47   if (DwarfReg < 32) {
48     emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
49   } else {
50     emitOp(dwarf::DW_OP_regx, Comment);
51     emitUnsigned(DwarfReg);
52   }
53 }
54 
55 void DwarfExpression::addBReg(int DwarfReg, int Offset) {
56   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
57   assert(!isRegisterLocation() && "location description already locked down");
58   if (DwarfReg < 32) {
59     emitOp(dwarf::DW_OP_breg0 + DwarfReg);
60   } else {
61     emitOp(dwarf::DW_OP_bregx);
62     emitUnsigned(DwarfReg);
63   }
64   emitSigned(Offset);
65 }
66 
67 void DwarfExpression::addFBReg(int Offset) {
68   emitOp(dwarf::DW_OP_fbreg);
69   emitSigned(Offset);
70 }
71 
72 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
73   if (!SizeInBits)
74     return;
75 
76   const unsigned SizeOfByte = 8;
77   if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
78     emitOp(dwarf::DW_OP_bit_piece);
79     emitUnsigned(SizeInBits);
80     emitUnsigned(OffsetInBits);
81   } else {
82     emitOp(dwarf::DW_OP_piece);
83     unsigned ByteSize = SizeInBits / SizeOfByte;
84     emitUnsigned(ByteSize);
85   }
86   this->OffsetInBits += SizeInBits;
87 }
88 
89 void DwarfExpression::addShr(unsigned ShiftBy) {
90   emitConstu(ShiftBy);
91   emitOp(dwarf::DW_OP_shr);
92 }
93 
94 void DwarfExpression::addAnd(unsigned Mask) {
95   emitConstu(Mask);
96   emitOp(dwarf::DW_OP_and);
97 }
98 
99 bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
100                                     unsigned MachineReg, unsigned MaxSize) {
101   if (!llvm::Register::isPhysicalRegister(MachineReg)) {
102     if (isFrameRegister(TRI, MachineReg)) {
103       DwarfRegs.push_back(Register::createRegister(-1, nullptr));
104       return true;
105     }
106     return false;
107   }
108 
109   int Reg = TRI.getDwarfRegNum(MachineReg, false);
110 
111   // If this is a valid register number, emit it.
112   if (Reg >= 0) {
113     DwarfRegs.push_back(Register::createRegister(Reg, nullptr));
114     return true;
115   }
116 
117   // Walk up the super-register chain until we find a valid number.
118   // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
119   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
120     Reg = TRI.getDwarfRegNum(*SR, false);
121     if (Reg >= 0) {
122       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
123       unsigned Size = TRI.getSubRegIdxSize(Idx);
124       unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
125       DwarfRegs.push_back(Register::createRegister(Reg, "super-register"));
126       // Use a DW_OP_bit_piece to describe the sub-register.
127       setSubRegisterPiece(Size, RegOffset);
128       return true;
129     }
130   }
131 
132   // Otherwise, attempt to find a covering set of sub-register numbers.
133   // For example, Q0 on ARM is a composition of D0+D1.
134   unsigned CurPos = 0;
135   // The size of the register in bits.
136   const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
137   unsigned RegSize = TRI.getRegSizeInBits(*RC);
138   // Keep track of the bits in the register we already emitted, so we
139   // can avoid emitting redundant aliasing subregs. Because this is
140   // just doing a greedy scan of all subregisters, it is possible that
141   // this doesn't find a combination of subregisters that fully cover
142   // the register (even though one may exist).
143   SmallBitVector Coverage(RegSize, false);
144   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
145     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
146     unsigned Size = TRI.getSubRegIdxSize(Idx);
147     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
148     Reg = TRI.getDwarfRegNum(*SR, false);
149     if (Reg < 0)
150       continue;
151 
152     // Used to build the intersection between the bits we already
153     // emitted and the bits covered by this subregister.
154     SmallBitVector CurSubReg(RegSize, false);
155     CurSubReg.set(Offset, Offset + Size);
156 
157     // If this sub-register has a DWARF number and we haven't covered
158     // its range, and its range covers the value, emit a DWARF piece for it.
159     if (Offset < MaxSize && CurSubReg.test(Coverage)) {
160       // Emit a piece for any gap in the coverage.
161       if (Offset > CurPos)
162         DwarfRegs.push_back(Register::createSubRegister(
163             -1, Offset - CurPos, "no DWARF register encoding"));
164       if (Offset == 0 && Size >= MaxSize)
165         DwarfRegs.push_back(Register::createRegister(Reg, "sub-register"));
166       else
167         DwarfRegs.push_back(Register::createSubRegister(
168             Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"));
169     }
170     // Mark it as emitted.
171     Coverage.set(Offset, Offset + Size);
172     CurPos = Offset + Size;
173   }
174   // Failed to find any DWARF encoding.
175   if (CurPos == 0)
176     return false;
177   // Found a partial or complete DWARF encoding.
178   if (CurPos < RegSize)
179     DwarfRegs.push_back(Register::createSubRegister(
180         -1, RegSize - CurPos, "no DWARF register encoding"));
181   return true;
182 }
183 
184 void DwarfExpression::addStackValue() {
185   if (DwarfVersion >= 4)
186     emitOp(dwarf::DW_OP_stack_value);
187 }
188 
189 void DwarfExpression::addSignedConstant(int64_t Value) {
190   assert(isImplicitLocation() || isUnknownLocation());
191   LocationKind = Implicit;
192   emitOp(dwarf::DW_OP_consts);
193   emitSigned(Value);
194 }
195 
196 void DwarfExpression::addUnsignedConstant(uint64_t Value) {
197   assert(isImplicitLocation() || isUnknownLocation());
198   LocationKind = Implicit;
199   emitConstu(Value);
200 }
201 
202 void DwarfExpression::addUnsignedConstant(const APInt &Value) {
203   assert(isImplicitLocation() || isUnknownLocation());
204   LocationKind = Implicit;
205 
206   unsigned Size = Value.getBitWidth();
207   const uint64_t *Data = Value.getRawData();
208 
209   // Chop it up into 64-bit pieces, because that's the maximum that
210   // addUnsignedConstant takes.
211   unsigned Offset = 0;
212   while (Offset < Size) {
213     addUnsignedConstant(*Data++);
214     if (Offset == 0 && Size <= 64)
215       break;
216     addStackValue();
217     addOpPiece(std::min(Size - Offset, 64u), Offset);
218     Offset += 64;
219   }
220 }
221 
222 bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
223                                               DIExpressionCursor &ExprCursor,
224                                               unsigned MachineReg,
225                                               unsigned FragmentOffsetInBits) {
226   auto Fragment = ExprCursor.getFragmentInfo();
227   if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U)) {
228     LocationKind = Unknown;
229     return false;
230   }
231 
232   bool HasComplexExpression = false;
233   auto Op = ExprCursor.peek();
234   if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
235     HasComplexExpression = true;
236 
237   // If the register can only be described by a complex expression (i.e.,
238   // multiple subregisters) it doesn't safely compose with another complex
239   // expression. For example, it is not possible to apply a DW_OP_deref
240   // operation to multiple DW_OP_pieces.
241   if (HasComplexExpression && DwarfRegs.size() > 1) {
242     DwarfRegs.clear();
243     LocationKind = Unknown;
244     return false;
245   }
246 
247   // Handle simple register locations. If we are supposed to emit
248   // a call site parameter expression and if that expression is just a register
249   // location, emit it with addBReg and offset 0, because we should emit a DWARF
250   // expression representing a value, rather than a location.
251   if (!isMemoryLocation() && !HasComplexExpression &&
252       (!isParameterValue() || isEntryValue())) {
253     for (auto &Reg : DwarfRegs) {
254       if (Reg.DwarfRegNo >= 0)
255         addReg(Reg.DwarfRegNo, Reg.Comment);
256       addOpPiece(Reg.SubRegSize);
257     }
258 
259     if (isEntryValue())
260       finalizeEntryValue();
261 
262     if (isEntryValue() && !isIndirect() && !isParameterValue() &&
263         DwarfVersion >= 4)
264       emitOp(dwarf::DW_OP_stack_value);
265 
266     DwarfRegs.clear();
267     return true;
268   }
269 
270   // Don't emit locations that cannot be expressed without DW_OP_stack_value.
271   if (DwarfVersion < 4)
272     if (any_of(ExprCursor, [](DIExpression::ExprOperand Op) -> bool {
273           return Op.getOp() == dwarf::DW_OP_stack_value;
274         })) {
275       DwarfRegs.clear();
276       LocationKind = Unknown;
277       return false;
278     }
279 
280   assert(DwarfRegs.size() == 1);
281   auto Reg = DwarfRegs[0];
282   bool FBReg = isFrameRegister(TRI, MachineReg);
283   int SignedOffset = 0;
284   assert(!Reg.isSubRegister() && "full register expected");
285 
286   // Pattern-match combinations for which more efficient representations exist.
287   // [Reg, DW_OP_plus_uconst, Offset] --> [DW_OP_breg, Offset].
288   if (Op && (Op->getOp() == dwarf::DW_OP_plus_uconst)) {
289     uint64_t Offset = Op->getArg(0);
290     uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
291     if (Offset <= IntMax) {
292       SignedOffset = Offset;
293       ExprCursor.take();
294     }
295   }
296 
297   // [Reg, DW_OP_constu, Offset, DW_OP_plus]  --> [DW_OP_breg, Offset]
298   // [Reg, DW_OP_constu, Offset, DW_OP_minus] --> [DW_OP_breg,-Offset]
299   // If Reg is a subregister we need to mask it out before subtracting.
300   if (Op && Op->getOp() == dwarf::DW_OP_constu) {
301     uint64_t Offset = Op->getArg(0);
302     uint64_t IntMax = static_cast<uint64_t>(std::numeric_limits<int>::max());
303     auto N = ExprCursor.peekNext();
304     if (N && N->getOp() == dwarf::DW_OP_plus && Offset <= IntMax) {
305       SignedOffset = Offset;
306       ExprCursor.consume(2);
307     } else if (N && N->getOp() == dwarf::DW_OP_minus &&
308                !SubRegisterSizeInBits && Offset <= IntMax + 1) {
309       SignedOffset = -static_cast<int64_t>(Offset);
310       ExprCursor.consume(2);
311     }
312   }
313 
314   if (FBReg)
315     addFBReg(SignedOffset);
316   else
317     addBReg(Reg.DwarfRegNo, SignedOffset);
318   DwarfRegs.clear();
319   return true;
320 }
321 
322 void DwarfExpression::setEntryValueFlags(const MachineLocation &Loc) {
323   LocationFlags |= EntryValue;
324   if (Loc.isIndirect())
325     LocationFlags |= Indirect;
326 }
327 
328 void DwarfExpression::setLocation(const MachineLocation &Loc,
329                                   const DIExpression *DIExpr) {
330   if (Loc.isIndirect())
331     // Do not treat entry value descriptions of indirect parameters as memory
332     // locations. This allows DwarfExpression::addReg() to add DW_OP_regN to an
333     // entry value description.
334     if (!DIExpr->isEntryValue())
335       setMemoryLocationKind();
336 
337   if (DIExpr->isEntryValue())
338     setEntryValueFlags(Loc);
339 }
340 
341 void DwarfExpression::beginEntryValueExpression(
342     DIExpressionCursor &ExprCursor) {
343   auto Op = ExprCursor.take();
344   (void)Op;
345   assert(Op && Op->getOp() == dwarf::DW_OP_LLVM_entry_value);
346   assert(!isMemoryLocation() &&
347          "We don't support entry values of memory locations yet");
348   assert(!IsEmittingEntryValue && "Already emitting entry value?");
349   assert(Op->getArg(0) == 1 &&
350          "Can currently only emit entry values covering a single operation");
351 
352   emitOp(CU.getDwarf5OrGNULocationAtom(dwarf::DW_OP_entry_value));
353   IsEmittingEntryValue = true;
354   enableTemporaryBuffer();
355 }
356 
357 void DwarfExpression::finalizeEntryValue() {
358   assert(IsEmittingEntryValue && "Entry value not open?");
359   disableTemporaryBuffer();
360 
361   // Emit the entry value's size operand.
362   unsigned Size = getTemporaryBufferSize();
363   emitUnsigned(Size);
364 
365   // Emit the entry value's DWARF block operand.
366   commitTemporaryBuffer();
367 
368   IsEmittingEntryValue = false;
369 }
370 
371 unsigned DwarfExpression::getOrCreateBaseType(unsigned BitSize,
372                                               dwarf::TypeKind Encoding) {
373   // Reuse the base_type if we already have one in this CU otherwise we
374   // create a new one.
375   unsigned I = 0, E = CU.ExprRefedBaseTypes.size();
376   for (; I != E; ++I)
377     if (CU.ExprRefedBaseTypes[I].BitSize == BitSize &&
378         CU.ExprRefedBaseTypes[I].Encoding == Encoding)
379       break;
380 
381   if (I == E)
382     CU.ExprRefedBaseTypes.emplace_back(BitSize, Encoding);
383   return I;
384 }
385 
386 /// Assuming a well-formed expression, match "DW_OP_deref*
387 /// DW_OP_LLVM_fragment?".
388 static bool isMemoryLocation(DIExpressionCursor ExprCursor) {
389   while (ExprCursor) {
390     auto Op = ExprCursor.take();
391     switch (Op->getOp()) {
392     case dwarf::DW_OP_deref:
393     case dwarf::DW_OP_LLVM_fragment:
394       break;
395     default:
396       return false;
397     }
398   }
399   return true;
400 }
401 
402 void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
403                                     unsigned FragmentOffsetInBits) {
404   // If we need to mask out a subregister, do it now, unless the next
405   // operation would emit an OpPiece anyway.
406   auto N = ExprCursor.peek();
407   if (SubRegisterSizeInBits && N && (N->getOp() != dwarf::DW_OP_LLVM_fragment))
408     maskSubRegister();
409 
410   Optional<DIExpression::ExprOperand> PrevConvertOp = None;
411 
412   while (ExprCursor) {
413     auto Op = ExprCursor.take();
414     uint64_t OpNum = Op->getOp();
415 
416     if (OpNum >= dwarf::DW_OP_reg0 && OpNum <= dwarf::DW_OP_reg31) {
417       emitOp(OpNum);
418       continue;
419     } else if (OpNum >= dwarf::DW_OP_breg0 && OpNum <= dwarf::DW_OP_breg31) {
420       addBReg(OpNum - dwarf::DW_OP_breg0, Op->getArg(0));
421       continue;
422     }
423 
424     switch (OpNum) {
425     case dwarf::DW_OP_LLVM_fragment: {
426       unsigned SizeInBits = Op->getArg(1);
427       unsigned FragmentOffset = Op->getArg(0);
428       // The fragment offset must have already been adjusted by emitting an
429       // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
430       // location.
431       assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
432       assert(SizeInBits >= OffsetInBits - FragmentOffset && "size underflow");
433 
434       // If addMachineReg already emitted DW_OP_piece operations to represent
435       // a super-register by splicing together sub-registers, subtract the size
436       // of the pieces that was already emitted.
437       SizeInBits -= OffsetInBits - FragmentOffset;
438 
439       // If addMachineReg requested a DW_OP_bit_piece to stencil out a
440       // sub-register that is smaller than the current fragment's size, use it.
441       if (SubRegisterSizeInBits)
442         SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
443 
444       // Emit a DW_OP_stack_value for implicit location descriptions.
445       if (isImplicitLocation())
446         addStackValue();
447 
448       // Emit the DW_OP_piece.
449       addOpPiece(SizeInBits, SubRegisterOffsetInBits);
450       setSubRegisterPiece(0, 0);
451       // Reset the location description kind.
452       LocationKind = Unknown;
453       return;
454     }
455     case dwarf::DW_OP_plus_uconst:
456       assert(!isRegisterLocation());
457       emitOp(dwarf::DW_OP_plus_uconst);
458       emitUnsigned(Op->getArg(0));
459       break;
460     case dwarf::DW_OP_plus:
461     case dwarf::DW_OP_minus:
462     case dwarf::DW_OP_mul:
463     case dwarf::DW_OP_div:
464     case dwarf::DW_OP_mod:
465     case dwarf::DW_OP_or:
466     case dwarf::DW_OP_and:
467     case dwarf::DW_OP_xor:
468     case dwarf::DW_OP_shl:
469     case dwarf::DW_OP_shr:
470     case dwarf::DW_OP_shra:
471     case dwarf::DW_OP_lit0:
472     case dwarf::DW_OP_not:
473     case dwarf::DW_OP_dup:
474     case dwarf::DW_OP_push_object_address:
475       emitOp(OpNum);
476       break;
477     case dwarf::DW_OP_deref:
478       assert(!isRegisterLocation());
479       if (!isMemoryLocation() && ::isMemoryLocation(ExprCursor))
480         // Turning this into a memory location description makes the deref
481         // implicit.
482         LocationKind = Memory;
483       else
484         emitOp(dwarf::DW_OP_deref);
485       break;
486     case dwarf::DW_OP_constu:
487       assert(!isRegisterLocation());
488       emitConstu(Op->getArg(0));
489       break;
490     case dwarf::DW_OP_LLVM_convert: {
491       unsigned BitSize = Op->getArg(0);
492       dwarf::TypeKind Encoding = static_cast<dwarf::TypeKind>(Op->getArg(1));
493       if (DwarfVersion >= 5) {
494         emitOp(dwarf::DW_OP_convert);
495         // If targeting a location-list; simply emit the index into the raw
496         // byte stream as ULEB128, DwarfDebug::emitDebugLocEntry has been
497         // fitted with means to extract it later.
498         // If targeting a inlined DW_AT_location; insert a DIEBaseTypeRef
499         // (containing the index and a resolve mechanism during emit) into the
500         // DIE value list.
501         emitBaseTypeRef(getOrCreateBaseType(BitSize, Encoding));
502       } else {
503         if (PrevConvertOp && PrevConvertOp->getArg(0) < BitSize) {
504           if (Encoding == dwarf::DW_ATE_signed)
505             emitLegacySExt(PrevConvertOp->getArg(0));
506           else if (Encoding == dwarf::DW_ATE_unsigned)
507             emitLegacyZExt(PrevConvertOp->getArg(0));
508           PrevConvertOp = None;
509         } else {
510           PrevConvertOp = Op;
511         }
512       }
513       break;
514     }
515     case dwarf::DW_OP_stack_value:
516       LocationKind = Implicit;
517       break;
518     case dwarf::DW_OP_swap:
519       assert(!isRegisterLocation());
520       emitOp(dwarf::DW_OP_swap);
521       break;
522     case dwarf::DW_OP_xderef:
523       assert(!isRegisterLocation());
524       emitOp(dwarf::DW_OP_xderef);
525       break;
526     case dwarf::DW_OP_deref_size:
527       emitOp(dwarf::DW_OP_deref_size);
528       emitData1(Op->getArg(0));
529       break;
530     case dwarf::DW_OP_LLVM_tag_offset:
531       TagOffset = Op->getArg(0);
532       break;
533     case dwarf::DW_OP_regx:
534       emitOp(dwarf::DW_OP_regx);
535       emitUnsigned(Op->getArg(0));
536       break;
537     case dwarf::DW_OP_bregx:
538       emitOp(dwarf::DW_OP_bregx);
539       emitUnsigned(Op->getArg(0));
540       emitSigned(Op->getArg(1));
541       break;
542     default:
543       llvm_unreachable("unhandled opcode found in expression");
544     }
545   }
546 
547   if (isImplicitLocation() && !isParameterValue())
548     // Turn this into an implicit location description.
549     addStackValue();
550 }
551 
552 /// add masking operations to stencil out a subregister.
553 void DwarfExpression::maskSubRegister() {
554   assert(SubRegisterSizeInBits && "no subregister was registered");
555   if (SubRegisterOffsetInBits > 0)
556     addShr(SubRegisterOffsetInBits);
557   uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
558   addAnd(Mask);
559 }
560 
561 void DwarfExpression::finalize() {
562   assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
563   // Emit any outstanding DW_OP_piece operations to mask out subregisters.
564   if (SubRegisterSizeInBits == 0)
565     return;
566   // Don't emit a DW_OP_piece for a subregister at offset 0.
567   if (SubRegisterOffsetInBits == 0)
568     return;
569   addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
570 }
571 
572 void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
573   if (!Expr || !Expr->isFragment())
574     return;
575 
576   uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
577   assert(FragmentOffset >= OffsetInBits &&
578          "overlapping or duplicate fragments");
579   if (FragmentOffset > OffsetInBits)
580     addOpPiece(FragmentOffset - OffsetInBits);
581   OffsetInBits = FragmentOffset;
582 }
583 
584 void DwarfExpression::emitLegacySExt(unsigned FromBits) {
585   // (((X >> (FromBits - 1)) * (~0)) << FromBits) | X
586   emitOp(dwarf::DW_OP_dup);
587   emitOp(dwarf::DW_OP_constu);
588   emitUnsigned(FromBits - 1);
589   emitOp(dwarf::DW_OP_shr);
590   emitOp(dwarf::DW_OP_lit0);
591   emitOp(dwarf::DW_OP_not);
592   emitOp(dwarf::DW_OP_mul);
593   emitOp(dwarf::DW_OP_constu);
594   emitUnsigned(FromBits);
595   emitOp(dwarf::DW_OP_shl);
596   emitOp(dwarf::DW_OP_or);
597 }
598 
599 void DwarfExpression::emitLegacyZExt(unsigned FromBits) {
600   // (X & (1 << FromBits - 1))
601   emitOp(dwarf::DW_OP_constu);
602   emitUnsigned((1ULL << FromBits) - 1);
603   emitOp(dwarf::DW_OP_and);
604 }
605 
606 void DwarfExpression::addWasmLocation(unsigned Index, uint64_t Offset) {
607   assert(LocationKind == Implicit || LocationKind == Unknown);
608   LocationKind = Implicit;
609   emitOp(dwarf::DW_OP_WASM_location);
610   emitUnsigned(Index);
611   emitUnsigned(Offset);
612 }
613