1 //===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains support for writing dwarf debug info into asm files.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "DwarfExpression.h"
15 #include "DwarfDebug.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/CodeGen/AsmPrinter.h"
18 #include "llvm/Support/Dwarf.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
21 #include "llvm/Target/TargetSubtargetInfo.h"
22 
23 using namespace llvm;
24 
25 void DwarfExpression::addReg(int DwarfReg, const char *Comment) {
26   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
27   if (DwarfReg < 32) {
28     emitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
29   } else {
30     emitOp(dwarf::DW_OP_regx, Comment);
31     emitUnsigned(DwarfReg);
32   }
33 }
34 
35 void DwarfExpression::addRegIndirect(int DwarfReg, int Offset) {
36   assert(DwarfReg >= 0 && "invalid negative dwarf register number");
37   if (DwarfReg < 32) {
38     emitOp(dwarf::DW_OP_breg0 + DwarfReg);
39   } else {
40     emitOp(dwarf::DW_OP_bregx);
41     emitUnsigned(DwarfReg);
42   }
43   emitSigned(Offset);
44 }
45 
46 void DwarfExpression::addOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
47   if (!SizeInBits)
48     return;
49 
50   const unsigned SizeOfByte = 8;
51   if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
52     emitOp(dwarf::DW_OP_bit_piece);
53     emitUnsigned(SizeInBits);
54     emitUnsigned(OffsetInBits);
55   } else {
56     emitOp(dwarf::DW_OP_piece);
57     unsigned ByteSize = SizeInBits / SizeOfByte;
58     emitUnsigned(ByteSize);
59   }
60   this->OffsetInBits += SizeInBits;
61 }
62 
63 void DwarfExpression::addShr(unsigned ShiftBy) {
64   emitOp(dwarf::DW_OP_constu);
65   emitUnsigned(ShiftBy);
66   emitOp(dwarf::DW_OP_shr);
67 }
68 
69 void DwarfExpression::addAnd(unsigned Mask) {
70   emitOp(dwarf::DW_OP_constu);
71   emitUnsigned(Mask);
72   emitOp(dwarf::DW_OP_and);
73 }
74 
75 bool DwarfExpression::addMachineRegIndirect(const TargetRegisterInfo &TRI,
76                                             unsigned MachineReg, int Offset) {
77   if (isFrameRegister(TRI, MachineReg)) {
78     // If variable offset is based in frame register then use fbreg.
79     emitOp(dwarf::DW_OP_fbreg);
80     emitSigned(Offset);
81     return true;
82   }
83 
84   int DwarfReg = TRI.getDwarfRegNum(MachineReg, false);
85   if (DwarfReg < 0)
86     return false;
87 
88   addRegIndirect(DwarfReg, Offset);
89   return true;
90 }
91 
92 bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
93                                     unsigned MachineReg, unsigned MaxSize) {
94   if (!TRI.isPhysicalRegister(MachineReg))
95     return false;
96 
97   int Reg = TRI.getDwarfRegNum(MachineReg, false);
98 
99   // If this is a valid register number, emit it.
100   if (Reg >= 0) {
101     DwarfRegs.push_back({Reg, 0, nullptr});
102     return true;
103   }
104 
105   // Walk up the super-register chain until we find a valid number.
106   // For example, EAX on x86_64 is a 32-bit fragment of RAX with offset 0.
107   for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
108     Reg = TRI.getDwarfRegNum(*SR, false);
109     if (Reg >= 0) {
110       unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
111       unsigned Size = TRI.getSubRegIdxSize(Idx);
112       unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
113       DwarfRegs.push_back({Reg, 0, "super-register"});
114       // Use a DW_OP_bit_piece to describe the sub-register.
115       setSubRegisterPiece(Size, RegOffset);
116       return true;
117     }
118   }
119 
120   // Otherwise, attempt to find a covering set of sub-register numbers.
121   // For example, Q0 on ARM is a composition of D0+D1.
122   unsigned CurPos = 0;
123   // The size of the register in bits, assuming 8 bits per byte.
124   unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
125   // Keep track of the bits in the register we already emitted, so we
126   // can avoid emitting redundant aliasing subregs.
127   SmallBitVector Coverage(RegSize, false);
128   for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
129     unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
130     unsigned Size = TRI.getSubRegIdxSize(Idx);
131     unsigned Offset = TRI.getSubRegIdxOffset(Idx);
132     Reg = TRI.getDwarfRegNum(*SR, false);
133 
134     // Intersection between the bits we already emitted and the bits
135     // covered by this subregister.
136     SmallBitVector Intersection(RegSize, false);
137     Intersection.set(Offset, Offset + Size);
138     Intersection ^= Coverage;
139 
140     // If this sub-register has a DWARF number and we haven't covered
141     // its range, emit a DWARF piece for it.
142     if (Reg >= 0 && Intersection.any()) {
143       // Emit a piece for any gap in the coverage.
144       if (Offset > CurPos)
145         DwarfRegs.push_back({-1, Offset - CurPos, "missing"});
146       DwarfRegs.push_back(
147           {Reg, std::min<unsigned>(Size, MaxSize - Offset), "sub-register"});
148       if (Offset >= MaxSize)
149 	break;
150 
151       // Mark it as emitted.
152       Coverage.set(Offset, Offset + Size);
153       CurPos = Offset + Size;
154     }
155   }
156 
157   return CurPos;
158 }
159 
160 void DwarfExpression::addStackValue() {
161   if (DwarfVersion >= 4)
162     emitOp(dwarf::DW_OP_stack_value);
163 }
164 
165 void DwarfExpression::addSignedConstant(int64_t Value) {
166   emitOp(dwarf::DW_OP_consts);
167   emitSigned(Value);
168   addStackValue();
169 }
170 
171 void DwarfExpression::addUnsignedConstant(uint64_t Value) {
172   emitOp(dwarf::DW_OP_constu);
173   emitUnsigned(Value);
174   addStackValue();
175 }
176 
177 void DwarfExpression::addUnsignedConstant(const APInt &Value) {
178   unsigned Size = Value.getBitWidth();
179   const uint64_t *Data = Value.getRawData();
180 
181   // Chop it up into 64-bit pieces, because that's the maximum that
182   // addUnsignedConstant takes.
183   unsigned Offset = 0;
184   while (Offset < Size) {
185     addUnsignedConstant(*Data++);
186     if (Offset == 0 && Size <= 64)
187       break;
188     addOpPiece(std::min(Size-Offset, 64u), Offset);
189     Offset += 64;
190   }
191 }
192 
193 bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
194                                               DIExpressionCursor &ExprCursor,
195                                               unsigned MachineReg,
196                                               unsigned FragmentOffsetInBits) {
197   auto Fragment = ExprCursor.getFragmentInfo();
198   if (!addMachineReg(TRI, MachineReg, Fragment ? Fragment->SizeInBits : ~1U))
199     return false;
200 
201   bool HasComplexExpression = false;
202   auto Op = ExprCursor.peek();
203   if (Op && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
204     HasComplexExpression = true;
205 
206   // If the register can only be described by a complex expression (i.e.,
207   // multiple subregisters) it doesn't safely compose with another complex
208   // expression. For example, it is not possible to apply a DW_OP_deref
209   // operation to multiple DW_OP_pieces.
210   if (HasComplexExpression && DwarfRegs.size() > 1) {
211     DwarfRegs.clear();
212     return false;
213   }
214 
215   if (!HasComplexExpression) {
216     for (auto &Reg : DwarfRegs) {
217       if (Reg.DwarfRegNo >= 0)
218         addReg(Reg.DwarfRegNo, Reg.Comment);
219       addOpPiece(Reg.Size);
220     }
221     DwarfRegs.clear();
222     return true;
223   }
224 
225   // Pattern-match combinations for which more efficient representations exist
226   // first.
227   assert(DwarfRegs.size() == 1);
228   auto Reg = DwarfRegs[0];
229   assert(Reg.Size == 0 && "subregister has same size as superregister");
230   switch (Op->getOp()) {
231   default: {
232     addReg(Reg.DwarfRegNo, 0);
233     break;
234   }
235   case dwarf::DW_OP_plus:
236   case dwarf::DW_OP_minus: {
237     // [DW_OP_reg,Offset,DW_OP_plus, DW_OP_deref] --> [DW_OP_breg, Offset].
238     // [DW_OP_reg,Offset,DW_OP_minus,DW_OP_deref] --> [DW_OP_breg,-Offset].
239     auto N = ExprCursor.peekNext();
240     if (N && N->getOp() == dwarf::DW_OP_deref) {
241       int Offset = Op->getArg(0);
242       int SignedOffset = (Op->getOp() == dwarf::DW_OP_plus) ? Offset : -Offset;
243       if (isFrameRegister(TRI, MachineReg)) {
244         // If variable offset is based in frame register then use fbreg.
245         emitOp(dwarf::DW_OP_fbreg);
246         emitSigned(SignedOffset);
247       } else
248         addRegIndirect(Reg.DwarfRegNo, SignedOffset);
249       ExprCursor.consume(2);
250       break;
251     }
252     addReg(Reg.DwarfRegNo, 0);
253     break;
254   }
255   case dwarf::DW_OP_deref:
256     // [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
257     addRegIndirect(Reg.DwarfRegNo, 0);
258     ExprCursor.take();
259     break;
260   }
261   DwarfRegs.clear();
262   return true;
263 }
264 
265 void DwarfExpression::addExpression(DIExpressionCursor &&ExprCursor,
266                                     unsigned FragmentOffsetInBits) {
267   while (ExprCursor) {
268     auto Op = ExprCursor.take();
269 
270     // If we need to mask out a subregister, do it now, unless the next
271     // operation would emit an OpPiece anyway.
272     if (SubRegisterSizeInBits && Op->getOp() != dwarf::DW_OP_LLVM_fragment)
273       maskSubRegister();
274 
275     switch (Op->getOp()) {
276     case dwarf::DW_OP_LLVM_fragment: {
277       unsigned SizeInBits = Op->getArg(1);
278       unsigned FragmentOffset = Op->getArg(0);
279       // The fragment offset must have already been adjusted by emitting an
280       // empty DW_OP_piece / DW_OP_bit_piece before we emitted the base
281       // location.
282       assert(OffsetInBits >= FragmentOffset && "fragment offset not added?");
283 
284       // If \a addMachineReg already emitted DW_OP_piece operations to represent
285       // a super-register by splicing together sub-registers, subtract the size
286       // of the pieces that was already emitted.
287       SizeInBits -= OffsetInBits - FragmentOffset;
288 
289       // If \a addMachineReg requested a DW_OP_bit_piece to stencil out a
290       // sub-register that is smaller than the current fragment's size, use it.
291       if (SubRegisterSizeInBits)
292         SizeInBits = std::min<unsigned>(SizeInBits, SubRegisterSizeInBits);
293 
294       addOpPiece(SizeInBits, SubRegisterOffsetInBits);
295       setSubRegisterPiece(0, 0);
296       break;
297     }
298     case dwarf::DW_OP_plus:
299       emitOp(dwarf::DW_OP_plus_uconst);
300       emitUnsigned(Op->getArg(0));
301       break;
302     case dwarf::DW_OP_minus:
303       // There is no OP_minus_uconst.
304       emitOp(dwarf::DW_OP_constu);
305       emitUnsigned(Op->getArg(0));
306       emitOp(dwarf::DW_OP_minus);
307       break;
308     case dwarf::DW_OP_deref:
309       emitOp(dwarf::DW_OP_deref);
310       break;
311     case dwarf::DW_OP_constu:
312       emitOp(dwarf::DW_OP_constu);
313       emitUnsigned(Op->getArg(0));
314       break;
315     case dwarf::DW_OP_stack_value:
316       addStackValue();
317       break;
318     case dwarf::DW_OP_swap:
319       emitOp(dwarf::DW_OP_swap);
320       break;
321     case dwarf::DW_OP_xderef:
322       emitOp(dwarf::DW_OP_xderef);
323       break;
324     default:
325       llvm_unreachable("unhandled opcode found in expression");
326     }
327   }
328 }
329 
330 /// add masking operations to stencil out a subregister.
331 void DwarfExpression::maskSubRegister() {
332   assert(SubRegisterSizeInBits && "no subregister was registered");
333   if (SubRegisterOffsetInBits > 0)
334     addShr(SubRegisterOffsetInBits);
335   uint64_t Mask = (1ULL << (uint64_t)SubRegisterSizeInBits) - 1ULL;
336   addAnd(Mask);
337 }
338 
339 
340 void DwarfExpression::finalize() {
341   assert(DwarfRegs.size() == 0 && "dwarf registers not emitted");
342   // Emit any outstanding DW_OP_piece operations to mask out subregisters.
343   if (SubRegisterSizeInBits == 0)
344     return;
345   // Don't emit a DW_OP_piece for a subregister at offset 0.
346   if (SubRegisterOffsetInBits == 0)
347     return;
348   addOpPiece(SubRegisterSizeInBits, SubRegisterOffsetInBits);
349 }
350 
351 void DwarfExpression::addFragmentOffset(const DIExpression *Expr) {
352   if (!Expr || !Expr->isFragment())
353     return;
354 
355   uint64_t FragmentOffset = Expr->getFragmentInfo()->OffsetInBits;
356   assert(FragmentOffset >= OffsetInBits &&
357          "overlapping or duplicate fragments");
358   if (FragmentOffset > OffsetInBits)
359     addOpPiece(FragmentOffset - OffsetInBits);
360   OffsetInBits = FragmentOffset;
361 }
362