1 //===-- AsmPrinterDwarf.cpp - AsmPrinter Dwarf Support --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the Dwarf emissions parts of AsmPrinter.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "asm-printer"
15 #include "ByteStreamer.h"
16 #include "llvm/CodeGen/AsmPrinter.h"
17 #include "llvm/ADT/SmallBitVector.h"
18 #include "llvm/ADT/Twine.h"
19 #include "llvm/IR/DataLayout.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCSection.h"
22 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSymbol.h"
24 #include "llvm/MC/MachineLocation.h"
25 #include "llvm/Support/Dwarf.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Target/TargetFrameLowering.h"
28 #include "llvm/Target/TargetLoweringObjectFile.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 using namespace llvm;
32 
33 //===----------------------------------------------------------------------===//
34 // Dwarf Emission Helper Routines
35 //===----------------------------------------------------------------------===//
36 
37 /// EmitSLEB128 - emit the specified signed leb128 value.
38 void AsmPrinter::EmitSLEB128(int64_t Value, const char *Desc) const {
39   if (isVerbose() && Desc)
40     OutStreamer.AddComment(Desc);
41 
42   OutStreamer.EmitSLEB128IntValue(Value);
43 }
44 
45 /// EmitULEB128 - emit the specified signed leb128 value.
46 void AsmPrinter::EmitULEB128(uint64_t Value, const char *Desc,
47                              unsigned PadTo) const {
48   if (isVerbose() && Desc)
49     OutStreamer.AddComment(Desc);
50 
51   OutStreamer.EmitULEB128IntValue(Value, PadTo);
52 }
53 
54 /// EmitCFAByte - Emit a .byte 42 directive for a DW_CFA_xxx value.
55 void AsmPrinter::EmitCFAByte(unsigned Val) const {
56   if (isVerbose()) {
57     if (Val >= dwarf::DW_CFA_offset && Val < dwarf::DW_CFA_offset + 64)
58       OutStreamer.AddComment("DW_CFA_offset + Reg (" +
59                              Twine(Val - dwarf::DW_CFA_offset) + ")");
60     else
61       OutStreamer.AddComment(dwarf::CallFrameString(Val));
62   }
63   OutStreamer.EmitIntValue(Val, 1);
64 }
65 
66 static const char *DecodeDWARFEncoding(unsigned Encoding) {
67   switch (Encoding) {
68   case dwarf::DW_EH_PE_absptr:
69     return "absptr";
70   case dwarf::DW_EH_PE_omit:
71     return "omit";
72   case dwarf::DW_EH_PE_pcrel:
73     return "pcrel";
74   case dwarf::DW_EH_PE_udata4:
75     return "udata4";
76   case dwarf::DW_EH_PE_udata8:
77     return "udata8";
78   case dwarf::DW_EH_PE_sdata4:
79     return "sdata4";
80   case dwarf::DW_EH_PE_sdata8:
81     return "sdata8";
82   case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4:
83     return "pcrel udata4";
84   case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4:
85     return "pcrel sdata4";
86   case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8:
87     return "pcrel udata8";
88   case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8:
89     return "pcrel sdata8";
90   case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4
91       :
92     return "indirect pcrel udata4";
93   case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
94       :
95     return "indirect pcrel sdata4";
96   case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8
97       :
98     return "indirect pcrel udata8";
99   case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8
100       :
101     return "indirect pcrel sdata8";
102   }
103 
104   return "<unknown encoding>";
105 }
106 
107 /// EmitEncodingByte - Emit a .byte 42 directive that corresponds to an
108 /// encoding.  If verbose assembly output is enabled, we output comments
109 /// describing the encoding.  Desc is an optional string saying what the
110 /// encoding is specifying (e.g. "LSDA").
111 void AsmPrinter::EmitEncodingByte(unsigned Val, const char *Desc) const {
112   if (isVerbose()) {
113     if (Desc)
114       OutStreamer.AddComment(Twine(Desc) + " Encoding = " +
115                              Twine(DecodeDWARFEncoding(Val)));
116     else
117       OutStreamer.AddComment(Twine("Encoding = ") + DecodeDWARFEncoding(Val));
118   }
119 
120   OutStreamer.EmitIntValue(Val, 1);
121 }
122 
123 /// GetSizeOfEncodedValue - Return the size of the encoding in bytes.
124 unsigned AsmPrinter::GetSizeOfEncodedValue(unsigned Encoding) const {
125   if (Encoding == dwarf::DW_EH_PE_omit)
126     return 0;
127 
128   switch (Encoding & 0x07) {
129   default:
130     llvm_unreachable("Invalid encoded value.");
131   case dwarf::DW_EH_PE_absptr:
132     return TM.getDataLayout()->getPointerSize();
133   case dwarf::DW_EH_PE_udata2:
134     return 2;
135   case dwarf::DW_EH_PE_udata4:
136     return 4;
137   case dwarf::DW_EH_PE_udata8:
138     return 8;
139   }
140 }
141 
142 void AsmPrinter::EmitTTypeReference(const GlobalValue *GV,
143                                     unsigned Encoding) const {
144   if (GV) {
145     const TargetLoweringObjectFile &TLOF = getObjFileLowering();
146 
147     const MCExpr *Exp =
148         TLOF.getTTypeGlobalReference(GV, Encoding, *Mang, TM, MMI, OutStreamer);
149     OutStreamer.EmitValue(Exp, GetSizeOfEncodedValue(Encoding));
150   } else
151     OutStreamer.EmitIntValue(0, GetSizeOfEncodedValue(Encoding));
152 }
153 
154 /// EmitSectionOffset - Emit the 4-byte offset of Label from the start of its
155 /// section.  This can be done with a special directive if the target supports
156 /// it (e.g. cygwin) or by emitting it as an offset from a label at the start
157 /// of the section.
158 ///
159 /// SectionLabel is a temporary label emitted at the start of the section that
160 /// Label lives in.
161 void AsmPrinter::EmitSectionOffset(const MCSymbol *Label,
162                                    const MCSymbol *SectionLabel) const {
163   // On COFF targets, we have to emit the special .secrel32 directive.
164   if (MAI->needsDwarfSectionOffsetDirective()) {
165     OutStreamer.EmitCOFFSecRel32(Label);
166     return;
167   }
168 
169   // Get the section that we're referring to, based on SectionLabel.
170   const MCSection &Section = SectionLabel->getSection();
171 
172   // If Label has already been emitted, verify that it is in the same section as
173   // section label for sanity.
174   assert((!Label->isInSection() || &Label->getSection() == &Section) &&
175          "Section offset using wrong section base for label");
176 
177   // If the section in question will end up with an address of 0 anyway, we can
178   // just emit an absolute reference to save a relocation.
179   if (Section.isBaseAddressKnownZero()) {
180     OutStreamer.EmitSymbolValue(Label, 4);
181     return;
182   }
183 
184   // Otherwise, emit it as a label difference from the start of the section.
185   EmitLabelDifference(Label, SectionLabel, 4);
186 }
187 
188 /// Emit a dwarf register operation.
189 static void emitDwarfRegOp(ByteStreamer &Streamer, int Reg) {
190   assert(Reg >= 0);
191   if (Reg < 32) {
192     Streamer.EmitInt8(dwarf::DW_OP_reg0 + Reg,
193                       dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
194   } else {
195     Streamer.EmitInt8(dwarf::DW_OP_regx, "DW_OP_regx");
196     Streamer.EmitULEB128(Reg, Twine(Reg));
197   }
198 }
199 
200 /// Emit an (double-)indirect dwarf register operation.
201 static void emitDwarfRegOpIndirect(ByteStreamer &Streamer, int Reg, int Offset,
202                                    bool Deref) {
203   assert(Reg >= 0);
204   if (Reg < 32) {
205     Streamer.EmitInt8(dwarf::DW_OP_breg0 + Reg,
206                       dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg));
207   } else {
208     Streamer.EmitInt8(dwarf::DW_OP_bregx, "DW_OP_bregx");
209     Streamer.EmitULEB128(Reg, Twine(Reg));
210   }
211   Streamer.EmitSLEB128(Offset);
212   if (Deref)
213     Streamer.EmitInt8(dwarf::DW_OP_deref, "DW_OP_deref");
214 }
215 
216 /// Emit a dwarf register operation for describing
217 /// - a small value occupying only part of a register or
218 /// - a small register representing only part of a value.
219 static void emitDwarfOpPiece(ByteStreamer &Streamer, unsigned Size,
220                              unsigned Offset) {
221   assert(Size > 0);
222   if (Offset > 0) {
223     Streamer.EmitInt8(dwarf::DW_OP_bit_piece, "DW_OP_bit_piece");
224     Streamer.EmitULEB128(Size, Twine(Size));
225     Streamer.EmitULEB128(Offset, Twine(Offset));
226   } else {
227     Streamer.EmitInt8(dwarf::DW_OP_piece, "DW_OP_piece");
228     unsigned ByteSize = Size / 8; // Assuming 8 bits per byte.
229     Streamer.EmitULEB128(ByteSize, Twine(ByteSize));
230   }
231 }
232 
233 /// Some targets do not provide a DWARF register number for every
234 /// register.  This function attempts to emit a dwarf register by
235 /// emitting a piece of a super-register or by piecing together
236 /// multiple subregisters that alias the register.
237 static void EmitDwarfRegOpPiece(ByteStreamer &Streamer, const AsmPrinter &AP,
238                                 const MachineLocation &MLoc) {
239   assert(!MLoc.isIndirect());
240   const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
241   int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
242 
243   // Walk up the super-register chain until we find a valid number.
244   // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
245   for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
246     Reg = TRI->getDwarfRegNum(*SR, false);
247     if (Reg >= 0) {
248       unsigned Idx = TRI->getSubRegIndex(*SR, MLoc.getReg());
249       unsigned Size = TRI->getSubRegIdxSize(Idx);
250       unsigned Offset = TRI->getSubRegIdxOffset(Idx);
251       AP.OutStreamer.AddComment("super-register");
252       emitDwarfRegOp(Streamer, Reg);
253       emitDwarfOpPiece(Streamer, Size, Offset);
254       return;
255     }
256   }
257 
258   // Otherwise, attempt to find a covering set of sub-register numbers.
259   // For example, Q0 on ARM is a composition of D0+D1.
260   //
261   // Keep track of the current position so we can emit the more
262   // efficient DW_OP_piece.
263   unsigned CurPos = 0;
264   // The size of the register in bits, assuming 8 bits per byte.
265   unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize() * 8;
266   // Keep track of the bits in the register we already emitted, so we
267   // can avoid emitting redundant aliasing subregs.
268   SmallBitVector Coverage(RegSize, false);
269   for (MCSubRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
270     unsigned Idx = TRI->getSubRegIndex(MLoc.getReg(), *SR);
271     unsigned Size = TRI->getSubRegIdxSize(Idx);
272     unsigned Offset = TRI->getSubRegIdxOffset(Idx);
273     Reg = TRI->getDwarfRegNum(*SR, false);
274 
275     // Intersection between the bits we already emitted and the bits
276     // covered by this subregister.
277     SmallBitVector Intersection(RegSize, false);
278     Intersection.set(Offset, Offset + Size);
279     Intersection ^= Coverage;
280 
281     // If this sub-register has a DWARF number and we haven't covered
282     // its range, emit a DWARF piece for it.
283     if (Reg >= 0 && Intersection.any()) {
284       AP.OutStreamer.AddComment("sub-register");
285       emitDwarfRegOp(Streamer, Reg);
286       emitDwarfOpPiece(Streamer, Size, Offset == CurPos ? 0 : Offset);
287       CurPos = Offset + Size;
288 
289       // Mark it as emitted.
290       Coverage.set(Offset, Offset + Size);
291     }
292   }
293 
294   if (CurPos == 0) {
295     // FIXME: We have no reasonable way of handling errors in here.
296     Streamer.EmitInt8(dwarf::DW_OP_nop,
297                       "nop (could not find a dwarf register number)");
298   }
299 }
300 
301 /// EmitDwarfRegOp - Emit dwarf register operation.
302 void AsmPrinter::EmitDwarfRegOp(ByteStreamer &Streamer,
303                                 const MachineLocation &MLoc,
304                                 bool Indirect) const {
305   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
306   int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
307   if (Reg < 0) {
308     // We assume that pointers are always in an addressable register.
309     if (Indirect || MLoc.isIndirect()) {
310       // FIXME: We have no reasonable way of handling errors in here. The
311       // caller might be in the middle of a dwarf expression. We should
312       // probably assert that Reg >= 0 once debug info generation is more
313       // mature.
314       Streamer.EmitInt8(dwarf::DW_OP_nop,
315                         "nop (invalid dwarf register number for indirect loc)");
316       return;
317     }
318 
319     // Attempt to find a valid super- or sub-register.
320     if (!Indirect && !MLoc.isIndirect())
321       return EmitDwarfRegOpPiece(Streamer, *this, MLoc);
322   }
323 
324   if (MLoc.isIndirect())
325     emitDwarfRegOpIndirect(Streamer, Reg, MLoc.getOffset(), Indirect);
326   else if (Indirect)
327     emitDwarfRegOpIndirect(Streamer, Reg, 0, false);
328   else
329     emitDwarfRegOp(Streamer, Reg);
330 }
331 
332 //===----------------------------------------------------------------------===//
333 // Dwarf Lowering Routines
334 //===----------------------------------------------------------------------===//
335 
336 void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const {
337   switch (Inst.getOperation()) {
338   default:
339     llvm_unreachable("Unexpected instruction");
340   case MCCFIInstruction::OpDefCfaOffset:
341     OutStreamer.EmitCFIDefCfaOffset(Inst.getOffset());
342     break;
343   case MCCFIInstruction::OpDefCfa:
344     OutStreamer.EmitCFIDefCfa(Inst.getRegister(), Inst.getOffset());
345     break;
346   case MCCFIInstruction::OpDefCfaRegister:
347     OutStreamer.EmitCFIDefCfaRegister(Inst.getRegister());
348     break;
349   case MCCFIInstruction::OpOffset:
350     OutStreamer.EmitCFIOffset(Inst.getRegister(), Inst.getOffset());
351     break;
352   case MCCFIInstruction::OpRegister:
353     OutStreamer.EmitCFIRegister(Inst.getRegister(), Inst.getRegister2());
354     break;
355   case MCCFIInstruction::OpWindowSave:
356     OutStreamer.EmitCFIWindowSave();
357     break;
358   }
359 }
360