1 //===-- AsmPrinterDwarf.cpp - AsmPrinter Dwarf Support --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the Dwarf emissions parts of AsmPrinter.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "ByteStreamer.h"
15 #include "llvm/CodeGen/AsmPrinter.h"
16 #include "llvm/ADT/SmallBitVector.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/IR/DataLayout.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCSection.h"
21 #include "llvm/MC/MCStreamer.h"
22 #include "llvm/MC/MCSymbol.h"
23 #include "llvm/MC/MachineLocation.h"
24 #include "llvm/Support/Dwarf.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Target/TargetFrameLowering.h"
27 #include "llvm/Target/TargetLoweringObjectFile.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
30 using namespace llvm;
31 
32 #define DEBUG_TYPE "asm-printer"
33 
34 //===----------------------------------------------------------------------===//
35 // Dwarf Emission Helper Routines
36 //===----------------------------------------------------------------------===//
37 
38 /// EmitSLEB128 - emit the specified signed leb128 value.
39 void AsmPrinter::EmitSLEB128(int64_t Value, const char *Desc) const {
40   if (isVerbose() && Desc)
41     OutStreamer.AddComment(Desc);
42 
43   OutStreamer.EmitSLEB128IntValue(Value);
44 }
45 
46 /// EmitULEB128 - emit the specified signed leb128 value.
47 void AsmPrinter::EmitULEB128(uint64_t Value, const char *Desc,
48                              unsigned PadTo) const {
49   if (isVerbose() && Desc)
50     OutStreamer.AddComment(Desc);
51 
52   OutStreamer.EmitULEB128IntValue(Value, PadTo);
53 }
54 
55 /// EmitCFAByte - Emit a .byte 42 directive for a DW_CFA_xxx value.
56 void AsmPrinter::EmitCFAByte(unsigned Val) const {
57   if (isVerbose()) {
58     if (Val >= dwarf::DW_CFA_offset && Val < dwarf::DW_CFA_offset + 64)
59       OutStreamer.AddComment("DW_CFA_offset + Reg (" +
60                              Twine(Val - dwarf::DW_CFA_offset) + ")");
61     else
62       OutStreamer.AddComment(dwarf::CallFrameString(Val));
63   }
64   OutStreamer.EmitIntValue(Val, 1);
65 }
66 
67 static const char *DecodeDWARFEncoding(unsigned Encoding) {
68   switch (Encoding) {
69   case dwarf::DW_EH_PE_absptr:
70     return "absptr";
71   case dwarf::DW_EH_PE_omit:
72     return "omit";
73   case dwarf::DW_EH_PE_pcrel:
74     return "pcrel";
75   case dwarf::DW_EH_PE_udata4:
76     return "udata4";
77   case dwarf::DW_EH_PE_udata8:
78     return "udata8";
79   case dwarf::DW_EH_PE_sdata4:
80     return "sdata4";
81   case dwarf::DW_EH_PE_sdata8:
82     return "sdata8";
83   case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4:
84     return "pcrel udata4";
85   case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4:
86     return "pcrel sdata4";
87   case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8:
88     return "pcrel udata8";
89   case dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8:
90     return "pcrel sdata8";
91   case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata4
92       :
93     return "indirect pcrel udata4";
94   case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata4
95       :
96     return "indirect pcrel sdata4";
97   case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8
98       :
99     return "indirect pcrel udata8";
100   case dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_sdata8
101       :
102     return "indirect pcrel sdata8";
103   }
104 
105   return "<unknown encoding>";
106 }
107 
108 /// EmitEncodingByte - Emit a .byte 42 directive that corresponds to an
109 /// encoding.  If verbose assembly output is enabled, we output comments
110 /// describing the encoding.  Desc is an optional string saying what the
111 /// encoding is specifying (e.g. "LSDA").
112 void AsmPrinter::EmitEncodingByte(unsigned Val, const char *Desc) const {
113   if (isVerbose()) {
114     if (Desc)
115       OutStreamer.AddComment(Twine(Desc) + " Encoding = " +
116                              Twine(DecodeDWARFEncoding(Val)));
117     else
118       OutStreamer.AddComment(Twine("Encoding = ") + DecodeDWARFEncoding(Val));
119   }
120 
121   OutStreamer.EmitIntValue(Val, 1);
122 }
123 
124 /// GetSizeOfEncodedValue - Return the size of the encoding in bytes.
125 unsigned AsmPrinter::GetSizeOfEncodedValue(unsigned Encoding) const {
126   if (Encoding == dwarf::DW_EH_PE_omit)
127     return 0;
128 
129   switch (Encoding & 0x07) {
130   default:
131     llvm_unreachable("Invalid encoded value.");
132   case dwarf::DW_EH_PE_absptr:
133     return TM.getDataLayout()->getPointerSize();
134   case dwarf::DW_EH_PE_udata2:
135     return 2;
136   case dwarf::DW_EH_PE_udata4:
137     return 4;
138   case dwarf::DW_EH_PE_udata8:
139     return 8;
140   }
141 }
142 
143 void AsmPrinter::EmitTTypeReference(const GlobalValue *GV,
144                                     unsigned Encoding) const {
145   if (GV) {
146     const TargetLoweringObjectFile &TLOF = getObjFileLowering();
147 
148     const MCExpr *Exp =
149         TLOF.getTTypeGlobalReference(GV, Encoding, *Mang, TM, MMI, OutStreamer);
150     OutStreamer.EmitValue(Exp, GetSizeOfEncodedValue(Encoding));
151   } else
152     OutStreamer.EmitIntValue(0, GetSizeOfEncodedValue(Encoding));
153 }
154 
155 /// EmitSectionOffset - Emit the 4-byte offset of Label from the start of its
156 /// section.  This can be done with a special directive if the target supports
157 /// it (e.g. cygwin) or by emitting it as an offset from a label at the start
158 /// of the section.
159 ///
160 /// SectionLabel is a temporary label emitted at the start of the section that
161 /// Label lives in.
162 void AsmPrinter::EmitSectionOffset(const MCSymbol *Label,
163                                    const MCSymbol *SectionLabel) const {
164   // On COFF targets, we have to emit the special .secrel32 directive.
165   if (MAI->needsDwarfSectionOffsetDirective()) {
166     OutStreamer.EmitCOFFSecRel32(Label);
167     return;
168   }
169 
170   // Get the section that we're referring to, based on SectionLabel.
171   const MCSection &Section = SectionLabel->getSection();
172 
173   // If Label has already been emitted, verify that it is in the same section as
174   // section label for sanity.
175   assert((!Label->isInSection() || &Label->getSection() == &Section) &&
176          "Section offset using wrong section base for label");
177 
178   // If the section in question will end up with an address of 0 anyway, we can
179   // just emit an absolute reference to save a relocation.
180   if (Section.isBaseAddressKnownZero()) {
181     OutStreamer.EmitSymbolValue(Label, 4);
182     return;
183   }
184 
185   // Otherwise, emit it as a label difference from the start of the section.
186   EmitLabelDifference(Label, SectionLabel, 4);
187 }
188 
189 /// Emit a dwarf register operation.
190 static void emitDwarfRegOp(ByteStreamer &Streamer, int Reg) {
191   assert(Reg >= 0);
192   if (Reg < 32) {
193     Streamer.EmitInt8(dwarf::DW_OP_reg0 + Reg,
194                       dwarf::OperationEncodingString(dwarf::DW_OP_reg0 + Reg));
195   } else {
196     Streamer.EmitInt8(dwarf::DW_OP_regx, "DW_OP_regx");
197     Streamer.EmitULEB128(Reg, Twine(Reg));
198   }
199 }
200 
201 /// Emit an (double-)indirect dwarf register operation.
202 static void emitDwarfRegOpIndirect(ByteStreamer &Streamer, int Reg, int Offset,
203                                    bool Deref) {
204   assert(Reg >= 0);
205   if (Reg < 32) {
206     Streamer.EmitInt8(dwarf::DW_OP_breg0 + Reg,
207                       dwarf::OperationEncodingString(dwarf::DW_OP_breg0 + Reg));
208   } else {
209     Streamer.EmitInt8(dwarf::DW_OP_bregx, "DW_OP_bregx");
210     Streamer.EmitULEB128(Reg, Twine(Reg));
211   }
212   Streamer.EmitSLEB128(Offset);
213   if (Deref)
214     Streamer.EmitInt8(dwarf::DW_OP_deref, "DW_OP_deref");
215 }
216 
217 /// Emit a dwarf register operation for describing
218 /// - a small value occupying only part of a register or
219 /// - a small register representing only part of a value.
220 static void emitDwarfOpPiece(ByteStreamer &Streamer, unsigned Size,
221                              unsigned Offset) {
222   assert(Size > 0);
223   if (Offset > 0) {
224     Streamer.EmitInt8(dwarf::DW_OP_bit_piece, "DW_OP_bit_piece");
225     Streamer.EmitULEB128(Size, Twine(Size));
226     Streamer.EmitULEB128(Offset, Twine(Offset));
227   } else {
228     Streamer.EmitInt8(dwarf::DW_OP_piece, "DW_OP_piece");
229     unsigned ByteSize = Size / 8; // Assuming 8 bits per byte.
230     Streamer.EmitULEB128(ByteSize, Twine(ByteSize));
231   }
232 }
233 
234 /// Some targets do not provide a DWARF register number for every
235 /// register.  This function attempts to emit a dwarf register by
236 /// emitting a piece of a super-register or by piecing together
237 /// multiple subregisters that alias the register.
238 static void EmitDwarfRegOpPiece(ByteStreamer &Streamer, const AsmPrinter &AP,
239                                 const MachineLocation &MLoc) {
240   assert(!MLoc.isIndirect());
241   const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
242   int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
243 
244   // Walk up the super-register chain until we find a valid number.
245   // For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
246   for (MCSuperRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
247     Reg = TRI->getDwarfRegNum(*SR, false);
248     if (Reg >= 0) {
249       unsigned Idx = TRI->getSubRegIndex(*SR, MLoc.getReg());
250       unsigned Size = TRI->getSubRegIdxSize(Idx);
251       unsigned Offset = TRI->getSubRegIdxOffset(Idx);
252       AP.OutStreamer.AddComment("super-register");
253       emitDwarfRegOp(Streamer, Reg);
254       emitDwarfOpPiece(Streamer, Size, Offset);
255       return;
256     }
257   }
258 
259   // Otherwise, attempt to find a covering set of sub-register numbers.
260   // For example, Q0 on ARM is a composition of D0+D1.
261   //
262   // Keep track of the current position so we can emit the more
263   // efficient DW_OP_piece.
264   unsigned CurPos = 0;
265   // The size of the register in bits, assuming 8 bits per byte.
266   unsigned RegSize = TRI->getMinimalPhysRegClass(MLoc.getReg())->getSize() * 8;
267   // Keep track of the bits in the register we already emitted, so we
268   // can avoid emitting redundant aliasing subregs.
269   SmallBitVector Coverage(RegSize, false);
270   for (MCSubRegIterator SR(MLoc.getReg(), TRI); SR.isValid(); ++SR) {
271     unsigned Idx = TRI->getSubRegIndex(MLoc.getReg(), *SR);
272     unsigned Size = TRI->getSubRegIdxSize(Idx);
273     unsigned Offset = TRI->getSubRegIdxOffset(Idx);
274     Reg = TRI->getDwarfRegNum(*SR, false);
275 
276     // Intersection between the bits we already emitted and the bits
277     // covered by this subregister.
278     SmallBitVector Intersection(RegSize, false);
279     Intersection.set(Offset, Offset + Size);
280     Intersection ^= Coverage;
281 
282     // If this sub-register has a DWARF number and we haven't covered
283     // its range, emit a DWARF piece for it.
284     if (Reg >= 0 && Intersection.any()) {
285       AP.OutStreamer.AddComment("sub-register");
286       emitDwarfRegOp(Streamer, Reg);
287       emitDwarfOpPiece(Streamer, Size, Offset == CurPos ? 0 : Offset);
288       CurPos = Offset + Size;
289 
290       // Mark it as emitted.
291       Coverage.set(Offset, Offset + Size);
292     }
293   }
294 
295   if (CurPos == 0) {
296     // FIXME: We have no reasonable way of handling errors in here.
297     Streamer.EmitInt8(dwarf::DW_OP_nop,
298                       "nop (could not find a dwarf register number)");
299   }
300 }
301 
302 /// EmitDwarfRegOp - Emit dwarf register operation.
303 void AsmPrinter::EmitDwarfRegOp(ByteStreamer &Streamer,
304                                 const MachineLocation &MLoc,
305                                 bool Indirect) const {
306   const TargetRegisterInfo *TRI = TM.getRegisterInfo();
307   int Reg = TRI->getDwarfRegNum(MLoc.getReg(), false);
308   if (Reg < 0) {
309     // We assume that pointers are always in an addressable register.
310     if (Indirect || MLoc.isIndirect()) {
311       // FIXME: We have no reasonable way of handling errors in here. The
312       // caller might be in the middle of a dwarf expression. We should
313       // probably assert that Reg >= 0 once debug info generation is more
314       // mature.
315       Streamer.EmitInt8(dwarf::DW_OP_nop,
316                         "nop (invalid dwarf register number for indirect loc)");
317       return;
318     }
319 
320     // Attempt to find a valid super- or sub-register.
321     if (!Indirect && !MLoc.isIndirect())
322       return EmitDwarfRegOpPiece(Streamer, *this, MLoc);
323   }
324 
325   if (MLoc.isIndirect())
326     emitDwarfRegOpIndirect(Streamer, Reg, MLoc.getOffset(), Indirect);
327   else if (Indirect)
328     emitDwarfRegOpIndirect(Streamer, Reg, 0, false);
329   else
330     emitDwarfRegOp(Streamer, Reg);
331 }
332 
333 //===----------------------------------------------------------------------===//
334 // Dwarf Lowering Routines
335 //===----------------------------------------------------------------------===//
336 
337 void AsmPrinter::emitCFIInstruction(const MCCFIInstruction &Inst) const {
338   switch (Inst.getOperation()) {
339   default:
340     llvm_unreachable("Unexpected instruction");
341   case MCCFIInstruction::OpDefCfaOffset:
342     OutStreamer.EmitCFIDefCfaOffset(Inst.getOffset());
343     break;
344   case MCCFIInstruction::OpDefCfa:
345     OutStreamer.EmitCFIDefCfa(Inst.getRegister(), Inst.getOffset());
346     break;
347   case MCCFIInstruction::OpDefCfaRegister:
348     OutStreamer.EmitCFIDefCfaRegister(Inst.getRegister());
349     break;
350   case MCCFIInstruction::OpOffset:
351     OutStreamer.EmitCFIOffset(Inst.getRegister(), Inst.getOffset());
352     break;
353   case MCCFIInstruction::OpRegister:
354     OutStreamer.EmitCFIRegister(Inst.getRegister(), Inst.getRegister2());
355     break;
356   case MCCFIInstruction::OpWindowSave:
357     OutStreamer.EmitCFIWindowSave();
358     break;
359   case MCCFIInstruction::OpSameValue:
360     OutStreamer.EmitCFISameValue(Inst.getRegister());
361     break;
362   }
363 }
364