10c67e01eSJakob Stoklund Olesen //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
20c67e01eSJakob Stoklund Olesen //
30c67e01eSJakob Stoklund Olesen //                     The LLVM Compiler Infrastructure
40c67e01eSJakob Stoklund Olesen //
50c67e01eSJakob Stoklund Olesen // This file is distributed under the University of Illinois Open Source
60c67e01eSJakob Stoklund Olesen // License. See LICENSE.TXT for details.
70c67e01eSJakob Stoklund Olesen //
80c67e01eSJakob Stoklund Olesen //===----------------------------------------------------------------------===//
90c67e01eSJakob Stoklund Olesen //
100c67e01eSJakob Stoklund Olesen // This file implements an allocation order for virtual registers.
110c67e01eSJakob Stoklund Olesen //
120c67e01eSJakob Stoklund Olesen // The preferred allocation order for a virtual register depends on allocation
130c67e01eSJakob Stoklund Olesen // hints and target hooks. The AllocationOrder class encapsulates all of that.
140c67e01eSJakob Stoklund Olesen //
150c67e01eSJakob Stoklund Olesen //===----------------------------------------------------------------------===//
160c67e01eSJakob Stoklund Olesen 
17c784a1f9SJakob Stoklund Olesen #define DEBUG_TYPE "regalloc"
180c67e01eSJakob Stoklund Olesen #include "AllocationOrder.h"
19c784a1f9SJakob Stoklund Olesen #include "llvm/CodeGen/MachineFunction.h"
200c67e01eSJakob Stoklund Olesen #include "llvm/CodeGen/MachineRegisterInfo.h"
2105ff4667SAndrew Trick #include "llvm/CodeGen/RegisterClassInfo.h"
2226c9d70dSJakob Stoklund Olesen #include "llvm/CodeGen/VirtRegMap.h"
23c784a1f9SJakob Stoklund Olesen #include "llvm/Support/Debug.h"
24c784a1f9SJakob Stoklund Olesen #include "llvm/Support/raw_ostream.h"
25802d7555SChandler Carruth #include "llvm/Target/TargetMachine.h"
260c67e01eSJakob Stoklund Olesen 
270c67e01eSJakob Stoklund Olesen using namespace llvm;
280c67e01eSJakob Stoklund Olesen 
290c67e01eSJakob Stoklund Olesen // Compare VirtRegMap::getRegAllocPref().
300c67e01eSJakob Stoklund Olesen AllocationOrder::AllocationOrder(unsigned VirtReg,
310c67e01eSJakob Stoklund Olesen                                  const VirtRegMap &VRM,
32b8bf3c0fSJakob Stoklund Olesen                                  const RegisterClassInfo &RegClassInfo)
33c784a1f9SJakob Stoklund Olesen   : Pos(0) {
34c784a1f9SJakob Stoklund Olesen   const MachineFunction &MF = VRM.getMachineFunction();
35c784a1f9SJakob Stoklund Olesen   const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
36c784a1f9SJakob Stoklund Olesen   Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
37c784a1f9SJakob Stoklund Olesen   TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
38*3cb2cb80SJakob Stoklund Olesen   rewind();
390c67e01eSJakob Stoklund Olesen 
40c784a1f9SJakob Stoklund Olesen   DEBUG({
41c784a1f9SJakob Stoklund Olesen     if (!Hints.empty()) {
42c784a1f9SJakob Stoklund Olesen       dbgs() << "hints:";
43c784a1f9SJakob Stoklund Olesen       for (unsigned I = 0, E = Hints.size(); I != E; ++I)
44c784a1f9SJakob Stoklund Olesen         dbgs() << ' ' << PrintReg(Hints[I], TRI);
45c784a1f9SJakob Stoklund Olesen       dbgs() << '\n';
46c784a1f9SJakob Stoklund Olesen     }
47c784a1f9SJakob Stoklund Olesen   });
480cde8eb9SJakob Stoklund Olesen }
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