10c67e01eSJakob Stoklund Olesen //===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===// 20c67e01eSJakob Stoklund Olesen // 3*2946cd70SChandler Carruth // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*2946cd70SChandler Carruth // See https://llvm.org/LICENSE.txt for license information. 5*2946cd70SChandler Carruth // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 60c67e01eSJakob Stoklund Olesen // 70c67e01eSJakob Stoklund Olesen //===----------------------------------------------------------------------===// 80c67e01eSJakob Stoklund Olesen // 90c67e01eSJakob Stoklund Olesen // This file implements an allocation order for virtual registers. 100c67e01eSJakob Stoklund Olesen // 110c67e01eSJakob Stoklund Olesen // The preferred allocation order for a virtual register depends on allocation 120c67e01eSJakob Stoklund Olesen // hints and target hooks. The AllocationOrder class encapsulates all of that. 130c67e01eSJakob Stoklund Olesen // 140c67e01eSJakob Stoklund Olesen //===----------------------------------------------------------------------===// 150c67e01eSJakob Stoklund Olesen 160c67e01eSJakob Stoklund Olesen #include "AllocationOrder.h" 17c784a1f9SJakob Stoklund Olesen #include "llvm/CodeGen/MachineFunction.h" 180c67e01eSJakob Stoklund Olesen #include "llvm/CodeGen/MachineRegisterInfo.h" 1905ff4667SAndrew Trick #include "llvm/CodeGen/RegisterClassInfo.h" 2026c9d70dSJakob Stoklund Olesen #include "llvm/CodeGen/VirtRegMap.h" 21c784a1f9SJakob Stoklund Olesen #include "llvm/Support/Debug.h" 22c784a1f9SJakob Stoklund Olesen #include "llvm/Support/raw_ostream.h" 230c67e01eSJakob Stoklund Olesen 240c67e01eSJakob Stoklund Olesen using namespace llvm; 250c67e01eSJakob Stoklund Olesen 261b9dde08SChandler Carruth #define DEBUG_TYPE "regalloc" 271b9dde08SChandler Carruth 280c67e01eSJakob Stoklund Olesen // Compare VirtRegMap::getRegAllocPref(). 290c67e01eSJakob Stoklund Olesen AllocationOrder::AllocationOrder(unsigned VirtReg, 300c67e01eSJakob Stoklund Olesen const VirtRegMap &VRM, 315d1f12d1SMatthias Braun const RegisterClassInfo &RegClassInfo, 325d1f12d1SMatthias Braun const LiveRegMatrix *Matrix) 334b017e68SJonas Paulsson : Pos(0), HardHints(false) { 34c784a1f9SJakob Stoklund Olesen const MachineFunction &MF = VRM.getMachineFunction(); 35c784a1f9SJakob Stoklund Olesen const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); 36c784a1f9SJakob Stoklund Olesen Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); 374b017e68SJonas Paulsson if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix)) 384b017e68SJonas Paulsson HardHints = true; 393cb2cb80SJakob Stoklund Olesen rewind(); 400c67e01eSJakob Stoklund Olesen 41d34e60caSNicola Zaghen LLVM_DEBUG({ 42c784a1f9SJakob Stoklund Olesen if (!Hints.empty()) { 43c784a1f9SJakob Stoklund Olesen dbgs() << "hints:"; 44c784a1f9SJakob Stoklund Olesen for (unsigned I = 0, E = Hints.size(); I != E; ++I) 459d419d3bSFrancis Visoiu Mistrih dbgs() << ' ' << printReg(Hints[I], TRI); 46c784a1f9SJakob Stoklund Olesen dbgs() << '\n'; 47c784a1f9SJakob Stoklund Olesen } 48c784a1f9SJakob Stoklund Olesen }); 497e28db01SJakob Stoklund Olesen #ifndef NDEBUG 507e28db01SJakob Stoklund Olesen for (unsigned I = 0, E = Hints.size(); I != E; ++I) 510d955d0bSDavid Majnemer assert(is_contained(Order, Hints[I]) && 527e28db01SJakob Stoklund Olesen "Target hint is outside allocation order."); 537e28db01SJakob Stoklund Olesen #endif 540cde8eb9SJakob Stoklund Olesen } 55