1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/Analysis/TargetTransformInfo.h"
10 #include "llvm/Analysis/CFG.h"
11 #include "llvm/Analysis/LoopIterator.h"
12 #include "llvm/Analysis/TargetTransformInfoImpl.h"
13 #include "llvm/IR/CFG.h"
14 #include "llvm/IR/CallSite.h"
15 #include "llvm/IR/DataLayout.h"
16 #include "llvm/IR/Instruction.h"
17 #include "llvm/IR/Instructions.h"
18 #include "llvm/IR/IntrinsicInst.h"
19 #include "llvm/IR/Module.h"
20 #include "llvm/IR/Operator.h"
21 #include "llvm/IR/PatternMatch.h"
22 #include "llvm/InitializePasses.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include <utility>
26 
27 using namespace llvm;
28 using namespace PatternMatch;
29 
30 #define DEBUG_TYPE "tti"
31 
32 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
33                                      cl::Hidden,
34                                      cl::desc("Recognize reduction patterns."));
35 
36 namespace {
37 /// No-op implementation of the TTI interface using the utility base
38 /// classes.
39 ///
40 /// This is used when no target specific information is available.
41 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
42   explicit NoTTIImpl(const DataLayout &DL)
43       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
44 };
45 }
46 
47 bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) {
48   // If the loop has irreducible control flow, it can not be converted to
49   // Hardware loop.
50   LoopBlocksRPO RPOT(L);
51   RPOT.perform(&LI);
52   if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
53     return false;
54   return true;
55 }
56 
57 bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
58                                                LoopInfo &LI, DominatorTree &DT,
59                                                bool ForceNestedLoop,
60                                                bool ForceHardwareLoopPHI) {
61   SmallVector<BasicBlock *, 4> ExitingBlocks;
62   L->getExitingBlocks(ExitingBlocks);
63 
64   for (BasicBlock *BB : ExitingBlocks) {
65     // If we pass the updated counter back through a phi, we need to know
66     // which latch the updated value will be coming from.
67     if (!L->isLoopLatch(BB)) {
68       if (ForceHardwareLoopPHI || CounterInReg)
69         continue;
70     }
71 
72     const SCEV *EC = SE.getExitCount(L, BB);
73     if (isa<SCEVCouldNotCompute>(EC))
74       continue;
75     if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
76       if (ConstEC->getValue()->isZero())
77         continue;
78     } else if (!SE.isLoopInvariant(EC, L))
79       continue;
80 
81     if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
82       continue;
83 
84     // If this exiting block is contained in a nested loop, it is not eligible
85     // for insertion of the branch-and-decrement since the inner loop would
86     // end up messing up the value in the CTR.
87     if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
88       continue;
89 
90     // We now have a loop-invariant count of loop iterations (which is not the
91     // constant zero) for which we know that this loop will not exit via this
92     // existing block.
93 
94     // We need to make sure that this block will run on every loop iteration.
95     // For this to be true, we must dominate all blocks with backedges. Such
96     // blocks are in-loop predecessors to the header block.
97     bool NotAlways = false;
98     for (BasicBlock *Pred : predecessors(L->getHeader())) {
99       if (!L->contains(Pred))
100         continue;
101 
102       if (!DT.dominates(BB, Pred)) {
103         NotAlways = true;
104         break;
105       }
106     }
107 
108     if (NotAlways)
109       continue;
110 
111     // Make sure this blocks ends with a conditional branch.
112     Instruction *TI = BB->getTerminator();
113     if (!TI)
114       continue;
115 
116     if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
117       if (!BI->isConditional())
118         continue;
119 
120       ExitBranch = BI;
121     } else
122       continue;
123 
124     // Note that this block may not be the loop latch block, even if the loop
125     // has a latch block.
126     ExitBlock = BB;
127     ExitCount = EC;
128     break;
129   }
130 
131   if (!ExitBlock)
132     return false;
133   return true;
134 }
135 
136 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
137     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
138 
139 TargetTransformInfo::~TargetTransformInfo() {}
140 
141 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
142     : TTIImpl(std::move(Arg.TTIImpl)) {}
143 
144 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
145   TTIImpl = std::move(RHS.TTIImpl);
146   return *this;
147 }
148 
149 int TargetTransformInfo::getOperationCost(unsigned Opcode, Type *Ty,
150                                           Type *OpTy) const {
151   int Cost = TTIImpl->getOperationCost(Opcode, Ty, OpTy);
152   assert(Cost >= 0 && "TTI should not produce negative costs!");
153   return Cost;
154 }
155 
156 int TargetTransformInfo::getCallCost(FunctionType *FTy, int NumArgs,
157                                      const User *U) const {
158   int Cost = TTIImpl->getCallCost(FTy, NumArgs, U);
159   assert(Cost >= 0 && "TTI should not produce negative costs!");
160   return Cost;
161 }
162 
163 int TargetTransformInfo::getCallCost(const Function *F,
164                                      ArrayRef<const Value *> Arguments,
165                                      const User *U) const {
166   int Cost = TTIImpl->getCallCost(F, Arguments, U);
167   assert(Cost >= 0 && "TTI should not produce negative costs!");
168   return Cost;
169 }
170 
171 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
172   return TTIImpl->getInliningThresholdMultiplier();
173 }
174 
175 int TargetTransformInfo::getInlinerVectorBonusPercent() const {
176   return TTIImpl->getInlinerVectorBonusPercent();
177 }
178 
179 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
180                                     ArrayRef<const Value *> Operands) const {
181   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands);
182 }
183 
184 int TargetTransformInfo::getExtCost(const Instruction *I,
185                                     const Value *Src) const {
186   return TTIImpl->getExtCost(I, Src);
187 }
188 
189 int TargetTransformInfo::getIntrinsicCost(
190     Intrinsic::ID IID, Type *RetTy, ArrayRef<const Value *> Arguments,
191     const User *U) const {
192   int Cost = TTIImpl->getIntrinsicCost(IID, RetTy, Arguments, U);
193   assert(Cost >= 0 && "TTI should not produce negative costs!");
194   return Cost;
195 }
196 
197 unsigned
198 TargetTransformInfo::getEstimatedNumberOfCaseClusters(
199     const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
200     BlockFrequencyInfo *BFI) const {
201   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
202 }
203 
204 int TargetTransformInfo::getUserCost(const User *U,
205     ArrayRef<const Value *> Operands) const {
206   int Cost = TTIImpl->getUserCost(U, Operands);
207   assert(Cost >= 0 && "TTI should not produce negative costs!");
208   return Cost;
209 }
210 
211 bool TargetTransformInfo::hasBranchDivergence() const {
212   return TTIImpl->hasBranchDivergence();
213 }
214 
215 bool TargetTransformInfo::useGPUDivergenceAnalysis() const {
216   return TTIImpl->useGPUDivergenceAnalysis();
217 }
218 
219 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
220   return TTIImpl->isSourceOfDivergence(V);
221 }
222 
223 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
224   return TTIImpl->isAlwaysUniform(V);
225 }
226 
227 unsigned TargetTransformInfo::getFlatAddressSpace() const {
228   return TTIImpl->getFlatAddressSpace();
229 }
230 
231 bool TargetTransformInfo::collectFlatAddressOperands(
232   SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const  {
233   return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
234 }
235 
236 bool TargetTransformInfo::rewriteIntrinsicWithAddressSpace(
237   IntrinsicInst *II, Value *OldV, Value *NewV) const {
238   return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
239 }
240 
241 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
242   return TTIImpl->isLoweredToCall(F);
243 }
244 
245 bool TargetTransformInfo::isHardwareLoopProfitable(
246   Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
247   TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
248   return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
249 }
250 
251 bool TargetTransformInfo::preferPredicateOverEpilogue(Loop *L, LoopInfo *LI,
252     ScalarEvolution &SE, AssumptionCache &AC, TargetLibraryInfo *TLI,
253     DominatorTree *DT, const LoopAccessInfo *LAI) const {
254   return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LAI);
255 }
256 
257 void TargetTransformInfo::getUnrollingPreferences(
258     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
259   return TTIImpl->getUnrollingPreferences(L, SE, UP);
260 }
261 
262 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
263   return TTIImpl->isLegalAddImmediate(Imm);
264 }
265 
266 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
267   return TTIImpl->isLegalICmpImmediate(Imm);
268 }
269 
270 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
271                                                 int64_t BaseOffset,
272                                                 bool HasBaseReg,
273                                                 int64_t Scale,
274                                                 unsigned AddrSpace,
275                                                 Instruction *I) const {
276   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
277                                         Scale, AddrSpace, I);
278 }
279 
280 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
281   return TTIImpl->isLSRCostLess(C1, C2);
282 }
283 
284 bool TargetTransformInfo::canMacroFuseCmp() const {
285   return TTIImpl->canMacroFuseCmp();
286 }
287 
288 bool TargetTransformInfo::canSaveCmp(Loop *L, BranchInst **BI,
289                                      ScalarEvolution *SE, LoopInfo *LI,
290                                      DominatorTree *DT, AssumptionCache *AC,
291                                      TargetLibraryInfo *LibInfo) const {
292   return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
293 }
294 
295 bool TargetTransformInfo::shouldFavorPostInc() const {
296   return TTIImpl->shouldFavorPostInc();
297 }
298 
299 bool TargetTransformInfo::shouldFavorBackedgeIndex(const Loop *L) const {
300   return TTIImpl->shouldFavorBackedgeIndex(L);
301 }
302 
303 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType,
304                                              MaybeAlign Alignment) const {
305   return TTIImpl->isLegalMaskedStore(DataType, Alignment);
306 }
307 
308 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType,
309                                             MaybeAlign Alignment) const {
310   return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
311 }
312 
313 bool TargetTransformInfo::isLegalNTStore(Type *DataType,
314                                          Align Alignment) const {
315   return TTIImpl->isLegalNTStore(DataType, Alignment);
316 }
317 
318 bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
319   return TTIImpl->isLegalNTLoad(DataType, Alignment);
320 }
321 
322 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType,
323                                               MaybeAlign Alignment) const {
324   return TTIImpl->isLegalMaskedGather(DataType, Alignment);
325 }
326 
327 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType,
328                                                MaybeAlign Alignment) const {
329   return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
330 }
331 
332 bool TargetTransformInfo::isLegalMaskedCompressStore(Type *DataType) const {
333   return TTIImpl->isLegalMaskedCompressStore(DataType);
334 }
335 
336 bool TargetTransformInfo::isLegalMaskedExpandLoad(Type *DataType) const {
337   return TTIImpl->isLegalMaskedExpandLoad(DataType);
338 }
339 
340 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
341   return TTIImpl->hasDivRemOp(DataType, IsSigned);
342 }
343 
344 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
345                                              unsigned AddrSpace) const {
346   return TTIImpl->hasVolatileVariant(I, AddrSpace);
347 }
348 
349 bool TargetTransformInfo::prefersVectorizedAddressing() const {
350   return TTIImpl->prefersVectorizedAddressing();
351 }
352 
353 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
354                                               int64_t BaseOffset,
355                                               bool HasBaseReg,
356                                               int64_t Scale,
357                                               unsigned AddrSpace) const {
358   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
359                                            Scale, AddrSpace);
360   assert(Cost >= 0 && "TTI should not produce negative costs!");
361   return Cost;
362 }
363 
364 bool TargetTransformInfo::LSRWithInstrQueries() const {
365   return TTIImpl->LSRWithInstrQueries();
366 }
367 
368 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
369   return TTIImpl->isTruncateFree(Ty1, Ty2);
370 }
371 
372 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
373   return TTIImpl->isProfitableToHoist(I);
374 }
375 
376 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
377 
378 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
379   return TTIImpl->isTypeLegal(Ty);
380 }
381 
382 bool TargetTransformInfo::shouldBuildLookupTables() const {
383   return TTIImpl->shouldBuildLookupTables();
384 }
385 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(Constant *C) const {
386   return TTIImpl->shouldBuildLookupTablesForConstant(C);
387 }
388 
389 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
390   return TTIImpl->useColdCCForColdCall(F);
391 }
392 
393 unsigned TargetTransformInfo::
394 getScalarizationOverhead(Type *Ty, bool Insert, bool Extract) const {
395   return TTIImpl->getScalarizationOverhead(Ty, Insert, Extract);
396 }
397 
398 unsigned TargetTransformInfo::
399 getOperandsScalarizationOverhead(ArrayRef<const Value *> Args,
400                                  unsigned VF) const {
401   return TTIImpl->getOperandsScalarizationOverhead(Args, VF);
402 }
403 
404 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
405   return TTIImpl->supportsEfficientVectorElementLoadStore();
406 }
407 
408 bool TargetTransformInfo::enableAggressiveInterleaving(bool LoopHasReductions) const {
409   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
410 }
411 
412 TargetTransformInfo::MemCmpExpansionOptions
413 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
414   return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
415 }
416 
417 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
418   return TTIImpl->enableInterleavedAccessVectorization();
419 }
420 
421 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const {
422   return TTIImpl->enableMaskedInterleavedAccessVectorization();
423 }
424 
425 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
426   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
427 }
428 
429 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
430                                                          unsigned BitWidth,
431                                                          unsigned AddressSpace,
432                                                          unsigned Alignment,
433                                                          bool *Fast) const {
434   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth, AddressSpace,
435                                                  Alignment, Fast);
436 }
437 
438 TargetTransformInfo::PopcntSupportKind
439 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
440   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
441 }
442 
443 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
444   return TTIImpl->haveFastSqrt(Ty);
445 }
446 
447 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
448   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
449 }
450 
451 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
452   int Cost = TTIImpl->getFPOpCost(Ty);
453   assert(Cost >= 0 && "TTI should not produce negative costs!");
454   return Cost;
455 }
456 
457 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
458                                                const APInt &Imm,
459                                                Type *Ty) const {
460   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
461   assert(Cost >= 0 && "TTI should not produce negative costs!");
462   return Cost;
463 }
464 
465 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty) const {
466   int Cost = TTIImpl->getIntImmCost(Imm, Ty);
467   assert(Cost >= 0 && "TTI should not produce negative costs!");
468   return Cost;
469 }
470 
471 int TargetTransformInfo::getIntImmCostInst(unsigned Opcode, unsigned Idx,
472                                            const APInt &Imm, Type *Ty) const {
473   int Cost = TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty);
474   assert(Cost >= 0 && "TTI should not produce negative costs!");
475   return Cost;
476 }
477 
478 int TargetTransformInfo::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
479                                              const APInt &Imm, Type *Ty) const {
480   int Cost = TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty);
481   assert(Cost >= 0 && "TTI should not produce negative costs!");
482   return Cost;
483 }
484 
485 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
486   return TTIImpl->getNumberOfRegisters(ClassID);
487 }
488 
489 unsigned TargetTransformInfo::getRegisterClassForType(bool Vector, Type *Ty) const {
490   return TTIImpl->getRegisterClassForType(Vector, Ty);
491 }
492 
493 const char* TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
494   return TTIImpl->getRegisterClassName(ClassID);
495 }
496 
497 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
498   return TTIImpl->getRegisterBitWidth(Vector);
499 }
500 
501 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
502   return TTIImpl->getMinVectorRegisterBitWidth();
503 }
504 
505 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
506   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
507 }
508 
509 unsigned TargetTransformInfo::getMinimumVF(unsigned ElemWidth) const {
510   return TTIImpl->getMinimumVF(ElemWidth);
511 }
512 
513 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
514     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
515   return TTIImpl->shouldConsiderAddressTypePromotion(
516       I, AllowPromotionWithoutCommonHeader);
517 }
518 
519 unsigned TargetTransformInfo::getCacheLineSize() const {
520   return TTIImpl->getCacheLineSize();
521 }
522 
523 llvm::Optional<unsigned> TargetTransformInfo::getCacheSize(CacheLevel Level)
524   const {
525   return TTIImpl->getCacheSize(Level);
526 }
527 
528 llvm::Optional<unsigned> TargetTransformInfo::getCacheAssociativity(
529   CacheLevel Level) const {
530   return TTIImpl->getCacheAssociativity(Level);
531 }
532 
533 unsigned TargetTransformInfo::getPrefetchDistance() const {
534   return TTIImpl->getPrefetchDistance();
535 }
536 
537 unsigned TargetTransformInfo::getMinPrefetchStride() const {
538   return TTIImpl->getMinPrefetchStride();
539 }
540 
541 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
542   return TTIImpl->getMaxPrefetchIterationsAhead();
543 }
544 
545 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
546   return TTIImpl->getMaxInterleaveFactor(VF);
547 }
548 
549 TargetTransformInfo::OperandValueKind
550 TargetTransformInfo::getOperandInfo(Value *V, OperandValueProperties &OpProps) {
551   OperandValueKind OpInfo = OK_AnyValue;
552   OpProps = OP_None;
553 
554   if (auto *CI = dyn_cast<ConstantInt>(V)) {
555     if (CI->getValue().isPowerOf2())
556       OpProps = OP_PowerOf2;
557     return OK_UniformConstantValue;
558   }
559 
560   // A broadcast shuffle creates a uniform value.
561   // TODO: Add support for non-zero index broadcasts.
562   // TODO: Add support for different source vector width.
563   if (auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
564     if (ShuffleInst->isZeroEltSplat())
565       OpInfo = OK_UniformValue;
566 
567   const Value *Splat = getSplatValue(V);
568 
569   // Check for a splat of a constant or for a non uniform vector of constants
570   // and check if the constant(s) are all powers of two.
571   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
572     OpInfo = OK_NonUniformConstantValue;
573     if (Splat) {
574       OpInfo = OK_UniformConstantValue;
575       if (auto *CI = dyn_cast<ConstantInt>(Splat))
576         if (CI->getValue().isPowerOf2())
577           OpProps = OP_PowerOf2;
578     } else if (auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
579       OpProps = OP_PowerOf2;
580       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
581         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
582           if (CI->getValue().isPowerOf2())
583             continue;
584         OpProps = OP_None;
585         break;
586       }
587     }
588   }
589 
590   // Check for a splat of a uniform value. This is not loop aware, so return
591   // true only for the obviously uniform cases (argument, globalvalue)
592   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
593     OpInfo = OK_UniformValue;
594 
595   return OpInfo;
596 }
597 
598 int TargetTransformInfo::getArithmeticInstrCost(
599     unsigned Opcode, Type *Ty, OperandValueKind Opd1Info,
600     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
601     OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
602     const Instruction *CxtI) const {
603   int Cost = TTIImpl->getArithmeticInstrCost(
604       Opcode, Ty, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo, Args, CxtI);
605   assert(Cost >= 0 && "TTI should not produce negative costs!");
606   return Cost;
607 }
608 
609 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, Type *Ty, int Index,
610                                         Type *SubTp) const {
611   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Index, SubTp);
612   assert(Cost >= 0 && "TTI should not produce negative costs!");
613   return Cost;
614 }
615 
616 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst,
617                                  Type *Src, const Instruction *I) const {
618   assert ((I == nullptr || I->getOpcode() == Opcode) &&
619           "Opcode should reflect passed instruction.");
620   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, I);
621   assert(Cost >= 0 && "TTI should not produce negative costs!");
622   return Cost;
623 }
624 
625 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
626                                                   VectorType *VecTy,
627                                                   unsigned Index) const {
628   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
629   assert(Cost >= 0 && "TTI should not produce negative costs!");
630   return Cost;
631 }
632 
633 int TargetTransformInfo::getCFInstrCost(unsigned Opcode) const {
634   int Cost = TTIImpl->getCFInstrCost(Opcode);
635   assert(Cost >= 0 && "TTI should not produce negative costs!");
636   return Cost;
637 }
638 
639 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
640                                  Type *CondTy, const Instruction *I) const {
641   assert ((I == nullptr || I->getOpcode() == Opcode) &&
642           "Opcode should reflect passed instruction.");
643   int Cost = TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, I);
644   assert(Cost >= 0 && "TTI should not produce negative costs!");
645   return Cost;
646 }
647 
648 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
649                                             unsigned Index) const {
650   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
651   assert(Cost >= 0 && "TTI should not produce negative costs!");
652   return Cost;
653 }
654 
655 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
656                                          MaybeAlign Alignment,
657                                          unsigned AddressSpace,
658                                          const Instruction *I) const {
659   assert ((I == nullptr || I->getOpcode() == Opcode) &&
660           "Opcode should reflect passed instruction.");
661   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace, I);
662   assert(Cost >= 0 && "TTI should not produce negative costs!");
663   return Cost;
664 }
665 
666 int TargetTransformInfo::getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
667                                                unsigned Alignment,
668                                                unsigned AddressSpace) const {
669   int Cost =
670       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace);
671   assert(Cost >= 0 && "TTI should not produce negative costs!");
672   return Cost;
673 }
674 
675 int TargetTransformInfo::getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
676                                                 Value *Ptr, bool VariableMask,
677                                                 unsigned Alignment) const {
678   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
679                                              Alignment);
680   assert(Cost >= 0 && "TTI should not produce negative costs!");
681   return Cost;
682 }
683 
684 int TargetTransformInfo::getInterleavedMemoryOpCost(
685     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
686     unsigned Alignment, unsigned AddressSpace, bool UseMaskForCond,
687     bool UseMaskForGaps) const {
688   int Cost = TTIImpl->getInterleavedMemoryOpCost(Opcode, VecTy, Factor, Indices,
689                                                  Alignment, AddressSpace,
690                                                  UseMaskForCond,
691                                                  UseMaskForGaps);
692   assert(Cost >= 0 && "TTI should not produce negative costs!");
693   return Cost;
694 }
695 
696 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
697                                     ArrayRef<Type *> Tys, FastMathFlags FMF,
698                                     unsigned ScalarizationCostPassed) const {
699   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Tys, FMF,
700                                             ScalarizationCostPassed);
701   assert(Cost >= 0 && "TTI should not produce negative costs!");
702   return Cost;
703 }
704 
705 int TargetTransformInfo::getIntrinsicInstrCost(Intrinsic::ID ID, Type *RetTy,
706            ArrayRef<Value *> Args, FastMathFlags FMF, unsigned VF) const {
707   int Cost = TTIImpl->getIntrinsicInstrCost(ID, RetTy, Args, FMF, VF);
708   assert(Cost >= 0 && "TTI should not produce negative costs!");
709   return Cost;
710 }
711 
712 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
713                                           ArrayRef<Type *> Tys) const {
714   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys);
715   assert(Cost >= 0 && "TTI should not produce negative costs!");
716   return Cost;
717 }
718 
719 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
720   return TTIImpl->getNumberOfParts(Tp);
721 }
722 
723 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
724                                                    ScalarEvolution *SE,
725                                                    const SCEV *Ptr) const {
726   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
727   assert(Cost >= 0 && "TTI should not produce negative costs!");
728   return Cost;
729 }
730 
731 int TargetTransformInfo::getMemcpyCost(const Instruction *I) const {
732   int Cost = TTIImpl->getMemcpyCost(I);
733   assert(Cost >= 0 && "TTI should not produce negative costs!");
734   return Cost;
735 }
736 
737 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode, Type *Ty,
738                                                     bool IsPairwiseForm) const {
739   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm);
740   assert(Cost >= 0 && "TTI should not produce negative costs!");
741   return Cost;
742 }
743 
744 int TargetTransformInfo::getMinMaxReductionCost(Type *Ty, Type *CondTy,
745                                                 bool IsPairwiseForm,
746                                                 bool IsUnsigned) const {
747   int Cost =
748       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned);
749   assert(Cost >= 0 && "TTI should not produce negative costs!");
750   return Cost;
751 }
752 
753 unsigned
754 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
755   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
756 }
757 
758 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
759                                              MemIntrinsicInfo &Info) const {
760   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
761 }
762 
763 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
764   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
765 }
766 
767 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
768     IntrinsicInst *Inst, Type *ExpectedType) const {
769   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
770 }
771 
772 Type *TargetTransformInfo::getMemcpyLoopLoweringType(LLVMContext &Context,
773                                                      Value *Length,
774                                                      unsigned SrcAlign,
775                                                      unsigned DestAlign) const {
776   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAlign,
777                                             DestAlign);
778 }
779 
780 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
781     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
782     unsigned RemainingBytes, unsigned SrcAlign, unsigned DestAlign) const {
783   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
784                                              SrcAlign, DestAlign);
785 }
786 
787 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
788                                               const Function *Callee) const {
789   return TTIImpl->areInlineCompatible(Caller, Callee);
790 }
791 
792 bool TargetTransformInfo::areFunctionArgsABICompatible(
793     const Function *Caller, const Function *Callee,
794     SmallPtrSetImpl<Argument *> &Args) const {
795   return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
796 }
797 
798 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
799                                              Type *Ty) const {
800   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
801 }
802 
803 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
804                                               Type *Ty) const {
805   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
806 }
807 
808 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
809   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
810 }
811 
812 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
813   return TTIImpl->isLegalToVectorizeLoad(LI);
814 }
815 
816 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
817   return TTIImpl->isLegalToVectorizeStore(SI);
818 }
819 
820 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
821     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
822   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
823                                               AddrSpace);
824 }
825 
826 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
827     unsigned ChainSizeInBytes, unsigned Alignment, unsigned AddrSpace) const {
828   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
829                                                AddrSpace);
830 }
831 
832 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
833                                                   unsigned LoadSize,
834                                                   unsigned ChainSizeInBytes,
835                                                   VectorType *VecTy) const {
836   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
837 }
838 
839 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
840                                                    unsigned StoreSize,
841                                                    unsigned ChainSizeInBytes,
842                                                    VectorType *VecTy) const {
843   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
844 }
845 
846 bool TargetTransformInfo::useReductionIntrinsic(unsigned Opcode,
847                                                 Type *Ty, ReductionFlags Flags) const {
848   return TTIImpl->useReductionIntrinsic(Opcode, Ty, Flags);
849 }
850 
851 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
852   return TTIImpl->shouldExpandReduction(II);
853 }
854 
855 unsigned TargetTransformInfo::getGISelRematGlobalCost() const {
856   return TTIImpl->getGISelRematGlobalCost();
857 }
858 
859 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
860   return TTIImpl->getInstructionLatency(I);
861 }
862 
863 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
864                                      unsigned Level) {
865   // We don't need a shuffle if we just want to have element 0 in position 0 of
866   // the vector.
867   if (!SI && Level == 0 && IsLeft)
868     return true;
869   else if (!SI)
870     return false;
871 
872   SmallVector<int, 32> Mask(SI->getType()->getVectorNumElements(), -1);
873 
874   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
875   // we look at the left or right side.
876   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
877     Mask[i] = val;
878 
879   SmallVector<int, 16> ActualMask = SI->getShuffleMask();
880   return Mask == ActualMask;
881 }
882 
883 namespace {
884 /// Kind of the reduction data.
885 enum ReductionKind {
886   RK_None,           /// Not a reduction.
887   RK_Arithmetic,     /// Binary reduction data.
888   RK_MinMax,         /// Min/max reduction data.
889   RK_UnsignedMinMax, /// Unsigned min/max reduction data.
890 };
891 /// Contains opcode + LHS/RHS parts of the reduction operations.
892 struct ReductionData {
893   ReductionData() = delete;
894   ReductionData(ReductionKind Kind, unsigned Opcode, Value *LHS, Value *RHS)
895       : Opcode(Opcode), LHS(LHS), RHS(RHS), Kind(Kind) {
896     assert(Kind != RK_None && "expected binary or min/max reduction only.");
897   }
898   unsigned Opcode = 0;
899   Value *LHS = nullptr;
900   Value *RHS = nullptr;
901   ReductionKind Kind = RK_None;
902   bool hasSameData(ReductionData &RD) const {
903     return Kind == RD.Kind && Opcode == RD.Opcode;
904   }
905 };
906 } // namespace
907 
908 static Optional<ReductionData> getReductionData(Instruction *I) {
909   Value *L, *R;
910   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
911     return ReductionData(RK_Arithmetic, I->getOpcode(), L, R);
912   if (auto *SI = dyn_cast<SelectInst>(I)) {
913     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
914         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
915         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
916         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
917         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
918         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
919       auto *CI = cast<CmpInst>(SI->getCondition());
920       return ReductionData(RK_MinMax, CI->getOpcode(), L, R);
921     }
922     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
923         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
924       auto *CI = cast<CmpInst>(SI->getCondition());
925       return ReductionData(RK_UnsignedMinMax, CI->getOpcode(), L, R);
926     }
927   }
928   return llvm::None;
929 }
930 
931 static ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
932                                                    unsigned Level,
933                                                    unsigned NumLevels) {
934   // Match one level of pairwise operations.
935   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
936   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
937   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
938   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
939   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
940   if (!I)
941     return RK_None;
942 
943   assert(I->getType()->isVectorTy() && "Expecting a vector type");
944 
945   Optional<ReductionData> RD = getReductionData(I);
946   if (!RD)
947     return RK_None;
948 
949   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
950   if (!LS && Level)
951     return RK_None;
952   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
953   if (!RS && Level)
954     return RK_None;
955 
956   // On level 0 we can omit one shufflevector instruction.
957   if (!Level && !RS && !LS)
958     return RK_None;
959 
960   // Shuffle inputs must match.
961   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
962   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
963   Value *NextLevelOp = nullptr;
964   if (NextLevelOpR && NextLevelOpL) {
965     // If we have two shuffles their operands must match.
966     if (NextLevelOpL != NextLevelOpR)
967       return RK_None;
968 
969     NextLevelOp = NextLevelOpL;
970   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
971     // On the first level we can omit the shufflevector <0, undef,...>. So the
972     // input to the other shufflevector <1, undef> must match with one of the
973     // inputs to the current binary operation.
974     // Example:
975     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
976     //  %BinOp        = fadd          %NextLevelOpL, %R
977     if (NextLevelOpL && NextLevelOpL != RD->RHS)
978       return RK_None;
979     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
980       return RK_None;
981 
982     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
983   } else
984     return RK_None;
985 
986   // Check that the next levels binary operation exists and matches with the
987   // current one.
988   if (Level + 1 != NumLevels) {
989     Optional<ReductionData> NextLevelRD =
990         getReductionData(cast<Instruction>(NextLevelOp));
991     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
992       return RK_None;
993   }
994 
995   // Shuffle mask for pairwise operation must match.
996   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
997     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
998       return RK_None;
999   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
1000     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
1001       return RK_None;
1002   } else {
1003     return RK_None;
1004   }
1005 
1006   if (++Level == NumLevels)
1007     return RD->Kind;
1008 
1009   // Match next level.
1010   return matchPairwiseReductionAtLevel(cast<Instruction>(NextLevelOp), Level,
1011                                        NumLevels);
1012 }
1013 
1014 static ReductionKind matchPairwiseReduction(const ExtractElementInst *ReduxRoot,
1015                                             unsigned &Opcode, Type *&Ty) {
1016   if (!EnableReduxCost)
1017     return RK_None;
1018 
1019   // Need to extract the first element.
1020   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1021   unsigned Idx = ~0u;
1022   if (CI)
1023     Idx = CI->getZExtValue();
1024   if (Idx != 0)
1025     return RK_None;
1026 
1027   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1028   if (!RdxStart)
1029     return RK_None;
1030   Optional<ReductionData> RD = getReductionData(RdxStart);
1031   if (!RD)
1032     return RK_None;
1033 
1034   Type *VecTy = RdxStart->getType();
1035   unsigned NumVecElems = VecTy->getVectorNumElements();
1036   if (!isPowerOf2_32(NumVecElems))
1037     return RK_None;
1038 
1039   // We look for a sequence of shuffle,shuffle,add triples like the following
1040   // that builds a pairwise reduction tree.
1041   //
1042   //  (X0, X1, X2, X3)
1043   //   (X0 + X1, X2 + X3, undef, undef)
1044   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
1045   //
1046   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
1047   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
1048   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
1049   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
1050   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
1051   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1052   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
1053   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1054   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1055   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
1056   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1057   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
1058       RK_None)
1059     return RK_None;
1060 
1061   Opcode = RD->Opcode;
1062   Ty = VecTy;
1063 
1064   return RD->Kind;
1065 }
1066 
1067 static std::pair<Value *, ShuffleVectorInst *>
1068 getShuffleAndOtherOprd(Value *L, Value *R) {
1069   ShuffleVectorInst *S = nullptr;
1070 
1071   if ((S = dyn_cast<ShuffleVectorInst>(L)))
1072     return std::make_pair(R, S);
1073 
1074   S = dyn_cast<ShuffleVectorInst>(R);
1075   return std::make_pair(L, S);
1076 }
1077 
1078 static ReductionKind
1079 matchVectorSplittingReduction(const ExtractElementInst *ReduxRoot,
1080                               unsigned &Opcode, Type *&Ty) {
1081   if (!EnableReduxCost)
1082     return RK_None;
1083 
1084   // Need to extract the first element.
1085   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1086   unsigned Idx = ~0u;
1087   if (CI)
1088     Idx = CI->getZExtValue();
1089   if (Idx != 0)
1090     return RK_None;
1091 
1092   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1093   if (!RdxStart)
1094     return RK_None;
1095   Optional<ReductionData> RD = getReductionData(RdxStart);
1096   if (!RD)
1097     return RK_None;
1098 
1099   Type *VecTy = ReduxRoot->getOperand(0)->getType();
1100   unsigned NumVecElems = VecTy->getVectorNumElements();
1101   if (!isPowerOf2_32(NumVecElems))
1102     return RK_None;
1103 
1104   // We look for a sequence of shuffles and adds like the following matching one
1105   // fadd, shuffle vector pair at a time.
1106   //
1107   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
1108   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
1109   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
1110   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
1111   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1112   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
1113   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1114 
1115   unsigned MaskStart = 1;
1116   Instruction *RdxOp = RdxStart;
1117   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
1118   unsigned NumVecElemsRemain = NumVecElems;
1119   while (NumVecElemsRemain - 1) {
1120     // Check for the right reduction operation.
1121     if (!RdxOp)
1122       return RK_None;
1123     Optional<ReductionData> RDLevel = getReductionData(RdxOp);
1124     if (!RDLevel || !RDLevel->hasSameData(*RD))
1125       return RK_None;
1126 
1127     Value *NextRdxOp;
1128     ShuffleVectorInst *Shuffle;
1129     std::tie(NextRdxOp, Shuffle) =
1130         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
1131 
1132     // Check the current reduction operation and the shuffle use the same value.
1133     if (Shuffle == nullptr)
1134       return RK_None;
1135     if (Shuffle->getOperand(0) != NextRdxOp)
1136       return RK_None;
1137 
1138     // Check that shuffle masks matches.
1139     for (unsigned j = 0; j != MaskStart; ++j)
1140       ShuffleMask[j] = MaskStart + j;
1141     // Fill the rest of the mask with -1 for undef.
1142     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
1143 
1144     SmallVector<int, 16> Mask = Shuffle->getShuffleMask();
1145     if (ShuffleMask != Mask)
1146       return RK_None;
1147 
1148     RdxOp = dyn_cast<Instruction>(NextRdxOp);
1149     NumVecElemsRemain /= 2;
1150     MaskStart *= 2;
1151   }
1152 
1153   Opcode = RD->Opcode;
1154   Ty = VecTy;
1155   return RD->Kind;
1156 }
1157 
1158 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1159   switch (I->getOpcode()) {
1160   case Instruction::GetElementPtr:
1161     return getUserCost(I);
1162 
1163   case Instruction::Ret:
1164   case Instruction::PHI:
1165   case Instruction::Br: {
1166     return getCFInstrCost(I->getOpcode());
1167   }
1168   case Instruction::Add:
1169   case Instruction::FAdd:
1170   case Instruction::Sub:
1171   case Instruction::FSub:
1172   case Instruction::Mul:
1173   case Instruction::FMul:
1174   case Instruction::UDiv:
1175   case Instruction::SDiv:
1176   case Instruction::FDiv:
1177   case Instruction::URem:
1178   case Instruction::SRem:
1179   case Instruction::FRem:
1180   case Instruction::Shl:
1181   case Instruction::LShr:
1182   case Instruction::AShr:
1183   case Instruction::And:
1184   case Instruction::Or:
1185   case Instruction::Xor: {
1186     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1187     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1188     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1189     Op2VK = getOperandInfo(I->getOperand(1), Op2VP);
1190     SmallVector<const Value *, 2> Operands(I->operand_values());
1191     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1192                                   Op1VP, Op2VP, Operands, I);
1193   }
1194   case Instruction::FNeg: {
1195     TargetTransformInfo::OperandValueKind Op1VK, Op2VK;
1196     TargetTransformInfo::OperandValueProperties Op1VP, Op2VP;
1197     Op1VK = getOperandInfo(I->getOperand(0), Op1VP);
1198     Op2VK = OK_AnyValue;
1199     Op2VP = OP_None;
1200     SmallVector<const Value *, 2> Operands(I->operand_values());
1201     return getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, Op2VK,
1202                                   Op1VP, Op2VP, Operands, I);
1203   }
1204   case Instruction::Select: {
1205     const SelectInst *SI = cast<SelectInst>(I);
1206     Type *CondTy = SI->getCondition()->getType();
1207     return getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy, I);
1208   }
1209   case Instruction::ICmp:
1210   case Instruction::FCmp: {
1211     Type *ValTy = I->getOperand(0)->getType();
1212     return getCmpSelInstrCost(I->getOpcode(), ValTy, I->getType(), I);
1213   }
1214   case Instruction::Store: {
1215     const StoreInst *SI = cast<StoreInst>(I);
1216     Type *ValTy = SI->getValueOperand()->getType();
1217     return getMemoryOpCost(I->getOpcode(), ValTy,
1218                            MaybeAlign(SI->getAlignment()),
1219                            SI->getPointerAddressSpace(), I);
1220   }
1221   case Instruction::Load: {
1222     const LoadInst *LI = cast<LoadInst>(I);
1223     return getMemoryOpCost(I->getOpcode(), I->getType(),
1224                            MaybeAlign(LI->getAlignment()),
1225                            LI->getPointerAddressSpace(), I);
1226   }
1227   case Instruction::ZExt:
1228   case Instruction::SExt:
1229   case Instruction::FPToUI:
1230   case Instruction::FPToSI:
1231   case Instruction::FPExt:
1232   case Instruction::PtrToInt:
1233   case Instruction::IntToPtr:
1234   case Instruction::SIToFP:
1235   case Instruction::UIToFP:
1236   case Instruction::Trunc:
1237   case Instruction::FPTrunc:
1238   case Instruction::BitCast:
1239   case Instruction::AddrSpaceCast: {
1240     Type *SrcTy = I->getOperand(0)->getType();
1241     return getCastInstrCost(I->getOpcode(), I->getType(), SrcTy, I);
1242   }
1243   case Instruction::ExtractElement: {
1244     const ExtractElementInst * EEI = cast<ExtractElementInst>(I);
1245     ConstantInt *CI = dyn_cast<ConstantInt>(I->getOperand(1));
1246     unsigned Idx = -1;
1247     if (CI)
1248       Idx = CI->getZExtValue();
1249 
1250     // Try to match a reduction sequence (series of shufflevector and vector
1251     // adds followed by a extractelement).
1252     unsigned ReduxOpCode;
1253     Type *ReduxType;
1254 
1255     switch (matchVectorSplittingReduction(EEI, ReduxOpCode, ReduxType)) {
1256     case RK_Arithmetic:
1257       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1258                                              /*IsPairwiseForm=*/false);
1259     case RK_MinMax:
1260       return getMinMaxReductionCost(
1261           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1262           /*IsPairwiseForm=*/false, /*IsUnsigned=*/false);
1263     case RK_UnsignedMinMax:
1264       return getMinMaxReductionCost(
1265           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1266           /*IsPairwiseForm=*/false, /*IsUnsigned=*/true);
1267     case RK_None:
1268       break;
1269     }
1270 
1271     switch (matchPairwiseReduction(EEI, ReduxOpCode, ReduxType)) {
1272     case RK_Arithmetic:
1273       return getArithmeticReductionCost(ReduxOpCode, ReduxType,
1274                                              /*IsPairwiseForm=*/true);
1275     case RK_MinMax:
1276       return getMinMaxReductionCost(
1277           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1278           /*IsPairwiseForm=*/true, /*IsUnsigned=*/false);
1279     case RK_UnsignedMinMax:
1280       return getMinMaxReductionCost(
1281           ReduxType, CmpInst::makeCmpResultType(ReduxType),
1282           /*IsPairwiseForm=*/true, /*IsUnsigned=*/true);
1283     case RK_None:
1284       break;
1285     }
1286 
1287     return getVectorInstrCost(I->getOpcode(),
1288                                    EEI->getOperand(0)->getType(), Idx);
1289   }
1290   case Instruction::InsertElement: {
1291     const InsertElementInst * IE = cast<InsertElementInst>(I);
1292     ConstantInt *CI = dyn_cast<ConstantInt>(IE->getOperand(2));
1293     unsigned Idx = -1;
1294     if (CI)
1295       Idx = CI->getZExtValue();
1296     return getVectorInstrCost(I->getOpcode(),
1297                                    IE->getType(), Idx);
1298   }
1299   case Instruction::ExtractValue:
1300     return 0; // Model all ExtractValue nodes as free.
1301   case Instruction::ShuffleVector: {
1302     const ShuffleVectorInst *Shuffle = cast<ShuffleVectorInst>(I);
1303     Type *Ty = Shuffle->getType();
1304     Type *SrcTy = Shuffle->getOperand(0)->getType();
1305 
1306     // TODO: Identify and add costs for insert subvector, etc.
1307     int SubIndex;
1308     if (Shuffle->isExtractSubvectorMask(SubIndex))
1309       return TTIImpl->getShuffleCost(SK_ExtractSubvector, SrcTy, SubIndex, Ty);
1310 
1311     if (Shuffle->changesLength())
1312       return -1;
1313 
1314     if (Shuffle->isIdentity())
1315       return 0;
1316 
1317     if (Shuffle->isReverse())
1318       return TTIImpl->getShuffleCost(SK_Reverse, Ty, 0, nullptr);
1319 
1320     if (Shuffle->isSelect())
1321       return TTIImpl->getShuffleCost(SK_Select, Ty, 0, nullptr);
1322 
1323     if (Shuffle->isTranspose())
1324       return TTIImpl->getShuffleCost(SK_Transpose, Ty, 0, nullptr);
1325 
1326     if (Shuffle->isZeroEltSplat())
1327       return TTIImpl->getShuffleCost(SK_Broadcast, Ty, 0, nullptr);
1328 
1329     if (Shuffle->isSingleSource())
1330       return TTIImpl->getShuffleCost(SK_PermuteSingleSrc, Ty, 0, nullptr);
1331 
1332     return TTIImpl->getShuffleCost(SK_PermuteTwoSrc, Ty, 0, nullptr);
1333   }
1334   case Instruction::Call:
1335     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
1336       SmallVector<Value *, 4> Args(II->arg_operands());
1337 
1338       FastMathFlags FMF;
1339       if (auto *FPMO = dyn_cast<FPMathOperator>(II))
1340         FMF = FPMO->getFastMathFlags();
1341 
1342       return getIntrinsicInstrCost(II->getIntrinsicID(), II->getType(),
1343                                         Args, FMF);
1344     }
1345     return -1;
1346   default:
1347     // We don't have any information on this instruction.
1348     return -1;
1349   }
1350 }
1351 
1352 TargetTransformInfo::Concept::~Concept() {}
1353 
1354 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1355 
1356 TargetIRAnalysis::TargetIRAnalysis(
1357     std::function<Result(const Function &)> TTICallback)
1358     : TTICallback(std::move(TTICallback)) {}
1359 
1360 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1361                                                FunctionAnalysisManager &) {
1362   return TTICallback(F);
1363 }
1364 
1365 AnalysisKey TargetIRAnalysis::Key;
1366 
1367 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1368   return Result(F.getParent()->getDataLayout());
1369 }
1370 
1371 // Register the basic pass.
1372 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1373                 "Target Transform Information", false, true)
1374 char TargetTransformInfoWrapperPass::ID = 0;
1375 
1376 void TargetTransformInfoWrapperPass::anchor() {}
1377 
1378 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1379     : ImmutablePass(ID) {
1380   initializeTargetTransformInfoWrapperPassPass(
1381       *PassRegistry::getPassRegistry());
1382 }
1383 
1384 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1385     TargetIRAnalysis TIRA)
1386     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1387   initializeTargetTransformInfoWrapperPassPass(
1388       *PassRegistry::getPassRegistry());
1389 }
1390 
1391 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1392   FunctionAnalysisManager DummyFAM;
1393   TTI = TIRA.run(F, DummyFAM);
1394   return *TTI;
1395 }
1396 
1397 ImmutablePass *
1398 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1399   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1400 }
1401