1 //===- llvm/Analysis/TargetTransformInfo.cpp ------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/Analysis/TargetTransformInfo.h"
10 #include "llvm/Analysis/CFG.h"
11 #include "llvm/Analysis/LoopIterator.h"
12 #include "llvm/Analysis/TargetTransformInfoImpl.h"
13 #include "llvm/IR/CFG.h"
14 #include "llvm/IR/DataLayout.h"
15 #include "llvm/IR/Dominators.h"
16 #include "llvm/IR/Instruction.h"
17 #include "llvm/IR/Instructions.h"
18 #include "llvm/IR/IntrinsicInst.h"
19 #include "llvm/IR/Module.h"
20 #include "llvm/IR/Operator.h"
21 #include "llvm/IR/PatternMatch.h"
22 #include "llvm/InitializePasses.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include <utility>
26 
27 using namespace llvm;
28 using namespace PatternMatch;
29 
30 #define DEBUG_TYPE "tti"
31 
32 static cl::opt<bool> EnableReduxCost("costmodel-reduxcost", cl::init(false),
33                                      cl::Hidden,
34                                      cl::desc("Recognize reduction patterns."));
35 
36 namespace {
37 /// No-op implementation of the TTI interface using the utility base
38 /// classes.
39 ///
40 /// This is used when no target specific information is available.
41 struct NoTTIImpl : TargetTransformInfoImplCRTPBase<NoTTIImpl> {
42   explicit NoTTIImpl(const DataLayout &DL)
43       : TargetTransformInfoImplCRTPBase<NoTTIImpl>(DL) {}
44 };
45 } // namespace
46 
47 bool HardwareLoopInfo::canAnalyze(LoopInfo &LI) {
48   // If the loop has irreducible control flow, it can not be converted to
49   // Hardware loop.
50   LoopBlocksRPO RPOT(L);
51   RPOT.perform(&LI);
52   if (containsIrreducibleCFG<const BasicBlock *>(RPOT, LI))
53     return false;
54   return true;
55 }
56 
57 IntrinsicCostAttributes::IntrinsicCostAttributes(Intrinsic::ID Id,
58                                                  const CallBase &CI,
59                                                  unsigned ScalarizationCost)
60     : II(dyn_cast<IntrinsicInst>(&CI)), RetTy(CI.getType()), IID(Id),
61       ScalarizationCost(ScalarizationCost) {
62 
63   if (const auto *FPMO = dyn_cast<FPMathOperator>(&CI))
64     FMF = FPMO->getFastMathFlags();
65 
66   Arguments.insert(Arguments.begin(), CI.arg_begin(), CI.arg_end());
67   FunctionType *FTy = CI.getCalledFunction()->getFunctionType();
68   ParamTys.insert(ParamTys.begin(), FTy->param_begin(), FTy->param_end());
69 }
70 
71 IntrinsicCostAttributes::IntrinsicCostAttributes(Intrinsic::ID Id, Type *RTy,
72                                                  ArrayRef<Type *> Tys,
73                                                  FastMathFlags Flags,
74                                                  const IntrinsicInst *I,
75                                                  unsigned ScalarCost)
76     : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
77   ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
78 }
79 
80 IntrinsicCostAttributes::IntrinsicCostAttributes(Intrinsic::ID Id, Type *Ty,
81                                                  ArrayRef<const Value *> Args)
82     : RetTy(Ty), IID(Id) {
83 
84   Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
85   ParamTys.reserve(Arguments.size());
86   for (unsigned Idx = 0, Size = Arguments.size(); Idx != Size; ++Idx)
87     ParamTys.push_back(Arguments[Idx]->getType());
88 }
89 
90 IntrinsicCostAttributes::IntrinsicCostAttributes(Intrinsic::ID Id, Type *RTy,
91                                                  ArrayRef<const Value *> Args,
92                                                  ArrayRef<Type *> Tys,
93                                                  FastMathFlags Flags,
94                                                  const IntrinsicInst *I,
95                                                  unsigned ScalarCost)
96     : II(I), RetTy(RTy), IID(Id), FMF(Flags), ScalarizationCost(ScalarCost) {
97   ParamTys.insert(ParamTys.begin(), Tys.begin(), Tys.end());
98   Arguments.insert(Arguments.begin(), Args.begin(), Args.end());
99 }
100 
101 bool HardwareLoopInfo::isHardwareLoopCandidate(ScalarEvolution &SE,
102                                                LoopInfo &LI, DominatorTree &DT,
103                                                bool ForceNestedLoop,
104                                                bool ForceHardwareLoopPHI) {
105   SmallVector<BasicBlock *, 4> ExitingBlocks;
106   L->getExitingBlocks(ExitingBlocks);
107 
108   for (BasicBlock *BB : ExitingBlocks) {
109     // If we pass the updated counter back through a phi, we need to know
110     // which latch the updated value will be coming from.
111     if (!L->isLoopLatch(BB)) {
112       if (ForceHardwareLoopPHI || CounterInReg)
113         continue;
114     }
115 
116     const SCEV *EC = SE.getExitCount(L, BB);
117     if (isa<SCEVCouldNotCompute>(EC))
118       continue;
119     if (const SCEVConstant *ConstEC = dyn_cast<SCEVConstant>(EC)) {
120       if (ConstEC->getValue()->isZero())
121         continue;
122     } else if (!SE.isLoopInvariant(EC, L))
123       continue;
124 
125     if (SE.getTypeSizeInBits(EC->getType()) > CountType->getBitWidth())
126       continue;
127 
128     // If this exiting block is contained in a nested loop, it is not eligible
129     // for insertion of the branch-and-decrement since the inner loop would
130     // end up messing up the value in the CTR.
131     if (!IsNestingLegal && LI.getLoopFor(BB) != L && !ForceNestedLoop)
132       continue;
133 
134     // We now have a loop-invariant count of loop iterations (which is not the
135     // constant zero) for which we know that this loop will not exit via this
136     // existing block.
137 
138     // We need to make sure that this block will run on every loop iteration.
139     // For this to be true, we must dominate all blocks with backedges. Such
140     // blocks are in-loop predecessors to the header block.
141     bool NotAlways = false;
142     for (BasicBlock *Pred : predecessors(L->getHeader())) {
143       if (!L->contains(Pred))
144         continue;
145 
146       if (!DT.dominates(BB, Pred)) {
147         NotAlways = true;
148         break;
149       }
150     }
151 
152     if (NotAlways)
153       continue;
154 
155     // Make sure this blocks ends with a conditional branch.
156     Instruction *TI = BB->getTerminator();
157     if (!TI)
158       continue;
159 
160     if (BranchInst *BI = dyn_cast<BranchInst>(TI)) {
161       if (!BI->isConditional())
162         continue;
163 
164       ExitBranch = BI;
165     } else
166       continue;
167 
168     // Note that this block may not be the loop latch block, even if the loop
169     // has a latch block.
170     ExitBlock = BB;
171     TripCount = SE.getAddExpr(EC, SE.getOne(EC->getType()));
172 
173     if (!EC->getType()->isPointerTy() && EC->getType() != CountType)
174       TripCount = SE.getZeroExtendExpr(TripCount, CountType);
175 
176     break;
177   }
178 
179   if (!ExitBlock)
180     return false;
181   return true;
182 }
183 
184 TargetTransformInfo::TargetTransformInfo(const DataLayout &DL)
185     : TTIImpl(new Model<NoTTIImpl>(NoTTIImpl(DL))) {}
186 
187 TargetTransformInfo::~TargetTransformInfo() {}
188 
189 TargetTransformInfo::TargetTransformInfo(TargetTransformInfo &&Arg)
190     : TTIImpl(std::move(Arg.TTIImpl)) {}
191 
192 TargetTransformInfo &TargetTransformInfo::operator=(TargetTransformInfo &&RHS) {
193   TTIImpl = std::move(RHS.TTIImpl);
194   return *this;
195 }
196 
197 unsigned TargetTransformInfo::getInliningThresholdMultiplier() const {
198   return TTIImpl->getInliningThresholdMultiplier();
199 }
200 
201 unsigned
202 TargetTransformInfo::adjustInliningThreshold(const CallBase *CB) const {
203   return TTIImpl->adjustInliningThreshold(CB);
204 }
205 
206 int TargetTransformInfo::getInlinerVectorBonusPercent() const {
207   return TTIImpl->getInlinerVectorBonusPercent();
208 }
209 
210 int TargetTransformInfo::getGEPCost(Type *PointeeType, const Value *Ptr,
211                                     ArrayRef<const Value *> Operands,
212                                     TTI::TargetCostKind CostKind) const {
213   return TTIImpl->getGEPCost(PointeeType, Ptr, Operands, CostKind);
214 }
215 
216 unsigned TargetTransformInfo::getEstimatedNumberOfCaseClusters(
217     const SwitchInst &SI, unsigned &JTSize, ProfileSummaryInfo *PSI,
218     BlockFrequencyInfo *BFI) const {
219   return TTIImpl->getEstimatedNumberOfCaseClusters(SI, JTSize, PSI, BFI);
220 }
221 
222 int TargetTransformInfo::getUserCost(const User *U,
223                                      ArrayRef<const Value *> Operands,
224                                      enum TargetCostKind CostKind) const {
225   int Cost = TTIImpl->getUserCost(U, Operands, CostKind);
226   assert((CostKind == TTI::TCK_RecipThroughput || Cost >= 0) &&
227          "TTI should not produce negative costs!");
228   return Cost;
229 }
230 
231 BranchProbability TargetTransformInfo::getPredictableBranchThreshold() const {
232   return TTIImpl->getPredictableBranchThreshold();
233 }
234 
235 bool TargetTransformInfo::hasBranchDivergence() const {
236   return TTIImpl->hasBranchDivergence();
237 }
238 
239 bool TargetTransformInfo::useGPUDivergenceAnalysis() const {
240   return TTIImpl->useGPUDivergenceAnalysis();
241 }
242 
243 bool TargetTransformInfo::isSourceOfDivergence(const Value *V) const {
244   return TTIImpl->isSourceOfDivergence(V);
245 }
246 
247 bool llvm::TargetTransformInfo::isAlwaysUniform(const Value *V) const {
248   return TTIImpl->isAlwaysUniform(V);
249 }
250 
251 unsigned TargetTransformInfo::getFlatAddressSpace() const {
252   return TTIImpl->getFlatAddressSpace();
253 }
254 
255 bool TargetTransformInfo::collectFlatAddressOperands(
256     SmallVectorImpl<int> &OpIndexes, Intrinsic::ID IID) const {
257   return TTIImpl->collectFlatAddressOperands(OpIndexes, IID);
258 }
259 
260 bool TargetTransformInfo::isNoopAddrSpaceCast(unsigned FromAS,
261                                               unsigned ToAS) const {
262   return TTIImpl->isNoopAddrSpaceCast(FromAS, ToAS);
263 }
264 
265 unsigned TargetTransformInfo::getAssumedAddrSpace(const Value *V) const {
266   return TTIImpl->getAssumedAddrSpace(V);
267 }
268 
269 Value *TargetTransformInfo::rewriteIntrinsicWithAddressSpace(
270     IntrinsicInst *II, Value *OldV, Value *NewV) const {
271   return TTIImpl->rewriteIntrinsicWithAddressSpace(II, OldV, NewV);
272 }
273 
274 bool TargetTransformInfo::isLoweredToCall(const Function *F) const {
275   return TTIImpl->isLoweredToCall(F);
276 }
277 
278 bool TargetTransformInfo::isHardwareLoopProfitable(
279     Loop *L, ScalarEvolution &SE, AssumptionCache &AC,
280     TargetLibraryInfo *LibInfo, HardwareLoopInfo &HWLoopInfo) const {
281   return TTIImpl->isHardwareLoopProfitable(L, SE, AC, LibInfo, HWLoopInfo);
282 }
283 
284 bool TargetTransformInfo::preferPredicateOverEpilogue(
285     Loop *L, LoopInfo *LI, ScalarEvolution &SE, AssumptionCache &AC,
286     TargetLibraryInfo *TLI, DominatorTree *DT,
287     const LoopAccessInfo *LAI) const {
288   return TTIImpl->preferPredicateOverEpilogue(L, LI, SE, AC, TLI, DT, LAI);
289 }
290 
291 bool TargetTransformInfo::emitGetActiveLaneMask() const {
292   return TTIImpl->emitGetActiveLaneMask();
293 }
294 
295 Optional<Instruction *>
296 TargetTransformInfo::instCombineIntrinsic(InstCombiner &IC,
297                                           IntrinsicInst &II) const {
298   return TTIImpl->instCombineIntrinsic(IC, II);
299 }
300 
301 Optional<Value *> TargetTransformInfo::simplifyDemandedUseBitsIntrinsic(
302     InstCombiner &IC, IntrinsicInst &II, APInt DemandedMask, KnownBits &Known,
303     bool &KnownBitsComputed) const {
304   return TTIImpl->simplifyDemandedUseBitsIntrinsic(IC, II, DemandedMask, Known,
305                                                    KnownBitsComputed);
306 }
307 
308 Optional<Value *> TargetTransformInfo::simplifyDemandedVectorEltsIntrinsic(
309     InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
310     APInt &UndefElts2, APInt &UndefElts3,
311     std::function<void(Instruction *, unsigned, APInt, APInt &)>
312         SimplifyAndSetOp) const {
313   return TTIImpl->simplifyDemandedVectorEltsIntrinsic(
314       IC, II, DemandedElts, UndefElts, UndefElts2, UndefElts3,
315       SimplifyAndSetOp);
316 }
317 
318 void TargetTransformInfo::getUnrollingPreferences(
319     Loop *L, ScalarEvolution &SE, UnrollingPreferences &UP) const {
320   return TTIImpl->getUnrollingPreferences(L, SE, UP);
321 }
322 
323 void TargetTransformInfo::getPeelingPreferences(Loop *L, ScalarEvolution &SE,
324                                                 PeelingPreferences &PP) const {
325   return TTIImpl->getPeelingPreferences(L, SE, PP);
326 }
327 
328 bool TargetTransformInfo::isLegalAddImmediate(int64_t Imm) const {
329   return TTIImpl->isLegalAddImmediate(Imm);
330 }
331 
332 bool TargetTransformInfo::isLegalICmpImmediate(int64_t Imm) const {
333   return TTIImpl->isLegalICmpImmediate(Imm);
334 }
335 
336 bool TargetTransformInfo::isLegalAddressingMode(Type *Ty, GlobalValue *BaseGV,
337                                                 int64_t BaseOffset,
338                                                 bool HasBaseReg, int64_t Scale,
339                                                 unsigned AddrSpace,
340                                                 Instruction *I) const {
341   return TTIImpl->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg,
342                                         Scale, AddrSpace, I);
343 }
344 
345 bool TargetTransformInfo::isLSRCostLess(LSRCost &C1, LSRCost &C2) const {
346   return TTIImpl->isLSRCostLess(C1, C2);
347 }
348 
349 bool TargetTransformInfo::isNumRegsMajorCostOfLSR() const {
350   return TTIImpl->isNumRegsMajorCostOfLSR();
351 }
352 
353 bool TargetTransformInfo::isProfitableLSRChainElement(Instruction *I) const {
354   return TTIImpl->isProfitableLSRChainElement(I);
355 }
356 
357 bool TargetTransformInfo::canMacroFuseCmp() const {
358   return TTIImpl->canMacroFuseCmp();
359 }
360 
361 bool TargetTransformInfo::canSaveCmp(Loop *L, BranchInst **BI,
362                                      ScalarEvolution *SE, LoopInfo *LI,
363                                      DominatorTree *DT, AssumptionCache *AC,
364                                      TargetLibraryInfo *LibInfo) const {
365   return TTIImpl->canSaveCmp(L, BI, SE, LI, DT, AC, LibInfo);
366 }
367 
368 TTI::AddressingModeKind
369 TargetTransformInfo::getPreferredAddressingMode(const Loop *L,
370                                                 ScalarEvolution *SE) const {
371   return TTIImpl->getPreferredAddressingMode(L, SE);
372 }
373 
374 bool TargetTransformInfo::isLegalMaskedStore(Type *DataType,
375                                              Align Alignment) const {
376   return TTIImpl->isLegalMaskedStore(DataType, Alignment);
377 }
378 
379 bool TargetTransformInfo::isLegalMaskedLoad(Type *DataType,
380                                             Align Alignment) const {
381   return TTIImpl->isLegalMaskedLoad(DataType, Alignment);
382 }
383 
384 bool TargetTransformInfo::isLegalNTStore(Type *DataType,
385                                          Align Alignment) const {
386   return TTIImpl->isLegalNTStore(DataType, Alignment);
387 }
388 
389 bool TargetTransformInfo::isLegalNTLoad(Type *DataType, Align Alignment) const {
390   return TTIImpl->isLegalNTLoad(DataType, Alignment);
391 }
392 
393 bool TargetTransformInfo::isLegalMaskedGather(Type *DataType,
394                                               Align Alignment) const {
395   return TTIImpl->isLegalMaskedGather(DataType, Alignment);
396 }
397 
398 bool TargetTransformInfo::isLegalMaskedScatter(Type *DataType,
399                                                Align Alignment) const {
400   return TTIImpl->isLegalMaskedScatter(DataType, Alignment);
401 }
402 
403 bool TargetTransformInfo::isLegalMaskedCompressStore(Type *DataType) const {
404   return TTIImpl->isLegalMaskedCompressStore(DataType);
405 }
406 
407 bool TargetTransformInfo::isLegalMaskedExpandLoad(Type *DataType) const {
408   return TTIImpl->isLegalMaskedExpandLoad(DataType);
409 }
410 
411 bool TargetTransformInfo::hasDivRemOp(Type *DataType, bool IsSigned) const {
412   return TTIImpl->hasDivRemOp(DataType, IsSigned);
413 }
414 
415 bool TargetTransformInfo::hasVolatileVariant(Instruction *I,
416                                              unsigned AddrSpace) const {
417   return TTIImpl->hasVolatileVariant(I, AddrSpace);
418 }
419 
420 bool TargetTransformInfo::prefersVectorizedAddressing() const {
421   return TTIImpl->prefersVectorizedAddressing();
422 }
423 
424 int TargetTransformInfo::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
425                                               int64_t BaseOffset,
426                                               bool HasBaseReg, int64_t Scale,
427                                               unsigned AddrSpace) const {
428   int Cost = TTIImpl->getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg,
429                                            Scale, AddrSpace);
430   assert(Cost >= 0 && "TTI should not produce negative costs!");
431   return Cost;
432 }
433 
434 bool TargetTransformInfo::LSRWithInstrQueries() const {
435   return TTIImpl->LSRWithInstrQueries();
436 }
437 
438 bool TargetTransformInfo::isTruncateFree(Type *Ty1, Type *Ty2) const {
439   return TTIImpl->isTruncateFree(Ty1, Ty2);
440 }
441 
442 bool TargetTransformInfo::isProfitableToHoist(Instruction *I) const {
443   return TTIImpl->isProfitableToHoist(I);
444 }
445 
446 bool TargetTransformInfo::useAA() const { return TTIImpl->useAA(); }
447 
448 bool TargetTransformInfo::isTypeLegal(Type *Ty) const {
449   return TTIImpl->isTypeLegal(Ty);
450 }
451 
452 unsigned TargetTransformInfo::getRegUsageForType(Type *Ty) const {
453   return TTIImpl->getRegUsageForType(Ty);
454 }
455 
456 bool TargetTransformInfo::shouldBuildLookupTables() const {
457   return TTIImpl->shouldBuildLookupTables();
458 }
459 
460 bool TargetTransformInfo::shouldBuildLookupTablesForConstant(
461     Constant *C) const {
462   return TTIImpl->shouldBuildLookupTablesForConstant(C);
463 }
464 
465 bool TargetTransformInfo::shouldBuildRelLookupTables() const {
466   return TTIImpl->shouldBuildRelLookupTables();
467 }
468 
469 bool TargetTransformInfo::useColdCCForColdCall(Function &F) const {
470   return TTIImpl->useColdCCForColdCall(F);
471 }
472 
473 unsigned
474 TargetTransformInfo::getScalarizationOverhead(VectorType *Ty,
475                                               const APInt &DemandedElts,
476                                               bool Insert, bool Extract) const {
477   return TTIImpl->getScalarizationOverhead(Ty, DemandedElts, Insert, Extract);
478 }
479 
480 unsigned TargetTransformInfo::getOperandsScalarizationOverhead(
481     ArrayRef<const Value *> Args, ArrayRef<Type *> Tys) const {
482   return TTIImpl->getOperandsScalarizationOverhead(Args, Tys);
483 }
484 
485 bool TargetTransformInfo::supportsEfficientVectorElementLoadStore() const {
486   return TTIImpl->supportsEfficientVectorElementLoadStore();
487 }
488 
489 bool TargetTransformInfo::enableAggressiveInterleaving(
490     bool LoopHasReductions) const {
491   return TTIImpl->enableAggressiveInterleaving(LoopHasReductions);
492 }
493 
494 TargetTransformInfo::MemCmpExpansionOptions
495 TargetTransformInfo::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
496   return TTIImpl->enableMemCmpExpansion(OptSize, IsZeroCmp);
497 }
498 
499 bool TargetTransformInfo::enableInterleavedAccessVectorization() const {
500   return TTIImpl->enableInterleavedAccessVectorization();
501 }
502 
503 bool TargetTransformInfo::enableMaskedInterleavedAccessVectorization() const {
504   return TTIImpl->enableMaskedInterleavedAccessVectorization();
505 }
506 
507 bool TargetTransformInfo::isFPVectorizationPotentiallyUnsafe() const {
508   return TTIImpl->isFPVectorizationPotentiallyUnsafe();
509 }
510 
511 bool TargetTransformInfo::allowsMisalignedMemoryAccesses(LLVMContext &Context,
512                                                          unsigned BitWidth,
513                                                          unsigned AddressSpace,
514                                                          Align Alignment,
515                                                          bool *Fast) const {
516   return TTIImpl->allowsMisalignedMemoryAccesses(Context, BitWidth,
517                                                  AddressSpace, Alignment, Fast);
518 }
519 
520 TargetTransformInfo::PopcntSupportKind
521 TargetTransformInfo::getPopcntSupport(unsigned IntTyWidthInBit) const {
522   return TTIImpl->getPopcntSupport(IntTyWidthInBit);
523 }
524 
525 bool TargetTransformInfo::haveFastSqrt(Type *Ty) const {
526   return TTIImpl->haveFastSqrt(Ty);
527 }
528 
529 bool TargetTransformInfo::isFCmpOrdCheaperThanFCmpZero(Type *Ty) const {
530   return TTIImpl->isFCmpOrdCheaperThanFCmpZero(Ty);
531 }
532 
533 int TargetTransformInfo::getFPOpCost(Type *Ty) const {
534   int Cost = TTIImpl->getFPOpCost(Ty);
535   assert(Cost >= 0 && "TTI should not produce negative costs!");
536   return Cost;
537 }
538 
539 int TargetTransformInfo::getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx,
540                                                const APInt &Imm,
541                                                Type *Ty) const {
542   int Cost = TTIImpl->getIntImmCodeSizeCost(Opcode, Idx, Imm, Ty);
543   assert(Cost >= 0 && "TTI should not produce negative costs!");
544   return Cost;
545 }
546 
547 int TargetTransformInfo::getIntImmCost(const APInt &Imm, Type *Ty,
548                                        TTI::TargetCostKind CostKind) const {
549   int Cost = TTIImpl->getIntImmCost(Imm, Ty, CostKind);
550   assert(Cost >= 0 && "TTI should not produce negative costs!");
551   return Cost;
552 }
553 
554 int TargetTransformInfo::getIntImmCostInst(unsigned Opcode, unsigned Idx,
555                                            const APInt &Imm, Type *Ty,
556                                            TTI::TargetCostKind CostKind,
557                                            Instruction *Inst) const {
558   int Cost = TTIImpl->getIntImmCostInst(Opcode, Idx, Imm, Ty, CostKind, Inst);
559   assert(Cost >= 0 && "TTI should not produce negative costs!");
560   return Cost;
561 }
562 
563 int
564 TargetTransformInfo::getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
565                                          const APInt &Imm, Type *Ty,
566                                          TTI::TargetCostKind CostKind) const {
567   int Cost = TTIImpl->getIntImmCostIntrin(IID, Idx, Imm, Ty, CostKind);
568   assert(Cost >= 0 && "TTI should not produce negative costs!");
569   return Cost;
570 }
571 
572 unsigned TargetTransformInfo::getNumberOfRegisters(unsigned ClassID) const {
573   return TTIImpl->getNumberOfRegisters(ClassID);
574 }
575 
576 unsigned TargetTransformInfo::getRegisterClassForType(bool Vector,
577                                                       Type *Ty) const {
578   return TTIImpl->getRegisterClassForType(Vector, Ty);
579 }
580 
581 const char *TargetTransformInfo::getRegisterClassName(unsigned ClassID) const {
582   return TTIImpl->getRegisterClassName(ClassID);
583 }
584 
585 unsigned TargetTransformInfo::getRegisterBitWidth(bool Vector) const {
586   return TTIImpl->getRegisterBitWidth(Vector);
587 }
588 
589 unsigned TargetTransformInfo::getMinVectorRegisterBitWidth() const {
590   return TTIImpl->getMinVectorRegisterBitWidth();
591 }
592 
593 Optional<unsigned> TargetTransformInfo::getMaxVScale() const {
594   return TTIImpl->getMaxVScale();
595 }
596 
597 bool TargetTransformInfo::shouldMaximizeVectorBandwidth(bool OptSize) const {
598   return TTIImpl->shouldMaximizeVectorBandwidth(OptSize);
599 }
600 
601 ElementCount TargetTransformInfo::getMinimumVF(unsigned ElemWidth,
602                                                bool IsScalable) const {
603   return TTIImpl->getMinimumVF(ElemWidth, IsScalable);
604 }
605 
606 unsigned TargetTransformInfo::getMaximumVF(unsigned ElemWidth,
607                                            unsigned Opcode) const {
608   return TTIImpl->getMaximumVF(ElemWidth, Opcode);
609 }
610 
611 bool TargetTransformInfo::shouldConsiderAddressTypePromotion(
612     const Instruction &I, bool &AllowPromotionWithoutCommonHeader) const {
613   return TTIImpl->shouldConsiderAddressTypePromotion(
614       I, AllowPromotionWithoutCommonHeader);
615 }
616 
617 unsigned TargetTransformInfo::getCacheLineSize() const {
618   return TTIImpl->getCacheLineSize();
619 }
620 
621 llvm::Optional<unsigned>
622 TargetTransformInfo::getCacheSize(CacheLevel Level) const {
623   return TTIImpl->getCacheSize(Level);
624 }
625 
626 llvm::Optional<unsigned>
627 TargetTransformInfo::getCacheAssociativity(CacheLevel Level) const {
628   return TTIImpl->getCacheAssociativity(Level);
629 }
630 
631 unsigned TargetTransformInfo::getPrefetchDistance() const {
632   return TTIImpl->getPrefetchDistance();
633 }
634 
635 unsigned TargetTransformInfo::getMinPrefetchStride(
636     unsigned NumMemAccesses, unsigned NumStridedMemAccesses,
637     unsigned NumPrefetches, bool HasCall) const {
638   return TTIImpl->getMinPrefetchStride(NumMemAccesses, NumStridedMemAccesses,
639                                        NumPrefetches, HasCall);
640 }
641 
642 unsigned TargetTransformInfo::getMaxPrefetchIterationsAhead() const {
643   return TTIImpl->getMaxPrefetchIterationsAhead();
644 }
645 
646 bool TargetTransformInfo::enableWritePrefetching() const {
647   return TTIImpl->enableWritePrefetching();
648 }
649 
650 unsigned TargetTransformInfo::getMaxInterleaveFactor(unsigned VF) const {
651   return TTIImpl->getMaxInterleaveFactor(VF);
652 }
653 
654 TargetTransformInfo::OperandValueKind
655 TargetTransformInfo::getOperandInfo(const Value *V,
656                                     OperandValueProperties &OpProps) {
657   OperandValueKind OpInfo = OK_AnyValue;
658   OpProps = OP_None;
659 
660   if (const auto *CI = dyn_cast<ConstantInt>(V)) {
661     if (CI->getValue().isPowerOf2())
662       OpProps = OP_PowerOf2;
663     return OK_UniformConstantValue;
664   }
665 
666   // A broadcast shuffle creates a uniform value.
667   // TODO: Add support for non-zero index broadcasts.
668   // TODO: Add support for different source vector width.
669   if (const auto *ShuffleInst = dyn_cast<ShuffleVectorInst>(V))
670     if (ShuffleInst->isZeroEltSplat())
671       OpInfo = OK_UniformValue;
672 
673   const Value *Splat = getSplatValue(V);
674 
675   // Check for a splat of a constant or for a non uniform vector of constants
676   // and check if the constant(s) are all powers of two.
677   if (isa<ConstantVector>(V) || isa<ConstantDataVector>(V)) {
678     OpInfo = OK_NonUniformConstantValue;
679     if (Splat) {
680       OpInfo = OK_UniformConstantValue;
681       if (auto *CI = dyn_cast<ConstantInt>(Splat))
682         if (CI->getValue().isPowerOf2())
683           OpProps = OP_PowerOf2;
684     } else if (const auto *CDS = dyn_cast<ConstantDataSequential>(V)) {
685       OpProps = OP_PowerOf2;
686       for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I) {
687         if (auto *CI = dyn_cast<ConstantInt>(CDS->getElementAsConstant(I)))
688           if (CI->getValue().isPowerOf2())
689             continue;
690         OpProps = OP_None;
691         break;
692       }
693     }
694   }
695 
696   // Check for a splat of a uniform value. This is not loop aware, so return
697   // true only for the obviously uniform cases (argument, globalvalue)
698   if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
699     OpInfo = OK_UniformValue;
700 
701   return OpInfo;
702 }
703 
704 int TargetTransformInfo::getArithmeticInstrCost(
705     unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
706     OperandValueKind Opd1Info,
707     OperandValueKind Opd2Info, OperandValueProperties Opd1PropInfo,
708     OperandValueProperties Opd2PropInfo, ArrayRef<const Value *> Args,
709     const Instruction *CxtI) const {
710   int Cost = TTIImpl->getArithmeticInstrCost(
711       Opcode, Ty, CostKind, Opd1Info, Opd2Info, Opd1PropInfo, Opd2PropInfo,
712       Args, CxtI);
713   assert(Cost >= 0 && "TTI should not produce negative costs!");
714   return Cost;
715 }
716 
717 int TargetTransformInfo::getShuffleCost(ShuffleKind Kind, VectorType *Ty,
718                                         ArrayRef<int> Mask, int Index,
719                                         VectorType *SubTp) const {
720   int Cost = TTIImpl->getShuffleCost(Kind, Ty, Mask, Index, SubTp);
721   assert(Cost >= 0 && "TTI should not produce negative costs!");
722   return Cost;
723 }
724 
725 TTI::CastContextHint
726 TargetTransformInfo::getCastContextHint(const Instruction *I) {
727   if (!I)
728     return CastContextHint::None;
729 
730   auto getLoadStoreKind = [](const Value *V, unsigned LdStOp, unsigned MaskedOp,
731                              unsigned GatScatOp) {
732     const Instruction *I = dyn_cast<Instruction>(V);
733     if (!I)
734       return CastContextHint::None;
735 
736     if (I->getOpcode() == LdStOp)
737       return CastContextHint::Normal;
738 
739     if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) {
740       if (II->getIntrinsicID() == MaskedOp)
741         return TTI::CastContextHint::Masked;
742       if (II->getIntrinsicID() == GatScatOp)
743         return TTI::CastContextHint::GatherScatter;
744     }
745 
746     return TTI::CastContextHint::None;
747   };
748 
749   switch (I->getOpcode()) {
750   case Instruction::ZExt:
751   case Instruction::SExt:
752   case Instruction::FPExt:
753     return getLoadStoreKind(I->getOperand(0), Instruction::Load,
754                             Intrinsic::masked_load, Intrinsic::masked_gather);
755   case Instruction::Trunc:
756   case Instruction::FPTrunc:
757     if (I->hasOneUse())
758       return getLoadStoreKind(*I->user_begin(), Instruction::Store,
759                               Intrinsic::masked_store,
760                               Intrinsic::masked_scatter);
761     break;
762   default:
763     return CastContextHint::None;
764   }
765 
766   return TTI::CastContextHint::None;
767 }
768 
769 int TargetTransformInfo::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
770                                           CastContextHint CCH,
771                                           TTI::TargetCostKind CostKind,
772                                           const Instruction *I) const {
773   assert((I == nullptr || I->getOpcode() == Opcode) &&
774          "Opcode should reflect passed instruction.");
775   int Cost = TTIImpl->getCastInstrCost(Opcode, Dst, Src, CCH, CostKind, I);
776   assert(Cost >= 0 && "TTI should not produce negative costs!");
777   return Cost;
778 }
779 
780 int TargetTransformInfo::getExtractWithExtendCost(unsigned Opcode, Type *Dst,
781                                                   VectorType *VecTy,
782                                                   unsigned Index) const {
783   int Cost = TTIImpl->getExtractWithExtendCost(Opcode, Dst, VecTy, Index);
784   assert(Cost >= 0 && "TTI should not produce negative costs!");
785   return Cost;
786 }
787 
788 int TargetTransformInfo::getCFInstrCost(unsigned Opcode,
789                                         TTI::TargetCostKind CostKind) const {
790   int Cost = TTIImpl->getCFInstrCost(Opcode, CostKind);
791   assert(Cost >= 0 && "TTI should not produce negative costs!");
792   return Cost;
793 }
794 
795 int TargetTransformInfo::getCmpSelInstrCost(unsigned Opcode, Type *ValTy,
796                                             Type *CondTy,
797                                             CmpInst::Predicate VecPred,
798                                             TTI::TargetCostKind CostKind,
799                                             const Instruction *I) const {
800   assert((I == nullptr || I->getOpcode() == Opcode) &&
801          "Opcode should reflect passed instruction.");
802   int Cost =
803       TTIImpl->getCmpSelInstrCost(Opcode, ValTy, CondTy, VecPred, CostKind, I);
804   assert(Cost >= 0 && "TTI should not produce negative costs!");
805   return Cost;
806 }
807 
808 int TargetTransformInfo::getVectorInstrCost(unsigned Opcode, Type *Val,
809                                             unsigned Index) const {
810   int Cost = TTIImpl->getVectorInstrCost(Opcode, Val, Index);
811   assert(Cost >= 0 && "TTI should not produce negative costs!");
812   return Cost;
813 }
814 
815 int TargetTransformInfo::getMemoryOpCost(unsigned Opcode, Type *Src,
816                                          Align Alignment, unsigned AddressSpace,
817                                          TTI::TargetCostKind CostKind,
818                                          const Instruction *I) const {
819   assert((I == nullptr || I->getOpcode() == Opcode) &&
820          "Opcode should reflect passed instruction.");
821   int Cost = TTIImpl->getMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
822                                       CostKind, I);
823   assert(Cost >= 0 && "TTI should not produce negative costs!");
824   return Cost;
825 }
826 
827 int TargetTransformInfo::getMaskedMemoryOpCost(
828     unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace,
829     TTI::TargetCostKind CostKind) const {
830   int Cost =
831       TTIImpl->getMaskedMemoryOpCost(Opcode, Src, Alignment, AddressSpace,
832                                      CostKind);
833   assert(Cost >= 0 && "TTI should not produce negative costs!");
834   return Cost;
835 }
836 
837 int TargetTransformInfo::getGatherScatterOpCost(
838     unsigned Opcode, Type *DataTy, const Value *Ptr, bool VariableMask,
839     Align Alignment, TTI::TargetCostKind CostKind, const Instruction *I) const {
840   int Cost = TTIImpl->getGatherScatterOpCost(Opcode, DataTy, Ptr, VariableMask,
841                                              Alignment, CostKind, I);
842   assert(Cost >= 0 && "TTI should not produce negative costs!");
843   return Cost;
844 }
845 
846 int TargetTransformInfo::getInterleavedMemoryOpCost(
847     unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
848     Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
849     bool UseMaskForCond, bool UseMaskForGaps) const {
850   int Cost = TTIImpl->getInterleavedMemoryOpCost(
851       Opcode, VecTy, Factor, Indices, Alignment, AddressSpace, CostKind,
852       UseMaskForCond, UseMaskForGaps);
853   assert(Cost >= 0 && "TTI should not produce negative costs!");
854   return Cost;
855 }
856 
857 int
858 TargetTransformInfo::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
859                                            TTI::TargetCostKind CostKind) const {
860   int Cost = TTIImpl->getIntrinsicInstrCost(ICA, CostKind);
861   assert(Cost >= 0 && "TTI should not produce negative costs!");
862   return Cost;
863 }
864 
865 int TargetTransformInfo::getCallInstrCost(Function *F, Type *RetTy,
866                                           ArrayRef<Type *> Tys,
867                                           TTI::TargetCostKind CostKind) const {
868   int Cost = TTIImpl->getCallInstrCost(F, RetTy, Tys, CostKind);
869   assert(Cost >= 0 && "TTI should not produce negative costs!");
870   return Cost;
871 }
872 
873 unsigned TargetTransformInfo::getNumberOfParts(Type *Tp) const {
874   return TTIImpl->getNumberOfParts(Tp);
875 }
876 
877 int TargetTransformInfo::getAddressComputationCost(Type *Tp,
878                                                    ScalarEvolution *SE,
879                                                    const SCEV *Ptr) const {
880   int Cost = TTIImpl->getAddressComputationCost(Tp, SE, Ptr);
881   assert(Cost >= 0 && "TTI should not produce negative costs!");
882   return Cost;
883 }
884 
885 int TargetTransformInfo::getMemcpyCost(const Instruction *I) const {
886   int Cost = TTIImpl->getMemcpyCost(I);
887   assert(Cost >= 0 && "TTI should not produce negative costs!");
888   return Cost;
889 }
890 
891 int TargetTransformInfo::getArithmeticReductionCost(unsigned Opcode,
892                                                     VectorType *Ty,
893                                                     bool IsPairwiseForm,
894                                                     TTI::TargetCostKind CostKind) const {
895   int Cost = TTIImpl->getArithmeticReductionCost(Opcode, Ty, IsPairwiseForm,
896                                                  CostKind);
897   assert(Cost >= 0 && "TTI should not produce negative costs!");
898   return Cost;
899 }
900 
901 int TargetTransformInfo::getMinMaxReductionCost(
902     VectorType *Ty, VectorType *CondTy, bool IsPairwiseForm, bool IsUnsigned,
903     TTI::TargetCostKind CostKind) const {
904   int Cost =
905       TTIImpl->getMinMaxReductionCost(Ty, CondTy, IsPairwiseForm, IsUnsigned,
906                                       CostKind);
907   assert(Cost >= 0 && "TTI should not produce negative costs!");
908   return Cost;
909 }
910 
911 InstructionCost TargetTransformInfo::getExtendedAddReductionCost(
912     bool IsMLA, bool IsUnsigned, Type *ResTy, VectorType *Ty,
913     TTI::TargetCostKind CostKind) const {
914   return TTIImpl->getExtendedAddReductionCost(IsMLA, IsUnsigned, ResTy, Ty,
915                                               CostKind);
916 }
917 
918 unsigned
919 TargetTransformInfo::getCostOfKeepingLiveOverCall(ArrayRef<Type *> Tys) const {
920   return TTIImpl->getCostOfKeepingLiveOverCall(Tys);
921 }
922 
923 bool TargetTransformInfo::getTgtMemIntrinsic(IntrinsicInst *Inst,
924                                              MemIntrinsicInfo &Info) const {
925   return TTIImpl->getTgtMemIntrinsic(Inst, Info);
926 }
927 
928 unsigned TargetTransformInfo::getAtomicMemIntrinsicMaxElementSize() const {
929   return TTIImpl->getAtomicMemIntrinsicMaxElementSize();
930 }
931 
932 Value *TargetTransformInfo::getOrCreateResultFromMemIntrinsic(
933     IntrinsicInst *Inst, Type *ExpectedType) const {
934   return TTIImpl->getOrCreateResultFromMemIntrinsic(Inst, ExpectedType);
935 }
936 
937 Type *TargetTransformInfo::getMemcpyLoopLoweringType(
938     LLVMContext &Context, Value *Length, unsigned SrcAddrSpace,
939     unsigned DestAddrSpace, unsigned SrcAlign, unsigned DestAlign) const {
940   return TTIImpl->getMemcpyLoopLoweringType(Context, Length, SrcAddrSpace,
941                                             DestAddrSpace, SrcAlign, DestAlign);
942 }
943 
944 void TargetTransformInfo::getMemcpyLoopResidualLoweringType(
945     SmallVectorImpl<Type *> &OpsOut, LLVMContext &Context,
946     unsigned RemainingBytes, unsigned SrcAddrSpace, unsigned DestAddrSpace,
947     unsigned SrcAlign, unsigned DestAlign) const {
948   TTIImpl->getMemcpyLoopResidualLoweringType(OpsOut, Context, RemainingBytes,
949                                              SrcAddrSpace, DestAddrSpace,
950                                              SrcAlign, DestAlign);
951 }
952 
953 bool TargetTransformInfo::areInlineCompatible(const Function *Caller,
954                                               const Function *Callee) const {
955   return TTIImpl->areInlineCompatible(Caller, Callee);
956 }
957 
958 bool TargetTransformInfo::areFunctionArgsABICompatible(
959     const Function *Caller, const Function *Callee,
960     SmallPtrSetImpl<Argument *> &Args) const {
961   return TTIImpl->areFunctionArgsABICompatible(Caller, Callee, Args);
962 }
963 
964 bool TargetTransformInfo::isIndexedLoadLegal(MemIndexedMode Mode,
965                                              Type *Ty) const {
966   return TTIImpl->isIndexedLoadLegal(Mode, Ty);
967 }
968 
969 bool TargetTransformInfo::isIndexedStoreLegal(MemIndexedMode Mode,
970                                               Type *Ty) const {
971   return TTIImpl->isIndexedStoreLegal(Mode, Ty);
972 }
973 
974 unsigned TargetTransformInfo::getLoadStoreVecRegBitWidth(unsigned AS) const {
975   return TTIImpl->getLoadStoreVecRegBitWidth(AS);
976 }
977 
978 bool TargetTransformInfo::isLegalToVectorizeLoad(LoadInst *LI) const {
979   return TTIImpl->isLegalToVectorizeLoad(LI);
980 }
981 
982 bool TargetTransformInfo::isLegalToVectorizeStore(StoreInst *SI) const {
983   return TTIImpl->isLegalToVectorizeStore(SI);
984 }
985 
986 bool TargetTransformInfo::isLegalToVectorizeLoadChain(
987     unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
988   return TTIImpl->isLegalToVectorizeLoadChain(ChainSizeInBytes, Alignment,
989                                               AddrSpace);
990 }
991 
992 bool TargetTransformInfo::isLegalToVectorizeStoreChain(
993     unsigned ChainSizeInBytes, Align Alignment, unsigned AddrSpace) const {
994   return TTIImpl->isLegalToVectorizeStoreChain(ChainSizeInBytes, Alignment,
995                                                AddrSpace);
996 }
997 
998 bool TargetTransformInfo::isLegalToVectorizeReduction(
999     RecurrenceDescriptor RdxDesc, ElementCount VF) const {
1000   return TTIImpl->isLegalToVectorizeReduction(RdxDesc, VF);
1001 }
1002 
1003 unsigned TargetTransformInfo::getLoadVectorFactor(unsigned VF,
1004                                                   unsigned LoadSize,
1005                                                   unsigned ChainSizeInBytes,
1006                                                   VectorType *VecTy) const {
1007   return TTIImpl->getLoadVectorFactor(VF, LoadSize, ChainSizeInBytes, VecTy);
1008 }
1009 
1010 unsigned TargetTransformInfo::getStoreVectorFactor(unsigned VF,
1011                                                    unsigned StoreSize,
1012                                                    unsigned ChainSizeInBytes,
1013                                                    VectorType *VecTy) const {
1014   return TTIImpl->getStoreVectorFactor(VF, StoreSize, ChainSizeInBytes, VecTy);
1015 }
1016 
1017 bool TargetTransformInfo::preferInLoopReduction(unsigned Opcode, Type *Ty,
1018                                                 ReductionFlags Flags) const {
1019   return TTIImpl->preferInLoopReduction(Opcode, Ty, Flags);
1020 }
1021 
1022 bool TargetTransformInfo::preferPredicatedReductionSelect(
1023     unsigned Opcode, Type *Ty, ReductionFlags Flags) const {
1024   return TTIImpl->preferPredicatedReductionSelect(Opcode, Ty, Flags);
1025 }
1026 
1027 bool TargetTransformInfo::shouldExpandReduction(const IntrinsicInst *II) const {
1028   return TTIImpl->shouldExpandReduction(II);
1029 }
1030 
1031 unsigned TargetTransformInfo::getGISelRematGlobalCost() const {
1032   return TTIImpl->getGISelRematGlobalCost();
1033 }
1034 
1035 bool TargetTransformInfo::supportsScalableVectors() const {
1036   return TTIImpl->supportsScalableVectors();
1037 }
1038 
1039 int TargetTransformInfo::getInstructionLatency(const Instruction *I) const {
1040   return TTIImpl->getInstructionLatency(I);
1041 }
1042 
1043 static bool matchPairwiseShuffleMask(ShuffleVectorInst *SI, bool IsLeft,
1044                                      unsigned Level) {
1045   // We don't need a shuffle if we just want to have element 0 in position 0 of
1046   // the vector.
1047   if (!SI && Level == 0 && IsLeft)
1048     return true;
1049   else if (!SI)
1050     return false;
1051 
1052   SmallVector<int, 32> Mask(
1053       cast<FixedVectorType>(SI->getType())->getNumElements(), -1);
1054 
1055   // Build a mask of 0, 2, ... (left) or 1, 3, ... (right) depending on whether
1056   // we look at the left or right side.
1057   for (unsigned i = 0, e = (1 << Level), val = !IsLeft; i != e; ++i, val += 2)
1058     Mask[i] = val;
1059 
1060   ArrayRef<int> ActualMask = SI->getShuffleMask();
1061   return Mask == ActualMask;
1062 }
1063 
1064 static Optional<TTI::ReductionData> getReductionData(Instruction *I) {
1065   Value *L, *R;
1066   if (m_BinOp(m_Value(L), m_Value(R)).match(I))
1067     return TTI::ReductionData(TTI::RK_Arithmetic, I->getOpcode(), L, R);
1068   if (auto *SI = dyn_cast<SelectInst>(I)) {
1069     if (m_SMin(m_Value(L), m_Value(R)).match(SI) ||
1070         m_SMax(m_Value(L), m_Value(R)).match(SI) ||
1071         m_OrdFMin(m_Value(L), m_Value(R)).match(SI) ||
1072         m_OrdFMax(m_Value(L), m_Value(R)).match(SI) ||
1073         m_UnordFMin(m_Value(L), m_Value(R)).match(SI) ||
1074         m_UnordFMax(m_Value(L), m_Value(R)).match(SI)) {
1075       auto *CI = cast<CmpInst>(SI->getCondition());
1076       return TTI::ReductionData(TTI::RK_MinMax, CI->getOpcode(), L, R);
1077     }
1078     if (m_UMin(m_Value(L), m_Value(R)).match(SI) ||
1079         m_UMax(m_Value(L), m_Value(R)).match(SI)) {
1080       auto *CI = cast<CmpInst>(SI->getCondition());
1081       return TTI::ReductionData(TTI::RK_UnsignedMinMax, CI->getOpcode(), L, R);
1082     }
1083   }
1084   return llvm::None;
1085 }
1086 
1087 static TTI::ReductionKind matchPairwiseReductionAtLevel(Instruction *I,
1088                                                         unsigned Level,
1089                                                         unsigned NumLevels) {
1090   // Match one level of pairwise operations.
1091   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
1092   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
1093   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
1094   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
1095   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
1096   if (!I)
1097     return TTI::RK_None;
1098 
1099   assert(I->getType()->isVectorTy() && "Expecting a vector type");
1100 
1101   Optional<TTI::ReductionData> RD = getReductionData(I);
1102   if (!RD)
1103     return TTI::RK_None;
1104 
1105   ShuffleVectorInst *LS = dyn_cast<ShuffleVectorInst>(RD->LHS);
1106   if (!LS && Level)
1107     return TTI::RK_None;
1108   ShuffleVectorInst *RS = dyn_cast<ShuffleVectorInst>(RD->RHS);
1109   if (!RS && Level)
1110     return TTI::RK_None;
1111 
1112   // On level 0 we can omit one shufflevector instruction.
1113   if (!Level && !RS && !LS)
1114     return TTI::RK_None;
1115 
1116   // Shuffle inputs must match.
1117   Value *NextLevelOpL = LS ? LS->getOperand(0) : nullptr;
1118   Value *NextLevelOpR = RS ? RS->getOperand(0) : nullptr;
1119   Value *NextLevelOp = nullptr;
1120   if (NextLevelOpR && NextLevelOpL) {
1121     // If we have two shuffles their operands must match.
1122     if (NextLevelOpL != NextLevelOpR)
1123       return TTI::RK_None;
1124 
1125     NextLevelOp = NextLevelOpL;
1126   } else if (Level == 0 && (NextLevelOpR || NextLevelOpL)) {
1127     // On the first level we can omit the shufflevector <0, undef,...>. So the
1128     // input to the other shufflevector <1, undef> must match with one of the
1129     // inputs to the current binary operation.
1130     // Example:
1131     //  %NextLevelOpL = shufflevector %R, <1, undef ...>
1132     //  %BinOp        = fadd          %NextLevelOpL, %R
1133     if (NextLevelOpL && NextLevelOpL != RD->RHS)
1134       return TTI::RK_None;
1135     else if (NextLevelOpR && NextLevelOpR != RD->LHS)
1136       return TTI::RK_None;
1137 
1138     NextLevelOp = NextLevelOpL ? RD->RHS : RD->LHS;
1139   } else
1140     return TTI::RK_None;
1141 
1142   // Check that the next levels binary operation exists and matches with the
1143   // current one.
1144   if (Level + 1 != NumLevels) {
1145     if (!isa<Instruction>(NextLevelOp))
1146       return TTI::RK_None;
1147     Optional<TTI::ReductionData> NextLevelRD =
1148         getReductionData(cast<Instruction>(NextLevelOp));
1149     if (!NextLevelRD || !RD->hasSameData(*NextLevelRD))
1150       return TTI::RK_None;
1151   }
1152 
1153   // Shuffle mask for pairwise operation must match.
1154   if (matchPairwiseShuffleMask(LS, /*IsLeft=*/true, Level)) {
1155     if (!matchPairwiseShuffleMask(RS, /*IsLeft=*/false, Level))
1156       return TTI::RK_None;
1157   } else if (matchPairwiseShuffleMask(RS, /*IsLeft=*/true, Level)) {
1158     if (!matchPairwiseShuffleMask(LS, /*IsLeft=*/false, Level))
1159       return TTI::RK_None;
1160   } else {
1161     return TTI::RK_None;
1162   }
1163 
1164   if (++Level == NumLevels)
1165     return RD->Kind;
1166 
1167   // Match next level.
1168   return matchPairwiseReductionAtLevel(dyn_cast<Instruction>(NextLevelOp), Level,
1169                                        NumLevels);
1170 }
1171 
1172 TTI::ReductionKind TTI::matchPairwiseReduction(
1173   const ExtractElementInst *ReduxRoot, unsigned &Opcode, VectorType *&Ty) {
1174   if (!EnableReduxCost)
1175     return TTI::RK_None;
1176 
1177   // Need to extract the first element.
1178   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1179   unsigned Idx = ~0u;
1180   if (CI)
1181     Idx = CI->getZExtValue();
1182   if (Idx != 0)
1183     return TTI::RK_None;
1184 
1185   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1186   if (!RdxStart)
1187     return TTI::RK_None;
1188   Optional<TTI::ReductionData> RD = getReductionData(RdxStart);
1189   if (!RD)
1190     return TTI::RK_None;
1191 
1192   auto *VecTy = cast<FixedVectorType>(RdxStart->getType());
1193   unsigned NumVecElems = VecTy->getNumElements();
1194   if (!isPowerOf2_32(NumVecElems))
1195     return TTI::RK_None;
1196 
1197   // We look for a sequence of shuffle,shuffle,add triples like the following
1198   // that builds a pairwise reduction tree.
1199   //
1200   //  (X0, X1, X2, X3)
1201   //   (X0 + X1, X2 + X3, undef, undef)
1202   //    ((X0 + X1) + (X2 + X3), undef, undef, undef)
1203   //
1204   // %rdx.shuf.0.0 = shufflevector <4 x float> %rdx, <4 x float> undef,
1205   //       <4 x i32> <i32 0, i32 2 , i32 undef, i32 undef>
1206   // %rdx.shuf.0.1 = shufflevector <4 x float> %rdx, <4 x float> undef,
1207   //       <4 x i32> <i32 1, i32 3, i32 undef, i32 undef>
1208   // %bin.rdx.0 = fadd <4 x float> %rdx.shuf.0.0, %rdx.shuf.0.1
1209   // %rdx.shuf.1.0 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1210   //       <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
1211   // %rdx.shuf.1.1 = shufflevector <4 x float> %bin.rdx.0, <4 x float> undef,
1212   //       <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1213   // %bin.rdx8 = fadd <4 x float> %rdx.shuf.1.0, %rdx.shuf.1.1
1214   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1215   if (matchPairwiseReductionAtLevel(RdxStart, 0, Log2_32(NumVecElems)) ==
1216       TTI::RK_None)
1217     return TTI::RK_None;
1218 
1219   Opcode = RD->Opcode;
1220   Ty = VecTy;
1221 
1222   return RD->Kind;
1223 }
1224 
1225 static std::pair<Value *, ShuffleVectorInst *>
1226 getShuffleAndOtherOprd(Value *L, Value *R) {
1227   ShuffleVectorInst *S = nullptr;
1228 
1229   if ((S = dyn_cast<ShuffleVectorInst>(L)))
1230     return std::make_pair(R, S);
1231 
1232   S = dyn_cast<ShuffleVectorInst>(R);
1233   return std::make_pair(L, S);
1234 }
1235 
1236 TTI::ReductionKind TTI::matchVectorSplittingReduction(
1237   const ExtractElementInst *ReduxRoot, unsigned &Opcode, VectorType *&Ty) {
1238 
1239   if (!EnableReduxCost)
1240     return TTI::RK_None;
1241 
1242   // Need to extract the first element.
1243   ConstantInt *CI = dyn_cast<ConstantInt>(ReduxRoot->getOperand(1));
1244   unsigned Idx = ~0u;
1245   if (CI)
1246     Idx = CI->getZExtValue();
1247   if (Idx != 0)
1248     return TTI::RK_None;
1249 
1250   auto *RdxStart = dyn_cast<Instruction>(ReduxRoot->getOperand(0));
1251   if (!RdxStart)
1252     return TTI::RK_None;
1253   Optional<TTI::ReductionData> RD = getReductionData(RdxStart);
1254   if (!RD)
1255     return TTI::RK_None;
1256 
1257   auto *VecTy = cast<FixedVectorType>(ReduxRoot->getOperand(0)->getType());
1258   unsigned NumVecElems = VecTy->getNumElements();
1259   if (!isPowerOf2_32(NumVecElems))
1260     return TTI::RK_None;
1261 
1262   // We look for a sequence of shuffles and adds like the following matching one
1263   // fadd, shuffle vector pair at a time.
1264   //
1265   // %rdx.shuf = shufflevector <4 x float> %rdx, <4 x float> undef,
1266   //                           <4 x i32> <i32 2, i32 3, i32 undef, i32 undef>
1267   // %bin.rdx = fadd <4 x float> %rdx, %rdx.shuf
1268   // %rdx.shuf7 = shufflevector <4 x float> %bin.rdx, <4 x float> undef,
1269   //                          <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>
1270   // %bin.rdx8 = fadd <4 x float> %bin.rdx, %rdx.shuf7
1271   // %r = extractelement <4 x float> %bin.rdx8, i32 0
1272 
1273   unsigned MaskStart = 1;
1274   Instruction *RdxOp = RdxStart;
1275   SmallVector<int, 32> ShuffleMask(NumVecElems, 0);
1276   unsigned NumVecElemsRemain = NumVecElems;
1277   while (NumVecElemsRemain - 1) {
1278     // Check for the right reduction operation.
1279     if (!RdxOp)
1280       return TTI::RK_None;
1281     Optional<TTI::ReductionData> RDLevel = getReductionData(RdxOp);
1282     if (!RDLevel || !RDLevel->hasSameData(*RD))
1283       return TTI::RK_None;
1284 
1285     Value *NextRdxOp;
1286     ShuffleVectorInst *Shuffle;
1287     std::tie(NextRdxOp, Shuffle) =
1288         getShuffleAndOtherOprd(RDLevel->LHS, RDLevel->RHS);
1289 
1290     // Check the current reduction operation and the shuffle use the same value.
1291     if (Shuffle == nullptr)
1292       return TTI::RK_None;
1293     if (Shuffle->getOperand(0) != NextRdxOp)
1294       return TTI::RK_None;
1295 
1296     // Check that shuffle masks matches.
1297     for (unsigned j = 0; j != MaskStart; ++j)
1298       ShuffleMask[j] = MaskStart + j;
1299     // Fill the rest of the mask with -1 for undef.
1300     std::fill(&ShuffleMask[MaskStart], ShuffleMask.end(), -1);
1301 
1302     ArrayRef<int> Mask = Shuffle->getShuffleMask();
1303     if (ShuffleMask != Mask)
1304       return TTI::RK_None;
1305 
1306     RdxOp = dyn_cast<Instruction>(NextRdxOp);
1307     NumVecElemsRemain /= 2;
1308     MaskStart *= 2;
1309   }
1310 
1311   Opcode = RD->Opcode;
1312   Ty = VecTy;
1313   return RD->Kind;
1314 }
1315 
1316 TTI::ReductionKind
1317 TTI::matchVectorReduction(const ExtractElementInst *Root, unsigned &Opcode,
1318                           VectorType *&Ty, bool &IsPairwise) {
1319   TTI::ReductionKind RdxKind = matchVectorSplittingReduction(Root, Opcode, Ty);
1320   if (RdxKind != TTI::ReductionKind::RK_None) {
1321     IsPairwise = false;
1322     return RdxKind;
1323   }
1324   IsPairwise = true;
1325   return matchPairwiseReduction(Root, Opcode, Ty);
1326 }
1327 
1328 int TargetTransformInfo::getInstructionThroughput(const Instruction *I) const {
1329   TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput;
1330 
1331   switch (I->getOpcode()) {
1332   case Instruction::GetElementPtr:
1333   case Instruction::Ret:
1334   case Instruction::PHI:
1335   case Instruction::Br:
1336   case Instruction::Add:
1337   case Instruction::FAdd:
1338   case Instruction::Sub:
1339   case Instruction::FSub:
1340   case Instruction::Mul:
1341   case Instruction::FMul:
1342   case Instruction::UDiv:
1343   case Instruction::SDiv:
1344   case Instruction::FDiv:
1345   case Instruction::URem:
1346   case Instruction::SRem:
1347   case Instruction::FRem:
1348   case Instruction::Shl:
1349   case Instruction::LShr:
1350   case Instruction::AShr:
1351   case Instruction::And:
1352   case Instruction::Or:
1353   case Instruction::Xor:
1354   case Instruction::FNeg:
1355   case Instruction::Select:
1356   case Instruction::ICmp:
1357   case Instruction::FCmp:
1358   case Instruction::Store:
1359   case Instruction::Load:
1360   case Instruction::ZExt:
1361   case Instruction::SExt:
1362   case Instruction::FPToUI:
1363   case Instruction::FPToSI:
1364   case Instruction::FPExt:
1365   case Instruction::PtrToInt:
1366   case Instruction::IntToPtr:
1367   case Instruction::SIToFP:
1368   case Instruction::UIToFP:
1369   case Instruction::Trunc:
1370   case Instruction::FPTrunc:
1371   case Instruction::BitCast:
1372   case Instruction::AddrSpaceCast:
1373   case Instruction::ExtractElement:
1374   case Instruction::InsertElement:
1375   case Instruction::ExtractValue:
1376   case Instruction::ShuffleVector:
1377   case Instruction::Call:
1378     return getUserCost(I, CostKind);
1379   default:
1380     // We don't have any information on this instruction.
1381     return -1;
1382   }
1383 }
1384 
1385 TargetTransformInfo::Concept::~Concept() {}
1386 
1387 TargetIRAnalysis::TargetIRAnalysis() : TTICallback(&getDefaultTTI) {}
1388 
1389 TargetIRAnalysis::TargetIRAnalysis(
1390     std::function<Result(const Function &)> TTICallback)
1391     : TTICallback(std::move(TTICallback)) {}
1392 
1393 TargetIRAnalysis::Result TargetIRAnalysis::run(const Function &F,
1394                                                FunctionAnalysisManager &) {
1395   return TTICallback(F);
1396 }
1397 
1398 AnalysisKey TargetIRAnalysis::Key;
1399 
1400 TargetIRAnalysis::Result TargetIRAnalysis::getDefaultTTI(const Function &F) {
1401   return Result(F.getParent()->getDataLayout());
1402 }
1403 
1404 // Register the basic pass.
1405 INITIALIZE_PASS(TargetTransformInfoWrapperPass, "tti",
1406                 "Target Transform Information", false, true)
1407 char TargetTransformInfoWrapperPass::ID = 0;
1408 
1409 void TargetTransformInfoWrapperPass::anchor() {}
1410 
1411 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass()
1412     : ImmutablePass(ID) {
1413   initializeTargetTransformInfoWrapperPassPass(
1414       *PassRegistry::getPassRegistry());
1415 }
1416 
1417 TargetTransformInfoWrapperPass::TargetTransformInfoWrapperPass(
1418     TargetIRAnalysis TIRA)
1419     : ImmutablePass(ID), TIRA(std::move(TIRA)) {
1420   initializeTargetTransformInfoWrapperPassPass(
1421       *PassRegistry::getPassRegistry());
1422 }
1423 
1424 TargetTransformInfo &TargetTransformInfoWrapperPass::getTTI(const Function &F) {
1425   FunctionAnalysisManager DummyFAM;
1426   TTI = TIRA.run(F, DummyFAM);
1427   return *TTI;
1428 }
1429 
1430 ImmutablePass *
1431 llvm::createTargetTransformInfoWrapperPass(TargetIRAnalysis TIRA) {
1432   return new TargetTransformInfoWrapperPass(std::move(TIRA));
1433 }
1434